Vorrichtung und Verfahren zum Schutz einer integrierten Schaltung

Monolithisch integrierte Struktur einer elektronischen Vorrichtung mit einer bestimmten unidirektionalen Konduktionsschwellenspannung

Halbleiteranordnung mit einem Schutzelement und Verfahren zu ihrer Herstellung

ELEKTROSTATISCHE ENTLADUNGSSCHUTZSCHALTUNGEN UNTER VERWENDUNG POLARISIERTER UND ABGESCHLOSSENER PNP TRANSISTORKETTEN

ELEKTROSTATISCHE SCHUTZVORRICHTUNG

Aspekte der Erfindung stellen eine elektrostatische Schutzvorrichtung zum Schutz eines Eingangsanschlusses einer elektronischen Schaltung bereit. Die elektrostatische Schutzvorrichtung umfasst eine gestapelte Spulenbaugruppe mit vier Anschlüssen. Die elektrostatische Schutzvorrichtung umfasst ferner eine Human-Body-Model-ESD-Schutzschaltung, eine Charge-Device-Model-ESD-Schutzschaltung und eine Impedanzanpassungsschaltung. Die ESD-Schutzschaltung des Human-Body-Model-ESD-Schutzschaltung, die ESD-Schutzschaltung des Charge-Device-Model-ESD-Schutzschaltung und die Impedanzanpassungsschaltung sind mit separaten Anschlüssen verbunden, die aus den vier Anschlüssen ausgewählt werden.

Vertikale MOSFET-Vorrichtung mit Schutz.

Halbleitervorrichtung mit elektrostatischer Entladungsschutzstruktur

Eine Halbleiterkörper (10) umfasst einen Halbleiterkörper (100), der eine erste Oberfläche (101) und eine zweite Oberfläche (102) entgegengesetzt zu der ersten Oberfläche (101) hat. Die Halbleitervorrichtung (10) umfasst weiterhin eine erste Isolationsschicht (200) auf der ersten Oberfläche (101) des Halbleiterkörpers (100) und eine elektrostatische Entladungsschutzstruktur (310) auf der ersten Isolationsschicht (200). Die elektrostatische Entladungsschutzstruktur (310) umfasst einen ersten Anschluss (312) und einen zweiten Anschluss (314). Die Halbleitervorrichtung (10) umfasst weiterhin eine Wärmeabfuhrstruktur (700), die ein erstes Ende (701) in direktem Kontakt mit der elektrostatischen Entladungsschutzstruktur (310) und ein zweites Ende (702) in direktem Kontakt mit einem elektrisch isolierenden Bereich hat. Die elektrostatische Entladungsschutzstruktur (310) umfasst erste und zweite Ausdiffusionsbereiche (320, 322) des gleichen Leitfähigkeitstyps, die zu der Wärmeabfuhrstruktur (700 ...

Verfahren zum Schutz vor elektrostatischer Entladung, Schaltung zum Schutz vor elektrostatischer Entladung und integrierte Schaltung

Gemäß einer Ausführungsform beinhaltet ein Verfahren zum Schutz vor elektrostatischer Entladung (ESD): eine Spannung zwischen mehreren Schaltungsknoten unter Verwendung einer Spannungsteilerschaltung aufzuteilen, um eine aufgeteilte Spannung zu bilden; eine Temperaturabhängigkeit der aufgeteilten Spannung zu kompensieren, um eine temperaturkompensierte aufgeteilte Spannung zu bilden; die Spannung zwischen den mehreren Schaltungsknoten unter Verwendung einer Transientendetektionsschaltung zu überwachen, um ein Transientendetektionssignal zu bilden; und eine Klemmschaltung, die zwischen den mehreren Schaltungsknoten verschaltet ist, auf Basis der temperaturkompensierten aufgeteilten Spannung und auf Basis des Transientendetektionssignals zu aktivieren.

Integrierte Halbleiterschaltung

Integrierte Halbleiterschaltung (B2), die auf einem gemeinsamen Halbleiterkörper (U2 bis U4) einen IGBT (Z1), eine mit dessen isolierter Gateelektrode verbundene Steuerschaltung (B1) mit einem n-Kanal-MOSFET (M1) und eine mit der Steuerschaltung (B1) und dem Emitteranschluss des IGBT (Z1) verbundene Schutzschaltung mit einer Zener-Diode (D1) aufweist, dadurch gekennzeichnet, – dass die Steuerschaltung (B1) zusätzlich einen p-Kanal-MOSFET (M2) und die Schutzschaltung zusätzlich zwei Schottky-Dioden (D2 und D3) enthält, – dass der Eingang (P1) der integrierten Halbleiterschaltung (B2) mit der Kathode der Zener-Diode (D1) und mit der Anode der einen Schottky-Diode (D2) verbunden ist, wobei die Kathode dieser Schottky-Diode (D2) an den Eingang der Steuerschaltung (B1) und an die Kathode der anderen Schottky-Diode (D3) angeschlossen ist und die Anode der Zener-Diode (D1) und die Anode der anderen Schottky-Diode (D3) mit dem Emitter des IGBT (Z1) verbunden sind, – wobei der Halbleiterkörper ( ...

Verfahren zum Herstellen einer Schutzstruktur

Verfahren zur Herstellung einer Schutzstruktur (100, 200), wobei das Verfahren folgende Merkmale aufweist: – Bereitstellen eines Halbleitersubstrats (110) mit einer Dotierung von einem ersten Leitfähigkeitstyp, – Aufbringen einer Halbleiterschicht (120) mit einer Dotierung von einem zweiten Leitfähigkeitstyp an einer Oberfläche des Halbleitersubstrats (110), – Ausbilden einer vergrabenen Schicht (140) mit einer Dotierung von einem zweiten Leitfähigkeitstyp in einem ersten Bereich (150) der Halbleiterschicht (120), wobei die vergrabene Schicht (140) am Übergang (170) von der Halbleiterschicht (120) zum Halbleitersubstrat (110) erzeugt wird, – Ausbilden eines ersten Dotierstoffgebiets (180) mit einer Dotierung von einem ersten Leitfähigkeitstyp in dem ersten Bereich (150) der Halbleiterschicht (120) über der vergrabenen Schicht (140), – Ausbilden eines zweiten Dotierstoffgebiets (190) mit einer Dotierung von einem zweiten Leitfähigkeitstyp in einem zweiten Bereich (160) der Halbleiterschicht ...

MITINTEGRIERTER HALBLEITERUEBERGANG NIEDRIGER DURCHBRUCHSSPANNUNG ALS SCHUTZELEMENT

MOS-Halbleiteranordnung

MOS-Halbleiteranordnung mit einem Halbleitersubstrat, einem Halbleiterelement (4) in MOS-Ausführung mit einer ersten Elektrode, einer zweiten Elektrode und einer Gateelektrode als Steuereingang eines Steuerabschnitts mit MOS-Aufbau, einem mit der ersten Elektrode verbundenen ersten Ausgangsanschluß (S) und einem mit der zweiten Elektrode verbundenen zweiten Ausgangsanschluß (D), einem Steuereingangsanschluß (G), einer internen Steuerschaltung (9), die zwischen den Steuereingangsanschluß (G) und die Gateelektrode (g) des Halbleiterelements (4) geschaltet ist, und einer Schutzeinrichtung (Z1p, Z21, Z3pr), die zwischen den Steuereingangsanschluß (G) und den ersten Ausgangsanschluß (S) geschaltet ist und zum Schutz gegen Überspannungen dient, sowie einen ersten Zweig, der eine erste Zenerdiode (Z1p) enthält, die eine auf einem isolierenden Film auf dem Halbleitersubstrat aufgebrachte Polysiliciumschicht aufweist, und einen zweiten Zweig umfaßt, der eine zweite Zenerdiode (Z21), die in einer ...

Gruppe-III-Nitrid-basierte ESD-Schutzvorrichtung

Vorrichtung zum Schutz vor elektrostatischen Entladungen, umfassend:eine erste Gruppe-III-Nitrid-p-i-n-Diode; undeine zweite Gruppe-III-Nitrid-p-i-n-Diode, die mit der ersten Gruppe-III-Nitrid-p-i-n-Diode in einer antiparallelen Anordnung verbunden ist, wobei die Anordnung eingerichtet ist,ein Spannungsklemmen bei 5V oder weniger unter Vorspannung in Durchlassrichtung entweder der ersten oder der zweiten Gruppe-III-Nitrid-p-i-n-Diode für transienten Strom sowohl in der Durchlass- als auch in der Sperrrichtung bereitzustellen,wobei die erste Gruppe-III-Nitrid-p-i-n-Diode eine erste intrinsische Gruppe-III-Nitridzone umfasst, die zwischen einer ersten Gruppe-III-Nitridzone vom n-Typ und einer ersten Gruppe-III-Nitridzone vom p-Typ angeordnet ist;die zweite Gruppe-III-Nitrid-p-i-n-Diode eine zweite intrinsische Gruppe-III-Nitridzone umfasst, die zwischen einer zweiten Gruppe-III-Nitridzone vom n-Typ und einer zweiten Gruppe-III-Nitridzone vom p-Typ angeordnet ist;die erste Gruppe-III-Nitridzone ...

ZENERDIODEN UND ZUGEHÖRIGE HERSTELLUNGSVERFAHREN

In einem allgemeinen Gesichtspunkt kann eine Halbleitervorrichtung ein hochdotiertes Substrat eines ersten Leitfähigkeitstyps, eine niedrigdotierte Epitaxialschicht eines zweiten Leitfähigkeitstyps, die auf dem hochdotierten Substrat angeordnet ist, und eine hochdotierte Epitaxialschicht des zweiten Leitfähigkeitstyps einschließen, die auf der niedrigdotierten Epitaxialschicht angeordnet ist. Die hochdotierte Epitaxialschicht kann eine Dotierungskonzentration aufweisen, die größer ist als eine Dotierungskonzentration des niedrigdotierten Epitaxialschicht. Mindestens ein Abschnitt des hochdotierten Substrats kann in einer ersten Anschlussklemme einer Zenerdiode eingeschlossen sein, und mindestens ein Abschnitt der niedrigdotierten Epitaxialschicht und mindestens ein Abschnitt der hochdotierten Epitaxialschicht können in einer zweiten Anschlussklemme der Zenerdiode eingeschlossen sein. Die Halbleitervorrichtung kann ferner einen Abschlussgraben einschließen, der sich durch die hochdotierte ...

Halbleiter-Anordnung mit ESD-Schutzschaltung

Eine Halbleiter-Anordnung (10) mit ESD-Schutzschaltung ist offenbart. Die Halbleiter-Anordnung (10) umfasst einen ersten Halbleiterchip (20a) mit einer ersten integrierten Schaltung (25a) und einen zweiten Halbleiterchip (20b) mit einer zweiten integrierten Schaltung (25b). Die Halbleiter-Anordnung hat eine ESD-Schutzschaltung (30). Der erste Halbleiterchip (20a) ist ansonsten von dem zweiten Halbleiterchip (20b) isoliert und die erste integrierte Schaltung (25a) ist mit der zweiten integrierten Schaltung (25b) nur über die ESD-Schutzschaltung (30) verbunden/geschaltet.

SCR BAUTEIL MIT NIEDRIGER SCHWELL- UND HALTESPANNUNG FÜR ESD SCHUTZ

ESD-Schutzschaltung mit skalierbarer Stromfestigkeit und Spannungsfestigkeit

Vorgestellt wird eine ESD-Schutzschaltung (10) aus Halbleiterstrukturen als Grundelemente (16; 18), deren elektrische Leitfähigkeit sich bei einer anliegenden Spannung, die einen Schwellenwert überschreitet, durchbruchartig oder lawinenartig ändert. Die ESD-Schutzschaltung (10) zeichnet sich dadurch aus, dass die ESD-Schutzschaltung (10) eine Matrix von Grundelementen aufweist, bei der eine gewünschte Stromfestigkeit durch Vorgabe einer Zahl von Grundelementen jeder Zeile und eine gewünschte Spannungsfestigkeit durch Vorgabe einer Zahl von Zeilen einstellbar ist.

Gated semiconductor device

Semiconductor device

Low leakage electrostatic discharge protection system

An integrated circuit 16 is protected against ESD events by means of an arrangement having a high voltage diode 32 connected between an input pad 10 and a positive supply 12, a high voltage diode 34 connected between the input pad 10 and a negative supply 14 and an element 36 connected between the positive and negative supplies 12, 14 and capable of conducting in both directions during an ESD event. The element 36 may be a diode 36 and has a reverse breakdown voltage exceeding the difference between the supply voltages 12, 14. The diode 36 may be a fast acting lateral npn diode with snap back action under reverse bias. The diodes 32, 34 have a much greater reverse breakdown voltage than diode 36 and may be Schottky diodes, avalanche diodes or MOS-transistors. Field plating (Fig.4) may be used to increase the reverse breakdown voltage of diodes 32, 34. Alternatively, special diffusion (ie. p-base) may be used. Deep junction diodes (Fig.5) may also be used. Additional high voltage diodes ...

Diode assembly and method of manufacture thereof

A diode assembly comprises first and second diodes 15, 16, each having a different breakdown voltage, the first and second diodes each comprising a semiconductor substrate 12, an electrically conducting channel layer 13 on the semiconductor substrate, an upper semiconductor layer 14 on the channel layer, the upper semiconductor layer comprising a recess 17, first and second ohmic contacts 22, 23 on the upper semiconductor layer on opposite sides of the recess, the ohmic contacts being connected together to form a first diode contact, and a gate electrode 21 within the recess, the gate electrode forming a second diode contact, wherein the area of the recess of the first diode covered by the first gate electrode is different to the area of the recess of the second diode covered by the second gate electrode. The diode assembly may be used to provide electrostatic discharge protection for a gallium arsenide based circuit.

A diode assembly

A diode assembly

Transferring logging data from an offset well location to a target well location

Systems and methods for transferring logging data from an offset well location to a target well location by adjusting the logging data to account for the difference in correlated depths between the target well and the offset well where logging data is acquired.

Transferring logging data from an offset well location to a target well location

Transferring logging data from an offset well location to a target well location

A structure and method for guarding a low voltage region of a semiconductor device from a high voltage region of the semiconductor device

PROTECTION DIODE TO THE PROTECTION OF SEMICONDUCTOR CIRCUITS AGAINST ELECTROSTATIC UNLOADINGS

MANUFACTURING PROCESS FUR ACTIVE MATRIX SUBSTRATE

INTEGRATED CIRCUIT WITH ÜBERSPANNUNGSCHUTZ AND THEIR MANUFACTURING PROCESSES

DATA MEDIUM, WHICH CONTAINS AN INTEGRATED CIRCUIT WITH A ESD PROTECTIVE CIRCUIT

FIELD-EFFECT TRANSISTOR WITH INSULATING GATE ELECTRODE

Field-effect transistor with insulating gate electrode

DATA CARRIER COMPRISING AN INTEGRATED CIRCUIT WITH AN ESD PROTECTION CIRCUIT

A voltage-tolerant electrostatic discharge protection device

VOLTAGE LIMITING PROTECTION FOR HIGH FREQUENCY POWER DEVICE

An RF power device comprising a power transistor fabricated in a first semiconductor chip and a MOSCAP type structure fabricated in a second semiconductor chip. A voltage limiting device is provided for protecting the power transistor from input voltage spikes and is preferably fabricated in the semiconductor chip along with the MOSCAP. Alternatively, the voltage limiting device can be a discrete element fabricated on or adjacent to the capacitor semiconductor chip. By removing the voltage limiting device from the power transistor chip, fabrication and testing of the voltage limiting device is enhanced, and semiconductor area for the power device is increased and aids in flexibility of device fabrication.

INPUT TRANSIENT PROTECTION FOR INSULATED GATE FIELD EFFECT TRANSISTORS

INPUT TRANSIENT PROTECTION FOR COMPLEMENTARY INSULATED GATE FIELD EFFECT TRANSISTOR INTEGRATED CIRCUIT

Feldeffekttransistor mit mindestens einer isolierten Torelektrode

Feldeffekttransistor mit isolierter Torelektrode

Feldeffekttransistor mit einer Schutzdiode

Feldeffekttransistor mit mindestens zwei Torelektroden

Fin type diode and manufacturing method thereof

Surge protection circuit

The signal receiving circuit and a transmitting-receiving circuit

Semiconductor device including a diode and method of manufacturing a semiconductor device

A semiconductor device includes a transistor cell array in the semiconductor body of a first conductivity type. The semiconductor device further includes a first trench in the transistor cell array between transistor cells. The first trench extends into the semiconductor body from a first side and includes a pn junction diode electrically coupled to the semiconductor body at a sidewall.

Protecting an integrated circuit against electrostatic overloads.

DEVICE SAFETY AGAINST ELECTROSTATIC DISCHARGES POURCOMPOSANTS MICRO-ELECTRONICS ON SUBSTRATE OF THE TYPE ONESELF

Plasma generating device for internal combustion engine, has periodic pulse voltage generator with switching transistor, and zener diode, connected between drain and source of transistor, limiting voltage difference between drain and source

Le dispositif de génération de plasma, comprend une bougie de génération de plasma contenant un résonateur inductif capacitif (RS2) apte à produire une haute tension, des moyens (OSC) de génération d'un train d'impulsions de commande haute fréquence, et un générateur de tension (GENI) comprenant un transistor de commutation (M1) dont l'électrode de commande est reliée à la sortie des moyens de génération et une sortie (D) apte à délivrer un train d'impulsions de tension au résonateur en réponse au train d'impulsions de commande reçues sur l'électrode de commande du transistor de commutation. Il comprend en outre des moyens (D1) connectés entre les deux électrodes de conduction du transistor de commutation et aptes à limiter la différence de tension entres ces deux autres électrodes.

DEVICE FOR PROTECTING AGAINST ELECTROSTATIC DISCHARGES HAS ADJUSTABLE TRIP THRESHOLD

PROCESS OF TEST Of a STRUCTURE PROTEGEE AGAINST OVERPRESSURES AND CORRESPONDING STRUCTURE

Le dispositif électronique comprend une structure intégrée comportant un composant électronique (CCI) et des moyens de protection (CPRA1, CPRB1) de ce composant contre des surtensions, et des moyens de commande (MCDM) configurés pour inhiber une partie (CPRB1) des moyens de protection en présence d'une tension de test aux bornes du composant.

ON THE SOI INTEGRATED CIRCUIT COMPRISING A DIODE SIDE PROTECTION AGAINST ELECTROSTATIC DISCHARGES

STRUCTURE OF PROTECTION AGAINST OVERPRESSURES FOR DIFFERENTIAL CONNECTION

L'invention concerne une structure de protection (40) d'un circuit intégré connecté à des premier (11) et second (12) rails d'une liaison différentielle contre des surtensions, comprenant : au moins une première diode (41) et au moins une deuxième diode (42) en antiparallèle, entre le premier rail et un noeud commun (N) ; au moins une troisième diode (43) et au moins une quatrième diode (44) en antiparallèle, entre le second rail et le noeud commun ; et un condensateur (46) entre le noeud commun et un rail de potentiel bas de référence.

AN OVERVOLTAGE PROTECTION DEVICE

L'invention concerne un dispositif (20) de protection contre les surcharges électrostatiques comprenant successivement : un substrat (22) semiconducteur très fortement dopé d'un premier type de conductivité ; une première couche semiconductrice enterrée (24) fortement dopée d'un deuxième type de conductivité ; une première couche (28) semiconductrice faiblement dopée du deuxième type de conductivité ; et une deuxième couche (30) fortement dopée du premier type de conductivité, ce dispositif (20) comprenant en outre, entre la première couche enterrée (24) et la première couche (28), une troisième couche (26) dopée du premier type de conductivité, ayant une épaisseur et une concentration en atomes dopants adaptées à former à la jonction de la première couche (28) et de la troisième couche (26) une diode (12) fonctionnant en inverse en perçage.

PROTECTIVE SYSTEM WITH RESPECT TO AN ELECTROSTATIC DISCHARGE HAS WEAK ESCAPE

L'invention concerne un circuit de protection vis-à-vis de décharges électrostatiques qui convient pour une utilisation avec un circuit intégré, comprenant : une première diode à jonction PIN haute tension (32) connectée entre une alimentation positive (12) dudit circuit et une première entrée (10); une seconde diode à jonction PIN haute tension (34) connectée entre une alimentation négative (14) dudit circuit et ladite entrée (10), ladite première diode et ladite seconde diode étant chacune constituées par une diode à placage de champ pour augmenter une tension de claquage inverse desdites diodes (32, 34); et une troisième diode (36) connectée entre ladite alimentation positive (12) et ladite alimentation négative (14), ladite troisième diode pouvant conduire dans les deux sens à une tension faible, ladite troisième diode présentant une tension de claquage inverse qui excède la tension de ladite alimentation. Ceci empêche qu'une fuite par diode d'entrée n'augmente du fait d'une contrainte ...

SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE

A SEMICONDUCTOR DEVICE

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE CAPABLE OF REDUCING THE AREA OF AN INTERFACE PART AND MAINTAINING A TRANSMITTABLE FREQUENCY AND A WAVEFORM

PURPOSE: A semiconductor integrated circuit device is provided to maintain a signal transmission speed or the quality of a waveform. CONSTITUTION: A semiconductor integrated circuit device includes a protection target circuit and a power outage protection device. The protection target circuit has a differential input pair(11,12) and is an object to be protected from power outage. The power outage protection device protects the protection target circuit from power outage noise. The protection device is formed to be connected to the center point of an end terminal resistor which connects one side of the differential input pair to the other side. COPYRIGHT KIPO 2011 ...

정전기 방전 다이오드

... 방법은 기판에 형성되는 제 1 비아의 일 부분을 노출시키기 위해 기판의 이면을 씨닝하는 단계를 포함한다. 방법은 또한 기판의 이면에 제 1 다이오드를 형성하는 단계를 포함한다. 제 1 다이오드는 제 1 비아에 결합된다.

Single event transient immune antenna diode circuit

An antenna diode circuit is described. The antenna diode circuit includes two diodes connected in series between a signal line and ground. Alternatively, the antenna diode circuit is connected in series between a signal line and a power supply. In addition to protecting the signal line from charge accumulation during wafer fabrication, the antenna diode circuit prevents a single event transient glitch caused by a particle strike to either one of the diodes in the antenna diode circuit.

Random number generator with antifuse differential cell and associated sensing method

A random number generator includes a cell array including a plurality of antifuse differential cells; and a sensing circuit having an input terminal and an inverted input terminal. When a first antifuse differential cell of the cell array is selected as a selected cell, a bit line of the selected cell is connected with the input terminal of the sensing circuit, and an inverted bit line of the selected cell is connected with the inverted input terminal of the sensing circuit. During a read action, the sensing circuit is capable of determining a storing state of the selected cell and one bit of a random code according a first charging current flowing through the bit line and a second charging current flowing through the inverted bit line.

Method and device for electrical overstress and electrostatic discharge protection

A semiconductor device is protected from electrical overstress (EOS) and electro-static discharge (ESD) events by a series protection circuit electrically coupled in series along the transmission line between a signal source and a load. The series protection circuit includes a first field-effect transistor (FET) electrically coupled in series between the signal source and load. A parallel protection circuit is electrically coupled between the transmission line and a ground node. The parallel protection circuit can include a transient-voltage-suppression (TVS) diode.

Antenna protection cell

A cell library stores a plurality of standard layout cells. A functional integrated circuit design is received, and a plurality of the standard layout cells are selected from the cell library based on the received functional integrated circuit design. A first standard layout cell from the cell library that is selected based on the received functional integrated circuit design includes a buffer circuit having an input terminal, an output terminal, a first voltage terminal and a second voltage terminal, and an antenna protection circuit connected between the input terminal and the second voltage terminal.

Low leakage electrostatic discharge protectioin system

ESD PROTECTION SYSTEM FOR HIGH FREQUENCY APPLICATIONS

TRANSIENT-VOLTAGE-SUPPRESSION (TVS) DIODE DEVICE AND METHOD OF FABRICATING THE SAME

Esd device layout for effectively reducing internal circuit area and avoiding esd and breakdown damage and effectively protecting high voltage ic

Themally stable semiconductor power device

Active matrix substrate and method of manufacturing the same and active matrix liquid crystal display

A method of manufacturing an active matrix substrate (1) comprising a row and column array of active elements (10) wherein each element (11) is associated with a TFT (13) having a gate electrode (306) connected to a corresponding row conductor (15) and source (320) and drain (321) electrodes connected to corresponding column conductors (14), and ESD protective circuitry (20) connected to at least one of the row conductors for protecting the TFTs against electrostatic discharge (ESD). The method comprising the steps of forming semiconductor regions of the TFTs (302) and the ESD protective circuitry (303); depositing gate electrodes (306) of the TFTs and corresponding row conductors (15); and depositing source (320) and drain (321) electrodes of the TFTs and corresponding column conductors (14), wherein the ESD protective circuitry (20) is operative to control ESD prior to deposition of the column conductors (14).

SEMICONDUCTOR COMPONENT

The invention relates to a semiconductor component (10) having an integrated circuit (12) which has at least two layers (14, 16, 18) which are arranged above one another, are spaced apart from one another by at least one intermediate layer (24, 26) and are electrically conductive in regions, wherein conductor track sections (28) for providing a first voltage potential are provided in a first layer (14) and conductor track sections (30) for providing a second voltage potential are provided in a second layer (16), and having at least one protective diode (36) which is electrically connected to a conductor track section (28) of the first layer (14) and to a conductor track section (30) of the second layer (16), is formed in a substrate layer (38), which is arranged under the first and second layers (14, 16), in order to dissipate voltage spikes and is at least partially arranged directly under a conductor track section. The invention provides for the electrical connection between the protective ...

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME

A capacitance component region is formed below a temperature detection diode (1) or below protection diodes (21, 22). Further, capacitance component regions are formed below an anode metal wiring (6) that connects the temperature detection diode (1) and an anode electrode pad (3) with each other, and below a cathode metal wiring (7) that connects the temperature detection diode (1) and a cathode electrode pad (4) with each other. The capacitance component region is formed with an insulating film interposed between polycrystalline silicon layers. More specifically, a first insulating film, a polycrystalline silicon conductive layer, and a second insulating film are laminated in this order on a first principal surface of the semiconductor substrate, and the temperature detection diode (1), the protection diodes (21, 22), the anode metal wiring (6) or the cathode metal wiring (7), which are made of polycrystalline silicon, are arranged on top of the second insulating film. This makes it possible ...

SEMICONDUCTOR DEVICE

An electrostatic discharge (ESD) protection device (1) is provided with a silicon substrate (10) and a redistribution layer (20). Titanium/copper/titanium electrodes (23A, 23B) of the redistribution layer (20) are electrically connected, via contact holes (22A, 22B), to an ESD protection circuit having aluminum electrode films (111 to 113, 121, 131) formed on a surface of the silicon substrate (10). The aluminum electrode film (121) is electrically connected to the titanium/copper/titanium electrode (23A), and the aluminum electrode film (131) is electrically connected to the titanium/copper/titanium electrode (23B). A diode forming area (141) is formed between the aluminum electrode films (111 and 121), and a diode forming area (144) is formed between the aluminum electrode films (112 and 131). The titanium/copper/titanium electrode (24A) does not overlap with the diode forming area (144), and the titanium/copper/titanium electrode (24B) overlaps with the diode forming area (141).A semiconductor ...

SEMICONDUCTOR DEVICE

A semiconductor device is provided with a silicon carbide semiconductor substrate, a silicon carbide layer, a switching element portion, and an overvoltage detection sensor element portion of smaller area than the switching element portion. The switching element portion has a first electrode pad, a first termination which surrounds the pad and is disposed on the silicon carbide layer, and a first dielectric film which covers the top of the first termination and is disposed so as to be in contact with the silicon carbide layer. The overvoltage detection sensor element portion has a second electrode pad, a second termination which surrounds the pad and is disposed on the silicon carbide layer, and a second dielectric film which covers the top of the second termination and is disposed so as to be in contact with the silicon carbide layer. The dielectric breakdown field strength in at least a part of the portion of the second dielectric film in contact with the silicon carbide layer is less ...

SOI DEVICE AND METHOD FOR ITS FABRICATION

A silicon on insulator (SOI) device [53] and methods for fabricating such a device are provided. The device includes an MOS capacitor [52] coupled between voltage busses [100, 102] and formed in a monocrystalline semiconductor layer [30] overlying an insulator layer [32] and a semiconductor substrate [34]. The device includes at least one electrical discharge path [86, 98, 180, 178] for discharging potentially harmful charge build up on the MOS capacitor [52]. The MOS capacitor has a conductive electrode material forming a first plate [64] of the MOS capacitor and an impurity doped region [60] in the monocrystalline silicon layer [30] beneath the conductive electrode material forming a second plate. A first voltage bus [100] is coupled to the first plate [64] of the capacitor and to an electrical discharge path through a diode [177] formed in the semiconductor substrate and a second voltage bus [102] is coupled to the second plate [60] of the capacitor.

SEMICONDUCTOR COMPONENT AND CORRESPONDING TESTING METHOD

The invention relates to a semiconductor component comprising a first main terminal (40); a second main terminal (80); a gate terminal (70) for controlling the current between the main terminals (40, 80), a first diode device (100) which can be switched between the first gate (40) and the gate terminal (70) and whose first breakdown voltage is such that the first diode device short-circuits the first main terminal (40) with the gate terminal (70), hereby switching on the semiconductor component, when the voltage that drops off over the first diode device (100) exceeds a certain predetermined value. The first diode device (100) is connected to the control gate (70) in an integrated manner and has an external contacting area (120) for connecting to the first main terminal (40).

VOLTAGE LIMITING PROTECTION FOR HIGH FREQUENCY POWER DEVICE

An RF power device comprising a power transistor fabricated in a first semiconductor chip and a MOSCAP type structure fabricated in a second semiconductor chip. A voltage limiting device is provided for protecting the power transistor from input voltage spikes and is preferably fabricated in the semiconductor chip along with the MOSCAP. Alternatively, the voltage limiting device can be a discrete element fabricated on or adjacent to the capacitor semiconductor chip. By removing the voltage limiting device from the power transistor chip, fabrication and testing of the voltage limiting device is enhanced, and semiconductor area for the power device is increased and aids in flexibility of device fabrication.

Semiconductor device having electro-static discharge protection structure

A semiconductor device, having an electro-static discharge (ESD) protection structure, comprises: a diode, connected between a gate and a source of the semiconductor device, and comprising a diode main body, and two connection portions, respectively connected to two terminals of the diode main body and respectively electrically connected to the gate and the source; and a substrate comprising two insulation pads disposed thereon and separated from each other. A surface of the substrate between the insulation pads is provided with an insulation layer. The diode main body is arranged on the insulation layer. The two connection portions are configured to extend, respectively, from either end of the diode main body to the insulation pad on the corresponding side. A dielectric layer is arranged on the diode and the two insulation pads, and a metal conduction line layer is arranged on the dielectric layer.

Semiconductor device with a diode-type ESD protection circuit

A semiconductor device has a semiconductor chip, an internal circuit region arranged on an inner side of the semiconductor chip, and a bonding pad region arranged adjacently to the internal circuit region. A diode-type ESD protection circuit is formed of a junction between a first conductivity type diffusion layer for fixing a substrate potential of the semiconductor chip and a pair of second conductivity type diffusion layers arranged on an inner side of the first conductivity type diffusion layer. The first conductivity type diffusion layer is arranged on an entire peripheral region or a part of the peripheral region of the semiconductor chip with the peripheral region being outside of the internal circuit region and the bonding pad region. One of the pair of second conductivity type diffusion layers comprising a diffusion layer for breakdown adjustment at a junction portion with the first conductivity type diffusion layer.

DISPLAY DEVICE INCLUDING ELECTROSTATIC DISCHARGE CIRCUIT

The present invention relates to a display device including a static electricity discharge circuit. The display device according to an exemplary embodiment of the present invention includes: a thin film transistor array panel including a display area including a plurality of pixels and a peripheral area around the display area; a signal wire positioned at the peripheral area; and a static electricity discharge circuit unit positioned at the peripheral area and connected to the signal wire, wherein the static electricity discharge circuit unit includes a first portion and a second portion positioned at a same layer as a portion of the signal wire and facing each other with a separation space therebetween, and a connecting member positioned at a different layer from the first portion and the second portion and electrically connecting the first portion and the second portion.

Low leakage diodes

A diode includes an anode of a first conductivity type; a first cathode of the first conductivity type; and a second cathode of a second conductivity type opposite the first conductivity type. A lightly-doped region of the first conductivity type is under and vertically overlaps the anode and the first and the second cathodes. The portion of the lightly-doped region directly under the second cathode is fully depleted at a state when no bias voltage is applied between the anode and the second cathode.

Semiconductor device

The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.

Electrostatic discharge protection circuit

There provided an electrostatic discharge protection circuit for preventing a damage to a transistor due to an ESD surge. In the protection circuit, a first and a second signal line serving as a source or a drain of a transistor Tr1 are connected to a first and a second power source terminal, respectively. A first diode has an anode connected to the first signal line and a cathode connected to a back gate of the transistor and a cathode of a second diode. The second diode has an anode connected to the second signal line 2. Thus, the source and drain of the transistor Tr1 are switched to each other in accordance with an ESD surge voltage generated in the first and the second signal line. Therefore, an ESD surge current runs through a source-drain path without producing a parasitic action in a well tap of the source and the drain, thereby preventing a damage to the transistor Tr1.

Semiconductor device with self-aligned protection diode

A self-aligned protection diode is formed at the first polycrystalline silicon level, thereby enabling in-process charging damage protection while reducing the layout area. The self-aligned protection diode is formed by providing an etch stop layer having an arcuate portion with different etching characteristics than horizontal portions, isotropically etching the arcuate portion to form a through hole exposing a side surface of a polycrystalline silicon layer and the underlying semiconductor substrate, ion implanting impurities to form the protection diode, and filling the through hole with a metal interconnecting the side surface of the polycrystalline silicon layer with the vertically self-aligned protection diode.

I.C. power supply terminal protection clamp

A power supply terminal clamping circuit for use in an integrated circuit protects positive and negative voltage power supply terminals from both overvoltage and ESD events. A diode stack is connected between a protected power supply terminal and ground, with the number of diodes in the stack establishing a clamping voltage. The stack becomes forward-biased when the voltage on the protected terminal reaches the clamping voltage, which triggers a switch that provides a current path between the terminal and ground that clamps the terminal voltage. A bipolar transistor embodiment includes a diode stack made from diode-connected bipolar transistors and a bipolar Darlington pair switch.

Semiconductor device having digital and analog circuits integrated on one chip

First and second well regions of N conductivity type are formed in a P-type semiconductor substrate. A digital circuit is formed in the first well region. An analog circuit is formed in the second well region. A power source wiring for supplying a bias potential is connected to the substrate. The power source wiring is connected to a power source terminal which is different from the power source terminal of the digital circuit.

Semiconductor memory device having contact holes of differing structure

A semiconductor memory device comprises a semiconductor substrate, a first conducting layer formed above the main surface of the semiconductor substrate, a second conducting layer formed above the first conducting layer through a first insulating layer and connected to the first conducting layer through a first via-conductor formed in a first contact hole formed in the first insulating layer, and a third conducting layer formed beneath the second conducting layer through a second insulating layer and connected to the second conducting layer through a second via-conductor formed in a second contact hole formed in the second insulating layer, in which an angle formed by a tangent to an inner wall of the first contact hole and a normal to the first conducting layer at a portion of the first conducting layer at which the first contact hole is in contact with the first conducting layer, is larger than an angle formed by a tangent to an inner wall of the second contact hole and a normal to the ...

Edge termination for zener-clamped power device

A semiconductor power device (100) that includes a number of bipolar or FET power devices (116), an over-voltage clamp (118), and an edge termination structure (110) that separates the power devices (116) and the over-voltage clamp (118). The power devices (116) are formed in an interior region (100a) of a semiconductor substrate (128), while the over-voltage clamp (118) is formed in a peripheral region (100b) of the substrate. The over-voltage clamp (118) and the gate/base terminals of the power devices (116) are formed in a polysilicon layer (126) overlying the substrate (128), such that the over-voltage clamp (118) is connected between the anode and gate/base terminals of each power device (116) to provide over-voltage protection. The edge termination structure (110) is formed in the substrate (128) so as to completely surround the interior region (100a) of the substrate (128), and therefore surrounds the power devices (116) to form a continuous barrier structure between the power devices ...

Semiconductor device

An amplifier circuit including a semiconductor element is formed on a substrate. A protection circuit is formed including a plurality of protection diodes that are formed on the substrate and that are connected in series with each other, the protection circuit being connected to an output terminal of the amplifier circuit. A pad conductive layer is formed that at least partially includes a pad for connecting to a circuit outside the substrate. An insulating protective film covers the pad conductive layer. The insulating protective film includes an opening that exposes a partial area of a surface of the pad conductive layer, and that covers another area. A first bump is formed on the pad conductive layer on a bottom surface of the opening, and a second bump at least partially overlaps the protection circuit in plan view and is connected to a ground (GND) potential connected to the amplifier circuit.

ESD protection circuit with very low input capacitance for high-frequency I/O ports

The present invention proposes an ESD protection circuit with low input capacitance, suitable for an I/O pad. The ESD protection circuit includes a plurality of diodes and a power-rail ESD clamp circuit between power lines. The diodes are stacked and coupled between a first power line and the I/O pad. The ESD protection circuit between power lines is coupled between the first power line and a second power line. During normal operation, the diodes are reverse-biased and the ESD protection circuit between power lines is turned off. When an ESD event between the power line and the I/O pad occurs, the diodes are forward-biased, and the ESD protection circuit between power lines is turned on to conduct ESD current. The equivalent input capacitance of the ESD protection circuit of the present invention is very small, making it particularly suitable for the I/O port of high-frequency or high-speed IC.

Electrostatic discharge protection device having a graded junction and method for forming the same

An electrostatic discharge protection device is formed in a substrate and contains a drain area of a first dopant concentration abutting an extended drain area having a dopant concentration lower than the first dopant concentration. Similarly, a highly doped source area abuts a lower doped source extension area. The source and drain are laterally bounded by oxide regions and covered by an insulation layer. The areas of lower doping prevent charge crowding during an electrostatic discharge event by resistively forcing current though the nearly planer bottom surface of the drain, rather than the curved drain extension. In addition, a highly doped buried layer can abut an area of a graded doping level. By adjusting the doping levels of the graded areas and the buried layers, the substrate breakdown voltage is pre-selected.

SOI voltage dependent negative-saturation-resistance resistor ballasting element for ESD protection of receivers and driver circuitry

A ballasting resistor incorporating therein an H-shaped gate structure reduces a current therethrough by utilizing a pinching effect. The ballasting resistor is formed on a silicon-on-insulator substrate and includes a pair of N+ regions, a P- body region formed between the NM regions, and a pair of P+ nodes connected to the P- body region. The P- body region resides under the gate structure, which includes a thin dielectric layer formed on the P- body region and a conductive layer formed on the dielectric layer. The ballasting resistor is biased in such a manner that the P-N junctions are reverse-biased to pinch down the cross-sectional area of the current path provided inside the P- body region between the nodes as an applied voltage increases. The ballasting resistor has a MOS transistor-like structure; and, therefore, electrostatic discharge protection can be provided for the conventional SOI MOS circuits without requiring additional processing steps.

Electronics device

An electronics device includes a power semiconductor device including a temperature detection diode, a first semiconductor integrated circuit device including a detection circuit for detecting VF from the temperature detection diode and a second semiconductor integrated circuit device. The second semiconductor integrated circuit device includes, an outside air temperature acquisition unit which acquires outside air temperature information, a storage which stores temperature characteristic data of the temperature detection diode and a first value based on a signal from the detection circuit at a first temperature and a temperature arithmetic processing unit which calculates a temperature of the power semiconductor device from a third value based on a signal from the detection circuit, the temperature characteristic data, the first temperature acquired by the outside air temperature acquisition unit and the first value.

Method and Device for Electrical Overstress and Electrostatic Discharge Protection

A semiconductor device is protected from electrical overstress (EOS) and electro-static discharge (ESD) events by a series protection circuit electrically coupled in series along the transmission line between a signal source and a load. The series protection circuit includes a first field-effect transistor (FET) electrically coupled in series between the signal source and load. A parallel protection circuit is electrically coupled between the transmission line and a ground node. The parallel protection circuit can include a transient-voltage-suppression (TVS) diode.

Circuit system for protecting thin dielectric devices from ESD induced damages

A circuit system is disclosed for protecting a capacitor coupled between a voltage supply node and a complementary voltage supply node from an ESD. The circuit system includes at least one NMOS transistor having a drain coupled to the voltage supply node, a source and a gate together coupled to the complementary voltage supply node, and at least one diode chain having one or more diodes serially coupled between the voltage supply node and the complementary voltage supply node. During an ESD event, the diode chain and the NMOS transistor dissipate an ESD current from the voltage supply node to the complementary voltage supply node, thereby protecting the capacitor from ESD induced damages.

Bipolar Transistor Including Lateral Suppression Diode

A transistor includes an emitter of a first conductivity type, base of a second conductivity type, collector of the first conductivity type, and cathode of a lateral suppression diode. The emitter is disposed at a top surface of the transistor and configured to receive electrical current from an external source. The base is configured to conduct the electrical current from the collector to the emitter. The base is disposed at the top surface of the transistor and laterally between the emitter and the collector. The collector is configured to attract and collect minority carriers from the base. The cathode of the first conductivity type is surrounded by the base and disposed between the emitter and the collector, and the cathode is configured to suppress a lateral flow of the minority carriers from the base to the collector.

Over charge protection device

An over-voltage protection device includes a substrate including an upper surface and a lower surface; a first electrode provided on the upper surface of the substrate; a second electrode provided on the lower surface on the substrate; a first conductive layer overlying the lower surface of the substrate, the first conductive region being a conductive region of a first type; a plurality of first conductive regions provided proximate the upper surface of the substrate, the plurality of first conductive regions being conductive regions of the first type; and a plurality of second conductive region provided proximate the upper surface of the substrate, the plurality of second conductive region being conductive regions of a second type. The plurality of the first conductive regions are provided in an alternating manner with the plurality of second conductive regions. The first electrode is contacting the plurality of the first and second conductive regions.

Electrostatic discharge protection structure

An electrostatic discharge, ESD, protection structure (200) formed within a semiconductor substrate of an integrated circuit device (600). The integrated circuit device (600) comprising: a radio frequency domain (632); a digital domain (610). The ESD protection structure (200) further includes an intermediate domain located between the radio frequency domain (632) and the digital domain (610) that comprises at least one radio frequency, RF, passive or active device that exhibits an impedance characteristic that increases as a frequency of operation increases.

Lateral transient voltage suppressor for low-voltage applications

A lateral transient voltage suppressor for low-voltage applications is disclosed. The suppressor comprises an N-type heavily doped substrate and at least two clamp diode structures horizontally arranged in the N-type heavily doped substrate. Each clamp diode structure further comprises a clamp well arranged in the N-type heavily doped substrate and having a first heavily doped area and a second heavily doped area. The first and second heavily doped areas respectively belong to opposite types. There is a plurality of deep isolation trenches arranged in the N-type heavily doped substrate and having a depth greater than depth of the clamp well. The deep isolation trenches can separate each clamp well. The present invention avoids the huge leakage current to be suitable for low-voltage application.

Electrostatic discharge (esd) protection device, method of fabricating the device, and electronic apparatus including the device

An electrostatic discharge (EDS) device includes a substrate, an external well of a first conductivity type in the substrate, and an internal well of a second conductivity type in the external well, the first conductivity type opposite the second conductivity type. The EDS device further includes a first heavily doped region of the first conductivity type located at a surface of the internal well, a second heavily doped region of the second conductivity type located at a surface of the internal well, and a third heavily doped region of the first conductivity type located at a surface of the external well. The second heavily doped region is interposed between and spaced from each of the first and third heavily doped regions, and at least one of a space between the first and second heavily doped regions and a space between the second and third heavily doped regions is devoid of a device isolation structure of electrical isolation material.

Electrostatic discharge protection circuit

An electrostatic discharge protection circuit includes a diode chain coupled between a power supply voltage end and a control node, a control voltage generator configured to generate a control voltage in response to a first current flowing through the diode chain, and a discharger configured to discharge a second current from the power supply voltage end to a ground voltage end in response to the control voltage, wherein the diode chain includes a plurality of P-well regions formed in an N-well region, diodes formed in the respective P-well regions, and a resistor coupled between the diodes.

Diode and electrostatic discharge protection circuit including the same

A diode includes a first region having a first conductive type impurity and formed in a first well having the first conductive type impurity, a second region formed in the first well and having a second conductive type impurity, and a semiconductor pattern disposed above the first well and including a first portion having the first conductive type impurity and a second portion having the second conductive type impurity. The first region and the first portion are coupled with an anode, and the second region and the second portion are coupled with a cathode.

Method for Preventing the Over-Stress of MV Devices

A device includes a first power supply line carrying a first positive power supply voltage, and a second power supply line carrying a second positive power supply voltage lower than the first positive power supply voltage. The device further includes a protection circuit having a MOS transistor. A diode is coupled to the MOS transistor. The source-to-drain path of the MOS transistor and the diode are serially coupled between the first and the second power supply lines. The diode is forward biased by the first and the second positive power supply voltages.

Semiconductor device and manufacturing method of the same

In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n + -type semiconductor region of the protective diode are formed in the same step.

Vertical substrate diode, method of manufacture and design structure

A diode structure, formed under a buried dielectric layer of a silicon on insulator (SOI), method of manufacturing the same and design structure thereof are provided. In an embodiment the p-n junction of the diode structure can be advantageously arranged in a vertical orientation. The cathode comprises an N+ epitaxial layer formed upon a P-type substrate. The anode comprises an active region of the P-substrate. Contacts to the cathode and anode are formed through the buried dielectric layer. Contact to the anode is accomplished via a deep trench filled with a conductive plug. The deep trench also provides electrical isolation for the cathode (as well as p-n junction). Advantageously, embodiments of the present invention may be formed during formation of other structures which also include trenches (for example, deep trench capacitors) in order to reduce process steps required to form the diode structure under the buried dielectric layer of the SOI substrate.

Semiconductor device

A high-frequency power amplifier of the type to be mounted in an RF module for mobile phones having high-frequency power field effect transistors and gate protective diodes which are coupled between the gates and the sources of the high-frequency power field effect transistors. The gate protective diodes have an n type region formed over the main surface of a p type epitaxial layer, a first p type region formed at the center of the main surface of the n type region, a second p type region formed over the main surface of the epitaxial layer around the n type region from the periphery of the main surface of the n type region, and p+ type buried layers for coupling the second p type region to a substrate body. The distance between the end portions of the p+ type buried layers and the n+ type region is 7 μm or more.

Semiconductor device and solid state relay using same

A semiconductor device includes one or more unipolar compound semiconductor element; and bypass semiconductor elements externally connected to the respective compound semiconductor elements in parallel. A turn-on voltage of the bypass semiconductor elements is smaller than a turn-on voltage of the compound semiconductor elements in the direction from the source to the drain.

Electrostatic discharge protection

A chip includes a first circuit, a second circuit, a first interconnect, and a least one protection circuit. The first circuit has a first node, a first operational voltage node, and a first reference voltage node. The second circuit has a second node, a second operational voltage node, and a second reference voltage node. The first interconnect is configured to electrically connect the first node and the second node to form a 2.5D or a 3D integrated circuit. The at least one protection circuit is located at one or various locations of the chip.

Transistor Assembly as an ESD Protection Measure

A diode ( 23 ) is arranged near a transistor ( 25 ) to protect from ESD. The diode comprises a well ( 5 ) of a first conductivity type and a doped region ( 4 ) of a second conductivity type in opposition to the first conductivity type. The transistor comprises a doped well ( 2 ) and a doped region ( 1 ) of the first conductivity type. The well ( 2 ) of the transistor is doped lower than the well ( 5 ) of the diode.

Semiconductor Device Including First and Second Semiconductor Elements

A semiconductor device includes a first semiconductor element including a first pn junction between a first terminal and a second terminal. The semiconductor device further includes a semiconductor element including a second pn junction between a third terminal and a fourth terminal. The semiconductor element further includes a semiconductor body including the first semiconductor element and the second semiconductor element monolithically integrated. The first and third terminals are electrically coupled to a first device terminal. The second and fourth terminals are electrically coupled to a second device terminal. A temperature coefficient α 1 of a breakdown voltage V br1 of the first pn junction and a temperature coefficient α 2 of a breakdown voltage V br2 of the second pn junction have a same algebraic sign and satisfy 0.6×α 1 <α 2 <1.1×α 1 at T=300 K, wherein V br2 <V br1 .

Isolated zener diode

Disclosed is a Zener diode having a scalable reverse-bias breakdown voltage (V b ) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. However, while the anode contact region is contained entirely within the anode well region, one end of the cathode contact region extends laterally into the anode well region. The length of this end can be predetermined in order to selectively adjust the V b of the diode (e.g., increasing the length reduces V b of the diode and vice versa). Also disclosed are an integrated circuit, incorporating multiple instances of the diode with different reverse-bias breakdown voltages, a method of forming the diode and a design structure for the diode.

Devices and methods related to electrostatic discharge-protected cmos switches

Disclosed are devices and methods related to a CMOS switch for radio-frequency (RF) applications. In some embodiments, the switch can be configured to include a resistive body-floating circuit to provide improved power handling capability. The switch can further include an electrostatic discharge (ESD) protection circuit disposed relative to the switch to provide ESD protection for the switch. Such a switch can be implemented for different switching applications in wireless devices such as cell phones, including band-selection switching and transmit/receive switching.

STRUCTURES AND TECHNIQUES FOR USING MESH-STRUCTURE DIODES FOR ELECTRO-STATIC DISCHARGE (ESD) PROTECTION

An Electro-Static Discharge (ESD) protection using at least one I/O pad with at least one mesh structure of diodes provided on a semiconductor body is disclosed. The mesh structure has a plurality of cells. At least one cell can have a first type of implant surrounded by at least one cell with a second type of implant in at least one side of the cell, and at least cell can have a second type of implant surrounded by at least one cell with a first type of implant in at least one side of the cell. The two types of implant regions can be separated with a gap. A silicide block layer (SBL) can cover the gap and overlap into the both implant regions to construct P/N junctions on the polysilicon or active-region body on an insulated substrate. Alternatively, the two types of implant regions can be isolated by LOCOS, STI, dummy gate, or SBL on silicon substrate. The regions with the first and the second type of implants can be coupled to serve as the first and second terminal of a diode, respectively. The mesh structure can have a first terminal coupled to the I/O pad and a first terminal coupled to a first supply voltage. 1. A diode constructed in a mesh structure including a plurality of cells on a semiconductor body , the mesh structure comprising:at least one cell with a first type of implant surrounded by at least one cell with a second type of implant in at least one side;at least one cell with the second type of implant surrounded by at least one cell with the first type of implant in at least one side; andan isolation region between the first and the second type of implants to form P/N junctions in at least one side of the cell on the semiconductor body, andwherein regions with the first implant are coupled to serve as a first terminal of the diode, and regions with the second implant are coupled to serve as a second terminal of the diode.2. A diode as recited in claim 1 , wherein the semiconductor body comprises polysilicon claim 1 , or active region on an ...

Method and system for ultra miniaturized packages for transient voltage suppressors

A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The transient voltage suppressor (TVS) assembly includes a semiconductor die including a contact surface on a single side of the die, the die further including a substrate comprising a layer of at least one of an electrical insulator material, a semi-insulating material, and a first wide band gap semiconductor having a conductivity of a first polarity, at least a TVS device including a plurality of wide band gap semiconductor layers formed on the substrate; a first electrode coupled in electrical contact with the TVS device and extending to the contact surface, and a second electrode electrically coupled to the substrate extending to the contact surface.

BIDIRECTIONAL SILICON CARBIDE TRANSIENT VOLTAGE SUPRESSION DEVICES

An electronic device includes a silicon carbide layer having a first conductivity type and having a first surface and a second surface opposite the first surface, and first and second silicon carbide Zener diodes on the silicon carbide layer. Each of the first and second silicon carbide Zener diodes may include a first heavily doped silicon carbide region having a second conductivity type opposite the first conductivity type on the silicon carbide layer, and an ohmic contact on the first heavily doped silicon carbide region. 1. A method of forming an electronic device , comprising:providing a first conductivity type silicon carbide substrate;forming two silicon carbide Zener diodes on the silicon carbide substrate, wherein the silicon carbide substrate provides a common cathode for the silicon carbide Zener diodes;forming first and second ohmic contacts on the mesas opposite the substrate; andforming a third ohmic contact on the silicon carbide substrate.2. The method of claim 1 , wherein forming the two silicon carbide Zener diodes comprises:providing a second conductivity type silicon carbide epitaxial layer on the first conductivity type silicon carbide substrate; andetching through the second conductivity type silicon carbide epitaxial layer to form a pair of mesas that define respective Zener junctions.3. The method of claim 2 , further comprising:providing a first conductivity type silicon carbide epitaxial layer on the silicon carbide substrate, wherein the second conductivity type silicon carbide epitaxial layer is formed on the first conductivity type silicon carbide epitaxial layer;wherein etching the second conductivity type silicon carbide epitaxial layer to form the pair of mesas comprises etching into the first conductivity type silicon carbide epitaxial layer.4. The method of claim 3 , wherein etching the second conductivity type silicon carbide epitaxial layer to form the pair of mesas comprises etching through the first conductivity type silicon ...

Semiconductor device

A semiconductor device for protecting loads from power surges includes a first resistor having a first end connected to a first supply terminal, a capacitor connected to a second end of the first resistor and a second supply terminal. There is a first transistor with a source connected to the first supply terminal and a gate connected to a point between the first resistor and the capacitor. A second resistor is connected between the drain of the first transistor and the second supply terminal, and a first diode is connected between the gate and the source of the first transistor. A second transistor has a drain connected to the first supply terminal, a source connected to the second supply terminal, and a gate connected to the drain of the first transistor. There is a second diode connected between the gate and the source of the second transistor.

Passive devices for finfet integrated circuit technologies

Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A portion of a device layer of a semiconductor-on-insulator substrate is patterned to form a device region. A well of a first conductivity type is formed in the epitaxial layer and the device region. A doped region of a second conductivity type is formed in the well and defines a junction with a portion of the well. The epitaxial layer includes an exterior sidewall spaced from an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.

Diode Biased ESD Protection Device and Method

An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.

Diode Biased ESD Protection Device and Method

An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region. 1. A method of forming a semiconductor device , the method comprising:providing a semiconductor body of a first conductivity type;forming a gate region over a portion of the semiconductor body;forming highly doped source and drain regions of a second conductivity type opposite to the first conductivity type in the semiconductor body adjacent to the gate region;forming a diode on the semiconductor body, the diode comprising a first diode region of the first conductivity type and a second diode region of the second conductivity type;forming an external connection pad on the semiconductor body;electrically coupling the highly doped drain to the external connection pad;electrically coupling the diode between the gate region and the highly doped source region, wherein the second diode region of the second conductivity type is coupled to the gate region and the first diode region of the first conductivity type is coupled to the doped source region; andelectrically coupling the highly doped source region to a reference potential.2. The method of claim 1 , wherein the reference potential is ground.3. The method of claim 1 , wherein forming the diode comprises:doping a portion of the gate region adjacent to the highly doped source and drain with a material of the second conductivity type, thereby forming the second diode region; anddoping a portion of the gate region adjacent to the second diode region with a material of the first conductivity type, thereby forming the first diode region.4. The method of claim 1 , wherein forming the diode comprises:forming a first doped region of the second conductivity type over a region of the semiconductor body, ...

SEMICONDUCTOR DEVICE HAVING DIODE-BUILT-IN IGBT AND SEMICONDUCTOR DEVICE HAVING DIODE-BUILT-IN DMOS

A semiconductor device includes: a semiconductor substrate; a diode-built-in insulated-gate bipolar transistor having an insulated-gate bipolar transistor and a diode, which are disposed in the substrate, wherein the insulated-gate bipolar transistor includes a gate, and is driven with a driving signal input into the gate; and a feedback unit for detecting current passing through the diode. The driving signal is input from an external unit into the feedback unit. The feedback unit passes the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects no current through the diode, and the feedback unit stops passing the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects the current through the diode. 113-. (canceled)14. A semiconductor device comprising:a semiconductor substrate;a diode-built-in insulated-gate bipolar transistor having an insulated-gate bipolar transistor and a diode unit, which are disposed in the substrate, wherein the insulated-gate bipolar transistor includes a gate, and is driven with a driving signal input into the gate, wherein the diode unit includes a diode element and a diode current sensing element, and wherein the diode current sensing element passes current in proportion to current flowing through the diode element;a sensing resistor coupled with the diode current sensing element; anda feedback unit,wherein the driving signal is input from an external unit into the feedback unit,wherein the feedback unit provides a first diode current threshold, which defines whether the diode element passes current,wherein the feedback unit compares a voltage between two ends of the sensing resistor with the first diode current threshold,wherein the feedback unit passes the driving signal to the gate of the insulated-gate bipolar transistor so that the insulated-gate bipolar transistor turns on when the voltage between two ends of the sensing resistor is equal to or ...

Electrical Device and Method for Manufacturing Same

An electrical device includes a first layer, a second layer and an intrinsic layer. The first layer is of a first conductivity type, wherein the second layer is of a second conductivity type opposite to the first conductivity type. The intrinsic layer is arranged between the first and the second layer and has a reduced thickness at at least one portion. An area of the at least one portion is less than 50% of an active area in which the first and second layer face each other.

METHODS OF FORMING ELECTRONIC ELEMENTS WITH ESD PROTECTION

An electrostatic discharge (ESD) protection circuit () is coupled across input-output (I/O) pads () and common terminals () of a circuit core () to protect it from ESD events. The circuit () comprises, a unidirectional ESD clamp () and two or more floating diodes () arranged in parallel opposed configuration in series with the ESD clamp (), the combination coupled between the I/O pads () and the reference terminals (). In a preferred arrangement, the two strings of opposed parallel coupled diodes () are used with different numbers of diodes in each string. These diodes () operate in forward conduction (), so the energy dissipated therein during an ESD event is much reduced compared to a reverse biased diode and they can have smaller area. Signal clipping at the I/O pad () is reduced, less power is dissipated and less chip area is utilized. 1. A method for forming an electronic element , comprising:providing a substrate on or in which has been formed a circuit core having first and second terminals desired to be protected from electrostatic discharge (ESD) events and an asymmetrical ESD protection device having third and fourth terminals, the substrate having an insulating first surface region;depositing on the first surface region of the substrate a polycrystalline semiconductor (PSC) layer;in a first portion of the PSC layer, forming N diodes by localized doping of the PSC layer, wherein the PSC layer has therein N+(N−1) PN junctions of which (N−1) are shorted together;in a second portion of the PSC layer, forming M diodes by localized doping of the PSC layer, wherein the PSC layer has therein M+(M−1) PN junctions of which (M−1) are shorted together; andelectrically coupling the N diodes and M diodes in opposed parallel configuration between the first terminal of the circuit core and the third terminal of the ESD protection device, and coupling the fourth terminal of the ESD protection device to the second terminal of the circuit core.2. The method of claim 1 , ...

On-SOI integrated circuit comprising a lateral diode for protection against electrostatic discharges

An integrated circuit includes a transistor, an UTBOX buried insulating layer disposed under it, a ground plane disposed under the layer, a well disposed under the plane, a first trench made at a periphery of the transistor and extending through the layer and into the well, a substrate situated under the well, a p-n diode made on a side of the transistor and comprising first and second zones of opposite doping, the first zone being configured for electrical connection to a first electrode of the transistor, wherein first and second zones are coplanar with the plane, a second trench for separating the first and second zones, the second trench extending through the layer into the plane and until a depth less than an interface between the plane and the well, and a third zone under the second trench forming a junction between the zones.

ESD Protection

A two-stage protection device for an electronic component protects against transient disturbances. The electronic component may be a semiconductor component, and may include one or multiple transistors and/or an integrated circuit. The protection device is connected to at least a first contact and a second contact of the electronic component, and is disposed essentially in parallel to the component that is to be protected, between the first contact and the second contact. The protection device includes a first stage with at least one diode and a second stage separated from the first stage by a resistor. The second stage includes at least one diode arrangement having two back-to-back disposed diodes which are disposed cathode-to-cathode. 1. A protection device for protection against transient disturbances , the protection device configured for electrical connection to at least a first contact and a second contact of an electronic component , the protection device comprising:a first stage with at least one diode, the first stage being connected to at least one terminal; anda second stage separated from the first stage by a resistor and directly connected to the first contact and to the second contact, the second stage being adapted for smaller current than the first stage and comprising at least one diode arrangement including two back-to-back polysilicon diodes, the two back-to-back polysilicon diodes being disposed cathode-to-cathode in a p-n-p configuration comprising a floating n-type area between a first p-type area and a second p-type area.2. The protection device of claim 1 , wherein one anode of the two back-to-back polysilicon diodes is connected to the first contact of the electronic component by a connection having essentially zero resistance.3. The protection device of claim 1 , wherein the electronic component is a silicon semiconductor component having a silicon substrate and the two back-to-back polysilicon diodes are disposed on the silicon substrate.4 ...

SEMICONDUCTOR-ON-INSULATOR DEVICE WITH ASYMMETRIC STRUCTURE

Device structures with a reduced junction area in an SOI process, methods of making the device structures, and design structures for a lateral diode. The device structure includes one or more dielectric regions, such as STI regions, positioned in the device region and intersecting the p-n junction between an anode and cathode. The dielectric regions, which may be formed using shallow trench isolation techniques, function to reduce the width of a p-n junction with respect to the width area of the cathode at a location spaced laterally from the p-n junction and the anode. The width difference and presence of the dielectric regions creates an asymmetrical diode structure. The volume of the device region occupied by the dielectric regions is minimized to preserve the volume of the cathode and anode. 1. A device structure fabricated in a semiconductor layer of a semiconductor-on-insulator (SOI) substrate , the device structure comprising:a cathode including a first region of the semiconductor layer doped with a first conductivity type and a first width in the semiconductor layer; andan anode including a first region of a second conductivity type in the semiconductor layer, the anode arranged relative to the cathode so that the first region of the anode is coextensive with the first region of the cathode along a p-n junction, and the p-n junction having a second width measured in a direction parallel to the first width and shorter than the first width of the first region measured at a location spaced laterally from the p-n junction.2. The device structure of wherein the SOI substrate includes a buried dielectric layer and a handle wafer separated from the semiconductor layer by the buried dielectric layer claim 1 , and further comprising:at least one first dielectric region in the semiconductor layer, the at least one first dielectric region extending from a top surface of the semiconductor layer to the buried dielectric layer, and the at least one first dielectric region ...

Stacked and Tunable Power Fuse

The present disclosure provides a semiconductor device that includes a transistor including a substrate, a source, a drain, and a gate, and a fuse stacked over the transistor. The fuse includes an anode contact coupled to the drain of the transistor, a cathode contact, and a resistor coupled to the cathode contact and the anode contact via a first Schottky diode and a second Schottky diode, respectively. A method of fabricating such semiconductor devices is also provided. 1. A semiconductor device , comprising:a transistor including a substrate, a source, a drain, and a gate, wherein the source is grounded; and a first contact coupled to the drain of the transistor;', 'a second contact; and', 'a resistor coupled to the first contact and the second contact via at least one Schottky diode, and', 'wherein the fuse is configured to blow at a voltage between about 20 V and about 700 V., 'a fuse coupled to the transistor, the fuse including2. The semiconductor device of claim 1 , wherein the first contact is an anode contact and the second contact is a cathode contact.3. The semiconductor device of claim 1 , the at least one Schottky diode further includes:a first Schottky diode coupled between the first contact of the fuse and the resistor;a second Schottky diode coupled between the second contact of the fuse and the resistor.4. The semiconductor device of claim 1 , wherein the transistor includes an isolation structure disposed between the gate and the drain claim 1 , the isolation structure and the drain being within a n-well within the substrate claim 1 , and the substrate being doped with a p-type dopant.5. The semiconductor device of claim 1 , wherein the resistor includes a plurality of turns.6. The semiconductor device of claim 1 , further comprising a dielectric layer between the gate of the transistor and the resistor of the fuse.7. A semiconductor device claim 1 , comprising:a plurality of transistors, each transistor including a substrate, a source, a drain, ...

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE

A semiconductor device capable of ensuring a withstand voltage of a transistor and reducing a forward voltage of a Schottky barrier diode in a package with the transistor and the Schottky barrier diode formed on chip, and a semiconductor package formed by a resin package covering the semiconductor device are provided. The semiconductor device includes a semiconductor layer a transistor area D formed on the semiconductor layer and constituting the transistor and a diode area C formed on the semiconductor layer and constituting the Schottky barrier diode The semiconductor layer in the diode area C is thinner than the semiconductor layer in the transistor area D. 1. A semiconductor device , comprising:a semiconductor substrate; a first conductive type semiconductor area, formed on the semiconductor substrate,', 'a second conductive type semiconductor area, formed on the first conductive type semiconductor area,', 'a transistor area, comprising a transistor,', 'a diode area, comprising a Schottky barrier diode; and, 'a semiconductor layer, comprisinga metal film, electrically connected to the transistor and Schottky bonded with the semiconductor layer in the diode area,wherein a recessed portion is formed on the semiconductor layer in the diode area, which the recessed portion penetrates through the second conductive type semiconductor area to reach the first conductive type semiconductor area, and the Schottky barrier diode is formed in the first conductive type semiconductor area of the recessed portion.222. The semiconductor device according to claim 1 , wherein the Schottky barrier diode having a bottom surface portion parallel to a back surface (B) of the semiconductor substrate claim 1 , and a side surface portion perpendicular to the back surface.3. The semiconductor device according to claim 1 , wherein the semiconductor layer in the diode area is 1 μm or more thinner than the semiconductor layer in the transistor area.4. The semiconductor device according to ...

Field Controlled Diode With Positively Biased Gate

An integrated circuit containing a field controlled diode which includes a p-type channel region between an upper gate and a lower n-type depletion gate, a p-type anode in a p-type anode well abutting the channel region, and an n-type cathode in a p-type anode well abutting the channel region opposite from the anode well. An n-type lower gate link connects the lower gate to the surface of the substrate. A surface control element is located at the surface of the channel region between the cathode and the upper gate. A process of forming the integrated circuit containing the field controlled diode is described.

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME

A capacitive component region is formed below a temperature detecting diode or below a protective diode. In addition, the capacitive component region is formed below an anode metal wiring line connecting the temperature detecting diode and an anode electrode pad and below a cathode metal wiring line connecting the temperature detecting diode and a cathode electrode pad. The capacitive component region is an insulating film interposed between polysilicon layers. Specifically, a first insulating film, a polysilicon conductive layer, and a second insulating film are sequentially formed on a first main surface of a semiconductor substrate, and the temperature detecting diode, the protective diode, the anode metal wiring line, or the cathode metal wiring line is formed on the upper surface of the second insulating film. Therefore, it is possible to improve the static electricity resistance of the temperature detecting diode or the protective diode. 1. A semiconductor device comprising:a semiconductor element that makes a current flow in a thickness direction of a semiconductor substrate;a diode that is connected to the semiconductor element;a first insulating film that is formed on a first main surface of the semiconductor substrate;a conductive layer that is formed on the first insulating film;a second insulating film that is formed on the conductive layer;a first-conductivity-type layer and a second-conductivity-type layer that are formed on the second insulating film and form the diode;a first capacitor that has the second insulating film between the first-conductivity-type layer and the conductive layer as a first capacitive component region; anda second capacitor that has the second insulating film between the second-conductivity-type layer and the conductive layer as a second capacitive component region,wherein the conductive layer is electrically insulated.2. The semiconductor device according to claim 1 ,wherein the semiconductor element includes:a first ...

BI-DIRECTIONAL ESD DIODE STRUCTURE WITH ULTRA-LOW CAPACITANCE THAT CONSUMES A SMALL AMOUNT OF SILICON REAL ESTATE

A bi-directional electrostatic discharge diode structure consumes substantially less silicon real estate and provides ultra-low capacitance by utilizing a p− epitaxial layer that touches and lies between an n+ lower epitaxial layer and an n+ upper epitaxial layer. A metal contact touches and lies over a p+ layer, which touches and lies over the n+ upper epitaxial layer. 1. A diode structure comprising:a substrate region of a first conductivity type, the substrate region having a dopant concentration;a first semiconductor layer of a second conductivity type, the first semiconductor layer having a dopant concentration, and touching and lying over the substrate region;a second semiconductor layer of the first conductivity type, the second semiconductor layer touching and lying over the first semiconductor layer, the second semiconductor layer having a dopant concentration that is substantially less than the dopant concentration of the substrate region;a third semiconductor layer of the second conductivity type, the third semiconductor layer touching and lying over the second semiconductor layer; anda fourth semiconductor layer of the first conductivity type, the fourth semiconductor touching and lying over the third semiconductor layer.2. The diode structure of wherein the third semiconductor layer has a dopant concentration substantially equal to the dopant concentration of the first semiconductor layer.3. The diode structure of wherein the fourth semiconductor layer has a dopant concentration substantially equal to the dopant concentration of the substrate region.4. The diode structure of and further comprising a metal contact that touches and lies over the fourth semiconductor layer.5. The diode structure of wherein the second semiconductor layer lies completely between the first semiconductor layer and the third semiconductor layer.6. The diode structure of wherein the third semiconductor layer lies completely between the second semiconductor layer and the fourth ...

SEMICONDUCTOR DEVICE AND FAULT DETECTING METHOD

An obtained margin is smaller than a margin to be kept for a fault period predicted by life prediction based on a power cycle test, extending a maintenance cycle for replacement and so on. A method of detecting a fault of a semiconductor device including a power device mounted on a metal base and a drive circuit for driving the power device, the method detecting a fault of the semiconductor device beforehand based on an increase in thermal resistance between the metal base and the power device. A state of the power device is measured immediately before and after the power device is driven by the drive circuit. A temperature difference of the power device before and after driving is calculated according to the result of measurement. An increase in thermal resistance between the metal base and the power device is detected based on the temperature difference and an amount of electricity inputted to the power device in the driving period, and a fault of the semiconductor device is detected beforehand according to the increase. 1. A semiconductor device comprising:a power device mounted on a metal base;a drive circuit for driving the power device;a measuring circuit that measures a state of the power device immediately before and after a driving period in which the drive circuit drives the power device; anda control circuit that detects, according to a result of the measurement by the measuring circuit, an increase in thermal resistance between the metal base and the power device based on a temperature difference before and after the driving of the power device and input power to the power device in the driving period.2. The semiconductor device according to claim 1 ,wherein the control circuit causes the drive circuit to perform the driving on a condition that the input power is set at a predetermined value.3. The semiconductor device according to claim 2 ,wherein the drive circuit drives the power device in response to a driving signal with pulse width modulation, the ...

ESD PROTECTION STRUCTURE

An ESD protection structure comprising a thyristor structure. The thyristor structure is formed from a first P-doped section comprising a first P-doped well formed within a first region of a P-doped epitaxial layer, a first N-doped section comprising a deep N-well structure, a second P-doped section comprising a second P-doped well formed within a second region of the epitaxial layer, and a second N-doped section comprising an N-doped contact region formed within a surface of the second P-doped well. The ESD protection structure further comprises a P-doped region formed on an upper surface of the deep N-well structure and forming a part of the second P-doped section of the thyristor structure. 1. An electrostatic discharge , ESD , protection structure formed within a semiconductor substrate of an integrated circuit device; the ESD protection structure comprising at least a first thyristor structure being formed from:a first P-doped section comprising a first P-doped well formed within a first region of a P-doped epitaxial layer, the first P-doped section coupled to a power supply contact of the integrated circuit device to which ESD currents are to be shunted,a first N-doped section comprising a deep N-well structure,a second P-doped section comprising a second P-doped well formed within a second region of the epitaxial layer, anda second N-doped section comprising an N-doped contact region formed within a surface of the second P-doped well, the second N-doped section coupled to a contact of the integrated circuit device to be protected by the ESD protection structure;wherein the ESD protection structure further comprises a P-doped region formed on an upper surface of the deep N-well structure in contact with the second P-doped region of the epitaxial layer such that the P-doped region formed on the upper surface of the deep N-well structure forms a part of the second P-doped section of the first thyristor structure.2. The ESD protection structure of claim 1 , ...

MODULAR INTERCONNECTS FOR GATE-ALL-AROUND TRANSISTORS

A modular interconnect structure facilitates building complex, yet compact, integrated circuits from vertical GAA FETs. The modular interconnect structure includes annular metal contacts to the transistor terminals, sectors of stacked discs extending radially outward from the vertical nanowires, and vias in the form of rods. Extension tabs mounted onto the radial sector interconnects permit signals to fan out from each transistor terminal. Adjacent interconnects are linked by linear segments. Unlike conventional integrated circuits, the modular interconnects as described herein are formed at the same time as the transistors. Vertical GAA NAND and NOR gates provide building blocks for creating all types of logic gates to carry out any desired Boolean logic function. Stacked vertical GAA FETs are made possible by the modular interconnect structure. The modular interconnect structure permits a variety of specialized vertical GAA devices to be integrated on a silicon substrate using standard CMOS processes. 1. An apparatus comprising:a substrate having a substrate surface;a plurality of transistors, each transistor having a source terminal, a gate terminal, and a drain terminal extending out from the substrate in a direction transverse to the substrate surface; and a plurality of annular contacts, each annular contact aligned with and coupled to one of the terminals of the selected ones of the plurality of transistors;', 'a plurality of radial sectors, each radial sector coupled to one of the annular contacts and forming a conductive domain in a plane aligned with a respective one of the terminals; and', 'a plurality of vias coupled to selected ones of the conductive domains, the vias aligned substantially transverse to the substrate surface., 'a modular interconnect structure coupled to selected terminals of selected ones of the plurality of transistors, the modular interconnect structure including2. The apparatus of wherein the substrate is doped.3. The apparatus of ...

DISPLAY DEVICE

A display device includes a substrate including a display area and a non-display area, a first wiring at the non-display area of the substrate, a second wiring on a layer that is different from the first wiring at the non-display area of the substrate, an inorganic insulating layer on the first wiring and the second wiring, a pad on the inorganic insulating layer, and connected to a first end of the first wiring, a contact bridge on the inorganic insulating layer, and connecting the second wiring to a second end of the first wiring, an electrostatic electrode on the inorganic insulating layer between the pad and the contact bridge, a first organic insulating layer covering the contact bridge and the electrostatic electrode, and exposing the pad, a first upper wiring on the first organic insulating layer, and overlapping the contact bridge and the electrostatic electrode, and a second organic insulating layer on the first upper wiring. 1. A display device comprising:a substrate comprising a display area and a non-display area;a first wiring at the non-display area of the substrate;a second wiring on a layer that is different from the first wiring at the non-display area of the substrate;an inorganic insulating layer on the first wiring and the second wiring;a pad on the inorganic insulating layer, and connected to a first end of the first wiring;a contact bridge on the inorganic insulating layer, and connecting the second wiring to a second end of the first wiring;an electrostatic electrode on the inorganic insulating layer between the pad and the contact bridge;a first organic insulating layer covering the contact bridge and the electrostatic electrode, and exposing the pad;a first upper wiring on the first organic insulating layer, and overlapping the contact bridge and the electrostatic electrode; anda second organic insulating layer on the first upper wiring.2. The display device of claim 1 , wherein a distance from the pad to the contact bridge is greater than a ...

INTEGRATED CIRCUIT PROTECTION METHOD, AND CORRESPONDING INTEGRATED CIRCUIT

An integrated circuit includes a number of components disposed at a surface of a semiconductor body and an interconnect region connecting the components into a functional circuit. A metallic shield is also produced in the interconnect region. A configurable stage is configurable to operate in a receiving antenna configuration or in a detection configuration during which the integrated circuit is configured to detect a presence of an external electromagnetic radiation representative of an attack by injection of faults 1. A method comprising:experiencing, at an integrated circuit, an attack by injection of faults via an external electromagnetic radiation; and|using a metallic shield to detect the external electromagnetic radiation, the integrated circuit comprising the metallic shield disposed in an interconnection region of the integrated circuit.2. The method according to claim 1 , wherein using the metallic shield to detect the external electromagnetic radiation comprises locating the metallic shield in a receiving antenna configuration and a detecting a signal greater than a threshold flowing in the metallic shield.3. The method according to claim 1 , further comprising adjusting a sensitivity of detection by connecting a variable resistor to the metallic shield.4. The method according to claim 1 , wherein prior to using the metallic shield to detect the external electromagnetic radiation claim 1 , the method further comprises verifying an integrity of the metallic shield by checking a possible interruption of current flow in the metallic shield.5. An integrated circuit comprising:a plurality of components disposed at a surface of a semiconductor body;an interconnect region connecting the components into a functional circuit; anda protection device comprising a detector produced in the interconnect region, wherein the detector comprises a metallic shield and is configured to detect a presence of an external electromagnetic radiation representative of an attack by ...

CIRCUITRY WITH VOLTAGE LIMITING AND CAPACTIVE ENHANCEMENT

Aspects of the present disclosure are directed to circuitry operable with enhanced capacitance and mitigation of avalanche breakdown. As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves respective transistors of a cascode circuit, one of which controls the other in an off state by applying a voltage to a gate thereof. A plurality of doped regions are separated by trenches, with the conductive trenches being configured and arranged with the doped regions to provide capacitance across the source and the drain of the second transistor, and restricting voltage at one of the source and the drain of the second transistor, therein mitigating avalanche breakdown of the second transistor. 1. An apparatus comprising: a first transistor having a gate, a source, a channel and a drain; and', 'a second transistor having a gate, a source, a channel and a drain electrically connected to the source of the first transistor, the second transistor being configured and arranged to control the first transistor in an off state by applying a voltage to the gate of the first transistor;, 'a cascode circuit susceptible to overvoltage conditions including avalanche breakdown, the cascode circuit includinga plurality of conductive trenches; anda set of one or more doped regions, each doped region being between a respective adjacent pair of the conductive trenches and configured to provide a p-n junction, wherein the plurality of conductive trenches and one or more doped regions are configured and arranged with the cascode circuit to provide capacitance across the source and the drain of the second transistor and to mitigate avalanche breakdown of the second transistor by restricting a voltage level at the source or the drain of the second transistor,wherein the one or more doped regions and the conductive trenches are part of a circuit connected to the source and drain of the second transistor in parallel with the channel of the second ...

BIDIRECTIONAL ELECTROSTATIC DISCHARGE PROTECTION DEVICE

Provided by the present disclosure is a bidirectional electrostatic discharge protection device which includes a first doped region, a second doped region, a third doped region, a first diode and a second diode. The first doped region has a first conductivity type, and the second doped region and the third doped region both have a second conductivity type. The first doped region has a ring structure outside the second doped region and the third doped region. A cathode of the first diode is coupled to the first doped region, and an anode of the first diode is coupled to a first port together with the second doped region. A cathode of the second diode is coupled to the first doped region, and an anode of the second diode is coupled to a second port together with the third doped region. 1. A bidirectional electrostatic discharge protection device , comprising:a first doped region with a first conductivity type;a second doped region with a second conductivity type;a third doped region with the second conductivity type, wherein the first doped region has a ring structure outside the second doped region and the third doped region;a first diode having a cathode coupled to the first doped region, and an anode coupled to a first port together with the second doped region; anda second diode having a cathode coupled to the first doped region, and an anode coupled to a second port together with the third doped region.2. The bidirectional electrostatic discharge protection device according to claim 1 , wherein the first doped region claim 1 , the second doped region and the third doped region jointly form a bipolar transistor.3. The bidirectional electrostatic discharge protection device according to claim 1 , wherein the first doped region claim 1 , the second doped region and the third doped region jointly form two or more bipolar transistors coupled in parallel.4. The bidirectional electrostatic discharge protection device according to claim 1 , wherein the second doped ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

An insulating film provided between adjacent pixels is referred to as a bank, a partition, a barrier, an embankment or the like, and is provided above a source wiring or a drain wiring for a thin film transistor, or a power supply line. In particular, at an intersection portion of these wirings provided in different layers, a larger step is formed there than in other portions. Even when the insulating film provided between adjacent pixels is formed by a coating method, thin portions are problematically partially formed due to this step and the withstand pressure is reduced. In the present invention, a dummy material is arranged near the large step portion, particularly, around the intersection portion of wirings, so as to alleviate unevenness formed thereover. The upper wiring and the lower wiring are arranged in a misaligned manner so as not to align the end portions. 1. A display device comprising:a first conductive layer over an insulating surface;a first insulating layer over the first conductive layer,a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer over the first insulating layer,wherein the first conductive layer has a region electrically connected to a transistor and functioning as a gate wiring,wherein the second conductive layer has a region electrically connected to the transistor and functioning as a source wiring,wherein the third conductive layer has a region electrically connected to the transistor and functioning as a drain wiring,wherein the fourth conductive layer comprises a same material as the second conductive layer and the third conductive layer,wherein the fourth conductive layer is in a floating state,wherein the fifth conductive layer has a region electrically connected to a transistor located adjacent to the transistor and functioning as a source wiring,wherein the first conductive layer has a region overlapping an entire lower surface of the fourth conductive layer,wherein in a ...

GROUP III-NITRIDE POLARIZATION JUNCTION DIODES

Diodes employing one or more Group III-Nitride polarization junctions. A III-N polarization junction may include two III-N material layers having opposite crystal polarities. The opposing polarities may induce a two-dimensional charge sheet (e.g., 2D electron gas) within each of the two III-N material layers. Opposing crystal polarities may be induced through introduction of an intervening layer between two III-N material layers. The intervening layer may be of a material other than a Group III-Nitride. Where a P-i-N diode structure includes two Group III-Nitride polarization junctions, opposing crystal polarities at a first of such junctions may induce a 2D electron gas (2DEG), while opposing crystal polarities at a second of such junctions may induce a 2D hole gas (2DHG). Diode terminals may then couple to each of the 2DEG and 2DHG. 125-. (canceled)26. A diode structure , comprising:a first layer comprising a Group III-nitride (III-N) material having a first crystal polarity;a second layer comprising a III-N material having a second crystal polarity, inverted from the first crystal polarity;an intervening layer between the first and the second layers, wherein the intervening layer comprises other than a III-N material; anda first contact electrically coupled across at least one of the first and second layers to a second contact.27. The diode structure of claim 26 , wherein:the first layer comprises a first III-N material; andthe first contact is electrically coupled to the first III-N material through a first terminal material having a higher concentration of donor impurities than the first III-N material.28. The diode structure of claim 27 , further comprising:a third layer comprising a III-N material having the first crystal polarity;a second intervening between the second layer and the third layer, wherein the second intervening layer comprises other than a III-N material; andwherein the second contact is coupled to the third layer through a second III-N ...

Method for producing a through semiconductor via connection

A method of producing a through semiconductor via (TSV) connection is disclosed. In one aspect, an opening of the TSV is produced for contacting a first semiconductor die bonded to a second die or to a temporary carrier. The first die includes fin-shaped devices in the front end of line of the die. Etching of the TSV opening does not end on a metal pad, but the opening is etched until reaching a well that is formed of material of a first doping type and formed in the first die amid semiconductor material of a second doping type opposite the first. After filling the TSV opening with a conductive material, the TSV connects to a conductor of an intermediate metallization (IM) of the first die through at least one fin extending from the well and connected to the conductor. A package of dies comprising at least one TSV produced by the above method is also disclosed.

ELECTRONIC CIRCUIT WITH ELECTROSTATIC DISCHARGE PROTECTION

A semiconductor substrate includes a doped region having an upper surface. The doped region may comprise a conduction terminal of a diode (such as cathode) or a transistor (such as a drain). A silicide layer is provided at the doped region. The silicide layer has an area that only partially covers an area of the upper surface of the doped region. The partial area coverage facilitates modulating the threshold voltage and/or leakage current of an integrated circuit device. 1. An integrated circuit device , comprising:a semiconductor substrate including a doped region having an upper surface; anda silicide layer having an area that only partially covers an area of the upper surface of the doped region.2. The integrated circuit device of claim 1 , wherein the doped region is one of a source or drain region of a MOS-type transistor.3. The integrated circuit device of claim 1 , wherein the doped region is one of an anode or cathode of a diode.4. The integrated circuit device of claim 3 , wherein a portion of the anode of the diode is covered with a control electrode.5. The integrated circuit device of claim 1 , wherein the doped region forms a cathode of a diode and a drain a transistor which are electrically connected in series with each other.6. The integrated circuit device of claim 5 , wherein the doped region has a dopant concentration in a range from 10to 10atoms/cm.7. The integrated circuit device of claim 5 , further comprising a further silicide layer having an area that only partially covers an area of the upper surface of a further doped region in the semiconductor substrate forming an anode of the diode.8. The integrated circuit device of claim 5 , further comprising a further silicide layer having an area that only partially covers an area of the upper surface of a further doped region in the semiconductor substrate forming a source of the transistor.9. The integrated circuit device of claim 5 , wherein the diode and transistor which are electrically ...

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring connected to a signal terminal. Diffusion regions are separated in a whole part or one part of a range in a Y direction. That is, under first wiring, diffusion regions are only formed in parts opposed to diffusion regions formed under the second wiring and third wiring connected to a power supply terminal or a ground terminal, and a diffusion region is not formed in a central part in an X direction. Therefore, terminal capacity of the signal terminal can be reduced without causing ESD resistance to be reduced, in an ESD protection circuit with the signal terminal. 1. A semiconductor integrated circuit device having an ESD (Electro Static Discharge) protection circuit , wherein: a first wiring electrically connected to a first terminal;', 'a second wiring and a third wiring electrically connected to a power supply terminal or a ground terminal;', 'a first region and a second region having a first conductivity type, that are connected to the first wiring, the first and second regions being separated from each other and serving as one of an anode or a cathode of a diode;', 'a third region having a second conductivity type different from the first conductivity type, that is connected to the second wiring and disposed so as to be opposed to the first region in a first direction;', 'a fourth region having the second conductivity type, that is connected to the third wiring and disposed so as to be opposed to the second region in the first direction, and the third and fourth regions serving as the other of an anode or a cathode of the diode; and', 'a fifth region having the second conductivity type,, 'the ESD protection circuit comprisesthe third region, the first region, the second region and the fourth region are disposed in this order in the first direction, andthe fifth region is disposed so as to be opposed to the ...

SCHOTTKY DIODE STRUCTURES AND INTEGRATION WITH III-V TRANSISTORS

Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed. 1. A semiconductor device , comprising:a Schottky stack including a first layer above a substrate, and a second layer above the first layer, wherein the first layer includes an III-V material, and the second layer is a polarization layer;a Schottky anode in contact with the second layer to form a Schottky barrier at an interface between the Schottky anode and the second layer of the Schottky stack; anda cathode through the second layer of the Schottky stack and in contact with the first layer of the Schottky stack, wherein a current is to flow from the Schottky anode through the Schottky barrier in a vertical direction orthogonal to a surface of the substrate, and vertically through the second layer to the first layer of the Schottky stack, following the first layer of the Schottky stack in a horizontal direction to the cathode.2. The semiconductor device of claim 1 , wherein the Schottky anode is partially embedded into the second layer of the Schottky stack.3. The semiconductor device of claim 1 , wherein the second layer of the Schottky stack includes a material selected from the group ...

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring connected to a signal terminal. Diffusion regions are separated in a whole part or one part of a range in a Y direction. That is, under first wiring, diffusion regions are only formed in parts opposed to diffusion regions formed under the second wiring and third wiring connected to a power supply terminal or a ground terminal, and a diffusion region is not formed in a central part in an X direction. Therefore, terminal capacity of the signal terminal can be reduced without causing ESD resistance to be reduced, in an ESD protection circuit with the signal terminal. 1. A semiconductor integrated circuit device having an ESD (Electro Static Discharge) protection circuit , wherein: a first wiring extending in a first direction and electrically connected to a first terminal;', 'a second wiring and a third wiring extending in the first direction, electrically connected to a power supply terminal or a ground terminal, and disposed on both sides of the first wiring respectively;', 'a first region and a second region having a first conductivity type, that are connected to and formed under the first wiring, the first and second regions being separated from each other and serving as one of an anode or a cathode;', 'a third region and a fourth region having a second conductivity type, that are connected to and formed under the second wiring, and the fourth region being disposed so as to be opposed to the first region in the second direction, the third and fourth regions being separated from each other and serving as the other of an anode or a cathode; and', 'a fifth region and a sixth region having the second conductivity type, that are connected to and formed under the third wiring, and the fifth region being disposed so as to be opposed to the second region in the second direction, the fifth and sixth regions being ...

DISPLAY DEVICE

To make the dimension of an electrostatic protection circuit small with the same maintained high in sensitivity. The electrostatic protection circuit is of the configuration that a first diode and a second diode are connected in series, wherein a semiconductor layer owned by each diode is configured to be sandwiched between a gate electrode and a conductive light shielding film. The light shielding film is formed to overlap with the semiconductor layer and has a wider area than the semiconductor layer. This results in having a gate covering the semiconductor layer from an upper side and a back gate covering the semiconductor layer from a lower side, so that the sensitivity can be maintained high irrespective of decreasing the electrostatic protection circuit in dimension. 1. A display device having a substrate and an electrostatic protection circuit formed on the substrate ,the electrostatic protection circuit having a configuration in which a first connection wire, a first diode, a third connection wire, a second diode, and a second connection wire are connected in series, and a third connection wire has a first terminal and a second terminal;whereinthe first diode has a first semiconductor layer and a first gate electrode, the first gate electrode has a first region connected to the third connection wire, and a second region overlapping the first semiconductor layer,the first diode has, as viewed in a cross-sectional view, a structure in which a first light shielding film is formed on the substrate, the first semiconductor layer is formed over the first light shielding film, and the second region of the first gate electrode layer is formed over the first semiconductor,the second diode has a second semiconductor layer and a second gate electrode, the second gate electrode has a third region connected to the third connection wire, and a fourth region overlapping the second semiconductor layer,the second diode has, as viewed in a cross-sectional view, a structure in ...

INTEGRATED CIRCUIT WITH TRIPLE GUARD WALL POCKET ISOLATION

A semiconductor device includes a substrate having a semiconductor surface doped a second dopant type with a buried layer (BL) doped a first dopant type. First, second and third well regions doped the second dopant type are on top of the BL. Second doped regions doped the first dopant type on top of and contacting the BL arraigned as a first well ring and second well ring are around the first and third well regions respectively. At least one high-injection component including the first well region is surrounded by the first well ring. At least one component including the third well region is surrounded by the second well ring. An npn or pnp guard wall pocket including a wall of the first and second well rings, and the second well region is between the high-injection component and the component. 1. A semiconductor device , comprising:a substrate having a semiconductor surface of a second dopant type with buried layer (BL) of a first dopant type;well regions of said second dopant type arranged as a first well region, a second well region, and a third well region on top of said BL;second doped regions of said first dopant type on top of and contacting said BL arranged as a first well ring and a second well ring around said first and said second well regions, respectively;a transistor within said first well region and surrounded by said first well ring;a diode within said second well region and surrounded by said second well ring, andan npn or pnp guard wall pocket including a wall of said second well ring, said third well region, and a wall of said first well ring between said transistor and said diode.2. The semiconductor device of claim 1 , wherein said first dopant type is n-type and said second dopant type is p-type.3. The semiconductor device of claim 1 , wherein said first dopant type is p-type and said second dopant type is n-type.4. The semiconductor device of claim 1 , wherein the first well region is surrounded by the first well ring but not the second well ...

TERMINATION STRUCTURE FOR INSULATED GATE SEMICONDUCTOR DEVICE AND METHOD

A semiconductor device structure includes a region of semiconductor material having an active region and a termination region. An active structure is disposed in the active region and a termination structure is disposed in the termination region. In one embodiment, the termination structure includes a termination trench and a conductive structure within the termination trench and electrically isolated from the region of semiconductor material by a dielectric structure. A dielectric layer is disposed to overlap the termination trench to provide the termination structure as a floating structure. A Schottky contact region is disposed within the active region. A conductive layer is electrically connected to the Schottky contact region and the first conductive layer extends onto a surface of the dielectric layer and laterally overlaps at least a portion of the termination trench. 1. A semiconductor device structure , comprising: a first conductivity type;', 'a first major surface;', 'a second major surface opposite to the first major surface;', 'an active region; and', 'a termination region;, 'a region of semiconductor material comprising a first active trench extending from the first major surface into the region of semiconductor material to a first depth; and', 'a first conductive structure within the first active trench and electrically isolated from the region of semiconductor material by a first dielectric structure, wherein the first active trench has a first width proximate to the first major surface;, 'an active structure disposed in the active region comprising a first termination trench extending from the first major surface into the region of semiconductor material to a second depth;', [ a second width proximate to the first major surface;', 'a first side surface;', 'a second side surface opposite to the first side surface; and', 'a first lower surface extending between the first side surface and the second side surface;, 'the first termination trench ...

COMPENSATED WELL ESD DIODES WITH REDUCED CAPACITANCE

An integrated circuit with a shallow trench isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode in parallel with a shallow trench isolated, low capacitance, ESD protection diode. 1. An integrated circuit , comprising:a p-type substrate;a pwell formed in said p-type substrate where doping of said pwell is higher than doping of said p-type substrate;an NMOS transistor with a NMOS transistor gate and with N+ doped deep source and drain diffusions formed in a pwell on said p-type substrate;a first nwell formed in said p-type substrate;a PMOS transistor with a PMOS transistor gate and with P+ doped deep source and drain diffusions formed in said first nwell;an ESD diode gate which isolates a N+ deep diffusion from a P+ deep diffusion where said N+ deep diffusion and said N+ doped deep source and drain diffusion doping concentrations are equal and where said P+ deep diffusion and said P+ deep source and drain diffusion doping concentrations are equal; a diode formed between said N+ deep diffusion and said p-type substrate', 'a diode formed between a second nwell and an isolated pwell where said isolate pwell is formed in said second nwell;', 'a diode formed between a counter doped nwell N− diffusion and said p-type substrate; and', 'a diode formed between said counter doped nwell N− diffusion and said isolated pwell, 'a low capacitance GS ESD diode selected from the group consisting ofwhere said N+ deep diffusion is a cathode of said low capacitance GS ESD diode; andwhere said P+ deep diffusion is an anode of said low capacitance GS ESD diode.2. The integrated circuit of where said low capacitance GS ESD diode is a GS ESD P/N diode claim 1 , where said p-type substrate is under said N+ deep diffusion claim 1 , where said pwell is under said P+ deep diffusion claim 1 , where said low capacitance GS ESD ...

SEMICONDUCTOR DEVICE, POWER MODULE, AND CONTROL METHOD OF POWER CONVERSION DEVICE

The junction temperature of a field effect transistor is detected with a higher degree of accuracy than in the past. A semiconductor device controls multiple field effect transistors that configure a power conversion device, and includes a differential amplifier and a controller that controls ON/OFF of the multiple field effect transistors. The differential amplifier detects the potential difference between a source and a drain of a field effect transistor that is controlled in the OFF state by the controller and that induces an electric current flowing through the body diode thereof, among the multiple field effect transistors. 1. A semiconductor device to control a plurality of field effect transistors configuring a power conversion device ,wherein each of the field effect transistors includes a body diode,wherein the power conversion device comprises:a first power supply node and a second power supply node to supply mutually different reference potentials;a first coupling node to couple to a load;a first field effect transistor coupled between the first power supply node and the first coupling node; anda second field effect transistor coupled between the second power supply node and the first coupling node, andwherein the semiconductor device comprises:a controller to control ON/OFF of each of the field effect transistors configuring the power conversion device by pulse width control; anda differential amplifier to detect the potential difference between the first coupling node and the first power supply node.2. The semiconductor device according to claim 1 ,wherein, in a first period, the controller sets the first field effect transistor to an OFF state and the second field effect transistor to an ON state, to make a current flow between the first power supply node and the second power supply node through the load and the second field effect transistor,wherein, in a second period following the first period, the controller sets both of the first field effect ...

SEMICONDUCTOR DEVICE

A first ESD protection circuit is provided between a first high-potential side power supply and a first low-potential side power supply of a first power supply system and a second ESD protection circuit is provided between a second high-potential side power supply and a second low-potential side power supply of a second power supply system. A coupling circuit includes a bidirectional diode and couples the first and second low-potential side power supplies. A first transistor is composed of an n-channel MOS transistor, has a drain coupled to the first high-potential side power supply of the first power supply system, and has a back gate coupled to the second low-potential side power supply of the second power supply system. A resistor element is inserted in series between the drain of the first transistor and the first high-potential side power supply. 1. A semiconductor device including a first power supply system composed of a first high-potential side power supply and a first low-potential side power supply and a second power supply system composed of a second high-potential side power supply and a second low-potential side power supply , the semiconductor device comprising:a first ESD protection circuit provided between the first high-potential side power supply and the first low-potential side power supply and configured to absorb an input surge;a second ESD protection circuit provided between the second high-potential side power supply and the second low-potential side power supply and configured to absorb an input surge;a coupling circuit including a bidirectional diode and configured to couple the first low-potential side power supply and the second low-potential side power supply;a first transistor composed of an n-channel MOS transistor, having a drain coupled to the first high-potential side power supply, and having a back gate coupled to the second low-potential side power supply; anda first resistor element inserted in series between the drain of the ...

ELECTROSTATIC DISCHARGE DEVICES AND METHOD OF MAKING THE SAME

In one embodiment, electrostatic discharge (ESD) devices are disclosed. 1. An ESD device comprising:a semiconductor substrate of a first conductivity type;a first semiconductor region of the first conductivity type, wherein the first semiconductor region overlays substantially all of the semiconductor substrate;a first doped region of a second conductivity type, wherein the first doped region and the first semiconductor region together form a zener diode;a second semiconductor region of the second conductivity type disposed on a portion of the first semiconductor region and disposed on a portion of the first doped region, wherein a peak doping concentration of the second semiconductor region is less than a peak doping concentration of the semiconductor substrate;a second doped region of the first conductivity type disposed in the second semiconductor region and overlying the first doped region, wherein the second doped region is a least two microns apart from the first semiconductor region;a third doped region of the second conductivity type disposed in the second semiconductor region and overlying the first semiconductor region, wherein the third doped region is spaced at least two microns from the first semiconductor region;a fourth doped region of the first conductivity type disposed in the second semiconductor region and overlying the third doped region, wherein the third doped region, the fourth doped region, and the first semiconductor region together form a P-N-P junction; anda first isolation trench extending from a top surface of the second semiconductor region and into the first semiconductor region, wherein the first isolation trench surrounds an outside perimeter of the second doped region and at least a portion of the first doped region, and wherein the first isolation trench does not surround the third doped region or the fourth doped region.2. The ESD device of claim 1 , wherein the first conductivity type is a P-type conductivity and the second ...

SEMICONDUCTOR DEVICE

A semiconductor device includes first and second pads separated from each other, first and second test elements connected to the first and second pads and connected to each other in parallel between the first and second pads, a first diode connected to the first test element in series, and a second diode connected to the second test element in series. 1. A semiconductor device , comprising:first and second pads separated from each other;first and second test elements connected to the first and second pads and connected to each other in parallel between the first and second pads;a first diode connected to the first test element in series; anda second diode connected to the second test element in series.2. The semiconductor device as claimed in claim 1 , wherein the first diode is to be turned on and the second diode is to be turned off when a voltage greater than a voltage supplied to the second pad is supplied to the first pad.3. The semiconductor device as claimed in claim 2 , wherein a level of current flowing from the first pad to the second pad based on the greater voltage indicates that the first test element is defective.4. The semiconductor device as claimed in claim 1 , wherein the first diode is to be turned off and the second diode is to be turned on when a voltage greater than a voltage supplied to the first pad is supplied to the second pad.5. The semiconductor device as claimed in claim 4 , wherein a level of current flowing from the second pad to the first pad based on the greater voltage indicates that the second test element is defective.6. The semiconductor device as claimed in claim 1 , wherein:the first diode is connected between the first pad and the first test element, andthe second diode is connected between the first pad and the second test element.7. The semiconductor device as claimed in claim 6 , wherein:the first diode includes an anode connected to the first pad and a cathode connected to the first test element, andthe second diode ...

SIGNAL TRANSMISSION DEVICE

This invention, is concerning a signal voltage device, in which transformers and a reception circuit are formed on the same chip, and accordingly, no ESD protective element connected to a transformer connection terminal of the reception circuit is required, and negative pulses generated in reception-side inductors can be used in signal transmission. Signal transmission using both positive pulses and negative pulses is made possible as a result, and a stable signal transmission operation can be carried out even in a case where delay time varies in a signal detection circuit. Further, a reception circuit of low power consumption can be configured by using a single-ended Schmitt trigger circuit in the signal detection circuit. 16-. (canceled)7. A signal transmission device , comprising:a transmission circuit that operates with power from a first power supply and generates a transmission signal based on an input signal;a transformer that is connected to the transmission circuit; anda reception circuit that operates with power from a second power supply and receives via the transformer the transmission signal output ted by the transmission circuit, wherein the transformer comprises two transformers, which are a first transformer and a second transformer, each of the transformers being made up of a transmission-side inductor and a reception-side inductor;the transmission circuit inputs a transmission-side voltage signal, made up of one or a plurality of pulses, to a transmission terminal of the transmission-side inductor of the first transformer, in synchronization with a rising edge of the input signal, and inputs a transmission-side voltage signal, made up of one or a plurality of pulses, to a transmission terminal of the transmission-side inductor of the second transformer, in synchronization with a falling edge of the input signal;one terminal of two terminals of each of the reception-side inductors of the first and second transformers is connected to the second power ...

ELECTROSTATIC DISCHARGE (ESD) PROTECTION STRUCTURE UTILIZING FLOOR PLAN DESIGN TO PROTECT INTEGRATED CIRCUIT FROM ESD EVENT, AND RELATED INTEGRATED CIRCUIT AND ESD PROTECTION METHOD

An electrostatic discharge protection (ESD) structure for protecting a core circuit of an integrated circuit from an ESD event received by a conductive pad of the integrated circuit is provided. The ESD protection structure includes a first conductive layer, a clamp device, a first electrical connection part and a second electrical connection part. The first conductive layer is formed below the conductive pad, and includes a first conductive portion, an insulating portion and a second conductive portion. The insulating portion is surrounded by the first conductive portion and the second conductive portion. The first conductive portion is electrically connected between the conductive pad and the second conductive portion. The clamp device is arranged for clamping the ESD event. The first electrical connection part is coupled between the first conductive portion and the clamp device. The second electrical connection part is coupled between the second conductive portion and the core circuit. 1. An electrostatic discharge (ESD) protection structure for protecting a core circuit of an integrated circuit from an ESD event received by a conductive pad of the integrated circuit , the ESD protection structure comprising:a first conductive layer, formed below the conductive pad, wherein the first conductive layer comprises a first conductive portion, an insulating portion and a second conductive portion, the insulating portion is surrounded by the first conductive portion and the second conductive portion, and the first conductive portion is electrically connected between the conductive pad and the second conductive portion;a clamp device, for clamping the ESD event;a first electrical connection part, coupled between the first conductive portion of the first conductive layer and the clamp device; anda second electrical connection part, coupled between the second conductive portion of the first conductive layer and the core circuit.2. The ESD protection structure of claim 1 , ...

TRANSIENT VOLTAGE SUPRESSOR WITH A PUNCH-THROUGH SILICON CONTROLLED RECTIFIER LOW-SIDE STEERING DIODE

A transient voltage suppressor (TVS) device uses a punch-through silicon controlled rectifier (SCR) structure for the low-side steering diode where the punch-through SCR structure realizes low capacitance at the protected node. In some embodiments, the punch-through silicon controlled rectifier of the low-side steering diode includes a first doped region formed in a first epitaxial layer, a first well formed spaced apart from the first doped region where the first well is not biased to any electrical potential, and a second doped region formed in the first well. The first doped region, the first epitaxial layer, the first well and the second doped region form the punch-through silicon controlled rectifier, with the first doped region forming the anode and the second doped region forming the cathode of the punch-through silicon controlled rectifier. 1. A transient voltage suppressing (TVS) device comprising:a semiconductor layer comprising a first epitaxial layer of a first conductivity type;a plurality of active regions formed in the semiconductor layer, the active regions being isolated from each other by isolation structures;a high-side steering diode formed in a first active region and having an anode terminal coupled to a first protected node and a cathode terminal;a low-side steering diode formed in a second active region of the plurality of active regions and having a cathode terminal coupled to a second protected node and an anode terminal; wherein the low-side steering diode comprises a punch-through silicon controlled rectifier, the punch-through silicon controlled rectifier comprising:a first doped region of a second conductivity type, opposite the first conductivity type, formed in the first epitaxial layer;a first well of the second conductivity type formed in the first epitaxial layer spaced apart from the first doped region, wherein the first well is not biased to any electrical potential; anda second doped region of the first conductivity type formed ...

ON-CHIP MULTIPLE-STAGE ELECTRICAL OVERSTRESS (EOS) PROTECTION DEVICE

An on-chip multiple-stage electrical overstress (EOS) protection device is disclosed. The protection device includes a surge protector having a first clamping voltage and a first electrostatic discharge (ESD) protector having a second clamping voltage lower than the first clamping voltage. The surge protector is electrically connected to the first ESD protector in parallel. The surge protector and the first ESD protector are electrically connected between a receiving terminal and a voltage terminal, and the receiving terminal is electrically connected to an internal circuit. When an electrical overstress (EOS) signal including an electrostatic discharge (ESD) signal and a surge signal appears at the receiving terminal, the first ESD protector and the surge protector are triggered on in turn to clamp a voltage received by the internal circuit. 1. An on-chip multiple-stage electrical overstress (EOS) protection device comprising:a surge protector having a first clamping voltage; anda first electrostatic discharge (ESD) protector having a second clamping voltage lower than the first clamping voltage, the surge protector is electrically connected to the first ESD protector in parallel, the surge protector and the first ESD protector are electrically connected between a receiving terminal and a voltage terminal, the receiving terminal is electrically connected to an internal circuit, and when an electrical overstress (EOS) signal comprising an electrostatic discharge (ESD) signal and a surge signal appears at the receiving terminal, the first ESD protector and the surge protector are triggered on in turn to clamp a voltage received by the internal circuit.2. The on-chip multiple-stage EOS protection device according to claim 1 , wherein the receiving terminal is an input/output (I/O) port claim 1 , the voltage terminal is a low-voltage terminal claim 1 , and the internal circuit is electrically connected to the low-voltage terminal and a high-voltage terminal.3. The on- ...

Electrostatic Discharge (ESD) Diode in FinFET Technology

In an embodiment, an ESD protection circuit is provided in which diodes may be formed between N+ and P+ diffusions within an insulated semiconductor region and in which additional diodes may be formed between adjacent insulated regions of opposite conduction type as well. The diodes may be used in parallel to form an ESD protection circuit, which may have low on resistance and may sink high ESD current per unit area. To support the formation of the ESD protection circuit, each silicon region may have alternating N+ and P+ diffusions, and adjacent silicon regions may have N+ and P+ diffusions alternating in opposite locations. That is a perpendicular drawn between the N+ diffusions of one adjacent region may intersect P+ diffusions in the other adjacent region, and vice versa.

THREE-DIMENSIONAL ELECTROSTATIC DISCHARGE SEMICONDUCTOR DEVICE

Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.

THREE-DIMENSIONAL ELECTROSTATIC DISCHARGE SEMICONDUCTOR DEVICE

Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.

PREPARATION METHOD FOR SEMICONDUCTOR DEVICE

The present application relates to a preparation method for a semiconductor device, comprising: sequentially forming an isolating dielectric layer and a doped semiconductor layer of a first conductivity type on a non-primitive cell area of a semiconductor substrate; performing a first conductivity type of well injection by using the semiconductor layer and the isolating dielectric layer as masks, and forming a well area in a primitive cell area; forming an operation structure in the well area, and forming a protection structure in the semiconductor layer; and forming an interlayer dielectric layer on the operation structure and the protection structure, forming a contact hole in the interlayer dielectric layer, forming a metal interconnection layer connected to the contact hole on the interlayer dielectric layer, and connecting the operation structure and the protection structure by means of the metal interconnection layer and the contact hole. 1. A method for manufacturing a semiconductor device , the semiconductor device comprising a work structure and a protection structure configured to protect the work structure , the method comprising:providing a semiconductor substrate comprising a cell region and a non-cell region, forming an isolation dielectric layer on the non-cell region of the semiconductor substrate, and forming a semiconductor layer having a first-conductivity-type doping on the isolation dielectric layer;performing a first-conductivity-type well implantation to the semiconductor substrate by using the semiconductor layer and the isolation dielectric layer as masks, and forming a well region in the cell region of the semiconductor substrate;doping the well region to form the work structure in the cell region, and doping the semiconductor layer to form the protection structure on the non-cell region; andforming an interlayer dielectric layer on the work structure and the protection structure, forming a contact hole in the interlayer dielectric layer, ...

Electrostatic discharge devices and method of making the same

In one embodiment, electrostatic discharge (ESD) devices are disclosed.

INTEGRATED CIRCUIT STRUCTURE WITH AVALANCHE JUNCTION TO DOPED SEMICONDUCTOR OVER SEMICONDUCTOR WELL

Embodiments of the disclosure provide an integrated circuit (IC) structure, including a doped well in a semiconductor substrate, in addition to a base region, emitter region, and collector region in the doped well. An insulative material is within the doped well, with a first end horizontally adjacent the collector region and a second end opposite the first end. A doped semiconductor region is within the doped well adjacent the second end of the insulative material. The doped semiconductor region is positioned to define an avalanche junction between the collector region and the doped semiconductor region across the doped well. 1. An integrated circuit (IC) structure , comprising:a doped well in a semiconductor substrate, the doped well having a first doping type;a base region within the doped well, and having the first doping type;an emitter region within the doped well and having a second doping type opposite the first doping type;a first insulator within the doped well, horizontally between the base region and the emitter region;a collector region within the doped well and having the second doping type;a second insulator within the doped well, horizontally between the collector region and the emitter region;an insulative material within the doped well, the insulative material having a first end horizontally adjacent the collector region and a second end opposite the first end; anda doped semiconductor region within the doped well adjacent the second end of the insulative material, wherein the doped semiconductor region is of the first doping type, such that an avalanche junction is defined between the collector region and the doped semiconductor region across the doped well.2. The IC structure of claim 1 , wherein the insulative material comprises a nitride having a depth below an upper surface of the doped well that is less than a depth of the collector region and a depth of the doped semiconductor region below an upper surface of the doped well.3. The IC ...

INTEGRATED CIRCUIT WITH ELECTROSTATIC DISCHARGE PROTECTION

An integrated circuit includes an input/output (I/O) pad, an electrostatic discharge (ESD) primary circuit and a bias voltage generator. The electrostatic discharge primary circuit includes a first transistor. A first terminal of the first transistor is coupled to the I/O pad. The bias voltage generator is configured to provide a gate bias signal to the gate terminal of the first transistor. The bias voltage generator provides the gate bias signal at a first voltage level in response to that an ESD event occurs on the I/O pad. The bias voltage generator provides the gate bias signal at a second voltage level in response to that no ESD event occurs on the I/O pad. The first voltage level is lower than the second voltage level. 1. An integrated circuit , comprising:an input/output (I/O) pad;an electrostatic discharge (ESD) primary circuit comprising a first transistor, wherein a first terminal of the first transistor is coupled to the I/O pad; anda bias voltage generator configured to provide a gate bias signal to a gate terminal of the first transistor, wherein the bias voltage generator provides the gate bias signal at a first voltage level in response to that an ESD event occurs on the I/O pad, and the bias voltage generator provides the gate bias signal at a second voltage level in response to that no ESD event occurs on the I/O pad, the first voltage level is lower than the second voltage level.2. The integrated circuit of claim 1 , wherein a second terminal of the first transistor is coupled to a first reference voltage pin claim 1 , in response to that the ESD event occurs on the I/O pad claim 1 , a voltage level on the I/O pad exceeds a threshold voltage of the ESD primary circuit claim 1 , and the ESD primary circuit is activated to guide an ESD current from the I/O pad through the ESD primary circuit to the first reference voltage pin.3. The integrated circuit of claim 2 , wherein the ESD primary circuit further comprises a second transistor claim 2 , a ...

DESIGN AND MANUFACTURE OF POWER DEVICES HAVING INCREASED CROSS OVER CURRENT

An embodiment relates to a n-type planar gate DMOSFET comprising a Silicon Carbide (SiC) substrate. The SiC substrate includes a N+ substrate, a N− drift layer, a P-well region and a first N+ source region within each P-well region. A second N+ source region is formed between the P-well region and a source metal via a silicide layer. During third quadrant operation of the DMOSFET, the second N+ source region starts depleting when a source terminal is positively biased with respect to a drain terminal. The second N+ source region impacts turn-on voltage of body diode regions of the DMOSFET by establishing short-circuitry between the P-well region and the source metal when the second N+ source region is completely depleted. 1. A device comprising a unit cell on a Silicon Carbide (SiC) substrate , the unit cell comprising:a first conductivity type source region;a second conductivity type well contact region;a second conductivity type well region;a first metal region; anda silicide layer,wherein the device comprises a vertical Silicon Carbide double-implantation metal oxide semiconductor field-effect transistor (DMOSFET) comprising a drain terminal on a backside of the SiC substrate and a source terminal on a topside of the SiC substrate,wherein the first metal region is in contact with the second conductivity type well contact region, andwherein the silicide layer is in contact with the second conductivity type well contact region through the first metal region.2. The device of claim 1 , wherein the first metal region comprises a target work function.3. The device of claim 2 , wherein the target work function ranges from 3.5 electron volts to 6 electron volts.4. The device of claim 1 , wherein a first conductivity type region comprises one of (a) a p-type region and (b) a n-type region.5. The device of claim 1 , wherein a second conductivity type region comprises one of (a) a p-type region and (b) a n-type region.6. The device of claim 4 , wherein the first ...

DESIGN AND MANUFACTURE OF POWER DEVICES HAVING INCREASED CROSS OVER CURRENT

An embodiment relates to a n-type planar gate DMOSFET comprising a Silicon Carbide (SiC) substrate. The SiC substrate includes a N+ substrate, a N− drift layer, a P-well region and a first N+ source region within each P-well region. A second N+ source region is formed between the P-well region and a source metal via a silicide layer. During third quadrant operation of the DMOSFET, the second N+ source region starts depleting when a source terminal is positively biased with respect to a drain terminal. The second N+ source region impacts turn-on voltage of body diode regions of the DMOSFET by establishing short-circuitry between the P-well region and the source metal when the second N+ source region is completely depleted. 1. A device comprising a unit cell on a Silicon Carbide (SiC) substrate , the unit cell comprising:a first conductivity type source region;a second conductivity type well region;a second conductivity type well contact region; anda silicide layer,wherein the device comprises a vertical Silicon Carbide double-implantation metal oxide semiconductor field-effect transistor (DMOSFET) comprising a drain terminal on a backside of the SiC substrate and a source terminal on a topside of the SiC substrate,wherein a lateral extent of the second conductivity type well contact region varies with a non-zero value in direction orthogonal to the unit cell,wherein the second conductivity type well contact region is located adjacent and contiguous between the first conductivity type source region in a lateral direction, andwherein the second conductivity type well contact region is located between the silicide layer and the second conductivity type well region in a vertical direction.2. The device of claim 1 , wherein the second conductivity type well contact region comprises a periodic contact with a source metal region via the silicide layer between an adjacent interlayer dielectric (ILD) region.3. The device of claim 1 , wherein the second conductivity type well ...

Design and manufacture of power devices having increased cross over current

An embodiment relates to a n-type planar gate DMOSFET comprising a Silicon Carbide (SiC) substrate. The SiC substrate includes a N+ substrate, a N− drift layer, a P-well region and a first N+ source region within each P-well region. A second N+ source region is formed between the P-well region and a source metal via a silicide layer. During third quadrant operation of the DMOSFET, the second N+ source region starts depleting when a source terminal is positively biased with respect to a drain terminal. The second N+ source region impacts turn-on voltage of body diode regions of the DMOSFET by establishing short-circuitry between the P-well region and the source metal when the second N+ source region is completely depleted.

Design and manufacture of power devices having increased cross over current

An embodiment relates to a n-type planar gate DMOSFET comprising a Silicon Carbide (SiC) substrate. The SiC substrate includes a N+ substrate, a N− drift layer, a P-well region and a first N+ source region within each P-well region. A second N+ source region is formed between the P-well region and a source metal via a silicide layer. During third quadrant operation of the DMOSFET, the second N+ source region starts depleting when a source terminal is positively biased with respect to a drain terminal. The second N+ source region impacts turn-on voltage of body diode regions of the DMOSFET by establishing short-circuitry between the P-well region and the source metal when the second N+ source region is completely depleted.

Crystal oscillator with electrostatic discharge (esd) compliant drive level limiter

A crystal oscillator may be configured to limit crystal drive level in the crystal oscillator by clamping via a diode-resistor branch, voltage applied to a drain pad of the crystal oscillator. The crystal oscillator may incorporate Pierce crystal oscillator based implementation. The crystal oscillator may comprise an on-chip main branch, comprising at least one transistor element; an on-chip drain branch connecting the main branch to a drain pad; an on-chip gate branch connecting the main branch to a gate pad. The diode-resistor branch may be connected to the drain branch, and may comprise at least one diode and at least one resistor element. The at least one diode and the at least one resistor element may be connected in series in the diode-resistor branch. The clamped voltage may be applied from an off-chip drain node, through the drain pad.

Electrostatic discharge protection structure and fabrication method thereof

A method is provided for fabricating an electrostatic discharge (ESD) protection structure. The method includes forming a substrate having a first region and a second region, wherein the first region and the second region have a preset distance; forming a well area in the substrate; forming a first fin portion in the substrate in the first region and a second fin portion in the substrate in the second region; forming a supporting gate structure, wherein the supporting gate structure includes a first supporting gate crossing the first fin portion and a second supporting gate crossing the second fin portion; forming a dielectric layer on the well area; and forming a conductive structure in the dielectric layer, wherein the conductive structure includes a first conductive structure connecting to the first fin portion and a second conductive structure connecting to the second fin portion.

Optoelectronic semiconductor device and fabrication method thereof

An optoelectronic semiconductor includes a carrier, a semiconductor main body having a first semiconductor layer, a second semiconductor layer, and a radiation emitting layer for generating electromagnetic radiation, the semiconductor main body having at least one recess extending through the radiation emitting layer; a first electrode and a second electrode; a first electrical connection layer electrically connected between the first semiconductor layer and the first electrode; a second electrical connection layer electrically connected between the second semiconductor layer and the second electrode and extending through the recess from the carrier to the second semiconductor layer; and a zener diode structure disposed between the first electrical connection layer and the second electrical connection layer so that the first electrical connection layer and the second electrical connection layer are electrically dependent, wherein at least a portion of the zener diode structure is located in a current path between the first electrode and the second electrode.

Semiconductor Device and Method for Forming the Semiconductor Device

A semiconductor device and a method for forming the semiconductor device. The semiconductor device includes: a unipolar component at least including a first epitaxial layer and a first substrate; and a bypass component at least including a second epitaxial layer and a second substrate; the unipolar component and the bypass component are connected in parallel; a difference of a thickness of the unipolar component and a thickness of the bypass component is lower than or equal to a predetermined value. 1. A semiconductor device , comprising:a unipolar component at least comprising a first epitaxial layer and a first substrate, wherein a source electrode of the unipolar component is an aluminum silicon type element; anda bypass component at least comprising a second epitaxial layer and a second substrate, wherein a barrier metal of the bypass component is a titanium or molybdenum type element; the unipolar component and the bypass component are connected in parallel;wherein a difference of a first thickness and a second thickness is lower than or equal to 10% and higher than or equal to −10%;the first thickness is an addition of the thickness of the first epitaxial layer and the thickness of the first substrate, the second thickness is an addition of the thickness of the second epitaxial layer and the thickness of the second substrate.2. The semiconductor device according to claim 1 , wherein the unipolar component and the bypass component comprise silicon carbide material.3. (canceled)4. The semiconductor device according to claim 1 , wherein a difference of a first concentration and a second concentration is lower than or equal to 10% and higher than or equal to −10%;the first concentration is a concentration of carriers in the first epitaxial layer, and the second concentration is a concentration of carriers in the second epitaxial layer.5. (canceled)6. A method for forming a semiconductor device claim 1 , comprising:providing a unipolar component at least comprising ...

DIODE DESIGN ON FINFET DEVICE

An electrostatic discharge (ESD) protection device includes a semiconductor substrate including a first region of a first conductivity type and a second region of a second conductivity type opposite the first conductivity type, the first region and the second region being adjacent to each other and forming a pn junction in the semiconductor substrate, a semiconductor fin on the semiconductor substrate, and an electrode on the semiconductor fin. The pn junction in the semiconductor substrate has a relatively large area to prevent local hot spots from occurring when a current flows through the ESD protection device, thereby reducing performance degradation of a semiconductor device. 1. A semiconductor device , comprising:a semiconductor substrate including a first region of a first conductivity type and a second region of a second conductivity type opposite the first conductivity type, the first region and the second region the first region and the second region being adjacent to each other and forming a pn junction in the semiconductor substrate;a first semiconductor fin and a second semiconductor fin on the semiconductor substrate, the first and second semiconductor fins being separated from each other, a trench formed around the first and second semiconductor fins;a first insulator layer partially filled the trench, the first insulator layer including a first portion around the first semiconductor fin and a second portion around the second semiconductor fin, the first portion having an upper surface lower than an upper surface of the second portion;an electrode on the first semiconductor fin; anda source and a drain on the second semiconductor fin.2. The semiconductor device of claim 1 , wherein the second region has a doping concentration greater than a doping concentration of the first region.3. The semiconductor device of claim 1 , wherein the first semiconductor fin is on the second region.4. The semiconductor device of claim 1 , wherein the first conductivity ...

ELECTROSTATIC DISCHARGE CLAMP STRUCTURES

The present disclosure generally relates to semiconductor structures and, more particularly, to electrostatic discharge clamp structures and methods of manufacture. The structure includes: a network of clamps; sense elements in series with the clamps and configured to sense a turn-on of at least one clamp of the network of clamps; and feedback elements connected to the clamps to facilitate triggering of remaining clamps of the network of clamps. 1. A circuit structure , comprising:a network of clamps;sense elements in series with the clamps and configured to sense a turn-on of at least one clamp of the network of clamps; andfeedback elements connected to the clamps to facilitate triggering of remaining clamps of the network of clamps.2. The circuit structure of claim 1 , wherein the clamps are silicon controlled rectifier (SCR) clamps.3. The structure of claim 1 , wherein the sense elements comprise diodes.4. The structure of claim 1 , wherein the sense elements comprise resistors.5. The structure of claim 1 , wherein the sense elements comprise a differential amplifier.6. The structure of claim 1 , wherein the feedback elements comprise a triggering circuit.7. The structure of claim 6 , wherein the triggering circuit is a resistor-capacitor (RC) triggering circuit.8. The structure of claim 7 , wherein each clamp is 0.6 amps.9. A circuit structure claim 7 , comprising:a network of silicon controlled rectifier (SCR) clamps;a passive element directly connected to at least one SCR clamp;a sensing amplifier directly connected to the passive element; anda triggering circuit connected to the at least one SCR clamp to facilitate triggering of the at least one SCR clamp.10. The structure of claim 9 , wherein the passive element is a diode or a resistor.11. The structure of claim 10 , wherein the sensing amplifier is a differential amplifier.12. The structure of claim 11 , wherein a current difference between the diode or the resistor and the at least one SCR clamp is sensed ...

BIAS TECHNIQUES AND CIRCUIT ARRANGEMENTS TO REDUCE LEAKAGE CURRENT IN A CIRCUIT

An apparatus includes an input/output (I/O) pin and an electrostatic discharge device. The electrostatic discharge device is coupled to the I/O pin and to a voltage regulator. 1. A method comprising:providing a discharge current path between an input/output (I/O) pin and an output node of a voltage regulator; andproviding a second discharge current path between the output node and a ground pin.2. The method of claim 1 , further comprising selectively coupling the voltage regulator to a supply voltage by controlling a pull-up transistor and a pull-down transistor.3. The method of claim 2 , wherein the pull-up transistor and the pull-down transistor are included in a head switch coupled to the voltage regulator.4. The method of claim 1 , selectively coupling the voltage regulator to a supply voltage via a head switch claim 1 , the head switch including a first transistor having a first oxide thickness that is greater than a second oxide thickness of a second transistor of circuitry claim 1 , the circuitry powered by the voltage regulator.5. The method of claim 4 , wherein the supply voltage is selectively coupled to the voltage regulator based on an enable signal.6. The method of claim 4 , wherein the circuitry includes a device to protect from electrostatic discharge.7. The method of claim 1 , wherein the discharge current path includes a first diode claim 1 , and wherein the second discharge current path includes an electrostatic discharge device.8. The method of claim 7 , further comprising disabling a clamp circuit of the electrostatic discharge device responsive to an enable signal.9. The method of claim 1 , further comprising providing a third discharge current path between the I/O pin and the ground pin.10. The method of claim 9 , wherein the discharge current path includes a first diode claim 9 , wherein the second discharge current path includes an electrostatic discharge device claim 9 , and wherein the third discharge current path includes a second diode.11 ...

SEMICONDUCTOR ESD PROTECTION CIRCUIT

A semiconductor device includes a Zener diode having an anode layer and a cathode layer. The Zener diode provides an electrostatic discharge (ESD) path for ESD signals. At least two channel diodes are coupled to the ESD path of the Zener diode. Each of the channel diodes includes a common cathode layer and a separate anode region. The common cathode layer of the channel diodes is disposed on the cathode layer of the Zener diode. At least two channels are provided where each channel is coupled to one of the separate anode regions to provide an electrical connection for protected signal paths to the ESD path. 1. A semiconductor device comprising:a Zener diode comprising an anode layer and a cathode layer, the Zener diode provides an electrostatic discharge (ESD) path for ESD signals;at least two channel diodes coupled to the ESD path of the Zener diode, each of the channel diodes includes a common cathode layer and a separate anode region, the common cathode layer of the channel diodes being disposed on the cathode layer of the Zener diode; andat least two channels, each channel coupled to one of the separate anode regions to provide an electrical connection for protected signal paths to the ESD path.2. The semiconductor device of claim 1 , wherein the anode layer of the Zener diode is a P-doped substrate layer.3. The semiconductor device of claim 2 , wherein the cathode layer is an N-doped buried layer (NBL) that is ion implanted on the anode layer.4. The semiconductor device of claim 3 , wherein a doping level of the NBL is within a range of about 1E17 to about 2E18 per cubic centimeter of the NBL to mitigate vertical parasitic leakage paths between the channel diodes and the Zener diode.5. The semiconductor device of claim 1 , wherein the common cathode layer is grown as an N-doped epitaxial layer (NEPI) on to the cathode layer of the Zener diode.6. The semiconductor device of claim 5 , wherein a doping level of the NEPI layer is doped such that the resistivity ...

CASCODE CONFIGURED SEMICONDUCTOR COMPONENT AND METHOD

In accordance with an embodiment, semiconductor component having a compound semiconductor material based semiconductor device connected to a silicon based semiconductor device and a protection element, wherein the silicon based semiconductor device is a transistor. The protection element is coupled in parallel across the silicon based semiconductor device and may be a resistor, a diode, or a transistor. In accordance with another embodiment, the silicon based semiconductor device is a diode. The compound semiconductor material may be shorted to a source of potential such as, for example, ground, with a shorting element. 1. A semiconductor component having at least first and second terminals , comprising:a first semiconductor device having first and second current carrying terminals, the first semiconductor device configured from a silicon based material;a second semiconductor device having a control terminal and first and second current carrying terminals, the second semiconductor device configured from a III-N semiconductor material, the first current carrying terminal of the first semiconductor device coupled to a second current carrying terminal of the second semiconductor device, and the control terminal of the second semiconductor device coupled to the second current carrying terminal of the first semiconductor device; anda third semiconductor device having a control terminal and first and second current carrying terminals, the first current carrying terminal of the third semiconductor device coupled to the control terminal of the third semiconductor device, to the first current carrying terminal of the first semiconductor device, and to the second current carrying terminal of the second semiconductor device.2. The semiconductor component of claim 1 , wherein the first semiconductor device is a first transistor claim 1 , the second semiconductor device is a second transistor claim 1 , the third semiconductor device is a third transistor and the silicon based ...

CASCODE CONFIGURED SEMICONDUCTOR COMPONENT

In accordance with an embodiment, semiconductor component includes a compound semiconductor material based semiconductor device coupled to a silicon based semiconductor device and a protection element, wherein the silicon based semiconductor device is a transistor. The protection element is coupled in parallel across the silicon based semiconductor device and may be a resistor, a diode, or a transistor. In accordance with another embodiment, the silicon based semiconductor device is a diode. The compound semiconductor material may be shorted to a source of potential such as, for example, ground, with a shorting element. 1. A semiconductor component having at least first and second terminals , comprising:a first semiconductor device having first and second current carrying terminals, the first semiconductor device configured from a silicon based material;a second semiconductor device having a control terminal, first and second current carrying terminals, and a body terminal, the second semiconductor device configured from a III-N semiconductor material, the first current carrying terminal of the first semiconductor device coupled to the second current carrying terminal of the second semiconductor device, the control terminal of the second semiconductor device coupled to the second current carrying terminal of the first semiconductor device, and the body terminal of the second semiconductor device connected to the second current carrying terminal of the first semiconductor device; anda protection element having first and second terminals, the first terminal of the protection element coupled to the first current carrying terminal of the first semiconductor device and to the second current carrying terminal of the second semiconductor device.2. The semiconductor component of claim 1 , wherein the first semiconductor device is a first transistor claim 1 , the second semiconductor device is a second transistor claim 1 , and the silicon based semiconductor material is ...

DISPLAY DEVICE

A display device according to one aspect of the present invention includes a plurality of scanning lines () and a plurality of signal lines (); a plurality of pixel thin-film transistors; a common scanning interconnect (); and a plurality of protective diodes () (protective elements). At least a part of a plurality of connecting interconnects that electrically connect the common scanning interconnect with the plurality of protective diodes are constituted by connecting interconnects () on the same layer as the signal lines. The surface area of overlapping parts between a plurality of semiconductor layers of thin-film transistors and the scanning lines and the surface area overlapping parts between the plurality of semiconductor layers and the common scanning interconnect are substantially equal. 1. A display device comprising:a plurality of scanning lines and a plurality of signal lines that mutually intersect;a plurality of pixel circuit thin-film transistors provided at a plurality of pixels partitioned by the plurality of scanning lines and the plurality of signal lines;a common scanning interconnect that electrically connects between the plurality of scanning lines; anda plurality of protective elements that electrically connect between the common scanning interconnect and each of the plurality of scanning lines,wherein at least a part of the plurality of connecting interconnects that electrically connect the common scanning interconnect with the plurality of protective elements are constituted by interconnects on the same layer as the signal lines,a plurality of pixel circuit semiconductor layers constituting the plurality of pixel circuit thin-film transistors and each of the plurality of scanning lines overlap when seen in plan view,a plurality of semiconductor layers on the same layer as the pixel circuit semiconductor layers and a common interconnect that intersects with the plurality of scanning lines overlap when seen in plan view, andthe surface area of ...

Plasma protection diode for a hemt device

A silicon substrate having a III-V compound layer disposed thereon is provided. A diode is formed in the silicon substrate through an ion implantation process. The diode is formed proximate to an interface between the silicon substrate and the III-V compound layer. An opening is etched through the III-V compound layer to expose the diode. The opening is filled with a conductive material. Thereby, a via is formed that is coupled to the diode. A High Electron Mobility Transistor (HEMT) device is formed at least partially in the III-V compound layer.

CONFIGURATION OF GATE TO DRAIN (GD) CLAMP AND ESD PROTECTION CIRCUIT FOR POWER DEVICE BREAKDOWN PROTECTION

A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped-well that is disposed below and engulfing the U-shaped bend. 1. A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source encompassed in a body region and a drain with a gate to control an electric current transmitted between the source and the drain , wherein the semiconductor further comprising:a clamp termination structure connected in series to a silicon diode comprising a doped column disposed in said semiconductor substrate; andan end well doped with a same conductivity type as the doped column enclosing an end portion of the doped column.2. The semiconductor power device of wherein:the clamp termination structure comprises at least another doped column constituting parallel doped columns having a predefined gap between the doped columns.3. The semiconductor power device of wherein:said predefined gap ranging between 2 to 5 micrometers.4. The semiconductor power device of wherein:said parallel doped columns further include a U-shaped bend for connecting together two ends of two adjacent parallel doped columns.5. The semiconductor power device of wherein:the end-well is disposed below and engulfing an end of the doped column, wherein the end well having the same conductivity type as the ...

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE RELATING TO AN ELECTRICAL OVER STRESS PROTECTING CIRCUIT

A semiconductor integrated circuit device may include a first discharging unit and a second discharging unit. The first discharging unit may be coupled between a first line having a first voltage level and a second line having a second voltage level different from the first voltage level. The first discharging unit may be configured to discharge an electrical over stress (EOS) generated from the first line. The second discharging unit may be coupled between the first line and the second line. The second discharging unit may discharge the EOS in the first line to the second line based on an output signal from the first discharging unit. 1. A semiconductor integrated circuit device comprising:a first discharging unit connected between a first line having a first voltage level and a second line having a second voltage level different from the first voltage level to discharge an electrical over stress (EOS) generated in the first line; anda second discharging unit connected between the first line and the second line to discharge the EOS in the first line to the second line based on an output signal from the first discharging unit,wherein the first discharging unit comprises a phase changeable layer having variable resistances in accordance with a voltage difference between the first line and the second line.2. The semiconductor integrated circuit device of claim 1 , wherein the first line is configured to transmit a power voltage claim 1 , and the second line is configured to transmit a ground voltage.3. The semiconductor integrated circuit device of claim 1 , wherein the first discharging unit comprises an Ovonic threshold switch (OTS) unit coupled between the first line and the second discharging unit.4. The semiconductor integrated circuit device of claim 3 , wherein the OTS unit comprises:an upper electrode coupled to the first line;a lower electrode coupled to the second discharging unit; anda chalcogenide layer interposed between the upper electrode and the lower ...

OVERVOLTAGE PROTECTION DEVICE

An electrostatic discharge protection device includes the following successive structures: a very heavily-doped semiconductor substrate of a first conductivity type; a first heavily-doped buried semiconductor layer of a second conductivity type; a first lightly-doped semiconductor layer of the second conductivity type; and a second heavily-doped layer of the first conductivity type. The device further includes, located between first heavily-doped buried semiconductor layer and the first lightly-doped semiconductor layer, a third doped layer of the first conductivity type having a thickness and a dopant atom concentration configured to form, at a junction of the first lightly-doped semiconductor layer and the third layer, a diode having a reverse punchthrough operation. 1. A device of protection against electrostatic discharges , comprising the following successive structures:a very heavily-doped semiconductor substrate of a first conductivity type;a first heavily-doped buried semiconductor layer of a second conductivity type;a first lightly-doped semiconductor layer of the second conductivity type; anda second heavily-doped layer of the first conductivity type, andfurther comprising, between the first heavily-doped buried semiconductor layer and the first lightly-doped semiconductor layer, a third layer doped of the first conductivity type, having a thickness and a dopant atom concentration configured to form, at a junction of the first lightly-doped semiconductor layer and of the third layer, a diode having a reverse punchthrough operation.2. The device of claim 1 , wherein the first heavily-doped buried semiconductor layer claim 1 , the third layer claim 1 , the first lightly-doped semiconductor layer claim 1 , and the second heavily-doped layer are stacked on a first portion of the very heavily-doped semiconductor substrate claim 1 , wherein the very heavily-doped semiconductor substrate further comprises a second portion supporting:a second heavily-doped ...

METHODS FOR AN ESD PROTECTION CIRCUIT INCLUDING TRIGGER-VOLTAGE TUNABLE CASCODE TRANSISTORS

Methods to forming trigger-voltage tunable cascode transistors for an ESD protection circuit in FinFET IC devices and resulting devices. Embodiments include providing a substrate including adjacent first-type well areas, over the substrate, each pair of first-type well areas separated by a second-type well area; providing one or more junction areas in each first and second type well area, each junction area being a first type or a second type; forming fins, spaced from each other, perpendicular to and over the first and second type junction areas; and forming junction-type devices by forming electrical connections between the first and second type junction areas in the first-type well areas and the substrate, wherein a first-stage junction-type device in a first-type well area includes stacked first and second type junction areas, and wherein the first-stage junction-type device is adjacent a second-type well area including first and second type junction areas. 1. A method comprising:providing a p-type substrate including adjacent n-well areas, over the substrate, each pair of n-well areas separated by a p-well area;providing p-type and n-type junction areas in the n-type well areas;providing p-type or p-type and n-type junction areas in the p-type well areas;forming isolation trench regions separating the n-type and p-type well areas;forming fins, spaced from each other, perpendicular to and over the n-type and p-type junction areas;forming junction-type devices by forming electrical connections between the n-type and p-type junction areas in the n-type well areas and the substrate, wherein a first-stage junction-type device in an n-type well area includes stacked n-type and p-type junction areas, and wherein the first-stage junction-type device is adjacent a p-type well area including n-type and p-type junction areas; andconnecting the junction areas in the p-type well areas to an electrical ground.2. The method according to claim 1 , wherein:the p-type well area ...

ELECTRONIC DEVICE

An ESD protection device may include: a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection layer. 1a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion;a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, and an electrical connection layer;wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other, the electrical connection layer comprises at least one first via embedded in ...

SEMICONDUCTOR APPARATUS

A semiconductor apparatus includes: a device having a terminal; and a protection circuit configured to be connected to the terminal of the device, the protection circuit including at least two unidirectional conduction circuits connected in anti-parallel, the two unidirectional conduction circuits configured to have current directions opposite to each other in an on state, wherein the protection circuit is so configured that, at least one of the two unidirectional conduction circuits is turned on to release charges accumulated at the terminal when a voltage at the terminal of the device is out of a predetermined protection voltage range 1. A semiconductor apparatus , comprising:a device having a terminal; anda protection circuit configured to be connected to the terminal of the device, the protection circuit comprising at least two unidirectional conduction circuits connected in anti-parallel, the two unidirectional conduction circuits configured to have current directions opposite to each other in an on state,wherein the protection circuit is so configured that, at least one of the two unidirectional conduction circuits is turned on to release charges accumulated at the terminal when a voltage at the terminal of the device is out of a predetermined protection voltage range.2. The semiconductor apparatus according to claim 1 , wherein claim 1 ,the terminal of the device is used to receive a test voltage within a target test voltage range;a turn-on threshold of each of the unidirectional conduction circuits is set to be greater than a maximum value of an absolute value of the test voltage.3. The semiconductor apparatus according to claim 2 , wherein claim 2 , the protection voltage range is set to contain or be equal to the target test voltage range.4. The semiconductor apparatus according to claim 2 , wherein claim 2 ,the device has a safe voltage threshold associated with the terminal;the turn-on threshold of each of the unidirectional conduction circuits is set to ...

SHIELDED GATE TRENCH MOSFET WITH ESD DIODE MANUFACTURED USING TWO POLY-SILICON LAYERS PROCESS

A SGT MOSFET having ESD diode and a method of manufacturing the same are disclosed. The SGT trench MOSFET according to the present invention, has n+ doped gate shielded electrodes in an N channel device and requires only two poly-silicon layers, making the device can be shrunk with reducing shielded gate width for Rds reduction without increasing switching loss and having dynamic switching instability. 1. A Shielded Gate Trench (SGT) MOSFET comprising:an epitaxial layer of a first conductivity type extends over a substrate;a plurality of first type trenches is formed in said epitaxial layer in an active area, each of said first type trenches is filled with a shielded gate structure comprising a first poly-silicon layer in a lower portion to serve as a shielded electrode and a second poly-silicon layer in an upper portion to serve as a gate electrode, wherein said shielded electrode is insulated from said epitaxial layer by a first insulating film and said gate electrode is insulated from said epitaxial layer by a gate insulating film which has a thickness less than said first insulating film, wherein said shielded electrode and said gate electrode are insulated from each other by a second insulating film;an ESD clamp diode comprises said second poly-silicon layer formed on top of said epitaxial layer and is isolated from said epitaxial layer by said first insulating film;said ESD clamp diode is connected with at least one second type trench through a source metal, wherein said second type trench is filled with said first poly-silicon layer as a single electrode; andsaid first and second poly-silicon layers are doped with said first conductivity type.2. The SGT MOSFET of claim 1 , wherein said ESD clamp diode is consisted of at least one pair of back to back Zener diodes comprising multiple alternatively arranged doped regions of said first conductivity type and doped regions of a second conductivity type opposite to said first conductivity type.3. The SGT MOSFET of ...

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURE OF A SEMICONDUCTOR DEVICE

A semiconductor device is provided that includes a first n+ region, a first p+ region within the first n+ region, a second n+ region, a second p+ region, positioned between the first n+ region and the second n+ region. The first n+ region, the second n+ region and the second p+ region are positioned within a p− region. A first space charge region and a second space charge region are formed within the p− region. The first space region is positioned between the first n+ region and the second p+ region, and the second space region is positioned between the second p+ region and the second n+ region. 1. A semiconductor device comprising:a first n+ region,a first p+ region within the first n+ region,a second n+ region,a second p+ region, positioned between the first n+ region and the second n+ region,wherein the first n+ region, the second n+ region and the second p+ region are positioned within a p− region;a first space charge region and a second space charge region are formed within the p− region; andwherein the first space region is positioned between the first n+ region and the second p+ region, and the second space region is positioned between the second p+ region and the second n+ region.2. The semiconductor device as claimed in claim 1 , wherein the p− region is a lowly doped epitaxial layer.3. The semiconductor device as claimed in claim 1 , wherein all polarities are inverted claim 1 , so that all p-doping regions are n-doping regions and all n-doping regions are p-doping regions.4. The semiconductor device as claimed in claim 2 , wherein all polarities are inverted claim 2 , so that all p-doping regions are n-doping regions and all n-doping regions are p-doping regions.5. The semiconductor device as claimed in claim 1 , wherein the first space region and the second space region are 2 to 3 μm wide.6. The semiconductor device as claimed in claim 2 , wherein the first space region and the second space region are 2 to 3 μm wide.7. The semiconductor device as claimed ...

SEMICONDUCTOR DEVICE

To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged. 1. A semiconductor device comprising:(a) a semiconductor substrate of substantially rectangular shape having a pair of long edges and a pair of short edges;(b) an internal circuit including a plurality of MISFETs formed over the semiconductor substrate;(c) a plurality of protection elements formed over the semiconductor substrate so as to protect the internal circuit against static electricity;(d) a first insulating film formed over the semiconductor substrate so as to cover the plurality of MISFETs and the plurality of protection elements; and(e) a plurality of bump electrodes formed over the first insulating film, the plurality of bump electrodes being arranged along a first long edge of the pair of long edges,wherein the plurality of bump electrodes are bump electrodes for receiving input signals from an external device,wherein the plurality of protection elements are electrically coupled between the respective plurality of bump electrodes and the internal circuit,wherein the plurality of bump electrodes include a first bump electrode and a second bump electrode,wherein the plurality of protection elements include a first protection element and a second protection element,wherein the first protection element electrically coupled to the first bump electrode is disposed at a position overlapped with the first bump electrode in a planar view when ...

Method and system for a semiconductor device with integrated transient voltage suppression

A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.

STRUCTURES, METHODS AND APPLICATIONS FOR ELECTRICAL PULSE ANNEAL PROCESSES

Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds. 1. An electrostatic discharge (ESD) N+/P+ structure comprising:an N+ diffusion on a substrate;a P+ diffusion on the substrate and in electrical contact with the N+ diffusion; anda device between the N+ diffusion and the P+ diffusion, wherein the N+ diffusion and the P+ diffusion are ring structures surrounding the device.2. The structure of claim 1 , wherein the P+ diffusion on the substrate in in direct electrical and physical contact with the N+ diffusion thereby forming an ESD diode.3. The structure of claim 2 , wherein the device is a single device between the N+ diffusion and the P+ diffusion.4. The structure of claim 1 , wherein the N+ diffusion is an outer ring and the P+ diffusion is an inner ring of the ring structures.5. The structure of claim 1 , further comprising a contact on the P+ diffusion and a contact on the N+ diffusion to provide an electrical pulse to the P+ diffusion and allow the electrical pulse to flow out of the N+ diffusion claim 1 , respectively.6. The structure of claim 1 , wherein the device is an active device.7. The structure of claim 1 , wherein the device is an active device.8. The structure of claim 7 , wherein the active device is about 50 to 100 μm.9. The structure of claim 1 , wherein the N+ diffusion and the P+ diffusion form an ESD N+/P+ structure.1018. The structure of claim 1 , wherein the N+ diffusion and a P+ diffusion are formed in a closed or ring shape on a ...

STRUCTURES, METHODS AND APPLICATIONS FOR ELECTRICAL PULSE ANNEAL PROCESSES

Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds. 1. An electrostatic discharge (ESD) N+/P+ structure comprising:an N+ diffusion on a substrate;a P+ diffusion on the substrate and in electrical contact with the N+ diffusion; anda device between the N+ diffusion and the P+ diffusion,wherein the N+ diffusion and the P+ diffusion are in a side by side relationship.2. The structure of claim 1 , wherein the P+ diffusion on the substrate in direct electrical and physical contact with the N+ diffusion thereby forming an ESD diode.3. The structure of claim 2 , wherein the device is a single device between the N+ diffusion and the P+ diffusion.4. The structure of claim 1 , further comprising a contact on the P+ diffusion and a contact on the N+ diffusion to provide an electrical pulse to the P+ diffusion and allow the electrical pulse to flow out of the N+ diffusion claim 1 , respectively.5. The structure of claim 1 , wherein the N+ diffusion and the P+ diffusion form an ESD N+/P+ structure.6. The structure of claim 1 , wherein the N+ diffusion and the P+ diffusion are formed on a BOX layer formed on the substrate.7. The structure of claim 6 , wherein the N+ diffusion acts as a cathode and the P+ diffusion acts as an anode.8. The structure of claim 7 , further comprising contacts for supplying an electrical pulse to generate heat across the active region.91816aa. The structure of claim 8 , wherein a first contact allows an electric pulse to flow through the anode ...

SEMICONDUCTOR DEVICES

Provided are semiconductor devices. A semiconductor device includes a first well formed in a substrate; an element isolation layer formed on the first well; a second well formed in the first well on a first side of the element isolation layer; a third well formed in the second well, the third well has a higher concentration of impurities than the second well; a first electrode electrically connected to the third well; a fourth well formed in the first well on a second side of the element isolation layer; a fifth well formed in the fourth well, the fifth well has a different conductivity type from the fourth well; a second electrode electrically connected to the fifth well; and a sixth well overlapping the fourth well, the sixth well has a lower concentration of impurities than the fourth well. 1. A semiconductor device comprising:a first well formed in a substrate;an element isolation layer that is on the first well;a second well that is in the first well on a first side of the element isolation layer;a third well that is in the second well, wherein the third well has a higher concentration of impurities than the second well;a first electrode that is electrically connected to the third well;a fourth well that is in the first well on a second side of the element isolation layer;a fifth well that is in the fourth well, wherein the fifth well has a different conductivity type from the fourth well;a second electrode that is electrically connected to the fifth well; anda sixth well that overlaps the fourth well, wherein the sixth well has a lower concentration of impurities than the fourth well.2. The semiconductor device of claim 1 , wherein the sixth well overlaps the element isolation layer.3. The semiconductor device of claim 2 , wherein the sixth well and the fourth well have the same conductivity type.4. The semiconductor device of claim 2 , wherein the sixth well and the fourth well have different conductivity types.5. The semiconductor device of claim 4 , wherein ...

PLANAR SEMICONDUCTOR ESD DEVICE AND METHOD OF MAKING SAME

An ESD device is provided for protecting a circuit from electrostatic discharge, and includes a planar diode having an anode and a cathode. The anode is electrically coupled to a signal path of the circuit, and the cathode is electrically coupled to a ground of the circuit. The ESD device is configured to be off during normal operation of the circuit and to turn on in response to an electrostatic discharge on the signal path. Two depletion regions in the device are separated by an isolation well. In response to the electrostatic discharge, the depletion regions modulate (e.g., widen and merge), providing a path for the discharge to the ground of the circuit. 13-. (canceled)4. A planar diode , comprising:an anode electrically coupleable to a signal path of a circuit; anda cathode electrically coupleable to a ground of the circuit;wherein the planar diode allows current flow in only one direction and is configured to be off during normal operation of the circuit and to turn on in response to an electrostatic discharge on the signal path.5. The planar diode of claim 4 , further comprising two depletion regions separated by an isolation well during normal operation of the circuit.6. The planar diode of claim 5 , wherein the two depletion regions modulate in response to the electrostatic discharge claim 5 , such that a path for the electrostatic discharge is created to the ground of the circuit.7. The planar diode of claim 6 , further comprising;a substrate of a first type, wherein the first type is one of n-type and p-type;a left well, a right well and a middle well of a second type, the middle well situated between the left well and the right well;left, right and middle isolation wells under each of the left, right and middle wells, respectively;a first well of the first type extending between the left well and the middle well and between the left and middle isolation wells;a second well of the first type extending between the middle well and the right well and between ...

Avalanche Diode Having an Enhanced Defect Concentration Level and Method of Making the Same

The invention relates to an avalanche diode that can be employed as an ESD protection device. An avalanche ignition region is formed at the p-n junction of the diode and includes an enhanced defect concentration level to provide rapid onset of avalanche current. The avalanche ignition region is preferably formed wider than the diode depletion zone, and is preferably created by placement, preferably by ion implantation, of an atomic specie different from that of the principal device structure. The doping concentration of the placed atomic specie should be sufficiently high to ensure substantially immediate onset of avalanche current when the diode breakdown voltage is exceeded. The new atomic specie preferably comprises argon or nitrogen, but other atomic species can be employed. However, other means of increasing a defect concentration level in the diode depletion zone, such as an altered annealing program, are also contemplated.

SEMICONDUCTOR DEVICE

A semiconductor device includes a first overvoltage detection unit including a first comparator arranged to output a first detection signal based on a first divided voltage after dividing an output voltage of a power supply circuit by first resistors disposed externally and a second overvoltage detection unit including second resistors and a second comparator arranged to output a second detection signal based on a second divided voltage after dividing the output voltage by the second resistors. 1. A semiconductor device comprising:a first overvoltage detection unit including a first comparator arranged to output a first detection signal based on a first divided voltage after dividing an output voltage of a power supply circuit by first resistors disposed externally; anda second overvoltage detection unit including second resistors and a second comparator arranged to output a second detection signal based on a second divided voltage after dividing the output voltage by the second resistors.2. The semiconductor device according to claim 1 , further comprising a logic unit arranged to operate in accordance with the first detection signal and the second detection signal claim 1 , whereinthe logic unit turns off a switching element of the power supply circuit when one of the first detection signal and the second detection signal is detected, so as to perform overvoltage protection.3. The semiconductor device according to claim 1 , further comprising:an external terminal connected to an output capacitor disposed in the power supply circuit; anda discharge circuit arranged to discharge the output capacitor via the external terminal, whereinthe second resistors are connected to the external terminal.4. The semiconductor device according to claim 1 , further comprising:a first external terminal connected to an output capacitor disposed in the power supply circuit;a discharge circuit arranged to discharge the output capacitor via the first external terminal; anda second ...

STUCTURE FOR PROTECTING AN INTEGRATED CIRCUIT AGAINST ELECTROSTATIC DISCHARGES

An integrated circuit includes at least one input-output pad and a terminal intended to be connected to a source of a reference potential and further including a protection structure including a thyristor forward-connected between the pad and the terminal. The thyristor includes a first resistor between its cathode gate and the terminal. At least one Zener diode is disposed between the thyristor and the pad. The anode of the Zener diode is connected to the cathode gate of the thyristor and the cathode of the Zener diode is connected to the pad via at least one second resistor. The junction of the Zener diode is different from the junctions of the PNPN structure of the thyristor. 1. An semiconductor device comprising:an input-output pad;a terminal adapted to be connected to a source of a reference potential;a thyristor that is forward-connected between the pad and the terminal, the thyristor comprising a PNPN structure, an anode, a cathode gate and a first resistor between the cathode gate and the terminal; anda Zener diode coupled between the thyristor and the pad, the Zener diode having an anode coupled to the cathode gate of the thyristor and a cathode coupled connected to the pad via a second resistor, the Zener diode having a junction that is different from junctions of the PNPN structure of the thyristor.2. The semiconductor device of claim 1 , further comprising a third resistor between the anode of the thyristor and the pad.3. The semiconductor device of claim 1 , further comprising a diode having an anode coupled to the terminal and a cathode coupled to the pad.4. The semiconductor device of claim 1 , further comprising integrated circuitry coupled to the input-output pad claim 1 , the thyristor and Zener diode coupled to protect the integrated circuitry from electrostatic discharge.5. A semiconductor device claim 1 , comprising:a doped substrate of a first conductivity type and having a surface;a first doped semiconductor region of a second conductivity ...

ELECTROSTATIC PROTECTION ELEMENT

An electrostatic protection element includes a substrate of a first conductivity type, an epitaxial layer formed on the substrate, the epitaxial layer being of a second conductivity type; a well formed on the epitaxial layer, the well being of the first conductivity type; a transistor formed inside of the well, the transistor including a drain region, a source region formed to face the drain region across a channel region, and a gate formed above the channel region so as to be insulated; and a well contact region of the first conductivity type disposed so as to form an opposing region where the drain region and the well contact region face each other while being separated by a prescribed distance in a direction parallel to at least an extension direction of the gate. 1. An electrostatic protection element , comprising:a substrate of a first conductivity type;an epitaxial layer formed on the substrate, the epitaxial layer being of a second conductivity type;a well of the first conductivity type formed on the epitaxial layer;a transistor formed inside of the well, the transistor including a drain region, a source region formed to face the drain region across a channel region, and a gate formed above the channel region so as to be insulated; anda well contact region of the first conductivity type disposed in the well on an opposite side of the drain region from the gate in a width direction so as to form an opposing region in the well where the drain region and the well contact region face each other, the opposing region extending in a length direction parallel to a length of the gate.2. The electrostatic protection element according to claim 1 , wherein the well contact region is formed so as to surround the transistor in the length direction and the width direction.3. The electrostatic protection element according to claim 2 , further comprising an element isolation trench formed so as to surround the well contact region in the length direction and the width ...

STACKED ELECTROSTATIC DISCHARGE DIODE STRUCTURES

An electrostatic discharge (ESD) protection structure containing a bottom diode and a top diode vertically stacked on the bottom diode is provided to render sufficient protection from ESD events with reduced diode footprint. The bottom diode is serially connected to the top diode via a conductive strap structure. 1. A method of forming a semiconductor structure comprising:forming a plurality of first well regions of a first conductivity and a plurality of second well regions of a second conductivity type in a surface portion of a semiconductor substrate, wherein the second conductivity type is opposite from the first conductivity type;forming a stack comprising a first doped semiconductor portion of the second conductivity type and a second doped semiconductor portion of the first conductivity type on each of the plurality of first well regions, wherein adjacent stacks are electrically insulated from each other by a shallow trench (STI) layer;forming a conductive strap structure on sidewalls of each stack of the first doped semiconductor portion and the second doped semiconductor portion;forming an interlevel dielectric (ILD) layer on the STI layer, each conductive strap structure and each second doped semiconductor portion;forming an opening to expose at least a portion of each second doped semiconductor portion;forming a third doped semiconductor portion on the exposed portion of each second doped semiconductor portion; andforming a contact landing structure on each third doped semiconductor portion.2. The method of claim 1 , further comprising forming a dielectric fill portion on each contact landing structure within each opening.3. The method of claim 2 , further comprising forming a first contact structure contacting each contact landing structure claim 2 , a second contact structure contacting each of the plurality of first well regions claim 2 , and a shared contact structure connecting adjacent conductive strap structures.4. The method of claim 1 , further ...