PN-Übergangsdiode aus Diamant und Methode zu deren Herstellung

Leistungshalbleitermodul

Ein Leistungshalbleitermodul wird bereitgestellt, das eine Induktivität zwischen Verdrahtungsleitungen im Leistungshalbleitermodul reduziert, um eine Unterbindung eines Bruchs des Leistungshalbleiterelements durch eine Stoßspannung zu ermöglichen. Das Leistungshalbleitermodul: einen positiven Zweig und einen negativen Zweig, die durch eine Reihenschaltung von Halbleiterelementen (6) des lichtbogenselbstlöschenden Typs gebildet sind, und die an einer Reihenanschlussstelle zwischen den Halbleiterelementen (6) des lichtbogenselbstlöschenden Typs angeschlossen sind; eine positivseitige Gleichstromelektrode (10), eine negativseitige Gleichstromelektrode (11) und eine Wechselstromelektrode (12), die an den positiven Zweig und den negativen Zweig angeschlossen sind; und ein Substrat (2), auf dem ein Verdrahtungsmuster (3, 4) ausgebildet ist, wobei das Verdrahtungsmuster (3, 4) die Halbleiterelemente (6) des lichtbogenselbstlöschenden Typs des positiven Zweigs und des negativen Zweigs an die positivseitige ...

Power solid state switch of semiconductor switch type

The resistance in the current path of the solid state switch is adjustable by a control voltage at at least one control electrode. To achieve an isolating switch or free switch a material is inserted with an intrinsic conductivity corresponding to a band gap that is greater than 2.5 eV, and which has a breakdown strength of more than 1 kV per 18 micrometres. The material assumes the isolation state for a drive voltage of O V. In one embodiment the material inserted is silicon carbide.

A diamond field effect transistor

A field effect transistor

High power complimentary field-effect transistors

Vertical diamond field effect transistor and method for making same

Diamond heterojunction diode

Diamond sensors detectors and quantum devices

METHOD FOR FORMING N-TYPE SEMICONDUCTING DIAMOND FILMS BY VAPOR PHASE TECHNIQUES

An electrical conductor

An electrical conductor

An electrical conductor

An electrical conductor

HIGH-ORIENTED DIAMOND LAYER, PROCEDURE FOR YOUR PRODUCTION AS WELL AS ELECTRONIC DEVICE WITH AN HIGH-ORIENTED DIAMOND LAYER

DIAMOND TRANSISTOR AND PROCEDURE FOR ITS PRODUCTION.

A semiconductor device

Structures formed in diamond

N-V centers in diamond are created in a controlled manner. In one embodiment, a single crystal diamond is formed using a CVD process, and then annealed to remove N-V centers. A thin layer of single crystal diamond is then formed with a controlled number of N-V centers. The N-V centers form Qubits for use in electronic circuits. Masked and controlled ion implants, coupled with annealing are used in CVD formed diamond to create structures for both optical applications and nanoelectromechanical device formation. Waveguides may be formed optically coupled to the N-V centers and further coupled to sources and detectors of light to interact with the N-V centers.

Power supply device

A power supply device is provided with: a resistor 11 for limiting the current supplied from an AC power supply 2; a switching unit 12 connected in parallel with the resistor 11; a rectifier circuit unit 13 connected at a stage subsequent to the resistor 11 and the switching unit 12 and rectifying the AC voltage of the AC power supply 2; a booster circuit unit 14 for boosting the rectified DC voltage; a DC voltage detection unit 15 for detecting the DC voltage output from the booster circuit unit 14; an AC voltage detection unit 19 for detecting the AC voltage of the AC power supply 2; a protection setting unit 16 for comparing a first protection voltage calculated on the basis of the boost level obtained by the booster circuit unit 14 with a second protection voltage calculated on the basis of the AC voltage detected by the AC voltage detection unit 19 and setting one of the first and second protection voltages as a protection voltage; and a control unit 17 for, when the DC voltage becomes ...

NANOSENSORS

... ²²²Electrical devices comprised of nanowires are described, along with methods of ²their manufacture and use. The nanowires can be nanotubes and nanowires. The ²surface of the nanowires may be selectively functionalized. Nanodetector ²devices are described.² ...

P-N-P DIAMOND TRANSISTOR

The present invention provides a P-N-P diamond transistor and a method of manufacture thereof. The transistor comprises a diamond substrate having two p-type semiconducting regions separated by an insulating region with an n-type semiconducting layer established by chemical vapour deposition. Preferably the p-type regions are obtained by doping with boron and controlling the concentration of nitrogen impurities by the use of nitrogen getters. The n-type layer preferably contains phosphorus.

Power semiconductor module and power unit

Semiconductor device and method for manufacturing same

HIGH ORIENTATION DIAMOND LAYER FOR FORMING FLAT SURFACE WITHOUT NON-ORIENTED CRYSTAL AND INCREASING CRYSTAL GRAIN SIZE AND MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS WITH HIGH ORIENTATION DIAMOND LAYER

PURPOSE: A high orientation diamond layer and its manufacturing method, and an electronic apparatus with the high orientation diamond layer are provided to acquire a flat surface without a non-oriented crystal and to increase a crystal grain size. CONSTITUTION: A high orientation diamond layer includes a first diamond layer and a second diamond layer. The first diamond layer(1) is formed by using a {111} sector growth. The second diamond layer(2) is deposited on the first diamond layer. The second diamond layer is formed by using a {100} sector growth. The crystal grain size is gradually increased from the first diamond layer to the second diamond layer. The mean crystal grain size of the second diamond layer is in a range of 30 micro meters or more. © KIPO 2006 ...

DOPED ELONGATED SEMICONDUCTORS, GROWING SUCH SEMICONDUCTORS, DEVICES INCLUDING SUCH SEMICONDUCTORS AND FABRICATING SUCH DEVICES

A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. Such a semiconductor may comprise an interior core comprising a first semiconductor; and an exterior shell comprising a different material than the first semiconductor. Such a semiconductor may be elongated and may have, at any point along a longtiudinal section of such a semiconductor, a ratio of the length of the section to a longest width which is greater than 4:1, or greater than 10:1, or greater than 100:1, or even greater than 1000:1. At least one portion of such a semiconductor may a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less ...

FABRICATING A GALLIUM NITRIDE LAYER WITH DIAMOND LAYERS

SELF ALIGNED CARBIDE SOURCE/DRAIN FET

A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide drain portion, a nanostructure formed over the insulating carbon portion and connecting the metal carbide source portion to the metal carbide drain portion, and a gate stack formed over at least a portion of the insulating carbon portion and at least a portion of the nanostructure.

Diamond semiconductor system and method

Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The method may include the steps of selecting a diamond semiconductor material having a surface, exposing the surface to a source gas in an etching chamber, forming a carbide interface contact layer on the surface; and forming a metal layer on the interface layer.

Semiconductor devices with minimized current flow differences and methods of same

A semiconductor device with minimized current flow differences and method of fabricating same are disclosed. The method includes forming a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, in which the second layer is on top of the first layer, forming a plurality of mesas in the semiconductor layer stack, and forming a plurality of gates in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, in which the plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device.

Diamond films with heat-resisting ohmic electrodes

A is a heat-resisting ohmic electrode on diamond film, including: a p-type semiconducting diamond film; a boron-doped diamond layer provided on the semiconducting diamond film; and an electrode element made of p-type Si selectively formed on the boron-doped diamond layer; wherein the boron concentration in the boron-doped diamond layer is from 1.0×1019 to 1.8×1023 cm-3, and at least one impurity selected from the group consisting of B, Al and Ga is doped in the electrode element with a concentration from 1.0×1020 to 5.0×1022 cm-3. The ohmic electrode on diamond film is applicable for electronic devices operative at high temperature.

Diamond electric device on silicon

A diamond electric device is described. The device comprises a diamond film deposited on a semiconductor substrate and an upper electrode. The electrical contact between the diamond film and the electrode is formed only through an intervening silicon semiconductor film which prevents direct contact between the diamond film and the electrode. By this structure, the stability of electric performance is substantially improved.

Semiconducting diamond and process for producing the same

A semiconducting diamond which contains diamond carbon and at least one dopant element selected from the group consisting of S, Se, and Cl, and a process for producing the same.

Transparent nanocrystalline diamond coatings and devices

A method for coating a substrate comprises producing a plasma ball using a microwave plasma source in the presence of a mixture of gases. The plasma ball has a diameter. The plasma ball is disposed at a first distance from the substrate and the substrate is maintained at a first temperature. The plasma ball is maintained at the first distance from the substrate, and a diamond coating is deposited on the substrate. The diamond coating has a thickness. Furthermore, the diamond coating has an optical transparency of greater than about 80%. The diamond coating can include nanocrystalline diamond. The microwave plasma source can have a frequency of about 915 MHz.

Silicon carbide MOSFET with integrated MOS diode

A monolithically integrated MOS channel in gate-source shorted mode is used as a diode for the third quadrant conduction path for a power MOSFET. The MOS diode and MOSFET can be constructed in a variety of configurations including split-cell and trench. The devices may be formed of silicon carbide, gallium nitride, aluminum nitride, aluminum gallium nitride, diamond, or similar semiconductor. Low storage capacitance and low knee voltage for the MOS diode can be achieved by a variety of means. The MOS diode may be implemented with channel mobility enhancement materials, and/or have a very thin/high permittivity gate dielectric. The MOSFET gate conductor and MOS diode gate conductor may be made of polysilicon doped with opposite dopant types. The surface of the MOS diode dielectric may be implanted with cesium.

Silicon carbide layer on diamond substrate for supporting group III nitride heterostructure device

A high power, wide-bandgap device is disclosed that exhibits reduced junction temperature and higher power density during operation and improved reliability at a rated power density. The device includes a diamond substrate for providing a heat sink with a thermal conductivity greater than silicon carbide, a single crystal silicon carbide layer on the diamond substrate for providing a supporting crystal lattice match for wide-bandgap material structures that is better than the crystal lattice match of diamond, and a Group III nitride heterostructure on the single crystal silicon carbide layer for providing device characteristics.

SEMICONDUCTOR DEVICE AND ELECTRIC APPARATUS

The present invention provides a semiconductor device and an electric apparatus each of which can realize both high-speed switching operation and energy loss reduction and excels in resistance to current concentration based on a counter electromotive voltage generated by, for example, an inductance load of the electric apparatus. A semiconductor device (100) of the present invention includes: a semiconductor layer (3) made of a first conductivity type wide band-gap semiconductor; a transistor cell (101T) in which a vertical field effect transistor (102) is formed, the vertical field effect transistor (102) causing a charge carrier to move in a thickness direction of the semiconductor layer (3); and a diode cell (101S) in which a schottky diode (103) is formed, the schottky diode (103) being formed such that a schottky electrode (9) forms a schottky junction with the semiconductor layer (3), wherein the semiconductor layer 3 is divided into a plurality of square subregions (101T and 101S ...

Silicon Carbide on Diamond Substrates and Related Devices and Methods

A method of forming a high-power, high-frequency device in wide bandgap semiconductor materials with reduced junction temperature, higher power density during operation and improved reliability at a rated power density is disclosed, along with resulting semiconductor structures and devices. The method includes adding a layer of diamond to a silicon carbide wafer to increase the thermal conductivity of the resulting composite wafer, thereafter reducing the thickness of the silicon carbide portion of the composite wafer while retaining sufficient thickness of silicon carbide to support epitaxial growth thereon, preparing the silicon carbide surface of the composite wafer for epitaxial growth thereon, and adding a Group III nitride heterostructure to the prepared silicon carbide face of the wafer.

METHOD AND SYSTEM FOR DIAMOND-BASED OXYGEN SENSOR

A diamond based oxygen sensor is able to function in harsh environment conditions. The oxygen sensor includes a gateless field effect transistor including a synthetic, quasi-intrinsic, hydrogen-passivated, monocrystalline diamond layer exhibiting a -dimension hole gas effect. The oxygen sensor also includes a sensing layer comprising yttrium-stabilized zirconia deposited onto a surface of the gateless field effect transistor. 1. An oxygen sensor , comprising:{'b': 100', '116, 'a gateless field effect transistor (FET) () including a synthetic, quasi-intrinsic, hydrogen-passivated diamond layer () exhibiting a 2-dimension hole gas effect; and'}{'b': 124', '100, 'an oxygen-sensing layer () including a yttrium-stabilized zirconia (YSZ) supported by the gateless FET ().'}2100. The oxygen sensor of claim 1 , the gateless FET () further including:{'b': 118', '116, 'a first highly-doped p-type region () implanted within the monocrystalline diamond layer ();'}{'b': 120', '116, 'a second highly-doped p-type region () implanted within the monocrystalline diamond layer (); and'}{'b': 128', '116', '118', '120, 'a 2-dimension hole gas conductive channel () within the monocrystalline diamond layer () between the first highly-doped p-type region () and the second highly-doped p-type region ().'}3100. The oxygen sensor of claim 2 , the gateless FET () further including:{'b': 122', '118, 'an ohmic source contact () electrically coupled to the first highly-doped p-type region (); and'}{'b': 126', '120, 'an ohmic drain contact () electrically coupled to the second highly-doped p-type region ();'}{'b': 124', '128', '122', '126, 'wherein the oxygen-sensing layer () is supported by the 2-dimension hole gas conductive channel () and electrically coupled between the ohmic source contact () and the ohmic drain contact ().'}4100114116114. The oxygen sensor of claim 2 , the gateless FET () further including a polycrystalline diamond substrate () claim 2 , wherein the monocrystalline diamond ...

Semiconductor power device and method for producing same

A semiconductor power device of the present invention includes a first electrode and a second electrode, a breakdown voltage holding layer that is made of a semiconductor having a predetermined thickness and a predetermined impurity concentration, to which the first electrode and the second electrode are joined, and that has an active region in which carriers to generate electric conduction between the first electrode and the second electrode move, and an insulation film that is formed on the breakdown voltage holding layer and that has a high dielectric-constant portion having a higher dielectric constant than SiO2 at a part contiguous to the breakdown voltage holding layer.

SEMICONDUCTOR DEVICE

A semiconductor device having a low feedback capacitance and a low switching loss. The semiconductor device includes: a substrate; a drift layer formed on a surface of the semiconductor substrate; a plurality of first well regions formed on a surface of the drift layer; a source region which is an area formed on a surface of each of the first well regions and defining, as a channel region, the surface of each of the first well regions interposed between the area and the drift layer; a gate electrode formed over the channel region and the drift layer thereacross through a gate insulating film; and second well regions buried inside the drift layer below the gate electrode and formed to be individually connected to each of the first well regions adjacent to one another.

Diamond semiconductor device

The diamond semiconductor device is a diamond semiconductor device where a pair of electrodes are fixed on a diamond substrate, and wherein at least one interface to the electrode on the surface of the diamond substrate has a hydrogen termination and at least the surface of the substrate between the pair of two electrodes is controlled to have a larger electric resistivity value than inside the substrate. Accordingly, a diamond semiconductor device can be realized, capable of attaining the device work stability, especially the device work stability in severe environments such as high temperature with exhibiting the function of the hydrogen termination thereof to the utmost extent.

Stack comprising single-crystal diamond substrate

A stack including at least a semiconductor drift layer stacked on a single-crystal diamond substrate having a coalescence boundary, wherein the coalescence boundary of the single-crystal diamond substrate is a region that exhibits, in a Raman spectrum at a laser excitation wavelength of 785 nm, a full width at half maximum of a peak near 1332 cm−1due to diamond that is observed to be broader than a full width at half maximum of the peak exhibited by a region different from the coalescence boundary, the coalescence boundary has a width of 200 μm or more, and the semiconductor drift layer is stacked on at least the coalescence boundary.

DIAMOND FIELD EFFECT TRANSISTOR AND METHOD FOR PRODUCING SAME

Provided are a diamond field effect transistor using a silicon oxide film as a gate insulating film including a silicon-terminated layer containing C—Si bonds in order to reduce an interface state density, and a method for producing the same. A FET 100A includes a silicon oxide film 3A formed on a surface of a non-doped diamond layer 2A, a non-doped diamond layer 4A formed on a surface of the non-doped diamond layer 2A using the silicon oxide film 3A as a mask, a silicon-terminated layer 5A formed at an interface between the non-doped diamond layer 2A and the silicon oxide film 3A and at an interface between the non-doped diamond layer 4A and the silicon oxide film 3A, and a gate electrode 12A formed on the silicon oxide film 3A. The FET 100A operates using the silicon oxide film 3A and an insulating film 10A formed on the silicon oxide film 3A as a gate insulating film 11A and using the non-doped diamond layer 4A as each of a source region and a drain region.

Diamond MIS transistor

The invention relates to a deep depletion MIS transistor (100), comprising: a source region (S) and a drain region (D) made of doped semiconductor diamond of a first conductivity type; a channel region (C) made of doped semiconductor diamond of the first conductivity type, arranged between the source region and the drain region; a drift region (DR) made of doped semiconductor diamond of the first conductivity type, arranged between the channel region and the drain region; and a conductive gate (111) arranged on the channel region and separated from the channel region by a dielectric layer (113).

Highly-oriented diamond film, method for manufacturing the same, and electronic device having highly-oriented diamond film

DIAMOND SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD

PROBLEM TO BE SOLVED: To provide a diamond semiconductor device with a concentration of an electric field at a channel part and a gate insulating layer reduced, having a uniform insulating layer, preventing a dielectric breakdown, and reducing a defect in the vicinity of an interface between the channel part and the insulating layer, and to provide its manufacturing method. SOLUTION: A heavily boron-doped diamond layer 3a to be a source and a heavily boron-doped diamond layer 3b to be a drain are formed on a single crystal subtrate 1 of a diamond with its surface being {100} face by a selective growth method. At this point, a slope is formed by selecting a crystal face of an mutually opposed end of the diamond layer 3a and 3b. In the second place, an undoped diamond layer 5 is formed in a channel region. A source elecetrode 7 and a drain electrode 8 are formed on the diamond layer 3a and 3b, and a gate electrode 10 is formed on the layer 5 through an insulating layer 9. COPYRIGHT: (C)2005 ...

Verfahren zur Herstellung eines Schottky-Übergangs unter Verwendung von Diamant

Mounting of semiconductor-on-diamond wafers for device processing

P-Channel nanocrystalline diamond field effect transistor

An electrically conducting p-channel diamond lattice field effect transistor (DLFET) composed of nanocrystalline diamond having at least about 1020 atoms/cm3 of boron in conduction channel is disclosed, along with methods of making the same. The nanocrystalline diamond may be characterized by having an average grain size diameter of less than 1 žm, and in particular, grain sizes on the order of 10 to 20 nm, for improved performance of the DLFET.

Compound semiconductor device structures comprising polycrystalline CVD diamond

Magnetometer device based on electrical pumping in nitrogen-vacancy centers in diamond

SEMICONDUCTOR ELEMENT WITH DEPTHS IMPURITY LEVEL FOR APPLICATION AT HIGH TEMPERATURE

Structures formed in diamond

A semiconductor device

LARGE-SIZE MONOATOMIC AND MONOCRYSTALLINE LAYER, MADE OF DIAMOND-TYPE CARBON AND DEVICE FOR MAKING SAME

... ▓▓▓Selon l'invention, on forme un substrat monocristallin (2) en SiC terminÚ par ▓un plan atomique de carbone selon une reconstruction c(2x2) et on effectue au ▓moins un recuit du substrat, apte Ó transformer ce plan atomique, qui est un ▓plan de dimÞres C~C (4) de configuration sp, en un plan de dimÞres C-C (8) de ▓configuration sp3. Application Ó la microÚlectronique, l'optique, ▓l'optoÚlectronique, la micromÚcanique et aux biomatÚriaux.▓ ...

AN ELECTRICAL CONDUCTOR

The invention provides circuits and electronic devices which comprise an electrical flow path, at least part of which is formed by a body of a substrate material at least part of which is a doped part having a surface and implanted atoms at or below the surface, at least part of the surface defining a low resistance section of the electrical flow path.

SEMICONDUCTOR COMPONENT WITH JUNCTION TERMINATION WITH HIGH BLOCKING EFFECTIVENESS

An n- or p-doped semiconductor region (2) accommodates the depletion zone (21) of an active area (3) of the semiconductor component with a vertical extension dependent upon an applied blocking voltage. The junction termination (4) for the active area (3) is constituted with a semiconductor doped oppositely to the semiconductor region (2), and is arranged immediately adjacently around the active area (3) on or in a surface (20) of the semiconductor region (2). The lateral extension (W) of the junction termination (4) is greater than the maximum vertical extension (T) of the depletion zone (21), and the semiconductor region (2) as well as the junction termination (4) are constituted with a semiconductor with a band gap of at least 2 eV.

SEMICONDUCTOR COMPONENT WITH JUNCTION TERMINATION WITH HIGH BLOCKING EFFECTIVENESS

An n or p-doped semiconductor region (2) accepts the depletion region (21) of an active section (3) of the semiconductor component with a vertical expansion depending on an applied blocking voltage. The edge termination (4) for the active region (3) takes the form of a semiconductor with the opposite doping to the semiconductor region (2) immediately adjacent to the active region (3) or in a surface (20) of the semiconductor region (2). The lateral expansion (W) of the edge termination (4) is greater than the maximum vertical expansion (T) of the depletion region (21) and the semiconductor region (2) and the edge termination (4) are formed by a semiconductor with a band spacing of at least 2 eV.

METHOD OF MANUFACTURING A SCHOTTKY DIODE ON A DIAMOND SUBSTRATE

LAYER MONOATOMIC AND SINGLE-CRYSTAL OF BIG SIZE, OUT OF CARBON OF THE DIAMOND TYPE, AND MANUFACTORING PROCESS OF THIS LAYER

Couche monoatomique et monocristalline de grande taille, en carbone de type diamant, et procédé de fabrication de cette couche. Selon l'invention, on forme un substrat monocristallin (2) en SiC terminé par un plan atomique de carbone selon une reconstruction c (2x2) et on effectue au moins un recuit du substrat, apte à transformer ce plan atomique, qui est un plan de dimères C≡C (4) de configuration sp, en un plan de dimères C-C (8) de configuration Sp3. Application à la microélectronique, l'optique, l'optoélectronique, la micromécanique et aux biomatériaux.

2차원 인장 가능하고 구부릴 수 있는 장치

... 일 측면에서, 본 발명은 인장되거나, 압축되거나, 휘어지거나 또는 달리 변형될 때에도 우수한 성능을 제공할 수 있는 반도체 또는 전자 회로들과 같은 인장 가능하고, 또한 선택적으로는 인쇄 가능한, 구성 부품들, 및 그러한 인장 가능한 구성 부품들을 제조하거나 조절할 수 있는 관련 방법들을 제공한다. 일부 응용들에 있어서 선호되는 인장 가능한 반도체들과 전자 회로들은 인장 가능할 뿐만 아니라, 가요성이고, 따라서 상당한 신장, 휨, 구부림, 또는 하나 또는 그 이상의 축을 따르는 다른 변형도 가능하다. 또한, 본 발명의 인장 가능한 반도체들 및 전자 회로들은 완전히 가요성인 전자 및 광학전자 장치들을 제공하기 위하여 광범위한 장치 구성에 적용된다.

Fabricating a device with a diamond layer

In one aspect, a method includes forming a silicon dioxide layer on a surface of a diamond layer disposed on a gallium nitride (GaN)-type layer. The method also includes etching the silicon dioxide layer to form a pattern. The method further includes etching portions of the diamond exposed by the pattern.

Schottky diode using diamond rod and method for manufacturing the same

The present invention relates to a Schottky diode using a diamond rod, which comprises: a substrate with a gate layer formed thereon; an insulating layer disposed on the gate layer, wherein the insulating layer comprises a first contact region and a second contact region; a diamond rod disposed on the insulating layer, wherein a first end of the diamond rod connects to the first contact region, and a second end of the diamond rod connects to the second contact region; a first electrode corresponding to the first contact region of the insulating layer, and covering the first end of the diamond rod; and a second electrode corresponding to the second contact region of the insulating layer, and covering the second end of the diamond rod, and a method for manufacturing the same.

A switching device

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

The purpose of the present invention is to provide a fin-integrated semiconductor device, which has a simple structure, and which is provided with excellent heat dissipating characteristics, and to provide a method for manufacturing the fin-integrated semiconductor device. This semiconductor device is provided with: a base plate having fins provided upright on a first main surface; an insulating layer formed on a second main surface of a base plate facing the first main surface of the base plate; a circuit pattern fixed to the insulating layer; and a semiconductor element bonded to the circuit pattern. A slit that penetrates the fins in the thickness direction is formed in the fins.

SEMICONDUCTOR DEVICE

Disclosed is a semiconductor device comprising a conjugative element (1). In the conjugative element (1), a depletion layer is formed within a semiconductor layer (2), whereby, upon the application of a voltage in a forward direction, electrons present in an electrode layer (4) cannot be moved to the semiconductor layer (2). Therefore, there is no possibility that a majority of holes in a semiconductor layer (3) disappear as a result of recombination with conduction electrons present within the semiconductor layer (2). In this case, the holes reach the electrode layer (4) while being diffused in the semiconductor layer (2). According to the above constitution, the conjugative element (1) can function as a good conductor to the holes without any influence of electric resistance and can allow a current in an amount equal to or larger than a semiconductor element formed of an Si or SiC semiconductor to flow. The present invention can be applied to all of semiconductor materials such as diamond ...

Semiconductor device

Doping a dopant into a diamond semiconductor causes lattice defects. The pn junction diode or the Schottky junction diode made from diamond has low break down voltage and high reverse leakage current owing to the lattice defects. A non-doped or low doped diamond layer with high resistivity is epitaxially grown between the N-type diamond layer and the p-type diamond layer in the pn junction diode or between the metal layer and the doped diamond layer in the Schottky diode. The intermediate layer heightens the break down voltage and decreases the reverse leakage current.

Nanosensors

Electrical devices comprised of nanowires are described, along with methods of their manufacture and use. The nanowires can be nanotubes and nanowires. The surface of the nanowires may be selectively functionalized. Nanodetector devices are described.

Hydrogen-terminated diamond MISFET and its manufacturing method

On the surface of a hydrogen-terminated diamond 1 formed by terminating a surface 2 of either a homoepitaxial diamond or a heteroepitaxial diamond or a surface-flattened polycrystal diamond are formed a drain-ohmic contact 4 and a source-ohmic contact 3 of gold or platinum, an insulating layer 5 formed of silicon oxide (SiOx : 1≦X≦2) and a gate electrode 6 mounted on said insulating layer, and the surface other than the element forming region is set to be an insulating region being non-hydrogen-terminated, for example, oxygen-terminated, and the elements formed on said region is being isolated.

Method for manufacturing a flexible intraocular retinal implant having doped diamond electrodes

A method for manufacturing an intraocular retinal implant including: providing a mold capable of supporting growth of a layer of doped diamond, the mold including, on one face, elements all depressed or all projecting with respect to the surface of the face, and constituting a pattern cavity for the electrodes of the implant which it is desired to obtain; producing the doped diamond electrodes by growing a layer of doped diamond in all or part of a space occupied by the pattern cavity elements; forming a first insulating layer on the face of the mold including the pattern cavity; producing interconnection lines by depositing an electrically conductive material at least in spaces not covered by the first insulating layer; forming a second insulating layer on the mold face including the pattern cavity, the second layer covering the interconnection lines, the first and second insulating layers forming a flexible plate of the implant; removing the mold.

Diamond semiconductor device and method for manufacturing the same

A diamond semiconductor device includes a substrate made of single crystal diamond; a first diamond layer, placed on the substrate, containing an impurity; a second diamond layer containing the impurity, the second diamond layer being placed on the substrate and spaced from the first diamond layer; and a third diamond layer which has a impurity content less than that of the first and second diamond layers, which acts as a channel region, and through which charges are transferred from the first diamond layer to the second diamond layer. The first and second diamond layers have a first and a second end portion, respectively, facing each other with a space located therebetween. The first and second end portions have slopes epitaxially formed depending on the orientation of the substrate. The third diamond layer lies over the slopes and a section of the substrate that is located under the space.

SEMICONDUCTOR DEVICE

The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage Vof 0.3 V to 0.7 V and a leakage current Jof 1×10A/cmto 1×10A/cmin a rated voltage V. 1. A semiconductor device , comprising:a first conductivity type semiconductor layer made of a wide bandgap semiconductor with a trench having a side wall and a bottom wall formed on a side of a surface of the semiconductor layer;a Schottky electrode formed to come into contact with the surface of the semiconductor layer;a field region surrounding the Schottky electrode; andan annular trench formed on the field region and surrounding the Schottky electrode, whereina plurality of the annular trenches are arranged at intervals, andthe width of a part sandwiched between the annular trenches adjoining each other becomes greater in proportion to an approach to the far side from the near side with respect to the Schottky electrode.2. The semiconductor device according to claim 1 , wherein a breakdown voltage Vof the semiconductor device is 700 V or more claim 1 , and{'sub': R', 'B, 'the rated voltage Vof the semiconductor device is 50 to 90% of the breakdown voltage Vthat is 700 V or more.'}3. The semiconductor device according to claim 1 , wherein on-resistance R·A of the semiconductor device is 0.3 mΩ·cmto 3 mΩ·cm.5. The semiconductor device according to claim 4 , wherein the semiconductor layer includes a second conductivity type electric-field-moderating portion that is selectively formed at the bottom wall of the trench and at the edge part of the bottom wall.6. The semiconductor device according to claim 4 , wherein the electric-field-moderating portion is formed to straddle between the edge part of the bottom wall of the trench and the side wall of the trench.7. The semiconductor device according to claim 6 , wherein ...

METHOD FOR PRODUCING A SCHOTTKY DIODE ON A DIAMOND SUBSTRATE

A method for producing a Schottky diode, including the following steps: oxygenating the surface of a semiconductive layer of monocrystalline diamond, in such a way as to replace hydrogen surface terminations of the semiconductive layer with oxygen surface terminations; and forming, by physical vapour deposition, a first conductive layer of zirconium or indium-tin oxide on the surface of the semiconductive layer. 1. A method of manufacturing a Schottky diode , comprising the steps of:a) oxygenating the surface of a single-crystal diamond semiconductor layer, to replace hydrogen surface terminations of the semiconductor layer with oxygen surface terminations: andb) forming, by physical vapor deposition, a first indium tin oxide conductive layer at the surface of the semiconductor layer.2. The method of claim 1 , wherein at step a) claim 1 , the semiconductor layer is placed in an enclosure containing oxygen at a pressure lower than the atmospheric pressure claim 1 , and is irradiated with ultraviolet light.3. The method of claim 1 , wherein the first conductive layer is formed claim 1 , at step b) claim 1 , by sputtering of an indium tin oxide target.4. The method of claim 3 , wherein claim 3 , at step b) claim 3 , the semiconductor layer and the indium tin oxide target are placed in an enclosure containing an argon plasma.5. The method of claim 3 , further comprising claim 3 , after step b) claim 3 , an anneal of recrystallization of the indium tin oxide layer at a temperature in the range from 100 to 300° C.6. The method of claim 1 , further comprising claim 1 , after step b) claim 1 , depositing at least a second conductive layer at the surface of the first conductive layer claim 1 , said conductive layers forming together an electrode of the Schottky diode.7. The method of claim 6 , wherein said at least one second conductive layer comprises a gold layer.8. The method of claim 1 , wherein the semiconductor layer P-type doped.9. The method of claim 1 , wherein the ...

CONTROLLING DIAMOND FILM SURFACES AND LAYERING

A method comprising: providing at least one first diamond film comprising polycrystalline diamond, e.g., nanocrystalline or ultrananocrystalline diamond, disposed on a substrate, wherein the first diamond film comprises a surface comprising diamond asperities and having a first diamond film thickness, removing asperities from the first diamond film to form a second diamond film having a second diamond film thickness, wherein the second thickness is either substantially the same as the first thickness, or the second thickness is about 100 nm or less thinner than the first diamond film thickness, optionally patterning the second diamond film to expose substrate regions and, optionally, depositing semiconductor material on the exposed substrate regions, and depositing a solid layer on the second diamond film to form a first layered structure. Applications include for example dielectric isolation in the semiconductor industry, as well as surface acoustic wave devices, scanning probe microscope ...

Synthesis and processing of pure and NV nanodiamonds and other nanostructures for quantum computing and magnetic sensing applications

Using processes disclosed herein, materials and structures are created and used. For example, processes can include melting amorphous carbon doped with nitrogen and carbon-13 into an undercooled state followed by quenching. Materials disclosed herein may include dopants in concentrations exceeding thermodynamic solubility limits.

Semiconductor device

An n−-type semiconductor substrate (1) includes an active region and a terminal region disposed outside the active region. A p+-type anode layer (2) is formed in a portion of an upper surface of the n−-type semiconductor substrate (1) in the active region. A plurality of p+-type guard ring layers (3) are formed in a portion of the upper surface of the n−-type semiconductor substrate (1) in the terminal region. An n+-type cathode layer (5) is formed in a lower surface of the n−-type semiconductor substrate (1). An anode electrode (6) is connected to the p+-type anode layer (2). A metallic cathode electrode (7) is connected to the n+-type cathode layer (5). A recess (8) is formed by trenching the n+-type cathode layer (5) in the terminal region. The cathode electrode (7) is also formed in the recess (8).

SEMICONDUCTOR DEVICE WITH VOLTAGE RESISTANT STRUCTURE

A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion. 124-. (canceled)25. A semiconductor device comprising:a substrate;a cell region formed in the substrate, in which a circuit element is formed;a gate trench formed in the cell region;a source region formed in the cell region around the gate trench;a first conductivity type outer peripheral portion formed on a periphery of the cell region;a concave portion formed on a surface of a part of the outer peripheral portion;a second conductivity type surface doping region formed at a periphery of the concave portion;a source pad formed over the cell region; anda surface insulating film directly contacted to the substrate and disposed over a part of the cell region and the part of the outer peripheral portion, and a thickness of the surface insulating film in the cell region from a surface of the substrate to bottom of the source pad being different from a thickness of the surface insulating film in the outer peripheral portion from the surface of the substrate to an upper surface of the surface insulating film.26. The semiconductor device according to claim 25 , wherein the thickness of the surface insulating film in the cell region is thinner than the thickness of the surface insulating film in the outer peripheral portion.27. The ...

III-V nitride semiconductor device comprising a diamond layer

The invention relates to a semiconductor device, in particular to a chemical field effect transistor (ChemFET), a high-electron mobility transistor (HEMT) and an ion-sensitive field effect transistor (ISFET), as well as a method for manufacturing the same. The semiconductor device comprises a structure, the structure comprises a substrate, a first layer comprising GaN and a second layer comprising InAlN, wherein the first and the second layer are arranged parallely to each other on the substrate, and wherein the structure comprises a third layer comprising diamond.

Diamond semiconductor devices

Semiconductor device having a deep impurity level for high temperature range operation

DIAMOND SEMICONDUCTOR AND ITS CREATING METHOD

PROBLEM TO BE SOLVED: To make controllable the electric conduction of a p-type and n-type, etc., of a thin-film diamond layer, by implanting the ions of impurity elements into the thin-film diamond layer having such a high quality that it emits ultraviolet rays at a room temperature by exciting it through the projection of an electron beam on it when specifying its thickness. SOLUTION: This diamond thin-film manufacturing apparatus 100 is an end-launch type microwave-CVD diamond synthesizing apparatus wherein a microwave is projected on a substrate 11 from the normal direction thereof. Further, the ions of impurity elements are implanted into a thin-film diamond layer formed on the substrate 11 which has such a high quality that it emits ultraviolet rays at a room temperature by exciting it through the projection of an electron beam on it when its thickness is made at least not larger than 200 nm, and its electric conduction is made controllable correspondingly to the impurity elements.

DIAMOND SEMICONDUCTOR ELEMENT AND METHOD FOR FORMING THE SAME

PROBLEM TO BE SOLVED: To provide a method for forming a diamond thin film capable of forming a high-quality diamond thin film by decreasing a crystal defect, an impurity, etc., existing in the diamond thin film. SOLUTION: A diamond is annealed at stable high pressure which recovers and eliminates a lattice defect included in a crystal to improve the diamond crystal thin film in quality. Here, "stable (diamond)" or the following "(diamond) stably" indicates a state that a diamond keeps a diamond state without graphitization. A temperature T for annealing (also called as annealing temperature) and pressure P for annealing (also called as annealing pressure) are decided within an area where the diamond can be stably annealed. This area satisfies a formula of P>0.71+0.0027T or a formula of P=0.71+0.0027T shown in Fig.21, and also satisfies a formula of P≥1.5 GPa. The area is expressed by a slant line portion in Fig.21. COPYRIGHT: (C)2011,JPO&INPIT ...

ドープダイヤモンド電極を有する可撓性眼球内網膜インプラントを製造する方法

ПРОВОДНИК ЭЛЕКТРИЧЕСКОГО ТОКА

... 1. Токопроводящий канал, по меньшей мере часть которого образована телом из материала подложки, по меньшей мере часть которого представляет собой легированный участок, на поверхность или под поверхность которого имплантированы атомы, при этом по меньшей мере часть поверхности образует низкоомную зону токопроводящего канала, по меньшей мере часть которого проходит вдоль по меньшей мере части поверхности, причем подложка представляет собой алмаз, и с наружной стороны поверхности алмаза возникает поперечная проводимость.2. Токопроводящий канал по п.1, который является частью электрической цепи.3. Токопроводящий канал по п.1, в котором тело из материала подложки является частью электронного компонента, a цепь и электронный компонент являются частями электронного устройства.4. Токопроводящий канал по п.1, в котором остальная часть электронного компонента соединена с каналом посредством соединительных элементов.5. Токопроводящий канал по п.5, в котором значение удельного сопротивления низкомной ...

Halbleitervorrichtung

Eine Halbleitervorrichtung enthält ein isolierendes Substrat (12), ein Halbleiterelement (22), das an einer oberen Oberfläche des isolierenden Substrats (12) befestigt ist, ein Gehäuse (30), das aus einem Harz ausgebildet ist und einen Rahmenabschnitt (30A) aufweist, der das Halbleiterelement (22) umgibt, einen Metallträger (40), der über dem isolierenden Substrat (12) gelegen ist und ein an dem Rahmenabschnitt (30A) befestigtes Ende aufweist, einen Niederhalteabschnitt (30C), der in der Weise von dem Metallträger (40) nach unten ausgeht, dass er eine nach oben konvexe Biegung des isolierenden Substrats (12) verhindert, und einen Klebstoff (32), der das isolierende Substrat (12) und das Gehäuse (30) miteinander verbindet.

Diamanthalbleitervorrichtung und Verfahren zu dessen Herstellung

Diamanthalbleitervorrichtung mit: einem Substrat mit einem Substratabschnitt (1), der vollständig aus einkristallinem Diamant ausgebildet ist oder der eine Vielzahl von verbundenen Diamantkristallen mit leicht voneinander verschiedenen Orientierungen beinhaltet, und der im Wesentlichen dieselben Eigenschaften wie die eines einkristallinen Substrats aufweist; einer ersten Diamantschicht (3a), die zumindest teilweise auf dem Substratabschnitt lokal angeordnet ist und einen Dotierstoff enthält; einer zweiten Diamantschicht (3b) mit dem Dotierstoff, wobei die zweite Diamantschicht zumindest teilweise auf dem Substratabschnitt lokal angeordnet ist und von der ersten Diamantschicht beabstandet ist; und einer dritten Diamantschicht (5), die einen geringeren Dotierstoffgehalt als die erste und zweite Diamantschicht aufweist, die als zwischen der ersten und der zweiten Diamantschicht angeordneter Kanalbereich wirkt, und durch die Ladungen von der ersten Diamantschicht zur zweiten Diamantschicht ...

Temperatursensor

Temperatursensorvorrichtung (10), umfassend:eine erste Elektrode (11; 31; 122),einen ersten Schichtabschnitt (13; 34; 126; 154; 192), wobei der erste Schichtabschnitt (13; 34; 126; 154; 192) in einem Temperaturbereich elektrisch im Wesentlichen nicht leitend ist,einen zweiten Schichtabschnitt (14; 35; 127), wobei der zweite Schichtabschnitt (14; 35; 127) ein dotiertes zweites Halbleitermaterial umfasst, welches in dem Temperaturbereich einen temperaturabhängigen elektrischen Widerstand aufweist, undeine zweite Elektrode (12; 32; 123; 1512; 191), undeine Messschaltung (16), welche eingerichtet ist, zur Bestimmung der Temperatur eine Kapazitätsmessung zwischen der ersten Elektrode (11; 31; 122; 198) und der zweiten Elektrode (12; 32; 123; 1512; 191) durchzuführen.

Rückwärtsleitende Halbleitervorrichtung

Eine rückwärtsleitende Halbleitervorrichtung (100) weist eine Hochkonzentrations-Anodenschicht (42) und eine Sperr-Metallschicht (52) auf, wobei die Breite der Hochkonzentrations-Anodenschicht (42) größer festgelegt ist als die Kontaktbreite zwischen der Sperr-Metallschicht (52) und der Hochkonzentrations-Anodenschicht (42), wodurch sichergestellt wird, dass die Kontaktfläche zwischen der Sperr-Metallschicht (52) und der Hochkonzentrations-Anodenschicht (42) konstant ist.

Halbleitervorrichtung

Eine Halbleitervorrichtung mit verbesserter Wärmeabstrahlung und verbessertem Isoliervermögen wird angegeben. Die Halbleitervorrichtung weist Folgendes auf: ein Halbleiterelement (2); einen Leiterrahmen (4), der an die eine Fläche des Halbleiterelements (2) gebondet ist; eine erste Isolierschicht (5), die an der anderen Fläche des Leiterrahmens (4) angeordnet ist; und eine metallische Basisplatte (6), die mit dem Leiterrahmen (4) verbunden ist, wobei die erste Isolierschicht (5) zwischen diesen angeordnet ist, wobei sich ein äußerer peripherer Bereich der ersten Isolierschicht innerhalb eines äußeren peripheren Bereichs der metallischen Basisplatte befindet, und wobei der äußere periphere Bereich der ersten Isolierschicht (5) mit einer zweiten Isolierschicht (7) bedeckt ist, die eine höhere Feuchtigkeits-Widerstandsfähigkeit und ein höheres Isoliervermögen als die erste Isolierschicht (5) aufweist, wobei der äußere periphere Bereich einen Konzentrationspunkt des elektrischen Feldes in einem ...

Befestigen von Halbleiter-auf-Diamant-Wafern zur Bauteilverarbeitung

Die vorliegende Erfindung offenbart einen Halbleiter-auf-Diamant-auf-Trägersubstrat-Wafer (55). Der Halbleiter-auf-Diamant-auf-Träger-Wafer (55) weist auf: einen Halbleiter-auf-Diamant-Wafer (40) mit einer Diamantseite und einer Halbleiterseite; ein Trägersubstrat (50), das auf der Diamantseite des Halbleiter-auf-Diamant-Wafers (40) angeordnet ist und mindestens eine Schicht mit einem niedrigeren Wärmeausdehnungskoeffizienten (CTE) als Diamant aufweistt; und eine Haftschicht (48), die zwischen der Diamantseite des Halbleiter-auf-Diamant-Wafers (40) und dem Trägersubstrat (50) angeordnet ist, um das Trägersubstrat (50) an den Halbleiter-auf-Diamant-Wafer (40) zu bonden. Der Halbleiter-auf-Diamant-auf-Trägersubstrat-Wafer (55) weist die folgenden Charakteristiken auf: eine Gesamtdickenvariation von nicht mehr als 40 µm; eine Waferdurchbiegung von nicht mehr als 100 µm; und eine Waferverwerfung von nicht mehr als 40 µm.

Leistungshalbleitervorrichtung und Leistungshalbleiterkernmodul

Es ist eine Aufgabe eine Druckkontakt-Leistungshalbleitervorrichtung und ein Leistungshalbleiterkernmodul bereitzustellen, die eingerichtet sind, ihre Größen geeignet zu reduzieren. Jedes Leistungshalbleiterkernmodul umfasst das Folgende: eine Mehrzahl von Leistungshalbleiter-Chips, welche eine Mehrzahl von selbstabschaltenden Halbleiterelementen und eine Mehrzahl von Dioden umfasst, die in einer Draufsicht nebeneinanderliegenden; und eine Mehrzahl von ersten Federn, die zwischen einer oberen Metallplatte und einer leitfähigen Abdeckplatte angeordnet ist. Die Mehrzahl von selbstabschaltenden Halbleiterelementen jedes Leistungshalbleiterkernmoduls ist in einer Draufsicht entlang einer L-förmigen Linie, oder einer kreuzförmigen Linie, oder einer T-förmigen Linie angeordnet.

METHOD FOR FORMING N-TYPE SEMICONDUCTING DIAMOND FILMS BY VAPOR PHASE TECHNIQUES

Semiconducting polycrystalline diamond electronic devices employing an insulating diamond layer

Semiconductor structures e.g. Schottkey diodes and MISFETs made of polycrystalline diamond thin films are fabricated by depositing a polycrystalline diamond film (20) on a substrate (10), a second polycrystalline diamond film (25) which is boron-doped on the first film (20) and an undoped diamond film (30) acting as an insulating layer on the boron-doped film or layer. Ion-implantation can be employed to reduce the ohmic contact resistance which enables the entire structure to be made using a deep implant to form a channel layer and so allows an insulating gate to be formed as an integral part of the device. A buried channel in the layer 25 can be doped through the use of several implantation steps through the insulating undoped layer. As a result, more active polycrystalline diamond devices which have excellent resistance and reverse voltage characteristics can be provided which have increased thermal capacity and increased range of operational environmental conditions when contrasted ...

Diamond schottky diode

Compound semiconductor device structures comprising polycrystalline CVD diamond

DIAMOND SCHOTTKY DIODE

P-type semiconductor devices

SEMICONDUCTING POLYCRYSTALLINE DIAMOND ELECTRONIC DEVICES EMPLOYING AN INSULATING DIAMOND LAYER AND METHOD OF MAKING SAME

Diamond components for quantum imaging, sensing and information processing devices

Diamond semiconductor element and process for producing the same

A process of producing a diamond thin-film includes implanting dopant into a diamond by an ion implantation technique, forming a protective layer on at least part of the surface of the ion-implanted diamond, and firing the protected ion-implanted diamond at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C. A process of producing a diamond semiconductor includes implanting dopant into each of two diamonds by an ion implantation technique and superimposing the two ion-implanted diamonds on each other such that at least part of the surfaces of each of the ion-implanted diamonds makes contact with each other, and firing the ion implanted diamonds at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C.

Semiconductor rectifier device

A semiconductor rectifier device according to an embodiment includes a semiconductor substrate of a first conductive type of a wide gap semiconductor, a semiconductor layer of the first conductive type of the wide gap semiconductor formed on an upper surface of the semiconductor substrate, wherein an impurity concentration of the semiconductor layer is between 1E+14 atoms/cm 3 and 5E+16 atoms/cm 3 inclusive, and a thickness thereof is 8 μm or more, a first semiconductor region of the first conductive type of the wide gap semiconductor formed on the semiconductor layer surface, a second semiconductor region of the second conductive type of the wide gap semiconductor formed as sandwiched by the first semiconductor regions, wherein a width of the second semiconductor region is 15 μm or more, a first electrode formed on the first and second semiconductor regions, and a second electrode formed on a lower surface of the semiconductor substrate.

Method for manufacturing diode, and diode

A semiconductor substrate having a first side and a second side made of single crystal silicon carbide is prepared. A mask layer having a plurality of openings and made of silicon oxide is formed on the second side. The plurality of openings expose a plurality of regions included in the second side, respectively. A plurality of diamond portions are formed by epitaxial growth on the plurality of regions, respectively. The epitaxial growth is stopped before the plurality of diamond portions come into contact with each other. A Schottky electrode is formed on each of the plurality of diamond portions. An ohmic electrode is formed on the first side.

ELECTRONIC FIELD EFFECT DEVICES AND METHODS FOR THEIR MANUFACTURE

Electronic field effect devices, and methods of manufacture of these electronic field effect devices are disclosed. In particular, there is disclosed an electronic field effect device which has improved electrical properties due to the formation of a highly mobile two-dimensional charge-carrier gas in a simple structure formed from diamond in combination with polar materials. 1. An electronic field effect device comprising: a first diamond layer, at least a first surface of which comprises crystalline intrinsic diamond, and', 'a second layer disposed on the first surface of the first layer, wherein the second layer is polar; wherein, 'an interface between two materials, wherein the interface is formed bythere is a discontinuity in polarization between the first layer and the second layer; andthere is a band offset between the first layer and the second layer, in the band in which the dominant charge carriers are present, such that the dominant charge carriers are confined to a planar region within the first layer and in close proximity to the interface by the combined effects of a polarization induced sheet charge and an electric field provided by the discontinuity in polarization between the first layer and the second layer, and the band offset.2. The electronic field-effect device of wherein the second layer comprises a pyroelectric layer.3. The electronic field-effect device of wherein the second layer comprises AlN or AlGaN.4. The electronic field-effect device of wherein the diamond layer comprises synthetic diamond formed by chemical vapour deposition.58-. (canceled)97. The electronic field-effect device of claim wherein the second layer is arranged so that a component of its polarization vector points away from the interface.10. The electronic field-effect device of wherein the second layer is arranged so that its polarization vector P is substantially normal to the interface.1120-. (canceled)21. The electronic field-effect device of claim 1 , further ...

PIEZOELECTRIC DEVICES AND METHODS FOR THEIR PREPARATION AND USE

Methods for fabricating a piezoelectric device are provided. The methods can include providing a substrate and forming a nanocrystalline diamond layer on a first surface of the substrate. The methods can also include depositing a piezoelectric layer on a first surface of the nanocrystalline diamond layer. 1. A method for fabricating a piezoelectric device , the method comprising:providing a substrate;forming a nanocrystalline diamond (NCD) layer on a first surface of the substrate; anddepositing a piezoelectric layer on a first surface of the nanocrystalline diamond layer.2. The method of claim 1 , wherein the substrate comprises silicon.3. The method of claim 1 , wherein the piezoelectric layer has a perovskite structure.4. The method of claim 1 , wherein the forming a nanocrystalline diamond (NCD) layer comprises using a chemical vapor deposition (CVD) technique.56.-. (canceled)7. The method of claim 1 , wherein the depositing a piezoelectric layer comprises using a pulsed laser deposition (PLD) technique.8. The method of claim 1 , wherein the piezoelectric layer comprises lead zirconate titanate (PZT).9. The method of claim 1 , wherein the piezoelectric layer comprises lead lanthanum zirconate titanate (PLZT).10. The method of claim 1 , wherein depositing the piezoelectric layer comprises exposing a piezoelectric target placed within a pulsed laser deposition (PLD) chamber to a laser source.11. The method of claim 10 , further comprising annealing the deposited piezoelectric layer.12. The method of claim 10 , wherein a deposition temperature within the PLD chamber is about 525° C. to about 600° C.13. The method of claim 12 , wherein the deposition temperature is about 550° C.14. The method of claim 10 , wherein a deposition pressure within the PLD chamber is about 0.4 mbar to about 0.6 mbar.15. A method for fabricating a piezoelectric device claim 10 , the method comprising:providing a diamond substrate; anddepositing a lead zirconate titanate (PZT) layer on a ...

Diamond Semiconductor System and Method

Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The method may include the steps of selecting a diamond semiconductor material having a surface, exposing the surface to a source gas in an etching chamber, forming a carbide interface contact layer on the surface; and forming a metal layer on the interface layer. 1. A method of fabricating diamond semiconductor , the method including the steps of:selecting a diamond semiconductor material having a surface;exposing the surface to a source gas in an etching chamber;forming a carbide interface contact layer on the surface; andforming a metal layer on the interface contact layer.2. A diamond semiconductor formed according to the method of claim 2 , wherein the diamond semiconductor material has n-type donor atoms and a diamond lattice claim 2 , wherein at least 0.16% of the donor atoms contribute conduction electrons with mobility greater than 770 cm/Vs to the diamond lattice at 100 kPa and 300K.3. A method of fabricating diamond semiconductor claim 2 , the method including the steps of:selecting a diamond semiconductor material having a surface; andexposing the surface to a source gas in an etching chamber;wherein the etching chamber is operated with an applied power within a range of 100 to 2000 watts and an external bias of greater than 50 volts.4. The method of fabricating diamond semiconductors of claim 3 , wherein the etching chambers creates a source plasma claim 3 , and the source plasma is an oxygen plasma.5. The method of fabricating diamond semiconductors of claim 3 , wherein the source gas is primarily argon.6. The method of fabricating diamond semiconductors of claim 3 , wherein the source gas is primarily a mixture of argon and oxygen.7. A diamond semiconductor formed according to the method of .8. A diamond semiconductor formed according to the method of claim 3 , wherein the diamond semiconductor material has n-type donor atoms and a diamond lattice claim 3 ...

SUPER INTEGRATED CIRCUIT CHIP SEMICONDUCTOR DEVICE

The CP555 Super Integrated Circuit Chip has a ceramic package casing made from (B4-C) Boron Carbide: a non-conducting ceramic material. The IC is connected to connector pins by microcircuits and a custom formulated bond wire. The CP555 Integrated Circuit's ceramic Boron Carbide (B4-C) outer package casing, Heterodiamond substrates and dielectric components allows these integrated circuits to reduce electro-migration to a minimum, produce superior radiation hardness, heat resistance, electromagnetic shielding, and resistance to damage from harsh elements and environments. The CP555 Integrated Circuit can be used as a CMOS, PIC or DIE microcontroller circuit or computer processor (CPU). , shows the integrated circuit package the outer package casing also in , top left. Together, the Heterodiamond (B-C-N) semiconductor substrate and dielectric components, combined with a (Cu—Au—Ag) custom formulated bond wire work synergistically to make The CP555 Super Integrated Circuit Chip a unique semiconductor device. 1. This type of semiconductor device consist of a ceramic package containing B4-C Boron carbide , a ceramic material which is obtained by decomposing B2O3 with carbon in an electric furnace , it's unique and exceptional qualities produce superior radiation hardness , heat resistance , electromagnetic shielding , and resistance to damage from harsh elements and environments.2. Heterodiamond , symbol B-C-N , is used as a substrate material in this type of integrated circuit , this semiconductor substrate , because of Heterodiamond's unique semiconductor electrical behavior , between that of a conductor and an insulator at room temperature; with the proper addition of dopant element (silicon and Gallium) , p-n junctions can be formed on Heterodiamond and can be useful to electronic components and integrated circuits that are built from p-n junctions; Heterodiamond is a super-hard compound of boron , carbon , and nitrogen.3. A bonding wire for this type of semiconductor ...

Diamond Semiconductor System and Method

Disclosed herein is a new and improved system and method for fabricating monolithically integrated diamond semiconductor. The method may include the steps of seeding the surface of a substrate material, forming a diamond layer upon the surface of the substrate material; and forming a semiconductor layer within the diamond layer, wherein the diamond semiconductor of the semiconductor layer has n-type donor atoms and a diamond lattice, wherein at least 0.16% of the donor atoms contribute conduction electrons with mobility greater than 770 cm/Vs to the diamond lattice at 100 kPa and 300K. 1. A method of fabricating a monolithically integrated diamond semiconductor , the method including the steps of:seeding the surface of a substrate material;forming a diamond layer upon the surface of the substrate material; andforming a semiconductor layer within the diamond layer,{'sup': '2', 'wherein the diamond semiconductor of the semiconductor layer has n-type donor atoms and a diamond lattice, wherein at least 0.16% of the donor atoms contribute conduction electrons with mobility greater than 770 cm/Vs to the diamond lattice at 100 kPa and 300K.'}2. The method of fabricating a monolithically integrated diamond semiconductor of claim 1 , wherein the substrate material is selected from the group consisting of silicon claim 1 , silicon oxide claim 1 , refractory metal claim 1 , glass claim 1 , and wide band gap semiconductor material.3. The method of fabricating a monolithically integrated diamond semiconductor of claim 1 , wherein the diamond layer is formed using chemical vapor deposition.4. The method of fabricating a monolithically integrated diamond semiconductor of claim 1 , wherein the diamond layer is formed at or below 450 degrees Celsius.5. A monolithically integrated diamond semiconductor device formed according to the method of .6. The monolithically integrated diamond semiconductor device of claim 5 , wherein the device is one of a group consisting of an LED claim 5 , ...

Method for manufacturing a flexible intraocular retinal implant having doped diamond electrodes

A method for manufacturing an intraocular retinal implant including: providing a mold capable of supporting growth of a layer of doped diamond, the mold including, on one face, elements all depressed or all projecting with respect to the surface of the face, and constituting a pattern cavity for the electrodes of the implant which it is desired to obtain; producing the doped diamond electrodes by growing a layer of doped diamond in all or part of a space occupied by the pattern cavity elements; forming a first insulating layer on the face of the mold including the pattern cavity; producing interconnection lines by depositing an electrically conductive material at least in spaces not covered by the first insulating layer; forming a second insulating layer on the mold face including the pattern cavity, the second layer covering the interconnection lines, the first and second insulating layers forming a flexible plate of the implant; removing the mold.

Method and system for ultra miniaturized packages for transient voltage suppressors

A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The transient voltage suppressor (TVS) assembly includes a semiconductor die including a contact surface on a single side of the die, the die further including a substrate comprising a layer of at least one of an electrical insulator material, a semi-insulating material, and a first wide band gap semiconductor having a conductivity of a first polarity, at least a TVS device including a plurality of wide band gap semiconductor layers formed on the substrate; a first electrode coupled in electrical contact with the TVS device and extending to the contact surface, and a second electrode electrically coupled to the substrate extending to the contact surface.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor element substrate, wherein an electrode pattern is formed on one surface of an insulating substrate and a back-surface electrode is formed on the other surface of the insulating substrate; a stress-relaxation adhesive layer made of resin that covers at least a part of a portion of the surface of the insulating substrate where the electrode pattern and the back-surface electrode are not formed; and a semiconductor element affixed, using a bonding material, to the surface of the electrode pattern opposite the insulating substrate, and a first sealing resin member which covers the semiconductor element and the semiconductor element substrate, and a modulus of elasticity of the stress-relaxation adhesive layer is lower than that of the first sealing resin member. 110-. (canceled)11. A semiconductor device , comprising:a semiconductor-element substrate, wherein an electrode pattern is formed on one surface of an insulating substrate and a back-surface electrode is formed on the other surface of the insulating substrate;a stress-relaxation adhesive layer made of resin which covers at least a part of a portion of the surface of the insulating substrate where the electrode pattern and the back-surface electrode are not formed and a part of portion of a surface of the electrode pattern;a semiconductor element affixed, via a bonding material, to the surface of the electrode pattern opposite the insulating substrate; anda first sealing resin member which covers the semiconductor element and the semiconductor-element substrate,wherein a coefficient of linear thermal expansion of the first sealing resin member is closer to a coefficient of linear thermal expansion of the electrode pattern than a coefficient of linear thermal expansion of the insulating substrate, and a modulus of elasticity of the stress-relaxation adhesive layer is lower than a modulus of elasticity of the first sealing resin member.12. A semiconductor device ...

SEMICONDUCTOR DEVICE

A semiconductor device including: a semiconductor element; a lead frame connected to the semiconductor element; a metal base plate mounted on the lead frame via a first insulation layer; and a second insulation layer disposed on the opposite side of the metal base plate face on which the first insulation layer is disposed; wherein the first insulation layer is an insulation layer whose heat-dissipation performance is higher than that of the second insulation layer, and the second insulation layer is an insulation layer whose insulation performance is the same as that of the first insulation layer or higher than that of the first insulation layer. 113-. (canceled)14: A semiconductor device , comprising:a semiconductor element;a lead frame connected to the semiconductor element;a metal base plate mounted on the lead frame via a first insulation layer; anda second insulation layer disposed on the opposite side of the metal base plate face on which the first insulation layer is disposed; whereina characteristic combination of the first insulation layer and the second insulation layer in a first case comprises:the first insulation layer is an insulation layer whose heat-dissipation performance is higher than that of the second insulation layer, and the second insulation layer is an insulation layer whose insulation performance is same as that of the first insulation layer or higher than that of the first insulation layer;an another characteristic combination of the first insulation layer and the second insulation layer in a second case comprises:the second insulation layer is an insulation layer whose insulation performance is higher than that of the first insulation layer, and the first insulation layer is an insulation layer whose heat-dissipation performance is same as that of the second insulation layer or higher than that of the second insulation layer.15: A semiconductor device according to claim 14 , wherein the first insulation layer is an insulation layer whose ...

DIAMOND AND DIAMOND COMPOSITE MATERIAL

A structure having: a substrate and a diamond layer on the substrate having diamond nanoparticles. The diamond nanoparticles are formed by colliding diamond particles with the substrate. A method of: directing an aerosol of submicron diamond particles toward a substrate, and forming on the substrate a diamond layer of diamond nanoparticles formed by the diamond particles colliding with the substrate. 1. A structure comprising:a substrate; and 'wherein the diamond nanoparticles are formed by colliding diamond particles with the substrate.', 'a diamond layer on the substrate comprising diamond nanoparticles;'}2. The structure of claim 1 , wherein the substrate comprises ZnS claim 1 , ZnSe claim 1 , a semiconductor claim 1 , an insulator claim 1 , or an infrared window.3. The structure of claim 1 , wherein the diamond nanoparticles are 10-50 nm in size.4. The structure of claim 1 , wherein the diamond nanoparticles are bonded together by mechanochemical reactions.5. The structure of claim 1 , wherein the diamond layer is a diamond composite layer.6. The structure of claim 5 , wherein the diamond composite layer comprises germanium claim 5 , ZnS claim 5 , ZnSe claim 5 , a dielectric claim 5 , or a semiconductor.7. The structure of claim 5 , wherein the percentage of diamond in the diamond composite layer varies with the depth within the diamond composite layer.8. The structure of claim 1 , wherein the structure comprises:a plurality of the diamond layers; anda spacer layer between each adjacent pair of the diamond layers.9. The structure of claim 8 , wherein the spacer layers comprise germanium claim 8 , ZnSe claim 8 , an infrared transparent material claim 8 , a metal claim 8 , a semiconductor claim 8 , an insulator claim 8 , a dielectric claim 8 , an amorphous material claim 8 , or a polycrystalline material.10. The structure of claim 1 , wherein the structure further comprises:an interface layer between the diamond layer and the substrate.11. The structure of claim ...

DIAMOND AND DIAMOND COMPOSITE MATERIAL

A structure having: a substrate and a diamond layer on the substrate having diamond nanoparticles. The diamond nanoparticles are formed by colliding diamond particles with the substrate. A method of: directing an aerosol of submicron diamond particles toward a substrate, and forming on the substrate a diamond layer of diamond nanoparticles formed by the diamond particles colliding with the substrate. 1. A structure comprising:a substrate; and 'wherein the diamond nanoparticles are formed by colliding diamond particles with the substrate.', 'a diamond layer on the substrate comprising diamond nanoparticles;'}2. The structure of claim 1 , wherein the substrate comprises ZnS claim 1 , ZnSe claim 1 , a semiconductor claim 1 , an insulator claim 1 , a metal claim 1 , a single crystal material claim 1 , a non-single crystal material claim 1 , or an infrared window.3. The structure of claim 1 , wherein the diamond nanoparticles are 10-200 nm in size.4. The structure of claim 1 , wherein the diamond nanoparticles are bonded together by mechanochemical reactions.5. The structure of claim 1 , wherein the diamond layer comprises at least 1 wt. % diamond.6. The structure of claim 1 , wherein the diamond layer comprises at least 10 wt. % diamond.7. The structure of claim 1 , wherein the diamond layer is a diamond composite layer.8. The structure of claim 7 , wherein the diamond composite layer comprises germanium claim 7 , ZnS claim 7 , ZnSe claim 7 , a dielectric claim 7 , a semiconductor claim 7 , YbF claim 7 , YF claim 7 , BaF claim 7 , CeF claim 7 , HfO claim 7 , YO claim 7 , GaS claim 7 , germanium gallium sulfide claim 7 , gallium claim 7 , a polymer claim 7 , or silica.9. The structure of claim 7 , wherein the percentage of diamond in the diamond composite layer varies with the depth within the diamond composite layer.10. The structure of claim 1 , wherein the structure comprises:a plurality of the diamond layers; anda spacer layer between each adjacent pair of the ...

WAFER PRECURSOR PREPARED FOR GROUP III NITRIDE EPITAXIAL GROWTH ON A COMPOSITE SUBSTRATE HAVING DIAMOND AND SILICON CARBIDE LAYERS, AND SEMICONDUCTOR LASER FORMED THEREON

A high power, wide-bandgap device is disclosed that exhibits reduced junction temperature and higher power density during operation and improved reliability at a rated power density. The device includes a diamond substrate for providing a heat sink with a thermal conductivity greater than silicon carbide, a single crystal silicon carbide layer on the diamond substrate for providing a supporting crystal lattice match for wide-bandgap material structures that is better than the crystal lattice match of diamond, and a Group III nitride heterostructure on the single crystal silicon carbide layer for providing device characteristics. 1. A wide bandgap device comprising:a diamond substrate;a buffer layer disposed over the diamond substrate;a first layer disposed over the buffer layer; anda second layer disposed over the first layer.2. A wide bandgap device according to claim 1 , wherein the buffer layer comprises Aluminum Nitride.3. A wide bandgap device according to claim 1 , wherein the first layer comprises Gallium Nitride.4. A wide bandgap device according to claim 1 , wherein the second layer comprises Aluminum Gallium Nitride.5. A wide bandgap device according to claim 1 , wherein the wide bandgap device is a high electron mobility transistor.6. A wide bandgap device according to claim 5 , wherein the wide bandgap device includes source claim 5 , gate claim 5 , and drain contacts.7. A wide bandgap device according to claim 5 , wherein the second layer forms a heterostructure with the first layer.8. A wide bandgap device comprising:a diamond substrate;a buffer layer disposed over the diamond substrate;a first layer disposed over the buffer layer; anda second layer disposed over the first layer for forming a heterostructure with the first layer.9. A wide bandgap device according to claim 8 , wherein the buffer layer comprises Aluminum Nitride.10. A wide bandgap device according to claim 8 , wherein the first layer comprises Gallium Nitride.11. A wide bandgap device ...

ELECTRICAL CONDUCTOR

The invention provides circuits and electronic devices which comprise an electrical flow path, at least part of which is formed by a body of a substrate material at least part of which is a doped part having a surface and implanted atoms at or below the surface, at least part of the surface defining a low resistance section of the electrical flow path. 1. An electrical flow path , at least part of which is formed by a body of a substrate material at least part of which is a doped part having a surface and implanted atoms at or below the surface , at least part of the surface defining a low resistance section of the electrical flow path at least part of which extends along at least part of the surface the substrate being a diamond and lateral conduction occurring externally to the surface of the diamond.2. An electrical flow path as claimed in claim 1 , which is part of a circuit.3. An electrical flow path as claimed in claim 1 , in which the body of substrate material is part of an electronic component and the circuit and the electronic component are parts of an electronic device.4. An electrical flow path as claimed in claim 3 , in which a remainder of the electronic component is connected to the flow path by connectors.5. An electrical flow path as claimed in claim 1 , in which the resistivity of the low resistance section of the electrical flow path is less than about 2×10Ω-m.6. An electrical flow path as claimed in claim 5 , in which the resistivity of the low resistance section of the electrical flow path is less than about 5×10Ω-m.7. An electrical flow path as claimed in claim 1 , in which the implanted atoms are selected from oxygen claim 1 , hydrogen claim 1 , lithium claim 1 , nitrogen claim 1 , fluorine claim 1 , chlorine claim 1 , sulphur claim 1 , phosphorus claim 1 , arsenic and combinations thereof.8. An electrical flow path as claimed in claim 1 , in which at least some of the implanted atoms are at depths of between about 0.1 Å and 5000 Å below the ...

DIAMOND SENSORS, DETECTORS, AND QUANTUM DEVICES

A thin plate of synthetic single crystal diamond material, the thin plate of synthetic single crystal diamond material having: a thickness in a range 100 nm to 50 μιη; a concentration of quantum spin defects greater than 0.1 ppb (parts-per-billion); a concentration of point defects other than the quantum spin defects of below 200 ppm (parts-per-million); and wherein at least one major face of the thin plate of synthetic single crystal diamond material comprises surface termination species which have zero nuclear spin and/or zero electron spin. 1. A thin plate of synthetic single crystal diamond material , the thin plate of synthetic single crystal diamond material having:a thickness in a range 100 nm to 50 μm;{'sup': '−', 'a concentration of negatively charged nitrogen-vacancy defects (NV) equal to or greater than 100 ppb (parts-per-billion);'}{'sup': '−', 'a concentration of point defects other than the NV defects of below 200 ppm (parts-per-million);'}a total nitrogen concentration equal to or greater than 10 ppm;a concentration of all non-nitrogen point defects equal to or less than 1 ppm;wherein at least one major face of the thin plate of synthetic single crystal diamond material comprises surface termination species which have zero nuclear spin and/or zero electron spin; and{'sup': '−', 'sub': '2', 'wherein the product of the concentration of NV defects and decoherence time Tin the thin plate of synthetic single crystal diamond material is at least 0.1 ppm μs.'}23-. (canceled)4. A thin plate of synthetic single crystal diamond material according to claim 1 , wherein the thickness of the thin plate of synthetic single crystal diamond material is in a range: 500 nm to 30 μm claim 1 , 1 μm to 20 μm claim 1 , or 5 μm to 10 μm.5. A thin plate of synthetic single crystal diamond material according to claim 1 , wherein the concentration of NV defects is equal to or greater than 1 ppm claim 1 , 5 ppm claim 1 , 10 ppm claim 1 , or 30 ppm.6. A thin plate of synthetic ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a channel layer formed on a substrate, an insulating layer formed in contact with the channel layer, an impurity-doped first semiconductor layer formed on an opposite side of the insulating layer from the channel layer, an impurity-doped second semiconductor layer formed on an opposite side of the first semiconductor layer from the insulating layer, and a gate electrode formed on an opposite side of the second semiconductor layer from the first semiconductor layer. A quotient of an impurity density of the first semiconductor layer divided by a relative permittivity of the first semiconductor layer is greater than a quotient of an impurity density of the second semiconductor layer divided by a relative permittivity of the second semiconductor layer. 1. A semiconductor device comprising:a channel layer formed on a substrate;an insulating layer formed in contact with said channel layer;an impurity-doped first semiconductor layer formed on an opposite side of said insulating layer from said channel layer;an impurity-doped second semiconductor layer formed on an opposite side of said first semiconductor layer from said insulating layer; anda gate electrode formed on an opposite side of said second semiconductor layer from said first semiconductor layer,wherein a quotient of an impurity density of said first semiconductor layer divided by a relative permittivity of said first semiconductor layer is greater than a quotient of an impurity density of said second semiconductor layer divided by a relative permittivity of said second semiconductor layer.2. The semiconductor device according to claim 1 , wherein when an on-voltage is applied to said gate electrode so that a saturation current flows through the semiconductor device claim 1 , a depletion layer forms to occupy entire said first semiconductor layer and a portion of said second semiconductor layer.3. The semiconductor device according to claim 2 , wherein said impurity density of said ...

SEMICONDUCTOR DEVICE

A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion. 1. A semiconductor device comprising:a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion; anda gate electrode buried in the gate trench via a gate insulating film,the outer peripheral portion having a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, andthe semiconductor device further comprising a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.2. The semiconductor device according to claim 1 , wherein the semiconductor device further comprises a surface insulating film disposed in a manner extending across the cell portion and the outer peripheral portion claim 1 , and in the cell portion claim 1 , formed to be thinner than a part in the outer peripheral portion.3. The semiconductor device according to claim 1 , wherein the semiconductor device further comprises a gate finger to make contact with the gate electrode claim 1 , andthe gate trench includes a line-shaped trench that runs across the gate finger under the gate ...

SEMICONDUCTOR DEVICE

A semiconductor device according to the present invention includes a semiconductor layer, a trench formed selectively in an obverse surface portion of the semiconductor layer and defining a unit cell of predetermined shape in the obverse surface portion, a second conductivity type layer formed to conform to a portion or an entirety of an inner surface of the trench, an obverse surface layer of a first conductivity type formed so as to be exposed from an obverse surface of the semiconductor layer in the unit cell, a reverse surface layer of the first conductivity type formed so as to be exposed from a reverse surface of the semiconductor layer, a drift layer of the first conductivity type formed between the obverse surface layer and the reverse surface layer of the semiconductor layer and being of lower concentration than the obverse surface layer and the reverse surface layer, a first electrode contacting the obverse surface layer and forming an ohmic contact with the obverse surface layer, and a second electrode contacting the reverse surface layer and forming an ohmic contact with the reverse surface layer. 1. A semiconductor device comprising:a semiconductor layer;a trench formed selectively in an obverse surface portion of the semiconductor layer and defining a unit cell of predetermined shape in the obverse surface portion;a second conductivity type layer formed to conform to a portion or an entirety of an inner surface of the trench;an obverse surface layer of a first conductivity type formed so as to be exposed from an obverse surface of the semiconductor layer in the unit cell;a reverse surface layer of the first conductivity type formed so as to be exposed from a reverse surface of the semiconductor layer;a drift layer of the first conductivity type formed between the obverse surface layer and the reverse surface layer of the semiconductor layer and being of lower concentration than the obverse surface layer and the reverse surface layer;a first electrode ...

Doped Diamond Semi-Conductor and Method of Manufacture

A doped diamond semiconductor and method of production using a laser is disclosed herein. As disclosed, a dopant and/or a diamond or sapphire seed material may be added to a graphite based ablative layer positioned below a confinement layer, the ablative layer also being graphite based and positioned above a backing layer, to promote formation of diamond particles having desirable semiconductor properties via the action of a laser beam upon the ablative layer. As disclosed, the diamond particles formed by either the machine or method of confined pulsed laser deposition disclosed may be arranged as semiconductors, electrical components, thermal components, quantum components and/or integrated circuits.

HETEROJUNCTION DEVICES AND METHODS FOR FABRICATING THE SAME

Current conducting devices and methods for their formation are disclosed. Described are vertical current devices that include a substrate, an n-type material layer, a plurality of p-type gates, and a source. The n-type material layer disposed on the substrate and includes a current channel. A plurality of p-type gates are disposed on opposite sides of the current channel. A source is disposed on a distal side of the current channel with respect to the substrate. The n-type material layer comprises beta-gallium oxide. 1a substrate;an n-type material layer disposed on the substrate, wherein the n-type material layer includes a current channel;a plurality of p-type gates disposed on opposite sides of the current channel; anda source disposed on a distal side of the current channel with respect to the substrate,wherein the n-type material layer comprises beta-gallium oxide.. A vertical current conducting device, comprising: The present application relates generally to heterojunction devices and methods for fabricating the same.In the world of semiconductors, Silicon (Si) is the most widely used. It properties lends itself to use in digital logic, memory, RF, power switching and optoelectronics. However, Si has fundamental limitations. For instance, in power switching applications, the operating voltage is limited by the electric field strength at which breakdowns occurs (E). Eis directly related to the bandgap of the material. Si has an Eof approximate 0.3 MV/cm, which limits its use in power switching applications. β-GaO, however, has a larger bandgap of approximately 4.9 eV, and an Eof 8 MV/cm. This corresponds to a power figure of merit (using the Baliga figure of merit) of approximately 3,444 as compared to 1 for Si. While SiC and GaN offer higher bandgaps than Si, their respective power figures of merit are 160 and 870, far less than β-GaO. However, β-GaOis not without limitations. As is typical of oxide semiconductors, it is unlikely that p-type doping can be ...

DIAMOND SUBSTRATE AND METHOD FOR MANUFACTURING DIAMOND SUBSTRATE

The crystal plane in the interior of the diamond substrate has a curvature higher than 0 kmand equal to or lower than 1500 kmby preparing a base substrate, forming a plurality of pillar-shaped diamonds formed of diamond single crystals on one side of the base substrate, causing diamond single crystals to grow from tips of each pillar-shaped diamond, coalescing each of the diamond single crystals grown from the tips of each pillar-shaped diamond to form a diamond substrate layer, separating the diamond substrate layer from the base substrate, and manufacturing the diamond substrate from the diamond substrate layer. 1. A diamond substrate formed of diamond single crystals , wherein a crystal plane in an interior of the diamond substrate has a curvature , and the curvature is higher than 0 kmand equal to or lower than 1500 km.2. The diamond substrate according to claim 1 , wherein the curvature is higher than 0 kmand equal to or lower than 400 km.3. The diamond substrate according to claim 1 , wherein the curvature is higher than 0 kmand equal to or lower than 200 km.4. The diamond substrate according to claim 1 , wherein a shape of the diamond substrate in an in-plane direction has a circular shape or a circular shape having an orientation flat plane claim 1 , anda diameter of the diamond substrate is equal to or larger than 0.4 inches.5. The diamond substrate according to claim 4 , wherein the diameter is equal to or larger than 2 inches.6. The diamond substrate according to claim 4 , wherein the diameter is equal to or larger than 2 inches and equal to or smaller than 8 inches.7. The diamond substrate according to claim 1 , wherein the crystal plane has an (001) plane.8. The diamond substrate according to claim 1 , wherein a surface roughness Ra of a surface of the diamond substrate is lower than 1 nm.9. The diamond substrate according to claim 8 , wherein the surface roughness Ra is equal to or lower than 0.1 nm.10. The diamond substrate according to claim 1 , ...

Method for synthesizing carbon materials from carbon agglomerates containing carbine/carbynoid chains

Provided is a method for synthesizing carbon agglomerates containing metastable carbyne/carbynoid chains; a method for synthesizing carbon or carbon compound allotropes from the agglomerates containing metastable carbyne/carbynoid chains; and the uses of the methods. The method for synthesizing carbon agglomerates containing metastable carbyne/carbynoid chains includes the following steps: a) forming carbon vapor precursors, containing carbine/carbynoid chains, by decomposing a carbon gas selected from among CH 4 , C 2 H 2 , C 2 H 4 , gaseous toluene, and benzene in the form of vapors at a temperature T such that 1 500° C.<T≦3 000° C.; and b) condensing the carbon vapor precursors, obtained in Step a), on the surface of a substrate, the temperature Ts of which is less than the temperature T. The invention is particularly of use in the field of electronics.

TRANSPARENT NANOCRYSTALLINE DIAMOND COATINGS AND DEVICES

A method for coating a substrate comprises producing a plasma ball using a microwave plasma source in the presence of a mixture of gases. The plasma ball has a diameter. The plasma ball is disposed at a first distance from the substrate and the substrate is maintained at a first temperature. The plasma ball is maintained at the first distance from the substrate, and a diamond coating is deposited on the substrate. The diamond coating has a thickness. Furthermore, the diamond coating has an optical transparency of greater than about 80%. The diamond coating can include nanocrystalline diamond. The microwave plasma source can have a frequency of about 915 MHz. 1. A method for coating a substrate , comprising:producing a plasma ball using a microwave plasma source in the presence of a mixture of gases, the plasma ball having a diameter;disposing the plasma ball at a first distance from the substrate, the substrate maintained at a first temperature; andmaintaining the plasma ball at the first distance from the substrate for a first time;depositing a diamond coating on the substrate, the diamond coating having a thickness,wherein, the diamond coating has an optical transparency of greater than about 80 percent.2. The method of claim 1 , wherein the diamond coating includes nanocrystalline diamond.3. The method of claim 1 , wherein the substrate and or thin film has a thickness less than a thickness threshold claim 1 , the thickness enabling the substrate to have an optical transparency of greater than 80%.4. The method of claim 3 , wherein the substrate includes at least one of gallium nitride claim 3 , aluminum gallium nitride claim 3 , gallium arsenide claim 3 , germanium claim 3 , silicon claim 3 , silicon nitride and silicon carbide.5. The method of claim 1 , wherein the microwave plasma source has a frequency of about 915 MHz.6. The method of claim 1 , wherein the diameter of the plasma ball is the range of about 15 cms to about 30 cms.7. The method of claim 3 , ...

SEMICONDUCTOR DEVICE AND POWER CONVERSION DEVICE

According to the present invention, a semiconductor device includes a semiconductor chip, resistance of which changes in accordance with temperature, an external resistor connected in series with the semiconductor chip and a detector configured to detect, while a first voltage is applied between both ends of a series circuit formed by the semiconductor chip and the external resistor, a second voltage applied between both ends of the external resistor, wherein the detector calculates a temperature of the semiconductor chip from the second voltage. 1. A semiconductor device , comprising:a semiconductor chip, resistance of which changes in accordance with temperature, the semiconductor chip including a switch having a gate terminal;an external resistor connected to the gate terminal in series with the semiconductor chip; anda detector configured to detect, while a first voltage is applied between both ends of a series circuit formed by the semiconductor chip and the external resistor, a second voltage present between both ends of the external resistor, whereinthe detector is coupled across the ends of the external resistor to calculate a temperature of the semiconductor chip from the second voltage.2. (canceled)3. The semiconductor device according to claim 1 , wherein the switch of the semiconductor chip switches when the first voltage is supplied to the series circuit.4. The semiconductor device according to claim 3 , wherein the detector calculates the temperature of the semiconductor chip from a time it takes for a voltage applied to the semiconductor chip to reach a preset level after a start of switching.5. The semiconductor device according to claim 3 , wherein the detector calculates the temperature of the semiconductor chip from a slope of a voltage curve of a voltage applied to the semiconductor chip at a start of switching.6. The semiconductor device according to claim 3 , wherein the detector calculates the temperature of the semiconductor chip from a time ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor layer including a wide bandgap semiconductor, the semiconductor layer having an element region and an outer peripheral region surrounding an outer periphery of the element region when viewed two-dimensionally, forming a step portion surrounding the outer periphery of the element region in the outer peripheral region, and forming a metal layer along the step portion. The step portion has a sidewall recessed downward from a main surface of the element region in a cross section parallel to a thickness direction of the semiconductor layer, and the metal layer extends to cover at least a portion of the sidewall. The method of manufacturing a semiconductor device further includes the step of dividing the semiconductor layer into the element regions on an outside of the step portion when viewed from the element region. 1. A method of manufacturing a semiconductor device , comprising the steps of:preparing a semiconductor layer including a wide bandgap semiconductor, said semiconductor layer having an element region and an outer peripheral region surrounding an outer periphery of said element region when viewed two-dimensionally;forming a step portion surrounding said outer periphery of said element region in said outer peripheral region; andforming a metal layer along said step portion,said step portion having a sidewall recessed downward from a main surface of said element region in a cross section parallel to a thickness direction of said semiconductor layer, said metal layer extending to cover at least a portion of said sidewall,said method further comprising the step of dividing said semiconductor layer into said element regions on an outside of said step portion when viewed from said element region.2. The method of manufacturing a semiconductor device according to claim 1 , further comprising the step of forming a first insulating film on said semiconductor layer claim 1 , ...

METHOD FOR PRODUCING A MOS STACK ON A DIAMOND SUBSTRATE

The invention relates to a method for producing a component comprising a conductive grid insulated from a semiconductor monocrystalline diamond substrate by an insulating region, comprising the following steps: a) oxygenating the surface of the substrate so as to replace the hydrogen surface terminations of the substrate with oxygen surface terminations; and b) forming the insulating region on the surface of the substrate by repeated monatomic layer deposition. 1. A method of manufacturing a component comprising a conductive gate insulated from a single-crystal diamond semiconductor substrate by an insulating region , comprising the steps of:a) oxygenating the surface of the substrate to replace hydrogen surface terminations of the substrate with oxygen surface terminations; andb) forming the insulating region at the surface of the substrate by atomic layer deposition.2. The method of claim 1 , wherein at step a) claim 1 , the substrate is placed in an enclosure containing dioxygen at a pressure lower than the atmospheric pressure claim 1 , and is irradiated with ultraviolet light.3. The method of claim 1 , wherein the insulating region is made of aluminum oxide.4. The method of claim 3 , wherein claim 3 , at step b) claim 3 , the forming of each atom monolayer of aluminum oxide comprises a phase of placing into contact the component surface with an atmosphere comprising trimethyl-aluminum claim 3 , followed by a phase of placing into contact the component surface with an atmosphere comprising water vapor.5. The method of claim 1 , wherein the gate is made of metal.6. The method of claim 1 , wherein the gate is made of aluminum.7. The method of claim 1 , wherein the substrate comprises an upper epitaxial layer made of P-type doped single-crystal diamond.8. A component comprising a semiconductor substrate made of doped single-crystal diamond coated with a conductive gate insulated by an insulating region claim 1 , wherein a surface region of the substrate located ...

Stretchable Form of Single Crystal Silicon for High Performance Electronics on Rubber Substrates

The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices. 1. A stretchable semiconductor element comprising:a flexible substrate having a supporting surface; anda semiconductor structure having a curved internal surface, wherein at least a portion of said curved internal surface is bonded to said supporting surface of said flexible substrate.2. The stretchable semiconductor element of wherein said semiconductor structure is a bent semiconductor structure.3. The stretchable semiconductor element of wherein said bent semiconductor structure has a wave-shaped claim 2 , wrinkled claim 2 , coiled or buckled conformation.4. The stretchable semiconductor element of wherein said bent semiconductor structure is under strain.5. The stretchable semiconductor element of wherein said bent semiconductor structure is under strain selected over the range of about 1% to about 30%.6. The stretchable semiconductor element of wherein said curved internal surface has at least one convex region claim 1 , at least one concave region or a combination of at least one convex region and at least one concave region.7. The stretchable semiconductor element of wherein said curved internal surface has a contour profile comprising a periodic wave or an aperiodic wave.8. The stretchable semiconductor element of wherein said bent semiconductor structure has a conformation comprising a ...

SEMICONDUCTOR DEVICE

A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, and a surface insulating film disposed in a manner extending across the cell portion and the outer peripheral portion, and in the cell portion, formed to be thinner than a part in the outer peripheral portion. 1. A semiconductor device comprising:a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion; anda surface insulating film disposed in a manner extending across the cell portion and the outer peripheral portion, and in the cell portion, formed to be thinner than a part in the outer peripheral portion.2. The semiconductor device according to claim 1 , wherein the semiconductor device comprises:a gate trench formed at a surface side of the cell portion; anda gate electrode buried in the gate trench via a gate insulating film,the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, andthe semiconductor device further comprises a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.3. The semiconductor device according to claim 2 , wherein the semiconductor device further comprises a gate finger to make contact with the gate electrode claim 2 , andthe gate trench includes a line-shaped trench that runs across the gate finger under the gate finger.4. The semiconductor device according to claim 2 , wherein the gate trench includes an inner trench at a portion lateral to which the channel is formed at ON-time claim 2 , and an outer trench constituted of an extension portion of the inner trench claim 2 , disposed outside with respect to the inner trench claim 2 , andthe semiconductor device further includes a ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor layer including a wide bandgap semiconductor, the semiconductor layer having an element region and an outer peripheral region surrounding an outer periphery of the element region when viewed two-dimensionally, forming a step portion surrounding the outer periphery of the element region in the outer peripheral region, and forming a metal layer along the step portion. The step portion has a sidewall recessed downward from a main surface of the element region in a cross section parallel to a thickness direction of the semiconductor layer, and the metal layer extends to cover at least a portion of the sidewall. The method of manufacturing a semiconductor device further includes the step of dividing the semiconductor layer into the element regions on an outside of the step portion when viewed from the element region. 111.-. (canceled)12. A semiconductor device comprising:a semiconductor layer including a wide bandgap semiconductor, said semiconductor layer having an element region and an outer peripheral region surrounding an outer periphery of said element region when viewed two-dimensionally;a step portion formed in said outer peripheral region and surrounding said outer periphery of said element region; anda metal layer formed along said step portion,said step portion having a sidewall recessed downward from a main surface of said element region in a cross section parallel to a thickness direction of said semiconductor layer, said metal layer extending to cover at least a portion of said sidewall.13. The semiconductor device according to claim 12 , further comprising a first insulating film formed on said semiconductor layer claim 12 , whereinsaid metal layer covers an end face of said first insulating film.14. The semiconductor device according to claim 12 , whereinan inner peripheral surface including said sidewall is continuous with an outer peripheral end face of said ...

DIAMOND NANO RESONATOR SEMI CONDUCTOR

A Diamond Nano Resonator Semiconductor, This is an Technology Light years Ahead of the 21Century. Diamond Sensors for your mobile Devices, such as a Cell Phone, Tablet, your Car, Buses, Commercial Airplane, Jets, Rockets, Satellites, Trains, Televisions, Radio, Diamond™ Smart Watch, Power Plants, Cell Phone Tower, everything will run on Synthetic Diamonds, Because nothing can transfer Heat and Conduct Electricity like Synthetic Diamonds, these Diamonds™ Coated Semiconductor runs on tiny Synthetic Nano Resonators in any size and shape, with Encryption Software in an Pseudonymous Format. All Figures will have this ability. And some will run on Anti Matter. 1. A Diamond Nano Resonator Semiconductor Comprising:A Diamond Coated Synthetic Diamond, and Sensor for Cars, Trucks, Trains, Diamonds Coated Smart Watch. Power Plants, cell phones tower, mother board circuits, commercial air planes, Jet planes, And Rockets, Satellites, cell phones, Tablets, three way radio, Data Centers, the commercial planes, and jets, and rockets will run on anti matter; the servers and drives will run on synthetic diamonds, Because there is nothing that transfer heat like Synthetic Diamonds with Encryption Software in a Pseudonymous Format, the diamonds can work any electronic device.2. As in The Device of further comprising capable of Cruise Ships , Helicopters , all running on Synthetic Diamonds; insulin pumps , EKG , pace makers for the heart , any medical equipment , will have Encryption Software in a pseudonymous format.3. A Electronic Kane as in with wireless ear plugs with a camera and sensor to see when an oncoming car is near claim 1 , or the light changes claim 1 , the sensor can detect cars claim 1 , the wireless earplugs will tell The blind person what to do claim 1 , when walk or stop this Al Kane is for the Blind claim 1 , Phone ready.4. A Smart Television as in with better picture from synthetic diamonds resonators with USB ports in the front and back claim 1 , a user can a USB ...

Semiconductor Structure or Device Integrated with Diamond

Semiconductor devices that include a semiconductor structure integrated with one or more diamond material layers. A first diamond material layer is formed on a bottom surface and optionally, the side surfaces of the semiconductor structure. In some embodiments, at least a portion of the semiconductor structure is embedded in the diamond. An electrical device can be formed on a top surface of the semiconductor structure. A second diamond material layer can be formed on the top surface of the semiconductor structure. The semiconductor structure can include a III-nitride material such as GaN, which can be embedded within a the first diamond material layer or encased by the first and/or second diamond material layer. 1. A material structure , comprising:a semiconductor material structure comprising at least one semiconductor material layer; anda first diamond material layer disposed on a bottom surface of the semiconductor material;wherein a lateral length of the semiconductor material structure is configured to reduce a compressive strain in the semiconductor material structure resulting from the presence of the diamond material layer thereon.2. The material structure according to claim 1 , wherein the semiconductor material structure includes at least one III-nitride semiconductor material layer.3. The material structure according to claim 2 , wherein the III-nitride semiconductor material comprises GaN.4. The material structure according to claim 1 , wherein the first diamond material layer extends along at least one side surface of the semiconductor material structure so that at least one semiconductor material layer in the semiconductor material structure is embedded in the first diamond material layer.5. The material structure according to claim 1 , further comprising a second diamond material layer disposed on a top surface of the semiconductor material structure.6. The material structure according to claim 5 , wherein one of the first and second diamond material ...

Power Electronics Assemblies Having a Semiconductor Device with Metallized Embedded Cooling Channels

A power electronics assembly having a semiconductor device that includes a first device surface opposite a second device surface, a semiconductor substrate layer that extends from the first device surface to a substrate-drift interface, a semiconductor drift layer that extends from the substrate-drift interface towards the second device surface, and a semiconductor fluid channel is positioned within the semiconductor substrate layer of the semiconductor device. Further, the semiconductor fluid channel includes an inner surface. Moreover, a fluid channel metallization layer is positioned along the inner surface of the semiconductor fluid channel. 1. A power electronics assembly comprising: a first device surface opposite a second device surface;', 'a semiconductor substrate layer extending from the first device surface to a substrate-drift interface;', 'a semiconductor drift layer extending from the substrate-drift interface towards the second device surface; and', 'a semiconductor fluid channel positioned within the semiconductor substrate layer of the power electronic semiconductor device, wherein the semiconductor fluid channel comprises an inner surface; and, 'a power electronic semiconductor-device comprisinga fluid channel metallization layer positioned along the inner surface of the semiconductor fluid channel.2. The power electronics assembly of claim 1 , wherein:the semiconductor fluid channel extends from the first device surface of the power electronic semiconductor device to a termination location located within the semiconductor substrate layer of the power electronic semiconductor device; andthe inner surface of the semiconductor fluid channel comprises a first wall portion and a second wall portion spaced apart from the first wall portion by a channel width.3. The power electronics assembly of claim 2 , wherein the channel width between the first wall portion and the second wall portion is uniform between the first device surface and the termination ...

SEMICONDUCTOR DEVICE AND CIRCUIT HAVING THE SAME

In a semiconductor device with a wide gap semiconductor, a gate insulating film is made of a material having a barrier against a minor carrier in an n-type body layer and having no barrier against a minor carrier in a p-type drift layer. As a result, in the semiconductor device with the wide gap semiconductor, a reduction in a conduction loss can be achieved while realizing an improvement in blocking resistance and securing reliability of the gate insulating film. 1. A semiconductor device with a wide gap semiconductor , comprising:a vertical MISFET including:a semiconductor substrate that includes a back surface layer having a first conductivity type, arranged on a back surface side, and made of the wide gap semiconductor with a high impurity concentration and a drift layer having the first conductivity type, arranged on a front surface side, and made of the wide gap semiconductor with a lower impurity concentration than the back surface layer;a body layer having a second conductivity type, arranged over the drift layer, and made of the wide gap semiconductor;a source region having the first conductivity type, arranged in an upper layer portion of the body layer, and made of the wide gap semiconductor having a higher impurity concentration than the drift layer;a trench gate structure that is arranged in a trench disposed from a surface of the source region to a depth deeper than the body layer, and includes a gate insulating film arranged on an inner wall surface of the trench and a gate electrode arranged on the gate insulating film;a source electrode that is electrically connected to the source region; anda drain electrode that is electrically connected to the back surface layer of the semiconductor substrate on the back surface side, wherein:the gate insulating film is made of a material having a barrier against a minor carrier in the body layer and having no barrier against a minor carrier in the drift layer.2. The semiconductor device according to claim 1 , ...

Diamond Semiconductor Device

An electrical device comprising a substrate of diamond material and elongate metal protrusions extending into respective recesses in the substrate. Doped semiconductor layers, arranged between respective protrusions and the substrate, behave as n type semiconducting material on application of an electric field, between the protrusions and the substrate, suitable to cause a regions of positive space charge within the semiconductor layers. 1. An electrical device comprising:a substrate of diamond material;at least one elongate first electrically conductive portion extending into a respective recess in said substrate; andat least one doped semiconducting region, arranged between at least one respective said first electrically conductive portion and said substrate, and adapted to behave as an n type semiconducting material on application of an electric field, between said first electrically conductive portion and said substrate, suitable to cause a region of positive space charge within the semiconducting region,wherein at least one recess further comprises at least one inclined distal surface defining a point, wherein at least one doped semiconducting region is arranged on a respective inclined distal surface.2. The device of claim 1 , wherein at least one said semiconducting region includes diamond.3. The device of claim 1 , wherein at least one said semiconducting region includes at least one donor dopant to impart an n-type semiconducting characteristic to said region.4. The device of claim 3 , wherein at least one said semiconducting region includes a plurality of dopant materials to impart an n-type semiconducting characteristic to said region.5. The device of according to claim 3 , wherein at least one said dopant is a group I element.6. The device of claim 3 , wherein at least one said dopant is a group V element.7. The device of claim 3 , wherein at least one said dopant is a group VI element.8. The device of claim 1 , wherein at least one said first ...

LATERAL FIN STATIC INDUCTION TRANSISTOR

Presented is a lateral fin static induction transistor including a semi conductive substrate, source and drain regions extending from an optional buffer layer of same or varied thickness supported by the semi conductive substrate, a semi conductive channel electrically coupling the source region to the drain region of the transistor, a portion of the semi conductive channel being a fin and having a face covered by a gated structure, thereby defining a gated channel within the semi conductive channel, the semi conductive channel further including a drift region electrically coupling the gated channel to the drain region of the transistor. 115.-. (canceled)16. A transistor comprising:source and drain regions disposed on a substrate;a fin disposed between the source and drain regions, the fin being at least partially covered by a conductive structure and a dielectric layer, the dielectric layer electrically insulating the conductive structure from the fin;wherein the source and drain regions comprise diamond doped with a P-type dopant, and the fin comprises diamond doped with a P-type dopant, wherein the P-type dopant concentration of the fin is less than the P-type dopant concentration of the source and drain regions.17. The transistor of claim 16 , wherein the source and drain regions comprise P-type diamond doped at a first amount; and whereinthe fin comprises P-type diamond doped at a second amount, the second amount being less than the first amount.18. The transistor of claim 17 , wherein the P-type diamond doped at the first amount is diamond doped with a boron concentration of at least 10cm; and the P-type diamond doped at the second amount is diamond doped with a boron concentration of 10cmor less.19. A transistor comprising:a source region,a drain region, ada buffer layer, the source and drain regions being next to and on the buffer layer;a semi conductive channel formed between the source and drain regions, a portion of the semi conductive channel comprising ...

SEMICONDUCTOR DEVICE

A higher-current device is implemented by increasing cross-sectional areas of terminals while securing solderability during mounting. The device makes securing of a creepage distance between terminals compatible with a reduction in package size. A semiconductor device is provided with a package , a semiconductor circuit , a control circuit , a plurality of main terminals and control terminals . Each main terminal is configured of a plurality of subterminals S, S and S arranged at mutually neighboring positions and projecting from the package . Distal end portions of the subterminals S, S and S making up the same main terminal are bent toward a mounting surface on which the semiconductor device is mounted and the bending positions of the subterminals S, S and S are configured to differ between the mutually neighboring subterminals S and S, and subterminals S and S 1. A semiconductor device comprising:a package making up a contour;a semiconductor circuit that is accommodated in the package and controls a main current according to a control signal from outside;a control terminal that projects from the package and inputs a control signal to the semiconductor circuit; anda plurality of main terminals that are terminals that carry a main current to the semiconductor circuit and have different functions for the semiconductor circuit,wherein at least one main terminal of the main terminals are configured of a plurality of subterminals projecting from the package at mutually neighboring positions, anddistal end portions of the subterminals making up the same main terminal are bent toward a mounting surface on which the semiconductor device is mounted and bending positions of the subterminals are caused to differ between the mutually neighboring subterminals.2. The semiconductor device according to claim 1 , wherein an interval size between two mutually neighboring subterminals making up the same main terminal is set to be smaller than an interval size between two mutually ...

CONVERSION OF CARBON INTO N-TYPE AND P-TYPE DOPED DIAMOND AND STRUCTURES

Using processes disclosed herein, materials and structures are created and used. For example, processes can include melting boron nitride or amorphous carbon into an undercooled state followed by quenching. Exemplary new materials disclosed herein can be ferromagnetic and/or harder than diamond. Materials disclosed herein may include dopants in concentrations exceeding thermodynamic solubility limits. A novel phase of solid carbon has structure different than diamond and graphite. 1. A large area single crystal film comprising n-type doped diamond having a concentration of n-type dopants that exceeds thermodynamic solubility limits.2. N-type doped diamond having a concentration of n-type dopants that exceeds thermodynamic solubility limits.3. A process comprising:doping amorphous carbon with n-type and/or p-type dopants;melting the doped amorphous carbon into an undercooled state; andquenching the melted amorphous carbon from the undercooled state to create n-type and/or p-type doped diamond.4. The process of claim 3 , wherein the n-type and/or p-type dopants are incorporated into electrically active substitutional sites of the created diamond with concentrations exceeding solubility limits via solute trapping.5. The process of claim 3 , further comprising:before the melting, depositing the amorphous carbon as a film on a substrate.6. The process of claim 5 , further comprising:using the substrate as a template for epitaxial growth of the created n-type and/or p-type doped diamond.7. The process of claim 3 , wherein the created n-type and/or p-type doped diamond is a nanodot claim 3 , nanodiamond claim 3 , microdiamond claim 3 , nanoneedle claim 3 , microneedle claim 3 , or large area single crystal film.8. The process of claim 3 , wherein the melting comprises:melting the doped amorphous carbon into an undercooled state by a laser pulse in an environment at ambient temperature and pressure.9. The process of claim 3 , wherein the quenching comprises:quenching the ...

METHOD TO FABRICATE MICRO AND NANO DIAMOND DEVICES

A method including forming a diamond material on the surface of a substrate; forming a first contact and a separate second contact; and patterning the diamond material to form a nanowire between the first contact and the second contact. An apparatus including a first contact and a separate second contact on a substrate; and a nanowire including a single crystalline or polycrystalline diamond material on the substrate and connected to each of the first contact and the second contact. 1. An apparatus comprising:a first contact and a separate second contact on a substrate; anda nanowire comprising a single crystalline or polycrystalline diamond material on the substrate and connected to each of the first contact and the second contact.2. The apparatus of claim 1 , wherein a diameter of the nanowire is 400 nanometers or less.3. The apparatus of claim 1 , wherein the first contact and the second contact are disposed on diamond material.4. The apparatus of claim 1 , wherein the nanowire is connected to the diamond material on which the first contact and the second contact are disposed.5. The apparatus of claim 1 , wherein the substrate comprises a semiconductor material.6. The apparatus of claim 1 , wherein the substrate comprises a dielectric material. This application is a divisional application of co-pending utility application U.S. patent application Ser. No. 13/598,152, filed Aug. 29, 2012, entitled “Method to Fabricate Micro and Nano Diamond Devices” which claims priority to and the benefit of the filing of U.S. Provisional Patent Application No. 61/529,067, filed Aug. 30, 2011. Both of the aforementioned applications are incorporated herein by reference.This invention was developed under Contract DE-AC04-94AL85000 between Sandia Corporation and the U.S. Department of Energy. The U.S. Government has certain rights in this invention.Nanowires.The properties of bulk diamond such as its wide band gap, negative electron affinity, chemical and biological inertness, ...

Semiconductor device having a breakdown voltage holding region

A semiconductor device of the present invention is a semiconductor device having a semiconductor layer comprising a wide band gap semiconductor, wherein the semiconductor layer includes: a first conductivity-type source region, a second conductivity-type channel region and a first conductivity-type drain region, which are formed in this order from the surface side of the semiconductor layer; a source trench lying from the surface of the semiconductor layer through the source region and the channel region to the drain region; a gate insulating film formed so as to contact the channel region; a gate electrode facing the channel region with the gate insulating film interposed therebetween; and a first breakdown voltage holding region of a second conductivity type formed selectively on the side face or the bottom face of the source trench, and the semiconductor device includes a barrier formation layer, which is joined with the drain region in the source trench, for forming, by junction with the drain region, a junction barrier lower than a diffusion potential of a body diode formed by p-n junction between the channel region and the drain region.

POWER-SEMICONDUCTOR ELEMENT DRIVING CIRCUIT

A driving circuit including: a voltage detector that detects the sum voltage of a positive bias voltage and a negative bias voltage, the negative bias voltage or the positive bias voltage; and a switching element that is connected to the control terminal of a power element and the negative side of a negative-voltage power supply; wherein, when the value of the detection target voltage becomes lower than a voltage setting value or when a voltage between the control terminal and the reference terminal in the power element increases in a state where the value of the detection target voltage is lower than the voltage setting value, the voltage detector turns on the switching element to thereby supply, between the above terminals in the power element, a voltage of 0V or lower. 1. A power-semiconductor element driving circuit for driving a power semiconductor element , comprising:a positive-voltage power supply for supplying, between a control terminal and a reference terminal in the power semiconductor element, a positive bias voltage;a negative-voltage power supply for supplying, between the control terminal and the reference terminal in the power semiconductor element, a negative bias voltage, a positive side of which is connected to a negative side of said positive-voltage power supply;a gate driving circuit that supplies, based on a control signal of a control circuit, either the positive bias voltage for turning on the power semiconductor element or the negative bias voltage for turning off the power semiconductor element, between the control terminal and the reference terminal in the power semiconductor element;a voltage detector that detects a detection target voltage that is a sum voltage of the positive bias voltage and the negative bias voltage, the negative bias voltage or the positive bias voltage; anda switching element that is connected to the control terminal of the power semiconductor element and a negative side of the negative-voltage power supply; ...

METHOD FOR GALLIUM NITRIDE ON DIAMOND SEMICONDUCTOR WAFER PRODUCTION

A GaN on diamond wafer and method for manufacturing the same is provided. The method comprising: disposing a GaN device or wafer on a substrate, having a nucleation layer disposed between the substrate and a GaN layer; affixing the device to a handling wafer; removing the substrate and substantially all the nucleation layer; and bonding the GaN layer to a diamond substrate. 1. A GaN on Diamond wafer , the system comprising:a diamond substrate;a layer of GaN bonded on said substrate at a low temperature, said layer of GaN being substantially free of a nucleation layer.2. The wafer of wherein said GaN layer is not greater than 0.2 μm thick.3. The wafer of claim 1 , wherein said GaN interfaces with said diamond substrate only in localized areas proximate to active devices.4. The wafer of wherein coefficient of thermal expansion mismatch between said GaN layer and said diamond substrate is minimized.5. The wafer of claim 1 , further comprising GaN devices disposed on said layer of GaN prior to the bonding of said GaN layer to said substrate.6. A method for manufacturing a GaN on Diamond device claim 1 , the method comprising:disposing a GaN device on a substrate, having a nucleation layer disposed between said sapphire substrate and a GaN layer;affixing said device to a handling wafer;removing said sapphire substrate and substantially all said nucleation layer;bonding said GaN layer to a diamond substrate.7. The method of wherein said substrate is a substrate material selected from the group of materials consisting of Si claim 6 , SiC claim 6 , and Sapphire.8. The method of further comprising thinning said GaN layer prior to bonding said GaN device to said diamond substrate.9. The method of further comprising removing a portion of said GaN layer to an InAlN etch stop layer.10. The method of wherein said bonding comprises bonding said GaN layer to said diamond substrate with a low-temperature claim 5 , low thermal resistance bond.11. The method of wherein said bond ...

MOTOR DRIVE DEVICE, ELECTRIC BLOWER, ELECTRIC VACUUM CLEANER, AND HAND DRYER

A motor drive device includes a single-phase inverter which is an inverter including a plurality of switching elements. The inverter converts a direct-current voltage output from a direct-current power supply into an alternating-current voltage, by operation of the plurality of switching elements operating, and applies the alternating-current voltage to a motor. The motor drive device includes a control power supply outputting power having a voltage lower than the direct-current voltage, by using the direct-current voltage. The motor drive device includes a drive signal generation unit driven by the power. The drive signal generation unit generates drive signals driving the plurality of switching elements, and outputs the generated drive signals to the plurality of switching elements. The motor drive device includes a power supply switch operating so as to allow supply of the power from the control power supply to the drive signal generation unit when a rotation speed of the motor is higher than a threshold. The power supply switch operates so as to stop the supply of the power from the control power supply to the drive signal generation unit when the rotation speed is lower than the threshold. 1. A motor drive device comprising:an inverter including a plurality of switching elements, the inverter converting a direct-current voltage output from a direct-current power supply into an alternating-current voltage by operation of the plurality of switching elements, and applying the alternating-current voltage to a motor;a control power supply outputting power having a voltage lower than the direct-current voltage, by using the direct-current voltage;a first signal generation unit driven by the power, the first signal generation unit generating drive signals driving the plurality of switching elements, and outputting the generated drive signals to the plurality of switching elements; anda power supply switch operating so as to allow supply of the power from the control ...

WIDE BANDGAP INSULATED GATE SEMICONDUCTOR DEVICE

A wide bandgap insulated gate semiconductor device includes a semiconductor substrate made of semiconductor having a bandgap wider than silicon; n drift layer over the semiconductor substrate; p-channel regions selectively disposed over the drift layer; n semiconductor regions selectively disposed in respective surfaces in the channel regions; a plurality of p base regions in contact with bottoms of the respective channel regions; a protruding drift layer portion that is n-type region interposed between the p-channel regions and the p base regions thereunder; a gate electrode formed, through a gate insulating film, on the protruding drift layer portion and on respective surfaces of the p-channel regions; a source electrode in contact with the n semiconductor regions in the channel regions; and a p floating region inside the protruding drift layer portion, having side faces respectively facing side faces of the second conductivity type base regions, wherein respective gaps between the p base regions and the p floating region defined by the respective side faces have a wide portion and a narrow portion. 1. A wide bandgap insulated gate semiconductor device , comprising:a semiconductor substrate made of semiconductor having a bandgap wider than silicon;a first conductivity type drift layer over the semiconductor substrate, said drift layer having a low impurity concentration;a plurality of second conductivity type channel regions selectively disposed over the drift layer;first conductivity type semiconductor regions selectively disposed in respective surfaces in said channel regions, said first conductivity type semiconductor regions having a high impurity concentration;a plurality of second conductivity type base regions in contact with bottoms of the respective channel regions, said base regions having a high impurity concentration;a protruding drift layer portion that is a first conductivity type region interposed between said plurality of channel regions and said ...

MULTI-LAYER SEMICONDUCTOR DEVICE STRUCTURE

One embodiment of the instant disclosure provides a semiconductor structure that comprises: a first device layer including a first active layer disposed over a substrate and a first gate layer disposed on the active layer, where at least one of the first active layer and the first gate layer includes a first layer alignment structure; a first bounding layer disposed over the first device layer, the first bounding layer including an opening arranged to detectably expose the first layer alignment structure; and a second device layer disposed over the bounding layer including a second layer alignment structure, where the second layer alignment structure is substantially aligned to the first layer alignment structure through the opening. 1. A semiconductor device structure comprising:a substrate;a first device layer formed over the substrate including a first active layer and a first gate layer, the first device layer defining a first transistor, wherein an alignment structure is patterned in the first active layer and the first gate layer;a dielectric layer formed over the first device layer, wherein the dielectric layer includes an opening over each of the alignment structures; and 'wherein the second device layer is patterned using a mask layer, wherein the mask layer includes corresponding structures that are aligned relative to the alignment structures of the first device layer, and wherein the alignment structures are detectable via the opening during the patterning of the second device layer.', 'a second device layer formed over the dielectric layer including a second active layer and a second gate layer, the second device layer defining a second transistor,'}2. The semiconductor device structure of claim 1 , wherein the corresponding structures in the second device layer includes i) a first feature substantially aligned to the alignment structure in the first active layer of the first device layer and ii) a second feature substantially aligned to the alignment ...

SEMICONDUCTOR DEVICE

According to an aspect of the present disclosure, a semiconductor device includes a semiconductor substrate, a lower electrode provided on the semiconductor substrate, an insulating film that is provided on the semiconductor substrate and surrounds the lower electrode and a metal film that is provided on the lower electrode and includes a convex portion on an upper surface thereof, wherein the convex portion includes a first portion extending in a first direction parallel to an upper surface of the semiconductor substrate, and a second portion extending in a second direction that is parallel to the upper surface of the semiconductor substrate and intersects the first direction, and the metal film is thinner than the insulating film. 1. A semiconductor device comprising:a semiconductor substrate;a lower electrode provided on the semiconductor substrate;an insulating film that is provided on the semiconductor substrate and surrounds the lower electrode; anda metal film formed of Ni—P that is provided on the lower electrode and includes a convex portion on an upper surface thereof,wherein the convex portion includes a first portion extending in a first direction parallel to an upper surface of the semiconductor substrate, and a second portion extending in a second direction that is parallel to the upper surface of the semiconductor substrate and intersects the first direction, andthe metal film is thinner than the insulating film.2. The semiconductor device according to claim 1 , wherein the convex portion is provided at an outer peripheral portion of the metal film along the insulating film.3. A semiconductor device comprising:a semiconductor substrate;a lower electrode provided on the semiconductor substrate;an insulating film that is provided on the semiconductor substrate, surrounds the lower electrode and forms an outer edge of a chip; anda metal film formed of Ni—P that is provided on the lower electrode and includes a convex portion on an upper surface thereof, ...

POWER SEMICONDUCTOR MODULE AND POWER UNIT

A power semiconductor module includes: a plurality of semiconductor element substrates disposed on the same plane, each of which includes an insulating substrate with a front-side electrode formed on one of the surfaces of an insulator plate and a back-side electrode formed on the other surface of the insulator plate and a power semiconductor element fixed on a surface of the front-side electrode; and a wiring member that electrically connects with each other the semiconductor element substrates adjacent to each other; and the semiconductor element substrates and the wiring member are molded with mold resin; wherein the mold resin is provided with a recessed part, between the insulating substrates adjacent to each other, which is not filled with the resin constituting the mold resin to a predetermined depth from the side of the back-side electrode. 1. A power semiconductor module , comprising:a plurality of semiconductor element substrates disposed on the same plane, each of which includes an insulating substrate with a front-side electrode formed on one of the surfaces of an insulator plate and a back-side electrode formed on the other surface of the insulator plate and a power semiconductor element fixed on a surface of the front-side electrode; anda wiring member that electrically connects with each other the semiconductor element substrates adjacent to each other;the semiconductor element substrates and the wiring member being molded with mold resin in such a way that at least a plurality of back-side electrodes disposed is exposed over the entire surfaces thereof; whereinthe mold resin is provided with a recessed part, between the insulating substrates adjacent to each other, which is not filled with the resin constituting the mold resin to a predetermined depth from the side of the back-side electrode.2. A power semiconductor module according to claim 1 , wherein the predetermined depth is greater than the thickness of the insulating substrate.3. A power ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device according to an embodiment includes an i-type or a p-type first diamond semiconductor layer, an n-type second diamond semiconductor layer provided on the first diamond semiconductor layer, a mesa structure and an n-type first diamond semiconductor region provided on the side surface. The mesa structure includes the first diamond semiconductor layer, the second diamond semiconductor layer, a top surface with a plane orientation of ±10 degrees or less from a {100} plane, and a side surface inclined by 20 to 90 degrees with respect to a direction of <011>±20 degrees from the {100} plane. The first diamond semiconductor region is in contact with the second diamond semiconductor layer and has an n-type impurity concentration lower than an n-type impurity concentration of the second diamond semiconductor layer. 1. A semiconductor device comprising:an i-type or a p-type first diamond semiconductor layer;an n-type second diamond semiconductor layer provided on the first diamond semiconductor layer; the first diamond semiconductor layer,', 'the second diamond semiconductor layer,', 'a top surface with a plane orientation of ±10 degrees or less from a {100} plane, and', 'a side surface inclined by 20 to 90 degrees with respect to a direction of <011>±20 degrees from the {100} plane; and, 'a mesa structure including'}an n-type first diamond semiconductor region provided on the side surface, the first diamond semiconductor region being in contact with the second diamond semiconductor layer and having an n-type impurity concentration lower than an n-type impurity concentration of the second diamond semiconductor layer.2. The device according to claim 1 , further comprising:a p-type third diamond semiconductor layer provided on the first diamond semiconductor layer opposite to the second diamond semiconductor layer, the third diamond semiconductor layer having a p-type impurity concentration higher than a p-type impurity concentration of the first diamond ...

SEMICONDUCTOR MODULE AND SEMICONDUCTOR MODULE MANUFACTURING METHOD

A semiconductor module includes a semiconductor element made of a wide-bandgap semiconductor, the semiconductor element having an upper surface with an edge, a buffer member that covers the edge of the upper surface of the semiconductor element, and a sealing resin that seals the semiconductor element and the buffer member. The buffer member has a thickness equal to or larger than 50 μm. 1. A semiconductor module , comprising:a semiconductor element made of a wide-bandgap semiconductor, the semiconductor element having an upper surface with an edge;a buffer member that covers said edge; anda sealing resin that seals the semiconductor element and the buffer member,wherein the buffer member has a thickness equal to or larger than 50 μm.2. The semiconductor module according to claim 1 , whereinthe semiconductor element has a rectangular shape in a plan view of the semiconductor module and having edges at four corners of the upper surface, andthe buffer member covers at least the four corners of the upper surface of the semiconductor element.3. The semiconductor module according to claim 1 , wherein the semiconductor element is made of one of silicon carbide (SiC) claim 1 , gallium nitride (GaN) or diamond.4. The semiconductor module according to claim 1 , wherein the buffer member contains at least one of polyimide claim 1 , polyamide or polyamide-imide as a main component.5. The semiconductor module according to claim 1 , wherein the buffer member has an elasticity coefficient lower than an elasticity coefficient of the sealing resin.6. The semiconductor module according to claim 1 , wherein the buffer member covers an entire circumference at the upper surface including the edge of the semiconductor element.7. The semiconductor module according to claim 1 , wherein the buffer member has an elasticity coefficient in a range of 0.5×10GPa to 3 GPa.8. The semiconductor module according to claim 1 , wherein the sealing resin contains at least one of epoxy claim 1 , ...

STACK COMPRISING SINGLE-CRYSTAL DIAMOND SUBSTRATE

There is provided a novel stack that includes a single-crystal diamond substrate having a coalescence boundary, yet effectively uses the coalescence boundary. A stack comprising at least a semiconductor drift layer stacked on a single-crystal diamond substrate having a coalescence boundary, wherein the coalescence boundary of the single-crystal diamond substrate is a region that exhibits, in a Raman spectrum at a laser excitation wavelength of 785 nm, a full width at half maximum of a peak near 1332 cmdue to diamond that is observed to be broader than a full width at half maximum of the peak exhibited by a region different from the coalescence boundary, the coalescence boundary has a width of 200 μm or more, and the semiconductor drift layer is stacked on at least the coalescence boundary. 1. A stack comprising at least a semiconductor drift layer stacked on a single-crystal diamond substrate having a coalescence boundary , wherein{'sup': '−1', 'the coalescence boundary of the single-crystal diamond substrate is a region that exhibits, in a Raman spectrum at a laser excitation wavelength of 785 nm, a full width at half maximum of a peak near 1332 cmdue to diamond that is observed to be broader than a full width at half maximum of the peak exhibited by a region different from the coalescence boundary,'}the coalescence boundary has a width of 200 μm or more, andthe semiconductor drift layer is stacked on at least the coalescence boundary.2. The stack according to claim 1 , wherein a P+ conductive layer and the semiconductor drift layer are stacked in this order on the coalescence boundary.3. The stack according to claim 2 , wherein an electrode is further stacked on the semiconductor drift layer.4. A power semiconductor device comprising the stack according to .5. A method for producing a stack according to claim 1 , comprising the steps of:preparing a single-crystal diamond substrate having a coalescence boundary; andstacking a semiconductor drift layer on at least ...

SEMICONDUCTOR DEVICE, INTELLIGENT POWER MODULE AND POWER CONVERSION APPARATUS

The present invention relates to a semiconductor device and it is an object of the present invention to provide a semiconductor device that makes it easy to change a specification on driving of a power semiconductor element or control of a protection operation thereof. The semiconductor device includes a power semiconductor element, a main electrode terminal of the power semiconductor element, a sensor section that emits a signal corresponding to a physical state of the power semiconductor element, a sensor signal terminal connected to the sensor section, a drive terminal that supplies power to drive the power semiconductor element and a case that accommodates the power semiconductor element, the main electrode terminal, the sensor section, the sensor signal terminal and the drive terminal, and the sensor signal terminal and the drive terminal are provided so as to be connectable from outside the case. 1. A semiconductor device comprising:a power semiconductor element;a main electrode terminal of the power semiconductor element;a sensor section that emits a signal corresponding to a physical state of the power semiconductor element;a sensor signal terminal connected to the sensor section;a drive terminal that supplies power to drive the power semiconductor element; anda case that accommodates the power semiconductor element, the main electrode terminal, the sensor section, the sensor signal terminal and the drive terminal,wherein the sensor signal terminal and the drive terminal are provided so as to be connectable from outside the case.2. The semiconductor device according to claim 1 , wherein the physical state is a temperature.3. The semiconductor device according to claim 1 , wherein the physical state is a current.4. The semiconductor device according to claims 1 , wherein the physical state is a voltage.5. The semiconductor device according to claims 1 , wherein the sensor signal terminal and the drive terminal are disposed inside the case and top ends of the ...

METHOD FOR PREPARING DIAMOND-BASED FIELD EFFECT TRANSISTOR, AND CORRESPONDING FIELD EFFECT TRANSISTOR

Disclosed are a preparation method for a diamond-based field effect transistor and a field effect transistor, relating to the technical field of semi-conductors. Said method comprising: forming a conductive layer on the upper surface of a diamond layer; the diamond layer being a high-resistance layer; manufacturing an active region mesa on the diamond layer; manufacturing, on the conductive layer, a source electrode on a first region corresponding to a source electrode region, and manufacturing, on the conductive layer, a drain electrode on a second region corresponding to a drain electrode region; depositing, on the conductive layer, a photocatalyst dielectric layer on the upper surface of a third region corresponding to a source and gate region, and depositing, on the conductive layer, the photocatalyst dielectric layer on the upper surface of a fourth region corresponding to a gate and drain region; illuminating the photocatalyst dielectric layer; depositing, on the conductive layer, a gate dielectric layer on a fifth region corresponding to gate electrode region, manufacturing a gate electrode on the upper surface of the gate dielectric layer. The present invention can reduce the on-resistance of devices. 1. A method for preparing a diamond-based field effect transistor , comprising:forming a conductive layer on an upper surface of a diamond layer, wherein the diamond layer is a high-resistance layer;manufacturing an active region mesa on the diamond layer;manufacturing a source electrode on a first region of the conductive layer corresponding to a source region;manufacturing a drain electrode on a second region of the conductive layer corresponding to a drain region;depositing a photocatalyst dielectric layer on an upper surface of a third region of the conductive layer corresponding to a source-to-gate region;depositing a photocatalyst dielectric layer on an upper surface of a fourth region of the conductive layer corresponding to a gate-to-drain region; ...

Power Semiconductor Device and Method

A power semiconductor device includes a semiconductor body having a front side surface, and a first passivation layer arranged above the front side surface. The first passivation layer is a polycrystalline diamond layer. 1. A power semiconductor device , comprisinga semiconductor body having a front side surface; anda first passivation layer arranged above the front side surface,wherein the first passivation layer is a polycrystalline diamond layer.2. The power semiconductor device of claim 1 , wherein the polycrystalline diamond layer comprises crystals having a diameter of at least 10 nm.3. The power semiconductor device of claim 1 , wherein a thickness of the first passivation layer is in a range from 30 nm to 2000 nm.4. The power semiconductor device of claim 1 , wherein the polycrystalline diamond layer has a thermal conductivity of at least 1200 W/(K m).5. The power semiconductor device of claim 1 , wherein the polycrystalline diamond layer has a specific heat capacity of at least 400 J/(kg K).6. The power semiconductor device of claim 1 , wherein the polycrystalline diamond layer has an electrical resistivity of at least 10Ohm cm.7. The power semiconductor device of claim 1 , wherein the polycrystalline diamond layer has a dielectric strength of at least 1500 kV/mm.8. The power semiconductor device of claim 1 , wherein the first passivation layer is arranged at least partially above an edge termination structure of the power semiconductor device.9. The power semiconductor device of claim 8 , wherein the edge termination structure comprises a doped crystalline semiconductor region that is in contact with at least a portion of the first passivation layer.10. The power semiconductor device of claim 9 , wherein the doped crystalline semiconductor region comprises at least one of a junction termination extension region and a guard ring.11. The power semiconductor device of claim 1 , wherein the first passivation layer is arranged at least partially in an active ...

Semiconductor device

A semiconductor device according to an embodiment includes: a first diamond semiconductor layer of a first conductivity type including a main surface having a first plane orientation; a trench structure formed in the first diamond semiconductor layer; a second diamond semiconductor layer formed on the first diamond semiconductor layer in the trench structure and having a lower dopant concentration than the first diamond semiconductor layer; a third diamond semiconductor layer of a second conductivity type formed on the second diamond semiconductor layer and having a higher dopant concentration than the second diamond semiconductor layer; a first electrode electrically connected to the first diamond semiconductor layer; and a second electrode electrically connected to the third diamond semiconductor layer.

Diamond Semiconductor System and Method

Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The system may include a diamond material having n-type donor atoms and a diamond lattice, wherein 0.16% of the donor atoms contribute conduction electrons with mobility greater than 770 cm2/Vs to the diamond lattice at 100 kPa and 300K. The method of fabricating diamond semiconductors may include the steps of selecting a diamond material having a diamond lattice; introducing a minimal amount of acceptor dopant atoms to the diamond lattice to create ion tracks; introducing substitutional dopant atoms to the diamond lattice through the ion tracks; and annealing the diamond lattice. 1. (canceled)2. (canceled)3. (canceled)4. (canceled)5. A method of fabricating diamond semiconductors , the method including the steps of:selecting a diamond material having a diamond lattice, forming a diamond layer on a silicon dioxide layer;introducing acceptor dopant atoms to the diamond lattice to create pathways;introducing substitutional dopant atoms to the diamond lattice through the pathways; andannealing the diamond lattice to remove the pathways;{'sup': 22', '3, 'wherein the introduction of the acceptor dopant atoms does not create a critical density of more than 10/cmof vacancies in the diamond layer.'}6. The method of claim 5 , wherein the diamond material is intrinsic diamond.7. The method of claim 5 , wherein the acceptor dopant atoms are introduced at 293 to 298 degrees Kelvin.8. The method of claim 5 , wherein the acceptor dopant claim 5 , atoms are boron.9. The method of claim 5 , wherein the amount of acceptor dopant atoms is between 5×10/cmand 5×10/cm.10. The method of claim 5 , wherein the substitutional dopant atoms are introduced at or below 78 degrees Kelvin.11. The method of claim 5 , wherein the substitutional dopant atoms are introduced at less than 500 keV.12. The method of claim 5 , wherein the substitutional dopant atoms are introduced at less than 140 keV and at a ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

An object is to provide a technology capable of suppressing a crack of a crystalline nitride layer which is generated due to a stress caused by difference in thermal expansion coefficients between a crystalline nitride and diamond. A semiconductor device includes a crystalline nitride layer, a structure containing silicon, and a diamond layer. The structure is disposed on a first main surface of the crystalline nitride layer. The diamond layer is disposed at least on a lateral portion of the structure and has a void between the diamond layer and the first main surface of the crystalline nitride layer. The void is a stress absorbing space, for example. 1: A semiconductor device , comprising:a crystalline nitride layer;a structure comprising silicon disposed on a first main surface of the crystalline nitride layer; anda diamond layer disposed at least on a lateral portion of the structure and having a void between the diamond layer and the first main surface of the crystalline nitride layer.2: The semiconductor device according to claim 1 ,wherein the diamond layer has a shape that widens upward.3: The semiconductor device according to claim 1 , further comprising:a gate electrode disposed on a second main surface that is opposite to the first main surface of the crystalline nitride layer,wherein at least a part of the gate electrode is positioned below the structure.4: The semiconductor device according to claim 1 ,wherein a plurality of the structures are disposed on the first main surface of the crystalline nitride layer, andthe diamond layer is disposed to be adjoined to adjacent structures among the plurality of the structures.5: The semiconductor device according to claim 4 ,wherein at least one of a plurality of die diamond layers is out of contact with the first main surface of the crystalline nitride layer.6: The semiconductor device according to claim 4 ,wherein adjacent lateral surfaces of the adjacent structures are unparallel to each other.7: A method of ...

Diamond Semiconductor System and Method

Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The system may include a diamond material having n-type donor atoms and a diamond lattice, wherein 0.16% of the donor atoms contribute conduction electrons with mobility greater than 770 cm2/Vs to the diamond lattice at 100 kPa and 300K. The method of fabricating diamond semiconductors may include the steps of selecting a diamond material having a diamond lattice; introducing a minimal amount of acceptor dopant atoms to the diamond lattice to create ion tracks; introducing substitutional dopant atoms to the diamond lattice through the ion tracks; and annealing the diamond lattice. 1. (canceled)2. (canceled)3. (canceled)4. (canceled)5. A method of fabricating diamond semiconductors , the method including the steps of:selecting a diamond material having a diamond lattice, forming a diamond layer on a silicon dioxide layer;introducing acceptor dopant atoms to the diamond lattice to create a plurality of temporary dopant pathways;introducing substitutional dopant atoms to the diamond lattice through at least a portion of the temporary dopant pathways; andannealing the diamond lattice to remove at least some of the temporary dopant pathways;{'sup': 22', '3, 'wherein the introduction of the acceptor dopant atoms does not create more than 10/cmof vacancies in the diamond layer.'}6. The method of claim 5 , wherein the diamond material is intrinsic diamond.7. The method of claim 5 , wherein the acceptor dopant atoms are introduced at 293 to 298 degrees Kelvin.8. The method of claim 5 , wherein the acceptor dopant atoms are boron.9. The method of claim 5 , wherein the amount of acceptor dopant atoms is between 5×10/cmand 5×10/cm.10. The method of claim 5 , wherein the substitutional dopant atoms are introduced at or below 78 degrees Kelvin.11. The method of claim 5 , wherein the substitutional dopant atoms are introduced at less than 500 keV.12. The method of claim 5 , wherein the ...

POWER SEMICONDUCTOR DEVICE

A power semiconductor device is provided with a semiconductor-element substrate in which a front-surface electrode pattern is formed on a surface of an insulating substrate; semiconductor elements for electric power which are affixed to the surface of the front-surface electrode pattern; a partition wall which is provided on the front-surface electrode pattern so as to enclose the semiconductor elements for electric power; a first sealing resin member which is filled inside the partition wall; a second sealing resin member which covers the first sealing resin member and a part of the semiconductor-element substrate which is exposed from the partition wall, wherein an electrode for a relay terminal is provided on a surface of the partition wall, and a wiring from inside of the partition wall to outside of the partition wall is led out via the electrode for a relay terminal. 1. A power semiconductor device comprising:a semiconductor-element substrate in which a front-surface electrode pattern is formed on a surface of an insulating substrate and a back-surface electrode pattern is formed on another surface of the insulating substrate;a semiconductor element for electric power which is affixed, using a bonding material, to the surface of the front-surface electrode pattern opposite the insulating substrate;a partition wall which is provided on the front-surface electrode pattern by bonding so as to enclose the semiconductor element for electric power;a first sealing resin member which is filled inside the partition wall so as to cover the semiconductor element for electric power and the front-surface electrode pattern in the partition wall; anda second sealing resin member which covers the first sealing resin member and a part of the semiconductor-element substrate which is exposed from the partition wall,wherein a modulus of elasticity of the second sealing resin member is set to be smaller than a modulus of elasticity of the first sealing resin member, an electrode ...

SEMICONDUCTOR DEVICE

A base plate, and a plurality of unit structures formed on the base plate are provided. Each of the unit structures including an insulating substrate fixed on the base plate, a metal pattern formed on the insulating substrate, a semiconductor element electrically connected to the metal pattern, and a main electrode having an upper end portion exposed to the outside and a lower end portion connected to a peripheral portion of the metal pattern closest to an outer edge of the base plate. 1. A semiconductor device comprising:a base plate formed into a rectangular shape as viewed in plan; anda plurality of unit structures formed nearer to a first side of the base plate and a plurality of unit structures formed nearer to a second side of the base plate opposite from the first side, each of the unit structures including:an insulating substrate fixed on the base plate;a metal pattern formed on the insulating substrate;a semiconductor element electrically connected to the metal pattern; anda main electrode having an upper end portion exposed to the outside and a lower end portion connected to a peripheral portion of the metal pattern closest to an outer edge of the base plate.2. A semiconductor device comprising:a base plate formed into a rectangular shape as viewed in plan; anda plurality of unit structures formed on the base plate, each of the unit structures including:an insulating substrate fixed on the base plate;a metal pattern formed on the insulating substrate;a semiconductor element electrically connected to the metal pattern; anda main electrode having an upper end portion exposed to the outside and a lower end portion connected to a peripheral portion of the metal pattern closest to an outer edge of the base plate, whereinthe plurality of unit structures include a first unit structure formed on a first side of the base plate, and a second unit structure formed on a second side of the base plate opposite from the first side, andthe main electrode includes a first ...

Semiconductor Device Comprising Diamond and Method For Its Manufacturing

Hot metal dissolution of carbon atoms is used to structure a diamond substrate. A layer of catalytic material is deposited on at least a portion of a surface of the diamond substrate. The layer of catalytic material may be structured using photolithography to define a gap exposing the surface of the diamond substrate, where the gap has a (110) orientation relative to the crystal structure of the diamond substrate. The exposed surface of the diamond substrate is etched to form at least one recess having at least one (111) oriented diamond surface (facet). The catalytic material is removed by a suitable cleaning process. The (111) oriented surface is then overgrown with diamond comprising a dopant resulting in a conductivity of the overgrown diamond that is different from the conductivity of the doped substrate. The doping concentration of the overgrown diamond is greater than 10cm. 1. A semiconductor device , comprisinga substrate comprising at least diamond and at least a first dopant resulting in a first conductivity and having a first surface having a [100] orientation and;at least one recess arranged on said first surface, said recess having at least one diamond facet having an [111] orientation;a homoepitaxially grown diamond material comprising a second dopant resulting in a second conductivity and being arranged at least partially on said at least one diamond facet.2. A device according to claim 1 , comprising a Schottky contact being arranged on said homoepitaxially grown diamond material.3. A device according to claim 1 , comprising an Ohmic contact being arranged on a second surface of said substrate claim 1 , said second surface being located opposite said first surface.4. A device according to claim 1 , wherein said substrate is composed of at least two layers of diamond material being arranged one above the other claim 1 , both layers having the first conductivity and different concentrations of dopants.5. A method for structuring a diamond surface claim ...

Substrates for semiconductor devices

A method of manufacturing a composite substrate for a semiconductor device, the method comprising: depositing silicon on a surface of a synthetic diamond wafer; and treating the synthetic diamond wafer to transform the deposited silicon into silicon carbide thus forming a layer of silicon carbide on the surface of the synthetic diamond wafer, wherein the synthetic diamond wafer is selected from one of: a single crystal diamond wafer; and a polycrystalline CVD diamond wafer having a nucleation face and a growth face wherein the nucleation face comprises smaller diamond grains than the growth face, and wherein if the synthetic diamond wafer is a polycrystalline CVD diamond wafer then the silicon carbide layer is formed on the growth face of the polycrystalline CVD diamond wafer.

DOPED ENCAPSULATION MATERIAL FOR DIAMOND SEMICONDUCTORS

According to some embodiments, a method for stabilizing electrical properties of a diamond semiconductor comprises terminating a surface of a diamond with hydrogen (H) or deuterium (D) atoms and over-coating the surface of the diamond with an encapsulating material comprising metal oxide salt doped with one or more elements capable of generating negative charge in the metal oxide salt. 1. A method for stabilizing electrical properties of a diamond semiconductor , the method comprising:terminating a surface of a diamond with hydrogen (H) or deuterium (D) atoms; andover-coating the surface of the diamond with an encapsulating material comprising metal oxide salt doped with one or more elements capable of generating negative charge in the metal oxide salt.2. The method of wherein the metal oxide salt comprises aluminum oxide (AlO) and the one or more elements capable of generating negative charge comprise at least one of silicon dioxide (SiO) and/or zirconium oxide (ZrO).3. The method of wherein the metal oxide salt comprises aluminum phosphate (AlPO) and the one or more elements capable of generating negative charge comprise at least one of silicon dioxide (SiO) and/or zirconium oxide (ZrO).4. The method of wherein the metal oxide salt comprises boron oxide (BO) and the one or more elements capable of generating negative charge comprise at least one of silicon dioxide (SiO) and/or zirconium oxide (ZrO).5. The method of wherein the encapsulating material comprises at least one of aluminum (Al) or boron (B) claim 1 , wherein claim 1 , in the encapsulating material claim 1 , the concentration of Al or B is less than that of the or more elements capable of generating negative charge.6. The method of wherein over-coating the surface of the diamond with the encapsulating material comprises using an evaporation process.7. The method of wherein the encapsulating material has a thickness of less than 2 nm.8. The method of wherein the evaporation process comprises:mounting the ...

Novel Series of Carbon Allotropes: Novamene

The present invention provides a series of new and useful synthetic carbon allotropes. The carbon allotropes contain at least two inner hexagonal rings of 6 carbon atoms, which are characterized by hybridized spbonds, as commonly found in graphene structure. The inner hexagonal rings are located in a central position within the carbon allotropes and bonded to each other in various configurations. Surrounding the hexagonal rings are additional carbon atoms, characterized by sphybridized bonding, found in diamond, and more specifically in hexagonal diamond, also known as Lonsdaleite. These surrounding Lonsdaleite structures are bonded to and surround the inner hexagonal rings and support them in a central position within the carbon allotropes. 1. A composition of matter comprising a carbon allotrope , said carbon allotrope having at least two inner hexagonal rings located within a single plane , having six carbon atoms bonded together by sp2 hybridized bonds , wherein said at least two inner hexagonal rings are centrally located within the carbon allotrope , and wherein said at least two inner hexagonal rings are bonded to and supported in said central location through bonding with additional carbon atoms by sp3 hybridized bonds.2. A composition of matter as in claim 1 , wherein said at least two inner hexagonal rings of the carbon allotrope are graphene crystals.3. A composition of matter as in claim 1 , wherein said additional carbon atoms bonded by sp3 hybridized bonds form Lonsdaleite structures supporting said at least two inner hexagonal rings.4. A composition of matter as in claim 1 , wherein said carbon allotrope comprises at least three inner hexagonal rings claim 1 , centrally located within said carbon allotrope.5. A composition of matter as in claim 1 , wherein said carbon allotrope comprises at least four inner hexagonal rings claim 1 , centrally located within said carbon allotrope.6. A composition of matter as in claim 1 , wherein said carbon allotrope ...

TEMPERATURE SENSOR

Temperature sensor devices and corresponding methods are provided. A temperature sensor may include a first layer being essentially non-conductive in a temperature range and a second layer having a varying resistance in the temperature range. 125-. (canceled)26. A temperature sensor device , comprising:a first electrode,a first layer portion in electrical contact with the first electrode, the first layer portion being essentially electrically non-conductive in a temperature range,a second layer portion in contact with a second electrode, the second layer portion having a temperature-dependent electrical resistance in the temperature range, where the second layer portion exhibits a temperature-dependent resistance and a capacitance, where the first layer portion is above the second layer portion, andthe second electrode in electrical contact with the second layer portion.27. The device of claim 26 , wherein the capacitance of the second layer is temperature-dependent.28. The device of claim 26 , wherein the first layer portion comprises a first semiconductor material having a dopant concentration below 1×10cm.29. The device of claim 27 , wherein the first semiconductor material has a band gap of at least 1.5 eV.30. The device of claim 26 , wherein the second layer portion comprises a second semiconductor material doped with at least one dopant claim 26 , a peak dopant concentration being at least 5×10cm.31. The device of claim 30 , wherein the dopant concentration in the second semiconductor material increases from a part of the second layer portion adjacent to the first layer portion towards the second electrode.32. The device of claim 30 , wherein the dopant generates at least one of a donor level having a distance of at least 0.2 eV from a conduction band or an acceptor level having a distance of at least 0.2 eV from a valence band.33. The device of claim 29 , wherein the first layer portion comprises a first semiconductor material claim 29 , wherein the first ...

WAFER LEVEL INTEGRATION INCLUDING DESIGN/CO-DESIGN, STRUCTURE PROCESS, EQUIPMENT STRESS MANAGEMENT, AND THERMAL MANAGEMENT

A multi-layer wafer and method of manufacturing such wafer are provided. The method comprises applying a stress compensating oxide layer to each of two heterogeneous wafers, applying at least one bonding oxide layer to at least one of the two heterogeneous wafers, chemical-mechanical polishing the at least one bonding oxide layer, and low temperature bonding the two heterogeneous wafers to form a multi-layer wafer pair. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafers having a stress compensating oxide layer and at least one bonding oxide layer applied to at least one of the two heterogeneous wafers. The two heterogeneous wafers are low temperature bonded together to form the multi-layer wafer. 114-. (canceled)15. A multi-layer wafer comprising:two heterogeneous wafers, each of the heterogeneous wafers having a stress compensating oxide layer;at least one bonding oxide layer applied to at least one of the two heterogeneous wafers;the two heterogeneous wafers low temperature bonded together to form the multi-layer wafer.16. The multi-layer wafer of claim 15 , wherein each of the two heterogeneous wafers are formed from at least one of: complementary metal-oxide semiconductor (CMOS) and GaN on Si claim 15 , CMOS and glass claim 15 , CMOS and sapphire claim 15 , CMOS and SiC on Si claim 15 , CMOS and diamond on Si claim 15 , or CMOS and sapphire on Si.17. The multi-layer wafer of claim 15 , wherein the stress compensating oxide layer is comprised of tetraethyl orthosilicate (TEOS).18. The multi-layer wafer of claim 15 , wherein each stress compensating oxide layer comprises a different stoichiometric SiOx deposition.19. The multi-layer wafer of claim 15 , further comprising islands of heterogeneous material in at least one heterogeneous wafer formed by at least one of depositing or growing the heterogeneous material.20. The multi-layer wafer of claim 19 , further comprising:channels between the islands of heterogeneous material ...

SEMICONDUCTOR DEVICE

The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage Vof 0.3 V to 0.7 V and a leakage current Jof 1×10A/cmto 1×10A/cmin a rated voltage V. 1. A semiconductor device comprising:a first conductivity type semiconductor layer made of a wide bandgap semiconductor, the first conductivity type semiconductor layer having an active region and a field region surrounding the active region;a Schottky electrode formed to come into contact with at least a portion of a surface of the first conductivity type semiconductor layer in the active region;a plurality of annular guard rings of a second conductivity type formed in the field region, wherein:the plurality of annular guard rings includes a first guard ring, a second guard ring and a third guard ring, anda first distance between the first guard ring and the second guard ring is different from a second distance between the second guard ring and the third guard ring.2. The semiconductor device according to claim 1 , further comprising:{'sub': '1', 'a taper trench formed in the active region, the taper trench having a bottom surface and a side surface inclined at an angle (θ) exceeding 90° with respect to the bottom surface; and'}an impurity region of the second conductivity type formed in the bottom surface and the side surface of the taper trench.3. The semiconductor device according to claim 2 , wherein{'sub': 5', '6, 'the impurity region has a first thickness (t) from the bottom surface of the taper trench measured in a depth direction of the taper trench and a second thickness (t) from the side surface of the taper trench measured in a direction perpendicular to the side surface, and the first thickness is greater than the second thickness.'}4. The semiconductor device according to claim 3 , wherein the second ...

SEMICONDUCTOR DEVICE WITH VOLTAGE RESISTANT STRUCTURE

A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.

SEMICONDUCTOR DEVICE AND METHOD FOR MANURACTURING THE SAME

A semiconductor device of the present invention includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first conductivity-type source region, a second conductivity-type channel region, and a first conductivity-type drain region formed in the semiconductor layer, a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer, a trench buried portion buried in the second trench, a second conductivity-type channel contact region selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, and electrically connected with the channel region, and a surface metal layer disposed on the source portion, and electrically connected to the source region and the channel contact region.

THERMAL DIFFUSION DOPING OF DIAMOND

Boron-doped diamond and methods for making it are provided. The doped diamond is made using an ultra-thin film of heavily boron-doped silicon as a dopant carrying material in a low temperature thermal diffusion doping process. 1. Boron-doped diamond comprising: a layer of diamond comprising a doped region extending into the layer from a surface , the doped region comprising substitutional boron dopant atoms , wherein the concentration of substitutional boron dopant atoms at the surface is at least 1×10cmand the depth profile of the substitutional boron dopant atoms corresponds to a complimentary-error-function.2. The diamond of claim 1 , wherein the concentration of substitutional boron dopant atoms at the surface is at least 2×10cm.3. The diamond of claim 1 , wherein the concentration of substitutional boron dopant atoms at the surface is at least 2.2×10cm.4. The diamond of claim 1 , wherein the concentration of substitutional boron dopant atoms at a depth of 100 nm from the surface is no greater than 1×10cm.5. The diamond of claim 1 , wherein the concentration of substitutional boron dopant atoms at a depth of 100 nm from the surface is no greater than 1×10cm.6. The diamond of claim 1 , wherein the diamond is free of Si atoms at a depth of 5 nm or greater from the surface.7. The diamond of claim 1 , wherein the surface is free of graphitized diamond.8. The diamond of claim 1 , wherein the diamond is natural diamond.9. The diamond of claim 1 , wherein the diamond comprises type IIa diamond.10. The diamond of claim 1 , wherein the diamond is single-crystalline diamond.11. The diamond of claim 1 , wherein the diamond is single-crystalline diamond claim 1 , the concentration of substitutional boron dopant atoms at the surface is at least 2×10cm claim 1 , and the concentration of substitutional boron dopant atoms at a depth of 100 nm from the surface is no greater than 1×10cm.12. A method of making substitutionally boron-doped diamond claim 1 , the method comprising: ...

SEMICONDUCTOR DEVICES WITH MINIMIZED CURRENT FLOW DIFFERENCES AND METHODS OF SAME

A semiconductor device with minimized current flow differences and method of fabricating same are disclosed. The method includes forming a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, in which the second layer is on top of the first layer, forming a plurality of mesas in the semiconductor layer stack, and forming a plurality of gates in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, in which the plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device. 1. A semiconductor device with minimized current flow differences comprising:a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, wherein the second layer is on top of the first layer;a plurality of mesas formed in the semiconductor layer stack; anda plurality of gates formed in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, wherein the plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device;wherein the plurality of gates are formed via dopant implantation of the semiconductor layer stack, the dopant implantation of the semiconductor layer stack occurs while the plurality of mesas have a plurality of masks thereon that are each wider ...

Diamond substrate and freestanding diamond substrate

A method for manufacturing a diamond substrate, including: a first step of preparing patterned diamond on a foundation surface, a second step of growing diamond from the patterned diamond prepared in the first step to form the diamond in a pattern gap of the patterned diamond prepared in the first step, a third step of removing the patterned diamond prepared in the first step to form a patterned diamond composed of the diamond formed in the second step, and a fourth step of growing diamond from the patterned diamond formed in the third step to form the diamond in a pattern gap of the patterned diamond formed in the third step. There can be provided a method for manufacturing a diamond substrate which can sufficiently suppress dislocation defects, a high-quality diamond substrate, and a freestanding diamond substrate.

SINGLE CRYSTAL DIAMOND AND SEMICONDUCTOR ELEMENT USING SAME

Provided is a single crystal diamond having a lowered dislocation density. The single crystal diamond () is provided with single crystal diamond layers (). One single crystal diamond layer () is formed on a diamond substrate () and contains point defects. The other single crystal diamond layer () is grown on the single crystal diamond layer (). The single crystal diamond layers () have a lower dislocation density than the diamond substrate. 1. A single crystal diamond comprising a first single crystal diamond layer formed on a substrate and containing a point defect , wherein the first single crystal diamond layer has a lower dislocation density than the substrate.2. The single crystal diamond according to claim 1 , further comprising a second single crystal diamond layer grown on the first single crystal diamond layer and having a lower dislocation density than the substrate.3. The single crystal diamond according to claim 1 , wherein the first single crystal diamond layer contains: any one of tungsten claim 1 , tantalum claim 1 , rhenium claim 1 , iron claim 1 , nickel claim 1 , cobalt claim 1 , aluminum claim 1 , gallium claim 1 , germanium claim 1 , iridium claim 1 , and phosphorus; silicon; and molybdenum.4. The single crystal diamond according to claim 2 , wherein the second single crystal diamond layer has a lower dislocation density than the substrate by two orders of magnitude or more.5. The single crystal diamond according to claim 1 , wherein the first single crystal diamond layer has a film thickness of 1 μm or more.6. The single crystal diamond according to claim 2 , wherein the second single crystal diamond layer has a film thickness of 200 μm or more.7. The single crystal diamond according to claim 2 , wherein the first single crystal diamond layer further contains a p-type dopant.8. A semiconductor element comprising:{'claim-ref': {'@idref': 'CLM-00007', 'claim 7'}, 'the single crystal diamond according to ;'}a first metal that forms a Schottky ...

HEAT DISSIPATION SUBSTRATE AND METHOD FOR PRODUCING SAME

The present invention relates to a heat dissipation substrate, which is a composite substrate composed of two layers, and which is characterized in that a surface layer (first layer) () is configured of single crystal silicon and a handle substrate (second layer) () is configured of a material that has a higher thermal conductivity than the first layer. A heat dissipation substrate of the present invention has high heat dissipation properties. 1. A heat dissipating substrate which is a composite substrate consisting of two layers , wherein a surface layer (first layer) is composed of single crystal silicon and a handle substrate (second layer) is composed of a material having a higher thermal conductivity than the first layer.2. The heat dissipating substrate of wherein the material of the second layer is composed of aluminum nitride claim 1 , silicon carbide or diamond.3. A heat dissipating substrate which is a composite substrate consisting of three layers claim 1 , wherein a surface layer (first layer) is composed of single crystal silicon claim 1 , a handle substrate (second layer) is composed of a material having a higher thermal conductivity than the first layer claim 1 , and an intermediate layer (third layer) is composed of a material having a thermal conductivity which is equal to or higher than the thermal conductivity of the second layer.4. The heat dissipating substrate of wherein the materials of the second and third layers are selected from aluminum nitride claim 3 , silicon carbide claim 3 , and diamond.5. The heat dissipating substrate of which is prepared by bonding the first layer (silicon layer) to the second layer claim 1 , and thinning the first layer (silicon layer).6. The heat dissipating substrate of which is prepared by bonding the first layer (silicon layer) claim 3 , the intermediate layer (third layer) claim 3 , and the second layer claim 3 , and thinning the first layer (silicon layer).7. A method for preparing a heat dissipating ...

Diamond Semiconductor System and Method

Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The system may include a diamond material having n-type donor atoms and a diamond lattice, wherein 0.16% of the donor atoms contribute conduction electrons with mobility greater than 770 cm2/Vs to the diamond lattice at 100 kPa and 300K. The method of fabricating diamond semiconductors may include the steps of selecting a diamond material having a diamond lattice; introducing a minimal amount of acceptor dopant atoms to the diamond lattice to create ion tracks; introducing substitutional dopant atoms to the diamond lattice through the ion tracks; and annealing the diamond lattice. 1. (canceled)2. (canceled)3. (canceled)4. (canceled)5. A method of fabricating diamond semiconductors , the method including the steps of:selecting a diamond material having a diamond lattice;introducing a minimal amount of acceptor dopant atoms to the diamond lattice to create ion tracks;introducing substitutional dopant atoms to the diamond lattice through the ion tracks; andannealing the diamond lattice;wherein the introduction of the minimal amount of acceptor dopant atoms does not create a critical density of vacancies, and the introduction of the minimal amount of acceptor dopant atoms diminishes the resistive pressure capability of the diamond lattice.6. The method of claim 5 , wherein the diamond material is intrinsic diamond.7. The method of claim 5 , wherein the acceptor dopant atoms are introduced at 293 to 298 degrees Kelvin.8. The method of claim 5 , wherein the acceptor dopant atoms are boron.9. The method of claim 5 , wherein the minimal amount of acceptor dopant atoms is between 5×108/cm2 and 5×1010/cm2.10. The method of claim 5 , wherein the substitutional dopant atoms are introduced at or below 78 degrees Kelvin.11. The method of claim 5 , wherein the substitutional dopant atoms are introduced at less than 500 keV.12. The method of claim 5 , wherein the substitutional dopant ...

HYBRID POWER DEVICES AND SWITCHING CIRCUITS FOR HIGH POWER LOAD SOURCING APPLICATIONS

A hybrid switching circuit includes first and second switching devices containing first and second unequal bandgap semiconductor materials. These switching devices, which support parallel conduction in response to first and second control signals, are three or more terminal switching devices of different type. For example, the first switching device may be a three or more terminal wide bandgap switching device selected from a group consisting of JFETs, IGFETs and high electron mobility transistors HEMTs, and the second switching device may be a Si-IGBT. A control circuit is also provided, which is configured to drive the first and second switching devices with first and second periodic control signals having first and second unequal duty cycles. The first duty cycle may be greater than the second duty cycle and the active phases of the second periodic control signal may occur exclusively within the active phases of the first periodic control signal. 1. A hybrid switching circuit , comprising:first and second switching devices containing first and second unequal bandgap semiconductor materials, respectively, said first and second switching devices electrically coupled as a hybrid switch that supports parallel conduction in response to first and second control signals received at first and second control terminals of said first and second switching devices, respectively.2. The hybrid switching circuit of claim 1 , wherein the first and second switching devices are three or more terminal switching devices of different type.3. The hybrid switching circuit of claim 2 , wherein the second switching device is an insulated-gate bipolar transistor (IGBT).4. The hybrid switching circuit of claim 3 , wherein the first switching device is a three or more terminal switching device selected from a group consisting of junction field effect transistors (JFETs) claim 3 , insulated-gate field effect transistors (IGFETs) and high electron mobility transistors (HEMTs).5. The hybrid ...

IMPLANTED ISOLATION FOR DEVICE INTEGRATION ON A COMMON SUBSTRATE

Structures including devices, such as transistors, integrated on a semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a semiconductor substrate. A first transistor is formed in a first device region of a semiconductor substrate, and a second transistor is formed in a second device region of the semiconductor substrate. The second transistor includes a layer stack on the semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material. A polycrystalline layer includes a section that is positioned in the semiconductor substrate beneath the first device region. 1. A structure comprising:a semiconductor substrate has a first device region and a second device region;a first transistor in the first device region of the semiconductor substrate;a second transistor in the second device region of the semiconductor substrate, the second transistor including a layer stack on the semiconductor substrate, and the layer stack including a layer comprised of a III-V compound semiconductor material; anda polycrystalline layer in the semiconductor substrate, the polycrystalline layer including a first section positioned in the semiconductor substrate beneath the first device region.2. The structure of wherein the semiconductor substrate has a first surface and a trench extending from the first surface into the semiconductor substrate claim 1 , the layer stack is positioned on the semiconductor substrate inside the trench claim 1 , and further comprising:a polycrystalline region in the semiconductor substrate adjacent to the trench.3. The structure of wherein the polycrystalline region extends from the first surface to the first section of the polycrystalline layer.4. The structure of further comprising:a shallow trench isolation region in the semiconductor substrate, the shallow trench isolation region laterally positioned between the first device region and the second ...

SEMICONDUCTOR DEVICE

A semiconductor device includes an insulating substrate, a semiconductor element secured to a top surface of the insulating substrate, a case formed of a resin and having a frame portion surrounding the semiconductor element, a metal support located above the insulating substrate and having an end secured to the frame portion, a holding-down portion extending downward from the metal support so as to prevent upwardly convex bending of the insulating substrate, and an adhesive bonding the insulating substrate and the case together. 1. A semiconductor device comprising:an insulating substrate;a semiconductor element secured to a top surface of said insulating substrate;a case formed of a resin and having a frame portion surrounding said semiconductor element;a metal support located above said insulating substrate and having an end secured to said frame portion;a holding-down portion extending downward from said metal support so as to prevent upwardly convex bending of said insulating substrate; andan adhesive bonding said insulating substrate and said case together.2. The semiconductor device according to claim 1 , further comprising a plurality of said holding-down portions.3. The semiconductor device according to claim 1 , wherein said holding-down portion is formed of an elastic material.4. The semiconductor device according to claim 1 , wherein said insulating substrate is pressed downward and thereby bent into a downwardly convex shape by said holding-down portion claim 1 , and a bottom surface of said insulating substrate is located at a lower level than a bottom surface of said case.5. The semiconductor device according to claim 1 , wherein said metal support has a recess filled with resin material of said case.6. The semiconductor device according to claim 1 , wherein said metal support is formed of copper claim 1 , and said resin is a PPS resin.7. The semiconductor device according to claim 1 , wherein said insulating substrate is not in direct contact with ...

Method of evaluating semiconductor device and apparatus for evaluating semiconductor device

A method of evaluating a semiconductor device having an insulated gate formed of a metal-oxide film semiconductor. The semiconductor device has a high potential side and a low potential side, and a threshold voltage that is a minimum voltage for forming a conducting path between the high and low potential sides. The method includes determining a variation of the threshold voltage at turn-on of the semiconductor device by continuously applying an alternating current (AC) voltage to the gate of the semiconductor device, a maximum voltage of the AC voltage being equal to or higher than the threshold voltage of the semiconductor device.

HANDLE FOR SEMICONDUCTOR-ON-DIAMOND WAFERS AND METHOD OF MANUFACTURE

Methods for mounting and dismounting thin and/or bowed semiconductor-on-diamond wafers to a carrier are disclosed that flatten said wafers and provide mechanical support to enable efficient semiconductor device processing on said semiconductor-on-diamond wafers. 1. A method of forming a composite wafer , comprising:(a) preparing a stack of layers including a carrier plate, an adhesive layer disposed directly on the carrier plate, and a semiconductor-on-diamond wafer disposed directly on the adhesive layer, the carrier plate including a diamond material, the semiconductor-on-diamond wafer including a layer of single-crystal semiconductor and a layer of diamond that is in direct contact with the adhesive layer;(b) exerting axial pressure to the stack of layers to join the semiconductor-on-diamond wafer with the carrier plate; and [ separating the carrier plate from the semiconductor-on-diamond wafer; and', 'repeating the steps (a)-(c); and, '(i) if the determination in step (c) is negative;'}, '(d) curing the adhesive layer to secure the semiconductor-on-diamond wafer to the carrier plate.', '(ii) if the determination in step (c) is positive,'}], '(c) determining whether the composite wafer has a thickness variation of no more than a first value over a total area of the composite wafer;'}2. The method of claim 1 , wherein the first value is 30 μm.3. The method of claim 1 , further comprising claim 1 , after the step (d):(e) determining whether the composite wafer has a thickness variation of no more than a second value over a total area of the composite wafer; and separating the carrier plate from the semiconductor-on-diamond wafer; and', 'repeating the steps (a)-(e)., 'if the determination in step (e) is negative;'} 'further processing the composite wafer.', 'if the determination in step (e) is positive;'}4. The method of claim 1 , further comprising claim 1 , after the step (b):(e) determining whether the composite wafer has a bow of no more than a third value over ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE

A method for manufacturing a semiconductor device is carried out by readying each of a semiconductor element, a substrate having Cu as a principal element at least on a surface, and a ZnAl solder chip having a smaller shape than that of the semiconductor element; disposing the semiconductor element and the substrate so that respective bonding surfaces face each other, and sandwiching the ZnAl eutectic solder chip between the substrate and the semiconductor element; increasing the temperature of the ZnAl solder chip sandwiched between the substrate and the semiconductor element while applying a load to the ZnAl solder chip such that the ZnAl solder chip melts to form a ZnAl solder layer; and reducing the temperature of the ZnAl solder layer while applying a load to the ZnAl solder layer. 1. A method for manufacturing a semiconductor device , comprising:readying each of a semiconductor element, a substrate having Cu as a principal element at least on a surface, and a ZnAl eutectic solder chip having a smaller shape than that of the semiconductor element;disposing the semiconductor element and the substrate so that respective bonding surfaces face each other, and sandwiching the ZnAl eutectic solder chip between the substrate and the semiconductor element;increasing the temperature of the ZnAl eutectic solder chip sandwiched between the substrate and the semiconductor element while applying a load to the ZnAl eutectic solder chip such that the ZnAl eutectic solder chip melts to form a ZnAl solder layer; andreducing the temperature of the ZnAl solder layer while applying a load to the ZnAl solder layer such that an eutectic phase structure content of the ZnAl solder layer is entirely decreased in comparison to an eutectic phase structure content of the ZnAl eutectic solder chip.2. The method for manufacturing a semiconductor device according to claim 1 , whereinreducing of the temperature includes maintaining the temperature, or reducing the temperature at a gradual ...

Schottky Diode and Method for Its Manufacturing

The invention disclosure describes a manufacturing method for realizing so-called JBS areas for a unipolar power diode on the basis of diamond. In this special method, an n-doped layer is applied to the typically p-doped drift region, e.g. by means of epitaxial layer growth. The applied n-doped layer is then removed again in defined areas. A photolithographic mask may be applied and the n-doped layer is removed by dry or wet chemical etching. Having structured the JBS areas, the Schottky metal is applied to the entire surface. The resulting JBS structure shields an electric field generated by an applied reverse voltage from the Schottky transition. The reverse voltage from which the Schottky transition is fully shielded can be adjusted by altering the distance between the JBS areas. 1. A Schottky diode comprising:a drift region comprising diamond having a first conductivity type;a plurality of junction barrier Schottky regions comprising diamond having a second conductivity type opposite the first conductivity type and being arranged on a top of the drift region and separated by spaces;at least one Schottky contact being applied to the top of the drift region, thereby covering the junction barrier Schottky regions and filling the spaces between the junction barrier Schottky regions; andat least one Ohmic contact on the drift region.2. The Schottky diode according to claim 1 , wherein the Ohmic contact and the Schottky contact are located on opposite sides of the drift region.3. The Schottky diode according to claim 1 , wherein the drift region has a thickness of about 5 μm to about 20 μm or a thickness of about 8 μm to about 15 μm.4. The Schottky diode according to claim 1 , wherein the junction barrier Schottky regions are separated by a spacing of about 0.5 μm to about 4 μm.5. The Schottky diode according to claim 1 , wherein the the junction barrier Schottky regions have a thickness of about 0.2 μm to about 1.5 μm.6. The Schottky diode according to claim 1 , ...

Doped Diamond SemiConductor and Method of Manufacture

A doped diamond semiconductor and method of production using a laser is disclosed herein. As disclosed, a dopant and/or a diamond or sapphire seed material may be added to a graphite based ablative layer positioned below a confinement layer, the ablative layer also being graphite based and positioned above a backing layer, to promote formation of diamond particles having desirable semiconductor properties via the action of a laser beam upon the ablative layer. Dopants may be incorporated into the process to activate the reaction sought to produce a material useful in production of a doped semiconductor or a doped conductor suitable for the purpose of modulating the electrical, thermal or quantum properties of the material produced. As disclosed, the diamond particles formed by either the machine or method of confined pulsed laser deposition disclosed may be arranged as semiconductors, electrical components, thermal components, quantum components and/or integrated circuits. 1. An electrical component comprising:a) at least a first portion formed from and composed of diamond, the first portion primarily defined as an insulator;b) at least a second portion formed from and composed of graphite, the second portion primarily defined as a conductor;c) at least a third portion formed from and composed of a doped diamond, the third portion primarily defined as a semiconductor;d) wherein the first portion, the second portion and the third portion are integrally formed and work together for transmission of an electrical signal across the electrical component.2. The electrical component according to wherein a metallic compound is present in the second portion.3. The electrical component according to formed as a resistor claim 1 , a transistor claim 1 , capacitor claim 1 , inverter claim 1 , an inductor or a diode or combination therein.4. The electrical component according to formed as a resistor claim 2 , a transistor claim 2 , capacitor claim 2 , inverter claim 2 , an ...

DEVICE FOR FORMING DIAMOND FILM ETC. AND METHOD THEREFOR

According to an embodiment of the present invention, there is provided a device for forming at least a diamond film on a surface of a substrate, the device comprising: a container configured to hold a raw material liquid and to place the substrate in the raw material liquid; an electrode part comprising a positive electrode and a negative electrode and configured to generate a plasma in the raw material liquid; a raw material gas supply part and a carrier gas supply part, each of the raw material gas supply part and the carrier gas supply part being connected to the electrode part; and a power source configured to apply a voltage to the electrode part, wherein the power source is a direct current power source, and the electrode part further comprises an adjunctive member, and the adjunctive member is attached to an electrode at a plasma generation region of the electrode part. 1. A device for forming at least a diamond film on a surface of a substrate , the device comprising:a container configured to hold a raw material liquid and to place the substrate in the raw material liquid;an electrode part comprising a positive electrode and a negative electrode and configured to generate a plasma in the raw material liquid;a raw material gas supply part and a carrier gas supply part, each of the raw material gas supply part and the carrier gas supply part being connected to the electrode part; anda power source configured to apply a voltage to the electrode part,wherein the power source is a direct current power source, and the electrode part further comprises an adjunctive member, and the adjunctive member is attached to an electrode at a plasma generation region of the electrode part.2. The device according to claim 1 , wherein the adjunctive member is a melting prevention member for the electrode at the plasma generation region.3. The device according to claim 1 , wherein the adjunctive member is an impurity supply source member at the plasma generation region.4. The ...

GaN/DIAMOND WAFERS

Wafers including a diamond layer and a semiconductor layer having III-Nitride compounds and methods for fabricating the wafers are provided. A nucleation layer, at least one semiconductor layer having III-Nitride compound and a protection layer are formed on a silicon substrate. Then, a silicon carrier wafer is glass bonded to the protection layer. Subsequently the silicon substrate, nucleation layer and a portion of the semiconductor layer are removed. Then, an intermediate layer, a seed layer and a diamond layer are sequentially deposited on the III-Nitride layer. Next, a support wafer that includes a GaN layer (or a silicon layer covered by a protection layer) is deposited on the diamond layer. Then, the silicon carrier wafer and the protection layer are removed. 1. A method for processing a semiconductor wafer , comprising:disposing and patterning a first metal layer on a semiconductor layer of a semiconductor wafer, wherein the semiconductor wafer includes a support wafer, a diamond layer, an intermediate layer and the semiconductor layer;drilling one or more holes from the first metal layer toward the support wafer to thereby form one or more vias that extend from the first metal layer into the support wafer;disposing a second metal layer on the first metal layer and in a portion of the one or more vias; andremoving the support wafer to expose a surface of the diamond layer.2. The method of claim 1 , wherein the support wafer and the bonding layer are removed by carrying out a lapping process.3. The method of claim 1 , further comprising:cleaning the exposed surface of the diamond layer.4. The method of claim 3 , wherein the exposed surface of the diamond layer is cleaned by dry etching.5. The method of claim 1 , further comprising:disposing a third metal layer on the exposed surface of the diamond layer and a side surface of the one or more vias, wherein the third metal layer electrically contacts the second metal layer.6. The method of claim 5 , wherein the ...

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING P-TYPE CONDUCTIVE CHANNEL IN DIAMOND USING ABRUPT HETEROJUNCTION

The present application discloses a semiconductor device and a method for forming a p-type conductive channel in a diamond using an abrupt heterojunction, which pertain to the technical field of fabrication of semiconductor devices. The method includes: forming a diamond layer on a substrate; forming one or multiple layers of a heterogeneous elementary substance or compound having an acceptor characteristic on an upper surface of the diamond layer; forming a heterojunction at an interface between the diamond layer and an acceptor layer; forming two-dimensional hole gas at one side of the diamond layer with a distance of 10 nm-20 nm away from the heterojunction; and using the two-dimensional hole gas as a p-type conductive channel. The method enables a concentration and a mobility of carriers to maintain stable at a temperature range of 0° C.-1000° C., thereby realizing normal operation of the diamond device at high temperature environment. 1. A method for forming a p-type conductive channel in a diamond using an abrupt heterojunction , comprising the following steps:{'b': 1', '2, 'forming a diamond layer () on a substrate ();'}processing the diamond layer into a hydrogen-terminated diamond layer so that an upper surface of the hydrogen-terminated diamond layer possesses C—H bonds; and{'b': 3', '4', '4, 'forming one or multiple layers of a heterogeneous elementary substance or compound having an acceptor characteristic on the upper surface of the hydrogen-terminated diamond layer, forming a heterojunction at an interface between the hydrogen-terminated diamond layer and an acceptor layer (), forming two-dimensional hole gas () at one side of the hydrogen-terminated diamond layer with a distance of 10 nm-20 nm away from the heterojunction, and using the two-dimensional hole gas () as a p-type conductive channel.'}2. The method of claim 1 , further comprising: before forming the one or multiple layers of the heterogeneous elementary substance or compound having the ...

SEMICONDUCTOR DEVICE

The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage Vof 0.3 V to 0.7 V and a leakage current Jof 1×10A/cmto 1×10A/cmin a rated voltage V. 1. A semiconductor device comprising:a first conductivity type semiconductor layer made of a wide bandgap semiconductor, anda Schottky electrode formed to come into contact with a surface of the semiconductor layer,{'sub': th', 'r', 'R, 'sup': −9', '2', '−4', '2, 'wherein a threshold voltage Vis 0.3 V to 0.7 V, and a leakage current Jin a rated voltage Vis 1×10A/cmto 1×10A/cm.'}2. The semiconductor device according to claim 1 , wherein a breakdown voltage Vof the semiconductor device is 700 V or more claim 1 , and{'sub': R', 'B, 'the rated voltage Vof the semiconductor device is 50 to 90% of the breakdown voltage Vthat is 700 V or more.'}3. The semiconductor device according to claim 1 , wherein on-resistance R·A of the semiconductor device is 0.3 mΩ·cmto 3 mΩ·cm.5. The semiconductor device according to claim 4 , wherein the semiconductor layer includes a second conductivity type electric-field-moderating portion that is selectively formed at the bottom wall of the trench and at the edge part of the bottom wall.6. The semiconductor device according to claim 4 , wherein the electric-field-moderating portion is formed to straddle between the edge part of the bottom wall of the trench and the side wall of the trench.7. The semiconductor device according to claim 6 , wherein the electric-field-moderating portion is formed to lead to an opening end of the trench along the side wall of the trench.8. The semiconductor device according to claim 4 , wherein the trench includes a taper trench that has the bottom wall having a planar shape and the side wall inclined at an angle exceeding 90° with respect to the bottom wall having a ...

SEMICONDUCTOR DEVICE

The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage Vof 0.3 V to 0.7 V and a leakage current Jof 1×10A/cmto 1×10A/cmin a rated voltage V. 1. A semiconductor device , comprising:a substrate;a first conductive type epitaxial layer, formed on a surface of the substrate;a field insulating film, covering a portion of a surface of the first conductive type epitaxial layer, wherein the portion of the surface of the first conductive type epitaxial layer comprises a field region and an active region surrounded by the field region; andan electric field moderating part, positioned in a portion of the field region closer to the active region, wherein a top surface of the electric field moderating part is lower than a surface of the active region, and wherein the electric field moderating part comprises a second conductive type layer.2. The semiconductor device according to claim 1 , further comprising:a plurality of trench in the active region, each trench having a sidewall and a bottom; anda Schottky electrode, contacting at least a portion of the surface of the active region.3. The semiconductor device according to claim 2 , the bottom and the sidewall of the trench in the active region further comprising the electric field moderating part.4. The semiconductor device according to claim 3 , wherein the Schottky electrode is formed to fill the trenches; and the electric field moderating part has a contact portion at the bottom wall of the trench claim 3 , and an ohmic junction is formed between the contact portion and the Schottky electrode filling the trenches.5. The semiconductor device according to claim 3 , wherein a part of the first conductive type epitaxial layer that is different from the electric field moderating part has a first conductive type first part ...

SEMICONDUCTOR DEVICE

The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage Vof 0.3 V to 0.7 V and a leakage current Jof 1×10A/cmto 1×10A/cmin a rated voltage V. 1. A Schottky barrier diode , comprising:a first conductivity type semiconductor substrate made of a wide bandgap semiconductor;a plurality of deformed portions formed at a surface of the first conductive type semiconductor substrate, the plurality of deformed portions arranged in stripes at equal intervals, and each of the deformed portions including a bottom portion which is lower than adjacent other portion of the deformed portions in a thickness direction;a plurality of second conductivity type impurity regions formed at the bottom portions of the plurality of deformed portions;a Schottky electrode being in contact with the surface of the first conductive type semiconductor substrate; andan insulating film formed at a periphery of the Schottky electrode, whereinthe plurality of deformed portions extend in a first direction,lengths of the plurality of deformed portions are decreased in a step-by-step manner near a corner portion of the first conductivity type semiconductor substrate in a plan view such that the plurality of deformed portions have the smallest lengths at both ends in a second direction.2. The Schottky barrier diode according to claim 1 , wherein the first conductivity type semiconductor substrate includes an SiC substrate.3. The Schottky barrier diode according to claim 2 , wherein the first conductivity type is an n-type conductivity and the second conductivity type is a p-type conductivity.4. The Schottky barrier diode according to claim 3 , whereinthe bottom portion of each of the deformed portions includes a bottom wall parallel to the surface of the first conductive type semiconductor substrate, ...

SEMICONDUCTOR PACKAGE WITH GROUNDED FENCE TO INHIBIT DENDRITES OF DIE-ATTACH MATERIALS

The present disclosure relates to a semiconductor package with at least one grounded fence to inhibit dendrites of die-attach materials. The semiconductor package includes a carrier, a die-attach material, and a wire-bonded die. The carrier includes a die pad and a negative carrier contact. The wire-bonded die includes a die body, a negative die contact, a grounded fence, and a bonding wire. A bottom surface of the die body is coupled to the die pad by the die-attach material. The negative die contact and the grounded fence reside over a top surface of the die body. The grounded fence, which has a same DC potential as the die pad, extends between the negative die contact and a periphery of the top surface of the die body. The bonding wire extends from the negative die contact to the negative carrier contact. 1. An apparatus comprising:a carrier comprising a die pad and a first negative carrier contact;a die-attach material; the bottom surface of the die body is coupled with a top surface of the die pad by the die-attach material;', 'the first negative die contact and the first grounded fence reside over the top surface of the die body;', 'the first grounded fence, which has a same DC potential as the die pad, extends between the first negative die contact and a periphery of the top surface of the die body; and', 'the first bonding wire extends from the first negative die contact to the first negative carrier contact., 'a wire-bonded die comprising a die body that has a top surface and a bottom surface opposite the top surface of the die body, a first negative die contact, a first grounded fence, and a first bonding wire, wherein2. The apparatus of wherein the die-attach material is a dendrite forming metal.3. The apparatus of wherein the die-attach material is formed of sintered silver or tin.4. The apparatus of wherein:the carrier further comprises a non-negative carrier contact, wherein the die pad is surrounded by the first negative carrier contact and the non- ...

Multi-layer semiconductor device structure

One embodiment of the instant disclosure provides a semiconductor structure that comprises: a first device layer including a first active layer disposed over a substrate and a first gate layer disposed on the active layer, where at least one of the first active layer and the first gate layer includes a first layer alignment structure; a first bounding layer disposed over the first device layer, the first bounding layer including an opening arranged to detectably expose the first layer alignment structure; and a second device layer disposed over the bounding layer including a second layer alignment structure, where the second layer alignment structure is substantially aligned to the first layer alignment structure through the opening.

DIAMOND SEMICONDUCTOR SYSTEM AND METHOD

Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The method may include the steps of selecting a diamond semiconductor material having a surface, exposing the surface to a source gas in an etching chamber, forming a carbide interface contact layer on the surface; and forming a metal layer on the interface layer. 118. -. (canceled)9. A method of fabricating contacts on diamond semiconductors , the method including the steps of:{'sup': '2', 'selecting a diamond semiconductor material having a surface, the diamond semiconductor material having n-type donor atoms and a diamond lattice, wherein between 0.16% and 0.30% of the n-type donor atoms contribute conduction electrons with mobility greater than 770 cm/Vs to the diamond lattice at 100 kPa and 300K;'}forming a carbide interface contact layer on the surface; andforming a metal layer on the interface contact layer.10. The method of fabricating contacts on diamond semiconductors of claim 9 , wherein the metal layer is a degeneratively doped semiconductor layer.11. The method of fabricating contacts on diamond semiconductors of claim 9 , wherein the metal layer is deposed via sputtering.12. The method of fabricating contacts on diamond semiconductors of claim 9 , wherein the metal layer is deposed via vapor deposition.13. The method of fabricating contacts on diamond semiconductors of claim 9 , wherein the metal layer is a transparent metal.14. The method of fabricating contacts on diamond semiconductors of claim 9 , further including the step of deposing the diamond material on a metal substrate.15. The method of fabricating contacts on diamond semiconductors of claim 9 , further including the step of annealing the diamond material.16. A diamond semiconductor formed according to the method of .17. A method of fabricating contacts on diamond semiconductors claim 9 , the method including the steps of:{'sup': '2', 'selecting a diamond semiconductor material having a surface, ...

Wide-Gap Semiconductor Substrate, Apparatus For Manufacturing Wide-Gap Semiconductor Substrate, And Method For Manufacturing Wide-Gap Semiconductor Substrate

Provided is a method for manufacturing a wide-gap semiconductor substrate enabling formation of a device having low power loss while maintaining high mechanical strength. This method is an etching method for etching a wide-gap semiconductor substrate (W) placed on a platen () disposed in a processing chamber () by means of plasma generated from an etching gas so that only a device formation region of the wide-gap semiconductor substrate (W) is thinned, the method including a step of supplying the etching gas into the processing chamber () and generating the plasma from the etching gas, and a step of applying a bias potential to the platen () to etch only the device formation region of the wide-gap semiconductor substrate (W) so as to thin only the device formation region. 1. A wide-gap semiconductor substrate for forming a device thereon , comprising:a first substrate region as an inner region having a first thickness; anda second substrate region surrounding an outer periphery of the first substrate region and having a second thickness greater than the first thickness,the device being formed on the first substrate region,the first thickness being not less than 10 μm and not more than 50 μm andthe second substrate region being formed to have the second thickness of 100 μm to 350 μm and set to have a radial width of 1 mm to 10 mm.2. The wide-gap semiconductor substrate of claim 1 , wherein the first substrate region is formed by dry etching.3. The wide-gap semiconductor substrate of claim 1 , wherein the wide-gap semiconductor substrate is made of silicon carbide (4H—SiC claim 1 , 6H—SiC claim 1 , or 3C—SiC) claim 1 , gallium nitride (GaN) claim 1 , gallium oxide (GaO) claim 1 , or diamond (C).4. A wide-gap semiconductor substrate manufacturing apparatus etching a wide-gap semiconductor substrate placed on a platen disposed in a processing chamber by means of plasma generated from an etching gas so that only a device formation region of the wide-gap semiconductor ...

Diamond Like Carbon (DLC) in a Semiconductor Stack as a Selector for Non-Volatile Memory Application

Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The semiconductor layer of the selector element can include a trilayer stack of diamond like carbon/silicon/diamond like carbon. Conductive materials of the MSM may include tungsten, titanium nitride, carbon, or a combination thereof. 1. A nonvolatile memory cell comprising:a first electrode layer; wherein the selector element comprises a first conductive layer, a semiconductor layer, and a second conductive layer;', 'wherein the semiconductor layer comprises a trilayer stack of a first diamond like carbon (DLC) sub-layer/a silicon sub-layer/a second diamond like carbon (DLC) sub-layer such that the silicon sub-layer is disposed between the first DLC sub-layer and the second DLC sub-layer;, 'a selector element;'}a resistive switching layer comprising a metal oxide and operable to switch between a first resistive state and a second resistive state different from the first resistive state; and 'wherein the resistive switching layer and the selector are stacked between the first electrode layer and the second electrode layer and are interconnected in series.', 'a second electrode layer,'}2. The nonvolatile memory cell as in claim 1 , wherein a thickness of the trilayer stack is less than about 140 nm.3. The nonvolatile memory cell as in claim 1 , wherein a thickness of each of the first DLC sub-layer and the second DLC sub-layer in the trilayer stack is between about 5 nm and about 50 nm.4. The nonvolatile memory cell as in claim 1 , wherein a thickness of the silicon sub-layer in the trilayer stack is between about 10 nm and about 40 nm.5. The ...

Semiconductor device, semiconductor wafer and method for manufacturing semiconductor device

A semiconductor device according to the present disclosure includes a semiconductor substrate having an effective region and an ineffective region, an upper surface electrode layer provided on an upper surface of the semiconductor substrate and a rear surface electrode layer provided on a rear surface of the semiconductor substrate, wherein the semiconductor substrate includes a lifetime control layer that is provided in the effective region, a measurement layer provided at an upper surface side of the ineffective region and a crystal defect layer that is provided in the ineffective region, the upper surface electrode layer includes a plurality of measurement electrodes provided on the measurement layer, the measurement layer includes a conducting layer at least at a portion where the plurality of measurement electrodes are provided, and the crystal defect layer is provided between the plurality of measurement electrodes.

DIAMOND SUBSTRATE

The crystal plane in the interior of the diamond substrate has a curvature higher than 0 kmand equal to or lower than 1500 kmby preparing a base substrate, forming a plurality of pillar-shaped diamonds formed of diamond single crystals on one side of the base substrate, causing diamond single crystals to grow from tips of each pillar-shaped diamond, coalescing each of the diamond single crystals grown from the tips of each pillar-shaped diamond to form a diamond substrate layer, separating the diamond substrate layer from the base substrate, and manufacturing the diamond substrate from the diamond substrate layer. 1. A diamond substrate formed of diamond single crystals ,wherein the diamond substrate is one self-supported substrate as a flat plate shape in which a front surface and a rear surface of the diamond substrate are formed in parallel and evenly in appearance,a shape of the diamond substrate in an in-plane direction has a circular shape or a circular shape having an orientation flat plane,a diameter of the diamond substrate is equal to or larger than 0.4 inches and equal to or smaller than 8 inches, and{'sup': −1', '−1, 'a crystal plane in an interior of the diamond substrate has a curvature, and the curvature is higher than 0 kmand equal to or lower than 1500 km.'}2. The diamond substrate according to claim 1 , wherein the curvature is higher than 0 kmand equal to or lower than 400 km.3. The diamond substrate according to claim 1 , wherein the curvature is higher than 0 kmand equal to or lower than 200 km.4. The diamond substrate according to claim 1 , wherein the diameter is equal to or larger than 2 inches.5. The diamond substrate according to claim 1 , wherein the diameter is equal to or larger than 2 inches and equal to or smaller than 8 inches.6. The diamond substrate according to claim 1 , wherein the crystal plane has an (001) plane.7. The diamond substrate according to claim 1 , wherein a surface roughness Ra of a surface of the diamond substrate ...