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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 1822. Отображено 100.
01-03-2012 дата публикации

Method for Forming a Semiconductor Device, and a Semiconductor with an Integrated Poly-Diode

Номер: US20120049270A1
Автор: Anton Mauder, Frank Pfirsch, Franz Hirler, Hans-Joachim Schulze
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A method for forming a field effect power semiconductor is provided. The method includes providing a semiconductor body, a conductive region arranged next to a main surface of the semiconductor body, and an insulating layer arranged on the main horizontal surface. A narrow trench is etched through the insulating layer to expose the conductive region. A polycrystalline semiconductor layer is deposited and a vertical poly-diode structure is formed. The polycrystalline semiconductor layer has a minimum vertical thickness of at least half of the maximum horizontal extension of the narrow trench. A polycrystalline region which forms at least a part of a vertical poly-diode structure is formed in the narrow trench by maskless back-etching of the polycrystalline semiconductor layer. Further, a semiconductor device with a trench poly-diode is provided.

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Номер записи: 1
29-03-2012 дата публикации

Power Semiconductor Device Having Gate Electrode Coupling Portions for Etchant Control

Номер: US20120074472A1
Автор: Koichiro Sakanishi, Koji Fujishima, Tsuyoshi Kachi
Принадлежит: Renesas Electronics Corp

A general insulated gate power semiconductor active element with many gate electrodes arranged in parallel has a laminated structure including a barrier metal film and a thick aluminum electrode film formed over the gate electrodes via an interlayer insulating film. When the aluminum electrode film is embedded in between the gate electrodes in parallel, voids may be generated with the electrodes. Such voids allow the etchant to penetrate in wet etching, which may promote the etching up to a part of the electrode film in an active cell region which is to be left. Thus, an insulated gate power semiconductor device is provided to include gate electrodes protruding outward from the inside of the active cell region, and a gate electrode coupling portion for coupling the gate electrodes outside the active cell region. The gate electrode coupling portion is covered with a metal electrode covering the active cell region.

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Номер записи: 2
26-04-2012 дата публикации

Dummy gate for a high voltage transistor device

Номер: US20120098063A1
Автор: Han-Chung Lin, Yung-Chih Tsai
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The present disclosure provides a semiconductor device. The semiconductor device includes a first doped region and a second doped region both formed in a substrate. The first and second doped regions are oppositely doped. The semiconductor device includes a first gate formed over the substrate. The first gate overlies a portion of the first doped region and a portion of the second doped region. The semiconductor device includes a second gate formed over the substrate. The second gate overlies a different portion of the second doped region. The semiconductor device includes a first voltage source that provides a first voltage to the second gate. The semiconductor device includes a second voltage source that provides a second voltage to the second doped region. The first and second voltages are different from each other.

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Номер записи: 3
02-08-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120193711A1
Автор: Junichi Mitani, Masayoshi Asano
Принадлежит: Fujitsu Semiconductor Ltd

A gate electrode, an element isolation film and a drain region in an LDMOS transistor formation region and a gate electrode, an element isolation film and an anode region in an ESD protection element formation region are formed to satisfy relationships of A 1 ≧A 2 and B 1 <B 2 where the LDMOS transistor formation region has an overlap length A 1 of the gate electrode and the element isolation film and a distance B 1 between the gate electrode and the drain region, and the ESD protection element formation region has an overlap length A 2 of the gate electrode and the element isolation film and a distance B 2 between the gate electrode and the anode region.

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Номер записи: 4
08-11-2012 дата публикации

Integrating schottky diode into power mosfet

Номер: US20120280307A1
Автор: Anup Bhalla, Daniel Ng, Hong Chang, John Chen, Jongoh Kim, YI Su
Принадлежит: ALPHA AND OMEGA SEMICONDUCTOR INC

A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in the trenches that define the mesa. A second conductive region is formed in the portion of the trenches that define the mesa. The second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region. A first electrical contact is made to the second conductive regions and a second electrical contact to the first conductive region in the shield electrode pickup trenches. One or more Schottky diodes are formed within the mesa.

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Номер записи: 5
21-02-2013 дата публикации

High density lateral dmos and associated method for making

Номер: US20130043534A1
Автор: Donald R. Disney, Lei Zhang, Tiesheng Li
Принадлежит: Monolithic Power Systems Inc

The present disclosure discloses a lateral DMOS with recessed source contact and method for making the same. The lateral DMOS comprises a recessed source contact which has a portion recessed into a source region to reach a body region of the lateral DMOS. The lateral DMOS according to various embodiments of the present invention may have greatly reduced size and may be cost saving for fabrication.

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Номер записи: 6
25-07-2013 дата публикации

Semiconductor device with high voltage transistor

Номер: US20130189820A1
Автор: Masashi Shima
Принадлежит: Fujitsu Semiconductor Ltd

A method for manufacturing a semiconductor includes: forming an isolation region defining first, second and third active regions; implanting first impurity ions of a first conductivity type to form first, second and third wells; implanting second impurity ions of the first conductivity type to form first and second channel regions; implanting second impurity ions of a second conductivity to form a first drain region, such that a portion of the first channel region is overlapped with the first drain region; forming first, second and third gate electrodes, the first gate electrode superposing a portion of the first drain region and covering one lateral end of the first channel region; forming first insulating side wall spacers and a second insulating side wall spacer on a side wall of the first gate electrode; and implanting fourth impurity ions of the second conductivity type to form second drain/source regions.

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Номер записи: 7
26-12-2013 дата публикации

Trench shielding structure for semiconductor device and method

Номер: US20130341712A1
Автор: Brian Pratt, Peter A. Burke, Prasad Venkatraman
Принадлежит: Semiconductor Components Industries LLC

A shielding structure for a semiconductor device includes a plurality of trenches. The trenches include passivation liners and shield electrodes, which are formed therein. In one embodiment, the shielding structure is placed beneath a control pad. In another embodiment, the shielding structure is placed beneath a control runner.

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Номер записи: 8
02-01-2014 дата публикации

Mos transistor device in common source configuration

Номер: US20140001855A1
Автор: Jacek Korec, Stephen L. Colino
Принадлежит: Texas Instruments Inc

A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the semiconductor substrate and additional p-channel LDMOS transistors formed over the semiconductor substrate. First drain and gate electrodes are formed over the substrate and are coupled to the first LDMOS transistor. Additional drain and gate electrodes are formed over the substrate and are coupled to the second LDMOS transistor. A common source electrode for the first and second LDMOS transistors is also formed over the substrate.

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Номер записи: 9
09-01-2014 дата публикации

Metal/Semiconductor Compound Thin Film and a DRAM Storage Cell and Method of Making

Номер: US20140008710A1
Автор: Wu Dongping, Zhang Shili, ZHANG Wei, Zhu Zhiwei
Принадлежит: FUDAN UNIVERSITY

A metal-semiconductor-compound thin film is disclosed, which is formed between a semiconductor layer and a polycrystalline semiconductor layer, the metal-semiconductor-compound thin film having a thickness of about 2˜5 nm, so as to improve a contact between the semiconductor layer and the polycrystalline semiconductor layer. A DRAM storage cell is also disclosed. A metal-semiconductor-compound thin film having a thickness of about 2-5 nm is added between a drain region of a MOS transistor and a polycrystalline semiconductor buffer layer in the DRAM storage cell, so as to enhance read/write speed of the transistor of the DRAM storage cell while preventing excessive increase in leakage current between the drain region and a semiconductor substrate. A method for making a DRAM storage cell is also disclosed. A DRAM storage cell made using the method has a metal-semiconductor-compound thin film, with a thickness controlled at about 2˜5 nm, formed between a drain region of its MOS transitor and a polycrystalline semiconductor buffer layer, so as to enhance the performance of the DRAM storage cell. 1. A metal-semiconductor-compound thin film formed between a semiconductor layer and a polycrystalline semiconductor layer , to improve a contact between the semiconductor layer and the polysilicon layer , characterized in that the metal-semiconductor-compound thin film has a thickness of 2˜5 nm.2. The metal-semiconductor-compound thin film of claim 1 , characterized in that the semiconductor layer is silicon or silicon-on-insulator claim 1 , the polycrystalline semiconductor layer includes doped polysilicon claim 1 , and the metal/semiconductor compound thin film includes a metal silicide.3. The metal-semiconductor-compound thin film of claim 1 , characterized in that the semiconductor layer is germanium or germanium-on-insulator claim 1 , the polycrystalline semiconductor layer includes doped polycrystalline germanium claim 1 , and the metal/semiconductor compound thin film ...

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Номер записи: 10
12-01-2017 дата публикации

Semiconductor device

Номер: US20170012048A1
Автор: Nobuo Tsuboi
Принадлежит: Renesas Electronics Corp

A semiconductor device can be reduced in size. The semiconductor device has a first conductivity type p type well layer extending in the X direction of the main surface of a semiconductor substrate; a reference potential wire coupled with the p type well layer, and extending in the X direction; first and second active regions arranged on the opposite sides of the reference potential wire in the Y direction; and a gate electrode layer extending in the Y direction in such a manner as to cross with the first and second active regions. Then, the gate electrode layer has a first gate electrode of a second conductivity type at the crossing part with the first active region, a second gate electrode of the second conductivity type at the crossing part with the second active region, and a non-doped electrode between the first gate electrode and the second gate electrode.

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Номер записи: 11
14-01-2016 дата публикации

SEMICONDUCTOR DEVICES INCLUDING SEPARATE LINE PATTERNS

Номер: US20160013196A1
Автор: HAN Jeehoon, PARK Bongtae, PARK HYEONG, You Jang-Hyun
Принадлежит:

A semiconductor device includes a plurality of lines disposed on a semiconductor substrate, and remaining line patterns disposed spaced apart from the lines on extensions from the lines. The lines include first end-portions adjacent to the remaining line patterns. The remaining line patterns include second end-portions adjacent to the lines. The first end-portions and second end-portions are formed to have mirror symmetry with respect to each other. 120.-. (canceled)21. A semiconductor device comprising:a semiconductor substrate including an active region;a plurality of conductive lines on the semiconductor substrate, wherein end portions of each of the plurality of conductive lines extend on the active region of the semiconductor substrate; anda plurality of conductive line patterns on the semiconductor substrate spaced apart from the plurality of conductive lines, wherein end portions of each of the plurality of conducive line patterns extend on the active region of the semiconductor substrate, wherein each of the plurality of conductive line patterns corresponds to a respective one of the conductive lines, wherein the plurality of conductive line patterns are arranged in pairs, wherein conductive line patterns of each pair are connected, and wherein conductive line patterns of different pairs are separate.22. The semiconductor device of wherein the end portions of the plurality of conductive lines on the active region have mirror symmetry with respect to the end portions of the plurality of conductive line patterns on the active region.23. The semiconductor device of further comprising:a first plurality of floating gate patterns, wherein each of the first plurality of floating gate patterns is between a respective one of the end portions of the plurality of conductive lines and the active region; anda second plurality of floating gate patterns, wherein each of the second plurality of floating gate patterns is between a respective one of the end portions of the ...

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Номер записи: 12
15-01-2015 дата публикации

Iii-v compound semiconductor device having metal contacts and method of making the same

Номер: US20150014792A1
Автор: Richard Kenneth Oxland
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device comprises a semiconductor substrate; a channel layer of at least a first III-V semiconductor compound above the semiconductor substrate; a gate stack structure above a first portion of the channel layer; a source region and a drain region comprising at least a second III-V semiconductor compound above a second portion of the channel layer; and a first metal contact structure above the S/D regions comprising a first metallic contact layer contacting the S/D regions. The first metallic contact layer comprises at least one metal-III-V semiconductor compound.

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Номер записи: 13
11-01-2018 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20180012890A1
Автор: HAO Long, Jin Yan, Li Wei, WANG Dejin
Принадлежит:

A manufacturing method of a semiconductor device, comprising the following steps: providing a semiconductor substrate comprising a low-voltage device region and a high-voltage device region; forming first gate oxide layers in a non-gate region of the high-voltage device region and the low-voltage device region and a second gate oxide layer in a gate region of the high-voltage device region; the thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer; forming a first polysilicon gate and a first sidewall structure on the surface of the first gate oxide layer of the low-voltage device region and a second polysilicon gate and a second sidewall structure on the surface of the second gate oxide layer; the width of the second gate oxide layer is greater than the width of the second polysilicon gate; performing source drain ions injection to form a source drain extraction region; after depositing a metal silicide area block (SAB), performing a photolithographic etching on the metal SAB and forming metal silicide. The above manufacturing method of a semiconductor device simplifies process steps and reduces process cost. The present invention also relates to a semiconductor device. 1. A method of manufacturing a semiconductor device , comprising the steps of:providing a semiconductor substrate comprising a low-voltage device region and a high-voltage device region;forming a first gate oxide layer in a non-gate region of the high-voltage device region and the low-voltage device region, and forming a second gate oxide layer in a gate region of the high-voltage device region; wherein a thickness of the second gate oxide layer is greater than a thickness of the first gate oxide layer;forming a first polysilicon gate and a first sidewall structure on a surface of the first gate oxide layer of the low-voltage device region, and forming a second polysilicon gate and a second sidewall structure on a surface of the second gate oxide layer; ...

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Номер записи: 14
14-01-2016 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20160013287A1
Автор: YAMAMOTO Yoshiki
Принадлежит:

While increasing a threshold voltage of a MOSFET configuring a CMOS, electric power saving of elements is achieved by suppressing excessive increase in the threshold voltage, and occurrence of performance variation among the elements is suppressed. A gate electrode of an NMOS is made of a P-type semiconductor film, a high-permittivity film is provided in a gate insulating film of the NMOS, and an impurity is prevented from being introduced into a channel region of the NMOS. Moreover, a high-permittivity film is provided also in a gate insulating film of a PMOS. 1. A semiconductor device comprising:a semiconductor substrate;a first insulating film on the semiconductor substrate;a semiconductor layer on the first insulating film;a first gate electrode including a first semiconductor film of a P type, which is formed on the semiconductor layer via a second insulating film; anda pair of first source/drain regions formed by introducing an impurity of an N type into the semiconductor layer next to the first gate electrode,wherein the semiconductor substrate, the first insulating film, and the semiconductor layer configure a SOI substrate,the first gate electrode and the pair of first source/drain regions configure an N-channel-type field-effect transistor, andthe second insulating film contains a material having a permittivity higher than a permittivity of silicon oxide.2. The semiconductor device according to claim 1 ,wherein the semiconductor layer mutually between the pair of first source/drain regions is an intrinsic semiconductor layer.3. The semiconductor device according to claim 1 ,{'sup': 17', '3, 'wherein an impurity concentration of the P type in the semiconductor layer mutually between the pair of first source/drain regions is 1×10/cmor lower.'}4. The semiconductor device according to claim 1 ,wherein, among a first region and a second region arranged in a direction along an upper surface of the SOI substrate, the N-channel-type field-effect transistor is ...

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Номер записи: 15
14-01-2016 дата публикации

TRANSISTOR INCLUDING A STRESSED CHANNEL, A METHOD FOR FABRICATING THE SAME, AND AN ELECTRONIC DEVICE INCLUDING THE SAME

Номер: US20160013315A1
Автор: JI Yun-Hyuck
Принадлежит:

A semiconductor device includes a first channel, a second channel, a first strained gate electrode including a first lattice-mismatched layer for applying a first stress to the first channel, and a second strained gate electrode including a second lattice-mismatched layer for applying a second stress to the second channel. 113.-. (canceled)14. A method for fabricating a semiconductor device , the method comprising:preparing a substrate which includes a first transistor region and a second transistor region;forming a first strained gate electrode which includes a first lattice-mismatched crystalline silicon layer disposed over the first transistor region; andforming a second strained gate electrode which includes a second lattice-mismatched crystalline silicon layer disposed over the second transistor region.15. The method according to claim 14 , wherein the forming of the first strained gate electrode comprises:forming a gate dielectric layer over the substrate;forming an amorphous silicon layer over the gate dielectric layer;doping arsenic into a lower portion of the amorphous silicon layer to form a stacked structure of a doped amorphous silicon layer and an undoped amorphous silicon layer; andperforming an annealing process on the stacked structure to convert the stacked structure into the first lattice-mismatched crystalline silicon layer.16. The method according to claim 14 , wherein the forming of the second strained gate electrode comprises:forming a gate dielectric layer over the substrate;forming an amorphous silicon layer over the gate dielectric layer;doping boron into a lower portion of the amorphous silicon layer to form a first doped amorphous silicon layer;doping germanium into a upper portion of the amorphous silicon layer to form a second doped amorphous silicon layer over the first doped amorphous silicon layer; andperforming an annealing process on the first and second amorphous silicon layers to convert the first doped amorphous silicon layer and ...

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Номер записи: 16
11-01-2018 дата публикации

SEMICONDUCTOR DEVICES

Номер: US20180012970A1
Автор: KIM Myoungsoo
Принадлежит: Samsung Electroncis Co., Ltd.

The semiconductor device including a device isolation layer disposed in a substrate and defining an active region, a first conductive pattern on the active region, an impurity region in the active region on a side of the first conductive pattern, a second conductive pattern on the active region between the impurity region and the first conductive pattern, a first spacer between the first conductive pattern and the second conductive pattern, and a contact plug disposed on and electrically connected to the first conductive pattern may be provided. The second conductive pattern may have a width less than a width of the contact plug. 1. A semiconductor device comprising:a device isolation layer in a substrate, the device isolation layer defining an active region;a first conductive pattern on the active region;an impurity region in the active region, the impurity region on a side of the first conductive pattern;a second conductive pattern on the active region, the second conductive pattern between the impurity region and the first conductive pattern;a first spacer between the first conductive pattern and the second conductive pattern; anda contact plug on the first conductive pattern, if contact plug electrically connected to the first conductive pattern, a width of the second conductive pattern being less than a width of the contact plug.2. The semiconductor device of claim 1 , wherein the first and second conductive patterns comprise a same material.3. The semiconductor device of claim 1 , further comprising:a third conductive pattern on the active region, the third conductive pattern between the second conductive pattern and the first impurity region, a width of the third conductive pattern being less than the width of the contact plug; anda second spacer between the second conductive pattern and the third conductive pattern.4. The semiconductor device of claim 1 , wherein the first conductive pattern is in an electrically floating state.5. The semiconductor device of ...

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Номер записи: 17
03-02-2022 дата публикации

DESIGN AND MANUFACTURE OF POWER DEVICES HAVING INCREASED CROSS OVER CURRENT

Номер: US20220037470A1
Автор: PARK Jaehoon, Singh Ranbir, Sundaresan Siddarth
Принадлежит:

An embodiment relates to a n-type planar gate DMOSFET comprising a Silicon Carbide (SiC) substrate. The SiC substrate includes a N+ substrate, a N− drift layer, a P-well region and a first N+ source region within each P-well region. A second N+ source region is formed between the P-well region and a source metal via a silicide layer. During third quadrant operation of the DMOSFET, the second N+ source region starts depleting when a source terminal is positively biased with respect to a drain terminal. The second N+ source region impacts turn-on voltage of body diode regions of the DMOSFET by establishing short-circuitry between the P-well region and the source metal when the second N+ source region is completely depleted. 1. A device comprising a unit cell on a Silicon Carbide (SiC) substrate , the unit cell comprising:a first conductivity type source region;a second conductivity type well contact region;a second conductivity type well region;a first metal region; anda silicide layer,wherein the device comprises a vertical Silicon Carbide double-implantation metal oxide semiconductor field-effect transistor (DMOSFET) comprising a drain terminal on a backside of the SiC substrate and a source terminal on a topside of the SiC substrate,wherein the first metal region is in contact with the second conductivity type well contact region, andwherein the silicide layer is in contact with the second conductivity type well contact region through the first metal region.2. The device of claim 1 , wherein the first metal region comprises a target work function.3. The device of claim 2 , wherein the target work function ranges from 3.5 electron volts to 6 electron volts.4. The device of claim 1 , wherein a first conductivity type region comprises one of (a) a p-type region and (b) a n-type region.5. The device of claim 1 , wherein a second conductivity type region comprises one of (a) a p-type region and (b) a n-type region.6. The device of claim 4 , wherein the first ...

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Номер записи: 18
03-02-2022 дата публикации

DESIGN AND MANUFACTURE OF POWER DEVICES HAVING INCREASED CROSS OVER CURRENT

Номер: US20220037471A1
Автор: PARK Jaehoon, Singh Ranbir, Sundaresan Siddarth
Принадлежит:

An embodiment relates to a n-type planar gate DMOSFET comprising a Silicon Carbide (SiC) substrate. The SiC substrate includes a N+ substrate, a N− drift layer, a P-well region and a first N+ source region within each P-well region. A second N+ source region is formed between the P-well region and a source metal via a silicide layer. During third quadrant operation of the DMOSFET, the second N+ source region starts depleting when a source terminal is positively biased with respect to a drain terminal. The second N+ source region impacts turn-on voltage of body diode regions of the DMOSFET by establishing short-circuitry between the P-well region and the source metal when the second N+ source region is completely depleted. 1. A device comprising a unit cell on a Silicon Carbide (SiC) substrate , the unit cell comprising:a first conductivity type source region;a second conductivity type well region;a second conductivity type well contact region; anda silicide layer,wherein the device comprises a vertical Silicon Carbide double-implantation metal oxide semiconductor field-effect transistor (DMOSFET) comprising a drain terminal on a backside of the SiC substrate and a source terminal on a topside of the SiC substrate,wherein a lateral extent of the second conductivity type well contact region varies with a non-zero value in direction orthogonal to the unit cell,wherein the second conductivity type well contact region is located adjacent and contiguous between the first conductivity type source region in a lateral direction, andwherein the second conductivity type well contact region is located between the silicide layer and the second conductivity type well region in a vertical direction.2. The device of claim 1 , wherein the second conductivity type well contact region comprises a periodic contact with a source metal region via the silicide layer between an adjacent interlayer dielectric (ILD) region.3. The device of claim 1 , wherein the second conductivity type well ...

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Номер записи: 19
03-02-2022 дата публикации

Design and manufacture of power devices having increased cross over current

Номер: US20220037472A1
Автор: JaeHoon PARK, Ranbir Singh, Siddarth Sundaresan
Принадлежит: GeneSIC Semiconductor Inc

An embodiment relates to a n-type planar gate DMOSFET comprising a Silicon Carbide (SiC) substrate. The SiC substrate includes a N+ substrate, a N− drift layer, a P-well region and a first N+ source region within each P-well region. A second N+ source region is formed between the P-well region and a source metal via a silicide layer. During third quadrant operation of the DMOSFET, the second N+ source region starts depleting when a source terminal is positively biased with respect to a drain terminal. The second N+ source region impacts turn-on voltage of body diode regions of the DMOSFET by establishing short-circuitry between the P-well region and the source metal when the second N+ source region is completely depleted.

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Номер записи: 20
03-02-2022 дата публикации

Design and manufacture of power devices having increased cross over current

Номер: US20220037473A1
Автор: JaeHoon PARK, Ranbir Singh, Siddarth Sundaresan
Принадлежит: GeneSIC Semiconductor Inc

An embodiment relates to a n-type planar gate DMOSFET comprising a Silicon Carbide (SiC) substrate. The SiC substrate includes a N+ substrate, a N− drift layer, a P-well region and a first N+ source region within each P-well region. A second N+ source region is formed between the P-well region and a source metal via a silicide layer. During third quadrant operation of the DMOSFET, the second N+ source region starts depleting when a source terminal is positively biased with respect to a drain terminal. The second N+ source region impacts turn-on voltage of body diode regions of the DMOSFET by establishing short-circuitry between the P-well region and the source metal when the second N+ source region is completely depleted.

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Номер записи: 21
10-02-2022 дата публикации

Insulated trench gates with multiple layers for improved performance of semiconductor devices

Номер: US20220045189A1
Автор: Paul M. Moore, Richard A. Blanchard
Принадлежит: Pakal Technologies Inc

Trenches having a gate oxide layer are formed in the surface of a silicon wafer for vertical gates. Conductive doped polysilicon is then deposited in the trenches to form a relatively thin layer of doped polysilicon along the sidewalls. Thus, there is a central cavity surrounded by polysilicon. Next, the cavity is filled in with a much higher conductivity material, such as aluminum, copper, a metal silicide, or other conductor to greatly reduce the overall resistivity of the trenched gates. The thin polysilicon forms an excellent barrier to protect the gate oxide from diffusion from the inner conductor atoms. The inner conductor and the polysilicon conduct the gate voltage in parallel to lower the resistance of the gates, which increases the switching speed of the device. In another embodiment, a metal silicide is used as the first layer, and a metal fills the cavity.

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Номер записи: 22
24-01-2019 дата публикации

Method of Forming High-Voltage Transistor with Thin Gate Poly

Номер: US20190027487A1
Автор: Chang Kuo Tung, CHEN Chun, KANG Inkuk, Kang Sung-Taeg, Kim Unsoon, Pak James
Принадлежит: CYPRESS SEMICONDUCTOR CORPORATION

A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET. 1. A method of fabricating a semiconductor device comprising:depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region;forming a dielectric layer over the polysilicon gate layer;depositing a height-enhancing (HE) film over the dielectric layer, the HE film comprising an amorphous silicon film or a polysilicon film;patterning the HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region;implanting the HE film with a pre-amorphizing implant;performing a high energy implant to form at least one lightly doped region in a source or drain (S/D) region in the substrate adjacent to the HVFET gate;removing the HE film; andforming a low voltage (LV) logic FET in the peripheral region, wherein the LV logic FET is a high-k metal-gate (HKMG) logic FET.2. The method of claim 1 , wherein a depth of the lightly doped region in the substrate is greater than a height of the HVFET gate.34-. (canceled)5. The method of claim 1 , wherein removing the HE ...

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Номер записи: 23
01-02-2018 дата публикации

High Voltage Transistor Structure and Method

Номер: US20180033888A1
Автор: Chen Jing-Ying, Chen Po-Yu, Huang Wan-Hua, Wu Kuo-Ming
Принадлежит:

A device comprises a buried layer over a substrate, a first well over the buried layer, a first high voltage region and a second high voltage region extending through the first well, a first drain/source region in the first high voltage region, a first gate electrode over the first well, a first spacer on a first side of the first gate electrode, wherein the first spacer is between the first drain/source region and the first gate electrode, a second spacer on a second side of the first gate electrode, a second drain/source region in the second high voltage region and a first isolation region in the second high voltage region and between the second drain/source region and the first gate electrode. 1. A semiconductor device comprising:a substrate of a first conductivity;a buried layer over the substrate and having a second conductivity;a first well over the buried layer, wherein the first well is of the second conductivity;a first high voltage region and a second high voltage region extending through the first well, wherein the first high voltage region and the second high voltage region are of the first conductivity;a first drain/source region in the first high voltage region and of the first conductivity;a first gate electrode over the first well;a first spacer on a first side of the first gate electrode, wherein the first spacer is between the first drain/source region and the first gate electrode;a second spacer on a second side of the first gate electrode;a second drain/source region in the second high voltage region and of the first conductivity; anda first isolation region in the second high voltage region and between the second drain/source region and the first gate electrode.2. The semiconductor device of claim 1 , wherein:the first drain/source region is a source; andthe second drain/source region is a drain.3. The semiconductor device of claim 1 , wherein:a bottommost surface of the first isolation region is lower than a bottommost surface of the second ...

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Номер записи: 24
17-02-2022 дата публикации

Semiconductor device and method of forming the same

Номер: US20220052041A1
Автор: Meng-Han LIN, Te-An Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device includes a substrate, a metal gate and a poly gate. The substrate includes a first region and a second region. The metal gate is disposed on the first region of the substrate. The poly gate is disposed on the second region of the substrate. A gate area of the poly gate is greater than that of the metal gate.

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Номер записи: 25
17-02-2022 дата публикации

Method Of Making Memory Cells, High Voltage Devices And Logic Devices On A Substrate With Silicide On Conductive Blocks

Номер: US20220052059A1
Автор: Do Nhan, Liu Xian, Song Guo Xiang, SUN JACK, Wang Chunming, XING LEO, YANG ANDY
Принадлежит:

A method of forming a semiconductor device includes recessing the upper surface of first and second areas of a semiconductor substrate relative to the third area of the substrate, forming a pair of stack structures in the first area each having a control gate over a floating gate, forming a first source region in the substrate between the pair of stack structures, forming an erase gate over the first source region, forming a block of dummy material in the third area, forming select gates adjacent the stack structures, forming high voltage gates in the second area, forming a first blocking layer over at least a portion of one of the high voltage gates, forming silicide on a top surface of the high voltage gates which are not underneath the first blocking layer, and replacing the block of dummy material with a block of metal material. 1. A method of forming a semiconductor device , comprising:providing a substrate of semiconductor material that includes a first area, a second area and a third area;recessing an upper surface of the substrate in the first area and an upper surface of the substrate in the second area relative to an upper surface of the substrate in the third area;forming a pair of stack structures in the first area, wherein each of the stack structures includes a floating gate of conductive material disposed over and insulated from the upper surface of the substrate in the first area and a first non-floating gate of conductive material disposed over and insulated from the floating gate;forming a first source region in the substrate between the pair of stack structures in the first area;forming a second non-floating gate disposed over and insulated from the first source region in the first area;forming a block of dummy material disposed over and insulated from the upper surface of the substrate in the third area;forming third non-floating gates of conductive material disposed over and insulated from the upper surface of the substrate in the first area and ...

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Номер записи: 26
31-01-2019 дата публикации

Integrated semiconductor device and method for manufacturing the same

Номер: US20190035783A1
Автор: In Sik Jung, Jae Hyung JANG, Jin Yeong SON, Jun Hyun Kim, Kwang Il Kim, Young Bae Kim
Принадлежит: MagnaChip Semiconductor Ltd

A semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed in the first region and second region, respectively, wherein the first transistor includes a thick gate insulating layer and a thin buffer insulating layer formed in the substrate, a first gate electrode formed on the thick gate insulating layer, a first spacer formed on the thin buffer insulating layer, and a source region and a drain region formed in the substrate.

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Номер записи: 27
31-01-2019 дата публикации

PROOF MASS AND POLYSILICON ELECTRODE INTEGRATED THEREON

Номер: US20190035905A1
Автор: Jayaraman Logeeswaran Veerayah, Johari-Galle Houri, Kim Bongsang, SEEGER Joseph, Shin Jongwoo
Принадлежит:

A method includes depositing a silicon layer over a first oxide layer that overlays a first silicon substrate. The method further includes depositing a second oxide layer over the silicon layer to form a composite substrate. The composite substrate is bonded to a second silicon substrate to form a micro-electro-mechanical system (MEMS) substrate. Holes within the second silicon substrate are formed by reaching the second oxide layer of the composite substrate. The method further includes removing a portion of the second oxide layer through the holes to release MEMS features. The MEMS substrate may be bonded to a CMOS substrate. 1. A method comprising:depositing a silicon layer over a first oxide layer that overlays a first silicon substrate;depositing a second oxide layer over the silicon layer to form a composite substrate;bonding the composite substrate to a second silicon substrate to form a micro-electro-mechanical system (MEMS) substrate;forming holes within the second silicon substrate reaching the second oxide layer of the composite substrate;removing a portion of the second oxide layer through the holes to release MEMS features; andbonding the MEMS substrate to a CMOS substrate.2. The method as described in further comprising removing a portion of the first oxide layer through the holes.3. The method as described in further comprising forming vias from the second silicon substrate to the first silicon layer to provide electrical connection between the second silicon substrate and the composite substrate.4. The method as described in further comprising filling the vias with polycrystalline silicon.5. The method as described in claim 3 , wherein the forming the vias is through an etching process.6. The method as described in further comprising forming a standoff through patterning and etching process.7. The method as described in further comprising depositing Germanium on the standoff for eutectically bonding the MEMS substrate to the CMOS substrate.8. The ...

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Номер записи: 28
07-02-2019 дата публикации

Methods, apparatus and system for forming increased surface regions within epi structures for improved trench silicide

Номер: US20190043944A1
Автор: Annie Levesque, Judson R. Holt, Matthew W. Stoker, Timothy J. McArdle
Принадлежит: Globalfoundries Inc

At least one method, apparatus and system disclosed herein involves forming increased surface regions within EPI structures. A fin on a semiconductor substrate is formed. On a top portion of the fin, an epitaxial (EPI) structure is formed. The EPI structure has a first EPI portion having a first material and a second EPI portion having a second material. The first and second EPI portions are separated by a first separation layer. A first cavity is formed within the EPI structure by removing a portion of the second material in the second portion. A first conductive material is deposited into the first cavity.

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Номер записи: 29
03-03-2022 дата публикации

METHOD OF MANUFACTURING MICROELECTRONIC COMPONENTS

Номер: US20220068724A1
Автор: Fitz Clemens, NEMOUCHI Fabrice, Posseme Nicolas
Принадлежит: Commissariat A L'Energie Atomique Et Aux Energies Alternatives

A method is provided for producing a plurality of transistors on a substrate comprising at least two adjacent active areas separated by at least one electrically-isolating area, each transistor of the plurality of transistors including a gate having a silicided portion, and first and second spacers on either side of the gate, the first spacers being located on sides of the gate and the second spacers being located on sides of the first spacers. The method includes forming the gates of the transistors, forming the first spacers, forming the second spacers siliciding the gates so as to form the silicided portions of the gates, and removing the second spacers. The removal of the second spacers takes place during the silicidation of the gates and before the silicided portions are fully formed.

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Номер записи: 30
01-03-2018 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20180061755A1
Автор: Habu Mariko, KAWAHARA Shinji, TAKATA Osamu, YAMAMOTO Takeshi
Принадлежит:

A semiconductor device includes a semiconductor substrate comprising an upper layer portion, a first insulating member located in the upper layer portion of the semiconductor substrate and having one or more corner portions, an electrode located on the semiconductor substrate, wherein the electrode overlies at least one of the corner portions of the first insulating member, and an insulating film located between the semiconductor substrate and the electrode. 1. A semiconductor device , comprising:a semiconductor substrate comprising an upper layer portion;a first insulating member located in the upper layer portion of the semiconductor substrate and having one or more corner portions;an electrode located on the semiconductor substrate, wherein the electrode overlies at least one of the corner portions of the first insulating member; andan insulating film located between the semiconductor substrate and the electrode.2. The semiconductor device according to claim 1 , wherein{'b': '3', 'the first insulating member has an n-gonal shape, where n is an integer not less than ;'}n electrodes are located on the semiconductor substrate; andeach electrode of the n electrodes overlies a different corner portion of the first insulating member.3. The semiconductor device according to claim 2 , wherein n is 4.4. The semiconductor device according to claim 1 , further comprising an impurity-containing layer located in the upper layer portion in a location spaced from the first insulating member.5. The semiconductor device according to claim 4 , wherein the conductivity type of the impurity-containing layer is different from the conductivity type of the upper layer portion.6. The semiconductor device according to claim 1 , further comprising a second insulating member located in the upper layer portion of the semiconductor substrate and surrounding the first insulating member.7. The semiconductor device according to claim 1 , wherein the electrode further comprises:a silicon layer; ...

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Номер записи: 31
08-03-2018 дата публикации

Power device integration on a common substrate

Номер: US20180069077A1
Автор: Boyi Yang, Jacek Korec
Принадлежит: Silanna Asia Pte Ltd

A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

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Номер записи: 32
08-03-2018 дата публикации

Tunable breakdown voltage rf fet devices

Номер: US20180069088A1
Автор: John J. Pekarik, Qizhi Liu, Vibhor Jain
Принадлежит: International Business Machines Corp

A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

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Номер записи: 33
27-02-2020 дата публикации

Super-Self-Aligned Contacts and Method for Making the Same

Номер: US20200066722A1
Автор: Smayling Michael C.
Принадлежит:

A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. A width of each second hard mask filament is set to define an active area contact-to-gate structure spacing. A first passage is etched between facing exposed side surfaces of a given pair of neighboring second hard mask filaments and through a depth of the semiconductor wafer to an active area. A second passage is etched through a given first hard mask portion and through a depth of the semiconductor wafer to a top surface of the underlying gate structure. An electrically conductive material is deposited within both the first and second passages to respectively form an active area contact and a gate contact. 1. A semiconductor device , comprising:a first linear gate structure that does not form a transistor gate electrode;a second linear gate structure located next to the first linear gate structure, the second linear gate structure forming a first PMOS transistor and a first NMOS transistor;a third linear gate structure located next to the second linear gate structure, the third linear gate structure forming a second PMOS transistor and a second NMOS transistor;a fourth linear gate structure located next to the third linear gate structure, wherein the fourth linear gate structure does not form a transistor gate electrode;a first gate contact physically connected to the second linear gate structure at a location between the first PMOS transistor and the first NMOS transistor; anda second gate contact physically connected to the third linear gate structure at a location between the second PMOS transistor and the second NMOS transistor.2. The semiconductor device as recited in claim 1 , wherein each of the first claim 1 , second claim 1 , third claim 1 , and fourth linear gate structures extends lengthwise in ...

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Номер записи: 34
11-03-2021 дата публикации

ELECTRONIC DEVICES INCLUDING CAPACITORS, AND RELATED SYSTEMS

Номер: US20210074864A1
Автор: Smith Michael A.
Принадлежит:

A semiconductor structure includes a capacitor structure comprising an active region comprising opposing field edges parallel to a first horizontal direction and a gate region comprising opposing gate edges parallel to a second horizontal direction transverse to the first horizontal direction. The semiconductor structure also comprises a first dielectric material adjacent at least one of the opposing field edges or the opposing gate edges and a second dielectric material adjacent the active area and abutting portions of the first dielectric material. A height of the second dielectric material in a vertical direction may be less than the height of the first dielectric material. Semiconductor devices and related methods are also disclosed. 1. An electronic device , comprising:an array of memory cells; and an active area comprising a central portion surrounded by a peripheral portion;', 'a first dielectric material overlying at least a portion of the peripheral portion of the active area;', 'a second dielectric material abutting portions of the first dielectric material and overlying the central portion of the active area, the second dielectric material substantially fully surrounded on all sides by the first dielectric material, and the second dielectric material having a threshold voltage magnitude that is lower than a threshold voltage magnitude of the first dielectric material; and', 'gates electrically connecting the active area of individual capacitors of the array of capacitors., 'at least one charge pump circuit comprising an array of capacitors, wherein each capacitor of the array comprises2. The electronic device of claim 1 , wherein the first dielectric material exhibiting a first resistance comprises a low-voltage oxide material and the second dielectric material exhibiting a second resistance comprises a super low-voltage oxide material claim 1 , the second resistance of the second dielectric material being relatively lower than the first resistance of the ...

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Номер записи: 35
07-03-2019 дата публикации

SEMICONDUCTOR DEVICE WITH AIRGAP SPACER FOR TRANSISTOR AND RELATED METHOD

Номер: US20190074364A1
Автор: ADUSUMILLI Siva P., Dillon Joshua F., Schutz Laura J., Stamper Anthony K.
Принадлежит:

A method may include forming a transistor on a substrate, the transistor including a gate, and forming a sacrificial spacer extending along an entirety of a thickness of the gate. A via layer is then formed over/about the gate. The sacrificial spacer is at least partially removed, leaving an air vent opening. An airgap spacer is formed in the dielectric layer by depositing another dielectric layer to close off the air vent opening. The airgap spacer is coincident with at least one sidewall of the gate and extends along an entirety of a thickness of the gate. Gate airgaps may also be provided over the gate. Other embodiments extend the gate and airgap spacer the full thickness of the dielectric layer thereabout. Other embodiments extend the airgap spacer over the gate. 1. A semiconductor device , comprising:a transistor on a substrate, the transistor including a gate body;a first dielectric layer about the gate body;an airgap spacer adjacent to at least one sidewall of the gate body in the first dielectric layer and extending along an entirety of a thickness of the gate body;an air vent passage contiguous with the airgap spacer and extending from the airgap spacer through the first dielectric layer to at least an upper surface of the first dielectric layer; anda second dielectric layer over the first dielectric layer, the second dielectric layer pinching off an upper end of the air vent passage.2. The semiconductor device of claim 1 , wherein the airgap spacer is devoid of any spacer material.3. The semiconductor device of claim 1 , further comprising a gate airgap positioned over the gate body in at least the first dielectric layer.4. The semiconductor device of claim 1 , wherein the airgap spacer also extends over an upper surface of the gate body.5. The semiconductor device of claim 4 , wherein the air vent passage forms a gate airgap positioned over the gate body in at least the first dielectric layer and is contiguous with the airgap spacer positioned over the ...

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Номер записи: 36
15-03-2018 дата публикации

CLOSED CELL LATERAL MOSFET USING SILICIDE SOURCE AND METHOD OF FORMING

Номер: US20180076319A1
Автор: Mallikarjunaswamy Shekar
Принадлежит:

A closed cell lateral MOSFET device includes minimally sized source/body contacts formed in source cells with silicided source and body diffusion regions formed therein. In this manner, the cell pitch of the cellular transistor array is kept small while the ruggedness of the transistor is ensured. In other embodiments, a closed cell lateral MOSFET device is formed using silicided source and body diffusion regions and self-aligned contacts or borderless contacts as the source/body contacts. The polysilicon gate mesh can be formed using minimum polysilicon-to-polysilicon spacing to minimize the cell pitch of the cellular transistor array. 1. A method for forming a closed cell lateral MOS transistor , comprising:providing a semiconductor layer of a first conductivity type forming the body of the transistor and being lightly doped;forming a conductive gate overlying and insulated from a top surface of the semiconductor layer by a gate dielectric layer, the conductive gate forming a mesh having a plurality of openings, the plurality of openings defining a cellular array of source cells and drain cells;forming sidewall spacers on sidewalls of the conductive gate;forming a plurality of diffusion regions of a second conductivity type, opposite the first conductivity type, in the semiconductor layer exposed by the openings in the mesh, the plurality of diffusion regions forming the cellular array of source cells and drain cells, wherein alternating rows of the diffusion regions form source regions and drain regions of the transistor, and the semiconductor layer under the conductive gate between the source regions and the drain regions forms the channel of the transistor;forming a body diffusion region of the first conductivity type in each of source cells in the cellular array of source and drain cells, the body diffusion region being more heavily doped than the semiconductor layer and being encircled by the source region in each of the source cell, wherein the body ...

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Номер записи: 37
22-03-2018 дата публикации

Super-Self-Aligned Contacts and Method for Making the Same

Номер: US20180083003A1
Автор: Smayling Michael C.
Принадлежит:

A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. A width of each second hard mask filament is set to define an active area contact-to-gate structure spacing. A first passage is etched between facing exposed side surfaces of a given pair of neighboring second hard mask filaments and through a depth of the semiconductor wafer to an active area. A second passage is etched through a given first hard mask portion and through a depth of the semiconductor wafer to a top surface of the underlying gate structure. An electrically conductive material is deposited within both the first and second passages to respectively form an active area contact and a gate contact. 1. A semiconductor device , comprising:a first linear gate structure;a second linear gate structure located next to the first linear gate structure, the second linear gate structure separated from the first linear gate structure by a gate pitch, the second linear gate structure forming a first PMOS transistor and a first NMOS transistor;a third linear gate structure located next to the second linear gate structure, the third linear gate structure separated from the second linear gate structure by the gate pitch, the third linear gate structure forming a second PMOS transistor and a second NMOS transistor;a fourth linear gate structure located next to the third linear gate structure, the fourth linear gate structure separated from the third linear gate structure by the gate pitch, the fourth linear gate structure forming a third PMOS transistor and a third NMOS transistor;a fifth linear gate structures located next to the fourth linear gate structure, the fifth linear gate structure separated from the fourth linear gate structure by the gate pitch;a first gate contact physically connected to the second ...

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Номер записи: 38
14-03-2019 дата публикации

METAL SILICIDE, METAL GERMANIDE, METHODS FOR MAKING THE SAME

Номер: US20190081149A1
Автор: Blomberg Tom E., Haukka Suvi P., Pore Viljami J., Tois Eva E.
Принадлежит:

In one aspect, methods of silicidation and germanidation are provided. In some embodiments, methods for forming metal silicide can include forming a non-oxide interface, such as germanium or solid antimony, over exposed silicon regions of a substrate. Metal oxide is formed over the interface layer. Annealing and reducing causes metal from the metal oxide to react with the underlying silicon and form metal silicide. Additionally, metal germanide can be formed by reduction of metal oxide over germanium, whether or not any underlying silicon is also silicided. In other embodiments, nickel is deposited directly and an interface layer is not used. In another aspect, methods of depositing nickel thin films by vapor phase deposition processes are provided. In some embodiments, nickel thin films are deposited by ALD. 1. (canceled)2. A method for depositing an elemental cobalt thin film , the method comprising:providing a substrate comprising an interface layer directly over a silicon surface; contacting the substrate with a first vapor phase metal precursor comprising cobalt;', 'removing excess first vapor phase metal precursor from the reaction space; and', 'contacting the substrate with a second vapor phase reactant such that it reacts with the first vapor phase metal precursor to form elemental Co on the interface layer., 'carrying out one or more deposition cycles at a growth temperature of less than about 400° C., the deposition cycle comprising3. The method of claim 2 , wherein the metal precursor is a metal compound in which the metal is bound or coordinated to oxygen claim 2 , nitrogen claim 2 , carbon or a combination thereof.4. The method of claim 2 , wherein the metal precursor is an organic compound.5. The method of claim 4 , wherein the metal precursor is a betadiketonate claim 4 , betadiketiminato compounds claim 4 , amidinate compounds claim 4 , aminoalkoxide claim 4 , ketoiminate or cyclopentadienyl compound.6. The method of claim 4 , wherein the metal ...

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Номер записи: 39
24-03-2016 дата публикации

Method of manufacturing semiconductor device and sputtering apparatus

Номер: US20160086779A1
Автор: Hideaki Tsugane, Hidenori Suzuki, Takashi HAMAYA
Принадлежит: Renesas Electronics Corp

Reliability of a semiconductor device is improved, and use efficiency of a sputtering apparatus is increased. When depositing thin films over a main surface of a semiconductor wafer using a magnetron sputtering apparatus in which a collimator is installed in a space between the semiconductor wafer and a target installed in a chamber, a region inner than a peripheral part of the collimator is made thinner than the peripheral part. Thus, it becomes possible to suppress deterioration in uniformity of the thin film in a wafer plane, which may occur as the integrated usage of the target increases.

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Номер записи: 40
24-03-2016 дата публикации

Dummy Gate for a High Voltage Transistor Device

Номер: US20160086859A1
Автор: LIN Han-Chung, Tsai Yung-Chih
Принадлежит:

The present disclosure provides a semiconductor device. The semiconductor device includes a first doped region and a second doped region both formed in a substrate. The first and second doped regions are oppositely doped. The semiconductor device includes a first gate formed over the substrate. The first gate overlies a portion of the first doped region and a portion of the second doped region. The semiconductor device includes a second gate formed over the substrate. The second gate overlies a different portion of the second doped region. The semiconductor device includes a first voltage source that provides a first voltage to the second gate. The semiconductor device includes a second voltage source that provides a second voltage to the second doped region. The first and second voltages are different from each other. 1. A method of fabricating a semiconductor device , comprising:forming a first well in a substrate, the first well having a first type of conductivity;forming a second well in the substrate, the second well having a second type of conductivity different from the first type;forming a first gate and a second gate over the substrate, the first gate being formed over a first portion of the first well and a first portion of the second well, the second gate being formed over a second portion of the second well and being separated from the first gate;forming a source region in a second portion of the first well; andforming a drain region in a third portion of the second well.2. The method of claim 1 , further comprising: forming silicided upper surfaces for the first gate and the second gate.3. The method of claim 1 , wherein the first and second gates each include a polysilicon gate electrode.4. The method of claim 1 , further comprising:forming a mask over a portion of the first gate and a portion of the second gate, the mask covering a fourth portion of the second well that is disposed between the first portion and the second portion of the second well; ...

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Номер записи: 41
02-04-2015 дата публикации

Super-Self-Aligned Contacts and Method for Making the Same

Номер: US20150091190A1
Автор: Smayling Michael C.
Принадлежит:

A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. A width of each second hard mask filament is set to define an active area contact-to-gate structure spacing. A first passage is etched between facing exposed side surfaces of a given pair of neighboring second hard mask filaments and through a depth of the semiconductor wafer to an active area. A second passage is etched through a given first hard mask portion and through a depth of the semiconductor wafer to a top surface of the underlying gate structure. An electrically conductive material is deposited within both the first and second passages to respectively form an active area contact and a gate contact. 1. A semiconductor device , comprising:a first linear gate structure having side surfaces oriented in a first direction and a top surface, wherein a width of the first linear gate structure is defined by a distance extending in a second direction perpendicular to the first direction between the side surfaces of the first linear gate structure, the first linear gate structure forming a gate electrode of at least one transistor;a second linear gate structure having side surfaces oriented in the first direction and a top surface, wherein a width of the second linear gate structure is defined by a distance extending in the second direction between the side surfaces of the second linear gate structure, the second linear gate structure forming a gate electrode of at least one transistor;a first gate contact in physical contact with the top surface of the first linear gate structure, the first gate contact formed to cover the width of the first linear gate structure without extending in the second direction substantially beyond either of the side surfaces of the first linear gate structure; anda second gate ...

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Номер записи: 42
19-06-2014 дата публикации

PARTIAL POLY AMORPHIZATION FOR CHANNELING PREVENTION

Номер: US20140167110A1
Автор: Braithwaite Glyn, Javorka Peter
Принадлежит: GLOBAL FOUNDRIES Inc.

Semiconductor devices are formed without zipper defects or channeling and through-implantation and with different silicide thicknesses in the gates and source/drain regions, Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region in the substrate on each side of the gate, forming a wet cap fill layer on the source/drain region on each side of the gate, removing the nitride cap from the gate, and forming an amorphized layer in a top portion of the gate. Embodiments include forming the amorphized layer by implanting low energy ions. 1. A device comprising:a substrate,a gate formed on the substrate, the gate comprising a polycrystalline silicon layer formed in a lower two thirds of the gate; anda source/drain region in the substrate on each side of the gate;a first silicide formed in an upper one third of the gate; anda second silicide on each source/drain region, wherein the first silicide has a thickness greater than the second silicide.2. The device according to claim 1 , wherein the upper one third of the gate comprises amorphized silicon.3. The device according to claim 1 , wherein a thickness of the polycrsytalline silicon layer is 300 Å to 500 Å.4. The device according to claim 1 , wherein the thickness of the first silicide is 20% to 30% greater than the thickness of the second silicide.5. The device according to claim 1 , further comprising halo/extension regions in the substrate on each side of the gate.6. The device according to claim 1 , further comprising spacers on each side of the gate.7. The device according to claim 1 , wherein the source/drain regions ions implanted in the substrate.8. The device according to claim 1 , wherein the source/drain regions comprise. embedded silicon germanium (eSiGe) source/drain regions in the substrate.9. A device comprising:a substrate,at least one gate formed on the substrate, the gate comprising a polycrystalline silicon layer having a thickness of 300 Å to ...

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Номер записи: 43
25-03-2021 дата публикации

THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A STRING SELECTION LINE GATE ELECTRODE HAVING A SILICIDE LAYER

Номер: US20210091093A1
Автор: AHN JONGSEON, HAN Jeehoon, KANAMORI Kohji, KANG SEOGOO
Принадлежит:

A three-dimensional memory device is provided. The three-dimensional memory device may include a substrate, a cell stack, a string selection line gate electrode, a lower vertical channel structure, an upper vertical channel structure, and a bit line. The string selection line gate electrode may include a lower string selection line gate electrode and an upper string selection line gate electrode formed on an upper surface of the lower string selection line gate electrode. The lower string selection line gate electrode may include N-doped poly-crystalline silicon. The upper string selection line gate electrode may include silicide. 1. A three-dimensional memory device , comprising:a substrate;a cell stack disposed on the substrate;a string selection line gate electrode disposed on the cell stack;a lower vertical channel structure vertically penetrating the cell stack;an upper vertical channel structure vertically penetrating the string selection line gate electrode and being connected to the lower vertical channel structure; anda bit line disposed on the upper vertical channel structure,wherein the string selection line gate electrode includes a lower string selection line gate electrode and an upper string selection line gate electrode formed on an upper surface of the lower string selection line gate electrode,the lower string selection line gate electrode includes N-doped poly-crystalline silicon, andthe upper string selection line gate electrode includes silicide.2. The device of claim 1 , whereinthe lower vertical channel structure includes:a lower gap-fill pattern;a lower channel layer surrounding a sidewall of the lower gap-fill pattern; anda memory layer surrounding a sidewall of the lower channel layer,the upper vertical channel structure includes:an upper gap-fill pattern;an upper channel layer surrounding a sidewall of the upper gap-fill pattern; andan insulating liner surrounding a sidewall of the upper channel layer, andthe upper vertical channel ...

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Номер записи: 44
25-03-2021 дата публикации

Memory First Process Flow and Device

Номер: US20210091198A1
Автор: Chang Kuo Tung, CHEN Chun, FANG Shenqing, HADDAD Sameer S., Kim Unsoon, Pak James, Ramsbey Mark T.
Принадлежит: CYPRESS SEMICONDUCTOR CORPORATION

A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed. 120-. (canceled)21. A semiconductor device , comprising:a channel formed in a substrate;a memory gate on a charge storage structure having a charge storage layer disposed over a first portion of the channel;a select gate on a gate dielectric on a surface of the substrate over a second portion of the channel; anda dielectric structure between the memory gate and the select gate, the dielectric structure comprising multiple layers including a first dielectric layer adjacent to a sidewall of the memory gate, a second dielectric layer adjacent a sidewall of the select gate, and a nitride dielectric layer between the first and second dielectric layers, wherein at least a portion of the dielectric structure is positioned between the charge storage structure and the gate dielectric.22. The semiconductor device of claim 21 , wherein the second dielectric layer comprises an L-shaped dielectric layer including a first portion on the nitride dielectric layer parallel to the sidewall of the memory gate and a second portion on the surface of the substrate over the second portion of the channel.23. The semiconductor device of claim 22 , wherein the gate dielectric comprises the second portion of ...

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Номер записи: 45
31-03-2016 дата публикации

Semiconductor device and method for forming the same

Номер: US20160093710A1
Автор: Young Doo JEONG
Принадлежит: SK hynix Inc

A semiconductor device includes a junction region on both sides of a trench in a semiconductor substrate, a first gate electrode with a first workfunction buried in the trench, and a second gate electrode formed of a polycide layer having a second workfunction overlapping with the junction region at an upper part of the first gate electrode.

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Номер записи: 46
21-03-2019 дата публикации

Semiconductor device and manufacturing method of semiconductor device

Номер: US20190088776A1
Автор: Hiroaki Katou, Kenya Kobayashi, Saya SHIMOMURA, Takahiro Kawano, Tetsuya Ohno, Toshifumi NISHIGUCHI
Принадлежит: Toshiba Corp, Toshiba Electronic Devices and Storage Corp

According to one embodiment, a semiconductor device comprising a drain layer, a base region, a source region, a field plate electrode, and a gate region. The drift layer is formed on the drain layer. The base region is formed on the drift layer. The source region is formed on the base region. The field plate electrode is formed inside a trench reaching the drift layer through the base region from the source region. The gate region is formed inside the trench, wherein the gate region has a U-shape including a recess on the gate region in a direction along the trench and is formed such that, on upper surfaces of respective both ends of the U-shape, a position of an inner end on a side of the recess is higher than a position of an outer end on a side of the second insulating film.

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Номер записи: 47
05-05-2022 дата публикации

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20220140102A1
Автор: Cheng Chao-Sheng, JHENG Pei-Lun
Принадлежит:

A method for manufacturing a semiconductor structure is provided. The method comprises the following steps. A first silicon-containing gate electrode is formed on a semiconductor substrate in a first region. A second silicon-containing gate electrode is formed on the semiconductor substrate in a second region. A gate silicide element is formed on an upper surface of the first silicon-containing gate electrode. A source silicide element and a drain silicide element are formed on the semiconductor substrate on opposing sides of the second silicon-containing gate electrode respectively. The gate silicide element, the source silicide element and the drain silicide element are formed simultaneously.

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Номер записи: 48
07-04-2016 дата публикации

Method for making an integrated circuit

Номер: US20160099326A1
Автор: Heimanu Niebojewski, Sebastien Barnola, Yves Morand
Принадлежит: Commissariat a lEnergie Atomique et aux Energies Alternatives CEA, STMicroelectronics Crolles 2 SAS, STMICROELECTRONICS SA

A method includes making a gate stack on the surface of an active zone, including depositing a first dielectric layer; depositing a gate conductive layer; depositing a first metal layer; depositing a second metal layer; depositing a second dielectric layer; partially etching the gate stack for the formation of a gate zone on the active zone; making insulating spacers on either side of the gate zone on the active zone; making source and drain electrodes zones; making silicidation zones on the surface of the source and drain zones; etching, in the gate zone on the active zone, the second dielectric layer and the second metal layer with stopping on the first metal layer, so as to form a cavity between the insulating spacers; making a protective plug at the surface of the first metal layer of the gate zone on the active zone, where the protective plug fills the cavity.

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Номер записи: 49
05-04-2018 дата публикации

Methods and Devices Using PVD Ruthenium

Номер: US20180096852A1
Автор: LEI JIANXIN, MARSHALL Ross, RAMALINGAM Jothilingam, TANG XIANMIN
Принадлежит:

Ruthenium containing gate stacks and methods of forming ruthenium containing gate stacks are described. The ruthenium containing gate stack comprises a polysilicon layer on a substrate; a silicide layer on the polysilicon layer; a barrier layer on the silicide layer; a ruthenium layer on the barrier layer; and a spacer layer comprising a nitride on sides of the ruthenium layer, wherein the ruthenium layer comprises substantially no ruthenium nitride after formation of the spacer layer. Forming the ruthenium layer comprises sputtering the ruthenium in a krypton environment on a high current electrostatic chuck comprising a high resistivity ceramic material. The sputtered ruthenium layer is annealed at a temperature greater than or equal to about 500° C. 1. A method of forming a gate stack , the method comprising:providing a plasma sputter chamber including a target comprising ruthenium and a pedestal for supporting a substrate to be sputter deposited in opposition to the target, the pedestal comprising a high current electrostatic chuck at a temperature greater than or equal to about 350° C.;flowing krypton into the chamber and exciting the krypton into a plasma to deposit a ruthenium layer on the substrate;providing an anneal chamber; andannealing the ruthenium layer on the substrate at a temperature greater than or equal to about 500° C.2. The method of claim 1 , wherein the electrostatic chuck is at a temperature in the range of about 450° C. to about 550° C.3. The method of claim 1 , wherein the electrostatic chuck comprises high resistivity ceramic.4. The method of claim 1 , wherein annealing the ruthenium layer occurs at a temperature of about 900° C. for about 30 seconds in a Nenvironment.5. The method of claim 1 , wherein annealing the ruthenium layer comprises heating the ruthenium layer to about 500° C. claim 1 , increasing the temperature to about 900° C. at a rate greater than or equal to about 50° C./sec claim 1 , holding the temperature for about 30 ...

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Номер записи: 50
28-03-2019 дата публикации

METHODS, APPARATUS AND SYSTEM FOR STRINGER DEFECT REDUCTION IN A TRENCH CUT REGION OF A FINFET DEVICE

Номер: US20190097015A1
Автор: Aquilino Michael, Basker Veeraraghavan, Gao Jinsheng, Huang Haigou, JAEGER Daniel, Nassar Christopher, Zang Hui
Принадлежит: GLOBALFOUDRIES INC.

At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height. 1. A method , comprising:forming a plurality of fins on a semiconductor substrate;forming, over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion;forming, over a second portion of the fins, a gate region;forming a trench in a portion of the gate region;forming a first oxide layer at a bottom region of the trench; anddepositing, prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material into the trench for forming a second oxide layer, the second oxide layer comprising the flowable oxide and the first oxide layer, the second oxide layer having a first height.2. The method of claim 1 , further comprising:performing the amorphous-silicon (a-Si) deposition process;performing a replacement metal gate (RMG) process in the gate region;performing a oxide chemical-mechanical polishing (CMP) process over the flowable oxide; andperforming an oxide recess process to remove the flowable oxide from gate region portions outside the trench.3. The method of claim 2 , wherein performing the oxide recess process comprises performing at least one of a dry reactive-ion etching (ME) claim 2 , or a wet etch ...

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Номер записи: 51
28-03-2019 дата публикации

RELIABLE GATE CONTACTS OVER ACTIVE AREAS

Номер: US20190097016A1
Автор: Alptekin Emre, Chu Albert M., Eastman Eric, Na Myung-Hee, Ramachandran Ravikumar
Принадлежит:

A method for manufacturing a semiconductor device comprises forming a plurality of fins in an active region, forming a plurality of gates around the plurality of fins in the active region, forming one or more gate contacts in the active region, and forming a plurality of contacts to source/drain regions in the active region. 1. A semiconductor device , comprising:a plurality of fins;a plurality of gates formed around the plurality of fins; and a number of the plurality of fins; and', 'one or more gate contacts., 'an active region comprising2. The semiconductor device according to claim 1 , wherein the active region further comprises:a plurality of contacts to source/drain regions, wherein one or more of the plurality of contacts extend over less than the number of the plurality of fins in the active region.3. The semiconductor device according to claim 2 , wherein the one or more of the plurality of contacts are positioned at a predetermined distance away from the one or more gate contacts.4. The semiconductor device according to claim 2 , wherein the plurality of contacts comprise trench silicide contacts.5. The semiconductor device according to claim 2 , wherein the one or more of the plurality of contacts are formed on respective epitaxial regions of less than the number of the plurality of fins in the active region.6. The semiconductor device according to claim 2 , wherein at least one fin of the number of the plurality of fins in the active region is electrically isolated from the one or more of the plurality of contacts.7. The semiconductor device according to claim 6 , further comprising:an epitaxial region extending from the at least one fin; anda dielectric layer on the epitaxial region.8. The semiconductor device according to claim 2 , wherein one or more spacers are respectively positioned on the one or more gate contacts between the one or more gate contacts and the one or more of the plurality of contacts.9. The semiconductor device according to claim 1 ...

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Номер записи: 52
28-03-2019 дата публикации

GATE STACKS

Номер: US20190097017A1
Автор: Blomiley Eric, HU Yushi, King Matthew J., McTeer Everett Allen, Meldrim John Mark
Принадлежит:

Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten silicide (WSix) material over the gate and the STIs, and a tungsten silicon nitride (WSiN) material on a top surface of the WSix material. Some embodiments disclose a gate stack having a gate between STIs, a first WSix material over the gate and the STIs, a WSiN interlayer material on a top surface of the first WSix material, and a second WSix material on a top surface of the WSiN interlayer material. Additional embodiments are disclosed. 1. A memory device comprising:a memory array; and a gate between shallow trench isolations (STIs) and directly contacting the STIs, a height he gate being different from a height of the STIs;', 'a tungsten silicide (WSix) material on a top surface of the gate and top surfaces of the STIs; and', 'a tungsten silicon nitride. (WSiN) material on a top surface of the WSix material., 'a peripheral transistor coupled to the memory array, the peripheral transistor comprising2. The memory device of claim 1 , wherein the memory device comprises a three dimensional (3D) NAND flash memory device claim 1 , a planar non-volatile memory device claim 1 , or a volatile memory device.3. The memory device of claim 1 , wherein the peripheral transistor further comprises a dielectric material over the WSiN material claim 1 , and wherein the dielectric material comprises tetraethyl orthosilicate (TEOS).4. The memory of claim 1 , wherein the peripheral transistor further comprises a channel under the gate claim 1 , and wherein the channel comprises silicon.5. The memory device of claim 4 , wherein the peripheral transistor further comprises a gate oxide between the gate and the channel.6. The memory device of claim 1 , wherein the STIs comprise silicon oxide claim 1 , and wherein the gate comprises a polysilicon (poly) material.7. A memory device comprising:a memory array; and a gate between shallow ...

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Номер записи: 53
13-04-2017 дата публикации

Contact Structure of Gate Structure

Номер: US20170103918A1
Автор: Audrey Hsiao-Chiu HSU, Fu-Kai Yang, Hsien-Cheng WANG, Hsin-Ying Lin, Mei-Yun Wang, Shih-Wen Liu
Принадлежит: RAKA Corp, Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate are etched to expose an underlying silicon substrate. A silicide portion defined by a contact profile is deposited in the exposed portion of the silicon substrate. A second sidewall layer substantially covers the first sidewall layer and at least partially covering the silicide portion is formed after depositing the silicide portion. A metal glue layer is deposited around the first metal gate and the second metal gate defining a trench above the silicide portion. A metal plug is deposited within the trench.

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Номер записи: 54
13-04-2017 дата публикации

SEMICONDUCTOR DEVICE INCLUDING GATE ELECTRODE FOR APPLYING TENSILE STRESS TO SILICON SUBSTRATE, AND METHOD OF MANUFACTURING THE SAME

Номер: US20170104099A1
Автор: Oda Hidekazu, Ohta Kazunobu, Sayama Hirokazu, Sugihara Kouhei
Принадлежит: RENESAS ELECTRONICS CORPORATION

A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced. 1. (canceled)2. A semiconductor device including a first region of a semiconductor substrate and a second region of the semiconductor substrate , comprising:a first gate insulating film of a first NMOS transistor formed over the first region;a first gate electrode of the first NMOS transistor formed over the first gate insulating film;a first source region and a first drain region of the first NMOS transistor formed in the first region;a first channel region of the first NMOS transistor formed in the first region, formed under the first gate electrode and formed between the first source region and the first drain region;a second gate insulating film of a second NMOS transistor formed over the second region;a second gate electrode of the second NMOS transistor formed over the second gate insulating film;a second source region and a second drain region of the second NMOS transistor formed in the second region;a second channel region of the second NMOS transistor formed in the second region, formed under the second gate electrode and formed between the second source region and the second drain region,wherein a mass ...

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Номер записи: 55
11-04-2019 дата публикации

RADIOFREQUENCY SWITCH DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20190109200A1
Автор: He Wanxun, Xing Su
Принадлежит:

A radiofrequency switch device includes an insulation layer, a semiconductor layer, a gate structure, a first doped region, a second doped region, an epitaxial layer, a first silicide layer, and a second silicide layer. The semiconductor layer is disposed on the insulation layer. The gate structure is disposed on the semiconductor layer. The first doped region and the second doped region are disposed in the semiconductor layer at two opposite sides of the gate structure respectively. The epitaxial layer is disposed on the first doped region. The first silicide layer is disposed on the epitaxial layer. The second silicide layer is disposed in the second doped region. 1. A radiofrequency (RF) switch device , comprising:an insulation layer;a semiconductor layer disposed on the insulation layer;a gate structure disposed on the semiconductor layer;a first doped region and a second doped region, wherein the first doped region and the second doped region are disposed in the semiconductor layer and disposed at two opposite sides of the gate structure respectively;an epitaxial layer disposed on the first doped region;a first silicide layer disposed on the epitaxial layer; anda second silicide layer disposed in the second doped region.2. The RF switch device according to claim 1 , wherein the first doped region is a source doped region claim 1 , and the second doped region is a drain doped region.3. The RF switch device according to claim 1 , wherein a top surface of the first silicide layer is higher than a top surface of the second silicide layer in a thickness direction of the insulation layer.4. The RF switch device according to claim 3 , wherein a bottom surface of the first silicide layer is higher than a top surface of the semiconductor layer in the thickness direction of the insulation layer.5. The RF switch device according to claim 1 , wherein a bottom surface of the first silicide layer is higher than a top surface of the second silicide layer in a thickness ...

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Номер записи: 56
02-04-2020 дата публикации

LDMOS DEVICE AND METHOD FOR MANUFACTURING SAME

Номер: US20200105927A1
Автор: XU Zhaozhao
Принадлежит: Shanghai Huahong Grace Semiconductor Manufacturing Corporation

LDMOS device including a drift region, a body region, a gate dielectric layer, a polysilicon gate, a source region, a drain region and a common dielectric layer, the common dielectric layer covers a portion, between a second side of the polysilicon gate and the drain region, of the surface of the drift region, extends onto the surface of the polysilicon gate and also covers part of the surface of the drain region, a self-aligned metal silicide is formed on portions, not covered by the common dielectric layer, of the surfaces of the polysilicon gate, the source region and the drain region, and the common dielectric layer serves as a growth barrier layer of the self-aligned metal silicide; a drain terminal field plate is formed on a portion of the surface of the common dielectric layer; and a portion of the common dielectric layer serves as a field plate dielectric layer. 1. A LDMOS device , comprising:a first epitaxial layer of a second conduction type, wherein a drift region of a first conduction type and a body region of a second conduction type are formed in selected areas of the first epitaxial layer, and the drift region horizontally makes contact with the body region or is spaced from the body region by a certain distance;a gate structure which is formed on a surface of the body region by stacking a gate dielectric layer and a polysilicon gate, wherein channels are formed on the surface, covered by the polysilicon gate, of the body region, and a second side of the gate dielectric layer and a second side of the polysilicon gate extend onto a surface of the drift region;a source region which is formed on the surface of the body region and has a second side self-aligned with a first side of the polysilicon gate;a drain region which is formed in a selected area of the drift region and has a first side spaced from the second side of the polysilicon gate by a certain distance; anda common dielectric layer, wherein the common dielectric layer covers a portion, between ...

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Номер записи: 57
28-04-2016 дата публикации

INTEGRATED CIRCUIT DEVICES WITH COUNTER-DOPED CONDUCTIVE GATES

Номер: US20160118469A1
Автор: CHEN WEIZE, DE SOUZA RICHARD J., Hoque Md M., PARRIS PATRICE M.
Принадлежит: Freescale Semiconductor, Inc.

Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a first well of a first conductivity type, a source of a second conductivity type, and a drain of the second conductivity type. A channel extends between the source and the drain. A conductive gate extends across the channel. The conductive gate includes a first gate region and a second gate region of the second conductivity type and a third gate region of the first conductivity type. The third gate region extends between the first and second gate regions. The devices further include a gate dielectric that extends between the conductive gate and the substrate and also include a silicide region in electrical communication with the first, second, and third gate regions. The methods include methods of manufacturing the devices. 1. An integrated circuit device , comprising:a semiconductor substrate having a substrate surface;a well of a first conductivity type extending from the substrate surface;a source of a second conductivity type, which is different from the first conductivity type, formed within the well and extending from the substrate surface;a drain of the second conductivity type formed within the well and extending from the substrate surface;a channel formed within the well, the channel extending along the substrate surface and electrically separating the source and the drain;a conductive gate extending across the substrate surface and along the channel between the source and the drain and comprising(i) a first gate region of the second conductivity type,(ii) a second gate region of the second conductivity type, and(iii) a third gate region of the first conductivity type, wherein the third gate region extends between the first gate region and the second gate region;a gate dielectric extending between and electrically isolating the conductive gate and the substrate surface; anda silicide region in ...

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Номер записи: 58
17-07-2014 дата публикации

Trench shielding structure for semiconductor device and method

Номер: US20140197483A1
Автор: Gordon M. Grivna, Peter A. Burke, Prasad Venkatraman
Принадлежит: Semiconductor Components Industries LLC

A shielding structure for a semiconductor device includes a plurality of trenches. The trenches include passivation liners and shield electrodes, which are formed therein. In one embodiment, the shielding structure is placed beneath a control pad. In another embodiment, the shielding structure is placed beneath a control runner.

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Номер записи: 59
17-07-2014 дата публикации

Semiconductor device

Номер: US20140197490A1
Автор: Kyoya Nitta
Принадлежит: Renesas Electronics Corp

A semiconductor device with improved characteristics is provided. The semiconductor device includes a LDMOS, a source plug electrically coupled to a source region of the LDMOS, a source wiring disposed over the source plug, a drain plug electrically coupled to a drain region of the LDMOS, and a drain wiring disposed over the drain plug. The structure of the source plug of the semiconductor device is devised. The semiconductor device is structured such that the drain plug is linearly disposed to extend in a direction Y, and the source plug includes a plurality of separated source plugs arranged at predetermined intervals in the direction Y. In this way, the separation of the source plug decreases an opposed area between the source plug and the drain plug, and can thus decrease the parasitic capacitance therebetween.

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Номер записи: 60
27-04-2017 дата публикации

Transistor structure with reduced parasitic "side wall" characteristics

Номер: US20170117370A1
Автор: Hubert Rothleitner
Принадлежит: INFINEON TECHNOLOGIES AG

A MOS transistor structure for matched operation in weak-inversion or sub-threshold range (e.g. input-pair of operational amplifier, comparator, and/or current-mirror) is disclosed. The transistor structure may include a well region of any impurity type in a substrate (SOI is included). The well-region can even be represented by the substrate itself. At least one transistor is located in the well region, whereby the active channel-region of the transistor is independent from lateral isolation interfaces between GOX (gate oxide) and FOX (field oxide; including STI-shallow trench isolation).

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Номер записи: 61
24-07-2014 дата публикации

Self-Aligned Trench MOSFET and Method of Manufacture

Номер: US20140206165A1
Автор: JIAN Li, Kuo-In Chen, Kyle Terril
Принадлежит: Vishay Siliconix Inc

A trench metal-oxide-semiconductor field effect transistor (MOSFET), in accordance with one embodiment, includes a drain region, a plurality of gate regions disposed above the drain region, a plurality of gate insulator regions each disposed about a periphery of a respective one of the plurality of gate regions, a plurality of source regions disposed in recessed mesas between the plurality of gate insulator regions, a plurality of body regions disposed in recessed mesas between the plurality of gate insulator regions and between the plurality of source regions and the drain region. The MOSFET also includes a plurality of body contact regions disposed in the each body region adjacent the plurality of source regions, a plurality of source/body contact spacers disposed between the plurality of gate insulator regions above the recessed mesas, a source/body contact disposed above the source/body contact spacers, and a plurality of source/body contact, plugs disposed between the source/body contact spacers and coupling the source/body contact to the plurality of body contact regions and the plurality of source regions.

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Номер записи: 62
04-05-2017 дата публикации

FLASH MEMORY AND FABRICATING METHOD THEREOF

Номер: US20170125431A1
Автор: Chen Liang, Chiu Shengfen
Принадлежит:

In some embodiments, a flash memory and a fabricating method thereof are provided. The method includes proving a substrate including multiple memory transistors and selecting transistors; forming a functional layer covering outer surfaces of the memory transistors and selecting transistors, and surfaces of the substrate between adjacent memory transistors and selecting transistors; performing a surface roughening treatment to the functional layer to provide a roughed surface of the functional layer that absorbs water; and forming a dielectric layer using a chemical vapor deposition (CVD) process, the absorbed water is evaporated from the functional layer during the CVD process to form an upward air flow that resists the deposition of the dielectric layer, such that air gaps are formed between adjacent memory transistors, and the dielectric layer covers top surfaces of the plurality of memory transistors and selecting transistors and fills gaps between each selecting transistor and corresponding adjacent memory transistor. 1. A method for fabricating a flash memory , comprising:proving a substrate including a memory cell region;forming a memory transistor array including a plurality of memory transistors, and a plurality of selecting transistors in the memory cell region, wherein each selecting transistor is used for selecting one column of memory transistors in the memory transistor array;forming a functional layer covering outer surfaces of the plurality of memory transistors and selecting transistors, as well as surfaces of the substrate between adjacent memory transistors and selecting transistors;performing a surface roughening treatment to the functional layer to provide a roughed surface of the functional layer that absorbs water;making the roughed surface of the functional layer to absorb water; andforming a dielectric layer using a chemical vapor deposition process on the functional layer, wherein the absorbed water is evaporated from the roughed surface of ...

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Номер записи: 63
25-04-2019 дата публикации

Silicide Block Isolation For Reducing Off-Capacitance of A Radio Frequency (RF) Switch

Номер: US20190123166A1
Автор: Kanawati Roda
Принадлежит:

A silicon-on-insulator (SOI) CMOS transistor structure includes a plurality of series-connected SOI CMOS transistors, including a plurality of parallel source/drain regions, a plurality of channel/body regions located between the plurality of source/drain regions, and a polysilicon gate structure located over the plurality of channel regions. The polysilicon gate structure includes a plurality of polysilicon gate fingers, wherein each polysilicon gate finger extends over a corresponding one of the channel/body regions. A silicide blocking structure is formed over portions of the polysilicon gate fingers, wherein channel/body contact regions, which extend at least partially under the silicide blocking structure, provide electrical connections to the parallel channel/body regions. 1. (canceled)2. (canceled)3. (canceled)4. (canceled)5. (canceled)6. (canceled)7. (canceled)8. (canceled)9. (canceled)10. (canceled)11. (canceled)12. (canceled)13. A method comprising:forming a plurality of polysilicon gate electrodes over an active region of a silicon-on-insulator structure;forming a plurality of source/drain regions having a first conductivity type in the active region, wherein a plurality of channel/body regions having a second conductivity type exist in the active region, wherein each of the plurality of channel/body regions is located under a corresponding one of the polysilicon gate electrodes, and wherein each of the plurality of channel/body regions is located between adjacent pairs of the plurality of source/drain regions;forming a first plurality of contact regions having the second conductivity type, wherein the first plurality of contact regions are continuous with first ends of the plurality of channel/body regions;forming a silicide blocking structure that covers first portions of the first plurality of contact regions, adjacent first portions of the source/drain regions, and first portions of each of the plurality of polysilicon gate electrodes; and thenforming ...

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Номер записи: 64
16-04-2020 дата публикации

INTEGRATED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20200118998A1
Автор: JANG Jae Hyung, JUNG In Sik, KIM Jun Hyun, KIM Kwang II, KIM Young Bae, SON Jin Yeong
Принадлежит: MAGNACHIP SEMICONDUCTOR, LTD.

A semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed in the first region and second region, respectively, wherein the first transistor includes a thick gate insulating layer and a thin buffer insulating layer formed in the substrate, a first gate electrode formed on the thick gate insulating layer, a first spacer formed on the thin buffer insulating layer, and a source region and a drain region formed in the substrate. 1. A semiconductor device , comprising:a deep trench isolation region and a deep well region formed in a substrate;a body region and a drift region formed in the deep well region;a source region and a drain region formed in the body region and the drift region, respectively;a gate insulating layer formed on the deep well region;a gate electrode formed on the gate insulating layer; anda spacer formed on a sidewall of the gate electrode, wherein the spacer is disposed adjacent to the source region,wherein the gate insulating layer has a first part, having a first thickness, disposed under the gate electrode and has a second part, having a second thickness less than the first thickness, disposed under the spacer.2. The semiconductor device of claim 1 , wherein the second thickness is 10% to 50% of the first thickness.3. The semiconductor device of claim 1 , wherein the source region overlaps with the second part of the gate insulating layer having the second thickness.4. The semiconductor device of claim 1 , further comprising:a first isolation region that overlaps with the gate electrode; anda second isolation region disposed between the drain region and the deep trench isolation region.5. The semiconductor device of claim 1 , wherein the deep trench isolation region comprises a first deep trench and a second deep trench claim 1 ,wherein the deep well region is formed between the first deep trench and the second deep trench and has a depth smaller than a depth of the ...

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Номер записи: 65
01-09-2022 дата публикации

Backside Vias in Semiconductor Device

Номер: US20220278213A1
Автор: Chuang Cheng-Chi, Huang Lin-Yu, Su Huan-Chieh, Wang Chih-hao, Yu Li-Zhen
Принадлежит:

Methods of forming backside vias connected to source/drain regions of long-channel semiconductor devices and short-channel semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a second transistor structure adjacent the first transistor structure; a first interconnect structure on a front-side of the first transistor structure and the second transistor structure; and a second interconnect structure on a backside of the first transistor structure and the second transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a second dielectric layer on the backside of the second transistor structure; a first contact extending through the first dielectric layer and electrically coupled to a first source/drain region of the first transistor structure; and a second contact extending through the second dielectric layer and electrically coupled to a second source/drain region of the second transistor structure, the second contact having a second length less than a first length of the first contact. 1. A method comprising:forming a first transistor structure on a semiconductor substrate and a second transistor structure on the semiconductor substrate adjacent the first transistor structure; andforming a first interconnect structure on a backside of the first transistor structure and the second transistor structure, wherein forming the first interconnect structure comprises:forming a first contact electrically coupled to a first source/drain region of the first transistor structure; andforming a second contact electrically coupled to a second source/drain region of the second transistor structure, the second contact having a second length less than a first length of the first contact, wherein a first surface of the first contact opposite the first source/drain region is coplanar with a ...

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Номер записи: 66
02-05-2019 дата публикации

EARLY GATE SILICIDATION IN TRANSISTOR ELEMENTS

Номер: US20190131133A1
Автор: Smith Elliot John
Принадлежит:

By decoupling the formation of a metal silicide in the gate electrode structure and the raised drain and source regions, superior flexibility in designing transistor elements and managing overall process flow may be achieved. To this end, the metal silicide in the gate electrode structures may be formed prior to actually patterning the gate electrode structures, while, also during this process sequence, a mask material may be applied for reliably covering any device regions in which a silicidation is not required. Consequently, superior gate conductivity may be accomplished, without increasing the risk of silicide penetration into the channel region of sophisticated fully depleted SOI transistors. 1. A method , comprising:forming a semiconductor-containing material layer above a semiconductor layer, said semiconductor-containing material layer having an upper surface;forming a patterned mask layer above said upper surface of said semiconductor-containing material layer, said patterned mask layer exposing a first part of said semiconductor-containing material layer while covering a second part of said semiconductor-containing material layer;with said patterned mask layer in position, converting at least a portion of said first part of said semiconductor-containing material layer into a first metal semiconductor compound;removing said patterned mask layer;forming a gate electrode structure that comprises said first metal semiconductor compound;forming drain and source regions adjacent to said gate electrode structure; andforming a second metal semiconductor compound in said drain and source regions.2. The method of claim 1 , wherein said second part of said semiconductor-containing material layer is substantially free of said first metal semiconductor compound.3. The method of claim 2 , further comprising forming a non-gate electrode structure that comprises at least a portion of said second part of said semiconductor-containing material layer.4. The method of claim 1 ...

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Номер записи: 67
02-05-2019 дата публикации

ELECTRODE STRUCTURE, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR DEVICE INCLUDING THE ELECTRODE STRUCTURE

Номер: US20190131301A1
Автор: KIM Bong-Hyun, KIM Joon, Lee Dong-kak, LIM Han-jin
Принадлежит:

An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer. 120-. (canceled)21. A dynamic random access memory (DRAM) device comprising:a semiconductor substrate; a first polysilicon layer formed on the semiconductor substrate and doped with resistance adjustment impurities, wherein an upper portion of the first polysilicon layer is further doped with carbon impurities for adjusting grain size of the upper portion of the first polysilicon layer;', 'a first ohmic metal layer formed on the first polysilicon layer;', 'a first barrier metal layer formed on the first ohmic metal layer; and', 'a first metal layer formed on the first barrier metal layer;, 'a first electrode structure and a second electrode structure formed on the semiconductor substrate respectively, each of the first and second electrode structures comprisingan impurity region formed on the semiconductor substrate and between the first electrode structure and the second electrode structure; anda direct contact (DC) pad electrode formed between the first electrode structure and the second electrode structure and contacting the impurity region,wherein the direct contact (DC) pad electrode comprises a second polysilicon layer formed on the semiconductor substrate whose upper portion is doped with carbon impurities and a second metal layer formed on the second polysilicon layer.22. The dynamic random access memory (DRAM) device of claim 21 , wherein each of the first and second electrode structures further include a first insulation layer between the first polysilicon layer and the semiconductor substrate.23. The dynamic ...

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Номер записи: 68
28-05-2015 дата публикации

TAPERED GATE ELECTRODE FOR SEMICONDUCTOR DEVICES

Номер: US20150144960A1
Автор: ARTHUR STEPHEN DALEY, Dudoff Gregory Keith, Kovalec Roger Raymond, Saia Richard Joseph, Stum Zachary Matthew
Принадлежит: GENERAL ELECTRIC COMPANY

The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.) In an embodiment, a semiconductor device includes a gate oxide layer disposed on top of a semiconductor layer. The semiconductor device also includes a gate electrode having a tapered sidewall. Further, the gate electrode includes a polysilicon layer disposed on top of the gate oxide layer and a metal silicide layer disposed on top of the polysilicon layer. 1. A silicon carbide (SiC) semiconductor device , comprising:a gate oxide layer disposed on top of a SiC semiconductor layer; anda gate electrode comprising a tapered sidewall, wherein the gate electrode comprises a polysilicon layer disposed on top of the gate oxide layer and a metal silicide layer disposed on top of the polysilicon layer.2. The semiconductor device of claim 1 , wherein at least a portion of the tapered sidewall of the gate electrode is disposed at an angle relative to a surface of the semiconductor device claim 1 , and wherein the angle is between approximately 65 degrees and approximately 85 degrees.3. The semiconductor device of claim 1 , comprising a rounded photoresist layer disposed on top of the gate electrode.4. The semiconductor device of claim 1 , wherein the metal silicide layer comprises one or more of tantalum silicide claim 1 , nickel silicide claim 1 , cobalt silicide claim 1 , titanium silicide claim 1 , molybdenum silicide claim 1 , tungsten silicide claim 1 , niobium silicide claim 1 , hafnium silicide claim 1 , zirconium silicide claim 1 , vanadium silicide claim 1 , chromium silicide claim 1 , or platinum silicide.5. The semiconductor device of claim 1 , wherein a width of the metal silicide layer is approximately equal to a top width of the polysilicon layer.6. The semiconductor device of claim 1 , wherein the metal silicide layer comprises tantalum silicide.7. The semiconductor device of claim 1 , wherein the ...

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Номер записи: 69
03-06-2021 дата публикации

Semiconductor device, and manufacturing method thereof

Номер: US20210167190A1
Автор: Guipeng Sun, Huajun JIN
Принадлежит: CSMC Technologies Fab2 Co Ltd

A semiconductor device, and a manufacturing method thereof. The method includes: providing a semiconductor substrate provided with a body region, a gate dielectric layer, and a field oxide layer, formed on the semiconductor substrate; forming a gate polycrystalline, the gate polycrystalline covering the gate dielectric layer and the field oxide layer and exposing at least one portion of the field oxide layer; forming a drift region in the semiconductor substrate by ion implantation using a drift region masking layer as a mask, removing the exposed portion of the field oxide layer by further using the drift region masking layer as the mask to form a first field oxide self-aligned with the gate polycrystalline; forming a source region in the body region, and forming a drain region in the drift region; forming a second field oxide on the semiconductor substrate; and forming a second field plate on the second field oxide.

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Номер записи: 70
18-05-2017 дата публикации

Memory First Process Flow and Device

Номер: US20170141201A1
Автор: Chang Kuo Tung, CHEN Chun, FANG Shenqing, HADDAD Sameer, Kim Unsoon, Pak James, RAMSBEY Mark
Принадлежит:

A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed. 1. A memory device , comprising:a substrate;a memory gate on a charge storage structure on the substrate;a select gate on a gate dielectric on the substrate, the select gate proximal to the memory gate; anda dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, the dielectric structure comprising multiple dielectric layers parallel to sidewalls of the memory gate and the select gate, the multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate,wherein the memory gate and the select gate are separated by a total thickness of the multiple dielectric layers.2. The memory device of wherein the dielectric structure further comprises a second dielectric layer adjacent the sidewall of the select gate.3. The memory device of wherein at least a portion of the dielectric structure extends between the charge storage structure and the gate dielectric.4. The memory device of wherein the charge storage structure comprises a nitride charge storage layer claim 2 ...

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Номер записи: 71
14-08-2014 дата публикации

Laterally difffused metal oxide semiconductor device and method of forming the same

Номер: US20140225191A1
Автор: Ashraf W. Lotfi, Jian Tian
Принадлежит: Enpirion Inc

A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide semiconductor device includes a source/drain having a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The laterally diffused metal oxide semiconductor device further includes an oppositely doped well located under and within the channel region, and a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region.

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Номер записи: 72
26-05-2016 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20160149025A1
Автор: Hiroshi Miki, Hirotaka Hamamura, Mieko Matsumura, Toshiyuki Mine, Yuki Mori
Принадлежит: HITACHI LTD

Provided is a technique of securing reliability of a gate insulating film, as much as in a Si power MOSFET, in a semiconductor device in which a semiconductor material having a larger band gap than silicon is used, and which is typified by, for example, an SiC power MOSFET. In order to achieve this object, in the in the SiC power MOSFET, the gate electrode GE is formed in contact with the gate insulating film GOX, and is formed of the polycrystalline silicon film PF 1 having the thickness equal to or smaller than 200 nm, and the polycrystalline silicon film PF 2 formed in contact with the polycrystalline silicon film PF 1, and having any thickness.

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Номер записи: 73
10-06-2021 дата публикации

MEMORY STRUCTURE

Номер: US20210175237A1
Автор: Chiu Ching-Kang, Chu Ying-Tsung, Ho Ching-Sung
Принадлежит: Powerchip Semiconductor Manufacturing Corporation

A memory structure including a substrate, a memory cell, and a transistor is provided. The substrate includes a memory cell region and a peripheral circuit region. The memory cell is located in the memory cell region. The transistor is located in the peripheral circuit region. The transistor includes a gate, a first doped region, a second doped region, a first nickel silicide layer, and a second nickel silicide layer. The gate is located on the substrate and is insulated from the substrate. The first doped region and the second doped region are located in the substrate on two sides of the gate. The first nickel silicide layer is located on an entire top surface of the first doped region, and the second nickel silicide layer is located on an entire top surface of the second doped region. 1. A memory structure , comprising:a substrate comprising a memory cell region and a peripheral circuit region; a buried conductive structure located in the substrate;', 'a first contact located on the substrate on one side of the buried conductive structure;', 'a conductive line coupled to the first contact;', 'a second contact located on the substrate on another side of the buried conductive structure; and', 'a metal silicide layer located on the second contact; and, 'a memory cell located in the memory cell region and comprising a gate located on the substrate and insulated from the substrate;', 'a first doped region and a second doped region located in the substrate on two sides of the gate;', 'a first nickel silicide layer located on an entire top surface of the first doped region; and', 'a second nickel silicide layer located on an entire top surface of the second doped region., 'a transistor located in the peripheral circuit region and comprising2. The memory structure according to claim 1 , wherein the gate of the transistor comprises:a doped polysilicon layer;a metal layer located on the doped polysilicon layer;a hard mask layer located on the metal layer; anda gate ...

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Номер записи: 74
04-06-2015 дата публикации

FLASH MEMORY STRUCTURE AND METHOD FOR FORMING THE SAME

Номер: US20150155394A1
Автор: LAI Chia-Ping, TSAI Chun-Tse
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a word line cell disposed over the substrate. The semiconductor device structure includes a substrate and a control gate formed over the substrate. The semiconductor device further includes an insulating layer formed on a sidewall of the control gate and a memory gate formed adjacent to the insulating layer. In addition, the insulating layer has a first height, and the memory gate has a second height shorter than the first height. 1. A semiconductor device structure , comprising:a substrate;a control gate formed over the substrate;an insulating layer formed on a sidewall of the control gate; anda memory gate formed adjacent to the insulating layer;wherein the insulating layer has a first height, and the memory gate has a second height shorter than the first height.2. The semiconductor device structure as claimed in claim 1 , wherein the insulating layer comprises a first oxide layer claim 1 , a nitride layer formed over the first oxide layer claim 1 , and a second oxide layer formed over the nitride layer.3. The semiconductor device structure as claimed in claim 1 , wherein an upper portion of the insulating layer is formed on the sidewall of the control gate without being covered by the memory gate.4. The semiconductor device structure as claimed in claim 3 , wherein the upper portion of the insulating layer has a length in a range from about 5 nm to about 150 nm.5. The semiconductor device structure as claimed in claim 1 , wherein a difference between the first height and the second height is in a range from about 5 nm to about 150 nm.6. The semiconductor device structure as claimed in claim 1 , wherein the control gate has a third height greater than the first height.7. The semiconductor device structure as claimed in claim 1 , wherein the control gate comprises a first silicide layer and the memory gate comprises a second ...

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Номер записи: 75
16-05-2019 дата публикации

Semiconductor devices and methods for fabricating the same

Номер: US20190148521A1
Автор: Dae Joung Kim, Gun Ho JO, Jae Jong HAN, Jae Mun Kim, Moon Han PARK, Tae Ho Cha
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method for fabricating a semiconductor device includes forming a fin type pattern protruding from a substrate and extending in a first direction, forming a field insulating layer covering a limited portion of the fin type pattern on the substrate such that the field insulating layer exposes a separate limited portion of the fin type pattern, forming a gate structure on the field insulating layer and the fin type pattern, the gate structure extending in a second direction, the second direction different from the first direction, forming a first barrier layer containing a nitrogen element in a first region of the field insulating layer, wherein the first region is exposed by the gate structure, adjacent to the gate structure and extending in the second direction and forming a gate spacer on the first barrier layer and on a side wall of the gate structure.

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Номер записи: 76
22-09-2022 дата публикации

MULTI-SILICIDE STRUCTURE FOR A SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING THE SAME

Номер: US20220302278A1
Автор: CHENG Chung-Liang
Принадлежит:

A semiconductor device includes a multi-silicide structure comprising at least two conformal silicide layers. The multi-silicide structure may include a first conformal silicide layer on a source/drain, a second conformal silicide layer on the first conformal silicide layer, and a capping layer over the second conformal silicide layer. The semiconductor device includes a contact structure on the multi-silicide structure. The semiconductor device includes a dielectric material around the contact structure. In some implementations, a controller may determine etch process parameters to be used by an etch tool to perform an iteration of an atomic layer etch (ALE) process on the semiconductor device. 1. A semiconductor device , comprising: a first conformal silicide layer on a source/drain,', 'a second conformal silicide layer on the first conformal silicide layer, and', 'a capping layer over the second conformal silicide layer;, 'a multi-silicide structure comprising at least two conformal silicide layers, the multi-silicide structure includinga contact structure on the multi-silicide structure; anda dielectric material around the contact structure.2. The semiconductor device of claim 1 , wherein a ratio of metal to silicon in the first conformal silicide layer is greater than 1.3. The semiconductor device of claim 1 , wherein a ratio of silicon to metal in the second conformal silicide layer is greater than 1.4. The semiconductor device of claim 1 , wherein a total thickness of the at least two conformal silicide layers of the multi-silicide structure is at least approximately 20 angstroms.5. The semiconductor device of claim 1 , wherein a thickness of each of the at least two conformal silicide layers of the multi-silicide structure is in a range from approximately 5 angstroms to approximately 10 angstroms.6. The semiconductor device of claim 1 , wherein the at least two conformal silicide layers of the multi-silicide structure comprise at least one of nickel silicide ...

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Номер записи: 77
14-05-2020 дата публикации

NON-VOLATILE MEMORY

Номер: US20200152646A1
Автор: Cheng Yu-Ming, FAN DER-TSYR, Huang I-Hsin
Принадлежит: IoTMemory Technology Inc.

A non-volatile memory having memory cells is provided. The memory cell includes a source region and a drain region, a select gate, a dummy select gate, a floating gate, an erase gate, and a control gate. The select gate is disposed on the substrate between the source region and the drain region. The floating gate is disposed on the substrate between the select gate and the source region, and a top portion of the floating gate has corners in symmetry. The height of the floating gate is lower than the height of the select gate. The erase gate is provided on the source region and covers the corner at the side of the source. The control gate is disposed on the erase gate and the floating gate. 1. A non-volatile memory , comprising: a source region and a drain region, respectively disposed in the substrate;', 'a select gate, disposed on the substrate between the source region and the drain region;', 'a dummy select gate, disposed on the substrate in the source region;', 'a floating gate, disposed on the substrate between the select gate and the dummy select gate, wherein a height of the floating gate is lower than a height of the select gate, and a top portion of the floating gate has two corners in symmetry;', 'an erase gate, disposed on the dummy select gate and covering the corners;', 'a control gate, disposed on the erase gate and the floating gate;', 'a tunneling dielectric layer, disposed between the floating gate and the substrate;', 'an erase gate dielectric layer, disposed between the erase gate and the floating gate;', 'a select gate dielectric layer, disposed between the select gate and the substrate;', 'an insulating layer, disposed between the select gate and the floating gate; and', 'an inter-gate dielectric layer, disposed between the control gate and the floating gate and between the control gate and the erase gate., 'a first memory cell, disposed on a substrate and comprising2. The non-volatile memory as claimed in claim 1 , further comprising:a second ...

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Номер записи: 78
24-06-2021 дата публикации

SEMICONDUCTOR DEVICE HAVING IMPROVED ELECTROSTATIC DISCHARGE PROTECTION

Номер: US20210193643A1
Автор: Chu Chen-Liang, HSU SHENG-FU, KUNG TA-YUAN, Tsai Chih-Chung
Принадлежит:

Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions. 1. A semiconductor device , comprising:a source region in a substrate;a drain region in the substrate and laterally spaced from the source region; and the drain region comprises two or more first doped regions having a first doping type in the substrate;', 'the drain region comprises one or more second doped regions in the substrate;', 'the first doped regions have a greater concentration of first doping type dopants than the second doped regions; and', 'each of the second doped regions is disposed laterally between two neighboring first doped regions., 'a gate stack over the substrate and between the source region and the drain region, wherein2. The semiconductor device of claim 1 , wherein:the drain region comprises a first number of the first doped regions;the drain region comprises a second number of the second doped regions;the first number is any integer greater than or equal to two; andthe second number is an integer that is equal to the first number minus one.3. The semiconductor device of claim 1 , wherein the second doped regions have the first doping type.4. The semiconductor device of claim 1 , wherein the second doped regions have a second doping type different than the first doping type.5. The semiconductor device of claim 1 , wherein one of the first doped regions is ...

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Номер записи: 79
16-06-2016 дата публикации

High- voltage semiconductor device and method for manufacturing the same

Номер: US20160172490A1
Автор: Chu-Feng CHEN, Chung-Ren Lao, Hsing-Chao Liu, Wei-Chun CHOU
Принадлежит: Vanguard International Semiconductor Corp

The present disclosure provides a high-voltage semiconductor device, including: a substrate; an epitaxial layer disposed over the substrate and having a first conductive type; a gate structure disposed over the epitaxial layer; a source region and a drain region disposed in the epitaxial layer at opposite sides of the gate structure respectively; and a stack structure disposed between the gate structure and the drain region, wherein the stack structure includes: a blocking layer; an insulating layer disposed over the blocking layer; and a conductive layer disposed over the insulating layer and electrically connected the source region or the gate structure. The present disclosure also provides a method for manufacturing the high-voltage semiconductor device.

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Номер записи: 80
11-09-2014 дата публикации

Method of fabricating semiconductor device and device fabricated thereby

Номер: US20140252444A1
Автор: Bongtae Park, Hyeong Park, Jang-Hyun You, Jeehoon HAN
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes a plurality of lines disposed on a semiconductor substrate, and remaining line patterns disposed spaced apart from the lines on extensions from the lines. The lines include first end-portions adjacent to the remaining line patterns. The remaining line patterns include second end-portions adjacent to the lines. The first end-portions and second end-portions are formed to have mirror symmetry with respect to each other.

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Номер записи: 81
21-05-2020 дата публикации

SYSTEMS AND METHODS FOR IN-SITU DOPED SEMICONDUCTOR GATE ELECTRODES FOR WIDE BANDGAP SEMICONDUCTOR POWER DEVICES

Номер: US20200161442A1
Автор: Gorczyca Thomas Bert
Принадлежит:

In an embodiment, a wide bandgap semiconductor power device, includes a wide bandgap semiconductor substrate layer; an epitaxial semiconductor layer disposed above the wide bandgap semiconductor substrate layer; a gate dielectric layer disposed directly over a portion of the epitaxial semiconductor layer; and a gate electrode disposed directly over the gate dielectric layer. The gate electrode includes an in-situ doped semiconductor layer disposed directly over the gate dielectric layer and a metal-containing layer disposed directly over the in-situ doped semiconductor layer. 1. A wide bandgap semiconductor power device , comprising:a wide bandgap semiconductor substrate layer;an epitaxial semiconductor layer disposed above the wide bandgap semiconductor substrate layer;a gate dielectric layer disposed directly over a portion of the epitaxial semiconductor layer; and an in-situ doped semiconductor layer disposed directly over the gate dielectric layer; and', 'a metal-containing layer disposed directly over the in-situ doped semiconductor layer., 'a gate electrode disposed directly over the gate dielectric layer, wherein the gate electrode comprises2. The wide bandgap semiconductor power device of claim 1 , wherein a doping concentration of a portion of the in-situ doped semiconductor layer that is disposed nearest the gate dielectric layer is less than or equal to a doping concentration of other regions of the in-situ doped semiconductor layer of the gate electrode.3. The wide bandgap semiconductor power device of claim 1 , wherein the gate electrode comprises polycrystalline silicon.4. The wide bandgap semiconductor power device of claim 3 , wherein the gate electrode comprises low-pressure chemical vapor deposition (LPCVD) polysilicon.5. The wide bandgap semiconductor power device of claim 1 , wherein the wide bandgap semiconductor substrate and the epitaxial semiconductor layer comprise silicon carbide.6. The wide bandgap semiconductor power device of claim 1 , ...

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Номер записи: 82
21-05-2020 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20200161450A1
Автор: HUANG CHUN-SHUN
Принадлежит:

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a gate electrode, a drain region, a source region, an isolating layer, a plurality of metal contacts, a plurality of conductive plugs, and a contact liner. The gate electrode is disposed on the substrate. The drain region and the source region are disposed in the substrate and on opposite sides of the gate electrode. The isolating layer is disposed over the substrate and the gate electrode. The metal contacts are disposed in the gate electrode, the source region, and the drain region. The conductive plugs are disposed in the isolating layer and electrically coupled to the metal contacts. The contact liner surrounds the conductive plugs. The present disclosure further provides a method for manufacturing the semiconductor device. 1. A semiconductor device , comprising:a substrate;a gate electrode disposed on the substrate;a drain region and a source region disposed in the substrate and on opposite sides of the gate electrode;an isolating layer disposed over the substrate and the gate electrode;a plurality of metal contacts disposed in the gate electrode, the source region, and the drain region;a plurality of conductive plugs disposed in the isolating layer and electrically coupled to the metal contacts; anda contact liner surrounding the conductive plugs.2. The semiconductor device of claim 1 , further comprising a barrier layer disposed between the conductive plugs and the contact liner.3. The semiconductor device of claim 1 , wherein the isolating layer comprises:an underlying dielectric layer disposed on the substrate and surrounding the gate electrode; andan overlying dielectric layer disposed over the underlying dielectric layer and the gate electrode.4. The semiconductor device of claim 3 , wherein a top surface of one of the plurality of metal contacts in the gate electrode is coplanar with an upper surface of the underlying dielectric layer claim 3 , and top ...

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Номер записи: 83
21-06-2018 дата публикации

Source-Gate Region Architecture in a Vertical Power Semiconductor Device

Номер: US20180174968A1
Автор: Thomas E. Harrington, III
Принадлежит: D3 Semiconductor LLC

A vertical drift metal-oxide-semiconductor (VDMOS) transistor with improved contact to source and body regions, and a method of fabricating the same. A masked ion implant of the source regions into opposite-type body regions defines the locations of body contact regions, which are implanted subsequently with a blanket implant. The surface of the source regions and body contact regions are silicide clad, and an overlying insulator layer deposited and planarized. Contact openings are formed through the planarized insulator layer, within which conductive plugs are formed to contact the metal silicide, and thus the source and body regions of the device. A metal conductor is formed overall to the desired thickness, and contacts the conductive plugs to provide bias to the source and body regions.

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Номер записи: 84
02-07-2015 дата публикации

METHOD OF FORMING SILICON LAYER, AND METHOD OF MANUFACTURING FLASH MEMORY

Номер: US20150187578A1
Автор: Jhang Pei-Ci, Shieh Jung-Yu
Принадлежит: MACRONIX INTERNATIONAL CO., LTD.

A method of manufacturing a flash memory is provided. In the method, a hydrogen treatment is performed on a substrate, on which a polysilicon gate and a plurality of spacers on sidewalls of the polysilicon gate are formed. A silicon thin film is deposited on the polysilicon gate to extend a top area thereof. The hydrogen treatment and the deposition of the silicon thin film are accomplished repeatedly, and then a cobalt layer is deposited on the silicon thin film. A portion of the cobalt layer is converted to a CoSilayer, and the unreacted cobalt layer is then removed. 1. A method of manufacturing a flash memory , comprising:performing a hydrogen treatment on a substrate, on which a polysilicon gate and a plurality of spacers on sidewalls of the polysilicon gate are formed;performing LPCVD to deposit a silicon thin film on the polysilicon gate to extend a top area of the polysilicon gate, wherein a deposition selectivity of the silicon thin film on the polysilicon gate is higher than that on the plurality of spacers;repeating the steps of performing the hydrogen treatment and depositing the silicon thin film at least one time;depositing a cobalt layer on the silicon thin film;{'sub': 'x', 'converting a portion of the cobalt layer to a CoSilayer; and'}removing the unreacted cobalt layer.2. The method of claim 1 , wherein a material of the spacers comprises silicon oxide.3. The method of claim 1 , further comprising pre-cleaning the polysilicon gate before the step of performing the hydrogen treatment.4. The method of claim 1 , wherein a time of the hydrogen treatment is 30-60 seconds.5. The method of claim 1 , wherein a temperature range of the hydrogen treatment is 300-500° C.6. The method of claim 1 , wherein a power of the hydrogen treatment is higher than 100 W.7. The method of claim 1 , wherein a deposition time of depositing the silicon thin film is 90-150 seconds.8. The method of claim 1 , wherein a deposition temperature of depositing the silicon thin film is ...

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Номер записи: 85
08-07-2021 дата публикации

SEMICONDUCTOR DEVICE WITH A PROGRAMMABLE CONTACT AND METHOD FOR FABRICATING THE SAME

Номер: US20210210611A1
Автор: HUANG CHIN-LING
Принадлежит:

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a gate stack positioned on the substrate, a plurality of programmable contacts positioned on the gate stack, a pair of heavily-doped regions positioned adjacent to two sides of the gate stack and in the substrate, and a plurality of first contacts positioned on the pair of heavily-doped regions. A width of the plurality of programmable contacts is less than a width of the plurality of first contacts. 1. A semiconductor device , comprising:a substrate;a gate stack positioned on the substrate;a plurality of contacts positioned on the gate stack;a pair of heavily-doped regions positioned adjacent to two sides of the gate stack and in the substrate;a plurality of first contacts positioned on the pair of heavily-doped regions; anda pair of lightly-doped regions positioned adjacent to the pair of heavily-doped regions and in the substrate;wherein a width of the plurality of contacts is less than a width of the plurality of first contacts.2. The semiconductor device of claim 1 , wherein the gate stack comprises a gate insulating layer positioned on the substrate claim 1 , a gate bottom conductive layer positioned on the gate insulating layer claim 1 , and a gate top conductive layer positioned on the gate bottom conductive layer.3. The semiconductor device of claim 2 , further comprising a pair of first spacers attached to sidewalls of the gate insulating layer and sidewalls of the gate bottom conductive layer.4. The semiconductor device of claim 3 , wherein the gate insulating layer has a thickness between about 0.5 nm and about 5.0 nm claim 3 , and the gate insulating layer is formed of silicon oxide claim 3 , silicon nitride claim 3 , silicon oxynitride claim 3 , or silicon nitride oxide.5. The semiconductor device of claim 4 , wherein the gate bottom conductive layer has a thickness between about 50 nm and about ...

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Номер записи: 86
08-07-2021 дата публикации

SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME

Номер: US20210210638A1
Автор: HUANG Chung-Hsun, Huang Sheng-Fu
Принадлежит: NANYA TECHNOLOGY CORPORATION

A semiconductor structure and a method of forming the same are provided. In the semiconductor structure, contact spacers are formed at least on sidewalls of contact trenches in the substrate, so that the distance between the gate and the silicide layers disposed only on the bottom surfaces, rather than on the sidewalls and the bottom surfaces, of the contact trenches can be increased, and thus the current leakage induced by gate can be decreased. 1. A method of forming a semiconductor , the method comprising:forming a gate structure on a substrate;forming a source and a drain in the substrate on two sides of the gate structure;forming a dielectric layer on the substrate and the gate structure;forming two contact openings in the dielectric layer to respectively expose the source and the drain;forming two contact trenches in the source and drain and under the two contact openings, respectively;forming two contact spacers to respectively cover sidewalls of the contact trenches for avoiding current leakage induced by gate;forming two silicide layers under the bottom surface of the contact trenches; andforming two contact plugs to fill the contact trenches and the contact openings.2. The method of claim 1 , wherein the step of forming the contact spacers comprises:forming contact dielectric layers respectively on surfaces of the contact trenches by thermal oxidation or thermal nitridation; andanisotropically etching the contact dielectric layers to form the contact spacers on the sidewalls of the contact trenches and expose the substrate.3. The method of claim 1 , wherein the step of forming the contact spacers comprises:forming a contact dielectric layer conformally covering exposed surfaces of the dielectric layer, the contact openings and the contact trenches; andanisotropically etching the contact dielectric layer to form the contact spacers on the sidewalls of the contact openings and the contact trenches and expose the substrate.4. The method of claim 3 , wherein ...

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Номер записи: 87
30-06-2016 дата публикации

DEVICE AND METHODS FOR HIGH-K AND METAL GATE SLACKS

Номер: US20160190018A1
Автор: Chen Po-Nien, CHUANG Harry-Hak-Lay, Ng Jin-Aun, Young Bao-Ru, ZHU Ming
Принадлежит:

A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region. 1. A semiconductor device , comprising:a semiconductor substrate;isolation features to separate different regions on the substrate;a p-type field-effect transistor (pFET) core region having a first gate stack on the substrate, the first gate stack including an interfacial layer, a high k (HK) dielectric layer on the interfacial layer, and a capping layer of a first material on the HK dielectric layer;an input/output pFET (pFET IO) region having a second gate stack on the substrate, the second gate stack including a dielectric layer, an interfacial layer on the dielectric layer, a HK dielectric layer on the interfacial layer, and a capping layer of the first material on the HK dielectric layer;an n-type field-effect transistor (nFET) core region having a third gate stack on the substrate, the third gate stack including an interfacial layer, a capping layer of a second material on the interfacial layer, and a HK dielectric layer on the capping layer of the second material;an input/output nFET (nFET IO) region having a fourth gate stack on the substrate, the fourth gate stack including a dielectric layer, an interfacial layer on the dielectric layer, a capping layer of the second material on the interfacial layer, and a HK dielectric layer on the capping layer of the second material; anda high-resistor region having a fifth gate stack on the substrate, the fifth gate stack including an interfacial layer, a capping layer of the second material on the interfacial layer, and a HK ...

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Номер записи: 88
28-06-2018 дата публикации

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Номер: US20180182768A1
Автор: MIHARA Tatsuyoshi
Принадлежит:

After a dummy control gate electrode and a memory gate electrode are formed and an interlayer insulating film is formed so as to cover the gate electrodes, the interlayer insulating film is polished to expose the dummy control gate electrode and the memory gate electrode. Thereafter, the dummy control gate electrode is removed by etching, and then a control gate electrode is formed in a trench which is a region from which the dummy control gate electrode has been removed. The dummy control gate electrode is made of a non-doped or n type silicon film, and the memory gate electrode is made of a p type silicon film. In the process of removing the dummy control gate electrode, the dummy control gate electrode is removed by performing etching under the condition that the memory gate electrode is less likely to be etched compared with the dummy control gate electrode, in the state where the dummy control gate electrode and the memory gate electrode are exposed. 1. A manufacturing method of a semiconductor device having a memory cell of a non-volatile memory , the method comprising:(a) a step of preparing a semiconductor substrate;(b) a step of forming a dummy gate electrode on the semiconductor substrate via a first insulating film;(c) a step of forming a first gate electrode for the memory cell on the semiconductor substrate via a second insulating film having a charge accumulating portion therein so as to be adjacent to the dummy gate electrode;(d) a step of forming a first interlayer insulating film so as to cover the dummy gate electrode and the first gate electrode;(e) a step of polishing the first interlayer insulating film to expose the dummy gate electrode and the first gate electrode;(f) a step of removing the dummy gate electrode by etching after the step (e); and(g) a step of forming a second gate electrode for the memory cell in a first trench which is a region from which the dummy gate electrode has been removed in the step (f),wherein the dummy gate ...

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Номер записи: 89
09-07-2015 дата публикации

Shielded gate trench mos with improved source pickup layout

Номер: US20150194522A1
Автор: Gary Chen, Hong Chang, John Chen, Jongoh Kim, Limin Weng, Wenjun Li, YI Su
Принадлежит: ALPHA AND OMEGA SEMICONDUCTOR INC

A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.

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Номер записи: 90
11-06-2020 дата публикации

MICROELECTRONIC STRUCTURES INCLUDING CAPACITOR STRUTURES AND METHODS OF FORMING MICROELECTRONIC STRUCTURES

Номер: US20200185544A1
Автор: Smith Michael A.
Принадлежит:

A semiconductor structure includes a capacitor structure comprising an active region comprising opposing field edges parallel to a first horizontal direction and a gate region comprising opposing gate edges parallel to a second horizontal direction transverse to the first horizontal direction. The semiconductor structure also comprises a first dielectric material adjacent at least one of the opposing field edges or the opposing gate edges and a second dielectric material adjacent the active area and abutting portions of the first dielectric material. A height of the second dielectric material in a vertical direction may be less than the height of the first dielectric material. Semiconductor devices and related methods are also disclosed. 1. A microelectronic device , comprising:at least one capacitor structure comprising an active region comprising a central region surrounded by a peripheral region, the active region comprising opposing field edges parallel to a first horizontal direction;a gate region comprising opposing gate edges parallel to a second horizontal direction transverse to the first horizontal direction;a first dielectric material overlying at least a portion of the peripheral region of the active region and adjacent at least one of the opposing field edges or the opposing gate edges; anda second dielectric material overlying the central region of the active region and abutting portions of the first dielectric material, each of the first dielectric material and the second dielectric material having a height in a vertical direction transverse to the first horizontal direction and the second horizontal direction, wherein the height of the second dielectric material is less than the height of the first dielectric material.2. The microelectronic device of claim 1 , further comprising contacts located adjacent to at least two peripheral edges of the active region claim 1 , the contacts being located external to at least one of the opposing field edges or ...

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Номер записи: 91
20-07-2017 дата публикации

Method of fabricating semiconductor device

Номер: US20170207127A1
Автор: Chih-Chung Wang, Kuan-Chuan Chen, Nien-Chung Li, Shin-Hung Li, Wen-Fang Lee
Принадлежит: United Microelectronics Corp

A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a first gate and a second gate. The first gate is disposed on the substrate and includes a first gate insulating layer, a polysilicon layer, a silicide layer and a protective layer stacked with each other on the substrate and a first spacer surrounds the first gate insulating layer, the polysilicon layer, the silicide layer and the protective layer. The second gate is disposed on the substrate and includes a second gate insulating layer, a work function metal layer and a conductive layer stacked with each other on the substrate, and a second spacer surrounds the second gate insulating layer, the work function metal layer and the conductive layer.

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Номер записи: 92
26-07-2018 дата публикации

DEVICES AND METHODS FOR A POWER TRANSISTOR HAVING A SCHOTTKY OR SCHOTTKY-LIKE CONTACT

Номер: US20180212041A1
Автор: DOLNY Gary M., JR. William R., MILANOWSKI Randall, Richards
Принадлежит: Silicet, LLC

Devices, structures, and methods thereof for providing a Schottky or Schottky-like contact as a source region and/or a drain region of a power transistor are disclosed. A power transistor structure comprises a substrate of a first dopant polarity, a drift region formed on or within the substrate, a body region formed on or within the drift region, a gate structure formed on or within the substrate, a source region adjacent to the gate structure, a drain region formed adjacent to the gate structure. At least one of the source region and the drain region is formed from a Schottky or Schottky-like contact substantially near a surface of the substrate, comprising a silicide layer and an interfacial dopant segregation layer. The Schottky or Schottky-like contact is formed by low-temperature annealing a dopant segregation implant in the source and/or drain region. 1. A power transistor structure comprising:a substrate of a first dopant polarity including a conducting layer;a drift region formed directly adjacent to, indirectly adjacent to, within, or both directly adjacent to and within the substrate;a body region formed directly adjacent to, indirectly adjacent to, within, or both directly adjacent to and within the drift region;a gate structure formed directly adjacent to, indirectly adjacent to, within, or both directly adjacent to and within the substrate;a source region adjacent to the gate structure;a drain region formed directly adjacent to, indirectly adjacent to, within, or both directly adjacent to and within the drift region;wherein the source region and/or the drain region is formed from a Schottky or Schottky-like contact substantially near a surface of the substrate to reduce or eliminate snapback of the power transistor structure; andwherein the Schottky or Schottky-like contact is a rectifying barrier junction between the substrate and the conducting layer.2. The power transistor structure of claim 1 , further comprising non-continuous p+ body contacts ...

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Номер записи: 93
03-08-2017 дата публикации

Semiconductor Device and Method for Manufacturing Thereof

Номер: US20170221707A1
Автор: ENDO Yuta, NODA Kosei, Sato Yuichi
Принадлежит: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

A transistor that is formed using an oxide semiconductor film is provided. A transistor that is formed using an oxide semiconductor film with reduced oxygen vacancies is provided. A transistor having excellent electrical characteristics is provided. A semiconductor device includes a first insulating film, a first oxide semiconductor film, a gate insulating film, and a gate electrode. The first insulating film includes a first region and a second region. The first region is a region that transmits less oxygen than the second region does. The first oxide semiconductor film is provided at least over the second region. 1. A semiconductor device comprising:a first oxide semiconductor film over a substrate;a second oxide semiconductor film over the first oxide semiconductor film;a third oxide semiconductor film over the second oxide semiconductor film;a gate insulating film over the third oxide semiconductor film;a gate electrode over the gate insulating film; anda source electrode and a drain electrode,wherein the third oxide semiconductor film is not overlapped with the source electrode or the drain electrode.2. The semiconductor device according to claim 1 , wherein a side surface of the third oxide semiconductor film is aligned with a side surface of the gate insulating film.3. The semiconductor device according to claim 1 , wherein a side surface of the first oxide semiconductor film is aligned with a side surface of the second oxide semiconductor film.4. The semiconductor device according to claim 1 , further comprising a base insulating film under the first oxide semiconductor film.5. The semiconductor device according to claim 4 , wherein the base insulating film contains phosphorus or boron.6. A semiconductor device comprising:a first oxide semiconductor film over a substrate;a second oxide semiconductor film over the first oxide semiconductor film;a third oxide semiconductor film over the second oxide semiconductor film;a gate insulating film over the third ...

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Номер записи: 94
12-08-2021 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20210249314A1
Автор: Kawai Tohru, MIZUKAMI Yuta
Принадлежит:

A semiconductor device includes a semiconductor substrate, an insulating layer, a semiconductor layers and a silicide layer. The insulating layer is formed on the semiconductor substrate. The semiconductor layer is formed on the insulating layer and includes a polycrystalline silicon. The silicide layer is formed on the semiconductor layer. The semiconductor layer has a first semiconductor part and a second semiconductor part. The first semiconductor part includes a first semiconductor region of a first conductivity type, and a second semiconductor region of a second conductivity type. The second semiconductor part is adjacent the second semiconductor region. In a width direction of the first semiconductor part, a second length of the second semiconductor part is greater than a first length of the first semiconductor part. A distance between the first and second semiconductor regions is 100 nm or more in an extension direction in which the first semiconductor region extends. 1. A semiconductor device comprising:a semiconductor substrate;an insulating layer formed on a main surface of the semiconductor substrate;a semiconductor layer formed on the insulating layer, the semiconductor layer including a polycrystalline silicon; anda silicide layer formed on an upper surface of the semiconductor layer, a first semiconductor part including a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type different from the first conductivity type; and', 'a second semiconductor part of the second conductivity type, the second semiconductor part adjacent the second semiconductor region,, 'wherein the semiconductor layer includeswherein the first semiconductor part has a first length in a width direction of the first semiconductor part,wherein, in the width direction, the second semiconductor part has a second length greater than the first length, andwherein a distance between the first semiconductor region and the ...

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Номер записи: 95
02-07-2020 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Номер: US20200212176A1
Автор: Iijima Takeshi, KOSHIMIZU Makoto, NIWAYAMA Hideki, SOEDA Hiroki, TACHIGAMI Atsushi, UMEZU Kazuyuki
Принадлежит: RENESAS ELECTRONICS CORPORATION

A terrace insulating film (SL) to be overridden by a gate electrode (G) of an nLDMOS device is configured by LOCOS, and a device isolation portion (SS) is configured by STI. Furthermore, on an outermost periphery of an active region where a plurality of nLDMOS devices are formed, a guard ring having the same potential as that of a drain region (D) is provided. And, via this guard ring, the device isolation portion (SS) is formed in a periphery of the active region, thereby not connecting but isolating the terrace insulating film (SL) and the device isolation portion (SS) from each other. 1. A semiconductor device comprising:a semiconductor substrate of a first conductivity type; a back-gate region;', 'a source region surrounding the back-gate region in plan view; and', 'a drain region formed surrounding the source region in plan view;, 'a semiconductor layer formed on the semiconductor substrate and including an active region, the active region includinga first device isolation portion formed in the semiconductor layer, the first device isolation portion surrounding the active region of the semiconductor layer in plan view;a terrace insulating film formed between the source region and the drain region and formed on the semiconductor layer;a gate insulating film formed on the semiconductor layer;a gate electrode formed on the gate insulating film, partially formed on the terrace insulating film, and surrounding the source region in plan view;an interlayer insulating film formed on the semiconductor layer so as to cover the gate electrode;a first plug formed in the interlayer insulating film and formed on a first portion of the source region; anda second plug formed in the interlayer insulating film and formed on a second portion of the source region,wherein a thickness of the terrace insulating film is smaller than a thickness of the device isolation portion, andwherein, in cross-section view, the back-gate region is located between the first portion of the source ...

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Номер записи: 96
20-08-2015 дата публикации

NOVEL LATCH-UP IMMUNITY NLDMOS

Номер: US20150236006A1
Автор: LAI Da-Wei
Принадлежит:

An improved nLDMOS ESD protection device having an increased holding voltage is disclosed. Embodiments include: providing in a substrate a DVNW region; providing a HVPW region in the DVNW region; providing bulk and source regions in the HVPW region; providing a drain region in the DVNW region, separate from the HVPW region; and providing a polysilicon gate over a portion of the HVPW region and the DVNW region. 1. A device comprising:a substrate;a dual voltage n-well (DVNW) region in the substrate;a high voltage p-well (HVPW) region in the DVNW region;bulk and source regions in the HVPW region;a drain region in the DVNW region, separate from the HVPW region;a polysilicon gate over a portion of the HVPW region and the DVNW region;an n-well (NW) region in the DVNW region in the drain region; andan n-well (NW) region in the DVNW region in the drain region.2. The device according to claim 1 , further comprising:the device having no high voltage n-type double diffusion drain (HVNDDD) region.3. The device according to claim 1 , comprising:a silicided block layer on the first N+ region, a portion of the polysilicon gate, and the DVNW region therebetween.4. The device according to claim 1 , comprising:second and third N+ regions in the HVPW region; anda first P+ region separating the second and third N+ regions.5. The device according to claim 4 , wherein the second and third N+ regions and polysilicon gate being coupled to a ground rail.6. The device according to claim 5 , wherein the first N+ region is coupled to an I/O pad.7. The device according to claim 6 , further comprising:a second P+ region in the substrate, separate from the DVNW region, the second P+ region being coupled to the ground rail.8. A device claim 6 , comprising:a p-type substrate;a first P+ region in the p-type substrate;a dual voltage n-well (DVNW) region in the p-type substrate, separate from the first P+ region;a first N+ region in the DVNW region;a first shallow trench isolation (STI) layer ...

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Номер записи: 97
20-08-2015 дата публикации

Semiconductor device and operating method thereof

Номер: US20150236150A1
Автор: Chin-Sheng Yang, Chorng-Lih Young, Horng-Nan Chern, Ming-Hui Chang, Ming-Shing Chen, Wei-Ting Wu, Ying-Chou Lai
Принадлежит: United Microelectronics Corp

Provided is a semiconductor device including a P-type substrate, a P-type first well region, an N-type second well region, a gate, N-type source and drain regions, a dummy gate and an N-type deep well region. The first well region is in the substrate. The second well region is in the substrate proximate to the first well region. The gate is on the substrate and covers a portion of the first well region and a portion of the second well region. The source region is in the first well region at one side of the gate. The drain region is in the second well region at another side of the gate. The dummy gate is on the substrate between the gate and the drain region. The deep well region is in the substrate and surrounds the first and second well regions. An operation method of the semiconductor device is further provided.

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Номер записи: 98
09-08-2018 дата публикации

TUNABLE BREAKDOWN VOLTAGE RF FET DEVICES

Номер: US20180226477A1
Автор: Jain Vibhor, Liu Qizhi, PEKARIK JOHN J.
Принадлежит:

A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions. 1. A structure comprising:a gate dielectric material on a substrate;first, second and third silicide regions directly on the substrate and abutting the gate dielectric material, the first silicide region and the second silicide region each have a sidewall;a first sidewall spacer and a second sidewall spacer both on the gate dielectric material, the first sidewall spacer and the second sidewall spacer each comprising a side surface, with the side surface of the first silicide region being vertically aligned with the side surface of the first sidewall spacer, and the side surface of the second silicide region being vertically aligned with the side surface of the second sidewall spacer;a source region adjacent to the first silicide region;a drain region adjacent to the second silicide region and spaced apart from the source region; andcontacts to the first silicide region, the second silicide region, the third silicide region, and the source and drain regions.2. The structure of claim 1 , wherein the third silicide region is between the first sidewall spacer and a ...

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Номер записи: 99
10-08-2017 дата публикации

SEMICONDUCTOR STRUCTURE WITH RESIST PROTECTIVE OXIDE ON ISOLATION STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Номер: US20170229343A1
Автор: Chen Jui-Long, CHEN Po-An, HUANG Yi-Lii, LEE Kuo-Hsi, LIANG Chia-Yao, LIAO Chen-Liang, LIN Sheng-Yuan
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A method of forming a semiconductor structure includes; (i) forming an isolation structure in a semiconductor substrate, the isolation structure electrically isolating device regions of the semiconductor substrate; (ii) forming a gate structure extending from one of the device regions to the isolation structure; (iii) forming a resist protective oxide layer overlaying the gate structure and the isolation structure; and (iv) patterning the resist protective oxide layer to form a patterned resist protective oxide that covers at least a portion of the isolation structure and a portion of the gate structure on the isolation structure. 1. A method of forming a semiconductor structure , comprising:forming an isolation structure in a semiconductor substrate, the isolation structure electrically isolating device regions of the semiconductor substrate;forming a gate structure extending from one of the device regions to the isolation structure;forming a resist protective oxide layer overlaying the gate structure and the isolation structure; andpatterning the resist protective oxide layer to form a patterned resist protective oxide that covers at least a portion of the isolation structure and a portion of the gate structure on the isolation structure.2. The method according to claim 1 , wherein the isolation structure comprises a shallow trench isolation structure.3. The method according to claim 1 , wherein the gate structure has a first portion located on the isolation structure and a second portion extending from the first portion into one of the device regions.4. The method according to claim 3 , wherein the patterned resist protective oxide covers the first portion of the gate structure claim 3 , and the second portion of the gate structure is free from the patterned resist protective oxide.5. The method according to claim 1 , wherein the operation of forming the gate structure comprises:forming a gate stack comprising a high-k dielectric and a polycrystalline silicon ...

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