Obere Elektrodensperrschicht für RRAM

Verschiedene Ausführungsformen der vorliegenden Anmeldung richten sich an eine resistive Direktzugriffsspeicherzelle (RRAM-Zelle), die eine obere Elektrodensperrschicht aufweist, welche zum Blockieren der Bewegung von Stickstoff oder einem anderen geeigneten nichtmetallischen Element von einer oberen Elektrode der RRAM-Zelle zu einer aktiven Metallschicht der RRAM-Zelle konfiguriert ist. Blockieren der Bewegung des nichtmetallischen Elements kann die Ausbildung einer unerwünschten Schaltschicht zwischen der aktiven Metallschicht und der oberen Elektrode verhindern. Die unerwünschte Schaltschicht würde parasitären Widerstand der RRAM-Zelle erhöhen, sodass die obere Elektrodensperrschicht parasitären Widerstand durch Verhindern der Ausbildung der unerwünschten Schaltschicht verhindern kann.

Integrated circuit for memory module of e.g. portable computer, has resistance switching rods electrically connected with pair of electrodes and embedded partly in thermal check matrix with material having high electrical resistance

The circuit has a switching element (10) for switching between two states with different electrical resistances. A set of resistance switching rods (18a-18d) is electrically connected with a pair of electrodes (12, 20) and is embedded partly in a thermal check matrix. The thermal check matrix has a material with a high specific electrical resistance and a low dielectric constant. The thermal check matrix includes an exposable material and polyimide. The resistance switching rod exhibits a length ranging between 10 and 100 nanometers. Independent claims are also included for the following: (1) a memory component with a memory cell (2) a method for production of a resistance switching element.

Integrierte Schaltkreise; Verfahren zum Herstellen eines integrierten Schaltkreises und Speichermodul

Ausführungsformen der vorliegenden Erfindung betreffen im Allgemeinen integrierte Schaltkreise, Verfahren zum Herstellen eines integrierten Schaltkreises und ein Speichermodul. In einer Ausführungsform der Erfindung wird ein integrierter Schaltkreis mit einer programmierbaren Anordnung bereitgestellt. Die programmierbare Anordnung weist auf: ein Substrat, mindestens eine erste Elektrode, die in oder über dem Substrat angeordnet ist, Ionenleiter-Dotier-Material, das über der mindestens einen ersten Elektrode angeordnet ist, Ionenleiter-Material, das über dem Ionenleiter-Dotier-Material angeordnet ist, und mindestens eine zweite Elektrode, die über dem Ionenleiter-Material angeordnet ist.

Halbleiterwiderstandsspeicherbauelement und Herstellungsverfahren

Halbleiterwiderstandsspeicherbauelement mit einem Substrat (1) mit einer Oberseite, Wortleitungsstegen (5), die parallel im Abstand zueinander auf der Oberseite angeordnet sind, Bitleitungen (BLi), die im Abstand zueinander quer zu den Wortleitungen (WLk) angeordnet sind, Source-/Drain-Bereichen, die als dotierte Bereiche jeweils benachbart zu einem Wortleitungssteg (5) und zu einem Zwischenraum zwischen Wortleitungsstegen (5) ausgebildet sind, Aussparungen (13) des Substrates (1), die in jedem zweiten Zwischenraum zwischen den Wortleitungsstegen (5) gebildet sind, wobei die benachbart zu einem betreffenden Zwischenraum angeordneten Source-/Drain-Bereiche jeweils an eine Seitenwand der betreffenden Aussparung (13) angrenzen und die Bitleitungen (BLi) Anteile aufweisen, die in den Aussparungen (13) angeordnet sind, Widerstandsschichten (17), die an den Seitenwänden der Aussparungen (13) jeweils zwischen einem Source-/Drain-Bereich und einem Anteil einer Bitleitung (BLi) angeordnet und aus ...

THRESHOLS SWITCH

... 1411604 Glass compositions for glass-metal seals STANDARD TELEPHONES & CABLES Ltd 6 Dec 1973 [14 Dec 1972] 57671/72 Heading C1M [Also in Division H1] The subject-matter of this Specification is substantially the same as that of Specification 1,361,487, but titanium dioxide is used instead of cupric oxide as a constituent of the glass.

Procedure for the production of a voltage-controlled semiconductor switch

Porous SIO

THRESHOLD SWITCHING DEVICE

THRESHOLD SWITCHING DEVICE This invention relates to a method of forming a threshold switching device which exhibits negative differential resistance and to the devices formed thereby. The method comprises depositing a silicon dioxide film derived from hydrogen silsesqulioxane resin between at least two electrodes and then applying a voltage above a threshold voltage across the electrodes.

COMPOSITE MEMORY MATERIAL COMPRISING A MIXTURE OF PHASE-CHANGE MEMORY MATERIAL AND DIELECTRIC MATERIAL

A composite memory material (36) comprising a mixture of active phase-change memory material and inactive dielectric material. The phase-change material includes one or more elements selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, As, S, Si, P, O and mixtures of alloys thereof. A single cell memory element (30) comprising the aforementioned composite memory material (36), and a pair of spacedly disposed contacts (6, 8).

Sperrschichtfreies Halbleiterbauelement für Schaltzwecke

Three-demensional semiconductor memory devices having double-intersection array and methods of fabricating the same

Nonvolatile storage element and method for manufacturing nonvolatile storage element

Provided is a nonvolatile storage element with which deterioration of the oxygen concentration profile of a variable resistance layer due to the thermal budget can be suppressed, and which is capable of stable operation at a low voltage; also provided is a method for manufacturing the same. The nonvolatile storage element (12) is equipped with a first electrode layer (105) formed on a substrate (100), a variable resistance layer (106) arranged on the first electrode layer (105), and a second electrode layer (107) arranged on the variable resistance layer (106). The variable resistance layer (106) has a two layer structure formed by stacking an oxygen-nitrogen-deficient tantalum oxynitride layer (106a) and a tantalum oxide layer (106b).

Memristor based on Schottky junction modulation and preparation method thereof

Non-volatile memory and method for manufacturing same

3D RESISTIVE MEMORY

유-무기 하이브리드 페로브스카이트를 저항변화층으로 구비하는 저항변화 메모리 소자 및 그의 제조방법

... 저항 변화 메모리 소자 및 그의 제조방법을 제공한다. 상기 저항 변화 메모리 소자는 제1 전극과 제2 전극을 구비한다. 상기 제1 전극과 상기 제2 전극 사이에 위치하는 페로브스카이트 결정구조를 갖는 유기 금속 할라이드를 구비하는 저항 변화층이 배치된다.

상변화 메모리 디바이스들에서의 재료들 및 컴포넌트들

... 상변화 재료와, 그것과의 옴 접촉을 형성하는 전극을 가지는 상변화 메모리 셀들, 구조체들, 및 디바이스들이 개시되고 설명된다. 이러한 전극들은 10에서 100 mOhmㆍcm까지의 비저항을 가질 수 있다.

MEMORY CELL

MEMRISTIVE JUNCTION WITH INTRINSIC RECTIFIER

... 멤리스티브 접합(400)은 제 1 전극(102) 및 제 2 전극(104)을 포함할 수 있고, 멤리스티브 영역(106)이 이들 사이에 위치된다. 멤리스티브 영역은 이 전극 사이에 인가된 스위칭 전압(118)을 통해 두 가지 활성화 상태 사이를 스위칭하도록 구성된다. 활성화 상태는 제 1 전극과 제 2 전극 사이에서 판독 전압의 인가에 의해 확인될 수 있다. 접합은 제 1 전극과 멤리스티브 영역 사이 인터페이스(420)에 위치된 정류기 영역을 더 포함하며, 스위칭 전압에서 실질적으로 전도성이고 판독 전압에서 실질적으로 저항성인 온도 반응성 전이 재료의 레이어(402)를 포함한다.

RESISTIVE MEMORY DEVICE AND A METHOD FOR MANUFACTURING THE SAME, CAPABLE OF MAKING A RESET PROCESS MORE UNIFORMLY

PURPOSE: A resistive memory device and a method for manufacturing the same are provided to improve the endurance of a resistivity memory device by preventing the occurrence of a set stuck phenomenon when a memory device is operated. CONSTITUTION: A bottom electrode(13) is formed on a substrate(10). A resistance layer(14) is formed on the bottom electrode. An upper electrode(16) is formed on the resistance layer. An oxygen diffusion prevention pattern(15b) is included in the interface of the upper electrode and the resistance layer. The oxygen diffusion prevention pattern is made from a thin film. Multiple oxygen diffusion prevention patterns are separated from each other. COPYRIGHT KIPO 2010 ...

ELECTRICALLY ACTUATED DEVICE AND METHOD OF CONTROLLING THE FORMATION OF DOPANTS THEREIN

HIGH-RELIABILITY HIGH-SPEED MEMRISTOR

Non-linear selection device and method of fabricating the same, and non-volatile memory device the same

ATOMIC LAYER DEPOSITION OF METAL OXIDE MATERIALS FOR MEMORY APPLICATIONS

MEMRISTIVE JUNCTION WITH INTRINSIC RECTIFIER

MEMORY CELL WITH RESISTANCE- SWITCHING LAYERS AND LATERAL ARRANGEMENT

Reduced diffusion in metal electrode for two-terminal memory

Providing for two-terminal memory that mitigates diffusion of external material therein is described herein. In some embodiments, a two-terminal memory cell can comprise an electrode layer. The electrode layer can be at least in part permeable to ionically or chemically reactive material, such as oxygen or the like. The two-terminal memory can further comprise a diffusion mitigation material disposed between the electrode layer and external material. This diffusion mitigation material can be selected to mitigate or prevent diffusion of the undesired element(s) or compound(s), to mitigate or avoid exposure of such element(s) or compound(s) to the electrode layer. Accordingly, degradation of the two-terminal memory as a result of contact with the undesired element(s) or compound(s) can be mitigated by various disclosed embodiments.

Dual oxide analog switch for neuromorphic switching

Exemplary semiconductor structures for neuromorphic applications may include a first layer overlying a substrate material. The first layer may be or include a first oxide material. The structures may include a second layer disposed adjacent the first layer. The second layer may be or include a second oxide material. The structures may also include an electrode material deposited overlying the second layer.

Resistive memory with a thermally insulating region

Rram structure and method of making the same

REWRITEABLE MEMORY CELL COMPRISING A TRANSISTOR AND RESISTANCE-SWITCHING MATERIAL IN SERIES

A nonvolatile memory cell is provided, the cell comprising a transistor in series with resistance- switching material, which can be switched between at least two stable resistance states, for example a high-resistance state and a low-resistance state. In preferred embodiments the transistor is a TFT, having a channel region not formed in a monocrystalline wafer substrate. In preferred embodiments the transistor may have' either a vertically oriented ch'annel or a laterally oriented channel. Either embodiment can be formed in a monolithic three dimensional memory array in which multiple memory levels can be formed above a single substrate, forming a highly dense nonvolatile memory array.

NONVOLATILE RESISTANCE CHANGE ELEMENT

According to one embodiment, a nonvolatile resistance change element includes a first electrode, a second electrode and a first layer. The first electrode includes a metal element. The second electrode includes an n type semiconductor. The first layer is formed between the first electrode and the second electrode and includes a semiconductor element. The first layer includes a conductor portion made of the metal element. The conductor portion and the second electrode are spaced apart.

NON-VOLATILE STORAGE DEVICE AND MANUFACTURING METHOD THEREFOR

A resistance-changing layer (103) has a first resistance-changing layer (103a) including an oxygen-deficient first metal oxide and a second resistance-changing layer (103b) including an oxygen-deficient second metal oxide different from the first metal oxide. The second resistance-changing layer (103b) includes a non-metallic element (A) other than oxygen. When the composition of the first resistance-changing layer (103a) is represented by MOx, and the composition of the second resistance-changing layer (103b) is represented by NOyAz, the equation x < (y+z) is satisfied, the resistivity of the second resistance-changing layer (103b) is greater than the resistivity of the first resistance-changing layer (103a), and the film density of the second resistance-changing layer (103b) is less than the theoretical film density of the stoichiometric composition of the second metal oxide.

METHOD TO FORM A REWRITEABLE MEMORY CELL COMPRISING A DIODE AND A RESISTIVITY-SWITCHING GROWN OXIDE

A method is described to form a rewriteable memory cell including a diode and an oxide layer, wherein the resistivity of the oxide layer can be reversibly switched. In preferred embodiments, the oxide layer is a grown oxide. The diode is preferably formed of polysilicon which has been crystallized in contact with a silicide which has a close lattice match to silicon. The silicide provides a crystallization template such that the polysilicon is large- grained with few defects, and thus relatively low- resistivity. In preferred embodiments, a monolithic three dimensional memory array can be formed, in which multiple memory levels of such rewriteable memory cells are monolithically formed vertically stacked above a substrate.

GCIB-TREATED RESISTIVE DEVICE

The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a lower electrode, and forming an oxide material on the lower electrode. The oxide material is exposed to a gas cluster ion beam (GCIB) until a change in resistance of a first portion of the oxide material relative to the resistance of a second portion of the oxide material. An upper electrode is formed on the first portion.

NON-VOLATILE MEMORY AND METHOD FOR MANUFACTURING SAME

A non-volatile memory comprising a first substrate (100) and a second substrate (110) is disclosed. The first substrate (100) comprises a plurality of switching devices (4) arranged as a matrix and a plurality of first electrodes (18) electrically connected to the respective switching devices (4). The second substrate (110) comprises a conductive film (32) and a recording layer (34) whose resistance is changed by applying an electric pulse. The first electrodes (18) are integrally covered with the recording layer (34), so that the recording layer (34) is held between the first electrodes (18) and the conductive film (32). The first substrate (100) further comprises a second electrode (22) which is electrically connected to the conductive film (32) and held at a certain voltage when current is passed through the recording layer (34). With this non-volatile memory, high integration can be realized at low cost.

MEMORY ARRAY WITH GRADED MEMORY STACK RESISTANCES

Methods, systems, and devices for memory arrays having graded memory stack resistances are described. An apparatus may include a first subset of memory stacks having a first resistance based on a physical and/or electrical distance of the first subset of memory stacks from at least one of a first driver component or a second driver component. The apparatus may include a second subset of memory stacks having a second resistance that is less than the first resistance based on a physical and/or electrical distance of the second subset of memory from at least one of the first driver component or the second driver component.

ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME

Implementations of the disclosed technology provide an electronic device including a semiconductor memory and a method for fabricating the same, in which processes are easily performed and the characteristics of a variable resistance element are improved. An electronic device according to an implementation of the disclosed technology is an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a substrate; a conductive contact plug formed over the first conductive layer and including a stack of a conductive low-resistance structure and a conductive planarizing layer; and a variable resistance pattern coupled to the contact plug, wherein the low-resistance structure comprises a diffusion barrier layer, a low-resistance material layer and a gap-fill layer.

MEMORY CELLS INCLUDING VERTICALLY ORIENTED ADJUSTABLE RESISTANCE STRUCTURES

A memory cell is provided that includes a vertically-oriented adjustable resistance material layer, a control terminal disposed adjacent the vertically-oriented adjustable resistance material layer and coupled to a word line, and a reversible resistance-switching element disposed on the vertically-oriented adjustable resistance material layer. The control terminal is configured to adjust a resistance of the vertically-oriented adjustable resistance material layer.

Forming and training processes for resistance-change memory cell

During the manufacture of a set of non-volatile resistance-switching memory elements, a forming process is performed in which a voltage is applied over forming period until a conductive filament is formed in a resistance-switching layer. A heat source at a temperature of 50° C. to 150° C. is applied to expedite the forming process while reducing the required magnitude of the applied voltage. Manufacturing time and reliability are improved. After the forming process, an expedited training process can be performed in which a fixed number of cycles of voltage pulses are applied without verifying the memory elements. Subsequently, the memory elements are verified by determining their read current in an evaluation. Another fixed number of cycles of voltage pulses is applied without verifying the memory elements, if the memory elements do not pass the evaluation.

Electronic memory device

An electronic device includes a first electrode, a second electrode, and a solid electrolyte made of an ion-conducting material, the first and second electrodes being configured to form a metal dendrite. The device further includes a third electrode, an interface layer contacting the third electrode and a third surface of the electrolyte, the interface layer being an ionic insulator and an electronic insulator. The third electrode and the dendrite are arranged such that the device has two resistive states.

PHASE-CHANGE TaN RESISTOR BASED TRIPLE-STATE/MULTI-STATE READ ONLY MEMORY

The present invention relates to a nonvolatile memory such as, for example a ROM or an EPROM, in which the information density of the memory is increased relative to a conventional nonvolatile memory that includes two logic state devices. Specifically, the nonvolatile memory of the present invention includes a SiN/TaN/SiN thin film resistor embedded within a material having a thermal conductivity of about 1 W/m-K or less; and a non-linear Si-containing device coupled to the resistor. Read and write circuits and operations are also provided in the present application.

GLASS SHOWING ELECTRICAL SWITCHING PHENOMENA

Nonvolatile memory device and method for manufacturing same

According to one embodiment, a nonvolatile memory device includes a first wiring layer. The device includes a second wiring layer intersecting with the first wiring layer. And the device includes a first memory layer provided at a position where the first wiring layer and the second wiring layer intersect. And the first memory layer contacts with the first wiring layer, and the first wiring layer is a layer which is capable of supplying a metal ion to the first memory layer.

NON-VOLATILE MEMORY DEVICE

According to an embodiment, a non-volatile memory device includes a first conductive layer, a second conductive layer, and a resistance change layer provided between the first conductive layer and the second conductive layer. The resistance change layer is capable of making a transition between a low-resistance state and a high-resistance state, and includes an oxide containing at least one of hafnium (Hf) and zirconium (Zr), at least one selected from the group consisting of barium (Ba), lanthanum (La), gadolinium (Gd) and lutetium (Lu), and nitrogen (N). 1. A non-volatile memory device comprising:a first conductive layer;a second conductive layer; anda resistance change layer provided between the first conductive layer and the second conductive layer, the resistance change layer being capable of making a transition between a low-resistance state and a high-resistance state, and including an oxide containing at least one of hafnium (Hf) and zirconium (Zr), at least one selected from the group consisting of barium (Ba), lanthanum (La), gadolinium (Gd) and lutetium (Lu), and nitrogen (N).2. The device according to claim 1 , wherein the oxide includes a metal site containing one of Hf claim 1 , Zr claim 1 , Ba claim 1 , La claim 1 , Gd claim 1 , and Lu claim 1 , and an oxygen site replaced with nitrogen.3. The device according to claim 1 , wherein a ratio of nitrogen with respect to oxygen is one sixteenth or more claim 1 , and one fourth or less.4. The device according to claim 1 , wherein the resistance change layer includes a first part and a second part provided between the second conductive layer and the first part claim 1 , anda value obtained by dividing an absolute difference between a first nitrogen concentration in the first part and a second nitrogen concentration in the second part by lower one thereof is smaller than a value obtained by dividing an absolute difference between a first concentration, in the first part, of the one element selected from the ...

Non-volatile memory devices and methods of manufacturing the same

This technology relates to nonvolatile memory devices and methods of manufacturing the same. A nonvolatile memory device can include a memory cell array configured to include a plurality of strings, a page buffer unit connected to the plurality of strings, respectively, and configured to sense data, and a switching unit disposed between the memory cell array and the page buffer unit and configured to comprise a variable resistor.

Semiconductor device and method of forming the same

Methods of forming a semiconductor device include forming an insulation layer on a semiconductor structure, forming an opening in the insulation layer, the opening having a sidewall defined by one side of the insulation layer, forming a first metal layer in the opening, at least partially exposing the sidewall of the opening by performing a wet-etching process on the first metal layer, and selectively forming a second metal layer on the etched first metal layer. An average grain size of the first metal layer is smaller than an average grain size of the second metal layer. Related semiconductor devices are also disclosed.

Methods for forming resistive switching memory elements

Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

METHOD FOR MANUFACTURE OF A CEM DEVICE

A method for the manufacture of a correlated electron material device which method comprises forming a conductive substrate and forming a layer of a correlated electron material on the conductive substrate, wherein the forming of the correlated electron material layer comprises: forming a layer of a metal rich transition or other metal compound; and annealing the layer of the metal rich transition or other metal compound in an atmosphere containing a gaseous precursor for an electron-back donating extrinsic ligand capable of occupying an anion vacancy within the transition or other metal compound; wherein the annealing provides that an anion vacancy within the transition or other metal compound is occupied by an electron back-donating extrinsic ligand; and wherein the annealing is carried out at a predetermined temperature and for a predetermined time whereby to activate electron back-donation from a transition or other metal cation to the electron back-donating extrinsic ligand occupying ...

Three dimensional stacked semiconductor memory device

A semiconductor memory device may include: a plurality of row lines extended in parallel to each other in a first horizontal direction; a plurality of column line stacks extended in parallel to each other in a second horizontal direction perpendicular to the first horizontal direction, wherein each of the plurality of column line stacks includes a plurality of column lines extended in parallel to each other in a vertical direction; and a plurality of cell pillars that pass vertically through the column lines of the column line stacks, each of the plurality of cell pillars has a first end and a second end, wherein the first ends of the plurality of cell pillars are electrically coupled to the plurality of row lines, and the second ends of the plurality of cell pillars are floated. Each cell pillar includes a core and variable resistance memory layers.

Two stage forming of resistive random access memory cells

Provided are memory cells, such as resistive random access memory (ReRAM) cells, each cell having multiple metal oxide layers formed from different oxides, and methods of manipulating and fabricating these cells. Two metal oxides used in the same cell have different dielectric constants, such as silicon oxide and hafnium oxide. The memory cell may include electrodes having different metals. Diffusivity of these metals into interfacing metal oxide layers may be different. Specifically, the lower-k oxide may be less prone to diffusion of the metal from the interfacing electrode than the higher-k oxide. The memory cell may be formed to different stable resistive levels and then resistively switched at these levels. Each level may use a different switching power. The switching level may be selected a user after fabrication of the cell and in, some embodiments, may be changed, for example, after switching the cell at a particular level.

Resistance change memory device

A resistance change memory device is provided. The resistance change memory device includes a lower electrode, a tunneling barrier layer disposed on the lower electrode, a resistance switching layer disposed on the tunneling barrier layer, an oxygen vacancy reservoir layer disposed on the resistance switching layer, and an upper electrode disposed on the oxygen vacancy reservoir layer. The oxygen vacancy reservoir layer is electrically conductive.

Nonvolatile memory element and nonvolatile memory device

A variable resistance nonvolatile memory element includes a first electrode, a second electrode, and a variable resistance layer including: a first oxide layer including a metal oxide having non-stoichiometric composition and including p-type carriers; a second oxide layer located between and in contact with the first oxide layer and a second electrode and including a metal oxide having non-stoichiometric composition and including n-type carriers; an oxygen reservoir region located in the first oxide layer, having no contact with the first electrode, and having an oxygen content atomic percentage higher than that of the first oxide layer; and a local region located in the second oxide layer, having contact with the oxygen reservoir region, and having an oxygen content atomic percentage lower than that of the second oxide layer.

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

A nonvolatile semiconductor memory device comprises: a two terminal structured variable resistive element, wherein resistive characteristics defined by current-voltage characteristics at both ends transit between low and high resistance states stably by applying a voltage satisfying predetermined conditions to the both ends, a transition from the low resistance state to the high resistance state occurs by applying a voltage of a first polarity whose absolute value is at or higher than a first threshold voltage, and the reverse transition occurs by applying a voltage of a second polarity whose absolute value is at or higher than a second threshold voltage; a load circuit connected to the variable resistive element in series having an adjustable load resistance; and a voltage generation circuit for applying a voltage to both ends of a serial circuit; wherein the variable resistive element can transit between the states by adjusting a resistance of the load circuit.

Device fabrication

Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.

SEMICONDUCTOR STORAGE DEVICE

A semiconductor storage device includes interconnections in a first layer and a second layer, a first memory cell between a first and a second interconnection, and a dummy memory cell between the first interconnection and a third interconnection. A controller applies a first voltage of a first polarity to the first interconnection and a second voltage of a second polarity opposite the first polarity to the second interconnection at a first time. The controller applies a third voltage at a second time after the first time to the first interconnection. The third voltage having a smaller magnitude smaller than first voltage. The controller applies a fourth voltage to the third interconnection at the second time. The fourth voltage has a magnitude larger than the third voltage but smaller than the first voltage.

RESISTANCE RANDOM ACCESS MEMORY DEVICE

A resistance random access memory device according to one embodiment includes an interlayer insulation film which a trench is made therein, an ion supply layer provided along a bottom surface and a side surface of the trench, a portion of the ion supply layer provided along the bottom surface is thicker than a portion of the ion supply layer provided along the side surface, and a resistance change layer provided at least below the ion supply layer.

1-SELECTOR N-RESISTOR MEMRISTIVE DEVICES

A 1-Selector n-Resistor memristive device includes a first electrode, a selector, a plurality of memristors, and a plurality of second electrodes. The selector is coupled to the first electrode via a first interface of the selector. Each memristor is coupled to a second interface of the selector via a first interface of each memristor. Each second electrode is coupled to one of the memristors via a second interface of each memristor.

RESISTIVE MEMORY CELLS AND PRECURSORS THEREOF, METHODS OF MAKING THE SAME, AND DEVICES INCLUDING THE SAME

Resistive memory cells, precursors thereof, and methods of making resistive memory cells are described. In some embodiments, the resistive memory cells are formed from a resistive memory precursor that includes a switching layer precursor containing a plurality of oxygen vacancies that are present in a controlled distribution therein, optionally without the use of an oxygen exchange layer. In these or other embodiments, the resistive memory precursors described may include a second electrode formed on a switching layer precursor, wherein the second electrode is includes a second electrode material that is conductive but which does not substantially react with oxygen. Devices including resistive memory cells are also described.

Semiconductor device and method of manufacturing same

A semiconductor device including a transistor on a main surface side of a semiconductor substrate; and a resistance change element on a back-surface side of the semiconductor substrate, wherein the transistor includes a low-resistance section in the semiconductor substrate, the low-resistance section extending to the back surface of the semiconductor substrate, an insulating film is provided in contact with a back surface of the low-resistance section, the insulating film has an opening facing the low-resistance section, and the resistance change element is connected to the low-resistance section through the opening.

Confined Defect Profiling within Resistive Random Memory Access Cells

Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A stack including a defect source layer, a defect blocking layer, and a defect acceptor layer disposed between the defect source layer and the defect blocking layer may be subjected to annealing. During the annealing, defects are transferred in a controllable manner from the defect source layer to the defect acceptor layer. At the same time, the defects are not transferred into the defect blocking layer thereby creating a lowest concentration zone within the defect acceptor layer. This zone is responsible for resistive switching. The precise control over the size of the zone and the defect concentration within the zone allows substantially improvement of resistive switching characteristics of the ReRAM cell. In some embodiments, the defect source layer includes aluminum oxynitride, the defect blocking layer includes titanium nitride, and the defect acceptor layer includes aluminum oxide.

Nanoscale three-terminal switching device

A nanoscale three-terminal switching device has a bottom electrode, a top electrode, and a side electrode, each of which may be a nanowire. The top electrode extends at an angle with respect to the bottom electrode and has an end section going over and overlapping the bottom electrode. An active region is disposed between the top electrode and bottom electrode and contains a switching material. The side electrode is disposed opposite from the top electrode and in electrical contact with the active region. A self-aligned fabrication process may be used to automatically align the formation of the top and side electrodes with respect to the bottom electrode.

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

The embodiments provide a semiconductor memory device including: a plurality of first wiring lines extending in a first direction, the first wiring lines being provided in a second direction intersecting the first direction; a plurality of second wiring lines extending in the second direction, the second wiring lines being provided in the first direction; a plurality of memory cells provided in the intersections between the first wiring lines and the second wiring lines, each memory cell having a first stack structure comprising at least a variable resistor film; a contact extending in a third direction intersecting the first and second directions, the contact having a first end connected to one of the first wiring lines or one of the second wiring lines, the contact having a second stack structure having a stack of a plurality of films; and a wiring layer connected to a second end of the contact. At least some of the films of the second stack structure have generally the same third direction ...

MEMORY DEVICE HAVING STITCHED ARRAYS OF 4 F+hu 2 +l MEMORY CELLS

A memory device comprises a semiconductor substrate having a plurality of parallel trenches therein, a memory region formed in the substrate including an array of memory cells having a plurality of vertical selection transistors with respective channels formed in trench sidewalls, a plurality of buried source electrodes in trench bottoms, a plurality of paired gate electrodes formed on paired trench sidewalls, a first and second stitch region disposed adjacent the memory region along a trench direction including a first and second row of gate contacts, respectively, and a row of source contacts disposed in the first or second stitch region with each of the source contacts coupled to a respective one of the source electrodes. One of each pair of the gate electrodes is coupled to a respective one of the first row of gate contacts and the other one of each pair of gate electrodes is coupled to a respective one of the second row of gate contacts.

Electronic device including a switch element in which a metal nitride layer has a nitrogen concentration increasing as a closer distance from a switching layer, and method for fabricating the same

An electronic device includes a switch element. The switch element includes a first electrode including a first metal nitride which is conductive, a second electrode, a switching layer interposed between the first electrode and the second electrode, and a first barrier layer which is interposed between the first electrode and the switching layer and includes a second metal nitride which is insulative, wherein a metal in the first metal nitride is the same as a metal in the second metal nitride, and a metal-to-nitrogen bonding ratio of the first metal nitride is different from a metal-to-nitrogen bonding ratio of the second metal nitride.

1S1R MEMORY CELLS INCORPORATING A BARRIER LAYER

Thin film 1S1R bitcells incorporating a barrier between selector and memory elements. Devices incorporating such bitcells and methods of forming such bitcells are also described. In embodiments, the selector and memory element is each a dielectric material, and advantageously a metal oxide. Between the selector and memory elements is a barrier, which is to reduce intermixing and/or reaction of selector material and memory material. Addition of a barrier layer having suitable material properties into the 1S1R stack may extend the operating lifetime of a bitcell incorporated the stack by resisting intermixing and/or reaction of the selector and memory thin film materials driven by thermal and/or electric field stresses experienced by a bitcell during operation. In embodiments, a barrier layer may include one or more material layers having a composition distinct from the material composition(s) of the selector and memory elements.

NONVOLATILE MEMORY DEVICE HAVING A CURRENT LIMITING ELEMENT

Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. In one embodiment, the current limiting component comprises at least one layer of resistive material that is configured to improve the switching performance and lifetime of the formed resistive switching memory element. The electrical properties of the formed current limiting layer, or resistive layer, are configured to lower the current flow through the variable resistance layer during the logic state programming steps (i.e., set and reset steps) by adding a fixed series resistance in the formed resistive switching memory element found in the nonvolatile memory device.

Storage device and storage unit

A storage device includes: a first electrode; a storage layer including an ion source layer; and a second electrode. The first electrode, the storage layer, and the second electrode are provided in this order. The ion source layer contains a movable element, and has a volume resistivity of about 150 m·cm to about 12000 m·cm both inclusive.

Resistive random access memory devices

The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including an opening in a dielectric structure, the opening having a sidewall, a first electrode on the sidewall of the opening, a spacer layer on the first electrode, a resistive layer on the first electrode and upon an upper surface of the spacer layer, and a second electrode on the resistive layer.

BUFFER LAYER IN MEMORY CELL TO PREVENT METAL REDEPOSITION

Some embodiments relate to a memory device. The memory device includes a first electrode overlying a substrate. A data storage layer overlies the first electrode. A second electrode overlies the data storage layer. A conductive bridge is selectively formable within the data storage layer to couple the first electrode to the second electrode. An active metal layer is disposed between the data storage layer and the second electrode. A buffer layer is disposed between the active metal layer and the second electrode. The buffer layer has a lower reactivity to oxygen than the active metal layer.

SEMICONDUCTOR DEVICE

A semiconductor device may include: a plurality of first conductive lines extending in a first direction; a plurality of second conductive lines spaced apart from the first conductive lines and extending in a second direction intersecting the first direction; and a plurality of memory cells respectively disposed to overlap intersection regions of the plurality of the first conductive lines and the plurality of the second conductive lines; and a layer structured to include an insulating material containing metal ions and formed between each memory cell and at least one of a first conductive line and a second conductive line that intersects with each other at a memory cell.

MULTI-LAYER RECONFIGURABLE SWITCHES

NITRIDE-BASED MEMRISTORS

METHOD FOR INCREASING THE SURFACE ROUGHNESS OF A METAL LAYER

L'invention concerne un procédé pour augmenter la rugosité de surface d'une couche à base d'un métal (10) ayant un pouvoir catalytique, comprenant les étapes suivantes : - fixer (S11) du fluor ou du chlore à la surface de la couche à base de métal (10), en exposant la couche à base de métal (10) à un plasma formé à partir d'un gaz réactif contenant du fluor ou du chlore ; - exposer (S11) la surface de la couche à base de métal (10) à un environnement humide pour produire un acide, par réaction de l'hydrogène de l'environnement humide avec le fluor ou le chlore fixé à la surface de la couche à base de métal, l'acide réagissant avec le métal pour former des résidus, l'ensemble des résidus formant un motif (12) à la surface de la couche à base de métal (10) ; - graver la couche à base de métal (10) à travers les résidus (11), de façon à transférer le motif (12) dans la couche à base de métal (10).

SELF-SELECTING PCM DEVICE NOT REQUIRING DEDICATED SELECTOR TRANSISTOR

PROBLEM TO BE SOLVED: To provide a self-selecting PCM device that does not require a dedicated selector transistor. SOLUTION: A self-selecting storage device is formed by depositing a zinc oxide (ZnO) over a phase-change material through the use of atomic layer deposition (ALD). A diode formed at the ZnO/GST interface exhibits both rectification capability and storage capability within the PCM architecture. COPYRIGHT: (C)2011,JPO&INPIT ...

МЕМРИСТОР НА ОСНОВЕ СМЕШАННОГО ОКСИДА МЕТАЛЛОВ

Настоящее изобретение относится к устройствам микро- и наноэлектроники на основе перспективных материалов. Такие мемристорные устройства со стабильными и повторяемыми характеристиками могут быть использованы для создания компьютерных систем на основе аналоговой архитектуры искусственных нейронных сетей. Данное устройство состоит из активного слоя, расположенного между двумя токопроводящими слоями, находящегося с ними в электрическом контакте и представляющего собой оксид типа АВО, где элемент В является титаном, или цирконием, или гафнием, а элемент А - трехвалентным металлом с ионным радиусом, равным 0,7-1,2 ионного радиуса титана, или циркония, или гафния. Если элемент В является титаном, то в качестве А выбирают алюминий или скандий, если элемент В является цирконием или гафнием, то в качестве А выбирают скандий, или иттрий, или лютеций. Повышение стабильности и повторяемости напряжения переключения, сопротивления в низко- и высокоомном состояниях является техническим результатом предложенного ...

SPEICHERZELLE

3D-NAND MIT TEILBLOCKLÖSCHEN

Es werden Systeme und Verfahren zum Durchführen eines Teilblocklöschvorgangs auf einem Abschnitt eines Speicherarrays beschrieben. Das Speicherarray kann eine Mehrzahl von vertikalen NAND-Ketten einschließen, in denen ein erster Satz der Mehrzahl von vertikalen NAND-Ketten mit einer ersten Drain-seitigen Auswahlleitung verbunden ist, ein zweiter Satz der Mehrzahl von vertikalen NAND-Ketten mit einer zweiten Drain-seitigen Auswahlleitung verbunden ist und sowohl der erste Satz als auch der zweite Satz von vertikalen NAND-Ketten mit einer oder mehreren gemeinsam genutzten Wortleitungen verbunden sind. In Fällen, in denen eine erste vertikale NAND-Kette des ersten Satzes und eine zweite vertikale NAND-Kette des zweiten Satzes beide mit ausgewählten Bitleitungen und derselben gemeinsam genutzten Wortleitung verbunden sind, kann die Selektivität von Speicherzellen durch Anlegen unterschiedlicher Spannungen an die erste Drain-seitige Auswahlleitung und die zweite Drain-seitige Auswahlleitung ...

Method providing for a storage element

A method for forming a thin film (302) comprising a metal, metal compound, or metal oxide on a substrate, which method comprises forming one or more thin film layers (303, 304, 305) of a metal or metal oxide by a deposition process employing reactant precursors and/or relative amounts thereof which are selected to deposit a thin film layer with a controlled amount of dopant derived from at least one reactant precursor.

BISTABLE HETEROJUNCTION DEVICES

... 1447727 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 6 March 1974 [13 March 1973] 10016/74 Heading H1K A method of manufacturing a bi-stable heterojunction device, comprises growing a layer 12 of a first material on a substrate 10 of a second material, providing a blocking layer 14 on the layer 12, forming windows 16 in the blocking layer 14, and introducing ions into the layer 12 to form defects and traps 18 in the layer 14 under the windows 16. The layer 10 may be a semiconductor or metallic and the layer 12 may be a semiconductor or an insulator. The layer 12 may consist of GaN, AlN, GaP, ZnS, ZnSe, GaAs, GaSe, Ga 1-x Al x As, or Ga 1-x As x P on a substrate 10 of Si, Ge, GaAs, Se, W or Mo and the blocking layer 14 may be SiO 2 or Al 2 O 3 . The ions may be introduced by ion implantation or diffusion and consist of Si, Te, Ga, S, Se, P, Zn, Cu, Au, Pt or Ag. The windows 16 are rectangular and 1 micron or less on each side. The layer 10 may be a highly perfect single crystal ...

A light-activated switching resistor, an optical sensor incorporating a light-activated switching resistor, and methods of using such devices

A light-activated switching resistor, an optical sensor incorporating a light-activated switching resistor, and methods of using such devices

ELECTRONIC SWITCHING DEVICES

... 1384000 Ion-impermeable glass compositions INNOTECH CORP 22 Feb 1972 [9 March 1971] 8025/72 Heading C1M [Also in Division H1] The invention is concerned with glass electronic switching devices (see Division H1), and the Specification discloses the following particular compositions, all of which are said to be electrically insulating and ion impermeable, and may be deposited on metal or semi-conductor surface by one or more of sedimentation, r.f. sputtering or centrifuging techniques. All ratios are mole percentages. (i) SiO 2 3-12 (pref. 6À6); ZnO 45-65 (pref. 55À2); PbO 0-6 (pref. 2À7); B 2 O 3 25-40 (pref. 34À5); Al 2 O 3 0-3 (pref. 1À0) wherein calcium oxide, barium oxide or strontium oxide or a mixture thereof can replace ZnO in an amount up to 10 mole per cent of the total composition. (ii) SiO 2 55-65 (pref. 60); PbO 30-40 (pref. 35); Al 2 O 3 0-7 (pref. 0À7) where B 2 O 3 , V 2 C 5 or P 2 O 5 or a mixture thereof can replace SiO 2 and ZnO can replace PbO, up to 20 mole per cent of ...

METHOD OF CONTROLLABLY ALTERING THE CONDUCTIVITY OF A GLASSY AMORPHOUS MATERIAL

Logic high-K/metal gate 1T-1C RRAM MTP/OTP devices

Memory cell comprising nickel-cobalt oxide switching element

Oxides of both nickel and cobalt have lower resistivity than either nickel oxide or cobalt oxide. Nickel oxide and cobalt oxide can be reversibly switched between two or more stable resistivity states by application of suitable electrical pulses. It is expected that oxides including both nickel and cobalt, or (NixCOy)O, will switch between resistivity states at lower voltage and/or current than will nickel oxide or cobalt oxide. A layer of (NixCoy)O can be paired with a diode or transistor to form a nonvolatile memory cell.

METHOD OF MANUFACTURE OF SWITCHES HAS HETEROJUNCTION, NOT VOLATIFS AND FLIP-FLOPS, HAVING REPRODUCIBLE PARAMETERS OF OPERATION

ENCAPSULATING AN ORGANIC OPTOELECTRONIC COMPONENT

BARRIER-FREE SEMICONDUCTOR SWITCHING DEVICE

ENCAPSULATING AN ORGANIC OPTOELECTRONIC COMPONENT

Dispositif encapsulé comprenant : - un composant optoélectronique organique (C) présentant au moins une surface, dite sensible, devant être protégée de l'oxygène et/ou de la vapeur d'eau ; et - une structure multicouche d'encapsulation recouvrant au moins ladite surface sensible, comprenant au moins une couche en matériau organique (O) interposée entre une première (B1) et une deuxième (B2) couche barrière en matériau inorganique non métallique imperméable à l'oxygène et à la vapeur d'eau ; caractérisé en ce que ladite structure multicouche d'encapsulation comprend également au moins une couche (A), dite active, contenant un oxyde non stœchiométrique présentant une lacune en oxygène, également interposée entre ladite première et ladite deuxième couche barrière. Procédé d'encapsulation d'un composant présentant au moins une surface, dite sensible, devant être protégée de l'oxygène et/ou de la vapeur d'eau, par réalisation d'une telle structure multicouche d'encapsulation.

METHOD OF USING ELECTROCHEMICAL COMPONENTS FOR STORING ENERGY AND DATA AND ELECTRONIC CIRCUIT CONFIGURATION

Nonvolatile resistive memory device based on polyimide/graphene oxide nanocomposite

Nonvolatile memory device using resistance material and fabrication method of the same

STORAGE ELEMENT AND OPERATING METHOD OF STORAGE ELEMENT

PROCESS FOR PRODUCING RESISTANCE CHANGE DEVICE

유전체 메모리 소자를 가진 메모리 셀

... 일부 실시예들은 제 1 전극, 제 2 전극, 및 제 1 전극과 제 2 전극 사이에 위치된 유전체를 가진 메모리 셀을 구비한 장치 및 방법들을 포함한다. 유전체는 메모리 셀에 저장된 정보의 제 1 값을 나타내게 메모리 셀이 제 1 전극의 물질의 일부로부터 유전체 내에 도전성 경로를 형성할 수 있게 구성될 수 있다. 또한, 유전체는 메모리 셀에 저장된 정보의 제 2 값을 나타내게 메모리 셀이 도전성 경로를 단절시킬 수 있게 구성될 수 있다.

RESISTANCE STORAGE ELEMENT AND NONVOLATILE SEMICONDUCTOR STORAGE DEVICE

Nonvolatile Nano-channel Memory Device using Mesoporous Material

RESISTANCE CHANGE MEMORY

... 온/오프비가 높은 저항 변화형 기억 장치를 제공할 수 있다. 실시 형태에 따른 저항 변화형 기억 장치는, 제1 원소를 함유하는 제1 전극과, 상기 제1 전극 위에 구비되고, 상기 제1 원소의 산화물을 함유하는 저항 변화층과, 상기 저항 변화층 위에 구비되고, 제2 원소 및 산소를 함유하고, 산소 이온 전도성을 갖고, 비유전율이 상기 저항 변화층의 비유전율보다 높은 산소 전도층과, 상기 산소 전도층 위에 구비된 제2 전극을 구비한다. 상기 제1 전극과 상기 제2 전극 사이의 전압을 제로로부터 연속적으로 증가시킬 때, 상기 산소 전도층보다 먼저 상기 저항 변화층이 절연 파괴된다.

METHOD OF MANUFACTURING NONVOLATILE MEMORY ELEMENT, AND NONVOLATILE MEMORY ELEMENT

A variable resistance nonvolatile memory element manufacturing method includes: forming a first electrode on a substrate; forming a first metal oxide layer having a predetermined oxygen content atomic percentage on the first electrode; forming, in at least one part of the first metal oxide layer, a modified layer higher in resistance than the first metal oxide layer, by oxygen deficiency reduction; forming a second metal oxide layer lower in oxygen content atomic percentage than the first metal oxide layer, on the modified layer; and forming a second electrode on the second metal oxide layer. A variable resistance layer includes the first metal oxide layer having the modified layer and the second metal oxide layer, connects to the first electrode and the second electrode, and changes between high and low resistance states according to electrical pulse polarity. 122-. (canceled)23. A method of manufacturing a nonvolatile memory element , the method comprising:forming a first electrode on a substrate;forming a high resistance layer on the first electrode, the high resistance layer comprising a transition metal oxide;modifying at least one part of the high resistance layer to a modified layer by reducing an oxygen deficiency of the at least one part, the modified layer having a higher oxygen content atomic percentage than the high resistance layer;forming a low resistance layer on the modified layer, the low resistance layer comprising a transition metal oxide having a lower oxygen content atomic percentage than the high resistance layer; andforming a second electrode on the low resistance layer.24. The method of manufacturing a nonvolatile memory element according to claim 23 ,wherein the modifying includes modifying the whole high resistance layer to the modified layer.25. The method of manufacturing a nonvolatile memory element according to claim 23 ,wherein the modifying includes modifying a part of the high resistance layer to the modified layer, andthe ...

MEMORY CELL OF RESISTIVE RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF

A memory cell of a resistive random access memory and a manufacturing method thereof are provided. The method includes the following steps. A first electrode is formed. A metal oxide layer is formed on the first electrode. An electrode buffer stacked layer is formed on the metal oxide layer and includes a first buffer layer and a second buffer layer, and the first buffer layer is located between the second buffer layer and the metal oxide layer. An oxidation reaction between the second buffer layer and the metal oxide layer is relatively easier than an oxidation reaction between the first buffer layer and the metal oxide layer. A second electrode layer is formed on the electrode buffer stacked layer. 1. A method for manufacturing a memory cell of a resistive random access memory , comprising:forming a first electrode;forming a metal oxide layer on the first electrode;forming an electrode buffer stacked layer on the metal oxide layer, wherein the electrode buffer stacked layer comprises a first buffer layer and a second buffer layer, the first buffer layer is located between the metal oxide layer and the second buffer layer, and an oxidation reaction between the second buffer layer and the metal oxide layer is relatively easier than an oxidation reaction between the first buffer layer and the metal oxide layer; andforming a second electrode on the electrode buffer stacked layer.2. The method for manufacturing the memory cell of the resistive random access memory as claimed in claim 1 , wherein after the second electrode is formed claim 1 , the method further comprises performing a heat treatment process.3. The method for manufacturing the memory cell of the resistive random access memory as claimed in claim 1 , wherein the heat treatment process comprises an annealing processing claim 1 , a microwave heating processing claim 1 , or an electricity-based oxygen ion migration processing claim 1 , and a temperature of the heat treatment process is 200˜800 degrees Celsius ...

NONVOLATILE STORAGE ELEMENT AND METHOD FOR MANUFACTURING SAME

A variable resistance nonvolatile storage element includes: a first electrode; a second electrode; and a variable resistance layer having a resistance value that reversibly changes based on an electrical signal applied between the electrodes, wherein the variable resistance layer has a structure formed by stacking a first transition metal oxide layer, a second transition metal oxide layer, and a third transition metal oxide layer in this order, the first transition metal oxide layer having a composition expressed as MO(where M is a transition metal and O is oxygen), the second transition metal oxide layer having a composition expressed as MO(where x>y), and the third transition metal oxide layer having a composition expressed as MO(where y>z). 121-. (canceled)22. A nonvolatile storage element comprising:a first electrode;a second electrode; anda variable resistance layer provided between the first electrode and the second electrode, and having a resistance value that reversibly changes based on an electrical signal applied between the first electrode and the second electrode,{'sub': x', 'y', 'z, 'wherein the variable resistance layer has a structure formed by stacking a first transition metal oxide layer, a second transition metal oxide layer, and a third transition metal oxide layer in this order, the first transition metal oxide layer having a composition expressed as MO(where M is a transition metal and O is oxygen), the second transition metal oxide layer having a composition expressed as MO(where x>y), and the third transition metal oxide layer having a composition expressed as MO(where y>z), and'}oxygen content atomic percentages of the first transition metal oxide layer, the second transition metal oxide layer, and the third transition metal oxide layer are set to be different from each other.23. The nonvolatile storage element according to claim 22 ,wherein the first transition metal oxide layer is a layer in which a filament path is formed, the filament ...

BOTTOM ELECTRODES FOR USE WITH METAL OXIDE RESISTIVITY SWITCHING LAYERS

In a first aspect, a metal-insulator-metal (“MIM”) stack is provided that includes a first conductive layer, a resistivity-switching layer having a metal oxide layer formed above the first conductive layer, a material layer between the first conductive layer and the resistivity-switching layer, and a second conductive layer above the resistivity-switching layer. The first conductive layer includes a multi-layer metal-silicide stack, and the material layer has a Gibbs free energy of formation per O between about −3 and −6 eV. A memory cell may be formed from the MIM stack. Numerous other aspects are provided. 1. A metal-insulator-metal stack comprising:a first conductive layer comprising a multi-layer metal-silicide stack;a resistivity-switching layer comprising a metal oxide layer formed above the first conductive layer;a material layer disposed between the first conductive layer and the resistivity-switching layer, wherein the material layer has a Gibbs free energy of formation per O between about −3 and −6 eV; anda second conductive layer formed above the resistivity-switching layer.2. The metal-insulator-metal stack of claim 1 , wherein the multi-layer metal-silicide stack comprises:a first metal-silicide layer comprising one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, cobalt silicide or molybdenum silicide; anda second metal-silicide layer comprises a different one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, cobalt silicide or molybdenum silicide.3. The metal-insulator-metal stack of claim 2 , wherein the first metal-silicide layer comprises nickel silicide and the second metal-silicide layer comprises titanium silicide.4. The metal-insulator-metal stack of claim 2 , wherein the first metal-silicide layer comprises cobalt silicide and the second metal-silicide layer comprises titanium silicide.5. The metal-insulator-metal stack of claim 2 , wherein the first metal-silicide layer comprises titanium ...

NONVOLATILE MEMORY ELEMENT, METHOD OF MANUFACTURING NONVOLATILE MEMORY ELEMENT, METHOD OF INITIAL BREAKDOWN OF NONVOLATILE MEMORY ELEMENT, AND NONVOLATILE MEMORY DEVICE

A nonvolatile memory element includes a current steering element which bidirectionally rectifies current in response to applied voltage and a variable resistance element connected in series with the current steering element. The current steering element includes an MSM diode and an MSM diode which are connected in series and each of which bidirectionally rectifies current in response to applied voltage. The MSM diode and the MSM diode include a lower electrode, a first current steering layer, a first metal layer, a second current steering layer, and an upper electrode which are stacked in this order. The current steering element has a breakdown current which is larger than an initial breakdown current which flows in the variable resistance element at the time of initial breakdown. 1. A nonvolatile memory element comprising:a current steering element which bidirectionally rectifies current in response to applied voltage; anda variable resistance element which is connected in series with the current steering element and reversibly changes between a high resistance state and a low resistance state according to a polarity of applied voltage,wherein the current steering element includes a first bidirectional diode and a second bidirectional diode which are connected in series and each of which bidirectionally rectifies current in response to applied voltage,the first bidirectional diode and the second bidirectional diode include a first electrode, a first current steering layer, a first metal layer, a second current steering layer, and a second electrode which are stacked in this order, andthe current steering element has a breakdown current which is larger than an initial breakdown current which flows in the variable resistance element at a time of initial breakdown which changes the variable resistance element from an initial state to a state in which the variable resistance element can reversibly change between the high resistance state and the low resistance state, ...

MIIIM DIODE HAVING LANTHANUM OXIDE

A MIIIM diode and method of fabricating are disclosed. In one aspect, the MIIIM diode comprises a first metal electrode, a first region comprising a first insulator material having an interface with the first metal electrode, a second region comprising a second insulator material having an interface with the first insulator material, a third region comprising a third insulator material having an interface with the second insulator material, and a second metal electrode having an interface with the third insulator material. At least one of the first, second, or third insulator materials is lanthanum oxide. 1. A metal-insulator diode comprising:a first metal electrode;a first region comprising a first insulator material having an interface with the first metal electrode;a second region comprising a second insulator material having an interface with the first insulator material;a third region comprising a third insulator material having an interface with the second insulator material; anda second metal electrode having an interface with the third insulator material, at least one of the first, second, or third insulator materials is lanthanum oxide.2. The diode of claim 1 , wherein:at least one of the first insulator material, the second insulator material, or the third insulator material is hafnium oxide.3. The diode of claim 1 , wherein the first insulator material is hafnium oxide and the second insulator material is lanthanum oxide.4. The diode of claim 3 , wherein the third insulator material is silicon oxide.5. The diode of claim 3 , wherein the first region is approximately 10 angstroms thick and the second region is approximately 20 angstroms thick.6. The diode of claim 1 , wherein the first insulator material is lanthanum oxide and the second insulator material is hafnium oxide.7. The diode of claim 5 , wherein the first region is approximately 20 angstroms thick and the second region is approximately 10 angstroms thick.8. The diode of claim 1 , wherein the ...

VARIABLE RESISTIVE ELEMENT, AND NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE

A variable resistive element that performs a forming action at small current and a stable switching operation at low voltage and small current, and a low-power consumption large-capacity non-volatile semiconductor memory device including the element are realized. The element includes a variable resistor between first and second electrodes. The variable resistor includes at least two layers, which are a resistance change layer and high-oxygen layer, made of metal oxide or metal oxynitride. The high-oxygen layer is inserted between the first electrode having a work function smaller than the second electrode and the resistance change layer. The oxygen concentration of the metal oxide of the high-oxygen layer is adjusted such that the ratio of the oxygen composition ratio to the metal element to stoichiometric composition becomes larger than the ratio of the oxygen composition ratio to the metal element of the metal oxide forming the resistance change layer to stoichiometric composition. 1. A variable resistive element comprising:a variable resistor, a first electrode, and a second electrode, the variable resistor being sandwiched between the first electrode and the second electrode, whereinan electric resistance between the first and second electrodes is reversibly changed by opening and closing a filament path, formed in the variable resistor, according to an application of voltage between the first and second electrodes,the first electrode and the second electrode are made of conductive materials having different work functions,a work function of the second electrode is larger than a work function of the first electrode,the variable resistor includes a plurality of layers having at least a resistance change layer and a high-oxygen layer,the high-oxygen layer is sandwiched between the first electrode and the resistance change layer, anda ratio of an oxygen composition ratio to stoichiometric composition of metal oxide or metal oxynitride forming the high-oxygen layer ...

Memory Arrays and Methods of Forming Memory Cells

Some embodiments include methods of forming memory cells utilizing various arrangements of conductive lines, electrodes and programmable material; with the programmable material containing high k dielectric material directly against multivalent metal oxide. Some embodiments include arrays of memory cells, with the memory cells including programmable material containing high k dielectric material directly against multivalent metal oxide. 126-. (canceled)27. An array of memory cells , comprising:a plurality of first conductive lines extending along a first axis;spaced-apart programmable material lines extending across the first conductive lines; each of the programmable material lines comprising a high k dielectric portion directly against a multivalent metal oxide portion; the programmable material lines extending along a second axis which intersects the first axis;spaced-apart segments of first electrode material over the first conductive lines; the multivalent metal oxide of the programmable material lines being directly against the segments of the first electrode material;lines of second electrode material over and directly against the high k dielectric portions of the programmable material lines; anda plurality of second conductive lines extending along the first axis and being directly against the second electrode material.28. The array of wherein each of the programmable material lines has a thickness of the high k dielectric portion that is less than or equal to about one-fourth of a thickness of the individual multivalent metal oxide portion.29. The array of wherein the high k dielectric portions are configured as upwardly-opening containers claim 27 , and wherein the second electrode lines are within the upwardly-opening containers.30. The array of further comprising select devices between the first electrode material segments and the first conductive lines.31. The array of wherein the select devices are Schottky diodes.32. The array of wherein the second ...

RESISTIVE MEMORY HAVING RECTIFYING CHARACTERISTICS OR AN OHMIC CONTACT LAYER

Disclosed is a resistive memory simultaneously having rectifying characteristics and resistive characteristics according to a bias direction, wherein a resistive diode is interposed between electrodes at the top and bottom thereof. The resistive diode has a form in which a p-type resistive semiconductor layer is bonded to an n-type resistive semiconductor layer. When a high reverse bias is applied to the resistive diode, the resistive diode forms a conductive filament. When a forward bias is applied thereafter, a reset that destroys a portion of the formed conductive filament occurs, and as a result, a high resistance state is formed. Additionally, when a reverse bias is applied again, a set operation regenerating a conductive filament occurs. Thus, a low resistance state is achieved. Moreover, in order to achieve a resistive semiconductor layer and ohmic contact, and suppress the formation of a Schottky barrier, an ohmic contact layer is formed on the resistive diode. The present invention enables each memory cell to read information without misreading said information, even at a low readout voltage, and reduces the driving power required for a memory structure, such that a high-capacity and high-density memory is produced, and complexity and high costs of manufacturing processes may be avoided. 1. A resistive random access memory comprising:a lower electrode;a changeable resistance diode formed on the lower electrode; andan upper electrode formed on the changeable resistance diode,wherein the changeable resistance diode has both rectifying characteristics obtained through a p-n junction and resistance change obtained by forming a conductive filament.2. The resistive random access memory of claim 1 , wherein the changeable resistance diode comprises:a p-type changeable resistance semiconductor layer formed on the lower electrode; andan n-type changeable resistance semiconductor layer formed on the p-type changeable resistance semiconductor layer.3. The resistive ...

Nonvolatile Memory Device Having An Electrode Interface Coupling Region

Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.

TRAP PASSIVATION IN MEMORY CELL WITH METAL OXIDE SWITCHING ELEMENT

Non-volatile storage elements having a reversible resistivity-switching element and techniques for fabricating the same are disclosed herein. The reversible resistivity-switching element may be formed by depositing an oxygen diffusion resistant material (e.g., heavily doped Si, W, WN) over the top electrode. A trap passivation material (e.g., fluorine, nitrogen, hydrogen, deuterium) may be incorporated into one or more of the bottom electrode, a metal oxide region, or the top electrode of the reversible resistivity-switching element. One embodiment includes a reversible resistivity-switching element having a bi-layer capping layer between the metal oxide and the top electrode. Fabricating the device may include depositing (un-reacted) titanium and depositing titanium oxide in situ without air break. One embodiment includes incorporating titanium into the metal oxide of the reversible resistivity-switching element. The titanium might be implanted into the metal oxide while depositing the metal oxide, or after deposition of the metal oxide. 1. A method for fabricating a resistive random access memory (RRAM) element , the method comprising:forming a resistive random access memory (RRAM) element having a bottom electrode that includes a first electrically conductive material, a metal oxide region adjacent to the first electrically conductive material, and a top electrode that includes a second electrically conductive material adjacent to the metal oxide region, forming the resistive random access memory (RRAM) element includes adding a trap passivation material to one or more of the first electrically conductive material, the metal oxide region, or the second electrically conductive material, the passivation material passivates traps at at least one of a first interface between the metal oxide region and the bottom electrode or a second interface between the metal oxide region and the top electrode.2. The method for fabricating a resistive random access memory (RRAM) ...

LARGE ARRAY OF UPWARD POINTING P-I-N DIODES HAVING LARGE AND UNIFORM CURRENT

A circuit is provided that includes a plurality of vertically oriented p-i-n diodes. Each p-i-n diode includes a bottom heavily doped p-type region. When a voltage between about 1.5 volts and about 3.0 volts is applied across each p-i-n diode, a current of at least 1.5 microamps flows through 99 percent of the p-i-n diodes. Numerous other aspects are also provided. 1. A circuit comprising:a plurality of vertically oriented p-i-n diodes, wherein each p-i-n diode comprises a bottom heavily doped p-type region,wherein when a voltage between about 1.5 volts and about 3.0 volts is applied across each p-i-n diode, a current of at least 1.5 microamps flows through 99 percent of the p-i-n diodes.2. The circuit of claim 1 , wherein when a voltage between about 1.8 volts and about 2.2 volts is applied across each p-i-n diode claim 1 , a current of at least 1.5 microamps flows through 99 percent of the p-i-n diodes.3. The circuit of claim 1 , further comprising a plurality of resistivity-switching elements claim 1 , each p-i-n diode coupled to a corresponding one of the resistivity-switching elements.4. The circuit of claim 3 , wherein each resistivity-switching element comprises binary metal oxide or carbon nanotube fabric.5. The memory of claim 3 , wherein each resistivity-switching element comprises one or more of NiO claim 3 , NbO claim 3 , TiO claim 3 , HfO claim 3 , AlO claim 3 , MgO claim 3 , CoO claim 3 , CrO claim 3 , VO claim 3 , ZnO claim 3 , ZrO claim 3 , BNand AlN.6. The circuit of claim 1 , wherein each p-i-n diode is in contact with a silicide claim 1 , germanide claim 1 , or silicide-germanide layer.7. The circuit of claim 1 , further comprising:a first plurality of substantially parallel, substantially coplanar rail-shaped conductors formed above a substrate; anda second plurality of substantially parallel, substantially coplanar rail-shaped conductors formed above the first plurality of substantially parallel, substantially coplanar rail-shaped conductors, ...

Nonvolatile resistance change element

According to one embodiment, a nonvolatile resistance change element includes a first electrode, a second electrode, a first layer and a second layer. The second electrode contains at least one metal element selected from Ag, Cu, Ni, Co, Al, and Ti. The first layer is arranged between the first electrode and the second electrode. The second layer is arranged between the first electrode and the first layer. A diffusion coefficient of the metal element in the second layer is larger than a diffusion coefficient of the metal element in the first layer.

MEMORY COMPONENT, MEMORY DEVICE, AND METHOD OF OPERATING MEMORY DEVICE

A memory component including first and second electrodes with a memory layer therebetween, the memory layer having first and second memory layers, the first memory layer containing aluminum and a chalcogen element of tellurium, the second memory layer between the first memory layer and the first electrode and containing an aluminum oxide and at least one of a transition metal oxide and a transition metal oxynitride having a lower resistance than the aluminum oxide. 1. A memory component comprising:a first electrode;a second electrode; and the memory layer includes (a) a first memory layer containing aluminum (Al) and a chalcogen element of tellurium (Te), and (b) a second memory layer between the first memory layer and the first electrode and containing an aluminum oxide and at least one of a transition metal oxide and a transition metal oxynitride having a lower resistance than the aluminum oxide, and', 'the second memory layer has a configuration in which a first layer made of at least one of the transition metal oxide and the transition metal oxynitride and a second layer containing the aluminum oxide as its main component are layered in that order proceeding from a side facing the first electrode., 'a memory layer between the first and second electrodes, wherein,'}2. The memory component according to claim 1 , wherein the first memory layer has a thickness of 1 nm or more and has a resistance lower than the resistance value of the second memory layer.3. The memory component according to claim 1 , wherein the aluminum oxide and at least one of the transition metal oxide and the transition metal oxynitride are present in the first layer of the second memory layer in a mixed state.5. The memory component according to claim 1 , wherein the transition metal oxide or the transition metal oxynitride is at least one oxide or oxynitride of a transition metal selected from the group consisting of titanium (Ti) claim 1 , zirconium (Zr) claim 1 , hafnium (Hf) claim 1 , ...

NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

A nonvolatile memory device includes a first film layer formed on a substrate, and a second film layer formed on the first film layer. The second film layer comprises a first oxide material having a first oxygen content, and a second oxide material disposed laterally of the first oxide material and having a second oxygen content that is greater than the first oxygen content. The memory device also includes a third film layer formed on the second film layer, and the third film layer is disposed on the first oxide material and exposes portions of the second oxide material. 1. A nonvolatile memory device , comprising:a first film layer formed on a substrate; a first oxide material having a first oxygen content; and', 'a second oxide material disposed laterally of the first oxide material and having a second oxygen content that is greater than the first oxygen content; and, 'a second film layer formed on the first film layer, the second film layer comprisinga third film layer formed on the second film layer, the third film layer disposed on the first oxide material and exposing portions of the second oxide material.2. The nonvolatile memory device of claim 1 , wherein claim 1 , in the presence of an electric field claim 1 , the first oxygen content in a portion of the first oxide material is substantially equal to a stoichiometric amount of oxygen.3. The nonvolatile memory device of claim 1 , wherein the first oxide material and the second oxide material comprise the same constituent elements.4. The nonvolatile memory device of claim 1 , wherein the first film layer comprises a plurality of linear claim 1 , repeating rows of a conductive material disposed in a first direction on the substrate and a plurality of insulating sections disposed between the rows.5. The nonvolatile memory device of claim 4 , wherein second oxide material comprises a plurality of linear claim 4 , repeating rows disposed in a second direction on the first film layer claim 4 , the second ...

SELECTION DEVICE AND NONVOLATILE MEMORY CELL INCLUDING THE SAME AND METHOD OF FABRICATING THE SAME

A selection device, non-volatile memory cell, and method of fabricating the same. The selection device employs an oxide laminate structure including a tunneling oxide layer and a metal-cluster oxide layer between first and second electrodes, enabling a high selection ratio and sufficient on-current density to allow program data recordation in a memory cell at relatively low voltage. The non-volatile memory cell includes the selection device electrically connected to a resistive random access memory device, including a resistance change layer, enabling suppression of current leakage from a non-selected adjacent memory cell in an array structure. In the method of fabrication, a tunneling oxide layer is formed by depositing and oxidizing a metal layer to control oxygen vacancy density in the metal-cluster oxide layer, and an interface oxide layer is formed in the tunneling oxide layer by doping of metal-clusters in the metal-cluster oxide layer, improving on-current density of the selection device. 1. A selection device comprising:a first electrode;a second electrode;a tunneling oxide layer interposed between the first electrode and the second electrode; anda metal cluster oxide layer interposed between the tunneling oxide layer and the first electrode and/or between the tunneling oxide layer and the second electrode,wherein the tunneling oxide layer comprises an insulating oxide layer, and an interface oxide layer formed by doping of a metal contained in the metal cluster oxide layer into the tunneling oxide layer to adjoin the metal cluster oxide layer.2. The selection device according to claim 1 , wherein the interface oxide layer is an oxide layer into which a metal having a different valence electron number than the metal contained in the tunneling oxide layer is diffused.3. The selection device according to claim 1 , wherein the insulating oxide layer has a higher work function than the metal cluster oxide layer or the same work function as that of the metal ...

RESISTANCE CHANGE MEMORY DEVICE HAVING THRESHOLD SWITCHING AND MEMORY SWITCHING CHARACTERISTICS, METHOD OF FABRICATING THE SAME, AND RESISTANCE CHANGE MEMORY DEVICE INCLUDING THE SAME

Disclosed are a resistance change memory device, a method of fabricating the same, and a resistance change memory array including the same. The resistance change memory device includes a first electrode and a second electrode. A hybrid switching layer is interposed between the first electrode and the second electrode. The hybrid switching layer is a metal oxide layer having both threshold switching characteristics and memory switching characteristics. 1. A resistance change memory device comprising:a first electrode;a second electrode; anda hybrid switching layer disposed between the first electrode and the second electrode, the hybrid switching layer being a metal oxide layer having both threshold switching characteristics and memory switching characteristics.2. The resistance change memory device according to claim 1 , wherein the hybrid switching layer is represented by FeO(1≦X≦2) claim 1 , VO(1≦X≦2.5) claim 1 , TiO(1≦X≦2) claim 1 , or NbO(1≦X≦2.5).3. The resistance change memory device according to claim 1 , wherein the hybrid switching layer comprises:a threshold switching layer disposed on the first electrode and having threshold switching characteristics; anda memory switching layer disposed on the threshold switching layer and having memory switching characteristics,the memory switching layer and the threshold switching layer being formed of the same kind of metal oxide, the memory switching layer having a higher oxygen content than the threshold switching layer.4. The resistance change memory device according to claim 3 , wherein the threshold switching layer exhibits metal-insulator transition characteristics.5. The resistance change memory device according to claim 3 , wherein the threshold switching layer is represented by FeO(1≦X≦1.5) claim 3 , VO(1≦X≦2) claim 3 , TiO(1≦X≦1.75) claim 3 , or NbO(1≦X≦2).6. The resistance change memory device according to claim 3 , wherein the threshold switching layer is represented by NbO(1≦X≦2).7. The resistance change ...

OXIDE BASED MEMORY WITH A CONTROLLED OXYGEN VACANCY CONDUCTION PATH

Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming a substoichiometric oxide over the first conductive element, forming a second conductive element over the substoichiometric oxide, and oxidizing edges of the substoichiometric oxide by subjecting the substoichiometric oxide to an oxidizing environment to define a controlled oxygen vacancy conduction path near a center of the oxide. 1. An oxide based memory cell , comprising:a first conductive element;a substoichiometric oxide on the first conductive element; anda second conductive element directly on the substoichiometric oxide;wherein the memory cell includes a controlled oxygen vacancy conduction path near a center of the substoichiometric oxide.2. The memory cell of claim 1 , wherein the substoichiometric oxide is directly on the first conductive element.3. The memory cell of claim 1 , wherein the controlled oxygen vacancy conduction path is directly between the first conductive element and the second conductive element.4. The memory cell of claim 1 , wherein the first conductive element comprises a pillar and the controlled oxygen vacancy conduction path is at a center of the pillar.5. The memory cell of claim 1 , wherein the controlled oxygen vacancy conduction path is at an intersection of the substoichiometric oxide and a material intersecting the substoichiometric oxide.6. The memory cell of claim 1 , wherein the substoichiometric oxide comprises one of a titanium oxide (TiOx) claim 1 , a copper oxide (CuOx) claim 1 , and a tantalum oxide (TaOx).7. An oxide based memory cell claim 1 , comprising:a first conductive element;a substoichiometric oxide having an oxygen percentage below a stoichiometric ratio for the oxide on the first conductive element; anda second conductive element on the substoichiometric oxide;wherein the memory cell includes a ...

Bipolar Multistate Nonvolatile Memory

Embodiments generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching capacity by using multiple layers of variable resistance layers. In one embodiment, the resistive switching element comprises at least three layers of variable resistance materials to increase the number of logic states. Each variable resistance layer may have an associated high resistance state and an associated low resistance state. As the resistance of each variable resistance layer determines the digital data bit that is stored, the multiple variable resistance layers per memory element allows for additional data storage without the need to further increase the density of nonvolatile memory devices. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. 1. A multistate nonvolatile memory element comprising:a first layer operable as a first variable resistance layer;a second layer operable as a second variable resistance layer; anda third layer operable as a third variable resistance layer;wherein the first layer, the second layer, and the third layer are interconnected in series within the multistate nonvolatile memory element;wherein the first layer is configured to switch between a first low resistance state and a first high resistive state;wherein the second layer is configured to switch between a second low resistance state and a second high resistance state;wherein the third layer is configured to switch between a third low resistance state and a third high resistance state;wherein at least two of the first layer, the second layer, and the third layer comprises lanthanum oxide; andwherein the multistate nonvolatile memory element is switchable between at least four different stable resistive ...

SWITCHING ELEMENTS AND DEVICES, MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME

A switching element includes: a first electrode; a second electrode; and a silicon-containing chalconitride layer between the first electrode and the second electrode. A switching device includes: a threshold switch material layer between a first electrode and a second electrode. The threshold switch material layer includes a cationic metal element, a chalcogen element, a silicon element and a nitrogen element. A memory device include: a plurality of first wirings arranged in parallel with each other; a plurality of second wirings crossing the first wirings, and arranged in parallel with each other; and a memory cell formed at each intersection of the plurality of first wirings and the plurality of second wirings. The memory cell includes a laminate having a silicon-containing chalconitride layer, an intermediate electrode, and a memory layer. 1. A switching element comprising:a first electrode;a second electrode; anda silicon-containing chalconitride layer interposed between the first electrode and the second electrode.2. The switching element of claim 1 , wherein the silicon-containing chalconitride layer has a nitride thin film formed on the surface thereof.3. The switching element of claim 2 , wherein the nitride thin film comprises includes SiNx.4. The switching element of claim 1 , wherein the silicon-containing chalconitride layer comprises:a chalcogenide skeleton; anda silicon nitride skeleton bonded to the chalcogenide skeleton.5. The switching element of claim 4 , wherein the chalcogenide skeleton includes a cationic metal atom bonded to a chalcogen atom.6. The switching element of claim 5 , wherein the silicon nitride skeleton includes a silicon atom bonded to a nitrogen atom.7. The switching element of claim 6 , wherein the silicon atom is bonded to the chalcogenide atom to bond the chalcogenide skeleton to the silicon nitride skeleton.8. The switching element of claim 4 , wherein the silicon nitride skeleton includes a silicon atom bonded to a nitrogen ...

SEMICONDUCTOR STRUCTURES AND MEMORY CELLS INCLUDING CONDUCTIVE MATERIAL AND METHODS OF FABRICATION

Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed. 1. A method of forming at least one conductive element , comprising:forming a conductive material comprising silver over surfaces of a structure comprising at least one opening defined by sidewalls of a dielectric material;forming another conductive material over the conductive material; andperforming a polishing process to substantially redistribute at least one of the conductive material and the another conductive material into an unfilled region of the at least one opening.2. The method of claim 1 , wherein forming a conductive material comprising silver over surfaces of a structure comprising at least one opening defined by sidewalls of a dielectric material comprises forming the conductive material comprising silver over the sidewalls of the dielectric material and a surface of an electrode between the sidewalls of the dielectric material.3. A method of forming a memory cell claim 1 , comprising:forming a memory material over surfaces of a structure comprising at least one opening overlying a first electrode;forming a ...

Memory Cells, Memory Cell Constructions, and Memory Cell Programming Methods

Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material between the first conductive material and the second conductive material. A resistance of the memory component is configurable via a current conducted from the first conductive material through the oxide material to the second conductive material. Other embodiments include a diode comprising metal and a dielectric material and a memory component connected in series with the diode. The memory component includes a magnetoresistive material and has a resistance that is changeable via a current conducted through the diode and the magnetoresistive material. 134-. (canceled)35. A memory cell comprising: a first conductive material;', 'a second conductive material;', 'an oxide material between the first conductive material and the second conductive material; and', 'wherein the memory component is configured to have different electrical resistances corresponding to different memory states of the memory cell as a result of conduction of a current from the first conductive material through the oxide material to the second conductive material; and, 'a memory component comprisinga diode comprising a first electrode, a second electrode, and a dielectric material, the diode being connected in series with the memory component so that a current passing through the diode also passes through the memory component.36. The memory cell of wherein the first electrode comprises a first metal and the second electrode comprises a second metal different than the first metal.37. The memory cell of wherein a first work function associated with the first metal is related to an amount of energy used to remove an electron from the first metal and a second work function associated with the second metal is related to an amount of energy used to remove an electron from the second metal claim 36 , the first work function being lower than the second ...

Memristive elements that exhibit minimal sneak path current

Memristive elements are provided that include an active region disposed between a first electrode and a second electrode, the active region including two switching layers formed of a switching material capable of carrying a species of dopants and a conductive layer formed of a dopant source material. Memristive elements also are provided that include two active regions disposed between a first electrode and a second electrode, and a third electrode being disposed between and in electrical contact with both of the active regions. Each of the active regions include a switching layer formed of a switching material capable of carrying a species of dopants and a conductive layer formed of a dopant source material. Multilayer structures including the memristive elements also are provided.

VARIABLE RESISTANCE ELEMENT AND SEMICONDUCTOR STORAGE DEVICE

A variable resistance element is formed by sandwiching a metal oxide layer whose resistance changes between a pair of electrodes and the metal oxide layer includes a pair of variable resistance layers whose resistances change by formation of a current path and a branching suppression layer which is sandwiched between the variable resistance layers and suppresses branching of the current path. 1. A variable resistance element , wherein the variable resistance element is formed by sandwiching a metal oxide layer whose resistance changes between a pair of electrodes andthe metal oxide layer includesa pair of variable resistance layers whose resistances change by formation of a current path andbranching suppression layer which is sandwiched between the variable resistance layers and suppresses branching of the current path.2. The variable resistance element described in claim 1 , whereinthe variable resistance layer and the branching suppression layer include an oxide of a first metallic element that is at least one metallic element among Ni, Cu, and Co; and for the suppression of the branching, a second metallic element that can be ionized into a trivalent or more state is added and a partial substitution of the first metallic element with the second metallic element is performed.3. The variable resistance element described in claim 2 , whereinthe second metallic element is at least one metallic element among Al, Ti, Zr, Hf, Ta, W, and Mo.4. The variable resistance element described in claim 3 , whereinan addition amount of the second metallic element is 0.01 mol % to 50 mol %.5. The variable resistance element described in claim 1 , whereina film thickness of the variable resistance layer is set to a range from 0.1 nm to 3 nm.6. The variable resistance element described in claim 1 , whereina film thickness of the variable resistance layer is set to a range from 0.1 nm to 1 nm.7. The variable resistance element described in claim 1 , whereinthe variable resistance ...

Nonvolatile memory element and method for manufacturing the same

A nonvolatile memory element includes a first electrode, a second electrode, and a variable resistance layer positioned between the first electrode and the second electrode. The variable resistance layer has a resistance state which reversibly changes based on an electrical signal applied between the first electrode and the second electrode. The variable resistance layer includes a first variable resistance layer having a first metal oxide and a second variable resistance layer having a second metal oxide. The second variable resistance layer includes a metal-metal bonding region including a metal bond of metal atoms included in the second metal oxide, and the second metal oxide has a low degree of oxygen deficiency and a high resistance value compared to the first metal oxide.

RESISTANCE SWITCHING MATERIAL ELEMENT AND DEVICE EMPLOYING THE SAME

According to example embodiments, a resistance switching material element includes a resistance switching material layer between a first electrode and a second electrode, and a self-rectifying layer provided between the resistance switching material layer and one of the first and second electrodes. The second electrode may be on the first electrode. 1. A resistance switching material element comprising:a first electrode;a second electrode on the first electrode;a resistance switching material layer between the first electrode and the second electrode; anda self-rectifying layer between the resistance switching material layer and one of the first electrode and the second electrode.2. The resistance switching material element of claim 1 , wherein the self-rectifying layer contacts the resistance switching material layer.3. The resistance switching material element of claim 1 , wherein the self-rectifying layer is configured to have a tunneling mechanism that varies according to an applied voltage.4. The resistance switching material element of claim 3 , whereina first voltage is less than a second voltage,the self-rectifying layer is configured to have direct tunneling properties in which a flow of current is restricted if the first voltage is applied to the resistance switching material element,the self-rectifying layer is configured to have tunneling properties in which the flow of current rapidly increases if the second voltage is applied to the resistance switching material element.5. The resistance switching material element of claim 1 , whereinthe self-rectifying layer comprises a first area and a second area, andthe first area and the second have different conduction band offsets in a thickness direction of the self-rectifying layer.6. The resistance switching material element of claim 5 , whereinone of the first and second areas has a relatively larger conduction band offset than a conduction band offset of an other of the first and second areas, andthe one of ...

INVISIBLE/TRANSPARENT NONVOLATILE MEMORY

An optically transparent memory device comprises first and second electrodes, wherein the electrodes are formed from conductive material(s) that is transparent. The memory device also provides a resistive memory layer coupled to the first and second electrodes. The resistive memory layer is formed from a resistive memory material providing resistive switching that is transparent. Additionally, the optically transparent memory device may be incorporated into a variety of electronics. 1. An optically transparent memory device comprising:a first electrode, wherein the first electrode is formed from a first conductive material that is transparent;a resistive memory layer coupled to the first electrode, wherein the resistive memory layer is formed from a resistive memory material that is transparent; anda second electrode coupled to the resistive memory layer, wherein the second electrode is formed from a second conductive material that is transparent.2. The device of claim 1 , wherein the first and second electrodes are positioned on the resistive memory layer claim 1 , and the first and second electrodes are separated by a nanogap.3. The device of claim 1 , wherein the resistive memory layer is positioned between the first electrode and the second electrode.4. The device of claim 1 , further comprising a substrate claim 1 , wherein the substrate is made from an insulating material that is transparent.5. The device of claim 1 , wherein the first conductive material is graphene claim 1 , indium tin oxide (ITO) claim 1 , a transparent conducting oxide claim 1 , fluorine doped tin oxide (FTO) claim 1 , doped zinc oxide claim 1 , aluminum-doped zinc-oxide (AZO) claim 1 , indium-doped cadmium-oxide claim 1 , a transparent conducting polymer claim 1 , polyacetylene claim 1 , polyaniline claim 1 , polypyrrole claim 1 , polythiophenes claim 1 , or a nanocarbon coating.6. The device of claim 1 , wherein the second conductive material is graphene claim 1 , indium tin oxide (ITO) ...

NONVOLATILE MEMORY ELEMENT AND NONVOLATILE MEMORY DEVICE

A nonvolatile memory element includes: a first electrode; a second electrode; and a variable resistance layer comprising a metal oxide positioned between the first electrode and the second electrode. The variable resistance layer includes: a first oxide layer having a resistivity ρ, on the first electrode; a second oxide layer having a resistivity ρ(ρ<ρ), on the first oxide layer; a third oxide layer having a resistivity ρ(ρ<ρ), on the second oxide layer; and a localized region that is positioned in the third oxide layer and the second oxide layer to be in contact with the second electrode and not to be in contact with the first oxide layer, and is, in resistivity, lower than the third oxide layer and different from the second oxide layer. 1. A variable resistance nonvolatile memory element comprising:a first electrode; a variable resistance layer which comprises a metal oxide positioned between the first electrode and the second electrode, the metal oxide having a resistance state that reversibly changes between a high resistance state and a low resistance state according to a polarity of a voltage pulse applied between the first electrode and the second electrode,', 'wherein the variable resistance layer includes:', {'sub': x', 'x, 'a first metal oxide layer which is positioned on the first electrode, and has a resistivity ρand a composition that is expressed by MOwhere M represents a metal element;'}, {'sub': y', 'x', 'y', 'y, 'a second metal oxide layer which is positioned on the first metal oxide layer, and has a resistivity ρwhere ρ<ρand a composition expressed by NOwhere N represents a metal element;'}, {'sub': z', 'y', 'z', 'z, 'a third metal oxide layer which is positioned on the second metal oxide layer, and has a resistivity ρwhere ρ<ρand a composition expressed by POwhere P represents a metal element; and'}], 'a second electrode; and'}a localized region which is positioned in the third metal oxide layer and the second metal oxide layer to be in contact ...

Memory Cells and Methods of Forming Memory Cells

Some embodiments include memory cells which contain, in order; a first electrode material, a first metal oxide material, a second metal oxide material, and a second electrode material. The first metal oxide material has at least two regions which differ in oxygen concentration relative to one another. One of the regions is a first region and another is a second region. The first region is closer to the first electrode material than the second region, and has a greater oxygen concentration than the second region. The second metal oxide material includes a different metal than the first metal oxide material. Some embodiments include methods of forming memory cells in which oxygen is substantially irreversibly transferred from a region of a metal oxide material to an oxygen-sink material. The oxygen transfer creates a difference in oxygen concentration within one region of the metal oxide material relative to another. 117-. (canceled)18. A method of forming a memory cell , comprising:forming a metal oxide material over a first electrode material;forming an oxygen-sink material over and directly against the metal oxide material;forming a second electrode material over the oxygen-sink material; andtreating the metal oxide material to substantially irreversibly transfer oxygen from a region of the metal oxide material to the oxygen-sink material and thereby subdivide the metal oxide material into at least two regions, with one of the regions nearest the oxygen-sink material being relatively oxygen depleted relative to another of the regions.19. The method of wherein the metal oxide material is selected from the group consisting of aluminum oxide claim 18 , tantalum oxide claim 18 , titanium oxide claim 18 , nickel oxide claim 18 , hafnium oxide and zirconium oxide.20. The method of wherein the oxygen-sink material comprises one or more metals.21. The method of wherein the oxygen-sink material consists of one or more metals.22. The method of wherein the transfer of the ...

Nonvolatile Memory Elements

Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer. 1. A method of forming a nonvolatile memory element comprising:forming a conductive electrode layer;forming a first layer, comprising an oxide of a first element, on the conductive electrode layer;forming a second layer, comprising an oxide of a second element, on the first layer; and a resistive switching layer characterized by a high resistance state and a low resistance state,', {'sub': 's', 'a set voltage Vthat switches the resistive switching layer from the high resistance state to a low resistance state, and'}, {'sub': 'r', 'a reset voltage Vthat switches the resistive switching layer from the low resistance state to the high resistance state;'}], 'processing the conductive electrode layer, the first layer and the second layer such that the combination of the first layer and the second layer comprises'}{'sub': s', 'r, 'wherein at least one of the first element and the second element is selected such that the difference between Vand Vis greater than a predetermined value.'}2. The method of claim 1 , wherein one of the first element or the second element is hafnium claim 1 , and the other of the first element or the second element is niobium.3. The method of claim 1 , further comprising forming a current steering element claim 1 , wherein the conductive electrode layer is formed on the current steering element.4. The method of claim 3 , wherein the current steering element comprises one of ...

NONVOLATILE MEMORY ELEMENT AND NONVOLATILE MEMORY DEVICE

A variable resistance nonvolatile memory element includes a first electrode, a second electrode, and a variable resistance layer including: a first oxide layer including a metal oxide having non-stoichiometric composition and including p-type carriers; a second oxide layer located between and in contact with the first oxide layer and a second electrode and including a metal oxide having non-stoichiometric composition and including n-type carriers; an oxygen reservoir region located in the first oxide layer, having no contact with the first electrode, and having an oxygen content atomic percentage higher than that of the first oxide layer; and a local region located in the second oxide layer, having contact with the oxygen reservoir region, and having an oxygen content atomic percentage lower than that of the second oxide layer. 1. A variable resistance nonvolatile memory element comprising:a first electrode;a second electrode; anda variable resistance layer which is interposed between the first electrode and the second electrode and capable of reversibly switching between a high resistance state and a low resistance state based on a polarity of a voltage applied between the first electrode and the second electrode,wherein the variable resistance layer includes:a first oxide layer comprising a metal oxide having non-stoichiometric composition and including p-type carriers;a second oxide layer located between and in contact with the first oxide layer and the second electrode and comprising a metal oxide having non-stoichiometric composition and including n-type carriers;an oxygen reservoir region located in the first oxide layer, having no contact with the first electrode, and having an oxygen content atomic percentage higher than an oxygen content atomic percentage of the first oxide layer; anda local region located in the second oxide layer, having contact with the oxygen reservoir region, and having an oxygen content atomic percentage lower than an oxygen content ...

RESISTIVE RANDOM ACCESS MEMORY, CONTROLLING METHOD AND MANUFACTURING METHOD THEREFOR

A resistive random access memory (RRAM), a controlling method for the RRAM, and a manufacturing method therefor are provided. The RRAM includes a first electrode layer; a resistance switching layer disposed on the first electrode layer; a diffusion metal layer disposed on the resistance switching layer; and a second electrode layer disposed on the diffusion metal layer, wherein at least one extension electrode is disposed in the resistance switching layer. 1. A resistive random access memory (RRAM) structure , including:a first electrode layer;a resistance switching layer disposed on the first electrode layer, and at least one extension electrode is disposed in the resistance switching layer;a diffusion metal layer disposed on the resistance switching layer; anda second electrode layer disposed on the diffusion metal layer.2. The RRAM structure of claim 1 , wherein the resistance switching layer further includes a switching base part disposed on the first electrode layer claim 1 , and a porous part disposed between the switching base part and the diffusion metal layer claim 1 , wherein the porous part is made of a porous material claim 1 , when an electric field is applied to the diffusion metal layer claim 1 , the diffusion metal layer diffuses into the porous part to form one or more extension electrodes in the porous part.3. The RRAM structure of claim 2 , wherein a porous density of the porous part is in a range between 1% and 10%.4. The RRAM structure of claim 2 , wherein a porous size of the porous part is in a range between 1 nmand 10 nm.5. The RRAM structure of claim 2 , wherein a width of the extension electrode is gradually decreased toward the switching base part.6. The RRAM structure of claim 2 , wherein a thickness of the switching base part is in a range between 2 nm and 10 nm.7. The RRAM structure of claim 2 , wherein a thickness of the porous part is in a range between 2 nm and 10 um.8. The RRAM structure of claim 2 , wherein the diffusion metal ...

NONVOLATILE MEMORY ELEMENT AND METHOD OF MANUFACTURING NONVOLATILE MEMORY ELEMENT

A nonvolatile memory element includes: a first electrode; a second electrode; and a variable resistance layer between the first and second electrodes. The variable resistance layer having a resistance value that reversibly changes according to an electrical signal provided between the electrodes. The variable resistance layer includes a first variable resistance layer and a second variable resistance layer. The first variable resistance layer comprises a first metal oxide. The second variable resistance layer is planar and includes a first part and a second part. The first part comprises a second metal oxide and is planar. The second part comprises an insulator and is planar. The second metal oxide has a lower oxygen deficient degree than that of the first metal oxide. The first and second parts are in contact with different parts of a main surface of the first variable resistance layer which faces the second variable resistance layer. 1. A nonvolatile memory element , comprising:a first electrode;a second electrode; anda variable resistance layer between the first electrode and the second electrode, the variable resistance layer having a resistance value that reversibly changes according to an electrical signal applied between the first electrode and the second electrode,wherein the variable resistance layer includes at least a first variable resistance layer and a second variable resistance layer,the first variable resistance layer comprises a first metal oxide,the second variable resistance layer is planar and includes a first part and a second part, the first part comprising a second metal oxide and being planar, and the second part comprising an insulator and being planar,the second metal oxide has a lower oxygen deficient degree than an oxygen deficient degree of the first metal oxide, andthe first part and the second part of the second variable resistance layer are in contact with different parts of a main surface of the first variable resistance layer, the ...

MEMORY DEVICES HAVING UNIT CELL AS SINGLE DEVICE AND METHODS OF MANUFACTURING THE SAME

In one embodiment, a memory device includes a first electrode layer on a substrate; a data storing layer on the first electrode layer; and a second electrode layer on the data storing layer. At least one of the first and second electrode layers may be formed of a material having a conduction band offset that varies with an applied voltage. One of the first and second electrode layers may be connected to a bit line and the other may be connected to a word line. The first electrode layer may include one of graphene and metastable oxide. The second electrode layer may include one of graphene and metastable oxide. 1. A memory device comprising:a substrate; the second electrode layer being over the first electrode layer,', 'at least one of the first electrode layer and the second electrode layer including a material having a conduction band offset that varies in response to an applied voltage;, 'a first electrode layer and a second electrode layer on the substrate,'}a data storing layer between the first electrode layer and the second electrode layer;a bit line connected to one of the first electrode and the second electrode layers; anda word line connected to the other of the first electrode and the second electrode layers.2. The memory device of claim 1 , wherein the first electrode layer includes one of graphene and a metastable oxide.3. (canceled)4. The memory device of claim 1 , wherein the second electrode layer includes one of graphene and a metastable oxide.5. The memory device of claim 1 , wherein the data storing layer is a data storing layer of a non-volatile memory device.6. (canceled)7. The memory device of claim 1 , wherein the data storing layer is a data storing layer of embedded memory of a logic device.8. The memory device of claim 1 , wherein the conduction band offset of the material of at least one of the first electrode layer and the second electrode layer varies inversely proportional to the applied voltage.9. The memory device of claim 1 , further ...

RESISTIVE MEMORY DEVICE AND MEMORY APPARATUS AND DATA PROCESSING SYSTEM HAVING THE SAME

A resistive memory device includes a first electrode layer, a second electrode layer, and a first variable resistive layer and a second variable resistive layer stacked at least once between the first electrode layer and the second electrode layer. The first variable resistive material layer may include a metal nitride layer having a resistivity higher than that of the first electrode layer or the second electrode layer and less than or equal to that of an insulating material. 1. A resistive memory device , comprising:a first electrode layer;a second electrode layer; andat least one stack of a first variable resistive material layer and a second variable resistive material layer provided between the first electrode layer and the second electrode layer,wherein the first variable resistive material layer includes a metal nitride layer, andwherein a resistivity of the first variable resistive material layer is (i) higher than a resistivity of the first electrode layer or the second electrode layer and (ii) less than or equal to a resistivity of the second variable resistive material layer in a reset state.2. The resistive memory device of claim 1 ,wherein the first variable resistive material layer is formed over the first electrode layer and the second variable resistive material layer is formed over the first variable resistive material layer,wherein the first variable resistive material layer has a stacked structure of a first variable resistive layer and a second variable resistive layer.3. The resistive memory device of claim 2 , wherein the first variable resistive layer includes the metal nitride layer and the second variable resistive layer includes a metal oxide layer.4. The resistive memory device of claim 3 , wherein the metal oxide layer includes any of (i) a material substantially the same as the second variable resistive material layer and having substantially the same composition ratio as the second variable resistive material layer claim 3 , (ii) a ...

Semiconductor Constructions, Memory Cells, Memory Arrays and Methods of Forming Memory Cells

Some embodiments include a construction having oxygen-sensitive structures directly over spaced-apart nodes. Each oxygen-sensitive structure includes an angled plate having a horizontal portion along a top surface of a node and a non-horizontal portion extending upwardly from the horizontal portion. Each angled plate has an interior sidewall where an inside corner is formed between the non-horizontal portion and the horizontal portion, an exterior sidewall in opposing relation to the interior sidewall, and lateral edges. Bitlines are over the oxygen-sensitive structures, and have sidewalls extending upwardly from the lateral edges of the oxygen-sensitive structures. A non-oxygen-containing structure is along the interior sidewalls, along the exterior sidewalls, along the lateral edges, over the bitlines, and along the sidewalls of the bitlines. Some embodiments include memory arrays, and methods of forming memory cells.

ELECTRONIC DEVICE

This technology provides an electronic device. An electronic device in accordance with an implementation of this document includes a semiconductor memory, and the semiconductor memory includes a variable resistance structure including a material having a resistance that is changed by formation or dissipation of conductive filaments; and a Magnetic Tunnel Junction (MTJ) structure inserted in the variable resistance structure and comprising a first magnetic layer having a pinned magnetization direction, a second magnetic layer having a variable magnetization direction, and a tunnel dielectric layer interposed between the first magnetic layer and the second magnetic layer. 120-. (canceled)21. An electronic device , comprising: (1) a first variable resistance structure including a first material having a resistance that is changed by formation or dissipation of one or more conductive filaments or passages in the first material in response to a first control signal applied to the first material;', '(2) a Magnetic Tunnel Junction (MTJ) structure comprising a first magnetic layer having a pinned magnetization direction, a second magnetic layer having a variable magnetization direction, and a tunnel dielectric layer interposed between the first magnetic layer and the second magnetic layer, the MTJ structure being coupled to the first variable resistance structure by having the first magnetic layer in contact with the first variable resistance structure, wherein the MTJ structure exhibits a first MTJ resistance state when magnetizations of the first and second magnetic layers are parallel to each other and a second, different MTJ resistance state when magnetizations of the first and second magnetic layers are anti-parallel to each other; and', '(3) a second variable resistance structure including a second material having a resistance that is changed by formation or dissipation of one or more conductive filaments or passages in the second material in response to a second ...

THREE-TERMINAL NEUROMORPHIC VERTICAL SENSING

A neuromorphic device includes a first electrode layer arranged on a substrate, and an electrolyte layer arranged on the first electrode layer. The electrolyte layer includes a solid electrolyte material. The neuromorphic device further includes an ion permeable, electrically conductive membrane arranged on the electrolyte layer and an ion intercalation layer arranged on the ion permeable, electrically conductive membrane. The neuromorphic device includes a second electrode layer arranged on the ion intercalation layer. 1. A method of fabricating a neuromorphic device , the method comprising:forming an electrolyte layer on a gate electrode;forming a drain electrode on the electrolyte layer, the drain electrode comprising an ion permeable, electrically conductive membrane; andforming a source electrode on the drain electrode.2. The method of claim 1 , wherein the electrolyte layer comprises a solid electrolyte material.3. The method of claim 1 , wherein the electrolyte layer comprises an ion conductive claim 1 , electrically insulating material.4. The method of claim 1 , wherein the electrolyte layer comprises a lithium ion conductive material.5. The method of claim 1 , wherein the electrolyte layer comprises lithium phosphorus oxynitride.6. The method of further comprising forming a matrix layer between the drain electrode and the source electrode.7. The method of claim 6 , wherein the matrix layer comprises lithium cobalt oxide.8. The method of claim 1 , wherein the drain electrode comprises carbon claim 1 , metal claim 1 , or a combination thereof.9. The method of claim 1 , wherein the drain electrode comprises a porous material.10. The method of claim 1 , wherein the drain electrode comprises a patterned material.11. A method of fabricating a neuromorphic device claim 1 , the method comprising:forming an electrolyte layer on a source electrode;forming a drain electrode on the electrolyte layer, the drain electrode comprising an ion permeable, electrically ...

SEMICONDUCTOR MEMORY DEVICE, AND METHOD FOR PRODUCING THE SAME

Provided is a semiconductor memory device (resistance random access memory element) improved in properties. A Ru film is formed as a film of a lower electrode by sputtering, and a Ta film is formed thereonto by sputtering. Next, the Ta film is oxidized with plasma to oxidize the Ta film. In this way, a compound TaOis produced and further Ru is diffused into the compound to form a layer (variable resistance layer) in which Ru is diffused into the compound TaO. Such an incorporation of a metal (such as Ru) into a transition metal oxide TMO (such as TaO) makes it possible to form electron conductive paths additional to filaments to lower the filaments in density and thickness. Thus, the memory element can be restrained from undergoing OFF-fixation, by which the element is not easily lowered in resistance, to be improved in ON-properties. 1. A semiconductor memory device , comprising:a first electrode;a second electrode; anda variable resistance layer arranged between the first and second electrodes;wherein the variable resistance layer comprises an oxide layer of a first metal, and a second metal contained in the oxide layer of the first metal,wherein the first metal is a transition metal; andwherein the second metal is a metal that produces an electronic level inside a band gap of the oxide layer of the first metal.2. The semiconductor memory device according to claim 1 ,{'sub': 2', '5', '2', '2, 'wherein the oxide layer of the first metal comprises at least one selected from the group consisting of TaO, ZrO, and HfO.'}3. The semiconductor memory device according to claim 2 ,wherein the second metal is selected from the group consisting of Ru, Re, Ir, Os, and Nb.4. The semiconductor memory device according to claim 3 ,wherein the content by percentage of the second metal is from 1 to 20% by atom of the first metal in the oxide layer of the first metal.5. The semiconductor memory device according to claim 1 ,wherein the variable resistance layer is over the first ...

ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME

An electronic device includes a semiconductor memory that includes: an inter-layer dielectric layer including a hole over a substrate; a first nitride layer disposed on sidewalls of the hole; a selector disposed in a bottom portion of the hole and over the first nitride layer on the sidewalls of the hole; a stacked structure including a variable resistance pattern disposed over a lower structure including the selector; and a second nitride layer disposed in an upper portion and on sidewalls of the stacked structure. 1. An electronic device comprising a semiconductor memory that comprises:an inter-layer dielectric layer disposed over a substrate and including a hole therein;a first nitride layer disposed over sidewalls of the hole;a selector disposed over the bottom of the hole and over the first nitride layer in the hole;a stacked structure including a variable resistance pattern disposed over a lower structure including the selector; anda second nitride layer disposed over a top surface and sidewalls of the stacked structure.2. The electronic device according to claim 1 , wherein the semiconductor memory further comprises:a contact plug penetrating the inter-layer dielectric layer and contacting the substrate and disposed below the first nitride layer and the selector in the hole.3. The electronic device according to claim 1 , wherein the semiconductor memory further comprises:a conductive line disposed over the substrate and being in contact with the selector.4. The electronic device according to claim 1 , wherein the semiconductor memory further comprises:a conductive line disposed over the substrate; anda contact plug for coupling the conductive line to the selector.5. The electronic device according to claim 1 , wherein the second nitride layer has higher nitrogen density than the first nitride layer.6. The electronic device according to claim 1 , wherein the selector includes one among selection elements such as a Metal Insulator Transition (MIT) layer claim 1 ...

System on chip (SoC) based on neural processor or microprocessor

System on chips (SoCs) based on a microprocessor or a neural processor (e.g., brain-inspired processor) electrically coupled with electronic memory devices and/or optically coupled with an optical memory device, along with embodiment(s) of a building block (an element) of the microprocessor/neural processor, the electronic memory device and the optical memory device are disclosed. It should be noted that a microprocessor can include a graphical processor. 1. A system comprising: a neural processor ,wherein the neural processor comprises memristors, wherein the memristors are arranged in three-dimension (3-D),wherein the neural processor is coupled with an optical memory device by an optical signal to electrical signal converter (OEC) device,wherein the optical signal to electrical signal converter (OEC) device is coupled with an optical device,wherein the optical device comprises(i) a first wavelength for writing,(ii) a second wavelength for erasing,(iii) a third wavelength for reading,wherein the optical memory device is activated by(i) a first wavelength for writing,(ii) a second wavelength for erasing,(iii) a third wavelength for reading,wherein the neural processor is further coupled with an electronic memory device,wherein the electronic memory device comprises a phase change material of a nanoscaled dimension, or a phase transition material of a nanoscaled dimension,wherein the nanoscaled dimension is less than 1000 nanometers in any dimension.2. The system according to claim 1 , wherein the optical signal to electrical signal converter (OEC) device comprises plasmons-polaritons.3. The system according to claim 2 , wherein the plasmons-polaritons are coupled with an interferometer.4. The system according to claim 1 , wherein the optical signal to electrical signal converter (OEC) device comprises a metalized via hole claim 1 , a light source and a photodetector.5. The system according to claim 1 , wherein the optical memory device comprises a phase change ...

System on chip (Soc) based on neural processor or microprocessor

System on chips (SoCs) based on a microprocessor or a neural processor (e.g., brain-inspired processor) electrically coupled with electronic memory devices and/or optically coupled with an optical memory device, along with embodiment(s) of a building block (an element) of the microprocessor/neural processor, the electronic memory device and the optical memory device are disclosed. It should be noted that a microprocessor can include a graphical processor. Furthermore, two or more microprocessors/graphical processors/neural processors (or even a network of microprocessors/graphical processors/neural processors) can be coupled with an optical switch to mimic a (biological) cognitive system. 1. A system comprising: more than one neural processor ,wherein the one neural processor comprises memristors,wherein the one neural processor is coupled with an optical switch,wherein the one neural processor is further coupled with an optical memory device by an optical signal to electrical signal converter (OEC) device,wherein the optical signal to electrical signal converter (OEC) device is coupled with an optical device,wherein the optical device comprises(i) a first wavelength for writing,(ii) a second wavelength for erasing,(iii) a third wavelength for reading,wherein the optical memory device is activated by(i) a first wavelength for writing,(ii) a second wavelength for erasing,(iii) a third wavelength for reading,wherein the one neural processor is further coupled with an electronic memory device,wherein the electronic memory device comprises a phase change material of a nanoscaled dimension, or a phase transition material of a nanoscaled dimension,wherein the nanoscaled dimension is less than 1000 nanometers in any dimension.2. The system according to claim 1 , wherein the optical signal to electrical signal converter (OEC) device comprises plasmons-polaritons.3. The system according to claim 2 , wherein the plasmons-polaritons are coupled with an interferometer.4. The ...

RESISTIVE RANDOM-ACCESS MEMORY WITH PROTECTED SWITCHING LAYER

Resistive RAM (RRAM) devices having increased reliability and related manufacturing methods are described. Greater reliability of RRAM cells over time can be achieved by avoiding direct contact of metal electrodes with the device switching layer. 1. A resistive random-access memory (RRAM) device comprising:an intermediate first layer that includes a switching region with added switching species of at least one different material;a device layer of a semiconductor material at one side of the intermediate layer and includes a first doped region, and a substrate layer of a semiconductor material at an opposite side of the first layer and comprises a second doped region;electrodes that are spaced from said switching region and contact said first and second doped regions; andwherein said switching region is configured to switch between higher and lower resistivity states in response to a switching voltage without having been conditioned with a higher, breakdown voltage.2. The RRAM device of claim 1 , further including one or more active electronic circuits formed in one or both of said device and substrate layers.3. The RRAM device of claim 2 , in which said one or more active electronic circuits are formed only at said device layer.4. The RRAM device of claim 2 , in which said one or more active electronic circuits are formed only at said substrate layer.5. The RRAM device of claim 2 , in which at least one of said electrodes has a contact that extends through said device layer and said intermediate layer to said second doped region but is spaced from said switching region.6. The RRAM device of claim 2 , in which said intermediate layer and said device and substrate layers comprise a single chip and said switching region and first and second doped regions are configured as plural claim 2 , individually addressed resistive memory elements.7100. The RRAM device of claim 6 , in which said resistive memory elements are characterized by a lifetime of million or more switching ...

RESISTIVE RANDOM-ACCESS MEMORY (RRAM) CELL WITH RECESSED BOTTOM ELECTRODE SIDEWALLS

Various embodiments of the present application are directed towards an integrated circuit comprising a resistive random-access memory (RRAM) cell with recessed bottom electrode sidewalls to mitigate the effect of sidewall plasma damage. In some embodiments, the RRAM cell includes a lower electrode, a data storage element, and an upper electrode. The lower electrode includes a pair of recessed bottom electrode sidewalls respectively on opposite sides of the lower electrode. The data storage element overlies the lower electrode and includes a pair of storage sidewalls. The storage sidewalls are respectively on the opposite sides of the lower electrode, and the recessed bottom electrode sidewalls are laterally spaced from and laterally between the storage sidewalls. The upper electrode overlies the data storage element. 1. A method for forming an integrated circuit comprising a memory cell , the method comprising:forming a lower conductive layer on a substrate;forming a data storage layer overlying the lower conductive layer;forming an upper conductive layer overlying the data storage layer;patterning the upper conductive layer, the data storage layer, and the lower conductive layer to respectively form an upper electrode, a data storage element, and a lower electrode stacked on the substrate, wherein the patterning forms sidewall defects in storage sidewalls of the data storage element; andperforming an etch into the lower electrode to laterally recess electrode sidewalls of the lower electrode respectively relative to neighboring ones of the storage sidewalls.2. The method according to claim 1 , wherein the patterning comprises:performing a second etch into the data storage layer and the lower conductive layer to respectively form the data storage element and the lower electrode, wherein the storage sidewalls are respectively aligned with the electrode sidewalls upon completion of the second etch.3. The method according to claim 2 , wherein the second etch is ...

Morphology control of ultra-thin MeOx layer

A nonvolatile memory device contains a resistive switching memory element with improved device switching performance and life and methods for forming the same. The nonvolatile memory device has a first layer on a substrate, a resistive switching layer on the first layer, and a second layer. The resistive switching layer is disposed between the first layer and the second layer and the resistive switching layer comprises a material having the same morphology as the top surface of the first layer. A method of forming a nonvolatile memory element in a ReRAM device includes forming a resistive switching layer on a first layer and forming a second layer, so that the resistive switching layer is disposed between the first layer and the second layer. The resistive switching layer comprises a material formed with the same morphology as the top surface of the first layer. 1. A device comprising:a first layer operable as a first electrode; wherein the second layer is configured to switching between a low resistive state and a high resistive state,', 'wherein the second layer directly interfaces the first layer,', 'wherein a morphology of the first layer is same as a morphology of at least a portion of the second layer directly interfacing the first layer, and', 'wherein the morphology of the first layer is one of crystalline, polycrystalline, or amorphous; and, 'a second layer operable as a resistive switching layer'}a third layer operable as a second electrode,wherein the second layer is disposed between the first layer and the third layer.2. The device of claim 1 , wherein the morphology of the first layer is crystalline.3. The device of claim 1 , wherein the second layer has a thickness of less than 5 nanometers.4. The device of claim 3 , wherein the second layer has the thickness of between about 2 nanometers and 3 nanometers.5. The device of claim 3 , wherein the morphology of the second layer is substantially the same throughout the thickness of the second layer.6. The ...

SELF-SELECTING PCM DEVICE NOT REQUIRING A DEDICATED SELECTOR TRANSISTOR

A Zinc Oxide (ZnO) layer deposited using Atomic Layer Deposition (ALD) over a phase-change material forms a self-selected storage device. The diode formed at the ZnO/GST interface shows both rectification and storage capabilities within the PCM architecture. 1a first conductive line;a second conductive line;a dielectric between the first and second conductive lines;a first barrier between the first conductive line and the dielectric and contacting the first conductive line and the dielectric;a second barrier between the second conductive line and the dielectric and contacting the second conductive line and the dielectric;a first memory cell having an oxide-based material in contact with a phase change memory (PCM) material to form a diode junction in the PCM material, the oxide-based material contacting the first conductive line;a first material arranged in a stack with the oxide-based material and the PCM material;a second memory cell having an oxide-based material in contact with a PCM material to form a diode junction in the PCM material, the oxide-based material contacting the second conductive line; anda second material arranged in a stack with the oxide-based material and the PCM material of the second memory cell.. A storage device comprising: Floating gate memories are self selected devices where the selecting functions and the storage functions are realized in a unique device. However, this type of nonvolatile memory is being replaced by Phase Change Memory (PCM) for the next generation due to favorable write speeds, smaller cell sizes, simpler circuitries and a fabrication compatibility with the Complementary Metal-Oxide-Semiconductor (CMOS) process. Current PCM uses a dedicated selection device, usually a MOS or a BJT transistor, to select the memory cell for reading and writing. The selection device requires additional masks and process complexity, and therefore, improvements are needed in the selection device for selecting the memory cell.It will be ...

Diffusion Barrier Layer for Resistive Random Access Memory Cells

Provided are resistive random access memory (ReRAM) cells having diffusion barrier layers formed from various materials, such as beryllium oxide or titanium silicon nitrides. Resistive switching layers used in ReRAM cells often need to have at least one inert interface such that substantially no materials pass through this interface. The other (reactive) interface may be used to introduce and remove defects from the resistive switching layers causing the switching. While some electrode materials, such as platinum and doped polysilicon, may form inert interfaces, these materials are often difficult to integrate. To expand electrode material options, a diffusion barrier layer is disposed between an electrode and a resistive switching layer and forms the inert interface with the resistive switching layer. In some embodiments, tantalum nitride and titanium nitride may be used for electrodes separated by such diffusion barrier layers. 1. A method comprising: 'wherein the first layer is operable as a first electrode;', 'forming a first layer over a substrate,'} wherein the second layer is operable as a variable resistance layer and is configured to switch between a low resistive state and a high resistive state, and', 'wherein the second layer comprises a metal oxide; and, 'forming a second layer over the first layer,'} 'wherein the third layer is operable as a diffusion barrier and is configured to prevent the defects from entering and leaving the second layer; and', 'forming a third layer over the second layer,'} 'wherein the fourth layer is operable as a second electrode.', 'forming a fourth layer over the third layer,'}2. The method of claim 1 , wherein the third layer comprises one of BeO claim 1 , TaSiN claim 1 , a Ni—Ti alloy claim 1 , RuTiN claim 1 , an Ir—Al alloy claim 1 , (Ba claim 1 ,Sr)RuO claim 1 , or IrO.3. The method of claim 1 , wherein the third layer comprises BeO.4. The method of claim 1 , wherein the third layer comprises TaSiN.5. The method of claim ...

Memory cell selector and method of operating memory cell

Embodiments provide a selector device for selecting a memory cell. The selector device includes a first electrode; a second electrode; and a switching layer sandwiched between the first electrode and the second electrode. The switching layer includes at least one metal rich layer and at least one chalcogenide rich layer. The metal rich layer includes at least one of a metal or a metal compound, wherein metal content of the metal rich layer is greater than 50 at. %. The chalcogenide content of the chalcogenide rich layer is greater than 50 at. %.

ELECTRONIC DEVICE INCLUDING A SEMICONDUCTOR MEMORY AND METHOD FOR FABRICATING THE SAME

The disclosed technology provides semiconductor memory devices and applications in electronic devices. In one implementation, an electronic device includes a semiconductor memory that includes a first contact plug over a substrate; an interlayer dielectric layer located over the first contact plug and having a hole which exposes at least a portion of the first contact plug; a first electrode layer formed along a sidewall and a bottom surface of the hole to be in contact with the first contact plug; a variable resistance layer over the first electrode layer and structured to include (1) a first portion that extends along the sidewall of the hole in a direction perpendicular to the substrate and exhibits a variable resistance and (2) a second portion that is parallel to the bottom surface of the hole and does not exhibit a variable resistance, and a second electrode layer formed over the variable resistance layer. 1. An electronic device comprising a semiconductor memory , wherein the semiconductor memory includes:a substrate;a first contact plug formed over the substrate;an interlayer dielectric layer located over the first contact plug and having a hole which exposes at least a portion of the first contact plug;a first electrode layer formed along a sidewall and a bottom surface of the hole to be in contact with the first contact plug;a variable resistance layer formed over the first electrode layer and structured to include (1) a first portion that extends along the sidewall of the hole in a direction perpendicular to the substrate and exhibits a variable resistance and (2) a second portion that is parallel to the bottom surface of the hole and does not exhibit a variable resistance; anda second electrode layer formed over the variable resistance layer.2. The electronic device of claim 1 , wherein the second portion includes a structure identical to the first portion but are added with impurities which cause a loss of the variable resistance.3. The electronic ...

Formation of correlated electron material (cem) device via dopant deposition and anneal

Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) switch. In particular embodiments, formation of a CEM switch may comprise depositing metal layers, such layers of a transition metal, over a conductive substrate. Dopant layers may subsequently be deposited on the layers of the transition metal, followed by annealing of the layers of transition metal and dopant layers. Responsive to annealing, dopant from the dopant layers may diffuse into the one or more layers of transition metal, thereby forming a CEM.

METHODS OF FORMING RESISTIVE MEMORY ELEMENTS

A resistive memory element comprises a first electrode, an active material over the first electrode, a buffer material over the active material and comprising longitudinally extending, columnar grains of crystalline material, an ion reservoir material over the buffer material, and a second electrode over the ion reservoir material. A memory cell, a memory device, an electronic system, and a method of forming a resistive memory element are also described. 1. A method of forming a resistive memory element , comprising:forming a switchable resistivity material over an electrode, the switchable resistivity material comprising one or more of a metal oxide and a chalcogenide;{'sub': x', 'x', 'x', 'x', 'y', 'x', 'y', 'x', 'y', 'x', 'y', 'x', 'y', 'x', 'y', 'x', 'y', 'x', 'y', 'x', 'y, 'forming a buffer material over the switchable resistivity material, the buffer material comprising longitudinally extending, columnar grains of one or more of TiN, TaN, WN, TiNC, TaNC, WNC, TiNB, TaNB, WNB, TiNSi, TaNSi, and WNSi;'}forming a material over the buffer material, the material comprising a chalcogen and one or more of Cu, Ag, and Al; andforming another electrode over the material.2. The method of claim 1 , wherein forming a switchable resistivity material over an electrode comprises forming one or more of SiO claim 1 , AlO claim 1 , HfO claim 1 , HfSiO claim 1 , ZrO claim 1 , ZrSiO claim 1 , TiO claim 1 , TiSiO claim 1 , TaO claim 1 , TaSiO claim 1 , NbO claim 1 , NbSiO claim 1 , VO claim 1 , VSiO claim 1 , WO claim 1 , WSiO claim 1 , MoO claim 1 , MoSiO claim 1 , CrO claim 1 , and CrSiOover the electrode.3. The method of claim 1 , wherein forming a buffer material over the switchable resistivity material comprises forming the buffer material to further comprise one or more of O claim 1 , S claim 1 , Se claim 1 , and Te.4. The method of claim 1 , wherein forming a buffer material over the switchable resistivity material comprises forming the buffer material to have a thickness ...

Memory Devices and Memory Device Forming Methods

Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage. 161-. (canceled)62. A memory device comprising:a wordline;a bitline;a memory element between the wordline and the bitline; anda diode between the wordline and the bitline, the diode comprising a at least three dielectric layers and conductive diode material, the at least three dielectric layers between the bitline and the conductive diode material.63. The memory device of further comprising more than three dielectric layers.64. The memory device of wherein at least two of the at least three dielectric layers are different dielectric materials.65. The memory device of wherein the at least three dielectric layers are different dielectric materials.66. The memory device of wherein the bitline comprises a metal and wherein one dielectric layer of the at least three dielectric layers most proximate the bitline comprises a metal oxide claim 62 , the metal of the metal oxide being different from the metal of the bitline.67. The memory device of wherein the at least three dielectric layers comprise one or more of the following compositions: aluminum nitride claim 62 , aluminum oxide claim 62 , hafnium oxide claim 62 , ...

ReRAM Cells Including TaXSiYN Embedded Resistors

Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A ReRAM cell includes an embedded resistor and a resistive switching layer connected in series with this resistor. The resistor is configured to prevent over-programming of the cell by limiting electrical currents through the resistive switching layer. Unlike the resistive switching layer, which changes its resistance in order to store data, the embedded resistor maintains a substantially constant resistance during operation of the cell. The embedded resistor is formed from tantalum nitride and silicon nitride. The atomic ratio of tantalum and silicon may be specifically selected to yield resistors with desired densities and resistivities as well as ability to remain amorphous when subjected to various annealing conditions. The embedded resistor may also function as a diffusion barrier layer and prevent migration of components between one of the electrodes and the resistive switching layer. 1. A resistive random access memory cell comprising:a first conductive layer operable as an electrode;a second conductive layer operable as an electrode;a resistive switching layer disposed between the first electrode and the second electrode; anda constant-resistance layer operable as an embedded resistor disposed between the resistive switching layer and the second electrode,{'sub': X', 'Y, 'wherein the embedded resistor comprises TaSiN such that both X>0 and Y>0;'}wherein an atomic ratio of X to Y is between 0.5:1 and 15:1.2. The resistive random access memory cell of claim 1 , wherein the embedded resistor directly interfaces the resistive switching layer or the second electrode.3. The resistive random access memory cell of claim 1 , wherein X and Y are selected to reduce crystallization of TaSiN during annealing.4. The resistive random access memory cell of claim 1 , wherein an atomic ratio of X to Y is between 3:1 and 5:1.5. The resistive random access memory cell of claim 1 , ...

Resistive switching by breaking and re-forming covalent bonds

A variable resistance layer in a resistive non-volatile memory (ReRAM) cell changes its resistance in response to an applied signal by breaking and re-forming covalent bonds (e.g., in sub-stoichiometric silicon oxide). Resistivity decreases with increasing density of broken “dangling” bonds. When an electric field is applied, more dangling bonds are created, forming a filament of defects through which charge carriers can tunnel through the covalent layer. Passing a high current through the dangling-bond filament causes localized heating that re-forms the bonds. Optionally, an ionic oxide or nitride layer in contact with the covalent switching layer may serve as an oxygen source for thermal re-oxidation during the heating. 1. A device , comprising:a substrate;a first layer formed over the substrate, the first layer operable as a first electrode;a second layer formed over the first layer, the second layer operable as a second electrode; anda third layer formed between the first layer and the second layer;wherein the third layer reversibly changes resistance responsive to a first write signal or a second write signal;wherein a first write signal breaks covalent bonds in the third layer; andwherein a second write signal re-forms broken covalent bonds in the third layer.2. The device of claim 1 , wherein the third layer comprises silicon and at least one of oxygen or nitrogen.3. The device of claim 1 , wherein a portion of the third layer near an interface is heated to between 500C and 900C by the second write signal claim 1 , as calculated from thermal conductivities of the interface materials claim 1 , a reset pulse current claim 1 , a reset pulse length claim 1 , and a cross-sectional area of a conductive filament at the interface.4. The device of claim 1 , further comprising a fourth layer formed between the first layer and the second layer;wherein a dielectric constant of the fourth layer is greater than or equal to 9.5. The device of claim 4 , wherein the fourth ...

CURRENT-LIMITING ELECTRODES

A resistive-switching memory (ReRAM cell) has a current-limiting electrode layer that combines the functions of an embedded resistor, an outer electrode, and an intermediate electrode, reducing the thickness of the ReRAM stack and simplifying the fabrication process. The materials include compound nitrides of a transition metal and one of aluminum, boron, or silicon. In experiments with tantalum silicon nitride, peak yield in the desired resistivity range corresponded to 24 at % silicon and 32 at % nitrogen, believed to optimize the trade-off between inhibiting TaSiformation and minimizing nitrogen diffusion. A binary metal nitride may be formed at one or more of the interfaces between the current-limiting electrode and neighboring layers such as metal-oxide switching layers.

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device including first lines and second lines overlapping and intersecting each other, variable resistance memory elements disposed at intersections between the first lines and the second lines, and switching elements disposed between the variable resistance memory elements and the first lines. At least one of the switching elements includes first and second chalcogenide compound layers, and conductive nano-dots disposed between the first and second chalcogenide compound layers. 1. A semiconductor memory device , comprising:first lines and second lines overlapping and intersecting each other;variable resistance memory elements disposed at intersections between the first lines and the second lines; andswitching elements disposed between the variable resistance memory elements and the first lines, first and second chalcogenide compound layers; and', 'conductive nano-dots disposed between the first and second chalcogenide compound layers., 'wherein at least one of the switching elements comprises2. The semiconductor memory device of claim 1 , wherein the first and second chalcogenide compound layers comprise nitrogen claim 1 , the first chalcogenide compound layer including a nitrogen concentration greater than a nitrogen concentration of the second chalcogenide compound layer.3. The semiconductor memory device of claim 1 , wherein the first and second chalcogenide compound layers comprise an amorphous material.4. The semiconductor memory device of claim 1 , wherein the first chalcogenide compound layer has a thickness less than a thickness of the second chalcogenide compound layer.5. The semiconductor memory device of claim 1 , further comprising:first electrodes disposed between the first lines and the switching elements;second electrodes disposed between the second lines and the variable resistance memory elements; andthird electrodes disposed between the switching elements and the variable resistance memory elements.6. The semiconductor ...

METHOD OF MAKING A RESISTIVE RANDOM ACCESS MEMORY DEVICE

The disclosed technology generally relates to semiconductor devices, and relates more particularly to resistive random access memory devices and methods of making the same. In one aspect, a method of forming a resistive random access memory cell of a random access memory device includes forming a first electrode and forming a resistive switching material comprising an oxide of a pnictogen element by atomic layer deposition. The method additionally includes forming a metallic layer comprising the pnictogen element by atomic layer deposition (ALD). The resistive switching material is interposed between the first electrode and the metallic layer. 1. A method of forming a resistive random access memory device , comprising forming a resistive random access memory cell , wherein forming the resistive random access memory cell comprises:providing a first electrode;forming a resistive switching material comprising an oxide of a pnictogen element by atomic layer deposition; andforming a metallic layer comprising the pnictogen element by atomic layer deposition,wherein the resistive switching material is interposed between the first electrode and the metallic layer.2. The method of claim 1 , wherein forming the resistive switching material comprises depositing the resistive switching material by thermal atomic layer deposition.3. The method of claim 1 , wherein the pnictogen is Sb.4. The method of claim 3 , wherein the resistive switching material comprises SbO.5. The method of claim 3 , wherein depositing the metallic layer comprises using precursors comprising one of Sb halides claim 3 , Sb alkoxides claim 3 , Sb alkylamides and Sb alkylsilyls.6. The method of claim 5 , wherein depositing the metallic layer comprises using an Sb alkylsilyl as a first precursor in combination with a second precursor comprising one of Sb halides claim 5 , Sb alkoxides and Sb alkylamides.7. The method of claim 3 , wherein forming the resistive switching material comprises using precursors ...

NONVOLATILE MEMORY DEVICE

A structure of nonvolatile memory device includes a substrate, having a logic device region and a memory cell region. A first gate structure for a low-voltage transistor is disposed over the substrate in the logic device region, wherein the first gate structure comprises a single-layer polysilicon. A second gate structure for a memory cell is disposed over the substrate in the memory cell region. The second gate structure includes a gate insulating layer on the substrate. A floating gate layer is disposed on the gate insulating layer, wherein the floating gate layer comprises a first polysilicon layer and a second polysilicon layer as a stacked structure. A memory dielectric layer is disposed on the floating gate layer. A control gate layer is disposed on the memory dielectric layer, wherein the control gate layer and the single-layer polysilicon are originated from a preliminary polysilicon layer in same. 1. A structure of nonvolatile memory device , comprising:a substrate, having a logic device region and a memory cell region;a first gate structure for a low-voltage transistor, disposed over the substrate in the logic device region, wherein the first gate structure comprises a single-layer polysilicon; and a gate insulating layer on the substrate;', 'a floating gate layer on the gate insulating layer, wherein the floating gate layer comprises a first polysilicon layer and a second polysilicon layer as a stacked structure;, 'a second gate structure for a memory cell, disposed over the substrate in the memory cell region, wherein the second gate structure comprisesa memory dielectric layer on the floating gate layer; anda control gate layer on the memory dielectric layer, wherein the control gate layer and the single-layer polysilicon are originated from a preliminary polysilicon layer in same.2. The structure of nonvolatile memory device of claim 1 , wherein a thickness of the control gate layer is substantially equal to a thickness of the single-layer polysilicon ...

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FORMING THE SAME

A semiconductor memory device includes a substrate defined with a first cell region, a slimming region extending from the first cell region in a first direction and a second cell region extending from the slimming region in the first direction; first and second electrode structures each including electrodes which are stacked on the substrate, and disposed to be separated from each other in a second direction crossing with the first direction, with a slit interposed therebetween; and a plurality of step-shaped holes disposed in the slimming region along the first direction, and respectively formed in the first and second electrode structures. Each of the step-shaped holes includes first step structures which face each other in the first direction, are symmetrical to each other and are separated by the slit and second step structures which face each other in the second direction and are symmetrical to each other.

LIGAND SELECTION FOR TERNARY OXIDE THIN FILMS

Embodiments of the present invention are directed to forming a ternary compound using a modified atomic layer deposition (ALD) process. In a non-limiting embodiment of the invention, a first precursor and a second precursor are selected. The first precursor includes a first metal and a first ligand. The second precursor includes a second metal and a second ligand. The second ligand is selected based on the first ligand to target a second metal uptake. A substrate is exposed to the first precursor during a first pulse of an ALD cycle and the substrate is exposed to the second precursor during a second pulse of the ALD cycle, the second pulse occurring after the first pulse. The substrate is exposed to a third precursor (e.g., an oxidant) during a third pulse of the ALD cycle. The ternary compound can include a ternary oxide film. 1. A method of depositing a compound , the method comprising:selecting a first precursor comprising a first metal and a first ligand;selecting a second precursor comprising a second metal and a second ligand, the second metal different than the first metal, the second ligand selected based on the first ligand to target a second metal uptake;exposing a substrate to the first precursor during a first pulse of an atomic layer deposition (ALD) cycle;exposing the substrate to the second precursor during a second pulse of the ALD cycle, the second pulse occurring after the first pulse; andexposing the substrate to a third precursor during a third pulse of the ALD cycle.2. The method of further comprising selecting a precursor partial pressure claim 1 , gas flow claim 1 , and pulse time for at least one of the first pulse and the second pulse based on the target second metal uptake.3. The method of claim 1 , wherein the compound comprises a ternary oxide and the third precursor is an oxidant.4. The method of claim 1 , wherein during the first pulse the first metal of the first precursor adsorbs onto a surface of the substrate.5. The method of claim ...

RRAM CELL STRUCTURE WITH CONDUCTIVE ETCH-STOP LAYER

The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode. 1. A resistive random access memory (RRAM) device comprising:a semiconductor substrate;a metal interconnect structure disposed within a low-k dielectric layer and disposed over the semiconductor substrate;a conductive etch-stop layer (CESL) abutting an upper surface of the metal interconnect structure;a bottom electrode structure over the CESL;a variable resistance dielectric structure over the bottom electrode structure;a top electrode structure over the variable resistance dielectric structure;sidewall spacers about outer sidewalls of the top electrode structure; andwherein outer sidewalls of the bottom electrode structure are spaced apart by a first distance, and outer sidewalls of the top electrode structure are spaced apart by a second distance which is less than the first distance;wherein the CESL is a transitional metal nitride layer having an etch-selectivity that differs from an etch-selectivity of the bottom electrode structure.2. The RRAM device of claim 1 , wherein the bottom electrode structure is a single conductive electrode layer.3. The RRAM device of claim 1 , ...

NONVOLATILE MEMORY APPARATUS INCLUDING RESISTIVE-CHANGE MATERIAL LAYER

A nonvolatile memory apparatus includes a first electrode, a second electrode separated from the first electrode, a resistive-change material layer provided between the first electrode and the second electrode and configured to store information due to a resistance change caused by an electrical signal applied through the first electrode and the second electrode, and a diffusion prevention layer provided between the first electrode and the resistive-change material layer and/or between the second electrode and the resistive-change material layer and including a two-dimensional (2D) material having a monolayer thickness of about 0.35 nm or less. 2. The nonvolatile memory apparatus of claim 1 , wherein the diffusion prevention layer is a graphene diffusion prevention layer comprising graphene.3. The nonvolatile memory apparatus of claim 2 , wherein the graphene diffusion prevention layer has a thickness of about 0.5 nm to about 20 nm.4. The nonvolatile memory apparatus of claim 2 , wherein the graphene diffusion prevention layer has a grain size of about 1 nm to about 20 nm.5. The nonvolatile memory apparatus of claim 2 , wherein the graphene diffusion prevention layer has a grain size of about 20 nm or more.6. The nonvolatile memory apparatus of claim 1 , wherein the two-dimensional (2D) material has a monolayer thickness of about 0.35 nm or less.7. The nonvolatile memory apparatus of claim 1 , wherein the blocking layer comprises one selected from among a metal claim 1 , a nitride claim 1 , and an oxide.8. The nonvolatile memory apparatus of claim 7 , wherein the blocking layer comprises one selected from among Ru claim 7 , TiN claim 7 , TaN claim 7 , TiAlN claim 7 , AlO claim 7 , InO claim 7 , ZnO claim 7 , AlZnO claim 7 , InZnO claim 7 , and RuAlO.9. The nonvolatile memory apparatus of claim 1 , wherein the diffusion prevention layer is a boron nitride (BN) diffusion prevention layer comprising BN.10. The nonvolatile memory apparatus of claim 1 , wherein the first ...

NONVOLTILE RESISTANCE MEMORY AND ITS OPERATION THEREOF

A memory cell and the associated array circuits are disclosed. The memory array circuit includes a plurality of memory units, in which each of the memory units includes a storage device and a field-effect transistor. The storage device includes a top electrode, a bottom electrode and an oxide-based dielectric layer. The top electrode is formed by metal or metallic oxide dielectrics and connected to a word line. The bottom electrode is formed by metal, and the oxide-based dielectric layer is placed between the top electrode and the bottom electrode. The field-effect transistor includes a gate terminal connected to the bottom electrode, a source terminal connected to a ground line, and a drain terminal connected to a bit line. The resistance of the storage device is configured to be adjusted according to a first voltage applied to the word line and a second voltage applied to the bit line. 1. A memory array circuit , comprising:a plurality of memory units, wherein each of the memory units comprises: a top electrode formed by metal or metallic oxide compound or metallic-semiconductor compound connected to a word line;', 'a bottom electrode formed by metal or metallic oxide compound or metallic-semiconductor compound; and', 'an oxide-based dielectric formed between the top electrode and the bottom electrode; and, 'a storage device, comprising a gate terminal connected to the bottom electrode of the storage device;', 'a source terminal connected to a ground line; and', 'a drain terminal connected to a bit line;', 'a channel between the source terminal, the drain terminal, and the gate terminal;', 'wherein the resistance or conductivity of the storage device is configured to be adjusted according to the differences of voltages between the corresponding word lines, the corresponding bit lines, or the corresponding ground lines connected to memory units., 'a field-effect transistor, comprising2. The memory array circuit of claim 1 , wherein the storage device is configured ...

MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

A memory device having an array area and a periphery area is provided. The memory device includes a substrate, an isolation layer formed in the substrate, a first doped region formed on the isolation layer in the array area, a second doped region formed on the first doped region, a metal silicide layer formed on the second doped region, and a metal silicide oxide layer formed on the metal silicide layer. 1. A memory device having an array area and a periphery area , comprising:a substrate;an isolation layer formed in the substrate;a first doped region formed on the isolation layer in the array area;a second doped region formed on the first doped region;a first metal silicide layer formed on the second doped region;a metal silicide oxide layer formed on the first metal silicide layer;a P-well formed in the substrate in the periphery area;a N-well formed adjacent to the P-well in the periphery area;two first electrodes formed in the P-well;a first gate oxide layer formed on the P-well;two second electrodes formed in the N-well;a second gate oxide layer formed on the N-well;a first doped polysilicide layer formed on the first gate oxide layer;a second doped polysilicide layer formed on the second gate oxide layer; anda plurality of second metal silicide layers formed on the first doped polysilicide layer and the second doped polysilicide layer;wherein portions of the isolation layer is formed between the P-well and the N-well.2. The memory device according to claim 1 , further comprising:a plurality of first metal silicide layers; anda spacer formed between two of the first metal silicide layers.3. The memory device according to claim 1 , further comprising:an undoped region formed between the first doped region and the second doped region.45-. (canceled)6. The memory device according to claim 1 , further comprising:a first extension portion connected with one of the first electrodes;a second extension portion connected with another one of the first electrodes,a third ...

MEMRISTOR STRUCTURE WITH A DOPANT SOURCE

A memristor including a dopant source is disclosed. The structure includes an electrode, a conductive alloy including a conducting material, a dopant source material, and a dopant, and a switching layer positioned between the electrode and the conductive alloy, wherein the switching layer includes an electronically semiconducting or nominally insulating and weak ionic switching material. A method for fabricating the memristor including a dopant source is also disclosed. 1. A memristor , including:an electrode;a conductive alloy including a conducting material, a dopant source material, and a dopant; anda switching layer positioned between the electrode and the conductive alloy, wherein the switching layer includes an electronically semiconducting or nominally insulating and weak ionic switching material;{'sub': 'x', 'wherein the switching layer comprises a binary oxide M1O, where M is selected from the group consisting of transition metal oxides and metal oxides.'}2. The memristor of claim 1 , wherein the switching layer is a single layer structure claim 1 , a bi-layer structure or a multi-layer structure.3. The memristor of wherein the switching layer or a part thereof is to form a switching channel.4. The memristor of claim 1 , wherein the electrode and the conducting material include a material selected from the group consisting of aluminum claim 1 , copper claim 1 , gold claim 1 , molybdenum claim 1 , niobium claim 1 , palladium claim 1 , platinum claim 1 , ruthenium claim 1 , ruthenium oxide claim 1 , silver claim 1 , tantalum claim 1 , tantalum nitride claim 1 , titanium nitride claim 1 , tungsten claim 1 , and tungsten nitride.5. The memristor of claim 1 , wherein:the switching layer includes an oxide and the dopant is oxygen.6. The memristor of claim 1 , wherein the dopant source material is soluble in the conducting material claim 1 , the dopant is soluble in the dopant source material claim 1 , and the free energy of formation of a compound including the ...

RESISTIVE MEMORY STRUCTURE

A resistive memory structure including at least one reactive layer, at least one electrode, and at least one resistance-changing material is provided. The reactive layer extends along a first direction and a second direction. The electrode extends at least along a third direction, wherein the first direction, the second direction, and the third direction are different from each other. At least part of the resistance-changing material is disposed between the reactive layer and the electrode. When ions diffuse from the resistance-changing material to the reactive layer or from the reactive layer to the resistance-changing material, resistance of the resistance-changing material changes. 1. A resistive memory structure comprising:at least one reactive layer extending along a first direction and a second direction;at least one electrode extending at least along a third direction, wherein the first direction, the second direction, and the third direction are different from each other; andat least one resistance-changing material, at least part of the resistance-changing material being disposed between the reactive layer and the electrode, wherein when ions diffuse from the resistance-changing material to the reactive layer or from the reactive layer to the resistance-changing material, resistance of the resistance-changing material changes.2. The resistive memory structure according to claim 1 , wherein the reactive layer is a reactive metal layer.3. The resistive memory structure according to claim 2 , wherein a material of the reactive metal layer comprises Ti claim 2 , Ta claim 2 , or a combination thereof.4. The resistive memory structure according to wherein the at least one reactive layer is included among a plurality of metal layers.5. The resistive memory structure according to claim 4 , wherein sidewalls of the metal layers are oxidized.6. The resistive memory structure according to claim 4 , wherein a material of the metal layers comprises TiN claim 4 , TaN ...

RESISTANCE RANDOM ACCESS MEMORY DEVICE

Provided is a resistance random access memory device comprising: a first electrode; a second electrode; and a metallic oxide formed between the first electrode and the second electrode. Particularly, provided is a resistance random access memory device wherein the metallic oxide comprises a first crystal grain and a second crystal grain which differ from each other in crystallographic orientation and form a boundary area; wherein a surface is intervened between the first crystal grain and the second crystal grain in the boundary area, the surface having a surface index corresponding to a surface crystallographically consisting only of oxygen among the crystal faces of the metallic oxide; and wherein the boundary area is a surface in which an electrically conductive path is formed when voltage is applied between the first electrode and the second electrode. 1. A resistive random access memory , comprising:a first electrode;a second electrode; anda metal oxide formed between the first electrode and the second electrode,wherein the metal oxide comprises a first crystal grain and a second crystal grain having different crystal orientations and forming a boundary region therebetween; among crystal planes of the metal oxide, a plane having a plane index corresponding to a plane crystallographically consisting of oxygen is interposed between the first crystal grain and the second crystal grain in the boundary region; and the boundary region is a plane in which a conductive path is formed when voltage is applied between the first electrode and the second electrode.2. The resistive random access memory according to claim 1 , wherein the metal oxide is strontium titanate (SrTiO) having a perovskite structure; the first crystal grain has a (111) plane preferred orientation with respect to a reference plane formed by contact between a layer of the metal oxide and any one of the first electrode and the second electrode; and the second crystal grain has a (110) plane preferred ...

Non-Volatile Resistance-Switching Thin Film Devices

Disclosed herein are resistive switching devices having, e.g., an amorphous layer comprised of an insulating aluminum-based or silicon-based material and a conducting material. The amorphous layer may be disposed between two or more electrodes and be capable of switching between at least two resistance states. Circuits and memory devices including resistive switching devices are also disclosed, and a composition of matter involving an insulating aluminum-based or an silicon-based material and a conducting material. Also disclosed herein are methods for switching the resistance of an amorphous material. 1. A resistive device , comprising: a composition comprising:', 'an electrically insulating aluminum-containing composition; and', 'an electrically conducting composition, the electrically conducting composition comprising from about 1 percent to about 40 percent by molar percentage of the amorphous layer; and, 'at least one amorphous layer, each amorphous layer comprisingat least two electrodes in electrical contact with the amorphous layer.2. The resistive device of claim 1 , wherein the distance between at least one pair of electrodes is from about 2 to about 60 nanometers.3. The resistive device of claim 1 , comprising a plurality of said amorphous layers claim 1 , said layers comprising similar or different compositions.4. The resistive device of claim 1 , wherein the electrically conducting composition comprises a metal M claim 1 , wherein M comprises Pt claim 1 , Pd claim 1 , Ni claim 1 , W claim 1 , Au claim 1 , Ag claim 1 , Cu claim 1 , Al claim 1 , Rh claim 1 , Re claim 1 , Ir claim 1 , Os claim 1 , Ru claim 1 , Nb claim 1 , Ti claim 1 , Zr claim 1 , Hf claim 1 , V claim 1 , Ta claim 1 , Cr claim 1 , Mo claim 1 , Mn claim 1 , Tc Fe claim 1 , Co claim 1 , Zn claim 1 , Ga claim 1 , In claim 1 , Cd claim 1 , Hg claim 1 , Tl claim 1 , Sn claim 1 , Pb claim 1 , Sb claim 1 , Bi claim 1 , Be claim 1 , Mg claim 1 , Ca claim 1 , Sr claim 1 , Ba claim 1 , Li claim 1 , ...

SELECTOR DEVICES

Disclosed herein are selector devices and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, and a selector material between the first electrode and the second electrode. The selector material may include a dielectric material and a conductive dopant. 1. A selector device , comprising:a first electrode;a second electrode; anda selector material between the first electrode and the second electrode, wherein the selector material comprises a dielectric material and a conductive dopant, wherein the dielectric material comprises a chalcogenide.2. The selector device of claim 1 , wherein the chalcogenide comprises at least one of silicon and tellurium.3. The selector device of claim 2 , wherein the chalcogenide comprises germanium.4. The selector device of claim 1 , wherein the chalcogenide comprises a group IV or group VI element.5. The selector device of claim 1 , wherein the conductive dopant includes platinum claim 1 , silver claim 1 , gold claim 1 , tantalum claim 1 , copper claim 1 , cobalt claim 1 , tungsten claim 1 , ruthenium claim 1 , palladium claim 1 , or carbon.6. The selector device of claim 1 , wherein the conductive dopant has a work function less than 4.5 electron volts.7. The selector device of claim 1 , wherein the conductive dopant has a first ion migration velocity claim 1 , the dielectric material has a second ion migration velocity claim 1 , and the second ion migration velocity is greater than the first ion migration velocity by a factor of at least 10.8. The selector device of claim 1 , wherein the selector device has a threshold voltage between 0.4 volts and 2.5 volts claim 1 , and the selector device has a holding voltage between 0.1 volts and 2.5 volts.9. The selector device of claim 1 , further comprising a getter layer between the first electrode and the selector material.10. A memory cell claim 1 , comprising:a storage element; anda selector device coupled to the storage ...

SWITCHING BLOCK CONFIGURATION BIT COMPRISING A NON-VOLATILE MEMORY CELL

A configuration bit for a switching block routing array comprising a non-volatile memory cell is provided. By way of example, the configuration bit and switching block routing array can be utilized for a field programmable gate array, or other suitable circuit(s), integrated circuit(s), application specific integrated circuit(s), electronic device or the like. The configuration bit can comprise a switch that selectively connects or disconnects a node of the switching block routing array. A non-volatile memory cell connected to the switch can be utilized to activate or deactivate the switch. In one or more embodiments, the non-volatile memory cell can comprise a volatile resistance switching device connected in serial to a gate node of the switch, configured to trap charge at the gate node to activate the switch, or release the charge at the gate node to deactivate the switch. 1a non-volatile switch comprising an input node, an output node and a control gate, the input node connected to a first conductive line of a switching block routing array and the output node connected to a second conductive line of the switching block routing array;a volatile switch having a first contact and a second contact, the second contact is conductively connected to the control gate of the non-volatile switch; anda program circuit configured to selectively provide a voltage from a voltage source to the first contact of the volatile switch.. A circuit, comprising: This application for patent is a continuation of and claims priority to U.S. application Ser. No. 15/469,179, titled SWITCHING BLOCK CONFIGURATION BIT COMPRISING A NON-VOLATILE MEMORY CELL and filed Mar. 24, 2017, which is hereby incorporated by reference herein in its entirety and for all purposes.U.S. application Ser. No. 14/717,185 entitled “NON-VOLATILE MEMORY CELL UTILIZING VOLATILE SWITCHING TWO TERMINAL DEVICE AND A MOS TRANSISTOR” and filed May 20, 2015, U.S. application Ser. No. 14/588,185 entitled “SELECTOR DEVICE FOR ...

Memory cells, memory cell arrays, methods of using and methods of making

A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.

TUNABLE RESISTIVE ELEMENT

A tunable resistive element, comprising a first terminal, a second terminal, a dielectric layer and an intercalation layer. The dielectric layer and the intercalation layer is arranged between the first terminal and the second terminal. The dielectric layer is configured to form conductive filaments of oxygen vacancies on application of an electric field. The intercalation layer is configured to undergo a topotactic transition comprising an oxygen intercalation in combination with a change in the resistivity of the intercalation layer. A related memory device and a related neuromorphic network comprise resistive memory elements as memory cells and synapses respectively and a corresponding design structure. 1. A tunable resistive element , comprisinga first terminal;a second terminal;a dielectric layer; andan intercalation layer, whereinthe dielectric layer and the intercalation layer are arranged between the first terminal and the second terminal;the dielectric layer is configured to form conductive filaments of oxygen vacancies; andthe intercalation layer is configured to undergo a topotactic transition comprising an oxygen intercalation in combination with a change in the resistivity of the intercalation layer.2. The tunable resistive element of claim 1 , wherein the dielectric layer and the intercalation layer are arranged in series between the first terminal and the second terminal.3. The tunable resistive element of claim 1 , wherein the intercalation layer is configured to provide a decreasing resistance with an increasing oxygen level.4. The tunable resistive element of claim 1 , wherein the tunable resistive element is configured to at least:provide a first resistance state on application of an electrical reset-pulse to the resistive element, the first resistance state being characterized by a low oxygen level in the intercalation layer and a fully oxidized dielectric layer.5. The tunable resistive element of claim 1 , wherein the tunable resistive element ...

COMPLEMENTARY METAL OXIDE HETEROJUNCTION MEMORY DEVICES AND METHODS RELATED THERETO

A resistive memory device is disclosed. The memory device comprises one or mo re metal oxide layers. An oxygen vacancy or ion concentrations of the one or more metal oxide layer is controlled in the formation and the operation of the memory device to provide robust memory operation. 1. A memory device comprises:a first metal layer;a first metal oxide layer coupled to the first metal layer;a second metal oxide layer coupled to the first metal oxide layer; anda second metal layer coupled to the second metal oxide layer.2. The memory device of claim 1 , wherein a Gibbs free energy for the formation of the first metal oxide layer is lower than the Gibbs free energy for the formation of the second metal oxide layer.3. The memory device of claim 1 , further comprising a barrier layer claim 1 , coupled to the first metal oxide and wherein the second metal oxide layer is coupled to the barrier layer.4. The memory device of claim 1 , wherein a oxygen content of the second metal oxide is oxygen-rich.5. The memory device of claim 1 , wherein a oxygen content of the second metal oxide is oxygen-deficient.6. The memory device of claim 1 , wherein the first metal oxide layer has a first thickness that is three to one hundred time greater than a second thickness of the second metal oxide.7. The memory device of wherein the first metal oxide layer is characterized by a first state having a first resistance and a second state having a second resistance and the metal oxide layer is characterized by a third state having a third resistance state and a fourth state having a fourth resistance claim 1 , and wherein the first resistance is higher than the second resistance and the third resistance is higher than the fourth resistance.8. A method of forming a memory device comprising:providing a substrate having an upper surface and an opposing lower surface;depositing a first metal layer over the upper surface of the substrate;depositing a first metal oxide layer over the first metal layer ...

Resistive Random Access Memory Cells Having METAL ALLOY Current Limiting layers

Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from alloys of transition metals. Some examples of such alloys include chromium containing alloys that may also include nickel, aluminum, and/or silicon. Other examples include tantalum and/or titanium containing alloys that may also include a combination of silicon and carbon or a combination of aluminum and nitrogen. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature processing. In some embodiments, the breakdown voltage of a current limiting layer is at least about 8V. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layers while maintaining their performance. 1. A resistive random access memory cell comprising:an electrode layer;a current limiting layer, the current limiting layer comprising chromium, the current limiting layer having a breakdown voltage of at least 8V and a resistivity of at least 1 Ohm-cm in a direction normal to the current limiting layer; anda resistive switching layer comprising a resistive switching material.2. The resistive random access memory cell of claim 1 , wherein the current limiting layer comprises one of NiCr claim 1 , AlNiCr claim 1 , SiCr claim 1 , SiCrO claim 1 , or SiCrWN.3. The resistive random access memory cell of claim 1 , wherein a concentration of chromium in the chromium containing layer is between about 25 and 75 atomic percent.4. The resistive random access memory cell of claim 1 , wherein the current limiting layer has a resistivity of less than 0.001 Ohm-cm in a direction parallel to the current limiting layer.5. The resistive random access memory cell of claim 1 , wherein the current limiting layer extends across multiple resistive random access memory cells and is ...

Resistive-Switching Nonvolatile Memory Elements

Nonvolatile memory elements including resistive switching metal oxides may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer. 1. A device comprising: 'the metal nitride comprising a most prevalent metal,', 'a first conductive layer comprising metal nitride,'}a second conductive layer; and [ 'the non-stoichiometric metal oxide comprising the most prevalent metal,', 'the resistive switching layer comprising a non-stoichiometric metal oxide,'}, 'the first sub-layer and the second sub-layer having different compositions.', 'the resistive switching layer comprising a first sub-layer and a second sub-layer,'}], 'a resistive switching layer disposed between the first conductive layer and the second conductive layer,'}2. The device of claim 1 , wherein the first conductive layer forms an Ohmic contact with the resistive switching layer.3. The device of claim 2 , wherein the second conductive layer forms a Schottky contact with the resistive switching layer.4. The device of claim 1 , wherein the first conductive layer and the second conductive layer have different composition.5. The device of claim 1 , wherein one of the first conductive layer or the second conductive layer comprises a noble material.6. The device of claim 1 , wherein the ...

MEMORY DEVICE

A memory device, containing a first electrode, a second electrode and an oxide layer arranged between the first electrode and the second electrode, is produced. The oxide layer has a first zone and a second zone, with the first zone surrounding or being located on either side of the second zone, with the minimum distance d separating the two electrodes on the second zone of the oxide layer being less than the minimum distance d separating the two electrodes on the first zone of the oxide layer. 125.-. (canceled)26. A memory device , comprising:a first electrode;a second electrode; andan oxide layer arranged between the first electrode and the second electrode,wherein the oxide layer has a first zone and a second zone,the first zone surrounds or is located on either side of the second zone,{'b': 2', '1, 'a minimum distance d separating the first and second electrodes on the second zone is less than a minimum distance d separating the first and second electrodes on the first zone,'}a ratio between a surface area of at least one electrode of the first and second electrodes facing the second zone and a surface area of the at least one electrode of the first and second electrodes facing the first zone is from 0.0001 to 0.5.27. The device according to claim 26 ,{'b': 2', '1, 'wherein a ratio between the minimum distance d and the minimum distance d is from 0.2 to 0.7.'}28. The device according to claim 26 ,wherein at least one electrode of the first and second electrodes is in contact with the second zone andwherein a ratio between a surface area through which the at least one electrode faces the second zone and a surface area through which the at least one electrode faces the first zone is from 0.0001 to 0.5.29. The device according to claim 26 ,wherein at least one of the first and second electrodes is a non-inert electrode able to react with the oxide layer to create oxygen vacancies or defects in said oxide layer when a voltage is applied to the device.30. The device ...

RESISTIVE MEMORY ELEMENT BASED ON OXYGEN-DOPED AMORPHOUS CARBON

The present invention is notably directed to a resistive memory element comprising a resistively switchable material coupled to two conductive electrodes, wherein the resistively switchable material is an amorphous compound comprising carbon and oxygen. Moreover, the carbon and oxygen stoichiometric ratio can be within a range of 1:0.30 to 1:0.80. 1. A resistive memory element comprising:a resistively switchable material coupled to two conductive electrodes, wherein the resistively switchable material is an amorphous compound comprising carbon and oxygen.2. The resistive memory element according to claim 1 , wherein claim 1 , the resistive memory element comprises a C:O stoichiometric ratio range of 1:0.30 to 1:0.80.3. The resistive memory element according to claim 1 , wherein a ratio of C—C sp2 bonds to C—C sp3 bonds in the resistively switchable material in its pristine state is less than 0.4.4. The resistive memory element according to claim 3 , wherein the resistively switchable material is doped with one or more of the following elements: Si claim 3 , H and N.5. The resistive memory element according to claim 1 , wherein a first one of the two conductive electrodes comprises a first material in contact with the resistively switchable material claim 1 , the second one of the two electrodes comprises a second material in contact with the resistively switchable material claim 1 , and wherein the first material and the second material have different oxidation potentials claim 1 , and wherein the first material and the second material are: W and Pt claim 1 , graphite or graphene and Pt claim 1 , graphite or graphene and W claim 1 , or W and Al claim 1 , respectively.6. The resistive memory element according to claim 1 , wherein an average thickness of the resistively switchable material is between 2 and 30 nm.7. The resistive memory element according to claim 1 , wherein the resistively switchable material claim 1 , and the two conductive electrodes have a layered ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a bottom metal layer, a resistive random access memory (ReRAM) cell structure, and an upper metal layer. The bottom metal layer is located above the substrate. The ReRAM cell structure is formed on the bottom metal layer. The ReRAM cell structure includes a bottom electrode, a memory cell layer, a top electrode, and a spacer. The memory cell layer is formed on the bottom electrode. The top electrode is formed on the memory cell layer. The spacer is formed on two sides of the bottom electrode, the memory cell layer and the top electrode. The upper metal layer is electrically connected to and directly contacting the top electrode. 1. A semiconductor device , comprising:a bottom metal layer located above the substrate; a bottom electrode;', 'a memory cell layer formed on the bottom electrode;', 'a top electrode formed on the memory cell layer; and', 'a spacer formed on two sides of the bottom electrode, the memory cell layer and the top electrode; and, 'a resistive random access memory (ReRAM) cell structure formed on the bottom metal layer, comprisingan upper metal layer electrically connected to and directly contacting the top electrode.2. The semiconductor device according to claim 1 , further comprising:an inter-metal dielectric formed on the bottom metal layer, wherein the ReRAM cell structure and the upper metal layer are formed within the inter-metal dielectric.3. The semiconductor device according to claim 2 , wherein the inter-metal dielectric has a thickness of 2500-3500 Å.4. The semiconductor device according to claim 2 , further comprising:a via formed in the inter-metal dielectric and located at a lateral side of the ReRAM cell structure, wherein the upper metal layer is electrically connected to the bottom metal layer through the via.5. The semiconductor device according to claim 4 , wherein the via has a height of 1000-1500 Å.6. The ...

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

According to an embodiment, a semiconductor memory device comprises first wiring lines, second wiring lines, and first variable resistance elements. The first wiring lines are arranged in a first direction and have as their longitudinal direction a second direction intersecting the first direction. The second wiring lines are arranged in the second direction and have the first direction as their longitudinal direction. The first variable resistance elements are respectively provided at intersections of the first wiring lines and the second wiring lines. In addition, this semiconductor memory device comprises a first contact extending in a third direction that intersects the first direction and second direction and having one end thereof connected to the second wiring line. The other end and a surface intersecting the first direction of this first contact are covered by a first conductive layer. 1a plurality of first wiring lines arranged in a first direction and having as their longitudinal direction a second direction intersecting the first direction;a plurality of second wiring lines arranged in the second direction and having the first direction as their longitudinal direction;a plurality of first variable resistance elements respectively provided at intersections of the first wiring lines and the second wiring lines; anda first contact extending in a third direction intersecting the first direction and second direction, one end of the first contact being connected to the second wiring line,the other end of the first contact and a surface intersecting the first direction of the first contact being covered by a first conductive layer.. A semiconductor memory device, comprising: This application is a continuation of and claims the benefit of priority under 35 U.S.C. § 120 from U.S. application Ser. No. 15/791,514 filed Oct. 24, 2017, which is a continuation of U.S. application Ser. No. 15/077,026 filed Mar. 22, 2016 (now U.S. Pat. No. 9,812,502 issued Nov. 7, 2017 ...

SPHERICAL COMPLEMENTARY RESISTANCE SWITCHABLE FILLER AND NONVOLATILE COMPLEMENTARY RESISTANCE SWITCHABLE MEMORY COMPRISING THE SAME

A resistance-switchable material containing: an insulating support; and a complementary resistance switchable filler dispersed in the insulating support, wherein the complementary resistance switchable filler has a spherical core-shell structure containing: a spherical conductive core containing a conductive material; and an insulating shell formed on the surface of the core and containing an insulating material. The resistance-switchable material is capable of exhibiting complementary resistive switching characteristics with improved reliability and stability as symmetrical uniform filament current paths are formed in respective resistive layers adjacent to two electrodes with the conductive core of the complementary resistance-switchable filler at the center due to the electric field control effect by the spherical complementary resistance-switchable filler 1. A resistance-switchable material comprising:an insulating support; anda complementary resistance switchable filler dispersed in the insulating support, whereinthe complementary resistance switchable filler has a spherical core-shell structure comprising:a spherical conductive core comprising a conductive material; andan insulating shell formed on the surface of the core and comprising an insulating material.2. The resistance-switchable material according to claim 1 , wherein the spherical conductive core comprises one or more selected from a spherical carbon particle claim 1 , a spherical gold particle claim 1 , a spherical platinum particle claim 1 , a spherical silver particle and a spherical copper particle.3. The resistance-switchable material according to claim 1 , wherein the spherical conductive core has a diameter of 20-100 nm.4. The resistance-switchable material according to claim 1 , wherein the insulating shell has a thickness of 10-50 nm.5. The resistance-switchable material according to claim 1 , wherein the insulating shell comprises one or more selected from NiO claim 1 , SiO claim 1 , TiO ...

TIGHTLY INTEGRATED 1T1R ReRAM FOR PLANAR TECHNOLOGY

A semiconductor structure includes an oxide ReRAM co-integrated with a drain region of a field effect transistor (FET). The oxide ReRAM has a tip region defined by a pointed cone that contacts a faceted upper surface of the drain region of the FET. Such a tip region enhances the electric field of the oxide ReRAM and thus helps to control forming of the conductive filament of the oxide ReRAM. 110-. (canceled)11. A method of forming a semiconductor structure , the method comprising:providing a sacrificial gate structure on a surface of a semiconductor substrate, wherein a first dielectric spacer and a second dielectric spacer laterally surround the sacrificial gate structure;forming a source region and a drain region in the semiconductor substrate and on opposite sides of the sacrificial gate structure, wherein the source region and the drain region have faceted sidewall surfaces;performing a self-limiting etch of the drain region to provide a faceted upper surface to the drain region, wherein an interlayer dielectric (ILD) material layer protects the source region during the performing of the self-limiting etch; andforming elements of an oxide resistive random access memory (ReRAM) device in contact with the faceted upper surface of the drain region.12. The method of claim 11 , further comprising replacing claim 11 , after the forming of the elements of the ReRAM device claim 11 , the sacrificial gate structure with a functional gate structure claim 11 , wherein the functional gate structure comprises a gate dielectric material portion and a gate conductor portion.13. The method of claim 12 , further comprising forming a source contact structure contacting the source region claim 12 , a gate contact structure contacting the gate conductor portion claim 12 , and a ReRAM contact structure contacting a top electrode of the ReRAM device.14. The method of claim 11 , wherein the forming of the elements of ReRAM device comprises forming a resistive switching layer and a top ...

Resistive Memory Device and Method for Fabricating the Same

An embodiment of the present invention provides a resistive memory device and a method for fabricating the same. The resistive memory device includes a substrate and a plurality of memory cells spaced with each other over the substrate, each memory cell including a lower electrode, a resistive layer and an upper electrode, wherein the lower electrode is disposed over the substrate, the resistive layer is disposed over the lower electrode and the upper electrode is disposed over the resistive layer, and the resistive layer includes a resistive material portion and at least one doped resistive portion doped with an element for adjusting a resistance state. In the resistive memory device and the method for fabricating the same according to the present invention, since the resistive layer is not formed of single resistive material, during a set operation of the resistive memory device, a plurality of stable resistance states are produced according to various applied voltages, so that a storage density of the resistive memory device is increased without increasing a volume of the resistive memory device. 143212122. A resistive memory device , wherein the resistive memory device comprises a substrate () and a plurality of memory cells spaced with each other on the substrate , each memory cell comprising a lower electrode () , a resistive layer () and an upper electrode () , wherein the lower electrode is disposed over the substrate , the resistive layer is disposed over the lower electrode and the upper electrode is disposed over the resistive layer , and the resistive layer comprises a resistive material portion () and at least one doped resistive portion () doped with an element for adjusting a resistance state.2. The resistive memory device of claim 1 , wherein the resistive material portion is formed of one of silicon oxide SiOx claim 1 , germanium oxide GeOx claim 1 , titanium oxide TaOx and hafnium oxide HfOx.3. The resistive memory device of claim 1 , wherein the ...

NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME

A nonvolatile memory device and a method of operating the same are provided. The nonvolatile memory device may include a memory cell array having a vertical stack-type structure, a control logic, and a bit line. The memory cell array may include memory cells that each include corresponding portions of a semiconductor layer and a resistance change layer. The control logic, in a read operation, may be configured to apply a first voltage to a non-select memory cell and a second voltage to a non-select memory cell. The first voltage turns on current only in the semiconductor layer portion of the non-select memory cell. The second voltage turns on current in both the semiconductor layer and resistance change layer portions of the select memory cell. The bit line may be configured to apply a read voltage to the select memory cell during the read operation. 1. A memory device comprising:a memory cell array having a vertical stack-type structure including a semiconductor layer and a resistance change layer, the memory cell array including a plurality of memory cells that each include a corresponding portion of the semiconductor layer and a corresponding portion of the resistance change layer; and the control logic, in a read operation, being configured to apply a first voltage to a non-select memory cell and the first voltage has a level to turn on current only in the corresponding portion of the semiconductor layer of the non-select memory cell,', 'the control logic, during the read operation, being configured to apply a second voltage to a select memory cell and the second voltage has a level to turn on current in both the corresponding portion of the semiconductor layer and the corresponding portion of the resistance change layer of the select memory cell, and', 'the non-select memory cell and the select memory cell being among the plurality of memory cells of the memory cell array; and, 'a control logic,'}a bit line connected to the memory cell array, the bit line being ...

MEMRISTORS WITH DOPANT-COMPENSATED SWITCHING

A memristor with dopant-compensated switching, the memristor having a bottom electrode, a top electrode, and an active region sandwiched between the bottom electrode and the top electrode. The active region is made up of an electrically insulating material and an electrically conducting material. The insulating material includes compensating dopants to partially or fully compensate for native dopants in the insulating material. Methods for making the memristor are also disclosed. 1. A memristor with dopant-compensated switching , the memristors including:a bottom electrode;a top electrode; andan active region sandwiched between the bottom electrode and the top electrode, the active region comprising an electrically insulating material and an electrically conducting material,wherein the insulating material includes compensating dopants to partially or fully compensate for native dopants in the insulating material.2. The memristor of wherein the conductive material comprises a sub-oxide and the insulating material comprises a full oxide or wherein the conductive material comprises a sub-nitride and the insulating material comprises a full nitride.3. The memristor of wherein the compensating dopants are acceptor dopants.4. The memristor of wherein the compensating dopants are selected from metals that have one or more valences below that of the metal comprising the metal oxide or the metal nitride.5. The memristor of wherein the compensating dopants are donor dopants.6. The memristor of wherein the compensating dopants are selected from metals that have one or more valences above that of the metal comprising the metal oxide or the metal nitride.7. The memristor of wherein the active region comprises a relatively thick conductive material and a relatively thin insulating material sandwiched between the bottom electrode and the top electrode.8. The memristor of wherein the active region comprises a matrix of the insulting layer in which is dispersed the electrically ...

Memory device

According to one embodiment, a memory device includes a first electrode, a second electrode, a first layer, and a second layer. The first electrode includes a first element. The first layer is provided between the first electrode and the second electrode. The first layer includes at least one of an insulator or a first semiconductor. The second layer is provided between the first layer and the second electrode. The second layer includes a first region and a second region. The second region is provided between the first region and the second electrode. The second region includes a second element. A standard electrode potential of the second element is lower than a standard electrode potential of the first element. A concentration of nitrogen in the first region is higher than a concentration of nitrogen in the second region.

METHODS FOR RESISTIVE RAM (ReRAM) PERFORMANCE STABILIZATION VIA DRY ETCH CLEAN TREATMENT

The performance of a ReRAM structure may be stabilized by utilizing a dry chemical gas removal (or cleaning) process to remove sidewall residue and/or etch by-products after etching the ReRAM stack layers. The dry chemical gas removal process decreases undesirable changes in the ReRAM forming voltage that may result from such sidewall residue and/or etch by-products. Specifically, the dry chemical gas removal process may reduce the ReRAM forming voltage that may otherwise result in a ReRAM structure that has the sidewall residue and/or etch by-products. In one embodiment, the dry chemical gas removal process may comprise utilizing a combination of HF and NHgases. The dry chemical gas removal process utilizing HF and NHgases may be particularly suited for removing halogen containing sidewall residue and/or etch by-products. 1. A method of processing a resistive random access memory (ReRAM) device , comprising:patterning a multi-layer ReRAM stack on a substrate, wherein a sidewall material is formed on sidewalls of the multi-layer ReRAM stack; andimproving a forming voltage of the ReRAM device by removing the sidewall material from the sidewalls of the multi-layer ReRAM stack through the use of a dry chemical gas removal process.2. The method of claim 1 , wherein the improving the forming voltage of the ReRAM device decreases the forming voltage of the ReRAM device by 10% or more as compared to not removing the sidewall material from the sidewalls of the multi-layer ReRAM stack.3. The method of claim 2 , wherein the forming voltage of the ReRAM device decreases by at least 15%.4. The method of claim 2 , wherein the sidewall material contains a halogen.5. The method of claim 4 , wherein the dry chemical gas removal process comprises using HF gas and/or NHgas.6. The method of claim 5 , wherein the dry chemical gas removal process comprises using HF gas and NHgas.7. The method of claim 1 , wherein the patterning the multi-layer ReRAM stack on the substrate comprises ...

PHASE CHANGE MEMORY STRUCTURES AND DEVICES

A phase change memory (PCM) cell can include a PCM layer. A first electrode and a second electrode disposed on opposite sides of the PCM layer. The first electrode, the second electrode, or both includes a metal ceramic composite material layer disposed between an upper barrier layer and a lower barrier layer and wherein the metal ceramic composite material layer provides a corresponding electrode with an electrical resistivity of from 10 mOhm-cm to 1000 mOhm-cm. 1. A phase change memory (PCM) cell , comprising:a PCM layer comprising a PCM material; anda first electrode and a second electrode disposed on opposite sides of the PCM layer,wherein the first electrode, the second electrode, or both includes a metal ceramic composite material layer disposed between an upper barrier layer and a lower barrier layer.2. The PCM cell of claim 1 , wherein the PCM material comprises germanium claim 1 , antimony claim 1 , tellurium claim 1 , silicon claim 1 , nickel claim 1 , gallium claim 1 , arsenic claim 1 , silver claim 1 , tin claim 1 , gold claim 1 , lead claim 1 , bismuth claim 1 , indium claim 1 , selenium claim 1 , oxygen claim 1 , sulphur claim 1 , nitrogen claim 1 , carbon claim 1 , or a combination thereof.3. The PCM cell of claim 1 , further comprising a first lamina layer disposed between the PCM layer and the first electrode.4. The PCM cell of claim 3 , wherein the first lamina layer comprises a refractory metal claim 3 , a refractory metal nitride claim 3 , a refractory metal silicide claim 3 , a refractory metal carbide claim 3 , a refractory metal boride claim 3 , or a combination thereof.5. The PCM cell of claim 1 , further comprising a second lamina layer disposed between the PCM layer and the second electrode.6. The PCM cell of claim 5 , wherein the second lamina layer comprises a refractory metal claim 5 , a refractory metal nitride claim 5 , a refractory metal silicide claim 5 , a refractory metal carbide claim 5 , a refractory metal boride claim 5 , or a ...

MEMORY CELLS HAVING INCREASED STRUCTURAL STABILITY

A memory cell can include a top lamina layer, a bottom lamina layer, and a phase change material (PCM) layer between the top lamina layer and the bottom lamina layer. The PCM layer can have a top surface in direct contact with the top lamina layer and a bottom surface in direct contact with the bottom lamina layer. The top surface of the 1. A memory cell , comprising:a top lamina layer;a bottom lamina layer; anda phase change material (PCM) layer between the top lamina layer and the bottom lamina layer, the PCM layer having a top surface in direct contact with the top lamina layer and a bottom surface in direct contact with the bottom lamina layer,wherein the top surface of the PCM layer and the bottom surface of the PCM layer have a width ratio of from 0.8:1 to 1.05:1.2. The memory cell of claim 1 , wherein the top lamina layer and the bottom lamina layer comprise substantially the same material or combination of materials.3. The memory cell of claim 1 , wherein the top surface of the PCM layer and the bottom surface of the PCM layer have a width ratio of from 0.85:1 to 1.02:1.4. The memory cell of claim 1 , wherein the top surface of the PCM layer and the top lamina layer have a width ratio of from 0.7:1 to 1.05:1.5. The memory cell of claim 1 , wherein the bottom surface of the PCM layer and the bottom lamina layer have a width ratio of from 0.6:1 to 1.05:1.6. The memory cell of claim 1 , wherein the PCM layer has a substantially trapezoidal shaped cross-section.7. The memory cell of claim 1 , wherein a top lamina layer is wider than the top surface of the PCM layer forming an upper recess between a lateral edge of the top lamina layer and a lateral edge of the PCM layer at the top surface.8. The memory cell of claim 7 , wherein the upper recess has a depth of less than 5 nanometers (nm).9. The memory cell of claim 1 , wherein the bottom lamina layer is wider than the bottom surface of the PCM layer forming a lower recess between the lateral edge of the bottom ...

RESISTIVE RANDOM-ACCESS MEMORY (RRAM) CELL WITH RECESSED BOTTOM ELECTRODE SIDEWALLS

Various embodiments of the present application are directed towards an integrated circuit comprising a resistive random-access memory (RRAM) cell with recessed bottom electrode sidewalls to mitigate the effect of sidewall plasma damage. In some embodiments, the RRAM cell includes a lower electrode, a data storage element, and an upper electrode. The lower electrode includes a pair of recessed bottom electrode sidewalls respectively on opposite sides of the lower electrode. The data storage element overlies the lower electrode and includes a pair of storage sidewalls. The storage sidewalls are respectively on the opposite sides of the lower electrode, and the recessed bottom electrode sidewalls are laterally spaced from and laterally between the storage sidewalls. The upper electrode overlies the data storage element. 1. An integrated circuit comprising a memory cell , wherein the memory cell comprises:a lower electrode comprising a pair of electrode sidewalls, wherein the electrode sidewalls are respectively on opposite sides of the lower electrode;a data storage element overlying the lower electrode and comprising a pair of storage sidewalls, wherein the storage sidewalls are respectively on the opposite sides of the lower electrode, and wherein the electrode sidewalls are laterally spaced from and laterally between the storage sidewalls; andan upper electrode overlying the data storage element.2. The integrated circuit according to claim 1 , wherein the lower electrode has a first width claim 1 , and wherein the data storage element has a second width greater than the first width.3. The integrated circuit according to claim 1 , wherein the electrode sidewalls comprise a first electrode sidewall and a second electrode sidewall claim 1 , wherein the data storage element extends laterally and continuously from the first electrode sidewall to the second electrode sidewall in a first direction claim 1 , and wherein the data storage element further extends laterally and ...

A Switching Resistor And Method Of Making Such A Device

A switching resistor has a low resistance state and a high resistance state. The switching resistor comprises a dielectric layer disposed between a first electrode and a second electrode. The switching resistor further comprises a textured boundary surface between the first electrode and the dielectric layer. The textured boundary surface promotes the formation of a conductive pathway in the dielectric layer between the first electrode and the second electrode. 139-. (canceled)40. A switching resistor having a low resistance state and a high resistance state , comprising a dielectric layer disposed between a first electrode and a second electrode , wherein the dielectric is an oxide of silicon , and a textured boundary surface between the first electrode and the dielectric layer , wherein the dielectric layer includes column structures extending from the textured boundary surface between the first electrode and the dielectric layer towards the second electrode , wherein the textured boundary surface is configured to promote the formation of a conductive pathway in the dielectric layer , at the edge of a column structure , between the first electrode and the second electrode for intrinsic resistance switching.41. The switching resistor of claim 40 , wherein the textured boundary surface comprises a predetermined texture pattern.42. The switching resistor of claim 40 , wherein the textured boundary surface comprises random texturing.43. The switching resistor of claim 40 , wherein the first electrode and second electrodes are formed of metal or silicon.44. The switching resistor of claim 40 , wherein the dielectric layer is formed on the first electrode.45. The switching resistor of claim 40 , wherein at least one of the column structures is configured to form said conductive pathway in response to the application of an electroforming voltage to the switching resistor.46. The switching resistor of claim 45 , wherein boundaries between the column structures have a ...

PHASE CHANGE MEMORY STRUCTURES AND DEVICES

A phase change memory (PCM) cell () includes a PCM layer (), a metal ceramic composite material layer (), and a carbon nitride (CNX) electrode layer () disposed between the PCM material layer and the metal ceramic composite material layer. The CNX electrode layer can have an electrical resistivity at room temperature of from about 1 mOhm-cm to about 2000 mOhm-cm and an electrical resistivity at 650° C. of from about 1 mOhm-cm to about 100 mOhm-cm. 186-. (canceled)87. A phase change memory (PCM) cell , comprising:a PCM material layer;a metal ceramic composite material layer; and{'sub': 'X', 'an amorphous carbon nitride (CN) electrode layer disposed between the PCM material layer and the metal ceramic composite material layer.'}88. The PCM cell of claim 87 , wherein the PCM material layer comprises germanium claim 87 , antimony claim 87 , tellurium claim 87 , silicon claim 87 , nickel claim 87 , gallium claim 87 , arsenic claim 87 , silver claim 87 , tin claim 87 , gold claim 87 , lead claim 87 , bismuth claim 87 , indium claim 87 , yttrium claim 87 , selenium claim 87 , boron claim 87 , scandium claim 87 , oxygen claim 87 , sulphur claim 87 , nitrogen claim 87 , carbon claim 87 , or a combination thereof claim 87 , and the metal ceramic composite material layer comprises tungsten silicon nitride claim 87 , tantalum silicon nitride claim 87 , niobium silicon nitride claim 87 , molybdenum silicon nitride claim 87 , titanium silicon nitride claim 87 , carbon nitride claim 87 , tungsten carbon nitride claim 87 , doped alpha silicon claim 87 , doped alpha germanium claim 87 , or a combination thereof.89. The PCM cell of claim 87 , wherein the metal ceramic composite material layer comprises a metal silicon nitride claim 87 , the amorphous CNelectrode layer is at least 50% amorphous claim 87 , at least 70% amorphous claim 87 , or at least 90% amorphous claim 87 , and the amorphous CNelectrode layer has an electrical resistivity at room temperature of from about 1 mOhm-cm ...

Resistive Random Access Memory Cells Having Doped Current Limiting layers

Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from doped metal oxides and/or nitrides. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature annealing. In some embodiments, the breakdown voltage of a current limiting layer may be at least about 8V. Some examples of such current limiting layers include titanium oxide doped with niobium, tin oxide doped with antimony, and zinc oxide doped with aluminum. Dopants and base materials may be deposited as separate sub-layers and then redistributed by annealing or may be co-deposited using reactive sputtering or co-sputtering. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layer while maintaining their performance. 1. A resistive random access memory cell comprising:a first electrode layer;a second electrode layer;a third layer operable as a current limiter, the third layer comprising a metal oxide and a dopant, the third layer having a breakdown voltage of at least 8V and a resistivity of at least 1 Ohm-cm, the third layer disposed between the first electrode layer and the second electrode layer; anda fourth layer operable as a resistive switching layer and comprising a resistive switching material, the fourth layer disposed between the first electrode layer and the second electrode layer,wherein the breakdown voltage of the third layer is greater than a breakdown voltage of the fourth layer, andwherein a maximum resistivity of the third layer is greater than a resistivity of a low resistance state of the fourth layer and is less than a resistivity of a high resistance state of the fourth layer.2. The resistive random access memory cell of claim 1 , wherein the third layer comprises titanium oxide doped with niobium.3. The ...

Memory Devices and Memory Device Forming Methods

Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.

Process for depositing porous organosilicate glass films for use as resistive random access memory

A process for forming a resistive random-access memory device, the process comprising the steps of: depositing a first electrode on a substrate; forming a porous resistive memory material layer on the first electrode, wherein the porous resistive memory layer is formed by (i) depositing a gaseous composition comprising a silicon precursor and a porogen precursor and, once deposited, (ii) removing the porogen precursor by exposing the composition to UV radiation; and depositing a second electrode on top of the porous resistive memory material layer.

METHODS FOR FORMING MEMORY DEVICES, AND ASSOCIATED DEVICES AND SYSTEMS

Methods of manufacturing memory devices having memory cells and corresponding selectors, and associated systems and devices, are disclosed herein. In one embodiment, a method of manufacturing a memory device includes (a) removing a protection layer formed over the memory cells and (b) forming a cap layer over the memory cells before forming a conductive via through the memory device. The cap layer is configured to protect the memory cells during operation and can comprise a resistive material. The protection layer can be more efficiently removed with improved process margin and less device health impact using a polishing process before the conductive via is formed, thus increasing the manufacturing margin of the memory device.

SWITCHING DEVICE HAVING BI-DIRECTIONAL DRIVE CHARACTERISTICS AND METHOD OF OPERATING SAME

Disclosed is a bi-directional two-terminal phase-change memory device using a tunneling thin film and a method of operating the same. According to an one embodiment, a phase-change memory device comprises: a first electrode; a second electrode; and a phase-change memory cell interposed between the first electrode and the second electrode, wherein the phase-change memory cell comprises: a P-type intermediate layer used as a data storage as a crystal state changes due to a voltage applied through the first electrode and the second electrode; an upper layer and a lower layer formed using an N-type semiconductor material at both ends of the intermediate layer; and at least one tunneling thin film disposed on at least one area from among an area between the upper layer and the intermediate layer or an area between the lower layer and the intermediate layer, so as to reduce a leakage current in the intermediate layer or prevent intermixing between a P-type dopant and an N-type dopant. 1. A phase-change memory device comprising:a first electrode;a second electrode; anda phase-change memory cell interposed between the first electrode and the second electrode,wherein the phase-change memory cell comprises:a P-type intermediate layer used as data storage as a crystal state changes due to a voltage applied through the first electrode and the second electrode;an upper layer and a lower layer formed using an N-type semiconductor material at both ends of the intermediate layer; andat least one tunneling thin film arranged in at least one area from among an area between the upper layer and the intermediate layer and an area between the lower layer and the intermediate layer, the at least one tunneling thin film being configured to reduce a leakage current in the intermediate layer or prevent intermixing between a P-type dopant and an N-type dopant.2. The phase-change memory device of claim 1 , wherein the at least one tunneling thin film is formed using a material to have a ...

RESISTIVE MEMORY WITH A SWITCHING ZONE BETWEEN TWO DIELECTRIC REGIONS HAVING DIFFERENT DOPING AND/OR DIELECTRIC CONSTANTS

Resistive memory cell provided with a first electrode and a second electrode arranged on either side of a dielectric layer and facing an interface between a first region and a second region, said first and second region having different compositions in terms of doping and/or dielectric constant, so as to confine the zone of reversible creation of a conductive filament at said interface.

Atomic Layer Deposition of Metal Oxide Materials for Memory Applications

Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies. Therefore, the metal oxide film stacks have improved switching performance and reliability during memory cell applications compared to traditional hafnium oxide based stacks of previous memory cells. 1. A device comprising:a first electrode disposed on a substrate; 'the host layer comprising an exposed surface; and', 'a host layer disposed on the first electrode,'} wherein the coupling layer and the host layer form a misaligned grain interface,', 'the misaligned grain interface facilitating oxygen vacancy exchange between the coupling layer and the host layer., 'a coupling layer over the host layer,'}2. The device of claim 1 , wherein the host layer comprises a crystalline metal-rich oxide.3. The device of claim 2 , wherein the crystalline metal-rich oxide is represented by a generic chemical formula of MO claim 2 , wherein M comprises one of hafnium claim 2 , zirconium claim 2 , or titanium claim 2 , and wherein X is within a range from about 1.65 to about 1.95.4. The device of claim 3 , wherein X is within a range from about 1.70 to about 1.90.5. The device of claim 1 , wherein the coupling layer comprises an amorphous metal ...

METHODS OF FORMING METAL OXIDE

Some embodiments include methods of forming memory cells. Metal oxide may be deposited over a first electrode, with the deposited metal oxide having a relatively low degree of crystallinity. The degree of crystallinity within the metal oxide may be increased after the deposition of the metal oxide. A dielectric material may be formed over the metal oxide, and a second electrode may be formed over the dielectric material. The degree of crystallinity may be increased with a thermal treatment. The thermal treatment may be conducted before, during, and/or after formation of the dielectric material. 1. A method of increasing crystallinity within a metal oxide , comprising:annealing the metal oxide at a temperature of at least about 600° C. while exposing the metal oxide to an environment which is either inert relative to reaction with all constituents of the metal oxide, or reducing relative to reaction with one or more constituents of the metal oxide; the metal oxide being electrically conductive after said anneal.2. The method of wherein the metal oxide comprises oxygen in combination with one or more of praseodymium claim 1 , barium claim 1 , calcium claim 1 , manganese claim 1 , strontium claim 1 , titanium claim 1 , iron claim 1 , cesium and lead.3. The method of wherein the metal oxide comprises PrCaMnO; where the listed composition is described in terms of principle components claim 1 , rather than in terms of a specific stoichiometry.4. The method of wherein the environment comprises H.5. The method of wherein the environment comprises argon and/or N.6. A method of forming an electrically conductive metal oxide claim 1 , comprising:depositing metal oxide over an underlying material; andafter the depositing, increasing crystallinity of the metal oxide by annealing the metal oxide at a temperature of at least about 600° C. while exposing the metal oxide to an environment which is reducing relative to reaction with one or more constituents of the metal oxide.7. The ...