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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 1317. Отображено 100.
13-06-2013 дата публикации

Methods Of Forming Memory Cells, And Methods Of Patterning Chalcogenide-Containing Stacks

Номер: US20130149834A1
Автор: Imonigie Jerome, Liu Jun
Принадлежит: MICRON TECHNOLOGY, INC.

Some embodiments include methods of forming memory cells. Chalcogenide is formed over a plurality of bottom electrodes, and top electrode material is formed over the chalcogenide. Sacrificial material is formed over the top electrode material. A plurality of memory cell structures is formed by etching through the sacrificial material, top electrode material and chalcogenide. Each of the memory cell structures has a cap of the sacrificial material thereover. The etching forms polymeric residue over the sacrificial material caps, and damages chalcogenide along sidewalls of the structures. The sacrificial material is removed with an HF-containing solution, and such removes the polymeric residue off of the memory cell structures. After the sacrificial material is removed, the sidewalls of the structures are treated with one or both of HOand HNOto remove damaged chalcogenide from the sidewalls of the memory cell structures. 129-. (canceled)30. A method of forming chalcogenide structures , comprising:etching through the chalcogenide to pattern the chalcogenide into a plurality of structures; the etching damaging the chalcogenide along sidewalls of the structures; andtreating the sidewalls of the structures with an oxidant to alleviate the damage along the sidewalls.31. The method of wherein the etching utilizes a dry etch with one or more of HBr claim 30 , Cland CF.32. The method of wherein the etching utilizes a dry etch with HBr.33. The method of wherein the chalcogenide comprises Ge and Sb.34. The method of wherein the chalcogenide comprises Ge claim 30 , Sb and Te.35. The method of wherein the oxidant comprises HO.36. The method of wherein the oxidant comprises HNO.37. A method of forming memory cells claim 30 , comprising:forming electrode material over chalcogenide;forming sacrificial material over the electrode material;etching through the sacrificial material, electrode material and chalcogenide to form a plurality of spaced apart memory cell structures, each of ...

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Номер записи: 1
05-12-2013 дата публикации

Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same

Номер: US20130320287A1
Автор: April D. Schricker, Mark H. Clark, S. Brad Herner
Принадлежит: SanDisk 3D LLC

A method of forming a memory cell is provided that includes forming a steering element above a substrate, forming a material layer on the substrate, patterning and etching the material layer, and oxidizing the patterned and etched material layer to form a reversible resistance-switching material. Numerous other aspects are provided.

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Номер записи: 2
23-01-2014 дата публикации

VARIABLE RESISTANCE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20140021432A1
Автор: LEE Sung-Hoon
Принадлежит: SK HYNIX INC.

A method for fabricating a variable resistance memory device includes forming an insulating layer having a trench extending in a first direction over a substrate, forming first electrode conductive layers on both sidewalls of the trench, forming island-shaped first electrodes by patterning the conductive layers in a second direction crossing the first direction, forming variable resistance patterns over the first electrodes, and forming second electrodes over the variable resistance patterns. 1. A method for fabricating a variable resistance memory device , comprising:forming an insulating layer having a trench extending in a first direction over a substrate;forming first electrode conductive layers on both sidewalls of the trench;forming island-shaped first electrodes by patterning the conductive layers in a second direction crossing the first direction;forming variable resistance patterns over the first electrodes; andforming second electrodes over the variable resistance patterns.2. The method of claim 1 , wherein the forming of the first electrode conductive layers comprises:forming a conductive material along the entire surface of a structure having the trench formed therein; andblanket-etching the conductive material.3. The method of claim 1 , further comprising claim 1 , after the forming of the first electrodes:forming an insulating material to cover a structure having the first electrodes formed therein; andperforming a planarization process until the first electrode is exposed.4. The method of claim 1 , wherein each of the variable resistance patterns has a larger width than each of the first electrodes in the first and second directions.5. The method of claim 4 , wherein the forming of the variable resistance patterns is performed by a mask and etch process.6. The method of claim 1 , wherein the forming of the variable resistance patterns and the forming of the second electrodes comprise:sequentially forming a variable resistance material layer and a ...

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Номер записи: 3
23-01-2014 дата публикации

NONVOLATILE STORAGE ELEMENT AND METHOD OF MANUFACTURING THEREOF

Номер: US20140024197A1
Автор: Imai Shinichi, Kawashima Yoshio, Mikawa Takumi
Принадлежит:

A method of manufacturing a variable resistance nonvolatile memory element includes: forming a lower electrode layer above a substrate; forming, on the lower electrode layer, a variable resistance layer including an oxygen-deficient transition metal oxide; forming an upper electrode layer on the variable resistance layer; and forming a patterned mask on the upper electrode layer and etching the upper electrode layer, the variable resistance layer, and the lower electrode layer using the patterned mask, wherein in the etching, at least the variable resistance layer is etched using an etching gas containing bromine. 1. A method of manufacturing a nonvolatile memory element , the method comprising:forming a lower electrode layer above a substrate;forming, on the lower electrode layer, a variable resistance layer including an oxygen-deficient transition metal oxide;forming an upper electrode layer on the variable resistance layer; andforming a patterned mask on the upper electrode layer and etching the upper electrode layer, the variable resistance layer, and the lower electrode layer using the patterned mask,wherein in the etching, at least the variable resistance layer and the lower electrode layer are etched using an etching gas containing bromine.2. The method of manufacturing a nonvolatile memory element according to claim 1 ,wherein in the etching, the etching gas contains hydrogen bromide.3. The method of manufacturing a nonvolatile memory element according to claim 1 ,wherein in the forming of the variable resistance layer,the variable resistance layer is formed to comprise a transition metal oxide having resistance which is variable according to an oxygen amount in the transition metal oxide, the resistance being increased by incorporation of an impurity in the variable resistance layer.4. The method of manufacturing a nonvolatile memory element according to claim 3 ,wherein in the forming of the variable resistance layer,the variable resistance layer is formed ...

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Номер записи: 4
10-04-2014 дата публикации

Non-volatile memory device and manufacturing method thereof

Номер: US20140097396A1
Автор: Atsushi Himeno, Hideaki Murase, Yoshio Kawashima
Принадлежит: Panasonic Corp

A non-volatile memory device of the present invention comprises a first electrode; a variable resistance layer formed on and above the first electrode; a second electrode formed on and above the variable resistance layer; a side wall protective layer having an insulativity and covering a side wall of the first electrode, a side wall of the variable resistance layer and a side wall of the second electrode; and an electrically-conductive layer connected to the second electrode; the non-volatile memory device including a connection layer which is provided between the second electrode and the electrically-conductive layer to connect the second electrode and the electrically-conductive layer to each other, and comprises an electrically-conductive material different from a material constituting the electrically-conductive layer; wherein the side wall protective layer extends across the second electrode to a position which is above an upper end of the second electrode and below an upper end of the connection layer such that an upper end of the side wall protective layer is located above the upper end of the second electrode and below the upper end of the connection layer, when viewed from a side.

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Номер записи: 5
13-01-2022 дата публикации

Resistive memory device

Номер: US20220013171A1
Автор: Masayuki Terai
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A resistive memory device includes a first word line extending in a first horizontal direction, a second word line extending on the first word line in the first horizontal direction, a third word line extending on the second word line in the first horizontal direction, a first bit line extending between the first and second word lines in a second horizontal direction, a second bit line extending between the second and third word lines in the second horizontal direction, and memory cells respectively arranged between the first word line and the first bit line, between the first bit line and the second word line, between the second word line and the second bit line, and between the second bit line and the third word line. A thickness of the second word line is greater than a thickness of each of the first word line and the third word line.

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Номер записи: 6
05-01-2017 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

Номер: US20170005264A1
Автор: MASUOKA Fujio, Nakamura Hiroki
Принадлежит:

The present invention provides a memory structure including a resistance-changing storage element, which enables a reset operation with a reset gate and in which cross-sectional areas of a resistance-changing film and a lower electrode in a current-flowing direction can be decreased. The semiconductor device of the present invention comprises a first pillar-shaped semiconductor layer, a gate insulating film formed around the first pillar-shaped semiconductor layer, a gate electrode made of a metal and formed around the gate insulating film, a gate line made of a metal and connected to the gate electrode, a second gate insulating film formed around an upper portion of the first pillar-shaped semiconductor layer, a first contact made of a second metal and formed around the second gate insulating film, a second contact which is made of a third metal and which connects an upper portion of the first contact to an upper portion of the first pillar-shaped semiconductor layer, a second diffusion layer formed in a lower portion of the first pillar-shaped semiconductor layer, a pillar-shaped insulating layer formed on the second contact, a resistance-changing film formed around an upper portion of the pillar-shaped insulating layer, a lower electrode formed around a lower portion of the pillar-shaped insulating layer and connected to the resistance-changing film, a reset gate insulating film that surrounds the resistance-changing film, and a reset gate that surrounds the reset gate insulating film. 1a seventh step of depositing a second interlayer insulating film, forming a contact hole, depositing a fourth metal and a nitride film,removing portions of the fourth metal and the nitride film on the second interlayer insulating film to form a pillar-shaped nitride film layer and a lower electrode in the contact hole, the lower electrode surrounding a bottom portion of the pillar-shaped nitride film layer and the pillar-shaped nitride film layer,etching back the second interlayer ...

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Номер записи: 7
02-01-2020 дата публикации

Phase change memory device with reduced read disturb and method of making the same

Номер: US20200005863A1
Автор: Michael Grobis, Ward Parkinson, Zhaoqiang BAI
Принадлежит: SanDisk Technologies LLC

A method of operating a phase change memory device includes flowing a write current of a first polarity through a phase change memory element of a selected phase change memory cell, and flowing a read current of a second polarity opposite to the first polarity through the phase change memory element of the selected phase change memory cell. A first junction between the phase change memory element and a first electrode and a second junction between the phase change memory element and a second electrode exhibit asymmetric thermoelectric heat generation during the step of flowing the write current.

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Номер записи: 8
04-01-2018 дата публикации

CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME

Номер: US20180006217A1
Автор: GHETTI Andrea, Pellizzer Fabio, Tortorelli Innocenzo
Принадлежит:

The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. Upper conductive lines are formed over and crossing the line stacks, exposing portions of the line stacks between adjacent upper conductive lines. After forming the upper conductive lines, storage elements are formed at intersections between the lower conductive lines and the upper conductive lines by removing storage materials from exposed portions of the line stacks, such that each storage element is laterally surrounded by spaces. A continuous sealing material laterally surrounds each of the storage elements. 1. A method , comprising:forming a plurality of line stacks, wherein each of the plurality of line stacks includes a memory storage material line disposed over one of a plurality of lower conductive lines;forming a plurality of upper conductive lines on and crossing the plurality of line stacks, wherein forming the plurality of upper conductive lines exposes portions of the plurality of line stacks between adjacent ones of the plurality of upper conductive lines;after forming the plurality of upper conductive lines, forming a plurality of memory storage elements at intersections between the plurality of lower conductive lines and the plurality of upper conductive lines by removing memory storage material from the memory storage material lines such that each of the plurality of memory storage elements is laterally surrounded by spaces; andforming a continuous sealing material laterally surrounding each of the plurality of memory storage elements.2. The method of claim 1 , wherein:forming the plurality of line stacks comprises using a first photo mask to pattern a material stack including the memory storage material disposed over a lower conductive material;forming the plurality of upper conductive lines ...

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Номер записи: 9
04-01-2018 дата публикации

Methods of manufacturing semiconductor devices

Номер: US20180006219A1
Автор: Bok-yeon Won, Gwang-Hyun Baek, Hye-Jin Choi, Jae-Hun Seo, Jong-Chul Park, Jung-Ik Oh, Woo-Ram KIM, Yoo-Chul Kong
Принадлежит: SAMSUNG ELECTRONICS CO LTD

In method of manufacturing a semiconductor memory device, a selection layer and a variable resistance layer may be sequentially formed on a substrate. A preliminary first mask extending in a first direction may be formed on the variable resistance layer. An upper mask extending in a second direction crossing the first direction may be formed on the variable resistance layer and the preliminary first mask. The preliminary first mask may be etched using the upper mask as an etching mask to form a first mask having a pillar shape. The variable resistance layer and the selection layer may be anisotropically etched using the first mask as an etching mask to form a pattern structure including a variable resistance pattern and selection pattern sequentially stacked. The pattern structure may have a pillar shape. Damages to the pattern structure may decrease.

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Номер записи: 10
07-01-2021 дата публикации

CBRAM WITH CONTROLLED BRIDGE LOCATION

Номер: US20210005813A1
Автор: Adusumilli Praneet, Ando Takashi, Tang Jianshi, Vega Reinaldo
Принадлежит:

Devices with settable resistance and methods of forming the same include forming vertical dielectric structures from heterogeneous dielectric materials on a first electrode. A second electrode is formed on the vertical dielectric structures. 1. A method for forming a device with a settable resistance , comprising:forming a plurality of vertical dielectric structures from heterogeneous dielectric materials on a first electrode; andforming a second electrode on the plurality of vertical dielectric structures.2. The method of claim 1 , wherein forming the plurality of vertical dielectric structures comprises forming a mandrel from a first dielectric material that partially covers the first electrode.3. The method of claim 2 , wherein forming the plurality of vertical dielectric structures further comprises forming a first sidewall spacer from a second dielectric material claim 2 , different from the first dielectric material claim 2 , on a sidewall of the mandrel.4. The method of claim 3 , wherein forming the plurality of vertical dielectric structures further comprises forming a second sidewall spacer from a third dielectric material claim 3 , different from the second dielectric material claim 3 , on a sidewall of the first sidewall spacer.5. The method of claim 4 , wherein forming the plurality of vertical dielectric structures further comprises forming a third sidewall spacer from the second dielectric material on a sidewall of the second sidewall spacer.6. The method of claim 3 , wherein forming the plurality of vertical dielectric structures further comprises forming an interlayer dielectric from the first dielectric material on a sidewall of the first sidewall spacer.7. The method of claim 1 , further comprising forming spacer remnants on a sidewall of the first electrode as part of forming the plurality of vertical dielectric structures.8. The method of claim 1 , wherein the second electrode is formed from a conductive material that does undergo ...

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Номер записи: 11
02-01-2020 дата публикации

REDUCTION OF METAL RESISTANCE IN VERTICAL RERAM CELLS

Номер: US20200006426A1
Автор: Ando Takashi, Hashemi Pouya, Lee Choonghyun
Принадлежит:

Embodiments of the invention include resulting structures and a method for fabricating a vertical ReRAM array structure. The embodiments of the invention include forming alternating layers over a metal layer of a structure, wherein a layer of the alternating layers comprises a low resistivity material, masking one or more portions of a topmost layer of the alternating layers, and etching one or more portions of the alternating layers down to the metal layer. Embodiments of the invention also include depositing a lateral electrode layer over the etched one or more portions of the alternating layers, performing an etch back on the lateral electrode layer, and forming a vertical electrode layer over the structures. 1. A method for fabricating a vertical ReRAM array structure , the method comprising:forming alternating layers over a metal layer of a structure, wherein a layer of the alternating layers comprises a low resistivity material, wherein the low resistivity material is a metal and forms a lateral electrode access layer;masking one or more portions of a topmost layer of the alternating layers;etching one or more portions of the alternating layers down to the metal layer;depositing a lateral electrode layer over the etched one or more portions of the alternating layers and the lateral electrode access layer;performing an etch back on the lateral electrode layer; andforming a vertical electrode layer over the structures, wherein the vertical electrode layer contacts the lateral electrode layer, wherein the lateral electrode layer contacts the lateral electrode access layer.2. The method of claim 1 , wherein forming the vertical electrode comprises depositing a first transitional oxide layer claim 1 , depositing a second alloy layer on the transitional oxide layer claim 1 , depositing a barrier layer on the second alloy layer claim 1 , and wherein the lateral electrode access layer is formed on the barrier layer.3. The method of claim 1 , wherein:etching the one or ...

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Номер записи: 12
03-01-2019 дата публикации

METHOD FOR FABRICATING A PHASE-CHANGE MEMORY CELL

Номер: US20190006421A1
Автор: Casellato Cristina, Magistretti Michele, Pellizzer Fabio, Vigilante Monica
Принадлежит:

A method for fabricating a phase-change memory cell is described. The method includes forming a dielectric layer () on a metal layer () above a substrate. A phase-change material layer () is formed on the dielectric layer. A contact region () is formed, within the dielectric layer, between the phase-change material layer and the metal layer by breaking-down a portion of the dielectric layer. 1forming a selector device on a substrate;forming a metal plug to couple to a contact of the selector device of the memory cell;forming an oxygen-free layer on exposed portions of the metal plug to prevent oxidation of the metal plug;forming a dielectric layer on the oxygen-free layer;forming a phase-change material layer on the dielectric layer; and determining a set-state target current for the phase-change material layer, and', 'applying, through the metal plug, a current pulse greater than the set-state target current; and, 'forming a contact region disposed within the dielectric layer and between the phase-change material layer and the metal plug by'}subsequent to applying the current pulse greater than the set-state target current, making a determination of an actual amount of current driven by the phase-change memory cell in a crystalline state.. A method of forming a memory cell, the method comprising: Embodiments of the invention are in the field of phase-change memory cells and, in particular, methods for fabricating phase-change memory cells.Embedded SRAM and DRAM have problems with non-volatility and soft error rates, while embedded FLASH memories require additional masking layers or processing steps during manufacture, require high-voltage for programming, and have issues with endurance and reliability. Phase-Change Memory (PCM) overcomes the criticality of the above mentioned parameters and exhibits favorable write speeds, small cell sizes, simpler circuitries and a fabrication compatibility with the Complementary Metal-Oxide-Semiconductor (CMOS) process. However, ...

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Номер записи: 13
03-01-2019 дата публикации

VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20190006422A1
Автор: PARK Jong-Chul
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A variable resistance memory device including a first conductive line extending in a first direction on a substrate, a second conductive line on the first conductive line and extending in a second direction crossing the first direction, and a memory cell pillar connected to the first conductive line and the second conductive line at a crossing point therebetween and including a heating electrode layer and a variable resistance layer in contact with the heating electrode layer such that both sidewalls of the heating electrode layer are aligned with both sidewalls of the first conductive line in the first direction. 1. A variable resistance memory device comprising:a first conductive line on a substrate, the first conductive line extending in a first direction;a second conductive line on the first conductive line, the second conductive line extending in a second direction, the second direction being a direction crossing the first direction; anda memory cell pillar connected to the first conductive line and the second conductive line at an intersection point therebetween, the memory cell pillar including a heating electrode layer and a variable resistance layer, the variable resistance layer in contact with the heating electrode layer, two opposite sidewalls of the heating electrode layer aligned with two opposite sidewalls of the first conductive line in the first direction, respectively.2. The variable resistance memory device of claim 1 , wherein the heating electrode layer is in contact with a portion of a bottom surface of the variable resistance layer in the first direction claim 1 , and is in contact with an entirety of the bottom surface of the variable resistance layer in the second direction.3. The variable resistance memory device of claim 1 , wherein the substrate includes a substrate recess portion claim 1 , the substrate recess portion being a recess formed in the substrate in a self-aligned manner with respect to the two opposite sidewalls of the first ...

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Номер записи: 14
03-01-2019 дата публикации

APPARATUS AND TECHNIQUES FOR ANISOTROPIC SUBSTRATE ETCHING

Номер: US20190006587A1
Автор: Gilchrist Glen F. R., Liang Shurong, Pervaiz Raees, Rockwell Tyler, Starks Kenneth
Принадлежит: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.

A method may include generating a plasma in a plasma chamber, the plasma comprising an etchant species and extracting a pulsed ion beam from the plasma chamber and directing the pulsed ion beam to a substrate, where the pulsed ion beam comprises an ON portion and an OFF portion. During the OFF portion the substrate may not be biased with respect to the plasma chamber, and the duration of the OFF portion may be less than a transit time of the etchant species from the plasma chamber to the substrate. 1. A method , comprising:generating a plasma in a plasma chamber, the plasma comprising an etchant species; andextracting a pulsed ion beam from the plasma chamber and directing the pulsed ion beam to a substrate, the pulsed ion beam comprising an ON portion and an OFF portion,wherein during the OFF portion the substrate is not biased with respect to the plasma chamber, andwherein a duration of the OFF portion is less than a transit time of the etchant species from the plasma chamber to the substrate.2. The method of claim 1 , wherein the plasma is generated by providing RF power to the plasma chamber claim 1 , the method further comprising adjusting a level of RF power of the plasma in concert with the pulsed ion beam claim 1 , wherein the plasma comprises a first RF power level during the ON portion and a second RF power level during the OFF portion claim 1 , wherein the first RF power level is higher than the second RF power level.3. The method of claim 2 , wherein the second RF power level is adequate to sustain the plasma.4. The method of claim 1 , wherein the etchant species is a thermal neutral species.5. The method of claim 1 , wherein the etchant species comprises at least one of chlorine neutrals and chlorine ions.6. The method of claim 1 , comprising:setting a separation between the plasma chamber and the substrate, wherein the transit time of the etchant species is proportional to the separation; andsetting the duration of the OFF portion to be less than the ...

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Номер записи: 15
02-01-2020 дата публикации

THERMAL DISPERSION LAYER IN PROGRAMMABLE METALLIZATION CELL

Номер: US20200006649A1
Автор: Jiang Fa-Shen, Lin Hsing-Lien
Принадлежит:

Some embodiments relate to a memory device. The memory device includes a programmable metallization cell random access memory (PMCRAM) cell. The programmable metallization cell comprises a dielectric layer disposed over a bottom electrode, the dielectric layer contains a central region. A conductive bridge is formable and erasable within the dielectric layer and the conductive bridge is contained within the central region of the dielectric layer. A metal layer is disposed over the dielectric layer. A heat dispersion layer is disposed between the bottom electrode and the dielectric layer. 1. A memory device , comprising:a bottom electrode;a dielectric layer disposed over the bottom electrode;a top electrode disposed over the dielectric layer, wherein a conductive bridge is selectively formable within the dielectric layer to couple the bottom electrode to the top electrode; anda heat dispersion layer disposed between the bottom electrode and the dielectric layer.2. The memory device of claim 1 , wherein the heat dispersion layer is comprised of a material having a thermal conductivity greater than 100 W/m−K.3. The memory device of claim 1 , wherein the heat dispersion layer is comprised of aluminum nitride claim 1 , silicon carbide claim 1 , beryllium oxide claim 1 , or boron nitride.4. The memory device of wherein the memory device is configured to switch between a high-resistance state and a low-resistance state;wherein, when in the high-resistance state, a conductive pillar is disposed within a central region of the dielectric layer, the conductive pillar having a bottom surface in contact with an upper surface of the heat dispersion layer and having a top surface spaced apart from the top electrode by an upper portion of the dielectric layer; andwherein, when in the low-resistance state, the conductive pillar remains disposed within the central region of the dielectric layer and a conductive bridge is formed to extend through the upper portion of the dielectric ...

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Номер записи: 16
02-01-2020 дата публикации

RESISTIVE RANDOM-ACCESS MEMORY (RRAM) CELL WITH RECESSED BOTTOM ELECTRODE SIDEWALLS

Номер: US20200006653A1
Автор: Liu Shih-Chang, Tseng Yuan-Tai
Принадлежит:

Various embodiments of the present application are directed towards an integrated circuit comprising a resistive random-access memory (RRAM) cell with recessed bottom electrode sidewalls to mitigate the effect of sidewall plasma damage. In some embodiments, the RRAM cell includes a lower electrode, a data storage element, and an upper electrode. The lower electrode includes a pair of recessed bottom electrode sidewalls respectively on opposite sides of the lower electrode. The data storage element overlies the lower electrode and includes a pair of storage sidewalls. The storage sidewalls are respectively on the opposite sides of the lower electrode, and the recessed bottom electrode sidewalls are laterally spaced from and laterally between the storage sidewalls. The upper electrode overlies the data storage element. 1. A method for forming an integrated circuit comprising a memory cell , the method comprising:forming a lower conductive layer on a substrate;forming a data storage layer overlying the lower conductive layer;forming an upper conductive layer overlying the data storage layer;patterning the upper conductive layer, the data storage layer, and the lower conductive layer to respectively form an upper electrode, a data storage element, and a lower electrode stacked on the substrate, wherein the patterning forms sidewall defects in storage sidewalls of the data storage element; andperforming an etch into the lower electrode to laterally recess electrode sidewalls of the lower electrode respectively relative to neighboring ones of the storage sidewalls.2. The method according to claim 1 , wherein the patterning comprises:performing a second etch into the data storage layer and the lower conductive layer to respectively form the data storage element and the lower electrode, wherein the storage sidewalls are respectively aligned with the electrode sidewalls upon completion of the second etch.3. The method according to claim 2 , wherein the second etch is ...

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Номер записи: 17
02-01-2020 дата публикации

COMPACT RESISTIVE RANDOM ACCESS MEMORY INTEGRATED WITH A PASS GATE TRANSISTOR

Номер: US20200006656A1
Автор: Leobandung Effendi
Принадлежит:

A method of forming a resistive random access memory (ReRAM) device is provided. The method includes depositing a lower cap layer on a substrate, depositing a dielectric memory layer on the lower cap layer, and depositing an upper cap layer on the dielectric memory layer. The method further includes removing portions of the lower cap layer to form a lower cap slab, dielectric memory layer to form a dielectric memory slab on the lower cap slab, and upper cap layer to form an upper cap slab on the dielectric memory slab, wherein the lower cap slab, dielectric memory slab, and upper cap slab form a resistive memory element. 1. A method of forming a resistive random access memory (ReRAM) device , comprising:depositing a lower cap layer directly on a source/drain contact, wherein the source/drain contact is in direct contact with a source/drain on a substrate;depositing a dielectric memory layer on the lower cap layer;depositing an upper cap layer on the dielectric memory layer;forming a resistive element template on the upper cap layer;removing portions of the lower cap layer to form a lower cap slab, dielectric memory layer to form a dielectric memory slab on the lower cap slab, and upper cap layer to form an upper cap slab on the dielectric memory slab, exposed by the resistive element template, wherein the lower cap slab, dielectric memory slab, and upper cap slab form a resistive memory element; andforming a protective liner on the resistive element template and resistive memory element.2. The method of claim 1 , wherein the lower cap layer and upper cap layer each have a thickness in a range of about 2 nanometers (nm) to about 50 nm.3. The method of claim 1 , wherein the dielectric memory layer has a thickness in a range of about 2 nm to about 15 nm.4. The method of claim 1 , further comprising forming a field effect transistor device on the substrate claim 1 , wherein the field effect transistor device includes the source/drain claim 1 , and wherein the resistive ...

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Номер записи: 18
10-01-2019 дата публикации

LIQUID MIXTURE AND METHOD FOR ETCHING A SUBSTRATE USING THE LIQUID MIXTURE

Номер: US20190010397A1
Автор: Sellmer Reinhard
Принадлежит:

A liquid mixture for etching a substrate includes acetic acid in a range of 15 to 70 mass. % of the liquid mixture, nitric acid in a range of 5 to 50 mass. % of the liquid mixture, sulfuric acid in a range of 8 to 50 mass. % of the liquid mixture, and water in a range of 0 to 30 mass. % of the liquid mixture. 17-. (canceled)8. A method for etching a substrate , comprising:providing the substrate, wherein the substrate comprises a first exposed material and a second exposed material, wherein the first exposed material comprises tantalum oxide, and wherein the second exposed material is different than the first exposed material;treating the substrate using a plasma or a halogen species during processing, wherein a portion of the first exposed material is plasma-damaged or contaminated by the halogen species; anddispensing a liquid mixture onto the substrate to etch the plasma-damaged or contaminated portion of the first exposed material and a portion of the second exposed material from the substrate, acetic acid in a range of 15 to 70 mass. % of the liquid mixture;', 'nitric acid in a range of 5 to 50 mass. % of the liquid mixture;', 'sulfuric acid in a range of 8 to 50 mass. % of the liquid mixture; and', 'water in a range of 0 to 30 mass. % of the liquid mixture., 'wherein the liquid mixture includes'}9. (canceled)10. The method of claim 8 , wherein the substrate comprises a resistive random access memory cell.11. The method of claim 8 , further comprising prior to dispensing the liquid mixture:arranging the substrate on a spin chuck; androtating the substrate using the spin chuck.12. The method of further comprising mixing the liquid mixture with hydrofluoric acid prior to dispensing the liquid mixture.13. The method of claim 12 , wherein the concentration of the hydrofluoric acid is in a range from 0.05 to 1 mass. % of the liquid mixture.14. The method of claim 12 , wherein the concentration of the hydrofluoric acid is in a range from 0.1 to 0.5 mass. % of the ...

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Номер записи: 19
14-01-2016 дата публикации

SEMICONDUCTOR APPARATUS AND METHOD FOR FABRICATING THE SAME

Номер: US20160013408A1
Автор: KIM Hyung Keun
Принадлежит:

A method for fabricating a semiconductor apparatus includes providing a semiconductor substrate, stacking a conductive layer, a variable resistance layer, and a sacrificial layer on the semiconductor substrate, etching the conductive layer, the variable resistance layer, and the sacrificial layer to form a pillar structure including a lower electrode, a variable resistor device, and a sacrificial layer pattern, removing the sacrificial layer pattern, and forming an upper electrode over the variable resistor device in a hole which is formed by removing the sacrificial layer pattern. 1. A method for fabricating a semiconductor apparatus , the method comprising:providing a semiconductor substrate;stacking a conductive layer, a variable resistance layer, and a sacrificial layer over the semiconductor substrate;etching the conductive layer, the variable resistance layer, and the sacrificial layer to form a pillar structure which includes a lower electrode, a variable resistor device, and a sacrificial layer pattern;forming an intercell insulating layer between the pillar structure and a neighboring pillar structure;removing the sacrificial layer pattern; andforming an upper electrode, which has a contact area between the upper electrode and the variable resistor device, over the variable resistor device in a hole which is formed by removing the sacrificial layer pattern,wherein the contact area between the upper electrode and the variable resistor device is smaller than an upper surface area of the variable resistor device.2. The method of claim 1 , wherein the stacking of the conductive layer claim 1 , the variable resistance layer claim 1 , and the sacrificial layer further includes:stacking a protection layer suitable to protect the variable resistance layer between the variable resistance layer and the sacrificial layer,wherein the protection layer is etched to form a protection layer pattern during the forming of the pillar structure.3. The method of claim 1 , ...

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Номер записи: 20
10-01-2019 дата публикации

Semiconductor device and method for fabricating the same

Номер: US20190013357A1
Автор: Jeong Hee Park, Jong Uk Kim, Jung Moo Lee, Seong Geon PARK, Soon Oh PARK
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes a first memory cell, a second memory cell, a first capping film, and a second capping film. The first memory cell includes a first ovonic threshold switch (OTS) on a first phase change memory. The second memory cell includes a second OTS on a second phase change memory. The first capping film is on side surfaces of the first and second memory cells. The second capping film is on the first capping film and fills a space between the first and second memory cells.

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Номер записи: 21
10-01-2019 дата публикации

Replacement materials processes for forming cross point memory

Номер: US20190013358A1
Автор: DerChang Kau, Gianpaolo Spadini, Jong-Won Lee, Stephen W. Russell
Принадлежит: Micron Technology Inc

Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower conductive line. The method further includes forming a chalcogenide line extending in the first direction by selectively removing the sacrificial material of the sacrificial line and replacing the sacrificial line with a chalcogenide material.

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Номер записи: 22
10-01-2019 дата публикации

CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME

Номер: US20190013359A1
Автор: Sciarrillo Samuele
Принадлежит:

The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls. The memory device additionally comprises first protective dielectric insulating materials formed on a lower portion of the first pair of sidewalls and an isolation dielectric formed on the first protective dielectric insulating material and further formed on an upper portion of the first pair of sidewalls. 1. (canceled)2. A apparatus , comprising:a substrate; a first protective material formed on at least a portion of a first pair of sidewalls of the memory cell stack; and', 'a second protective material formed on at least a portion of a second pair of sidewalls of the memory cell stack, the second protective material intersecting the first protective material., 'a memory cell stack over the substrate, the memory cell stack comprising3. The apparatus of claim 2 , wherein the memory cell stack further comprises a first memory element and a second memory element claim 2 , and wherein the first protective material and the second protective material are formed on at least a portion of the first memory element.4. The apparatus of claim 4 , wherein the first protective material and the second protective material are formed on a portion of the memory cell stack claim ...

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Номер записи: 23
10-01-2019 дата публикации

MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20190013466A1
Автор: KANG DAE-HWAN, KOH Gwan-hyeob, Park Il-mok
Принадлежит:

A memory device including first conductive lines spaced apart from each other and extending in a first direction; second conductive lines spaced apart from each other and extending in a second direction that is different from the first direction; first memory cells having a structure that includes a selection device layer, a middle electrode layer, a variable resistance layer, and a top electrode layer; and insulating structures arranged alternately with the first memory cells in the second direction under the second conductive lines, wherein the first insulating structures have a top surface that is higher than a top surface of the first top electrode layer, and the second conductive lines have a structure that includes convex and concave portions, the convex portions being connected to the top surface of the top electrode layer and the concave portions accommodating the insulating structures between the convex portions. 1. (canceled)235.-. (canceled)36. A memory device , comprising:a plurality of first conductive lines on a substrate, the first conductive lines being spaced apart from each other and extending in a first direction;a plurality of second conductive lines on the plurality of first conductive lines, the second conductive lines being spaced apart from each other and extending in a second direction that is different from the first direction;a plurality of first memory cells respectively arranged at a plurality of cross points between the plurality of first conductive lines and the plurality of second conductive lines, each of the first memory cells having a structure that includes a first selection device layer, a first middle electrode layer, a first variable resistance layer, and a first top electrode layer, wherein the first middle electrode layer is disposed between the first selection device layer and the first variable resistance layer; anda plurality of first insulating structures arranged alternately with the plurality of first memory cells in ...

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Номер записи: 24
10-01-2019 дата публикации

RESISTANCE VARIABLE MEMORY DEVICE WITH NANOPARTICLE ELECTRODE AND METHOD OF FABRICATION

Номер: US20190013467A1
Автор: Campbell Kristy A., Liu Jun
Принадлежит:

A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a chalcogenide glass region. The method of forming the nanoparticle utilizes a template over the electrode or random deposition of the nanoparticle. 1. An apparatus , comprising:a processor; a first electrode;', 'an aluminum layer in contact with the first electrode, the aluminum layer comprising at least one nanochannel that extends through the aluminum layer to the first electrode;', 'at least one nanoparticle in contact with the aluminum layer, within the at least one nanochannel, or both;', 'a first germanium selenide layer in contact with the aluminum layer and the at least one nanoparticle; and', 'a second electrode in contact with the first germanium selenide layer., 'a memory circuit configured to communicate with the processor, the memory circuit comprising2. The apparatus of claim 1 , further comprising:a layer of nanoparticle material in contact with the first germanium selenide layer, wherein a thickness of the layer of nanoparticle material is the same as a thickness of the at least one nanochannel in the aluminum layer.3. The apparatus of claim 1 , further comprising:a metal chalcogenide layer in contact with the first germanium selenide layer; anda second germanium selenide layer in contact with the metal chalcogenide layer.4. The apparatus of claim 3 , further comprising:a metal layer in contact with the second germanium selenide layer, wherein at least a portion of the metal layer comprises silver; anda third germanium selenide layer in contact with the metal layer.5. The apparatus of claim 4 , wherein the metal chalcogenide layer comprises a chalcogenide glass.6. The apparatus of claim 5 , wherein the chalcogenide glass comprises at least a portion of the metal chalcogenide layer.7. The apparatus of claim 1 , wherein the first electrode and the second electrode each comprise at least one of tungsten ...

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Номер записи: 25
09-01-2020 дата публикации

Programming enhancement in self-selecting memory

Номер: US20200013463A1
Автор: Agostino Pirovano, Andrea Redaelli, Fabio Pellizzer, Innocenzo Tortorelli
Принадлежит: Micron Technology Inc

Methods, systems, and devices for programming enhancement in memory cells are described. An asymmetrically shaped memory cell may enhance ion crowding at or near a particular electrode, which may be leveraged for accurately reading a stored value of the memory cell. Programming the memory cell may cause elements within the cell to separate, resulting in ion migration towards a particular electrode. The migration may depend on the polarity of the cell and may create a high resistivity region and low resistivity region within the cell. The memory cell may be sensed by applying a voltage across the cell. The resulting current may then encounter the high resistivity region and low resistivity region, and the orientation of the regions may be representative of a first or a second logic state of the cell.

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Номер записи: 26
14-01-2021 дата публикации

MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20210013263A1
Автор: JEONG Ji-Hyun, KANG DAE-HWAN, KOH Gwan-hyeob
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion. 129.-. (canceled)30. A semiconductor device comprising:a substrate;a circuit layer disposed on the substrate;an interlayer insulating layer disposed on the circuit layer;a first electrode disposed on the interlayer insulating layer;a second electrode disposed on the interlayer insulating layer, and spaced apart from the first electrode;a first insulation disposed on the interlayer insulating layer;a second insulation disposed on the interlayer insulating layer, and spaced apart from the first insulation;a first memory cell and a second memory cell disposed on the first electrode, and spaced apart from each other;a third memory cell and a fourth memory cell disposed on the second electrode, and spaced apart from each other;a third electrode disposed on the first memory cell and the third memory cell;a fourth electrode disposed on the second memory cell and the fourth memory cell, and spaced apart from the third ...

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Номер записи: 27
09-01-2020 дата публикации

PCRAM STRUCTURE

Номер: US20200013951A1
Автор: WU Jau-Yi
Принадлежит:

A memory device includes the following items. A substrate. A bottom electrode disposed over the substrate. An insulating layer disposed over the bottom electrode, the insulating layer having a through hole defined in the insulating layer. A heater disposed in the through hole. A phase change material layer disposed over the heater. A selector layer disposed over the phase change material layer. An intermediate layer disposed over the through hole. Also, a metal layer disposed over the selector layer. The metal layer is wider than the phase change material layer. 1. A memory device comprising:a substrate;a bottom electrode disposed over the substrate;an insulating layer disposed over the bottom electrode, the insulating layer having a through hole defined in the insulating layer;a heater disposed in the through hole;a phase change material layer disposed over the heater;a selector layer disposed over the phase change material layer;an intermediate layer over the through hole; anda metal layer disposed over the selector layer.2. The memory device of claim 1 , wherein the intermediate layer is wider than a diameter of the through hole.3. The memory device of claim 1 , wherein the metal layer is wider than the phase change material layer.4. The memory device of claim 1 , wherein the phase change material layer is disposed in the through hole.5. The memory device of claim 1 , wherein the selector layer is disposed in the through hole.6. The memory device of claim 1 , wherein the intermediate layer contacting the metal layer.7. The memory device of claim 1 , wherein the intermediate layer is formed of at least one of carbon and tungsten.8. The memory device of claim 1 , wherein the metal layer functions as a top electrode.9. A memory device comprising:a substrate;a bottom electrode disposed over the substrate;a first heater disposed over the bottom electrode;a first phase change material layer disposed over the first heater;a first selector layer disposed over the first ...

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Номер записи: 28
18-01-2018 дата публикации

DYNAMIC LOGIC MEMCAP

Номер: US20180017870A1
Автор: GE NING, Li Zhiyong, Williams R. Stanley, Yang Jianhua
Принадлежит: Hewlett-Packard Development Company, L.P.

An integrated circuit may include a substrate with a plurality of transistors formed in the substrate. The plurality of transistors may be coupled to a first metal layer formed over the plurality of transistors. A plurality of high dielectric nanometer capacitors may be formed of memristor switch material between the first metal layer and a second metal layer formed over the plurality of high dielectric capacitors. The plurality of high dielectric capacitors may operate as memory storage cells in dynamic logic. 1. An integrated circuit , comprising:a substrate with a plurality of transistors formed in the substrate, the plurality of transistors coupled to a first metal layer formed over the plurality of transistors; anda plurality of high dielectric nanometer capacitors formed of memristor switch material creating an active region between the first metal layer and a second metal layer formed over the plurality of high dielectric memcaps, wherein the plurality of high dielectric memcaps are to operate as memory storage cells in dynamic logic.2. The integrated circuit of claim 1 , wherein the memristor switch material is formed of memristor switch oxide of the first metal layer and additionally operational as memristors.3. The integrated circuit of wherein the memristor switch material active region is formed of memristor switch elemental or compound semiconductor and doped with mobile dopants to allow for memristor operation.4. The integrated circuit of claim 2 , further comprising a second plurality of transistors coupled between respective plurality of high dielectric nanometer memcaps and a programming source to allow for programming the memristors.5. The integrated circuit of wherein the dynamic logic is to operate as a set of shift registers.6. The integrated circuit of wherein the set of shift registers is to control a set of fluid jet resistors.7. The integrated circuit of wherein the set of shift registers have set/reset functionality by programming the ...

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Номер записи: 29
21-01-2016 дата публикации

SELF-ALIGNED MEMORY CELL CONTACT

Номер: US20160020391A1
Автор: APODACA Mac D., SHEPARD Daniel R.
Принадлежит:

In various embodiments, a memory storage element for storing two or more bits of information is formed by connecting two resistive change elements in series whereby the first resistive change element is made of a first material and the second resistive change element is made of a second material and the melting point of the first resistive change element material is greater than the melting point of the second resistive change element material such that the set and reset states of the two elements can be written and read.

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Номер записи: 30
19-01-2017 дата публикации

Memory Cells, Memory Arrays, and Methods of Forming Memory Cells and Arrays

Номер: US20170018708A1
Автор: Cupeta Carmela, Pellizzer Fabio, Redaelli Andrea, Servalli Giorgio
Принадлежит:

Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures. 18-. (canceled)9: A method of forming memory cells , comprising:forming a plurality of heater structures over an array of electrical nodes; the array of electrical nodes having rows extending along a first direction and having columns extending along a second direction substantially orthogonal to the first direction; wordlines being under the electrical nodes and extending along the first direction;forming a phase change material across the plurality of heater structures;patterning the phase change material into a plurality of confined structures; the plurality of confined structures being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures in the plurality of confined structures; each confined structure of the plurality of confined structures being associated with only a single memory cell; andforming bitlines across the plurality of confined structures, with the bitlines extending along the second direction; and forming first trenches through the phase change material and the lines of ...

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Номер записи: 31
03-02-2022 дата публикации

RESISTIVE MEMORY DEVICE

Номер: US20220037401A1
Автор: Bae ByeongJu, KIM Jonguk, PARK JeongHee
Принадлежит:

A resistive memory device includes a plurality of first conductive lines in a first area and a second area on a substrate, a plurality of second conductive lines in the first area and the second area, the plurality of second conductive lines being apart from the plurality of first conductive lines in a vertical direction, and a plurality of memory cells connected to the first and second conductive lines at a plurality of intersections between the plurality of first and second conductive lines in the first area and the second area. The plurality of memory cells include an active memory cell in the first area and a dummy memory cell in the second area. The active memory cell including a first resistive memory pattern having a first width and the dummy memory cell including a second resistive memory pattern having a second width greater than the first width. 1. A resistive memory device comprising:a plurality of first conductive lines extending in a first horizontal direction in a first area and a second area on a substrate, the first horizontal direction being parallel to the substrate;a plurality of second conductive lines extending in a second horizontal direction crossing the first horizontal direction in the first area and the second area, the plurality of second conductive lines being apart from the plurality of first conductive lines in a vertical direction, the vertical direction being perpendicular to the substrate; anda plurality of memory cells connected to the first conductive lines and the second conductive lines at a plurality of intersections between the plurality of first conductive lines and the plurality of second conductive lines in the first area and the second area,wherein the plurality of memory cells comprise an active memory cell in the first area and a dummy memory cell in the second area, the active memory cell including a first resistive memory pattern having a first width in a horizontal direction, and the dummy memory cell including a ...

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Номер записи: 32
03-02-2022 дата публикации

EFFICIENT FABRICATION OF MEMORY STRUCTURES

Номер: US20220037402A1
Автор: Baker Kevin Lee, Lee Don Koun, Wei Lei
Принадлежит:

Methods, systems, and devices for efficient fabrication of memory structures are described. A multi-deck memory device may be fabricated using a sequence of fabrication steps that include depositing a first metal layer, depositing a cell layer on the first metal layer to form memory cells of the first memory deck, and depositing a second metal layer on the cell layer. The second metal layer may be deposited using a single deposition process rather than using multiple deposition processes. A second memory deck may be formed on the second metal layer such that stacked memory cells from the first and second deck share the use of the second metal layer. Using a single deposition process for the second metal layer may decrease the quantity of fabrication steps used to fabricate the multi-deck memory array and reduce or eliminate the exposure of the cell material to metal etchants. 1. A method , comprising:depositing a first metal material on a substrate to form a first metal layer corresponding to a first access line associated with accessing a first memory cell;depositing at least a first cell material on the first metal layer to form a cell layer comprising the first memory cell;depositing, using a single deposition process, a second metal material on the cell layer to form a second metal layer corresponding to a second access line associated with accessing the first memory cell; andforming a second memory cell on a portion of the second metal layer, wherein the second access line is further associated with accessing the second memory cell.2. The method of claim 1 , wherein depositing the at least the first cell material comprises:depositing a first electrode material on the first metal layer to form a first electrode layer;depositing a cell storage material on the first electrode layer to form a cell storage layer; anddepositing a second electrode material on the cell storage layer to form a second electrode layer, wherein the cell layer comprises the first electrode ...

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Номер записи: 33
03-02-2022 дата публикации

MEMORY WITH OPTIMIZED RESISTIVE LAYERS

Номер: US20220037403A1
Автор: Baker Kevin Lee, Barton Adam Thomas, Ege Efe Sinan, Venigalla Rajasekhar, Wei Lei, Zheng Pengyuan
Принадлежит:

A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via. 17-. (canceled)8. A memory device , comprising:a substrate;a plurality of memory stacks positioned on the substrate, each memory stack comprising a layered assembly of electrode materials and memory material;a first resistive material positioned on the plurality of memory stacks;a first conductive material positioned on the plurality of memory stacks over the first resistive material;a via positioned on the substrate, the via comprising a conductive material;a second resistive material positioned on the first conductive material and the via; anda second conductive material positioned on the second resistive material.9. The memory device of claim 8 , wherein the first resistive material covers the plurality of memory stacks and fails to cover the via.10. The memory device of claim 8 , wherein a resistivity of the first resistive material is greater than a resistivity of the second resistive material.11. The memory device of claim 8 , further comprising a dielectric material positioned in a gap of the memory device claim 8 , the via extending through the dielectric material.12. The memory device of claim 11 , further comprising a liner material positioned in the gap so as to form a barrier between the dielectric material and the first resistive material and between the dielectric material and the first ...

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Номер записи: 34
17-01-2019 дата публикации

STRUCTURES INCORPORATING AND METHODS OF FORMING METAL LINES INCLUDING CARBON

Номер: US20190019947A1
Автор: Gealy F. Daniel, GOTTI ANDREA, Tortorelli Innocenzo, Varesi Enrico
Принадлежит:

Disclosed technology relates generally to integrated circuits, and more particularly, to structures incorporating and methods of forming metal lines including tungsten and carbon, such as conductive lines for memory arrays. In one aspect, a memory device comprises a lower conductive line extending in a first direction and an upper conductive line extending in a second direction and crossing the lower conductive line, wherein at least one of the upper and lower conductive lines comprises tungsten and carbon. The memory device additionally comprises a memory cell stack interposed at an intersection between the upper and lower conductive lines. The memory cell stack includes a first active element over the lower conductive line and a second active element over the first active element, wherein one of the first and second active elements comprises a storage element and the other of the first and second active elements comprises a selector element. The memory cell stack further includes an electrode interposed between the at least one of the upper and lower conductive lines and the closer of the first and second active elements. 1. A method , comprising:forming a lower conductive line extending in a first direction by patterning a lower conductive material over a substrate;forming an upper conductive line extending in a second direction by patterning an upper conductive material over the lower conductive line;forming a memory cell between the lower conductive line and the upper conductive line, the memory cell including at least one active element, wherein the lower conductive line and the at least one active element are patterned in the first direction using a single mask process, and the upper conductive line and the at least one active element are patterned in the second direction using a single mask process, such that the at least one active element is isolated in both first and second directions after forming the memory cell; andwherein the upper conductive line, ...

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Номер записи: 35
17-01-2019 дата публикации

Memory Cells, Memory Arrays, and Methods of Forming Memory Cells and Arrays

Номер: US20190019949A1
Автор: Cupeta Carmela, Pellizzer Fabio, Redaelli Andrea, Servalli Giorgio
Принадлежит: MICRON TECHNOLOGY, INC.

Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures. 1. A method of forming a memory array , comprising:forming heater structures over an array of electrical nodes; the heater structures being in one-to-one correspondence with the electrical nodes; the array having rows extending along a first direction and having columns extending along a second direction substantially orthogonal to the first direction;forming confined phase change material structures over the heater structures and in one-to-one correspondence with the heater structures, having lateral peripheries of phase change material, the array having x-direction axes extending through the confined phase change material structures along the first direction and y-direction axes extending through the confined phase change material structures along the second direction;forming bitlines across the confined phase change material structures, with the bitlines extending along the second direction;forming conductive material caps between and contacting the bitlines and the confined phase change material structures, the confined phase change material structures ...

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Номер записи: 36
17-01-2019 дата публикации

VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF FORMING THE SAME

Номер: US20190019950A1
Автор: Eun Sung-Ho, JEONG Ji-Hyun, Kim Sungwon, Park Ilmok, PARK JUNGHOON, Song Seulji
Принадлежит:

Variable resistance memory devices and methods of forming the same are provided. The variable resistance memory devices may include a substrate including a cell region and a peripheral region, first conductive lines on the substrate, second conductive lines traversing the first conductive lines, variable resistance structures at intersecting points of the first conductive lines and the second conductive lines, and bottom electrodes between the first conductive lines and the variable resistance structures. The cell region may include a boundary region contacting the peripheral region, and one of the first conductive lines is electrically insulated from one of the variable resistance structures that is on the boundary region and overlaps the one of the first conductive lines, 1. A variable resistance memory device comprising:a substrate comprising a cell region and a peripheral region, the cell region comprising a boundary region being in contact with the peripheral region;a plurality of first conductive lines extending in a first direction on the substrate;a plurality of second conductive lines extending in a second direction and traversing the plurality of first conductive lines;a plurality of variable resistance structures, each of the plurality of variable resistance structures being at one of a plurality of intersecting points of the plurality of first conductive lines and the plurality of second conductive lines; anda plurality of bottom electrodes between the plurality of first conductive lines and the plurality of variable resistance structures,wherein one of the plurality of first conductive lines is electrically insulated from one of the plurality of variable resistance structures that is on the boundary region and overlaps the one of the plurality of first conductive lines.2. The claim 1 , variable resistance memory device of claim 1 , further comprising:an insulating pattern that is on the boundary region and is between the one of the plurality of first ...

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Номер записи: 37
16-01-2020 дата публикации

INTERCONNECT LANDING METHOD FOR RRAM TECHNOLOGY

Номер: US20200020745A1
Автор: CHANG Chih-Yang, Chen Hsia-Wei, Chu Wen-Ting, Liao Yu-Wen, Tu Kuo-Chi, Yang Chin-Chieh, Yang Jen-Sheng
Принадлежит:

The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit has a first inter-level dielectric (ILD) layer over a substrate. A lower electrode is over the first ILD layer, a data storage structure is over the lower electrode, and an upper electrode is over the data storage structure. An upper interconnect wire directly contacts an entirety of an upper surface of the upper electrode. A conductive via directly contacts an upper surface of the upper interconnect wire. The conductive via has an outermost sidewall that is directly over the upper surface of the upper interconnect wire. 1. An integrated chip , comprising:a first inter-level dielectric (ILD) layer over a substrate;a lower electrode over the first ILD layer;a data storage structure over the lower electrode;an upper electrode over the data storage structure;an upper interconnect wire directly contacting an entirety of an upper surface of the upper electrode; anda conductive via directly contacting an upper surface of the upper interconnect wire, wherein the conductive via has an outermost sidewall that is directly over the upper surface of the upper interconnect wire.2. The integrated chip of claim 1 , further comprising:a sidewall spacer covering sidewalls of the lower electrode, the data storage structure, and the upper electrode.3. The integrated chip of claim 2 , further comprising:a second ILD layer over the first ILD layer and laterally separated from the data storage structure by the sidewall spacer.4. The integrated chip of claim 2 , wherein the upper interconnect wire laterally extends over a top of the sidewall spacer.5. The integrated chip of claim 2 , wherein the sidewall spacer comprises a first sidewall directly contacting the data storage structure and a second sidewall directly contacting the upper interconnect wire.6. The integrated chip of claim 2 , further comprising:an etch stop layer disposed on the sidewall spacer, wherein the sidewall spacer and ...

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Номер записи: 38
16-01-2020 дата публикации

TAPERED MEMORY CELL PROFILES

Номер: US20200020855A1
Автор: Pellizzer Fabio, Pirovano Agostino, Yastrebenetsky Kolya
Принадлежит:

Methods, systems, and devices for tapered memory cell profiles are described. A tapered profile memory cell may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a bottom surface and a top surface opposite the bottom surface. In some cases, the self-selecting memory component may taper from the bottom surface to the top surface. In other examples, the self-selecting memory component may taper from the top surface to the bottom surface. The top surface of the self-selecting memory component may be coupled to a top electrode, and the bottom surface of the self-selecting memory component may be coupled to a bottom electrode. 1. (canceled)2. A memory device , comprising:a self-selecting memory component extending in a first direction, the self-selecting memory component including a first surface and a second surface opposite the first surface, the first surface being coupled with a word line extending in the first direction, and the second surface being coupled with a plurality of digit lines extending in a second direction different from the first direction;a first electrode coupled with the first surface of the self-selecting memory component; anda second electrode coupled with the second surface of the self-selecting memory component and in electronic communication with the first electrode via the self-selecting memory component, wherein a first area of the first surface contacting the first electrode is greater than a second area of the second surface contacting the second electrode.3. The memory device of claim 2 , wherein the first area of the first surface and the second area of the second surface determines a ratio.4. The memory device of claim 3 , wherein the ratio is configured to define a sense window associated with the self-selecting memory component by crowding ions at or near the first electrode or the second ...

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Номер записи: 39
16-01-2020 дата публикации

RRAM CELL STRUCTURE WITH CONDUCTIVE ETCH-STOP LAYER

Номер: US20200020856A1
Автор: Hsu Chern-Yow, Liu Ming Chyi, Liu Shih-Chang, Tsai Chia-Shiung, Tseng Yuan-Tai
Принадлежит:

The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode. 1. A resistive random access memory (RRAM) device comprising:a semiconductor substrate;a metal interconnect structure disposed within a low-k dielectric layer and disposed over the semiconductor substrate;a conductive etch-stop layer (CESL) abutting an upper surface of the metal interconnect structure;a bottom electrode structure over the CESL;a variable resistance dielectric structure over the bottom electrode structure;a top electrode structure over the variable resistance dielectric structure;sidewall spacers about outer sidewalls of the top electrode structure; andwherein outer sidewalls of the bottom electrode structure are spaced apart by a first distance, and outer sidewalls of the top electrode structure are spaced apart by a second distance which is less than the first distance;wherein the CESL is a transitional metal nitride layer having an etch-selectivity that differs from an etch-selectivity of the bottom electrode structure.2. The RRAM device of claim 1 , wherein the bottom electrode structure is a single conductive electrode layer.3. The RRAM device of claim 1 , ...

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Номер записи: 40
21-01-2021 дата публикации

MEMORY DEVICE AND A METHOD FOR FORMING THE MEMORY DEVICE

Номер: US20210020834A1
Автор: Loy Desmond Jia Jun, Tan Shyue Seng, Toh Eng Huat
Принадлежит:

A memory device may include at least one inert electrode, at least one mask element arranged over the at least one inert electrode, a switching layer arranged over the at least one mask element and the at least one inert electrode, and at least one active electrode arranged over the switching layer. Both of the at least one mask element and the switching layer may be in contact with a top surface of the at least one inert electrode. The switching layer in this memory device may thus include corners at which the conductive filaments may be confined. This memory device may be formed with a process that may utilize the at least one mask element to help reduce the chances of shorting between the inert and active electrodes. 1. A memory device comprising:at least one inert electrode;at least one mask element arranged over the at least one inert electrode;a switching layer arranged over the at least one mask element and the at least one inert electrode, wherein both of the at least one mask element and the switching layer are in contact with a top surface of the at least one inert electrode; andat least one active electrode arranged over the switching layer.2. The memory device of claim 1 , wherein the at least one inert electrode comprises two or more inert electrodes separated from each other.3. The memory device of claim 2 , wherein the memory device further comprises an insulating layer below the at least one mask element and wherein the two or more inert electrodes are arranged within the insulating layer.4. The memory device of claim 1 , wherein the at least one inert electrode comprises only a single inert electrode.5. The memory device of claim 1 , wherein the at least one active electrode comprises two or more active electrodes separated from each other.6. The memory device of claim 1 , wherein the at least one active electrode comprises only a single active electrode.7. The memory device of claim 1 , wherein the at least one mask element comprises only a single ...

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Номер записи: 41
21-01-2021 дата публикации

FABRICATION OF PHASE CHANGE MEMORY CELL IN INTEGRATED CIRCUIT

Номер: US20210020836A1
Автор: Kim Andrew Tae, Li Baozhen, Linder Barry, Yang Chih-Chao
Принадлежит:

A phase change memory (PCM) cell in an integrated circuit and a method of fabricating it involve depositing a layer of PCM material on a surface of a dielectric, and patterning the layer of PCM material into a plurality of PCM blocks. Heater material is formed on both sidewalls of each of the plurality of the PCM blocks to form a plurality of PCM cells. Each of the plurality of the PCM blocks and the heater material on both the sidewalls represents a PCM cell. An additional layer of the dielectric is deposited above and between the plurality of the PCM cells, and trenches are formed in the dielectric. Trenches are formed in contact with each side of each of the plurality of the PCM cells. Metal is deposited in each of the trenches. Current flow in the metal heats the heater material of one of the PCM cells. 1. A structure used to form a memory devices within an integrated circuit , the structure comprising:a plurality of phase change memory (PCM) cells, wherein each PCM cell includes PCM material between heater material on a first side and a second side of the PCM material;a plurality of metal components, wherein the heater material on the first side of the PCM material and the heater material on the second side of the PCM material of each of the plurality of the PCM cells is in contact with one of the plurality of the metal components; anddielectric directly above and below the plurality of the PCM cells.2. The structure according to claim 1 , wherein the heater material is tantalum nitride (TaN).3. The structure according to claim 1 , wherein the metal is copper (Cu) claim 1 , aluminum (Al) claim 1 , ruthenium (Ru) claim 1 , cobalt (Co) claim 1 , or tungsten (W).4. The structure according to claim 1 , wherein the PCM material is germanium-antimony-tellurium (GST).5. The structure according to claim 1 , wherein the plurality of metal components are metal wires.6. The structure according to claim 5 , further comprising a first metal level below the dielectric claim ...

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Номер записи: 42
28-01-2016 дата публикации

Semiconductor device and method for fabricating the same, and microprocessor, processor, system, data storage system and memory system including the semiconductor device

Номер: US20160028011A1
Автор: Hye-Jung Choi, Su-Ock Chung
Принадлежит: SK hynix Inc

A semiconductor device includes first lines extending in a first direction; second lines extending in a second direction crossing with the first direction; and first resistance variable elements defined between the first lines and the second lines and each including a first substance layer and a second substance layer, wherein the first substance layer extends in the first direction and the second substance layer extends in the second direction.

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Номер записи: 43
24-04-2014 дата публикации

NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20140110659A1
Автор: Himeno Atsushi, Kawashima Yoshio, Mikawa Takumi, Murase Hideaki
Принадлежит: Panasonic Corporation

A method of manufacturing a nonvolatile memory device includes: forming a first electrode; forming, above the first electrode, a metal oxide material layer including a first metal oxide; forming a mask above part of the metal oxide material layer main surface; forming, in a region of the metal oxide material layer not covered by the mask, a high oxygen concentration region including a second metal oxide having a lower degree of oxygen deficiency than the first metal oxide; removing the mask; forming, above a first variable resistance layer including the high oxygen concentration region and a low oxygen concentration region that is a region of the metal oxide material layer other than the high oxygen concentration region, a second variable resistance layer including a third metal oxide having a lower degree of oxygen deficiency than the first metal oxide; and forming a second electrode above the second variable resistance layer. 1. A method of manufacturing a nonvolatile memory device , the method comprising:forming a first electrode;forming, above the first electrode, a metal oxide material layer comprising a first metal oxide;forming a mask above a portion of a main surface of the metal oxide material layer;forming, in a region of the metal oxide material layer not covered by the mask, a high oxygen concentration region comprising a second metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first metal oxide;removing the mask;forming, above a first variable resistance layer including the high oxygen concentration region and a low oxygen concentration region, a second variable resistance layer comprising a third metal oxide having a degree of oxygen deficiency lower than the degree of oxygen deficiency of the first metal oxide, the low oxygen concentration region being a region of the metal oxide material layer other than the high oxygen concentration region; andforming a second electrode above the second variable ...

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Номер записи: 44
10-02-2022 дата публикации

PATTERNING OXIDATION RESISTANT ELECTRODE IN CROSSBAR ARRAY CIRCUITS

Номер: US20220045271A1
Автор: GE NING, Zhang Minxian
Принадлежит:

An example method includes: forming a bottom electrode on a substrate and forming a patterned mask layer on the bottom electrode; thermal oxidizing the bottom electrode layer via the patterned mask layer by applying a thermal process and a first plasma; removing a gaseous status of the bottom electrode oxide using a first vacuum purge; removing a solid status of the bottom electrode oxide by applying a second plasma; removing the gaseous status and the solid status of the bottom electrode oxide using a second vacuum purge to form a patterned bottom electrode; removing the patterned mask layer; forming a filament forming layer on the patterned bottom electrode; and a top electrode on the filament forming layer. The filament forming layer is configured to form a filament within the filament forming layer responsive to a switching voltage being applied to the filament forming layer. 1. A method of manufacturing an RRAM-based crossbar array circuit comprising:providing a substrate;forming a bottom electrode on the substrate;forming a patterned mask layer on the bottom electrode;thermal oxidizing the bottom electrode layer via the patterned mask layer by applying a thermal process and a first plasma;removing a gaseous status of the bottom electrode oxide by a first vacuum purge;removing a solid status of the bottom electrode oxide by applying a second plasma;removing the gaseous status of the bottom electrode oxide and the solid status of the bottom electrode oxide by a second vacuum purge to form a patterned bottom electrode;removing the patterned mask layer;forming a filament forming layer on the patterned bottom electrode; andforming a top electrode on the filament forming layer, wherein the filament forming layer is configured to form a filament within the filament forming layer when applying a switching voltage upon the filament forming layer.2. The method as claimed in claim 1 , wherein the first plasma comprises an oxygen plasma.3. The method as claimed in claim 1 ...

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Номер записи: 45
24-01-2019 дата публикации

Resistance change memory device and fabrication method thereof

Номер: US20190027683A1
Автор: Frederick Chen
Принадлежит: Winbond Electronics Corp

The resistance change memory device including a first resistance change memory element, a second resistance change memory element, and a memory controller is provided. The first resistance change memory element is disposed on a chip. The second resistance change memory element is disposed on the same chip. The memory controller is disposed on the same chip. The memory controller is configured to control data access of the first resistance change memory element and the second resistance change memory element. An accessing frequency of the first resistance change memory element is different from an accessing frequency of the second resistance change memory element.

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Номер записи: 46
24-04-2014 дата публикации

Phase-change random access memory device and method of manufacturing the same

Номер: US20140113427A1
Автор: Nam Kyun PARK
Принадлежит: SK hynix Inc

A phase-change random access memory (PCRAM) device includes a semiconductor substrate; switching elements formed on the semiconductor substrate; a plurality of phase-change structures formed on the switching elements; and heat absorption layers buried between the plurality of phase-change structures, wherein the plurality of phase-change structures are insulated from the heat absorption layers.

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Номер записи: 47
24-04-2014 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE

Номер: US20140113430A1
Автор: Hayakawa Yukio, Himeno Atsushi, Kawashima Yoshio, Mikawa Takumi, Murase Hideaki
Принадлежит: Panasonic Corporation

A method of manufacturing a semiconductor device according to the present invention includes: forming a lower electrode above a substrate; forming, above the lower electrode, a first variable resistance layer comprising a first metal oxide; forming a step region in the first variable resistance layer by collision of ions excited by plasma; removing residue of the first variable resistance layer created in the forming of the step region; forming a second variable resistance layer which covers the step region of the first variable resistance layer, comprises a second metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first metal oxide, and has a bend on a step formed along an edge of the step region; and forming an upper electrode above the second variable resistance layer. 1. A method of manufacturing a semiconductor memory device , comprising:forming a lower electrode above a substrate;forming a first variable resistance layer above the lower electrode, the first variable resistance layer comprising a first metal oxide;forming a step in a top face of the first variable resistance layer by causing ions excited by plasma to collide with a part of the top face of the first variable resistance layer;removing residue of the first variable resistance layer remaining on the step, after the step is formed;forming a second variable resistance layer covering the step of the first variable resistance layer, after the residue is removed, the second variable resistance layer comprising a second metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first metal oxide and having a bend on a surface above the step; andforming an upper electrode above the second variable resistance layer.2. The method of manufacturing a semiconductor memory device according to claim 1 ,wherein, in the removing of residue, the residue of the first variable resistance layer remaining on the step is removed while ...

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Номер записи: 48
23-01-2020 дата публикации

RRAM MEMORY CELL WITH MULTIPLE FILAMENTS

Номер: US20200027924A1
Автор: CHANG Chih-Yang, Chu Wen-Ting, Liao Yu-Wen, Yang Chin-Chieh
Принадлежит:

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a conductive element disposed within a dielectric structure over the substrate. The conductive element has a top surface extend between outermost sidewalls of the conductive element. A first resistive random access memory (RRAM) element is arranged within the dielectric structure and has a first data storage layer directly contacting the top surface of the conductive element. A second RRAM element is arranged within the dielectric structure and has a second data storage layer directly contacting the top surface of the conductive element. 1. An integrated chip , comprising:a conductive element disposed within a dielectric structure over a substrate, wherein the conductive element comprises a top surface extending between outermost sidewalls of the conductive element;a first resistive random access memory (RRAM) element arranged within the dielectric structure and having a first data storage layer directly contacting the top surface of the conductive element; anda second RRAM element arranged within the dielectric structure and having a second data storage layer directly contacting the top surface of the conductive element.2. The integrated chip of claim 1 , wherein a bottom surface of the conductive element has smaller width than the top surface of the conductive element.3. The integrated chip of claim 2 , further comprising:one or more lower interconnect layers disposed within a lower inter-level dielectric (ILD) structure that is between the bottom surface of the conductive element and the substrate.4. The integrated chip of claim 3 , wherein the conductive element is a different material than the one or more lower interconnect layers.5. The integrated chip of claim 3 , further comprising:an insulating layer disposed over the lower ILD structure and laterally surrounding a part of the conductive element, wherein the conductive element has a lower surface that is ...

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Номер записи: 49
23-01-2020 дата публикации

CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME

Номер: US20200027926A1
Автор: Sciarrillo Samuele
Принадлежит:

The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls. The memory device additionally comprises first protective dielectric insulating materials formed on a lower portion of the first pair of sidewalls and an isolation dielectric formed on the first protective dielectric insulating material and further formed on an upper portion of the first pair of sidewalls.

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Номер записи: 50
23-01-2020 дата публикации

Resistive memory crossbar array with top electrode inner spacers

Номер: US20200028076A1
Автор: Hiroyuki Miyazoe, Iqbal R. Saraf, Shyng-Tsong Chen, Takashi Ando
Принадлежит: International Business Machines Corp

A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming conductive lines within an interlayer dielectric (ILD), forming a metal nitride layer over at least one conductive line, forming a bottom electrode, forming a RRAM stack over the metal nitride layer, the RRAM stack including a first top electrode and a second top electrode, undercutting the second top electrode to define recesses, and filling the recesses with inner spacers.

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Номер записи: 51
23-01-2020 дата публикации

METAL LANDING ON TOP ELECTRODE OF RRAM

Номер: US20200028077A1
Автор: CHANG Chih-Yang, Chu Wen-Ting
Принадлежит:

Some embodiments relate to an integrated circuit including one or more memory cells arranged over a semiconductor substrate between an upper metal interconnect layer and a lower metal interconnect layer. A memory cell includes a bottom electrode disposed over the lower metal interconnect layer, a data storage or dielectric layer disposed over the bottom electrode, and a top electrode disposed over the data storage or dielectric layer. An upper surface of the top electrode is in direct contact with the upper metal interconnect layer without a via or contact coupling the upper surface of the top electrode to the upper metal interconnect layer. Sidewall spacers are arranged along sidewalls of the top electrode, and have bottom surfaces that rest on an upper surface of the data storage or dielectric layer. 1. An integrated circuit (IC) including one or more memory cells arranged over a semiconductor substrate between an upper metal interconnect layer and a lower metal interconnect layer , a memory cell comprising:a bottom electrode disposed over the lower metal interconnect layer;a data storage or dielectric layer disposed over the bottom electrode;a top electrode disposed over the data storage or dielectric layer, wherein an upper surface of the top electrode is in direct contact with the upper metal interconnect layer without a via or contact coupling the upper surface of the top electrode to the upper metal interconnect layer; andsidewall spacers arranged along sidewalls of the top electrode, and having bottom surfaces that rest on an upper surface of the data storage or dielectric layer.2. The IC of claim 1 , wherein the top electrode has an upper planar surface which extends continuously between sidewalls of the top electrode and which directly abuts the upper metal interconnect layer.3. The IC of claim 2 , wherein the bottom electrode has sidewalls which are aligned with the sidewalls of the top electrode.4. The IC of claim 1 , further comprising:a capping layer ...

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Номер записи: 52
23-01-2020 дата публикации

Resistive memory crossbar array compatible with cu metallization

Номер: US20200028080A1
Автор: Lawrence A. Clevenger, Michael RIZZOLO, Shyng-Tsong Chen, Takashi Ando
Принадлежит: International Business Machines Corp

A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a RRAM stack including a bottom electrode, a top electrode, and a bi-layer hardmask, forming a low-k dielectric layer over the RRAM stack, removing a first layer of the bi-layer hardmask during a via opening, and removing a second layer of the bilayer hardmask concurrently with a plurality of sacrificial layers formed over the low-k dielectric layer.

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Номер записи: 53
28-01-2021 дата публикации

CROSSBAR ARRAY CIRCUIT WITH 3D VERTICAL RRAM

Номер: US20210028230A1
Автор: GE NING, Zhang Minxian
Принадлежит: TETRAMEM INC.

Provided are 3D One-Transistor-N-RRAM (1TNR) structures and One-Selector-One-RRAM (1S1R) structures and methods for manufacturing the same. An example 3D 1TNR structure comprises: a plurality of gate lines; and a plurality of crossbar arrays (e.g., a first crossbar array and a second crossbar array). The first and second crossbar arrays are positioned on a first vertical plane and a second vertical plane, respectively. Each crossbar array in the plurality of crossbar arrays includes a first plurality of bit lines and a second plurality of word lines; Each word line in the second plurality of word lines is connected to a source and a destination of a second transistor; and each gate line in the plurality of gate lines is connected to a gate of a first transistor located in the first crossbar array and a gate of a second transistor located in the second crossbar array. 1. A 3D One-Transistor-N-RRAM (1TNR) structure comprising:a plurality of gate lines; and the first crossbar array is positioned on a first vertical plane;', 'the second crossbar array is positioned on a second vertical plane different from the first vertical plane;', 'each crossbar array in the plurality of crossbar arrays includes a first plurality of bit lines and a second plurality of word lines;', 'each word line in the second plurality of word lines is connected to a source and a destination of a second transistor;', 'each gate line in the plurality of gate lines is connected to a gate of a first transistor located in the first crossbar array and a gate of a second transistor located in the second crossbar array., 'a plurality of crossbar arrays, including a first crossbar array and a second crossbar array, wherein'}2. The 3D One-Transistor-N-RRAM (1TNR) structure of claim 1 , wherein the plurality of crossbar arrays includes a third crossbar array positioned on a third vertical plane different from both the first crossbar array and the second crossbar array.3. The 3D One-Transistor-N-RRAM (1TNR) ...

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Номер записи: 54
28-01-2021 дата публикации

RESISTIVE RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF

Номер: US20210028358A1
Автор: Gao Bin, Qian He, Wu Huaqiang, Wu Wei
Принадлежит: TSINGHUA UNIVERSITY

A resistive random access memory and a manufacture method thereof are provided. The resistive random access memory includes: a first electrode, a second electrode, a resistive layer between the first electrode and the second electrode, and at least one thermal enhanced layer; the thermal enhanced layer is adjacent to the resistive layer, and a thermal conductivity of the thermal enhanced layer is less than a thermal conductivity of the first electrode and a thermal conductivity of the second electrode. 120-. (canceled)21: A resistive random access memory , comprising:a first electrode;a second electrode;a resistive layer between the first electrode and the second electrode; andat least one thermal enhanced layer, wherein the at least one thermal enhanced layer is adjacent to the resistive layer, and a thermal conductivity of the at least one thermal enhanced layer is less than a thermal conductivity of the first electrode and a thermal conductivity of the second electrode,{'sup': 2', '2, 'an electrical conductivity of a material of the at least one thermal enhanced layer ranges from 10 μΩ/cmto 10 Ω/cm,'}the at least one thermal enhanced layer and the resistive layer are independent of each other, andthe at least one thermal enhanced layer is on at least one side of the resistive layer.22: The resistive random access memory according to claim 21 , wherein the thermal conductivity of the first electrode and/or the thermal conductivity of the second electrode are/is twice claim 21 , five times or more than ten times as high as the thermal conductivity of the at least one thermal enhanced layer.23: The resistive random access memory according to claim 21 , wherein the thermal conductivity of a material of the at least one thermal enhanced layer ranges from 0.01 W·m·Kto 20 W·m·K.24: The resistive random access memory according to claim 21 , wherein the at least one side of the resistive layer comprises a top side of the resistive layer claim 21 , or the at least one side ...

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Номер записи: 55
01-05-2014 дата публикации

MEMORY ELEMENTS USING SELF-ALIGNED PHASE CHANGE MATERIAL LAYERS AND METHODS OF MANUFACTURING SAME

Номер: US20140117300A1
Автор: Liu Jun
Принадлежит: MICRON TECHNOLOGY, INC.

A memory element and method of forming the same. The memory element includes a first electrode within a via in a first dielectric material. An insulating material element is positioned over and in contact with the first electrode. A phase change material is positioned over the first electrode and in contact with sidewalls of the insulating material element. The phase change material has a first surface in contact with a surface of the first electrode and a surface of the first dielectric material. A second electrode is in contact with a second surface of the phase change material, which is opposite to the first surface. 1. A memory element comprising:a first dielectric material having a via therein;a first electrode within the via;an insulating material element positioned over and in contact with the first electrode;a phase change material positioned over the first electrode and in contact with sidewalls of the insulating material element, the phase change material having a first surface in contact with a surface of the first electrode and a surface of the first dielectric material; anda second electrode in contact with a second surface of the phase change material, the second surface of the phase change material being opposite the first surface.2. The memory element of claim 1 , wherein said phase change material is in contact with a top surface of the insulating material element.3. The memory element of claim 1 , wherein a top surface of the insulating material element is planar to a top surface of the phase change material.4. The memory element of claim 1 , wherein a top surface of the insulating material element is below a top surface of the phase change material.5. The memory element of claim 4 , wherein a top surface of the second electrode is planar to a top surface of the phase change material.6. The memory element of claim 1 , wherein the phase change material has first and second diameters.7. The memory element of claim 6 , wherein the first and second ...

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Номер записи: 56
04-02-2016 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

Номер: US20160035792A1
Автор: Imamura Tsubasa, Sasaki Toshiyuki, Takahashi Atsushi
Принадлежит:

According to one embodiment, a semiconductor memory device includes a substrate including a major surface; a plurality of first films having conductivity or semiconductivity, the first films being provided above the substrate and extending in a first direction inclined with respect to the major surface; a plurality of second films having conductivity, the second films being provided above the substrate and extending in a second direction inclined with respect to the major surface and crossing the first direction; and a plurality of storage films provided in crossing sections of the first films and the second films. 1. A semiconductor memory device comprising:a substrate including a major surface;a plurality of first films having conductivity or semiconductivity, the first films being provided above the substrate and extending in a first direction inclined with respect to the major surface;a plurality of second films having conductivity, the second films being provided above the substrate and extending in a second direction inclined with respect to the major surface and crossing the first direction; anda plurality of storage films provided in crossing sections of the first films and the second films.2. The device according to claim 1 , wherein the first films pierce through layered second films.3. The device according to claim 1 , whereina stacked body including a plurality of electrode films as the second films and a plurality of insulating films respectively provided among the electrode films is provided above the substrate,a plurality of semiconductor bodies as the first films extend in the first direction piercing through the stacked body, andthe storage films include charge storage films provided between the electrode films and the semiconductor bodies.4. The device according to claim 3 , whereinthe storage films extend continuously in the first direction, anda plurality of columnar sections including the storage films and the semiconductor bodies extend in the ...

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Номер записи: 57
04-02-2016 дата публикации

ELECTRONIC DEVICE COMPRISING SEMICONDUCTOR MEMORY USING METAL ELECTRODE AND METAL COMPOUND LAYER SURROUNDING SIDEWALL OF THE METAL ELECTRODE

Номер: US20160035972A1
Автор: Lee Min-Suk, Shin Chang-Hyup
Принадлежит:

This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a lower electrode, a variable resistance element over the lower electrode, an upper electrode disposed over the variable resistance element and including metal, and a metal compound layer configured to surround a side of the upper electrode. The metal compound layer includes a compound of the metal of the upper electrode. 117-. (canceled)18. A method of manufacturing an electronic device comprising semiconductor memory , comprising:forming a material layer for forming a variable resistance element over a substrate;forming a metal layer over the material layer;forming a mask pattern over the metal layer;forming a metal layer pattern by etching the metal layer using the mask pattern as an etch barrier;transforming an external part of the metal layer pattern, corresponding to a specific width from an external side of the metal layer pattern, into a metal compound layer by performing surface treatment on the metal layer pattern to have a low etch rate as an etch barrier; andetching the material layer using the metal layer pattern and the metal compound layer as an etch barrier to form a variable resistance element having an external side aligned with an external side of the metal compound layer.19. The method of claim 18 , wherein the forming of the material layer includes forming a sequentially stack structure including a first magnetic layer claim 18 , a tunnel barrier layer claim 18 , and a second magnetic layer.20. The method of claim 18 , wherein the forming of the material layer comprises forming a metal oxide layer.21. The method of claim 18 , wherein the forming of the material layer comprises forming a phase change material layer.22. The method of claim 18 , wherein the surface treatment is performed using plasma treatment or thermal ...

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Номер записи: 58
04-02-2016 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20160035976A1
Автор: Mikawa Takumi, Okada Takashi
Принадлежит:

Provided are a variable resistance semiconductor memory device which changes its resistance without being affected by an underlying layer and is suitable as a memory device of increased capacity, and a method of manufacturing the same. The semiconductor memory device in the present invention includes: a first contact plug formed inside a first contact hole penetrating through a first interlayer insulating layer; a lower electrode having a flat top surface and is thicker above the first interlayer insulating layer than above the first contact plug; a variable resistance layer; and an upper electrode. The lower electrode, the variable resistance layer, and the upper electrode compose a variable resistance element. 110-. (canceled)11. A method of manufacturing a semiconductor memory device which includes a variable resistance element comprising:a lower electrode;a variable resistance layer formed on the lower electrode and including a first variable resistance layer comprising a transition metal oxide and a second variable resistance layer comprising a transition metal oxide having an oxygen content percentage higher than an oxygen content percentage of the transition metal oxide in the first variable resistance layer; andan upper electrode formed on the variable resistance layer,said method comprising:forming a first lower conductive layer on a semiconductor substrate;forming a first interlayer insulating layer on the semiconductor substrate so as to cover the first conductive layer;forming a first contact hole penetrating through the first interlayer insulating layer down to the first conductive layer;forming a first contact plug inside the first contact hole so that a recess is formed from a top surface of the first interlayer insulating layer toward the substrate;depositing a lower electrode material film on the first interlayer insulating layer so as to cover the first contact plug;forming the lower electrode having a flat, continuous top surface by planarizing ...

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Номер записи: 59
04-02-2016 дата публикации

MEMORY ELEMENTS USING SELF-ALIGNED PHASE CHANGE MATERIAL LAYERS AND METHODS OF MANUFACTURING SAME

Номер: US20160035977A1
Автор: Liu Jun
Принадлежит:

A memory element and method of forming the same. The memory element includes a first electrode within a via in a first dielectric material. An insulating material element is positioned over and in contact with the first electrode. A phase change material is positioned over the first electrode and in contact with sidewalls of the insulating material element. The phase change material has a first surface in contact with a surface of the first electrode and a surface of the first dielectric material. A second electrode is in contact with a second surface of the phase change material, which is opposite to the first surface. 110-. (canceled)11. A method of forming a memory element , the method comprising the acts of:forming a first dielectric material;forming a via within the first dielectric material;forming a first electrode within the via;forming an insulating material element in contact with the first electrode;forming a phase change material in contact with sidewalls of the insulating material element, over and in contact with a surface of the first dielectric material, over and in contact with a surface of the first electrode;forming a second dielectric material over and in contact with the phase change material;exposing at least a portion of a top surface of the phase change material;forming a second electrode in contact with the exposed surface of the phase change material and in contact with a top surface of the second dielectric material; andetching the second electrode, second dielectric material and phase change material but leaving the phase change material extending over at least a portion of the surface of the first electrode.12. The method of claim 11 , wherein the phase change material is formed in contact with an uppermost surface of the insulating material element.13. The method of claim 11 , wherein the second electrode claim 11 , second dielectric material and phase change material are etched during a same etch process.14. The method of claim 11 , ...

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Номер записи: 60
17-02-2022 дата публикации

SEMICONDUCTOR DEVICE INCLUDING DATA STORAGE MATERIAL PATTERN AND SELECTOR MATERIAL PATTERN

Номер: US20220052113A1
Автор: Ahn Dongho, CHOI Soyeon, KIM Chungman, LEE Jabin, LEE Jinwoo, PARK Kwangmin, WU Zhe, YU Seunggeun
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor device includes a lower insulating structure covering a circuit element on a semiconductor substrate and an upper structure on the lower insulating structure. The upper structure includes a memory cell structure between first and second conductive lines. The first conductive lines extend in a first horizontal direction, and the second conductive lines extend in a second horizontal direction. The memory cell structure includes at least three electrode patterns, a data storage material pattern, and a selector material pattern overlapping in a vertical direction. The selector material pattern includes a threshold switching material and a metal material. The threshold switching material includes germanium (Ge), arsenic (As), and selenium (Se), and the metal material includes at least one of tungsten (W), titanium (Ti), aluminum (Al), and copper (Cu). A content of the metal material is greater than 0 atomic % and less than 2 atomic %. 1. A semiconductor device comprising:a semiconductor substrate;a circuit element on the semiconductor substrate;a lower insulating structure covering the circuit element;circuit interconnections in the lower insulating structure, the circuit interconnections being on the semiconductor substrate and electrically connected to the circuit element; andan upper structure on the lower insulating structure,the upper structure including first conductive lines, second conductive lines, and a memory cell structure between the first conductive lines and the second conductive lines,the first conductive lines extending in a first horizontal direction,the second conductive lines extending in a second horizontal direction, perpendicular to the first horizontal direction,the memory cell structure including at least three electrode patterns, a data storage material pattern, and a selector material pattern overlapping each other in a vertical direction,the selector material pattern includes a threshold switching material and a metal material, ...

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Номер записи: 61
31-01-2019 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20190035852A1
Автор: Konno Takuya
Принадлежит: Toshiba Memory Corporation

According to an embodiment, a semiconductor memory device comprises first wiring lines, second wiring lines, and first variable resistance elements. The first wiring lines are arranged in a first direction and have as their longitudinal direction a second direction intersecting the first direction. The second wiring lines are arranged in the second direction and have the first direction as their longitudinal direction. The first variable resistance elements are respectively provided at intersections of the first wiring lines and the second wiring lines. In addition, this semiconductor memory device comprises a first contact extending in a third direction that intersects the first direction and second direction and having one end thereof connected to the second wiring line. The other end and a surface intersecting the first direction of this first contact are covered by a first conductive layer. 1a plurality of first wiring lines arranged in a first direction and having as their longitudinal direction a second direction intersecting the first direction;a plurality of second wiring lines arranged in the second direction and having the first direction as their longitudinal direction;a plurality of first variable resistance elements respectively provided at intersections of the first wiring lines and the second wiring lines; anda first contact extending in a third direction intersecting the first direction and second direction, one end of the first contact being connected to the second wiring line,the other end of the first contact and a surface intersecting the first direction of the first contact being covered by a first conductive layer.. A semiconductor memory device, comprising: This application is a continuation of and claims the benefit of priority under 35 U.S.C. § 120 from U.S. application Ser. No. 15/791,514 filed Oct. 24, 2017, which is a continuation of U.S. application Ser. No. 15/077,026 filed Mar. 22, 2016 (now U.S. Pat. No. 9,812,502 issued Nov. 7, 2017 ...

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Номер записи: 62
31-01-2019 дата публикации

APPARATUS AND METHODS FOR ELECTRICAL SWITCHING

Номер: US20190036021A1
Автор: Choi Shinhyun, Kim Jeehwan
Принадлежит:

Electrical switching technologies employ the otherwise undesirable line defect in crystalline materials to form conductive filaments. A switching cell includes a crystalline layer disposed between an active electrode and another electrode. The crystalline layer has at least one channel, such as a line defect, extending from one surface of the crystalline layer to the other surface. Upon application of a voltage on the two electrodes, the active electrode provides metal ions that can migrate from the active electrode to the other electrode along the line defect, thereby forming a conductive filament. The switching cell can precisely locate the conductive filament within the line defect and increase the device-to-device switching uniformity. 1. A method of actuating a device comprising a crystalline layer having at least one channel extending from a first side of the crystalline layer to a second side of the crystalline layer , a first electrode comprising an active material disposed on the first side of the crystalline layer , and a second electrode disposed on the second side of the crystalline layer , the method comprising:applying a first voltage, having a first sign, across the first electrode and the second electrode, the first voltage causing a plurality of metal ions of the active material to form a conductive filament extending between the first electrode and the second electrode along the at least one channel.2. The method of claim 1 , further comprising:applying a second voltage, having a second sign opposite to the first sign, between the first electrode and the second electrode to cause the plurality of metal ions to retreat back to the first electrode.3. The method of claim 1 , wherein the first voltage is about 4 V to about 6 V.4. The method of claim 1 , further comprising:maintaining the conductive filament in the at least one channel upon removal of the first voltage.5. A method of fabricating an electrical switching device claim 1 , the method ...

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Номер записи: 63
31-01-2019 дата публикации

SELF-ALIGNED MEMORY DECKS IN CROSS-POINT MEMORY ARRAYS

Номер: US20190036022A1
Автор: Conti Anna Maria, Pellizzer Fabio, Pirovano Agostino, Redaelli Andrea, Tortorelli Innocenzo
Принадлежит:

A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck. 1. A method of fabricating an electronic device comprising:forming, on a substrate, a first electrode layer and a first self-selecting memory stack on the first electrode layer, wherein the first self-selecting memory stack comprises a first layer of chalcogenide glass for both selection and storage;etching, in a first etching operation, the first electrode layer and the first self-selecting memory stack to form a first set of rows extending in a first direction on the substrate, each row of the first set of rows comprising remaining portions of the first electrode layer and the first self-selecting memory stack;forming a second electrode layer and a second self-selecting memory stack on the first set of rows, wherein the second self-selecting memory stack comprises a second layer of chalcogenide glass for both selection and storage;etching, in a second etching operation, the second electrode layer and the second self-selecting memory stack to form a first set of columns extending in a second direction on the first set of rows, each column of the first set of columns comprising remaining portions of the ...

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Номер записи: 64
30-01-2020 дата публикации

TIGHTLY INTEGRATED 1T1R ReRAM FOR PLANAR TECHNOLOGY

Номер: US20200035915A1
Автор: Ando Takashi, Hashemi Pouya, Reznicek Alexander
Принадлежит:

A semiconductor structure includes an oxide ReRAM co-integrated with a drain region of a field effect transistor (FET). The oxide ReRAM has a tip region defined by a pointed cone that contacts a faceted upper surface of the drain region of the FET. Such a tip region enhances the electric field of the oxide ReRAM and thus helps to control forming of the conductive filament of the oxide ReRAM. 110-. (canceled)11. A method of forming a semiconductor structure , the method comprising:providing a sacrificial gate structure on a surface of a semiconductor substrate, wherein a first dielectric spacer and a second dielectric spacer laterally surround the sacrificial gate structure;forming a source region and a drain region in the semiconductor substrate and on opposite sides of the sacrificial gate structure, wherein the source region and the drain region have faceted sidewall surfaces;performing a self-limiting etch of the drain region to provide a faceted upper surface to the drain region, wherein an interlayer dielectric (ILD) material layer protects the source region during the performing of the self-limiting etch; andforming elements of an oxide resistive random access memory (ReRAM) device in contact with the faceted upper surface of the drain region.12. The method of claim 11 , further comprising replacing claim 11 , after the forming of the elements of the ReRAM device claim 11 , the sacrificial gate structure with a functional gate structure claim 11 , wherein the functional gate structure comprises a gate dielectric material portion and a gate conductor portion.13. The method of claim 12 , further comprising forming a source contact structure contacting the source region claim 12 , a gate contact structure contacting the gate conductor portion claim 12 , and a ReRAM contact structure contacting a top electrode of the ReRAM device.14. The method of claim 11 , wherein the forming of the elements of ReRAM device comprises forming a resistive switching layer and a top ...

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Номер записи: 65
30-01-2020 дата публикации

Multi-layer structure to increase crystalline temperature of a selector device

Номер: US20200035916A1
Автор: Hai-Dang Trinh
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

In some embodiments, a semiconductor device is provided. The semiconductor device includes a first amorphous switching structure disposed over a first electrode. A buffer structure is disposed over the first amorphous switching structure. A second amorphous switching structure is disposed over the buffer structure. A second electrode is disposed over the second amorphous switching structure, where the first and second amorphous switching structures are configured to switch between low resistance states and high resistance states depending on whether a voltage from the first electrode to the second electrode exceeds a threshold voltage.

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Номер записи: 66
30-01-2020 дата публикации

VIA Structure and Methods of Forming the Same

Номер: US20200035918A1
Автор: Chen Jieh-Jang, Hsu Chern-Yow, HUANG WEI-CHIEH, Shiu Feng-Jia
Принадлежит:

A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column. 1. A method comprising:forming a dielectric layer over a first electrode;forming a plurality of sacrificial blocks over the dielectric layer;forming a first sacrificial layer covering the plurality of sacrificial blocks, the first sacrificial layer having a dip directly above the first electrode;removing a portion of the first sacrificial layer and a portion of the dielectric layer through the dip to expose the first electrode; andforming a conductive material in the dip such that the conductive material extends to the first electrode.2. The method of claim 1 , wherein the forming of the plurality of sacrificial blocks over the dielectric layer includes:forming a second sacrificial layer over the dielectric layer; andpatterning the second sacrificial layer to from the plurality of sacrificial blocks.3. The method of claim 1 , further comprising performing a planarization process to remove the first sacrificial layer and the plurality of sacrificial blocks.4. The method of claim 3 , wherein another portion of the dielectric layer is exposed after the performing of the planarization process.5. The method of claim 1 , further comprising:forming a phase-changing ...

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Номер записи: 67
12-02-2015 дата публикации

Resistive Memory Device and Method for Fabricating the Same

Номер: US20150041750A1
Автор: Cai Yimao, Mao Jun, Wu Huiwei
Принадлежит:

An embodiment of the present invention provides a resistive memory device and a method for fabricating the same. The resistive memory device includes a substrate and a plurality of memory cells spaced with each other over the substrate, each memory cell including a lower electrode, a resistive layer and an upper electrode, wherein the lower electrode is disposed over the substrate, the resistive layer is disposed over the lower electrode and the upper electrode is disposed over the resistive layer, and the resistive layer includes a resistive material portion and at least one doped resistive portion doped with an element for adjusting a resistance state. In the resistive memory device and the method for fabricating the same according to the present invention, since the resistive layer is not formed of single resistive material, during a set operation of the resistive memory device, a plurality of stable resistance states are produced according to various applied voltages, so that a storage density of the resistive memory device is increased without increasing a volume of the resistive memory device. 143212122. A resistive memory device , wherein the resistive memory device comprises a substrate () and a plurality of memory cells spaced with each other on the substrate , each memory cell comprising a lower electrode () , a resistive layer () and an upper electrode () , wherein the lower electrode is disposed over the substrate , the resistive layer is disposed over the lower electrode and the upper electrode is disposed over the resistive layer , and the resistive layer comprises a resistive material portion () and at least one doped resistive portion () doped with an element for adjusting a resistance state.2. The resistive memory device of claim 1 , wherein the resistive material portion is formed of one of silicon oxide SiOx claim 1 , germanium oxide GeOx claim 1 , titanium oxide TaOx and hafnium oxide HfOx.3. The resistive memory device of claim 1 , wherein the ...

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Номер записи: 68
04-02-2021 дата публикации

MEMORY DEVICE HAVING SEPARATE PROGRAMMING AND RESISTANCE READOUT CONTROL

Номер: US20210035639A1
Автор: Ando Takashi, Cohen Guy M., Gong Nanbo
Принадлежит:

A method for fabricating a semiconductor device includes forming first contacts to a heater for programming, and forming second contacts to a phase-change material layer for resistance readout. The phase-change material layer is formed in proximity to the heater, and the first contacts are electrically isolated from the second contacts to provide separate programming and resistance readout control. 1. A method for fabricating a semiconductor device , comprising:forming first contacts to a heater for programming, wherein the heater is disposed on a base structure including a substrate and a first insulator layer; andforming second contacts to a phase-change material layer for resistance readout, the phase-change material layer being formed in proximity to the heater, and the first contacts being electrically isolated from the second contacts to provide separate programming and resistance readout control.2. The method of claim 1 , further comprising:forming a semiconductor layer on the base structure; andforming the heater based on the semiconductor layer.3. The method of claim 2 , wherein forming the heater further includes converting the semiconductor layer into the heater using an anneal process.4. The method of claim 1 , further comprising forming a semiconductor layer as a mechanical support for the heater claim 1 , wherein the heater is formed around the semiconductor layer.5. The method of claim 1 , further comprising forming a second insulator layer to encapsulate the heater.6. The method of claim 5 , further comprising forming the phase-change material layer claim 5 , including depositing phase-change material and removing portions of the phase-change material from heater contact regions of the heater.7. The method of claim 6 , further comprising forming insulator material around the phase-change material layer claim 6 , wherein the first contacts are formed through the insulator material to the heater contact regions and the second contacts are formed ...

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Номер записи: 69
11-02-2016 дата публикации

ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20160043313A1
Автор: LEE Hyung-Dong
Принадлежит:

An electronic device includes a semiconductor memory. The semiconductor memory includes first lines extending in a first direction; second lines extending in a second direction crossing the first direction; insulating patterns interposed between the first and second lines at first intersections of the first and second lines; and variable resistance patterns interposed between the first and the second lines at second intersections of the first and second lines. A central intersection is defined by respective central lines of the first and second lines and corresponds to a coordinate (0, 0). The first intersections are located on first to (n+1)virtual lines, the (n+1)virtual line having a polygonal shape in which vertexes correspond to coordinates (−(k−n), 0), (k−n, 0), (0, k−n) and (0, −(k−n)) where k is a natural number and n is an integer in a range of 0 to (k−1). 1. An electronic device comprising a semiconductor memory unit , the semiconductor memory unit comprising:first lines extending in a first direction;second lines extending in a second direction crossing the first direction;insulating patterns interposed between the first lines and the second lines and located at first intersections of intersections of the first lines and the second lines; andvariable resistance patterns interposed between the first lines and the second lines and located at second intersections of the intersections of the first lines and the second lines,{'sup': th', 'th, 'wherein, when a central intersection defined by a central first line of the first lines and a central second line of the second lines corresponds to a coordinate (0, 0), the first intersections are located on first to (n+1)virtual lines, the (n+1)virtual line having a polygonal shape in which vertexes correspond to coordinates (−(k−n), 0), (k−n, 0), (0, k−n) and (0, −(k−n)) where k is a natural number and n is an integer in a range of 0 to (k−1).'}2. The electronic device according to claim 1 , wherein a cross-sectional ...

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Номер записи: 70
08-02-2018 дата публикации

ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20180040670A1
Автор: Glova Alvin Oliver, Sim Joon-Seop
Принадлежит:

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a first portion of a variable resistance element, the first portion having an island shape and including at least a free layer which has a variable magnetization direction; a second portion of the variable resistance element, the second portion having a line shape which extends in a direction over the first portion and including at least a pinned layer which has a pinned magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer. 1. An electronic device comprising a semiconductor memory ,wherein the semiconductor memory comprises:a variable resistance element including a first portion having a first shape and including a free layer which exhibits a variable magnetization direction, a second portion having a second shape different from the first shape, disposed over the first portion and including a pinned layer with a pinned magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer.2. The electronic device of claim 1 , wherein:the second portion is shaped to extend along an extended direction,a width of the first portion along a direction perpendicular to the extended direction decreases from a top to a bottom of the first portion along a vertical direction perpendicular to the extended direction, anda width of the second portion along the direction perpendicular to the extended direction increases from a top of the second portion to a bottom of the second portion along the vertical direction.3. The electronic device of claim 1 , wherein the tunnel barrier layer is included in the first portion and has a sidewall aligned with a sidewall of the free layer.4. The electronic device of claim 1 , wherein the tunnel barrier layer is included in the second portion and has a sidewall aligned with a sidewall of the pinned layer.5. The electronic device of claim 1 , wherein the ...

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Номер записи: 71
08-02-2018 дата публикации

SUBTRACTIVE PATTERNING OF BACK END OF LINE COMPATIBLE MIXED IONIC ELECTRONIC CONDUCTOR MATERIALS

Номер: US20180040819A1
Автор: Fraczak Gloria Wing Yun, Miyazoe Hiroyuki, Virwani Kumar
Принадлежит:

A method of forming a mixed ionic electron conductor (MIEC)-based memory cell access device using a subtractive etch process is provided. After blanket depositing a MIEC material layer on a bottom electrode and a dielectric layer laterally surrounding the bottom electrode and blanket depositing a metal layer on the MIEC material layer, the metal layer and the MIEC material layer are patterned simultaneously. 1. A method of forming a semiconductor structure comprising:forming a mixed ionic electric conductor (MIEC) material layer as a blanket layer on a bottom electrode and a dielectric material layer laterally surrounding the bottom electrode;forming a metal layer as a blanket layer on the MIEC material layer;forming a metallic hard mask portion consisting of a metal nitride directly on the metal layer; andpatterning the metal layer and the MIEC material layer to remove portions of the metal layer and portions of the MIEC material layer that are not covered by the metallic hard mask portion, wherein peripheral portions of the bottom electrode are exposed after the patterning.2. The method of claim 1 , wherein the patterning the metal layer and the MIEC material layer to remove the portions of the metal layer and the portions of the MIEC material layer that are not covered by the metallic hard mask portion are performed simultaneously utilizing an anisotropic etch.3. The method of claim 2 , wherein the anisotropic etch comprises etching the metal layer and the MIEC material layer with at least one etching gas comprising C claim 2 , H and O or a gas mixture of NHand CO claim 2 , a gas mixture of NHand CHor a gas mixture of NHand CH.4. The method of claim 1 , wherein the MIEC material layer comprises a material represented by a formula of MXY claim 1 , wherein:M is selected from the group consisting of Cu, Ag, Li and Zn,X is selected from the group consisting of Ge, Si, Sn, C, Cr, Mo and W, andY is selected from the group consisting of S, Se, Te or O, andwherein a is ...

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Номер записи: 72
12-02-2015 дата публикации

RESISTIVE MEMORY CELL

Номер: US20150044850A1
Автор: Ramaswamy D.V. Nirmal, Rocklein Matthew N.
Принадлежит:

Semiconductor memory devices, resistive memory devices, memory cell structures, and methods of forming a resistive memory cell are provided. One example method of a resistive memory cell can include a number of dielectric regions formed between two electrodes, and a barrier dielectric region formed between each of the dielectric regions. The barrier dielectric region serves to reduce an oxygen diffusion rate associated with the dielectric regions. 1. A method of forming a resistive memory cell , comprising:forming a first dielectric region between two electrodes;forming a barrier dielectric region on the first dielectric region; andforming a second dielectric region on the barrier dielectric region,wherein the barrier dielectric region includes a material having a slower oxygen diffusion rate and/or is a grain-boundary disruptor relative to the first and second dielectric regions.2. The method of claim 1 , further comprising forming one or more additional instances of barrier dielectric regions and dielectric regions claim 1 , wherein dielectric regions and additional instances of barrier dielectric regions alternate claim 1 , and each additional instances of barrier dielectric region is located between dielectric regions.3. The method of claim 1 , wherein forming each of the first and second dielectric regions and the barrier dielectric region includes forming a sub-nanometer thickness thereof.4. The method of claim 1 , wherein forming the barrier dielectric region includes forming to a thickness of less than about 20 Angstroms.5. The method of claim 1 , wherein forming the first and second dielectric regions includes forming the first and second dielectric regions to a thickness of between from about 10 to about 100 Angstroms.6. The method of claim 1 , wherein the thickness of the first and second dielectric regions and the barrier dielectric region is between from about 50 to about 1000 Angstroms.7. The method of claim 1 , wherein forming the first and second ...

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Номер записи: 73
24-02-2022 дата публикации

DIMENSION CONTROL FOR RAISED LINES

Номер: US20220059614A1
Автор: Nayaz Noemaun Ahmed
Принадлежит:

Methods, systems, and devices for dimension control for raised lines are described. For example, the techniques described herein may be used to fabricate raised lines (e.g., orthogonal raised lines). The lines may be fabricated such that an overall area of each line is consistent. In some examples, the techniques may be applied to form memory cells across multiple memory tiles, multiple memory arrays, and/or multiple wafers such that each memory cell comprises a consistent overall area. To form the lines and/or memory cells, a material associated with a desired properties may be deposited after performing a first cut. Due to the properties associated with the material, a width of the second cut may be affected, thus resulting in more uniform lines and/memory cells. 1. (canceled)2. An apparatus , comprising:a first pillar comprising a first memory cell coupled with a first conductive line and a second conductive line that each comprise a first conductive material;a second pillar comprising a second memory cell coupled with the second conductive line and a third conductive line that comprises the first conductive material; anda second conductive material below the second conductive line, at least a portion of the second conductive material extending below an upper surface of the first pillar and an upper surface of the second pillar at a location between the first pillar and the second pillar.3. The apparatus of claim 2 , further comprising:a dielectric material between the first pillar and the second pillar, wherein the portion of the second conductive material extends below at least a portion of the dielectric material.4. The apparatus of claim 2 , wherein the portion of the second conductive material has a first dimension equal to a distance between the first pillar and the second pillar and a second dimension equal to a width of the first memory cell claim 2 , the second memory cell claim 2 , or both.5. The apparatus of claim 4 , wherein the portion of the second ...

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Номер записи: 74
24-02-2022 дата публикации

SYSTEM ARCHITECTURE, STRUCTURE AND METHOD FOR HYBRID RANDOM ACCESS MEMORY IN A SYSTEM-ON-CHIP

Номер: US20220059618A1
Автор: Chen Hung-Yueh, Fan Ju-Chun, Hsu Ching-Hua, HSU Po-Kai, Lin Yi-Yu, Wang Hui-Lin
Принадлежит:

A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region. 1. A system architecture for hybrid random access memory in a system-on-chip , comprising:a computing unit;a hybrid register coupled to said computing unit;multiple magnetoresistive random access memory (MRAM) blocks, wherein each of said MRAM blocks comprises multiple MRAM cells coupled to a MRAM controller, and said MRAM controller is coupled to said hybrid register; andmultiple resistive random-access memory (ReRAM) blocks, wherein each of said ReRAM blocks comprises multiple ReRAM cells coupled to a ReRAM controller, and said ReRAM controller is coupled to said hybrid register;wherein said ReRAM cells and said MRAM cells are on the same semiconductor substrate.2. The system architecture for hybrid random access memory in a system-on-chip according to claim 1 , wherein said MRAM blocks are coupled to said ReRAM blocks.3. The system architecture for hybrid random access memory in a system-on-chip according to claim 1 , wherein each of said MRAM blocks further comprises:a hot spare coupled to said MRAM cells;a data backup unit coupled to said MRAM controller; anda redundant array of independent drivers (RAID) fail unit coupled to said MRAM controller.4. The system architecture for hybrid random access memory in a system-on-chip according to claim 1 , wherein each of said ReRAM blocks further comprises:a hot spare coupled to said ReRAM cells; anda RAID fail unit coupled to said ReRAM controller.5. The system architecture for hybrid random access memory in a system-on-chip according to claim 1 , wherein said hybrid register comprises a high-speed data register and a low-speed ...

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Номер записи: 75
24-02-2022 дата публикации

RESISTIVE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20220059762A1
Автор: YANG PO-YU
Принадлежит:

A resistive memory device includes a first stacked structure and a second stacked structure. The first stacked structure includes a first bottom electrode, a first top electrode disposed on the first bottom electrode, and a first variable resistance layer disposed between the first bottom electrode and the first top electrode in a vertical direction. The second stacked structure includes a second bottom electrode, a second top electrode disposed on the second bottom electrode, and a second variable resistance layer disposed between the second bottom electrode and the second top electrode in the vertical direction. A thickness of the first variable resistance layer is less than a thickness of the second variable resistance layer for increasing the number of switchable resistance states of the resistive memory device. 1. A resistive memory device , comprising: a first bottom electrode;', 'a first top electrode disposed on the first bottom electrode; and', 'a first variable resistance layer disposed between the first bottom electrode and the first top electrode in a vertical direction; and, 'a first stacked structure, comprising a second bottom electrode;', 'a second top electrode disposed on the second bottom electrode; and', 'a second variable resistance layer disposed between the second bottom electrode and the second top electrode in the vertical direction, wherein a thickness of the first variable resistance layer is less than a thickness of the second variable resistance layer., 'a second stacked structure, comprising2. The resistive memory device according to claim 1 , wherein a material composition of the first variable resistance layer is identical to a material composition of the second variable resistance layer.3. The resistive memory device according to claim 1 , wherein the first bottom electrode is electrically connected with the second bottom electrode claim 1 , and the first top electrode is electrically connected with the second top electrode.4. The ...

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Номер записи: 76
24-02-2022 дата публикации

MEMORY CELLS WITH ASYMMETRICAL ELECTRODE INTERFACES

Номер: US20220059763A1
Автор: Conti Anna Maria, Pellizzer Fabio, Pirovano Agostino, Yastrebenetsky Kolya
Принадлежит:

Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode. 1. (canceled)2. A memory device , comprising:a self-selecting memory component;a top electrode comprising a first interface with the self-selecting memory component having a first contact area; anda bottom electrode comprising a second interface with the self-selecting memory component having a second contact area that is less than the first contact area of the first interface.3. The memory device of claim 2 , wherein the bottom electrode tapers from a top surface to a bottom surface.4. The memory device of claim 2 , wherein the bottom electrode tapers from a bottom surface to a top surface.5. The memory device of claim 2 , wherein a length of a top surface of the bottom electrode that contacts the self-selecting memory component is less than a length of a bottom surface of the self-selecting memory component that contacts the bottom electrode.6. The memory device of claim 2 , wherein a length of a top surface of the bottom electrode is less than a length of a bottom surface of the top electrode in a first direction.7. The memory device of claim 2 , wherein an area of a top surface of the bottom electrode is different than an area of a bottom surface of the bottom electrode.8. The memory device of claim 2 , wherein a size of the bottom electrode is smaller than a size of the self-selecting memory component.9. The memory device of claim 2 , wherein a size of the bottom ...

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Номер записи: 77
24-02-2022 дата публикации

METHODS FOR RESISTIVE RAM (ReRAM) PERFORMANCE STABILIZATION VIA DRY ETCH CLEAN TREATMENT

Номер: US20220059765A1
Автор: Beckmann Karsten, Cady Nathaniel, Rodgers Martin, Sridhar Shyam, Voronin Sergey, WANG Qi
Принадлежит:

The performance of a ReRAM structure may be stabilized by utilizing a dry chemical gas removal (or cleaning) process to remove sidewall residue and/or etch by-products after etching the ReRAM stack layers. The dry chemical gas removal process decreases undesirable changes in the ReRAM forming voltage that may result from such sidewall residue and/or etch by-products. Specifically, the dry chemical gas removal process may reduce the ReRAM forming voltage that may otherwise result in a ReRAM structure that has the sidewall residue and/or etch by-products. In one embodiment, the dry chemical gas removal process may comprise utilizing a combination of HF and NHgases. The dry chemical gas removal process utilizing HF and NHgases may be particularly suited for removing halogen containing sidewall residue and/or etch by-products. 1. A method of processing a resistive random access memory (ReRAM) device , comprising:patterning a multi-layer ReRAM stack on a substrate, wherein a sidewall material is formed on sidewalls of the multi-layer ReRAM stack; andimproving a forming voltage of the ReRAM device by removing the sidewall material from the sidewalls of the multi-layer ReRAM stack through the use of a dry chemical gas removal process.2. The method of claim 1 , wherein the improving the forming voltage of the ReRAM device decreases the forming voltage of the ReRAM device by 10% or more as compared to not removing the sidewall material from the sidewalls of the multi-layer ReRAM stack.3. The method of claim 2 , wherein the forming voltage of the ReRAM device decreases by at least 15%.4. The method of claim 2 , wherein the sidewall material contains a halogen.5. The method of claim 4 , wherein the dry chemical gas removal process comprises using HF gas and/or NHgas.6. The method of claim 5 , wherein the dry chemical gas removal process comprises using HF gas and NHgas.7. The method of claim 1 , wherein the patterning the multi-layer ReRAM stack on the substrate comprises ...

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Номер записи: 78
07-02-2019 дата публикации

RESISTIVE RANDOM-ACCESS MEMORY (RRAM) CELL WITH RECESSED BOTTOM ELECTRODE SIDEWALLS

Номер: US20190044065A1
Автор: Liu Shih-Chang, Tseng Yuan-Tai
Принадлежит:

Various embodiments of the present application are directed towards an integrated circuit comprising a resistive random-access memory (RRAM) cell with recessed bottom electrode sidewalls to mitigate the effect of sidewall plasma damage. In some embodiments, the RRAM cell includes a lower electrode, a data storage element, and an upper electrode. The lower electrode includes a pair of recessed bottom electrode sidewalls respectively on opposite sides of the lower electrode. The data storage element overlies the lower electrode and includes a pair of storage sidewalls. The storage sidewalls are respectively on the opposite sides of the lower electrode, and the recessed bottom electrode sidewalls are laterally spaced from and laterally between the storage sidewalls. The upper electrode overlies the data storage element. 1. An integrated circuit comprising a memory cell , wherein the memory cell comprises:a lower electrode comprising a pair of electrode sidewalls, wherein the electrode sidewalls are respectively on opposite sides of the lower electrode;a data storage element overlying the lower electrode and comprising a pair of storage sidewalls, wherein the storage sidewalls are respectively on the opposite sides of the lower electrode, and wherein the electrode sidewalls are laterally spaced from and laterally between the storage sidewalls; andan upper electrode overlying the data storage element.2. The integrated circuit according to claim 1 , wherein the lower electrode has a first width claim 1 , and wherein the data storage element has a second width greater than the first width.3. The integrated circuit according to claim 1 , wherein the electrode sidewalls comprise a first electrode sidewall and a second electrode sidewall claim 1 , wherein the data storage element extends laterally and continuously from the first electrode sidewall to the second electrode sidewall in a first direction claim 1 , and wherein the data storage element further extends laterally and ...

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Номер записи: 79
18-02-2021 дата публикации

STRUCTURE AND METHOD TO EXPOSE MEMORY CELLS WITH DIFFERENT SIZES

Номер: US20210050220A1
Автор: CHANG Yao-Wen, Chen Sheng-Chau, Hsiao Cheng-Tai, Kuang Hsun-Chung, TSAI Cheng-Yuan
Принадлежит:

A method of forming a memory device is provided. In some embodiments, a memory cell is formed over a substrate, and a sidewall spacer layer is formed along the memory cell. A lower etch stop layer is formed on the sidewall spacer layer, and an upper dielectric layer is formed on the lower etch stop layer. A first etching process is performed to etch back the upper dielectric layer using the lower etch stop layer as an etch endpoint. 1. A method of forming a memory device , comprising:forming a memory cell over a substrate;forming a sidewall spacer layer along the memory cell;forming a lower etch stop layer on the sidewall spacer layer;forming an upper dielectric layer on the lower etch stop layer; andperforming a first etching process to etch back the upper dielectric layer using the lower etch stop layer as an etch endpoint.2. The method of claim 1 , prior to performing the first etching process claim 1 , further comprising:forming an upper etch stop layer over the upper dielectric layer; andperforming a first chemical-mechanical polishing (CMP) process to expose the upper dielectric layer directly above the memory cell.3. The method of claim 1 , after performing the first etching process claim 1 , further comprising:performing a blanket etch to remove the upper etch stop layer and to further lower the upper dielectric layer and expose the memory cell.4. The method of claim 1 , further comprising:forming a top interlayer dielectric layer over the upper dielectric layer; andforming a top metallization line and a top electrode via through the top interlayer dielectric layer to reach on the memory cell.5. The method of claim 1 , forming the memory cell comprises:forming a bottom electrode over the substrate;forming a switching dielectric over the bottom electrode; andforming a top electrode over the switching dielectric.6. The method of claim 1 , wherein the memory cell is a magnetoresistive random access memory (MRAM) cell.7. The method of claim 1 , wherein the ...

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Номер записи: 80
18-02-2021 дата публикации

Crosspoint Phase Change Memory with Crystallized Silicon Diode Access Device

Номер: US20210050384A1
Автор: Asit Ray, Bahman Hekmatshoartabari, Fabio Carta, Matthew J. BrightSky, Wanki Kim
Принадлежит: International Business Machines Corp

A method of fabricating an access device in a crosspoint memory array structure during BEOL processing includes: forming at least a first doped semiconductor layer on an upper surface of a first conductive layer, the first doped semiconductor layer being in electrical connection with the first conductive layer; exposing at least a portion of the first doped semiconductor layer to a directed energy source to cause localized annealing in the first doped semiconductor layer to activate a dopant of a first conductivity type in the first doped semiconductor layer, thereby converting at least a portion of the first doped semiconductor layer into a polycrystalline layer; forming a second conductive layer over a least a portion of the first doped semiconductor layer; and etching the first doped semiconductor layer and the first and second conductive layers to form an access device that is self-aligned with the first and second conductive layers.

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Номер записи: 81
06-02-2020 дата публикации

FILM SCHEME TO IMPROVE PEELING IN CHALCOGENIDE BASED PCRAM

Номер: US20200044148A1
Автор: Jiang Fa-Shen, LIANG Chin-Wei, Lin Hsing-Lien, Trinh Hai-Dang
Принадлежит:

A phase change memory (PCM) device including a PCM structure with a getter metal layer disposed between a phase change element (PCE) and a dielectric layer is provided. The PCM structure includes a dielectric layer, a bottom electrode, a via, a PCE, and a getter metal layer. The dielectric layer is disposed over a substrate. The bottom electrode overlies the dielectric layer. The via extends through the dielectric layer, from a bottom surface of the dielectric layer to a top surface of the dielectric layer. The phase change element overlies the bottom electrode. The getter metal layer is disposed between the dielectric layer and the PCE. 1. A phase change memory (PCM) structure comprising:a dielectric layer over a substrate;a via extending through the dielectric layer;a bottom electrode overlying the dielectric layer and the via, and further electrically coupled to the via;a phase change element overlying the bottom electrode;a top electrode overlying the phase change element; anda getter metal layer between the dielectric layer and the phase change element, wherein sidewalls of the top electrode and sidewalls of the getter metal layer are aligned, wherein the getter metal layer is between a top surface of the dielectric layer and a bottom surface of the bottom electrode.2. The PCM structure according to claim 1 , wherein the getter metal layer is comprised of a material that absorbs hydrogen (H).3. (canceled)4. (canceled)5. The PCM structure according to claim 1 , wherein the getter metal layer comprises a material different than a material of the bottom electrode.6. The PCM structure according to claim 1 , wherein the top and bottom electrodes are comprised of a first material and the getter metal layer is comprised of a second material claim 1 , wherein the first material is different than the second material.7. The PCM structure according to claim 1 , wherein sidewalls respectively of the top electrode claim 1 , the bottom electrode claim 1 , the phase change ...

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Номер записи: 82
06-02-2020 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20200044149A1
Автор: YAMAKAWA Koji
Принадлежит: Toshiba Memory Corporation

A semiconductor memory device includes a first electrode and a second electrode opposed to each other in a first direction, a phase-change film provided between the first electrode and the second electrode, a first film formed of an insulator provided on a side surface of the phase-change film in a second direction intersecting the first direction, and a second film formed of a conductor containing carbon and provided along a side surface of the phase-change film in the second direction with the first film interposed between the second film and the side surface. 1. A semiconductor memory device comprising:a first electrode and a second electrode opposed to each other in a first direction;a phase-change film provided between the first electrode and the second electrode;a first film formed of an insulator provided on a side surface of the phase-change film in a second direction intersecting the first direction; anda second film formed of a conductor containing carbon and provided along the side surface of the phase-change film in the second direction with the first film interposed between the second film and the side surface.2. The semiconductor memory device according to claim 1 , wherein the first film has a thermal conductivity in an in-plane direction that is greater than a thermal conductivity in a film-thickness direction.3. The semiconductor memory device according to claim 1 , wherein the first film contains carbon.4. The semiconductor memory device according to claim 3 , wherein the first film contains diamond-like carbon.5. The semiconductor memory device according to claim 1 , wherein the second film contains as least one of graphite and pyrolytic carbon.6. A semiconductor memory device comprising:a first electrode and a second electrode opposed to each other in a first direction;a phase-change film provided between the first electrode and the second electrode;a first film provided on a side surface of the phase-change film in a second direction ...

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Номер записи: 83
18-02-2021 дата публикации

INTERCONNECT STRUCTURE, SEMICONDUCTOR DEVICE, METHOD OF OPERATING ACTIVE ELEMENT, METHOD OF MANUFACTURING INTERCONNECT STRUCTURE, METHOD OF USING INTERCONNECT STRUCTURE, METHOD OF CONTROLLING INTERCONNECT RESISTANCE OF INTERCONNECT STRUCTURE, METHOD OF EVALUATING INTERCONNECT STRUCTURE, METHOD OF EVALUATING DEVICE, METHOD OF DRIVING DEVICE, AND EVALUATION DEVICE

Номер: US20210050513A1
Автор: ASANO Tetsuya, NISHIKAWA Asami, NISHITANI YU, Shibata Satoshi, SUGIMOTO Yuta, Tsujita Takuji
Принадлежит:

An interconnect structure according to the present disclosure includes: an interconnect layer containing a metal element as a main component and extending in a direction; a metal layer opposite to the interconnect layer, and a solid electrolyte layer between the interconnect layer and the metal layer. The solid electrolyte layer encloses the interconnect layer at least in a cross-sectional view taken along a plane orthogonal to the direction. The interconnect layer and the metal layer are electrically insulated from each other by the solid electrolyte layer. 1. An interconnect structure , comprising:an interconnect layer containing a metal element as a main component and extending in a direction;a metal layer opposite to the interconnect layer; anda solid electrolyte layer between the interconnect layer and the metal layer, the solid electrolyte layer enclosing the interconnect layer at least in a cross-sectional view taken along a plane orthogonal to the direction, whereinthe interconnect layer and the metal layer are electrically insulated from each other by the solid electrolyte layer.2. The interconnect structure according to claim 1 , whereinin the cross-sectional view, the interconnect layer has a pair of side surfaces opposite to each other and a bottom surface, andboth the metal layer and the solid electrolyte layer are opposite to each of the pair of side surfaces and the bottom surface.3. The interconnect structure according to claim 1 , whereinin the cross-sectional view, the interconnect layer has a circular or oval shape.4. The interconnect structure according to claim 3 , whereinthe interconnect layer serves as a columnar contact plug.5. The interconnect structure according to claim 1 , whereinin the cross-sectional view, an entire periphery of the interconnect layer is covered by the solid electrolyte layer, andin the cross-sectional view, an entire periphery of the solid electrolyte layer is covered by the metal layer.6. The interconnect structure ...

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Номер записи: 84
18-02-2021 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20210050517A1
Автор: BANNO Naoki, Tada Munehiro
Принадлежит: NEC Corporation

A semiconductor device includes a first insulation layer, a second insulation layer disposed on the first insulation layer and having an opening on an upper surface of the second insulation layer, a first electrode embedded in the second insulation layer and having an end exposed at the opening, a variable-resistance layer disposed on the first electrode and the second insulation layer in at least one region inside and around the opening, and a second electrode disposed on the variable-resistance layer. The opening and the second electrode are formed in a shape stretched in at least one axial direction. 1. A semiconductor device comprising:a first insulation layer;a second insulation layer disposed on the first insulation layer and having an opening on an upper surface of the second insulation layer;a first electrode embedded in the second insulation layer and having an end that is exposed at the opening;a variable-resistance layer disposed on the first electrode and the second insulation layer in at least one region inside and around the opening; anda second electrode that is disposed on the variable-resistance layer, whereinthe opening and the second electrode are formed in a shape stretched in at least one axial direction.2. The semiconductor device according to claim 1 , whereinthe variable-resistance layer is an ion conductive layer capable of conducting ions of a metal constituting the first electrode.3. The semiconductor device according to claim 1 , wherein at least one of a formation region of the opening and an opening region of the second electrode is elliptical.4. The semiconductor device according to claim 1 , wherein at least one of a formation region of the opening and an opening region of the second electrode is rectangular.5. The semiconductor device according to claim 1 , comprising the first electrode at two locations claim 1 , whereinthe first electrodes at the two locations are disposed to face each other with an interval.6. The semiconductor ...

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Номер записи: 85
18-02-2021 дата публикации

Techniques for forming self-aligned memory structures

Номер: US20210050521A1
Автор: Agostino Pirovano, Andrea Redaelli, Fabio Pellizzer, Innocenzo Tortorelli, Lorenzo Fratin, Stephen W. Russell
Принадлежит: Micron Technology Inc

Methods, systems, and devices for techniques for forming self-aligned memory structures are described. Aspects include etching a layered assembly of materials including a first conductive material and a first sacrificial material to form a first set of channels along a first direction that creates a first set of sections. An insulative material may be deposited within each of the first set of channels and a second sacrificial material may be deposited onto the first set of sections and the insulating material. A second set of channels may be etched into the layered assembly of materials along a second direction that creates a second set of sections, where the second set of channels extend through the first and second sacrificial materials. Insulating material may be deposited in the second set of channels and the sacrificial materials removed leaving a cavity. A memory material may be deposited in the cavity.

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Номер записи: 86
19-02-2015 дата публикации

DIODE FOR VARIABLE-RESISTANCE MATERIAL MEMORIES, PROCESSES OF FORMING SAME, AND METHODS OF USING SAME

Номер: US20150050795A1
Автор: Liu Jun, Violette Michael P.
Принадлежит:

A variable-resistance material memory (VRMM) device includes a container conductor disposed over an epitaxial semiconductive prominence that is coupled to a VRMM. A VRMM device may also include a conductive plug in a recess that is coupled to a VRMM. A VRMM array may also include a conductive plug in a surrounding recess that is coupled to a VRMM. Apparatuses include the VRMM with one of the diode constructions. 1. A process comprising:forming an island in a semiconductive film to include an island first height;reducing the island first height to an island second height, wherein the island second height is defined by first and second walls in the semiconductive film first height that are arrayed in a second direction that is orthogonal to the first direction;forming a diode plug above and against the island second height, wherein the diode plug also contacts the first and second walls;forming an electrode above and on the diode plug; andcoupling the electrode to a variable-resistance material memory (VRMM) cell.2. The process of claim 1 , wherein forming the diode plug includes filling a metal at the island second height and between the first and second walls.3. The process of claim 1 , wherein forming the island includes:forming a patterned nitride film above the semiconductive film; andetching to expose the semiconductive material substrate.4. The process of claim 1 , wherein the first and second walls are formed including:forming a patterned nitride film above the semiconductive film;etching to expose the semiconductive material substrate;filling adjacent the island with a shallow-trench isolation (STI);cross-patterning the patterned nitride film to expose a portion of the patterned nitride film; andetching to expose the first and second walls, the island second height, and wherein etching to expose the first and second walls also forms a recess with a floor thereof that includes the island second height, the first and second walls, and the STI.5. The process of ...

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Номер записи: 87
16-02-2017 дата публикации

MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20170047377A1
Автор: Chiang Kuang-Hao, Lai Erh-Kun
Принадлежит:

A memory device is provided. The memory device includes a substrate, a plurality of alternately stacked semiconductor layers and oxide layers disposed on the substrate, at least one through hole penetrating the stacked semiconductor layers and oxide layers, and an electrode layer disposed in the through hole. Each of the semiconductor layers includes a first area having a first conductive type and a second area having a second conductive type opposite to the first conductive type. 1. A memory device , comprising:a substrate;a plurality of alternately stacked semiconductor layers and oxide layers disposed on the substrate;a through hole penetrating the stacked semiconductor layers and oxide layers; andan electrode layer disposed in the through hole,wherein each of the semiconductor layers comprises a first area having a first conductive type and a second area having a second conductive type opposite to the first conductive type;an array layout of the memory device is a line type array layout;the line type array layout is physical 2 bits/per cell; andeven and odd lines of the array layout are decoded individually.2. The memory device according to claim 1 , further comprising:an isolation layer formed along a periphery of the through hole.3. The memory device according to claim 2 , wherein the second area is adjacent to the isolation layer claim 2 , and the first area is adjacent to the second area.4. The memory device according to claim 3 , wherein a concentration of the second area closer to the isolation layer is larger than a concentration of the second area farther away from the isolation layer.5. The memory device according to claim 2 , wherein the isolation layer comprises metal oxide or phase change material.6. The memory device according to claim 1 , further comprising:a conductive plug disposed in the substrate,wherein the conductive plug is electrically connected to the electrode layer.7. The memory device according to claim 1 , further comprising:a hard ...

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Номер записи: 88
15-02-2018 дата публикации

STORAGE DEVICE WITH COMPOSITE SPACER AND METHOD FOR MANUFACTURING THE SAME

Номер: US20180047895A1
Автор: Hsu Chern-Yow, Liu Shih-Chang, Sung Fu-Ting
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A storage device includes a first electrode, a stacked feature, a spacer and a barrier structure. The stacked feature is position over the first electrode, and includes a storage element and a second electrode over the storage element. The spacer is positioned on a sidewall of the stacked feature, the spacer having a notch positioned on a top surface of the spacer, in which the notch of the spacer has a surface which is continuous with a top surface of the stacked feature. The barrier structure is embedded in a lateral of the spacer. The barrier structure has a top extending upwards past a bottom of the notch. 1. A storage device , comprising:a first electrode;a stacked feature over the first electrode and comprising a storage element and a second electrode over the storage element;a spacer positioned on a sidewall of the stacked feature, the spacer having a notch positioned on a top surface of the spacer, wherein the notch of the spacer comprises a surface which is continuous with a top surface of the stacked feature; anda barrier structure embedded in a lateral of the spacer, wherein the barrier structure has a top extending upwards past a bottom of the notch.2. The storage device according to claim 1 , wherein the spacer is directly attached to the sidewall of the second electrode and a sidewall of the storage element.3. The storage device according to claim 1 , wherein the spacer comprises a bottom portion and a standing portion extending upwards from the bottom portion claim 1 , and the bottom portion has a width greater than a width of the standing portion.4. The storage device according to claim 3 , wherein the bottom portion is positioned on and in contact with a top surface of the first electrode.5. The storage device according to claim 3 , wherein the barrier structure stands on the bottom portion and in contact with the standing portion.6. The storage device according to claim 3 , wherein the width of the bottom portion of the spacer is approximately 5-30 ...

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Номер записи: 89
15-02-2018 дата публикации

MEMORY CELL WITH INDEPENDENTLY-SIZED ELECTRODE

Номер: US20180047896A1
Автор: GOTTI ANDREA, Ravasio Marcello, Sciarrillo Samuele
Принадлежит:

Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle electrode is formed between the memory element and the switch element. An outside electrode is formed adjacent the switch element or the memory element at a location other than between the memory element and the switch element. A lateral dimension of the middle electrode is different than a lateral dimension of the outside electrode. 120.-. (canceled)21. An apparatus , comprising:a first electrode extending a first distance in a first lateral dimension;a second electrode coupled to the first electrode, the second electrode extending a second distance in the first lateral dimension; anda third electrode coupled to the second electrode, the third electrode extending the first distance in the first lateral dimension.22. The apparatus of claim 21 , wherein the second electrode is formed from a material that is different than a material used to form the first electrode or a material used to form the third electrode.23. The apparatus of claim 21 , wherein the second distance in the first lateral dimension is less than the first distance in the first lateral dimension.24. The apparatus of claim 21 , wherein:the first electrode extends a first distance in a second lateral dimension,the second electrode extends a second distance in the second lateral dimension, andthe third electrode extends the first distance in the second lateral dimension.25. The apparatus of claim 24 , wherein the second distance in the second lateral dimension is less than the first distance in the second lateral dimension.26. The apparatus of claim 21 , wherein the second electrode is formed of a material having a higher etch rate than a material of which at least one of the first electrode and the second electrode is formed.27. The apparatus of claim 21 , wherein the second electrode is self-aligned with a conductive line coupled to the first ...

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Номер записи: 90
08-05-2014 дата публикации

Pillar structure for memory device and method

Номер: US20140127876A1
Автор: Scott Brad Herner
Принадлежит: Crossbar Inc

A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed to provide a metal-to-metal contact with the bottom wiring structure. The method forms a pillar structure by patterning and etching a material stack including the bottom metal barrier material, a contact material, a switching material, a conductive material, and a top barrier material. The pillar structure maintains a metal-to-metal contact with the bottom wiring structure regardless of the alignment of the pillar structure with the bottom wiring structure during etching. A top wiring structure is formed overlying the pillar structure at an angle to the bottom wiring structure.

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Номер записи: 91
26-02-2015 дата публикации

MEMRISTIVE DEVICE AND METHOD OF MANUFACTURE

Номер: US20150053908A1
Автор: Fowler Burt
Принадлежит: Privatran

A device with programmable resistance comprising memristive material between conductive electrodes on a substrate or in a film stack on a substrate is provided. During fabrication of a memristive device, a memristive layer may be hydrated after deposition of the memristive layer. The hydration of the memristive layer may be performed utilizing thermal annealing in a reducing ambient, implant or plasma treatment in a reducing ambient, or a deionized water rinse. Additionally, plasma-assisted etching of an electrode may be performed with hydration or in place of hydration to electroform devices in a batch, in situ process. The memristive device may be electroformed at low voltage and passivated to allow for device operation in air. Further, the memristive device is suitable for high throughput manufacturing. 1. A method for fabricating a memristive device comprising:forming a first electrode, wherein the first electrode is formed from a conductive or semiconductive material;depositing a memristive layer, wherein the memristive layer comprises at least one memristive material;{'sub': 2', '2', '2', '2', '3, 'hydrating said memristive layer utilizing a reducing ambient, wherein the reducing ambient is H, D, HO, DO, NH, H or D containing gas mixtures, or a combination thereof; and'}forming a second electrode, wherein said first and second electrodes are separated by said memristive layer.2. The method of claim 1 , wherein said hydrating comprises a thermal anneal of said memristive layer in said reducing ambient.3. The method of claim 1 , wherein said hydrating comprises a plasma treatment of said memristive layer in said reducing ambient.4. The method of claim 1 , wherein said hydrating comprises a deionized water rinse and drying in any inert ambient.5. The method of claim 1 , further comprising electroforming said memristive device claim 1 , wherein electroformation is performed during plasma-assisted etching of said second electrode.6. The method of claim 1 , further ...

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Номер записи: 92
03-03-2022 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20220069011A1
Автор: Ahn Dongho, KIM Chungman, KWON Segab, LEE Jabin, LEE Jinwoo, Lee Wonjun, PARK Kwangmin, WU Zhe, YU Seunggeun
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor device includes a semiconductor substrate, a peripheral device on the semiconductor substrate, a lower insulating structure on the semiconductor substrate and covering the peripheral device, a first conductive line on the lower insulating structure, a memory cell structure on the first conductive line, and a second conductive line on the memory cell structure. The memory cell structure may include an information storage material pattern and a selector material pattern on the lower insulating structure in a vertical direction. The selector material pattern may include a first selector material layer including a first material and a second selector material layer including a second material. The second selector material layer may have a threshold voltage drift higher than that of the first material. The second selector material layer may have a second width narrower than a first width of the first selector material layer.

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Номер записи: 93
03-03-2022 дата публикации

METHOD FOR FORMING A HARD MASK WITH A TAPERED PROFILE

Номер: US20220069204A1
Автор: Hsu Chern-Yow, KO Min-Yung, Liu Shih-Chang, Wu Chang-Ming
Принадлежит:

Various embodiments of the present disclosure are directed towards a method for forming a memory cell. In some embodiments, a memory film is deposited over a substrate and comprises a bottom electrode layer, a top electrode layer, and a data storage film between the top and bottom electrode layers. A hard mask film is deposited over the memory film and comprises a conductive hard mask layer. The top electrode layer and the hard mask film are patterned to respectively form a top electrode and a hard mask over the top electrode. A trimming process is performed to decrease a sidewall angle between a sidewall of the hard mask and a bottom surface of the hard mask. An etch is performed into the data storage film with the hard mask in place after the trimming process to form a data storage structure underlying the top electrode. 1. A method for forming a memory cell , the method comprising:depositing a memory film over a substrate, wherein the memory film comprises a bottom electrode layer, a top electrode layer, and a data storage film between the top and bottom electrode layers;depositing a hard mask film over the memory film;patterning the top electrode layer and the hard mask film to respectively form a top electrode and a hard mask over the top electrode;performing a trimming process to decrease a sidewall angle between a sidewall of the hard mask and a bottom surface of the hard mask; andperforming an etch into the data storage film with the hard mask in place after the trimming process to form a data storage structure underlying the top electrode.2. The method according to claim 1 , wherein the sidewall angle is greater than about 85 degrees before the trimming process and is less than about 82 degrees after the trimming process.3. The method according to claim 1 , wherein the trimming process comprises ion beam etching (IBE).4. The method according to claim 1 , wherein the trimming process comprises bombarding the sidewall with ions accelerated in a direction ...

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Номер записи: 94
03-03-2022 дата публикации

MEMORY ELECTRODES AND FORMATION THEREOF

Номер: US20220069207A1
Автор: Gleixner Robert J., McCrate Joseph M.
Принадлежит:

The present disclosure includes apparatuses and methods related to forming memory cells having memory element dimensions. For example, a memory cell may include a first electrode, a select-element material between the first electrode and a second electrode, and a lamina between the select-element material and the first electrode. The first electrode may comprise a first portion, proximate to the lamina, having a first lateral dimension; and a second portion, distal from the lamina, having a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension. 1. A memory cell , comprising:a first electrode;a select-element material between the first electrode and a second electrode; anda lamina between the select-element material and the first electrode; a first portion, proximate to the lamina, having a first lateral dimension; and', 'a second portion, distal from the lamina, having a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension., 'wherein the first electrode comprises2. The memory cell of claim 1 , wherein the first lateral dimension of the first portion of the first electrode is less than a lateral dimension of the select-element material.3. The memory cell of claim 1 , wherein the first lateral dimension of the first portion of the first electrode is less than a lateral dimension of the lamina between the first electrode and the select-element material.4. The memory cell of claim 1 , wherein the select-element material comprises a chalcogenide material with ovonic threshold switching characteristics to serve as both a select element and a storage element for the memory cell.5. The memory cell of claim 1 , wherein the lamina comprises a high dielectric constant (high-κ) material.6. The memory cell of claim 1 , comprising low dielectric constant (low-κ) material between the second portion of the first electrode and the lamina.7. The memory cell of claim 1 , wherein ...

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Номер записи: 95
03-03-2022 дата публикации

RESISTIVE RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME

Номер: US20220069210A1
Автор: HSU PO-YEN, KUO Tse-Mian, Wu Bo-Lun
Принадлежит:

A resistive random access memory is provided. The resistive random access memory includes a substrate, a first dielectric layer, a bottom electrode, a resistance switching layer, an oxygen exchange layer, a barrier layer and a top electrode. The first dielectric layer is disposed on the substrate. The bottom electrode is disposed on the first dielectric layer. The resistance switching layer is disposed on the bottom electrode. The oxygen exchange layer is disposed on the resistance switching layer. A contact area between the oxygen exchange layer and the resistance switching layer is smaller than a top surface area of the resistance switching layer. The barrier layer is disposed on the oxygen exchange layer. The top electrode is disposed on the barrier layer.

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Номер записи: 96
03-03-2022 дата публикации

RESISTIVE MEMORY ELEMENTS WITH MULTIPLE INPUT TERMINALS

Номер: US20220069213A1
Автор: Tan Shyue Seng, Toh Eng Huat, Wang Lanxiang
Принадлежит:

Structures for a resistive memory element and methods of forming a structure for a resistive memory element. The resistive memory element has a first electrode, a second electrode, a third electrode, and a switching layer. The first electrode is coupled to the switching layer, the second electrode is coupled to a side surface of the switching layer, and the third electrode is coupled to the switching layer.

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Номер записи: 97
03-03-2022 дата публикации

RESISTIVE RANDOM ACCESS MEMORY WITH PREFORMED FILAMENTS

Номер: US20220069218A1
Автор: LILL Thorsten, Pan Yang, YOON Hyungsuk
Принадлежит:

A method for fabricating a plurality of resistive random access memory (RRAM) cells includes providing a substrate including a memory medium arranged on an underlying layer; creating channel holes in the memory medium having a first critical dimension in a range from 1 nm to 20 nm; depositing switching material defining a filament of the RRAM cells in the channel holes; depositing a top electrode of the RRAM cells on the memory medium and the switching material; and separating adjacent ones of the RRAM cells by etching the top electrode and the memory medium between adjacent ones of the channel holes. 1. A method for fabricating a plurality of resistive random access memory (RRAM) cells , comprising:providing a substrate including a memory medium arranged on an underlying layer;creating channel holes in the memory medium having a first critical dimension in a range from 1 nm to 20 nm;depositing switching material defining a filament of the RRAM cells in the channel holes;depositing a top electrode of the RRAM cells on the memory medium and the switching material; andseparating adjacent ones of the RRAM cells by etching the top electrode and the memory medium between adjacent ones of the channel holes.2. The method of claim 1 , wherein creating the channel holes in the memory medium includes:depositing a first mask layer on the memory medium;patterning the channel holes having the first critical dimension in the mask layer;etching the memory medium through the channel holes to the underlying layer; andremoving the first mask layer.3. The method of claim 1 , wherein creating the channel holes in the memory medium includes:depositing a first mask layer on the memory medium;patterning the channel holes having a second critical dimension that is greater than the first critical dimension in the mask layer;etching the memory medium through the channel holes to the underlying layer;removing the first mask layer; andfilling the channel holes with a conformal layer to reduce ...

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Номер записи: 98
25-02-2016 дата публикации

Integrated phase change switch

Номер: US20160056373A1
Автор: Michael A. Stuber, Sinan Goktepeli
Принадлежит: Qualcomm Switch Corp

Various methods and devices that involve phase change material (PCM) switches are disclosed. An exemplary integrated circuit comprises an active layer with a plurality of field effect transistor (FET) channels for a plurality of FETs. The integrated circuit also comprises an interconnect layer comprising a plurality of conductive interconnects. The plurality of conductive interconnects couple the plurality of field effect transistors. The integrated circuit also comprises an insulator layer covering at least a portion of the interconnect layer. The integrated circuit also comprises a channel of a radio-frequency (RF) PCM switch. The channel of the RF PCM switch is formed on the insulator layer.

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Номер записи: 99
25-02-2021 дата публикации

MEMORY DEVICE AND METHOD OF FORMING THE SAME

Номер: US20210057645A1
Автор: LIM JU DY, Ng Mei Zhen, SEET CHIM SENG, Yamane Kazutaka
Принадлежит:

A memory device may be provided, including a first planar electrode, a second planar electrode, and a switching element arranged between the first planar electrode and the second planar electrode to where a first side of the switching element is arranged over the first planar electrode and where a second side of the switching element is arranged under the second planar electrode. The switching element is thicker at the first side than the second side, and the switching element is configured to provide a conductive filament formation region. 1. A memory device , comprising:a first planar electrode;a second planar electrode; anda switching element arranged between the first planar electrode and the second planar electrode to where a first side of the switching element is arranged over the first planar electrode and where a second side of the switching element is arranged under the second planar electrode;wherein the switching element is thicker at the first side than the second side; wherein the switching element is configured to provide a conductive filament formation region.2. The memory device of claim 1 , wherein the switching element has a triangular or trapezoidal cross-section.3. The memory device of claim 1 , further comprising:a layer at least partially lining the switching element.4. The memory device of claim 1 , further comprising:a dielectric layer arranged between the first planar electrode and the second planar electrode, wherein the dielectric layer is arranged around the switching element.5. The memory device of claim 1 , further comprising:a component arranged between the switching element and the second planar electrode; wherein the component is in electrical communication with the second planar electrode.6. The memory device of claim 5 , wherein the component comprises a nanopillar.7. The memory device of claim 5 , wherein:the component comprises a film embedded with nanoparticles.8. The memory device of claim 1 , wherein the switching element ...

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Номер записи: 100