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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Форма поиска

Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 9353. Отображено 100.
11-07-2017 дата публикации

Вычислительное устройство режектирования помех

Номер: RU0000172504U1

Устройство относится к вычислительной технике и предназначено для выделения сигналов движущихся целей на фоне пассивных помех при групповой перестройке несущей частоты зондирующих импульсов. Достигаемый технический результат - повышение эффективности выделения сигналов движущихся целей. Указанный результат достигается тем, что вычислительное устройство режектирования помех содержит первый и второй блоки задержки, блок весовых коэффициентов, первый и второй комплексные перемножители, весовой блок, комплексный сумматор, блок комплексного сопряжения, блок переключения, блок точности, блок коммутации, двухканальный коммутатор и синхрогенератор, определенным образом соединенные между собой и осуществляющие когерентную обработку исходных отсчетов. 11 ил. Ц 1 172504 ко РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ и, 278 м ил $ хх 5%“ $ < м. п | РЦ ‘’ х я (50) МПК НОЗН 17/06 (2006.01) (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (21)(22) Заявка: 2017111140, 03.04.2017 (24) Дата начала отсчета срока действия патента: 03.04.2017 Дата регистрации: 11.07.2017 Приоритет(ы): (22) Дата подачи заявки: 03.04.2017 (45) Опубликовано: 11.07.2017 Бюл. № 20 Адрес для переписки: 390005, г. Рязань, ул. Гагарина, 59/1, ФГБОУ ВО "РГРТУ", патентная служба (72) Автор(ы): Попов Дмитрий Иванович (КО) (73) Патентообладатель(и): Федеральное государственное бюджетное образовательное учреждение высшего образования "Рязанский государственный радиотехнический университет" (КО) (56) Список документов, цитированных в отчете о поиске: 30 743208, 25.06.1980. КП 2599621 СТ, 10.10.2016. ВП 157117 91, 20.11.2015. 05 5886914 А, 23.04.1999. (54) ВЫЧИСЛИТЕЛЬНОЕ УСТРОЙСТВО РЕЖЕКТИРОВАНИЯ ПОМЕХ (57) Реферат: Устройство относится к вычислительной технике и предназначено для выделения сигналов движущихся целей на фоне пассивных помех при групповой перестройке несущей частоты зондирующих импульсов. Достигаемый технический результат - повышение эффективности выделения сигналов движущихся ...

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30-06-2020 дата публикации

Адаптивный цифровой фильтр для подавления нефлуктуационных помех

Номер: RU0000198305U1

Полезная модель относится к области радиотехники и может быть использована в устройствах цифровой обработки сигналов, проходящих по каналам связи, в которых существует возможность искажения сигналов, связанных с наличием в каналах внешних нефлуктуационных помех. Заявленный адаптивный цифровой фильтр для подавления нефлуктуационных помех, содержащий первый преобразователь комплексной огибающей сигнала в комплексно сопряженную огибающую; первый регистр задержки, состоящий из последовательно соединенных первого, второго, третьего элементов задержки; второй регистр задержки, состоящий из последовательно соединенных четвертого, пятого, шестого элементов задержки; первый, второй и третий перемножители выходных сигналов первого регистра задержки с весовыми коэффициентами; первый сумматор; первый, второй и третий интеграторы; пятый, шестой и седьмой перемножители выходных сигналов второго регистра задержки с сигналом первой схемы адаптивной подстройки весовых коэффициентов, состоящей из последовательно соединенных блока вычисления производной, первого блока вычисления модуля, второго сумматора с напряжением -G и четвертого перемножителя с напряжением -d1, предложенный фильтр характеризуется тем, что включает второй преобразователь комплексной огибающей сигнала в комплексно сопряженную огибающую, вход которого соединен с выходом первого сумматора и с входом третьего регистра задержки, состоящего из последовательно соединенных седьмого, восьмого, девятого элементов задержки, выходы которых соединены с первыми входами восьмого, девятого и десятого перемножителей выходных сигналов третьего регистра задержки с весовыми коэффициентами, при этом выходы указанных перемножителей соединены с входами третьего сумматора, выход которого является выходом устройства и одновременно - входом второй схемы адаптивной подстройки весовых коэффициентов, содержащей последовательно соединенные второй блок вычисления модуля, блок возведения в квадрат, четвертый сумматор, на второй вход которого ...

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12-01-2012 дата публикации

Nicam decoder with output resampler

Номер: US20120008724A1
Принадлежит: THAT Corp

A NICAM audio signal re-sampler may include a non-linear interpolator configured to interpolate in a non-linear manner between sequential digital samples that are based on a stream of demodulated NICAM audio samples. A phase differential calculator may be included that compares phase information at different resolutions.

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26-01-2012 дата публикации

Dynamic impedance control for input/output buffers

Номер: US20120019282A1
Автор: Bruce Millar
Принадлежит: Mosaid Technologies Inc

A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.

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16-02-2012 дата публикации

Multi-Branch Rate Change Filter

Номер: US20120041995A1
Автор: Pierre-Andre Laporte
Принадлежит: Individual

The present invention relates to a rate change filter having multiple branches. The multi-branch rate change filter of the present invention achieves higher effective output rates by processing the input sample stream in two or more parallel filter branches with offset states.

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07-06-2012 дата публикации

Down sampling method and down sampling device

Номер: US20120142302A1
Принадлежит: Huawei Device Co Ltd

In the field of communications technologies, a down sampling method and a down sampling device are provided, to enable the energy of a down sampling point obtained in down sampling to be as large as possible. The down sampling method includes: extracting energy statistical values of sampling point sets in a current period; selecting a sampling position corresponding to a sampling point set with the largest energy statistical value as a down sampling position; and performing down sampling according to the down sampling position.

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19-07-2012 дата публикации

Multi-Rate Implementation Without High-Pass Filter

Номер: US20120185524A1
Автор: Jeffrey Clark
Принадлежит: Individual

A filtering method approximates a target Finite Impulse Response (FIR) (or transversal) filter and reduces computational requirements by eliminating high pass filtering required by known multi-rate filters. An input signal is copied into two identical signals and processed in parallel by a full-rate path, and by a reduced-rate path. Parallel filters are computed and applied in each path, the reduced-rate signal is up-sampled, and the two signals summed. The high pass filter required by known multi-rate filters is eliminated and the low pass filter in the prior art is implicit in a down sampling. Linear phase FIR filters are used for down and up sampling, resulting in constant group delay. Added benefits include the option of zero added latency through the filtering and the constant group delay added to the target FIR. The user may choose criteria such as minimum resolution in each band.

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16-08-2012 дата публикации

Reducing steady state error in fixed point implementations of recursive filters

Номер: US20120207200A1
Автор: Vignesh Sethuraman
Принадлежит: Qualcomm Inc

One feature includes a method for implementing a fixed point recursive filter that reduces or eliminates steady state error. The method comprises obtaining a first filter state value, processing the first filter state value to remove a scaling factor to obtain a second filter state value, ascertaining that the recursive filter has reached a steady state, determining a nonlinear drift parameter based on a difference between the first filter state value and the second filter state value multiplied by the scaling factor, and adjusting the second filter state value with the nonlinear drift parameter to reduce steady state error of the recursive filter. Ascertaining that the recursive filter has reached the steady state may include determining that a filter output value at time n is equal to a filter output value at time n−1.

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20-09-2012 дата публикации

Carrier Selection for Multiple Antennas

Номер: US20120238229A1
Автор: Rohit V. Gaikwad
Принадлежит: Broadcom Corp

A method and apparatus is disclosed to process a received single stream communication signal and/or a multiple stream communication. A communications receiver is configured to receive the received communication signal. A communications receiver determines whether the received communication signal includes a single stream communication signal or a multiple stream communication signal. The communications receiver determines whether a received communication signal complies with a known single stream communications standard. The communications receiver determines whether the received communication signal complies with a known multiple stream communications standard. The communications receiver decodes the received communication signal according to the known single stream communications standard upon determining the received communication includes the signal single stream communication signal. The communications receiver decodes the received communication signal according to the known multiple stream communications standard upon determining the received communication includes the multiple stream communication signal.

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25-10-2012 дата публикации

Demultiplexing device, multiplexing device, and relay device

Номер: US20120269238A1
Автор: Akinori Fujimura
Принадлежит: Mitsubishi Electric Corp

A demultiplexing device that can reduce power consumption. The demultiplexing device includes frequency-conversion and reception low-pass-filter units that perform a frequency converting process and a low-pass filtering process causing a signal to pass through a desired band, perform downsampling to reduce a sampling rate to half of a data rate of an input signal, and output the signal, reception channel-filter units that waveform-shape a signal with a desired frequency characteristic and output the waveform-shaped signal, a filter-bank control unit that generates a clock control signal for supplying a clock to frequency-conversion and reception low-pass-filter units and reception channel-filter units corresponding to signal passage bands, based on channel information, and a reception-clock supply unit that supplies a clock to frequency-conversion and reception low-pass-filter units and reception channel-filter units corresponding to signal passage bands, based on the clock control signal.

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04-04-2013 дата публикации

SIGNAL PROCESSOR, FILTER, CONTROL CIRCUIT FOR POWER CONVERTER CIRCUIT, INTERCONNECTION INVERTER SYSTEM AND PWM CONVERTER SYSTEM

Номер: US20130082636A1
Принадлежит: DAIHEN CORPORATION

A signal processor is configured to perform a process equivalent to performing a series of fixed-to-rotating coordinate conversion, a predetermined process and then rotating-to-fixed coordinate conversion, while maintaining linearity and time-invariance. The signal processor performs a process given by the following matrix G: 5. A control circuit for controlling a plurality of switching units inside a power converter circuit by a PWM signal , comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'a signal processor according to ; and'}a PWM signal generator for generation of a PWM signal based on an output signal from the signal processor obtained by an input thereto of a signal based on an output from or as input to the power converter circuit.6. The control circuit according to claim 5 , further comprising a two-phase conversion unit for conversion of a signal based on an output from or an input to the power converter circuit into a first signal and a second signal claim 5 , whereinthe PWM signal generator generates a PWM signal based on both an output signal obtained from an input of the first signal to the signal processor and an output signal obtained from an input of the second signal to the signal processor.7. A control circuit for controlling a plurality of switching units inside a power converter circuit by a PWM signal claim 5 , comprising:a two-phase conversion unit for conversion of a signal based on an output from or an input to the power converter circuit into a first signal and a second signal;{'claim-ref': {'@idref': 'CLM-00002', 'claim 2'}, 'the signal processor according to ; and'}a PWM signal generator for generation of a PWM signal based on an output signal from the signal processor obtained by an input thereto of the first signal and the second signal.8. The control circuit according to claim 6 , whereinthe power converter circuit relates to a three-phase alternate current, andthe two-phase conversion unit converts a signal based on a ...

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23-05-2013 дата публикации

Feedback-Based Particle Filtering

Номер: US20130132454A1

Methods for estimating a conditional probability distribution for signal states of a non-linear random dynamic process. The filter is based on multiple particles, each defined by a state space model similar to the dynamic process. Each particle is updated on the basis of a control input derived by proportional gain feedback on an innovation process. The innovation process is the difference between an increment in an observed quantity measured by one or more sensors and an average of a function of the particles. The particle filter of the invention may also be applied to filtering problems with data association uncertainty where multiple measurements are obtained, of which at most one originates from a specified target. 1. A method for estimating a conditional probability distribution for signal states of a non-linear random dynamic process , the method comprising:a. receiving sensor measurement data associated with the non-linear random dynamic process, the sensor measurement data providing a history of observations;b. initializing a state for each of a plurality of particles, the plurality of particles together comprising an entire population of particles, the states of the plurality of particles collectively probabilistically representing an estimate of a state of the non-linear random dynamic process at an initial time; andc. updating the state of each of the plurality of particles to obtain a posterior distribution based on a control input derived by proportional gain feedback on an innovation process, wherein the innovation process is the difference between an observed quantity based on sensor data at time t and a quantity in which a function of a particle state is a term.2. A method in accordance with claim 1 , further comprising acquiring the sensor measurement data from at least one sensor.3. A method in accordance with claim 2 , wherein the at least one sensor is a remote sensor.4. A method in accordance with claim 2 , wherein the at least one sensor is a ...

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20-06-2013 дата публикации

Digital/analogue conversion apparatus

Номер: US20130156231A1
Принадлежит: Trigence Semiconductor Inc

A digital/analog conversion apparatus to convert a digital signal into an analog signal. The digital/analog conversion apparatus can generate a high-quality analog signal, even when elements configuring the digital/analog conversion apparatus have variance, with high resolution and a small circuit size. The data conversion apparatus is provided with a first data converter to reduce the number of bits of an input signal, a second data converter to convert the format of the first output signal, and a third data converter for conversion into a code which corresponds to the history of the output from the second data converter.

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04-07-2013 дата публикации

Interpolation of Filter Coefficients

Номер: US20130170582A1
Принадлежит: St Ericsson SA

The frequency response of a digital filter, such as a pre-emphasis filter in a signal transmitter having a phase-locked loop, is adjusted using interpolation of the filter coefficients, enabling sets of filter coefficients to be pre-computed or generated as needed in the transmitter. The phase error behavior of the digital filter can be significantly improved.

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18-07-2013 дата публикации

Data Processing Method and System

Номер: US20130181769A1
Автор: Akira Noda
Принадлежит: Shimadzu Corp

For an input signal with a ringing superposed thereon, a ringing-generating filter ( 12 ) generates an analogous ringing waveform from only a peak portion of the signal which precedes the ringing. A subtractor ( 11 ) subtracts the analogous ringing waveform from the input signal to eliminate the ringing. The coefficient of the filter ( 12 ) is determined by applying a calculation method similar to a polynomial division based on the complete pivoting Gaussian elimination to polynomials using a reference data expressing a peak waveform and a ringing waveform, and by using a least squares method for minimizing the square of the covariance so as to allow the presence of noise in the data. Furthermore, by a repetitive process on a plurality of the same datasets, the calculation accuracy of the coefficient is improved even under the condition that the ringing frequency is high and the number of samples in one cycle is small. Thus, the ringing can be correctly eliminated even if the signal frequency is high.

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25-07-2013 дата публикации

DIGITAL RE-SAMPLING APPARATUS USING FRACTIONAL DELAY GENERATOR

Номер: US20130187694A1
Принадлежит: INNOWIRELESS CO., LTD.

Disclosed herein is a digital re-sampling apparatus. The digital re-sampling apparatus includes a sample buffer, a sample buffer control unit, a filter bank, a first delay bank, a fractional delay constant table, a combiner bank, and a second delay bank. The sample buffer temporarily stores an input sample in synchronization with an input sampling frequency. The sample buffer control unit controls writing and reading operations. The filter bank includes a number of digital filters equal to the number of stages, and filters the input sample. The first delay bank differentially delays a filter output value. The fractional delay constant table stores information about re-sampling time. The combiner bank includes a number of adders and multipliers, performs an operation, and outputs a re-sampled value. The second delay bank causes a delay so that output of each combiner can be synchronized with each output of the fractional delay constant table. 1. A digital re-sampling apparatus using a fractional delay generator , comprising:a sample buffer for temporarily storing an input sample in synchronization with an input sampling frequency;a sample buffer control unit for controlling writing and reading operations of the sample buffer;a filter bank for digital filtering of the input samples, and comprising multiple digital filters composed of multiple taps, as many as the number of the stages in the filter bank;a first delay bank for differentially delaying the outputs of the filters in the filter bank based on the corresponding number of the stages;a fractional delay constant table for storing information on time for re-sampling of the input samples;a combiner bank for generating a re-sampled output for every re-sampling time through arithmetic operations performed with the output of the first delay bank and the fractional delay constant stored in the fractional delay constant table, and comprising combiners composed of combinations of adders and multipliers, as many as the ...

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03-10-2013 дата публикации

Digital filter circuit and digital filter control method

Номер: US20130262545A1
Автор: Atsufumi Shibayama
Принадлежит: NEC Corp

[Objective] To provide a digital filter circuit and a digital filter control method which are capable of reducing circuit scale and power consumption for filter processing in a frequency domain such as an overlap FDE method. [Solution] A digital filter circuit according to the present invention includes: an overlap addition means for giving an overlap of M data (M is a positive integer) between the block and the previous block; an FFT processing means for transforming the generated block by FFT processing; a filter computation means for performing filter processing to the transformed block; an IFFT means for transforming the block, which the filter processing was performed to, by IFFT processing; an overlap removal means for removing M units of data from both ends of the transformed block; and a clock generation means for setting the frequency of a filter processing clock signal based on a value of M, wherein the filter processing clock signal drives the data output unit of the overlap addition means, the FFT means, the filter computation means, the IFFT means, and the input unit of the overlap removal means.

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17-10-2013 дата публикации

Filter system

Номер: US20130275483A1
Принадлежит: SIEMENS AG

A filter system with infinite impulse response is provided. The filter system has a transfer function that includes at least one pair of first order polynomial fractions. In one embodiment, the poles and/or the zeros of the pair of polynomial fractions are complex conjugates, respectively. The gain of the transfer function is realized, for example, by virtue of at least two separate multiplier elements

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24-10-2013 дата публикации

Shift-Invariant Digital Sampling Rate Conversion System

Номер: US20130279562A1
Автор: Stéphan Tassart
Принадлежит: St Ericsson SA

There is described a method of making a linear periodically time varying system shift-invariant, comprising the following steps implemented for each input signal the sampling rate of which has to be converted: —generating a set of polyphase components based on the input signal, —feeding the generated set of polyphase components to the system, and —generating an output signal by performing interleaving, shifting and addition on signals output by the system corresponding to the generated set of polyphase components processed by the system.

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24-10-2013 дата публикации

SIGNAL DECOMPOSITION, ANALYSIS AND RECONSTRUCTION

Номер: US20130282339A1
Принадлежит: Digital Intelligence, L.L.C.

The present invention provides a system and method for representing quasi-periodic (“qp”) waveforms comprising, representing a plurality of limited decompositions of the qp waveform, wherein each decomposition includes a first and second amplitude value and at least one time value. In some embodiments, each of the decompositions is phase adjusted such that the arithmetic sum of the plurality of limited decompositions reconstructs the qp waveform. These decompositions are stored into a data structure having a plurality of attributes. Optionally, these attributes are used to reconstruct the qp waveform, or patterns or features of the qp wave can be determined by using various pattern-recognition techniques. Some embodiments provide a system that uses software, embedded hardware or firmware to carry out the above-described method. Some embodiments use a computer-readable medium to store the data structure and/or instructions to execute the method. 1. An apparatus comprising:a computer having a storage device;means for obtaining a digitized quasi-periodic waveform;means for digitally filtering the digitized quasi-periodic waveform into a plurality of frequency-band components;means, using the computer, for forming a plurality of first data structures, each of the plurality of first data structures having a plurality of fractional-phase labels, each corresponding to one of a plurality of fractional phases that are each delimited by a plurality of fractional-phase time values, for each of a plurality of local cycles of a respective one of the plurality of frequency-band components;means, using the computer, for generating a plurality of states, each state including one fractional-phase label from each of the first data structures, wherein the fractional-phase labels of each state are coactive for that state, and wherein the plurality of states have a sequence; andmeans for storing the states and the sequence in the storage device accessible by the computer.2. An apparatus ...

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24-10-2013 дата публикации

NICAM Decoder with Output Resampler

Номер: US20130282385A1
Принадлежит: THAT Corp

A NICAM audio signal re-sampler may include a non-linear interpolator configured to interpolate in a non-linear manner between sequential digital samples that are based on a stream of demodulated NICAM audio samples. A phase differential calculator may be included that compares phase information at different resolutions.

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31-10-2013 дата публикации

Reduced-delay subband signal processing system and method

Номер: US20130287226A1
Автор: Yair Kerner
Принадлежит: Conexant Systems LLC

A method for signal processing, receiving a time domain signal having a sample-rate Fs and generating N time domain signal bands, each having a bandwidth equal to Fs/N. Receiving the N signal bands and transforming a first time domain signal band to a frequency domain at a first resolution and a second time domain signal band to the frequency domain at a second resolution, where the first resolution may be different from the second resolution. Determining one or more first filter coefficients using the frequency domain components from the first signal band and one or more second filter coefficients using the frequency domain components from the second signal band. Transforming the first and second filter coefficients from the frequency domain to a time domain. Applying the first and second time domain filter coefficients to the first and second time domain signals, respectively.

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12-12-2013 дата публикации

Method and apparatus for efficient frequency-domain implementation of time-varying filters

Номер: US20130332498A1
Автор: Earl Corban Vickers
Принадлежит: STMicroelectronics lnc USA

Embodiments are directed to efficient frequency-domain implementations of time-varying FIR filters. More specifically, time-varying FIR filters according to embodiments exploit the duality of the fast Fourier transform that windowing in the time domain equals convolution in the frequency domain. In one embodiment, convolution of the output of the FIR filter and a desired windowing function is performed in the frequency domain instead of taking the output of the FIR filter in the frequency domain, converting this output the time domain via an IFFT, and then windowing this output in the time domain before again converting back to the frequency domain. As long as the windowing function has certain characteristics, then the time-varying FIR filter is computationally efficient and introduces minimal audible artifacts into the output of the filter. Concepts described herein are discussed in terms of audio signals and systems but are not limited to audio signals and systems.

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12-12-2013 дата публикации

SIGNAL PROCESSING APPARATUS, SIGNAL PROCESSING METHOD, STORAGE MEDIUM

Номер: US20130332500A1
Принадлежит: NEC Corporation

To obtain a high-quality enhanced signal, disclosed is a signal processing apparatus including a transform unit that transforms a mixed signal in which a first signal and a second signal coexist, into a phase component and a magnitude component or power component for each frequency, a first control unit that replaces the phase component of a predetermined frequency, a second control unit that modifies the magnitude component or power component of the predetermined frequency in accordance with the amount of a change of the magnitude component or power component that arises from replacement by the first control unit, and a reconstruction unit that reconstructs the phase component replaced by the first control unit and the magnitude component or power component modified by the second control unit. 1. A signal processing apparatus comprising:a transform unit that transforms a mixed signal in which a first signal and a second signal coexist, into a phase component and a magnitude component or power component for each frequency;a first control unit that replaces the phase component of a predetermined frequency;a second control unit that modifies the magnitude component or power component of the predetermined frequency in accordance with an amount of a change of the magnitude component or power component that arises from replacement by said first control unit; anda reconstruction unit that reconstructs the phase component replaced by said first control unit and the magnitude component or power component modified by said second control unit.2. The signal processing apparatus according to claim 1 , whereinsaid first control unit includes a replacement amount generation unit that generates a replacement amount of the phase component, andsaid second control unit calculates the change amount based on the replacement amount provided from the replacement amount generation unit, and modifies the magnitude component or power component in accordance with the calculated change amount ...

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19-12-2013 дата публикации

DIGITAL SIGNAL-PROCESSING STRUCTURE AND METHODOLOGY FEATURING ENGINE-INSTANTIATED, WAVE-DIGITAL-FILTER CASCADING/CHAINING

Номер: US20130339416A1
Принадлежит: Acoustic Processing Technology, Inc.

Filter-chain-creating, digital signal-processing structure, for performing frequency band analysis and selection, which structure features a time-slice-based digital fabricating/instantiating engine, and engine-software-operating structure designed to operate the engine in a time-slice-based fabrication mode to create a chained arrangement of at least one of (a) Type-I, and (b) combined Type-I and Type-I wave digital filter (WDF) agencies in an overall, composite WDF structure to function for frequency band analysis and selection. 1. Signal-processing structure designed for frequency band analysis and selection comprisingan electronic engine designed to fabricate, in an instantiated manner, different, time-successive, chained wave digital filter (WDF) agencies structured to function for frequency band analysis and selection, andcontrol code structure operatively and drivingly connected to said engine, constructed to operate the engine in a fashion which includes instructing the engine to form said chained arrangement.2. Signal-processing structure designed for frequency band analysis and selection comprising{'sub': ';', 'sup': 'th', 'an electronic engine designed to fabricatein an instantiated manner, different, time-successive, 5-Order elliptical wave digital filter (WDF) sections created to form portions of a chained arrangement of at least one of (a) Typed, and (b) combined Type-I and Type-II agencies in an overall, composite WDF structure to function for frequency band analysis and selection, and through which sections a signal to be processed passes, each said section including a pair of branches possessing assigned, Gamma-factor multipliers, with one branch in each said pair optionally including a delay element, and'}control code structure operatively and drivingly connected to said engine, constructed to operate the engine in a fashion which includes instructing the engine, with regard to the instantiated fabrication of each said WDF section instance, and ...

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26-12-2013 дата публикации

Method and device for filtering a signal and control device for a process

Номер: US20130346460A1
Принадлежит: SIEMENS AG

A method for filtering a signal is proposed. A noisy input signal is continuously examined in order to determine whether the input signal it is within or outside a deadband. The deadband width and the zero point of the deadband are continuously adapted to the noise power of the input signal depending on the time behavior of the input signal and a predefined system time constant. At least one filtered output signal is continuously output, such as a deadband signal, which substantially corresponds to a smoothed input signal.

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02-01-2014 дата публикации

Method and Apparatus for Detecting the Presence of a Signal in a Frequency Band Using Non-Uniform Sampling

Номер: US20140003556A1
Автор: Ajay K. Luthra
Принадлежит: MOTOROLA MOBILITY LLC

A method and apparatus for detecting the presence of a signal in a frequency band using non-uniform sampling includes an analog to digital converter (ADC) ( 110 ) for sampling an analog input signal ( 105 ) to create discrete signal samples ( 115 ), an ADC exciter ( 120 ) for exciting the ADC to sample at non-uniform time periods, a digital filter ( 130 ) for converting the discrete signal samples into an energy versus frequency spectrum ( 300 ), and an energy comparator ( 140 ) coupled to an output of the digital filter. The energy comparator ( 140 ) detects the presence of any frequency bands exceeding an energy setpoint.

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09-01-2014 дата публикации

Systems and Methods for Filter Initialization and Tuning

Номер: US20140012888A1
Принадлежит: LSI Corporation

Various embodiments of the present invention provide systems and methods for data filter tuning. As an example, a method for filter tuning is disclosed that includes: providing a tunable filter having an operation filter and a calibration filter; applying a low frequency test input to the operation filter in place of an input signal to yield a first filter output; calculating a low frequency magnitude value corresponding to the first filter output; applying a high frequency test input to the operation filter in place of an input signal to yield a second filter output; calculating a high frequency magnitude value corresponding to the second filter output; modifying a tuning factor of the calibration filter when a ratio of the high frequency magnitude value and the low frequency magnitude value is outside of a defined range; and storing the tuning factor of the calibration filter when the ratio of the high frequency magnitude value and the low frequency magnitude value is within the defined range. 1. A method for selecting a cutoff frequency in a tunable filter circuit , the method comprising:providing a tunable filter circuit initialized to include a first set of tuning values corresponding to a first cutoff frequency and a second set of tuning values corresponding to a second cutoff frequency;receiving a request to operate the tunable filter circuit at a requested cutoff frequency; andprogramming the tunable filter circuit to operate at the requested cutoff frequency using at least one of the first set of tuning values and the second set of tuning values.2. The method of claim 1 , wherein the requested cutoff frequency is equal to the first cutoff frequency claim 1 , and wherein programming the tunable filter circuit to operate at the requested cutoff frequency uses the first set of tuning values.3. The method of claim 1 , wherein the requested cutoff frequency is greater than the first cutoff frequency and less than the second cutoff frequency claim 1 , and wherein ...

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16-01-2014 дата публикации

METHOD AND DEVICE FOR FILTERING DURING A CHANGE IN AN ARMA FILTER

Номер: US20140019504A1
Принадлежит:

A method and device are provided for filtering digital audio signals using at least one ARMA filter, particularly during a filter change. The method includes the following steps: a step of receiving a first request to change filtering to or from filtering by a first ARMA filter; and, in response to the first request, a step of gradually switching, at each of a plurality of cascaded first filtering blocks, between digital-signal filtering by a first basic filtering cell and digital-signal filtering by another associated basic filtering cell, the first basic filtering cells of the plurality of first filtering blocks factorizing the first filter. 1. A process for filtering a digital signal , the process comprising:a receiving step of a first request for filtering change to or from filtering by a first ARMA filter, wherein in response to said first request the method comprises a progressive switching step at a level of each of a plurality of first cascaded filtering blocks between digital signal filtering by a first elementary filtering cell originating from factorisation of the first filter and digital signal filtering by another associated elementary filtering cell, andwherein all of said first elementary filtering cells of the plurality of first filtering blocks factorise said first ARMA filter.2. The process as claimed in claim 1 , wherein the progressive switching at the level of a first filtering block comprises the combination of a filtered signal by the first elementary filtering cell with a filtered signal by the other associated elementary filtering cell to produce a mixed output signal of a filtering block during progressive switching.3. The process as claimed in claim 2 , wherein said progressive switching uses fades whereof fade coefficients corresponding are applied to the signals filtered by the first elementary filtering cells and by the other elementary filtering cells.4. The process as claimed in claim 2 , wherein within each first filtering block said ...

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06-02-2014 дата публикации

Cascaded Digital Filters with Reduced Latency

Номер: US20140040339A1
Принадлежит:

A filter and method for filtering a signal are disclosed. The filter is equivalent to a plurality of bi-quad filters connected in series, and is implemented on a digital processor that receives a sequence of signal values at a sampling rate characterized by a sampling interval and generates a filtered signal value upon receiving each received signal value. The filter has a latency that is less than the sampling interval. The filtered values can be generated by adding a term to a received signal value and multiplying the sum by a gain constant that depends on the filter constants. The added term does not depend on the current received signal value. The filter can be implemented in fixed-point integer arithmetic. 1. A filter comprising any positive integer number of poles and zeros where this filter is equivalent to a plurality of bi-quad and/or bilinear filters connected in series , said filter being implemented on a digital processor that receives a sequence of signal values at a sampling rate characterized by a sampling interval and generates a filtered signal value upon receiving each received signal value , said filter having a latency that is less than said sampling interval.2. The filter of wherein said filter is characterized by a number of parameters and wherein said latency is independent of said number of parameters.3. The filter of wherein said processor generates each filtered signal value by adding a term to a received signal value and multiplying the sum by a gain constant that depends on said constants claim 1 , wherein said term does not depend on said received signal value.4. The filter of wherein said term depends on previously received signal values and constants characterizing said series-connected bi-quad filters.5. The filter of wherein said plurality of bi-quad filters comprises a plurality of unit direct feedthrough gain bi-quad filters flowed by a gain stage.6. The filter of wherein a plurality of the unit direct feedthrough gain bi-quad ...

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06-02-2014 дата публикации

Whitening filter configuration method, program, and system

Номер: US20140040340A1
Автор: Junya Shimizu
Принадлежит: International Business Machines Corp

A system is configured so that signals passed through an all-pass filter using warp parameter λ are whitening-filtered, and so that the frequency axis is restored by an all-pass filter using warp parameter λ. This optimizes the whitening filter by determining the optimum λ. First, the AR order p is automatically estimated using λ=0. A spectral distance dλ is computed using a discrete Fourier transform spectrum value passed through an all-pass filter using warp parameter λ and a discrete AR spectrum value passed through an all-pass filter using warp parameter λ. The λ which minimizes the spectral distance dλ is set as the warp parameter, and a whitening filter is configured in which the warp parameter has been optimized.

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06-03-2014 дата публикации

Filter calculating device, transmitting device, receiving device, processor, and filter calculating method

Номер: US20140064354A1
Принадлежит: Sharp Corp

A filter calculating device includes a first equalization filter calculating section that generates at least a first conversion matrix and a first triangular matrix based on a channel state of a first channel; a first quasi-orthogonalization section that calculates a first unimodular matrix based on the first triangular matrix; and a second equalization filter calculating section that generates at least a second conversion matrix and a second triangular matrix based on a channel state of a second channel and the first unimodular matrix.

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20-03-2014 дата публикации

Passive switched-capacitor filters conforming to power constraint

Номер: US20140082038A1
Принадлежит: QUALCOMM INCORPORATED

Passive switched-capacitor (PSC) filters are described herein. In one design, a PSC filter implements a second-order infinite impulse response (IIR) filter with two complex first-order IIR sections. Each complex first-order IIR section includes three sets of capacitors. A first set of capacitors receives a real input signal and an imaginary delayed signal, stores and shares electrical charges, and provides a real filtered signal. A second set of capacitors receives an imaginary input signal and a real delayed signal, stores and shares electrical charges, and provides an imaginary filtered signal. A third set of capacitors receives the real and imaginary filtered signals, stores and shares electrical charges, and provides the real and imaginary delayed signals. In another design, a PSC filter implements a finite impulse response (FIR) section and an IIR section for a complex first-order IIR section. The IIR section includes multiple complex filter sections operating in an interleaved manner. 1. An apparatus comprising:a first complex first-order infinite impulse response (IIR) section operative to receive and filter a complex input signal and provide a complex filtered signal; anda second complex first-order IIR section coupled to the first complex first-order IIR section and operative to receive and filter the complex filtered signal and provide a complex output signal.2. The apparatus of claim 1 , wherein the first and second complex first-order IIR sections are implemented with first and second passive switched-capacitor (PSC) filter sections claim 1 , each PSC filter section comprising a plurality of capacitors and a plurality of switches.3. The apparatus of claim 1 , wherein the first complex first-order IIR section is defined by a first complex coefficient and the second complex first-order IIR section is defined by a second complex coefficient claim 1 , the second complex coefficient being a complex conjugate of the first complex coefficient.4. An apparatus ...

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27-03-2014 дата публикации

Processor having instruction set with user-defined non-linear functions for digital pre-distortion (dpd) and other non-linear applications

Номер: US20140086361A1
Принадлежит: LSI Corp

A processor is provided having an instruction set with user-defined non-linear functions for digital pre-distortion (DPD) and other non-linear applications. A signal processing function, such as DPD, is implemented in software by obtaining at least one software instruction that performs at least one non-linear function for an input value, x, wherein the at least one non-linear function comprises at least one user-specified parameter; in response to at least one of the software instructions for at least one non-linear function having at least one user-specified parameter, performing the following steps: invoking at least one functional unit that implements the at least one software instruction to apply the non-linear function to the input value, x; and generating an output corresponding to the non-linear function for the input value, x. The user-specified parameter can optionally be loaded from memory into at least one register.

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10-04-2014 дата публикации

DECIMATION FILTER

Номер: US20140101218A1
Автор: Tinker Darrell Eugene
Принадлежит: SIGMATEL, INC.

A system includes a decimation module having an adjustable decimation rate and a filter module responsive to the decimation module. A digital phase lock loop is operable to control a decimation rate of the decimation module. The decimation module is a cascade integrator comb decimation module. 120-. (canceled)21. A system comprising:a decimation module having an adjustable decimation rate, wherein the decimation module is a cascade integrator comb decimation module;a filter module responsive to the decimation module;a delta sigma modulator to receive an analog input signal, the delta sigma modulator responsive to a first clock;a bus interface module responsive to the filter module, the bus interface module responsive to a second clock; anda digital phase lock loop configured to control the adjustable decimation rate of the decimation module, wherein the digital phase lock loop adjusts the adjustable decimation rate of the decimation module based on a difference between a rate of the first clock and a rate of the second clock.22. The system of claim 21 , wherein the first clock is based on an on-chip clock and the second clock is based on an external clock.23. The system of claim 21 , wherein the filter module includes a plurality of finite impulse response filters.24. The system of claim 21 , wherein the adjustable decimation rate includes a non-integer portion to allow decimation at a non-integer rate.25. The system of claim 21 , wherein the digital phase lock loop is configured to control the adjustable decimation rate of the decimation module via an adjustable rate decimation signal.26. The system of claim 25 , wherein the decimation module includes an output adjustment module claim 25 , a variable rate down sampling module claim 25 , and an adder.27. The system of claim 26 , wherein the output adjustment module is configured to add an adjustment factor to an output of the variable rate down sampling module claim 26 , and wherein the adjustment factor is based on ...

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01-01-2015 дата публикации

N-Order Noise Shaper

Номер: US20150003502A1
Автор: Andreas Menkhoff
Принадлежит: Individual

An n-order noise shaper has an order n≧3, wherein a first set of polynomial coefficients are optimized with respect to a useful band and wherein a second set of polynomial coefficients are optimized with respect to an optimization aim depending on an overall out of band noise and/or on a maximum out of band noise.

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04-01-2018 дата публикации

PHASE FREQUENCY DETECTION DEVICE

Номер: US20180003750A1
Принадлежит: Mitsubishi Electric Corporation

Filter circuitry is constituted by transversal filters which are connected in parallel to each other. The transversal filters change amplitude and a phase of an input digital signal X[n·T] and output different digital signals X[n·T], X[n·T], and X[n·T] as respective resulting digital signals whose amplitude and phase have been changed. A phase frequency computer computes a phase θ[n·T] and a frequency f[n·T] of the input digital signal X[n·T] by performing phase computation and frequency computation using the digital signals X[n·T], X[n·T], and X[n·T] output by the transversal filters. 1. (canceled)2. A phase frequency detection device comprising:filter circuitry including a plurality of transversal filters which are connected in parallel to each other, the plurality of transversal filters changing amplitude and a phase of an input digital signal and outputting different digital signals as respective resulting digital signals whose amplitude and phase have been changed; anda phase frequency computer to compute a phase and a frequency of the input digital signal by performing phase computation and frequency computation using the digital signals output by the plurality of transversal filters,whereinthe filter circuitry is constituted such that a first transversal filter, a second transversal filter, and a third transversal filter, as the plurality of transversal filters, are connected in parallel to each other, andthe phase frequency computer includes:first division computation circuitry to perform a division computation between a digital signal output by the first transversal filter and a digital signal output by the second transversal filter, and to output a first division computation signal being a result of the division computation;second division computation circuitry to perform a division computation between a digital signal output by the third transversal filter and the digital signal output by the second transversal filter, and to output a second division ...

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02-01-2020 дата публикации

Method for Determining a Time of Contact on a Capacitive Sensor Element

Номер: US20200004380A1
Принадлежит: Leopold Kostal GmbH & Co. KG

A method for determining a time of contact of a capacitive sensor includes continuously measuring a capacitance value of the capacitive sensor and processing the measured capacitance value into a digital sensor signal. The sensor signal is filtered to output a filter signal. Initial dynamics of the filter signal are identified upon the filter signal exceeding a first set filter threshold value. A time at which the filter signal falls below a second set filter threshold value is determined as being a potential time of contact of the capacitive sensor. An actual time of contact of the capacitive sensor is determined when the sensor signal relative to an offset of the sensor signal exceeds a sensor signal threshold value. The offset of the sensor signal is a value of the sensor signal prior to the contact of the capacitive sensor. 1. A method for determining a time of contact of a capacitive sensor , the method comprising:continuously measuring a capacitance value of the capacitive sensor and processing the measured capacitance value into a digital sensor signal (SS);filtering the sensor signal (SS) by a digital filter to output therefrom a filter signal (F S);{'b': '1', 'identifying initial dynamics of the filter signal (FS) upon the filter signal (FS) exceeding a first set filter threshold value (FT);'}{'b': '2', 'determining a time at which the filter signal (FS) falls below a second set filter threshold value (FT) as being a potential time of contact of the capacitive sensor;'}{'b': '1', 'determining an actual time of contact of the capacitive sensor when the sensor signal (SS) relative to an offset of the sensor signal (SS) exceeds a sensor signal threshold value (ST), wherein the offset of the sensor signal (SS) is a value of the sensor signal (SS) prior to the contact of the capacitive sensor; and'}outputting the actual time of contact of the capacitive sensor.2. The method of wherein:the digital filter is a FIR filter.3. The method of wherein:the FIR filter has ...

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07-01-2021 дата публикации

SENSING DEVICE WITH FINGERPRINT SENSOR

Номер: US20210004097A1
Принадлежит: SAMSUNG ELECTRO-MECHANICS CO., LTD.

A sensing device with a fingerprint sensor is provided. The sensing device includes a touch input pattern included in the fingerprint sensor, an oscillation circuit connected to the touch input pattern and configured to change a capacitance of the oscillation circuit when a touch occurrence is sensed by the touch input pattern and generate an oscillation signal based on the change in the capacitance, and an operation detection circuit configured to detect a touch occurrence based on a frequency included in the oscillation signal input from the oscillation circuit and generate a detection signal. 1. A sensing device comprising:a sensor;a touch input pattern included in the sensor;an oscillation circuit connected to the touch input pattern, and configured to change a capacitance of the oscillation circuit when a touch occurrence is sensed by the touch input pattern, and generate an oscillation signal based on the change in the capacitance; anda detection circuit configured to detect the touch occurrence based on a frequency included in the oscillation signal and generate a detection signal.2. The device of claim 1 , wherein the oscillation signal is input to the operation detection circuit from the oscillation circuit.3. The device of claim 1 , wherein the sensor is a fingerprint sensor.4. The device of claim 3 , wherein the touch input pattern is a conductor pattern that includes a portion of a plurality of fingerprint recognition patterns included in the fingerprint sensor.5. The device of claim 3 , wherein the touch input pattern is a conductor pattern that is disposed separately from a plurality of fingerprint recognition patterns included in the fingerprint sensor.6. The device of claim 3 , wherein the oscillation circuit comprises:an inductance circuit comprising a coil element disposed on an external surface of the fingerprint sensor; anda capacitance circuit disposed on the external surface of the fingerprint sensor, and comprising a capacitor device spaced ...

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07-01-2016 дата публикации

Semi-Analog FIR Filter With High Impedance State

Номер: US20160006416A1
Автор: Mallinson A. Martin
Принадлежит:

A system and method is disclosed for placing some of the elements of a FIR filter into a high impedance state in certain situations. When it is detected that the signal to an impedance element is the same as the previous value, then the driver of that impedance element is “turned off” or goes into a high impedance state, so that no current flows through that impedance element, and it no longer contributes to the filter output. Alternatively, if the impedance elements are the same between two adjacent taps of the delay line, the driver of one of those impedance elements may be turned off or go into a high impedance state. The technique may be particularly useful in differential output filters. Turning off a driver effectively removes the attached impedance element from the filter and reduces current flow and power consumption, thus extending battery life in mobile devices. 1. A finite impulse response filter comprising:an input configured to receive an input signal;a delay line comprising a plurality of delay elements in series and connected to the input for propagating and delaying the input signal;a plurality of buffers, each buffer in the plurality of buffers coupled to the delay line after a separate one of the plurality of delay elements so as to receive the delayed input signal after the input signal has passed through the connected delay element;a plurality of control elements, each control element in the plurality of control elements coupled to a separate one of the plurality of buffers and configured to detect the delayed input signal immediately before and after the delay element to which the buffer is coupled and cause the buffer connected to the control element to not pass the delayed input signal through the buffer if the delayed input signal immediately before the delay element to which the buffer is coupled is the same as the delayed input signal after the same delay element;a plurality of impedance elements having impedance values, each of the ...

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02-01-2020 дата публикации

Multi-signal realignment for changing sampling clock

Номер: US20200005819A1
Принадлежит: SEAGATE TECHNOLOGY LLC

An apparatus may include a circuit configured to receive first and second samples of an underlying data from respective first and second sample periods and which correspond to respective first and second sensors, a phase control value may have first and second values during respective first and second sample periods. The phase control value may be a control value for a sample clock signal. The circuit may also determine a difference in the phase control value between the first value and the second value. The circuit may then digitally interpolate the first and second samples to produce a phase shifted first and second samples where the digital interpolation of at least one of the first and second samples mat be at least in part based on the difference in the phase control value to compensate for a phase misalignment between the first sample and the second sample.

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07-01-2021 дата публикации

SWITCHING OPERATION SENSING APPARATUS WITH TOUCH INPUT MEMBER IDENTIFICATION

Номер: US20210006246A1
Принадлежит: SAMSUNG ELECTRO-MECHANICS CO., LTD.

A switching operation sensing apparatus includes an input operation unit, an oscillation circuit, a frequency digital converter, and a touch detection circuit. The input operation unit includes a first switching member integrally formed with a housing. The oscillation circuit is configured to generate an oscillation signal having a resonant frequency, varying based on a capacitive change or an inductive change, depending on a touch input member in contact with the first switching member during an input operation. The frequency digital converter is configured to convert the oscillation signal into a count value. The touch detection circuit is configured to detect capacitive sensing and inductive sensing based on a slope change of the count value received from the frequency digital converter, and output corresponding touch detection signals of different levels based on the detection. 1. A switching operation sensing apparatus configured to be added to an electronic device , the electronic device comprising an input operation unit , the input operation unit comprising a first switching member disposed on a housing , the switching operation sensing apparatus comprising:an oscillation circuit configured to generate an oscillation signal having a resonant frequency, varying based on a capacitive change or an inductive change, depending on a touch input object in contact with the first switching member;a frequency digital converter configured to convert the oscillation signal into count values; anda touch detection circuit configured to detect capacitive sensing or inductive sensing based on a slope change of the count values received from the frequency digital converter, and output corresponding touch detection signals based on the detection.2. The switching operation sensing apparatus of claim 1 , wherein the corresponding touch detection signals have different levels with each other.3. The switching operation sensing apparatus of claim 1 , wherein the frequency digital ...

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07-01-2021 дата публикации

Data Recovery using Subcarriers Gradients

Номер: US20210006447A1
Автор: John W. Bogdan
Принадлежит: Individual

The data recovery from sub-carriers gradients (DRSG) of a received OFDM signal affected by deterministic and random distortions introduced by a transmission link, contributes a method and a circuit for utilizing gradients characterizing shapes of OFDM sub-carriers comprised in such OFDM signal for recovering data symbols transmitted originally.

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03-01-2019 дата публикации

Ultra-low power receiver

Номер: US20190007088A1

An ultra-low-power receiver includes a low-noise amplifier configured to receive an input analog signal and generate an amplified signal and a mixer electrically coupled to the low-noise amplifier. The mixer is configured to convert said amplified signal into an intermediate frequency signal. A progressively reduced intermediate frequency filter is configured to process the intermediate frequency signal from the mixer in discrete time.

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08-01-2015 дата публикации

DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS

Номер: US20150008956A1
Автор: MILLAR Bruce
Принадлежит:

A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination. 1. (canceled)2. A method for controlling the impedance of a buffer having a plurality of pull-up transistors and a plurality of pull-down transistors , the method comprising:receiving a data output signal;receiving an output enable signal;receiving a termination enable signal;receiving a first plurality of impedance control bits, a second plurality of impedance control bits, a third plurality of impedance control bits, and a fourth plurality of impedance control bits;enabling, when the output enable signal is in a first state and the data output signal is in a first state, one or more of the plurality of pull-up transistors determined by the first plurality of impedance control bits;enabling, when the output enable signal is in a first state and the data output signal is in a second state, one or more of the plurality of pull-down transistors determined by the second plurality of impedance control bits; andenabling, when the termination enable signal is in a first state, one or more of the plurality of pull-up transistors determined by the third plurality of impedance control bits and one or more of the plurality of pull-down transistors determined by the fourth plurality of impedance control bits;wherein the first and second pluralities of impedance control bits ...

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08-01-2015 дата публикации

BUFFER OFFSET MODULATION

Номер: US20150009056A1
Принадлежит:

One or more techniques for buffer offset modulation or buffer offset cancelling are provided herein. In an embodiment, an output for a sigma-delta analog digital converter (ADC) is provided using an output of a first chop-able buffer (FB) and an output of a second chop-able buffer (SB). For example, the output of the FB is associated with a first offset, the output of the SB is associated with a second offset, and the output of the ADC includes an ADC offset associated with the first offset and the second offset. In an embodiment, buffer offset modulation is provided by modulating the ADC offset using an offset rotation. In an example, the offset rotation is based at least in part on a reference clock and the output of the ADC. The buffer offset modulation mitigates the first offset or the second offset, where such offsets are generally undesired.

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20-01-2022 дата публикации

ANALOG FIR FILTER

Номер: US20220021374A1
Принадлежит:

A FIR filter (), comprising an input terminal for receiving an input signal, a first filtering circuit comprising: a first transconductance device () configured to generate a first current signal (i) proportional to the input signal; a first analog switch () commuted in n by a first digital gate signal (ϕ) and configured to block the current signal when the first digital gate signal has a first value and to transmit the current signal to a first integrating capacitor () when the first digital gate signal has a second value; characterized in that the first digital gate signal (ϕ) comprises a periodic series of pulses, wherein the pulses have widths proportional to the filter coefficients. 1. A FIR filter , comprising an input terminal for receiving an input signal , a first filtering circuit comprising: a first integrating capacitor , a first transconductance device configured to generate a first current signal proportional to the input signal; a first analog switch commuted by a first digital gate signal and configured to block the current signal when the first digital gate signal has a first value and to transmit the first current signal to the first integrating capacitor when the first digital gate signal has a second value; wherein the first digital gate signal comprises a periodic series of pulses , wherein the pulses have widths proportional to a set of coefficients of the FIR filter.2. The FIR filter of claim 1 , having a gate generator comprising a memory storing the filter coefficients and a digital-to-time converter claim 1 , wherein the filter coefficients are read from the memory and provided to the digital-to-time converter sequentially and synchronously with a clock signal claim 1 , and the digital-to-time converter generates for each received filter coefficient a pulse having a width proportional thereto.3. The FIR filter claim 1 , wherein the first integrating capacitor is periodically reset.4. The FIR filter of claim 1 , wherein the charge stored in ...

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12-01-2017 дата публикации

METHOD AND APPARATUS FOR SIGNAL FILTERING AND FOR IMPROVING PROPERTIES OF ELECTRONIC DEVICES

Номер: US20170012608A1
Автор: Nikitin Alexei V.
Принадлежит: AVATEKH, INC.

The present invention relates to nonlinear signal processing, and, in particular, to adaptive nonlinear filtering of real-, complex-, and vector-valued signals utilizing analog Nonlinear Differential Limiters (NDLs), and to adaptive real-time signal conditioning, processing, analysis, quantification, comparison, and control. More generally, this invention relates to methods, processes and apparatus for real-time measuring and analysis of variables, and to generic measurement systems and processes. This invention also relates to methods and corresponding apparatus for measuring which extend to different applications and provide results other than instantaneous values of variables. The invention further relates to post-processing analysis of measured variables and to statistical analysis. The NDL-based filtering method and apparatus enable improvements in the overall properties of electronic devices including, but not limited to, improvements in performance, reduction in size, weight, cost, and power consumption, and, in particular for wireless devices, NDLs enable improvements in spectrum usage efficiency. 1. An apparatus for analog-to-digital conversion capable of converting an input signal into an output signal , wherein said input signal is a physical signal and wherein said output signal is a quantized representation of said input signal , the apparatus comprising a quantizer and a nonlinear loop filter , wherein said nonlinear loop filter comprises a nonlinear filtering stage characterized by a bandwidth and transforming a nonlinear filtering stage input signal into a nonlinear filtering stage output signal , and wherein said bandwidth is a non-increasing function of a magnitude of a difference between said nonlinear filtering stage input signal and a feedback of said nonlinear filtering stage output signal.2. The apparatus of wherein said input signal comprises a signal of interest and an interfering signal affecting said signal of interest claim 1 , wherein ...

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15-01-2015 дата публикации

Cable and compensation method for transmitting high speed signal and delivering power

Номер: US20150015078A1
Автор: KIM Ook
Принадлежит: SMARTPHY INC.

The present specification provides a cable and a compensation method for transmitting a high speed signal and delivering power. The cable according to one embodiment disclosed in the present specification interconnects a first device and a second device, the cable comprising: a power line for transmitting power from the first device to the second device; and a voltage restorer for restoring voltage loss of the power receiving side of the second device generated based on the voltage drop relevant to the power line. 1. A cable connecting a first device and a second device with each other , the cable comprising:a power line transferring power from the first device to the second device; anda voltage compensator compensating for a power receiving side voltage loss of the second device that is caused due to a voltage drop corresponding to the power line.2. The cable of claim 1 , wherein the voltage compensator includes a DC-DC (DC to DC) converter or a boost converter.3. The cable of claim 1 , wherein the voltage compensator compensates for the power receiving side voltage loss based on at least one of a line current flowing through the power line and a power receiving side voltage of the second device.4. The cable of claim 1 , further comprising a current detector detecting a line current flowing through the power line.5. The cable of claim 4 , wherein the voltage compensator compensates for the power receiving side voltage loss based on the detected line current and a line resistance determined depending on a length of the power line.6. The cable of claim 5 , wherein the voltage compensator detects a voltage drop by multiplying the detected line current with the line resistance and adjusts an output voltage of the voltage compensator to be the same as a voltage obtained by adding the detected voltage drop to an input voltage of the voltage compensator to thus compensate for the power receiving side voltage loss.7. The cable of claim 6 , wherein the voltage compensator ...

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14-01-2016 дата публикации

METHOD AND APPARATUS FOR FAST DIGITAL FILTERING AND SIGNAL PROCESSING

Номер: US20160013773A1
Автор: Dourbal Pavel
Принадлежит:

A method and a system for digital filtering comprising fast tensor-vector multiplication provide factoring an original tensor into a kernel and a commutator, multiplying the kernel obtained by the factoring of the original tensor, by the vector and thereby obtaining a matrix, and summating elements and sums of elements of the matrix as defined by the commutator obtained by the factoring of the original tensor, and thereby obtaining a resulting tensor which corresponds to a product of the original tensor and the vector. 1. A digital filter comprising a network of modules for implementing a filter transfer function as a fast tensor-vector multiplication , comprising the steps of factoring an original tensor into a kernel and a commutator; multiplying the kernel obtained by the factoring of the original tensor , by the vector and thereby obtaining a matrix; and summating elements and sums of elements of the matrix as defined by the commutator obtained by the factoring of the original tensor , and thereby obtaining a resulting tensor which corresponds to a product of the original tensor and the vector.2. The digital filter according to claim 1 , further comprising rounding elements of the original tensor to a desired precision and obtaining the original tensor with the rounded elements claim 1 , wherein the factoring includes factoring the original tensor with the rounded elements into the kernel and the commutator.3. The digital filter according to claim 1 , wherein the factoring of the original tensor includes factoring into the kernel which contains kernel elements that are different from one another claim 1 , and wherein the multiplying includes multiplying the kernel which contains the different kernel elements.4. The digital filter according to claim 1 , further comprising using as the commutator a commutator image in which indices of elements of the kernel are located at positions of corresponding elements of the original tensor.5. The digital filter according to ...

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11-01-2018 дата публикации

HIGH SPEED SAMPLING OF SENSORS

Номер: US20180013387A1
Автор: Fells Julian
Принадлежит:

Systems and methods for interrogating sensing systems utilising bursts of samples. Bursts of samples correspond to optical pulses returning from optical sensors, where pulses are spaced at a period significantly longer than the pulse width, giving irregular sample spacing. The interrogation system and method processes the irregular busts of samples to recover phase information from received signals. 1. A method of interrogating an optical sensing system performed at an interrogation system , comprising the steps of:receiving a plurality of bursts of samples of an optical signal, each burst of samples comprising a plurality of samples of each pulse in a group of discrete optical pulses, wherein the groups are regularly spaced in time with a group repetition period larger than the group width, and the optical pulses comprise a phase modulated signal;processing the bursts of samples to obtain a series of regularly spaced samples; anddemodulating the regularly spaced samples to retrieve the phase information from the detected pulses.2. A method according claim 1 , wherein processing the bursts of samples comprises processing the samples utilising a filter bank.3. A method according to claim 2 , wherein the filter bank comprises a number of parallel paths equal to the number of samples in each burst.4. A method according to wherein the step of processing comprises the steps of downsampling the received samples claim 1 , upsampling the downsampled samples claim 1 , filtering the upsampled samples claim 1 , and combining the filtered samples.5. A method according to claim 4 , wherein the downsampling ratio is equal to the sample rate in each burst divided by the group repetition frequency.6. A method according to claim 4 , wherein the upsampling is performed at a rate of the group width multiplied by the sample rate in each burst.7. A method of interrogating an optical sensing system performed at an interrogation system claim 4 , comprising the steps of:receiving a ...

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11-01-2018 дата публикации

Digital filter circuit, signal processing device, and digital filter processing method

Номер: US20180013409A1
Принадлежит: NEC Corp

Provided is a digital filter circuit in which a filter coefficient can be easily changed, for which circuit scale and power consumption can be reduced, and which carries out digital filter processing in a frequency domain. This digital filter circuit includes: a separating circuit for separating a first complex number signal, of a frequency domain that was subjected to Fourier transform, into a real number portion and an imaginary number portion; a filter coefficient generating circuit for generating a first frequency domain filter coefficient from a first input filter coefficient and a third input filter coefficient, and for generating a second frequency domain filter coefficient from a second input filter coefficient and the third input filter coefficient; a first filter that filters the separated real number portion using the first frequency domain filter coefficient; a second filter that filters the separated imaginary number portion using the second frequency domain filter coefficient; and a combining circuit for combining the output from the two filters.

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10-01-2019 дата публикации

Laser frequency chirping structures, methods, and applications

Номер: US20190013798A1
Принадлежит: ANALOG PHOTONICS LLC

Aspects of the present disclosure describe systems, methods, and structures including integrated laser systems that employ external chirping structures that may advantageously include phase shifters and/or one or more filters. Further aspects of the present disclosure describe systems, methods, and structures including laser systems that employ external chirping structures that may advantageously include optical phased arrays.

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14-01-2021 дата публикации

SIGNAL PROCESSOR, FILTER, CONTROL CIRCUIT FOR POWER CONVERTER CIRCUIT, INTERCONNECTION INVERTER SYSTEM AND PWM CONVERTER SYSTEM

Номер: US20210013794A1
Принадлежит:

A signal processor is configured to perform a process equivalent to performing a series of fixed-to-rotating coordinate conversion, a predetermined process and then rotating-to-fixed coordinate conversion, while maintaining linearity and time-invariance. The signal processor performs a process given by the following matrix G: 130-. (canceled)32. The signal processor according to claim 31 , wherein the transfer function F(s) is equal to one of K/s (Krepresents an integral gain) claim 31 , K+K/s (Krepresents a proportional gain claim 31 , and Krepresents an integral gain) or K+K/s+K(Krepresents a proportional gain claim 31 , Krepresents an integral gain claim 31 , and Krepresents a differential gain).33. A control circuit for controlling a plurality of switching units inside a power converter circuit by a PWM signal claim 31 , comprising:{'claim-ref': {'@idref': 'CLM-00031', 'claim 31'}, 'a signal processor according to ; and'}a PWM signal generator configured to generate a PWM signal based on an output from the signal processor.34. The control circuit according to claim 33 , wherein the power converter circuit relates to a three-phase alternate current.35. The control circuit according to claim 33 , further comprising a divergence determination unit and an output control unit claim 33 ,wherein the divergence determination unit is configured to determine, based on output signals from the signal processor, if control for driving the plurality of switching units tends to diverge, andwherein when the divergence determination unit determines that the control for driving the plurality of switching units tends to diverge, the output control unit stops the output signal or changes a phase of the output signal to another phase whereby the control for driving the plurality of switching units does not diverge.36. The control circuit according to claim 33 , wherein the power converter circuit comprises a converter circuit for conversion of AC power supplied from an electrical ...

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03-02-2022 дата публикации

STORAGE APPARATUS, HIGH DIMENSIONAL GAUSSIAN FILTERING CIRCUIT, STEREO DEPTH CALCULATION CIRCUIT, AND INFORMATION PROCESSING APPARATUS

Номер: US20220035737A1
Автор: Yasuda Kazunori
Принадлежит:

A storage apparatus of an associative array type that stores a large-sized value at a low cost is provided. The storage apparatus of the associative array type includes a first memory, a second memory that stores a value, and a third memory. The first memory stores a key and an address of the second memory. The address of the second memory is an address where the value corresponding to the key is stored. The third memory stores an address of the first memory. The address of the first memory is an address where the key corresponding to the value stored in the second memory is stored. The first memory further stores a flag that indicates whether or not the key has been registered. 1. A storage apparatus of an associative array type comprising:a first memory;a second memory that stores a value; anda third memory, whereinthe first memory stores a key and an address of the second memory, the address of the second memory being an address where the value corresponding to the key is stored, andthe third memory stores an address of the first memory, the address of the first memory being an address where the key corresponding to the value stored in the second memory is stored.2. The storage apparatus according to claim 1 , wherein the first memory further stores a flag that indicates whether or not the key has been registered.3. The storage apparatus according to claim 1 , wherein the address at which the key is stored in the first memory is calculated from the key with use of a hash function.4. The storage apparatus according to claim 3 , wherein the address at which the key is stored in the first memory is calculated using an open addressing method.5. The storage apparatus according to claim 1 , whereineach of the first memory and the third memory includes an SRAM, anda memory of the second memory includes a DRAM.6. A High Dimensional Gaussian Filtering (HDGF) circuit configured to store a calculation value by using the storage apparatus according to .7. A stereo depth ...

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15-01-2015 дата публикации

DIGITAL FILTER CIRCUIT, DIGITAL FILTER PROCESSING METHOD AND DIGITAL FILTER PROCESSING PROGRAM STORAGE MEDIUM

Номер: US20150019608A1
Принадлежит: NEC Corporation

Reduction of a circuit size and power consumption for performing digital filtering processing in a frequency domain is realized. The digital filter circuit includes: a complex conjugate generation unit for generating a second complex number signal including conjugate complex numbers of all complex numbers included in a first complex number signal of the frequency domain generated by converting a complex number signal of a time domain by Fourier transform; a filter coefficient generation unit for generating a first and a second frequency domain filter coefficient of a complex number from a first, a second and a third input filter coefficient of a complex number having been inputted; a first filtering unit for performing filtering processing to the first complex number signal by the first frequency domain filter coefficient, and outputting a third complex number signal; a second filtering unit for performing filtering processing to the second complex number signal by the second frequency domain filter coefficient, and outputting a fourth complex number signal; and a complex conjugate combining unit for combining the third complex number signal and the fourth complex number signal, and generating a fifth complex number signal. 1. A digital filter circuit , comprising:a complex conjugate generation unit that generates a second complex number signal including respective conjugate complex numbers of all complex numbers included in a first complex number signal of a frequency domain generated by converting a complex number signal of a time domain by Fourier transform;a filter coefficient generation unit that generates a first and a second frequency domain filter coefficient of a complex number from a first, a second and a third input filter coefficient of a complex number having been inputted;a first filtering unit that performs filtering processing to the first complex number signal by the first frequency domain filter coefficient, and outputting a third complex number ...

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21-01-2016 дата публикации

ARCHITECTURE TO REJECT NEAR END BLOCKERS AND TRANSMIT LEAKAGE

Номер: US20160020752A1
Принадлежит:

A method and apparatus for minimizing transmit signal interference is provided. The method includes the steps of: receiving a signal and amplifying the received signal. The received signal is then mixed with an intermediate frequency signal to obtain a baseband modulated signal. The baseband modulated signal is first filtered in an RC filter. The resulting signal is then divided by a preselected amount and the first divided portion is sent to a main path of a biquad filter, which produces a first stage biquad filtered signal. The second portion of the divided signal is sent to an auxiliary path of the biquad filter, and produces a second filtered signal. The first and second signals are then recombined and sent to the second stage of the biquad filter, where further filtering takes place.

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21-01-2016 дата публикации

Generation of High-Rate Sinusoidal Sequences

Номер: US20160020753A1
Принадлежит:

Provided are, among other things, systems, apparatuses methods and techniques for generating discrete-time sinusoidal sequences. One such apparatus includes a plurality of parallel processing branches, with each of the parallel processing branches operating at a subsampled rate and utilizing a recursive filter to generate sub-rate samples which represent a different subsampling phase of a complete signal that is output by the apparatus. 1. An apparatus for generating discrete-time samples of a sinusoidal waveform , comprising:an output line for providing output samples of a sinusoid that are discrete in time and in value;a plurality of processing branches coupled to the output line, each of said processing branches including a recursive digital filter;a first input line for setting a frequency of the sinusoid; anda second input line for setting an initial state of the recursive digital filter in at least one of said processing branches,wherein each of said processing branches operates at a subsampled rate, and generates an output sequence at said subsampled rate which represents a different subsampling phase of a complete, full-rate sinusoidal sequence in accordance with a value provided on said second input line, andwherein said recursive digital filter within each said processing branch operates independently of the recursive digital filter within the other processing branches and produces subsampled outputs via a linear combination of prior output samples generated within said processing branch.2. An apparatus according to claim 1 , further comprising a multiplexer with inputs that are coupled to outputs of said parallel processing branches and which combines multiple claim 1 , sub-rate inputs into a single claim 1 , full-rate output.3. An apparatus according to claim 1 , wherein the frequency of the sinusoid is established by a programmable coefficient within the recursive digital filter.4. An apparatus according to claim 1 , wherein the initial state of the ...

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17-04-2014 дата публикации

Digitally Controlled Delay Line for a Structured ASIC Having a Via Configurable Fabric for High-Speed Interface

Номер: US20140103985A1
Принадлежит: eASIC Corporation

A Digitally Controlled Delay Line (DCDL) for a Structured ASIC chip is used to delaying input or output signals into or out of core logic in a Structured ASIC. The DCDL has a multi-stage configuration that in a preferred embodiment comprises two fine delay stages for fine tuning the delay using sub-gate delay through an inverter whose delay can be adjusted with parallel CMOS transistors whose gates are biased with a voltage control signal that is thermometer coded. The fine-tune stages are followed by coarse delay stages that use gate-level delay. A DCDL controller outputs control signals that are Grey coded and converted to thermometer coded control signals by a Binary-to-Thermometer Decoder. The DCDL circuit block and accompanying Structured ASIC are manufactured on a 28 nm CMOS process lithographic node or smaller. A high speed routing fabric using a balanced binary tree is employed with the DCDL. 1. A Digitally Controlled Delay Line (DCDL) , comprising:a module for the coarse delay of a signal having an input and an output;a module for the fine delay of a signal, having an input and an output;wherein a signal is capable of being delayed by the fine delay module for a period of time less than the period of time the signal is capable of being delayed by the coarse delay module.2. The DCDL according to claim 1 , wherein:the fine delay module is in series with the coarse delay module, with the output of the fine delay module input into the input of the coarse delay module; and,the coarse delay module comprises a delay producing inverter.3. The DCDL according to claim 2 , further comprising:a circuit for producing a thermometer coded signal output.4. The DCDL according to claim 3 , wherein:the fine delay module comprises a sub-gate delay logic array comprising a delay-producing inverter, the inverter having a plurality of parallel pFET and nFET transistors.5. The DCDL according to claim 3 , wherein:the fine delay module comprises a sub-gate delay logic array ...

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03-02-2022 дата публикации

SIGNAL DETECTION METHOD FOR NON-COHERENT DETECTION IN A CHIRP SPREAD SPECTRUM COMMUNICATION SYSTEM

Номер: US20220038134A1
Автор: BARNAWI Ahmed
Принадлежит: KING ABDULAZIZ UNIVERSITY

A system and methods for transmission and non-coherent detection of data signals modulated by a plurality of overlapping chirps in a chirp spread spectrum communication system (CSS). Data signals input to an adaptive overlapping transmitter are modulated by a plurality of overlapping chirps and transmitted over a wireless communication system to a non-coherent receiver. The coherent receiver includes a chirp matched filter which matches the chirps to an internal chirp signal, a delay filter which delays each chirp, a multiplier which multiplies each delayed chirp by a next chirp, an integrator which sums the amplitudes of the chirps and decision circuitry which determines the polarity of each sum and outputs a stream of ones and zeroes representing the data signals. 116-. (canceled)17. A communication signal detection method for a chirp spread spectrum communication system (CSS) , comprising:{'sub': 'b,new', 'receiving an encoded stream of data signals modulated by a plurality of overlapping chirps by a non-coherent receiver at non-coherent FIR chirp matched filter, the encoded stream having a data rate, T, wherein the encoded stream of data signals is generated with a differential phase shift keying (DPSK) convertor;'}{'sub': 'b,old', 'generating an internal chirp signal by a non-coherent finite impulse response (FIR) chirp matched filter, the internal chirp signal having an FT product equal to a sweep frequency (F) multiplied by the inverse of the data rate of the chirp spread spectrum communication system, T;'}matching the encoded stream to the internal chirp signal and generating a stream of first chirp matched signals;delaying each first chirp matched signal by a FIR delay filter and generating a second chirp matched signal which is phase shifted from the first chirp matched signal;multiplying the second chirp matched signal by the first chirp matched signal and generating a stream of multiplied chirp matched signals each having a main lobe;integrating a ...

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18-01-2018 дата публикации

Filter generator, filter generation method, and filter generation program

Номер: US20180019720A1
Принадлежит: Clarion Co Ltd

A filter generator ( 100 ) generates a filter on the basis of band information (frequency) and gain characteristics (gain value) set by a user. The filter generator ( 100 ) obtains weighting factor information on the basis of the band information selected by the user and calculates a gain difference between a gain value used in a preceding filtering process and the new gain value selected by the user. The filter generator ( 100 ) then obtains a correction gain by multiplying the weighting factor information by the gain difference and generates a filter by multiplying a coefficient of the filter used in the preceding filtering process by the correction gain.

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18-01-2018 дата публикации

METHODS AND APPARATUS FOR EFFICIENT LINEAR COMBINER

Номер: US20180019732A1
Принадлежит:

In accordance with an example, an integrated circuit includes a linear combiner having an input for receiving a signal. The linear combiner also has a plurality of operator circuits for applying weighting factors to the signal, in which a first operator circuit in the plurality of operator circuits performs a first operation on the signal using a first sub-weight of one of the weighting factors to provide a first tile output and a second operator circuit in the plurality of operator circuits performs a second operation on the signal using a second sub-weight of the one of the weighting factors to provide a second tile output. The linear combiner also has an adder having a first input coupled to receive the first tile output and the second tile outputs and providing a combined output. 1. An integrated circuit including a linear combiner , comprising:an input operable to receiving a signal;a plurality of operator circuits operable to apply weighting factors to the signal, in which a first operator circuit in the plurality of operator circuits performs a first operation on the signal using a first sub-weight of one of the weighting factors to provide a first tile output and a second operator circuit in the plurality of operator circuits performs a second operation on the signal using a second sub-weight of the one of the weighting factors to provide a second tile output; andan adder having a first input coupled to receive the first tile output and the second tile output and providing a combined output.2. The integrated circuit of in which the first sub-weight and second sub-weight are computed from bits of the one of the weighting factors.3. The integrated circuit of in which the operator circuits are multipliers.4. The integrated circuit of in which the first tile output is shifted upwards by a number of bits corresponding to bits in the second sub-weight.5. The integrated circuit of in which the linear combiner is a filter.6. The integrated circuit of further ...

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17-01-2019 дата публикации

SIGNAL PROCESSOR, FILTER, CONTROL CIRCUIT FOR POWER CONVERTER CIRCUIT, INTERCONNECTION INVERTER SYSTEM AND PWM CONVERTER SYSTEM

Номер: US20190020261A1
Принадлежит:

A signal processor is configured to perform a process equivalent to performing a series of fixed-to-rotating coordinate conversion, a predetermined process and then rotating-to-fixed coordinate conversion, while maintaining linearity and time-invariance. The signal processor performs a process given by the following matrix G: 130-. (canceled)3223ss. The filter according to claim 31 , wherein G()=G()=0.3323ss. The filter according to claim 31 , wherein G()≠0 and G()≠0.34. The filter according to claim 31 , wherein the transfer function F(s) is equal to one of K/s (Krepresents an integral gain) claim 31 , K+K/s (Krepresents a proportional gain claim 31 , and Krepresents an integral gain) or K+K/s+K·s (Krepresents a proportional gain claim 31 , Krepresents an integral gain claim 31 , and Krepresents a differential gain).35. The filter according to claim 31 , wherein the transfer function F(s) is equal to 1/(T·s+1) claim 31 , where T represents a time constant.36. The filter according to claim 31 , wherein the transfer function F(s) is equal to T·s/(T·s+1) claim 31 , where T represents a time constant.37. The filter according to claim 31 , wherein a positive phase component of a fundamental wave of the first input signal Sis different in phase by 90 degrees from a positive phase component of a fundamental wave of the second input signal S.38. The filter according to claim 31 , wherein the first input signal Sis a non-zero signal claim 31 , and the second input signal Sis zero.39. A filtering system comprising:{'claim-ref': {'@idref': 'CLM-00031', 'claim 31'}, 'a filter according to ; and'}{'sub': 1', '2, 'a signal converter configured to convert three-phase alternate signals to the first input signal Sand the second input signal S.'}40. A filtering system comprising:{'claim-ref': {'@idref': 'CLM-00031', 'claim 31'}, 'a filter according to ; and'}{'sub': 1', '2, 'a signal converter configured to convert a single-phase alternate signal to the first input signal Sand the ...

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17-01-2019 дата публикации

High Order Filter Circuit

Номер: US20190020329A1
Автор: CHEN SZ-AN, Lee Shuenn-Yuh
Принадлежит:

A high order filter circuit is integrated by a plurality of the low order filter circuits. Before correcting the high order filter circuit, switch units may restore the high order filter circuit to the low order filter circuits for correction, and then combine the corrected low order filter circuits to form the original high order filter circuit. 1. A high order filter circuit including:a plurality of second order filter units for filtering inputted signals;a plurality of switch units for connecting the plurality of second order filter units in a cascade to form a high order filter unit when the switch units are closed, and for restoring the high order filter unit to the plurality of second order filter units when the switch units are opened;an analog-to-digital converter (ADC) having a first working status and a second working status, for detecting peaks of predetermined band signals outputted from the second order filter units and digitalizing the peaks when the ADC is in the first working status, and for detecting and converting the predetermined band signals from the second order filter units to digital signals and outputting the digital signals when the ADC is in the second working status; anda digital correction unit for comparing the digitalized peaks with a default value and generating comparison results, and according to the comparison results, the digital correction unit generating frequency control signals and working status control signals and sending them as feedbacks respectively to the second order filter units for adjusting their working frequencies and to the ADC for switching its working status.2. The high order filter circuit according to claim 1 , wherein the second order filter unit is a second order notch filter unit or a second order band-pass filter unit claim 1 , and the working frequency is a notch center frequency of the notch filter unit or a band-pass center frequency of the band-pass filter unit.3. The high order filter circuit ...

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17-01-2019 дата публикации

RECEIVING DEVICE

Номер: US20190020508A1
Автор: NODA Yasunori
Принадлежит: Mitsubishi Electric Corporation

A receiving device includes: a resampler to convert a sampling rate of a reception signal, and output a first signal that is a signal having been subjected to sampling rate conversion; an equalizer to perform an adaptive equalization process using the first signal as an input, and output a second signal that is a signal having been subjected to the adaptive equalization process and having a sampling rate that is an integer fraction of an input signal; a correlation calculator to calculate a correlation function between the first signal and the second signal; and a rate controller to control a rate conversion ratio for sampling rate conversion in the resampler on a basis of the correlation function. 1. A receiving device comprising:a resampler to convert a sampling rate of a reception signal, and output a first signal that is a signal having been subjected to sampling rate conversion;an equalizer to perform an adaptive equalization process using the first signal as an input, and output a second signal that is a signal having been subjected to the adaptive equalization process and having a sampling rate that is an integer fraction of an input signal;a correlation calculator to calculate a correlation function between the first signal and the second signal; anda rate controller to control a rate conversion ratio for sampling rate conversion in the resampler on a basis of the correlation function.2. The receiving device according to claim 1 , whereinthe rate controller controls the rate conversion ratio on a basis of a delay time corresponding to a maximum value of the correlation function.3. The receiving device according to claim 1 , further comprisingan upsampler to upsample the second signal, whereinthe correlation calculator calculates a correlation function between the first signal and the second signal having been subjected to upsampling by the upsampler.4. The receiving device according to claim 3 , further comprisinga symbol determiner to perform symbol ...

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16-01-2020 дата публикации

METHOD AND APPARATUS FOR PROCESSING MULTIMEDIA SIGNALS

Номер: US20200021936A1
Автор: LEE Taegyu, OH Hyunoh

The present invention relates to a method and an apparatus for processing a signal, which are used for effectively reproducing a multimedia signal, and more particularly, to a method and an apparatus for processing a signal, which are used for implementing filtering for multimedia signal having a plurality of subbands with a low calculation amount. 1. (canceled)2. A method for processing a multimedia signal , the method comprising:receiving a multimedia signal;receiving a set of filter coefficients for each subband, wherein the set of filter coefficients is truncated frequency-dependently from a set of proto-type subband filter coefficients based on a filter order for a corresponding subband, and wherein the filter order determines a length of the set of filter coefficients for each subband and is determined to be variable in a frequency domain; andfiltering each subband signal of the multimedia signal by using the set of filter coefficients corresponding thereto.3. The method of claim 2 , wherein the filter order is determined based at least part on energy decay time information of the corresponding subband.4. The method of claim 3 , wherein the energy decay time information is obtained from one or more sets of proto-type subband filter coefficients for the corresponding subband.5. The method of claim 3 , wherein the multimedia signal includes an audio signal claim 3 , andwherein the set of proto-type subband filter coefficients is a set of binaural room impulse response (BRIR) filter coefficients in the frequency domain.6. The method of claim 5 , wherein the energy decay time information includes reverberation time information.7. The method of claim 2 , wherein the filter order has a single value for each subband.8. An apparatus for processing a multimedia signal claim 2 , the apparatus comprising: receive a multimedia signal;', 'receive a set of filter coefficients for each subband, wherein the set of filter coefficients is truncated frequency-dependently from a ...

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17-04-2014 дата публикации

Vector processor having instruction set with vector convolution function for fir filtering

Номер: US20140108477A1
Принадлежит: LSI Corp

A vector processor is provided having an instruction set with a vector convolution function. The disclosed vector processor performs a convolution function between an input signal and a filter impulse response by obtaining a vector comprised of at least N 1+ N 2 - 1 input samples; obtaining N 2 time shifted versions of the vector (including a zero shifted version), wherein each time shifted version comprises Ni samples; and performing a weighted sum of the time shifted versions of the vector by a vector of Ni coefficients; and producing an output vector comprising one output value for each of the weighted sums. The vector processor performs the method, for example, in response to one or more vector convolution software instructions having a vector input. The vector can comprise a plurality of real or complex input samples and the filter impulse response can be expressed using a plurality of coefficients that are real or complex.

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25-01-2018 дата публикации

METHOD FOR THE NON-LINEAR ESTIMATION OF A MIXTURE OF SIGNALS

Номер: US20180026607A1
Принадлежит:

This method for the non-linear estimation of no more than two mixed signals from separate sources, the time/frequency representation of which shows an unknown non-zero proportion of zero components, using an array made up of P>2 antennas, when the directional vectors U and V of the sources emitting these signals are additionally known or estimated, includes the following steps: 1. A method for the non-linear estimation of no more than two mixed signals from separate sources , the time/frequency representation of which shows an unknown non-zero proportion of zero components , using an array made up of P>2 antennas , when the directional vectors U and V of the sources emitting these signals are additionally known or estimated , comprising the following steps:a) calculating the successive discrete Fourier transforms of the signal received by the antennas and sampled to obtain a time-frequency P-vector grid of the signal; each element of the grid being referred to as a box and containing a complex vector X forming a measurement; andb) for each box, calculating the conditional expectation estimator of the signal, or of the signals, from the measurement X and an a priori probability density (p(s)) for the signals that is a Gaussian mixture.2. The method according to claim 1 , characterized in that it includes a step for estimating parameters (q claim 1 ,σ claim 1 ,σ) necessary to establish the conditional expectation using the method of moments operating on the boxes of a divided window in the time/frequency grid.3. The method according to claim 1 , characterized in that the calculation of the conditional expectation estimator is approximated by a Conditional Expectation with 4 Linear Filters obtained by a four-hypothesis decision processing pertaining to four Hermitian forms of the measurement X claim 1 , followed by linear filtering commanded by the result of the decision.4. The method according to claim 3 , characterized in that the calculation of the Conditional ...

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28-01-2021 дата публикации

Adaptive filter bank for modeling a thermal system

Номер: US20210025766A1
Автор: Larry A. Turner
Принадлежит: Schneider Electric USA Inc

Embodiments of the disclosure implement an application of an adaptive filter bank that is used to characterize the heat transfer of a volume in a thermal system, to estimate temperature and power consumption, and to improve performance characteristics in applications including optimal temperature control and diagnostics. In some embodiments, the adaptive filter bank is an iterative solution, comprised of a collection of adaptive filters defined to consume incident signals, produce an aggregate reference signal, estimate an error relative to an observed primary signal, and modify thermal coefficients to converge on a solution. For example, the incident signals are comprised of properties related to active, passive, solar irradiance, and unobserved heat transfer. A reference signal is an estimate of a primary signal, related to the rate of heat transfer or temperature change. Thereupon, the thermal coefficients are modified in an adaptive process to include gradient descent, which minimizes estimation error.

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28-01-2021 дата публикации

LOW PASS FILTER AND FILTER DIAGNOSTICS

Номер: US20210025943A1
Принадлежит:

As one example, a filter apparatus includes an input to receive an electrical input signal. The filter apparatus includes a forward path connected between the input and an output of the filter apparatus. A feedback path is connected to provide feedback to the forward path based on an output signal at the output of the filter apparatus. A filter bypass is configured to provide the input signal directly to the output and to the feedback path for an activation phase of the filter apparatus. Diagnostics may also be performed. 1. A filter apparatus comprising:an input to receive an electrical input signal;a forward path connected between the input and an output of the filter apparatus;a feedback path connected to provide feedback to the forward path based on an output signal at the output; anda filter bypass configured to send the input signal directly to the output and to the feedback path for an activation phase of the filter apparatus.2. The filter apparatus of claim 1 , wherein the forward path comprises:a gain stage to apply a gain factor to the input signal to provide an intermediate signal; anda combiner configured to add the feedback to the intermediate signal to provide the output signal.3. The filter apparatus of claim 2 , wherein the feedback path comprises:a delay element to impose a predetermined delay to the output signal; anda gain stage to apply another gain factor to the delayed output signal and provide the feedback to the combiner.4. The filter apparatus of claim 2 , wherein the filter bypass comprises a multiplexer having inputs coupled to receive the input signal and an output of the combiner claim 2 , the multiplexer having an output corresponding to the output of the filter apparatus claim 2 , the multiplexer sending one of the input signal and the output of the combiner to the output of the filter apparatus based on a control input.5. The filter apparatus of claim 4 , wherein the control input operates the multiplexer to send the input signal to ...

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24-01-2019 дата публикации

COMPACT MODEL NONLINEAR COMPENSATION OF BANDLIMITED RECEIVER SYSTEMS

Номер: US20190028131A1
Автор: Wang Xiao-Yu
Принадлежит: Massachusetts Institute of Technology

A nonlinear compensator is provided to include a decomposition circuit and a plurality of filter elements. The decomposition circuit has a nonlinear frequency response characteristic and the decomposition circuit is configured to receive an input signal and decompose the input signal into decomposed signals corresponding to positive and negative frequency signal components of the input signal. Each of the plurality of filter elements is configured to receive at least portions of the decomposed signals and apply filter element characteristics to the decomposed signals with the filter element characteristics that are matched to the nonlinear frequency response of the decomposition circuit. 1. A nonlinear compensator comprisinga decomposition circuit having a nonlinear frequency response characteristic, the decomposition circuit being configured to receive an input signal and decompose the input signal provided thereto into decomposed signals corresponding to positive and negative frequency signal components of the input signal; anda plurality of filter elements each of which is configured to receive at least portions of the decomposed signals and apply filter element characteristics to the decomposed signals with the filter element characteristics being matched to the nonlinear frequency response of the decomposition circuit.2. The nonlinear compensator of claim 1 , wherein the plurality of filter elements is configured to reduce the number of tones to characterize the nonlinear system.3. The nonlinear compensator of claim 1 , wherein the plurality of filters comprises at least one of:at least one nonlinear operation element; orat least one linear operation filter.4. The nonlinear compensator of claim 3 , wherein the at least one nonlinear operation element comprises at least one static nonlinear mathematical operation element.5. The nonlinear compensator of claim 3 , wherein the at least one linear operation filter comprises at least one of:at least one static linear ...

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23-01-2020 дата публикации

FIXED LATENCY CONFIGURABLE TAP DIGITAL FILTER

Номер: US20200028494A1
Автор: Achanta Srinivas

A fixed latency configurable tap or fixed-tap digital filter may filter a signal in a fixed amount of time, regardless of the number of taps. The filter may include one or more of a clock, a plurality of registers in a shift register, an adder, an accumulator, and/or a scaler. In at least one embodiment, a running average may be maintained as samples are received such that the latency remains fixed with a constant number of clock cycles. 1. A fixed latency digital filter with a selectable tap length , comprising: 'wherein, for each sampling interval of the digital filter, the first register receives a new sampled value and shifts stored sampled values within the shift register, such that after a plurality of sampling intervals, each sampled value is shifted from the first register through the plurality of intermediary registers to the last register;', 'a shift register with a number of registers equal to a selected tap length, including a first register, a plurality of intermediary registers, and a last register,'}an adder to generate a difference between a sampled value stored in the last shift register and a sampled value stored in the first register during each sampling interval;an accumulator that, for each sampling period, generates an accumulation value by adding a difference generated by the adder during a previous sampling period to a sum of prior differences generated by the adder; anda scaler to generate a filtered value output by multiplying the accumulation value by 1/C, where C is a constant.2. The filter of claim 1 , wherein the constant claim 1 , C claim 1 , is equal to the tap length claim 1 , such that the digital filter is a moving average digital filter.3. The filter of claim 1 , wherein the sampled values comprise sampled values from an electrical power line.4. The filter of claim 1 , further comprising an input to receive a timing signal from a clock that defines the sampling interval of the digital filter.5. The filter of claim 1 , further ...

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28-01-2021 дата публикации

ELECTRICAL CIRCUIT FOR FILTERING A LOCAL OSCILLATOR SIGNAL AND HARMONIC REJECTION MIXER

Номер: US20210028771A1
Принадлежит:

An electrical circuit can have a local oscillator, a first mixer, a second mixer, and a delay element. The first mixer mixes an input signal with a local oscillator signal. The second mixer mixes the input signal with a delayed local oscillator signal, delayed by the delay element. The output signals from the first mixers are combined to form an output signal of the electrical circuit. 1. An electrical circuit , the electrical circuit comprising:an input terminal;an output terminal;a local oscillator;a first mixer;a second mixer; anda delay element, wherein:the first mixer is configured to receive an input signal from the input terminal and to mix the input signal with a local oscillator signal from the local oscillator,the second mixer is configured to receive the input signal from the input terminal and to mix the input signal with a delayed local oscillator signal,the delay element configured to receive the local oscillator signal, and to delay the received local oscillator signal to provide the delayed local oscillator signal to the second mixer, andthe electrical circuit is configured to combine an output signal from the first mixer with an output signal from the second mixer to form an output signal at the output terminal.2. The electrical circuit according to claim 1 , the electrical circuit further comprising at least one additional mixer claim 1 ,wherein the at least one additional mixer is configured to receive the input signal from the input terminal and to mix the input signal with a further delayed local oscillator signal,wherein the further delayed local oscillator signal is a local oscillator signal with a delay longer than the delayed local oscillator signal, andwherein the electrical circuit is configured to combine the output signal from the first mixer with the output signal from the second mixer and the output signal from the at least one additional mixer to form the output signal at the output terminal.3. The electrical circuit according to ...

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02-02-2017 дата публикации

STEP ATTENUATORS

Номер: US20170033772A1
Автор: Domino William J.
Принадлежит:

In some embodiments, an attenuator can include a first group of attenuation steps with each attenuation step being configured to switchably provide a first attenuation value, and a second group of attenuation steps with each attenuation step being configured to switchably provide a second attenuation value less than the first attenuation value. The attenuator can be capable of providing a total attenuation value from approximately zero to a sum of the attenuation steps of the first group and the second group in increments of the second attenuation value. With such a configuration, a glitch can have a maximum magnitude that is a difference between the first attenuation value and the second attenuation value during a change in the total attenuation value. 1. An attenuator comprising:a first group of attenuation steps each configured to switchably provide a first attenuation value; anda second group of attenuation steps each configured to switchably provide a second attenuation value less than the first attenuation value, the attenuator capable of providing a total attenuation value from approximately zero to a sum of the attenuation steps of the first group and the second group in increments of the second attenuation value, such that during a change in the total attenuation value, a glitch has a maximum magnitude that is a difference between the first attenuation value and the second attenuation value.2. The attenuator of wherein the attenuation steps of the first group and the second group are arranged in series between an input node and an output node of the attenuator.3. The attenuator of wherein the first group of attenuation steps are arranged in series with each other claim 2 , and the second group of attenuation steps are arranged in series with each other.4. The attenuator of wherein the first group of attenuation steps includes N switchable attenuation steps capable of providing attenuation from approximately zero to N times the first attenuation value claim ...

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17-02-2022 дата публикации

COMPUTATIONAL ARRAY MICROPROCESSOR SYSTEM USING NON-CONSECUTIVE DATA FORMATTING

Номер: US20220050806A1
Принадлежит:

A microprocessor system comprises a computational array and a hardware data formatter. The computational array includes a plurality of computation units that each operates on a corresponding value addressed from memory. The values operated by the computation units are synchronously provided together to the computational array as a group of values to be processed in parallel. The hardware data formatter is configured to gather the group of values, wherein the group of values includes a first subset of values located consecutively in memory and a second subset of values located consecutively in memory. The first subset of values is not required to be located consecutively in the memory from the second subset of values. 121.-. (canceled)22. A microprocessor system , comprising:a computational array that includes a plurality of computation units, wherein each of the plurality of computation units operates on a corresponding value addressed from memory and the values operated by the plurality of computation units are provided to the computational array as a group of values to be processed in parallel, the group of values being utilized as a first input to the computational array; anda hardware data formatter configured to gather the group of values based on a data formatting operation, the data formatting operation identifying at least a stride,wherein the group of values are provided, by the hardware data formatter, to the computational array, and wherein the computational array disables particular computational units based on the stride.23. The microprocessor system of claim 22 , wherein the values operated by the computational units are synchronously provided to the computational array.24. The microprocessor system of claim 22 , wherein the hardware data formatter comprises a plurality of read buffers configured to store respective subsets of the values.25. The microprocessor system of claim 24 , wherein each subset corresponds to values located consecutively in the ...

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01-02-2018 дата публикации

DETERMINATION DEVICE AND METHOD FOR DETERMINING AN ACTIVE CHANNEL OF A PLURALITY OF CHANNELS

Номер: US20180035464A1
Принадлежит:

A determination device serves for determining an active channel of a plurality of channels in a wireless signal, wherein adjacent channels overlap each other by a predetermined frequency threshold. The determination device comprises a receiver for receiving the wireless signal and providing a respective digitized signal, a first filter for applying a mean filter to the digitized signal, and a detector for detecting the active channel in the first filtered signal. 1. A determination device for determining an active channel of a plurality of channels in a wireless signal , wherein adjacent channels overlap each other by a predetermined frequency threshold , the determination device comprising:a receiver for receiving the wireless signal and providing a respective digitized signal,a first filter for applying a mean filter to the digitized signal and providing a first filtered signal, anda detector for detecting the active channel in the first filtered signal.2. The determination device according to claim 1 , the first filter comprising a summing unit for sample-wise summing frames of the digitized signal of a predetermined frame length.3. The determination device according to claim 2 , comprising a Fourier transformer claim 2 , and the predetermined frame length being equal to the window size in samples of the Fourier transformer.4. The determination device according to claim 2 , the first filter comprising a divider for dividing the value of the individual samples of the sample-wise summed frames by the number of summed frames.5. The determination device according to claim 3 , the transformer transforming the first filtered signal into the frequency domain and providing the transformed signal to the detector claim 3 , or the transformer transforming the digitized signal into the frequency domain and providing the transformed digitized signal to the first filter.6. The determination device according to claim 1 , the receiver comprising a signal input coupled to an ...

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05-02-2015 дата публикации

Multi-Channel Scalable EEG Acquisition System on a Chip with Integrated Patient Specific Seizure Classification and Recording Processor

Номер: US20150038870A1
Принадлежит:

An integrated circuit chip and method for EEG monitoring. In one embodiment, the integrated circuit chip includes an Analog Front End cell in communication with an electrode and a Classification Processor wherein a signal received from the electrode is processed by the Classification Engine cell and designated as seizure or non-seizure. In another embodiment, the Analog Front End cell includes an amplifier cell in communication with an electrode; and an ASPU cell in communication with the amplifier cell. In yet another embodiment, the Classification Processor includes a DBE Channel Controller cell; a Feature Extraction Engine Processor cell, and a Classification Engine cell in communication with the Feature Extraction Engine Processor cells and the DBE Channel Controller cell. 1. An integrated circuit chip for EEG monitoring , comprising: an amplifier cell in communication with an EEG electrode;', 'an ASPU cell in communication with the amplifier cell; and, 'an Analog Front End cell, the Analog Front End cell comprising a DBE Channel Controller cell;', 'a Feature Extraction Engine Processor cell, the Feature Extraction Engine Processor cell in communication with the DBE Channel Controller cell and the Analog Front End cell; and', 'a Classification Engine cell in communication with the Feature Extraction Engine Processor cell and the DBE Channel Controller cell,, 'a Classification Processor comprisingwherein a signal received from the electrode is processed by the Classification Engine cell and designated as seizure or non-seizure.2. The integrated circuit chip of wherein the amplifier cell in communication with the electrode is a CS-CCIA cell.3. The integrated circuit chip of wherein the amplifier cell in communication with the electrode is an autozeroing amplifier circuit cell.4. The integrated circuit chip of wherein the Feature Extraction Engine Processor cell comprises:a plurality of bandpass filter cells, each bandpass filter cell in communication with the ASPU ...

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08-02-2018 дата публикации

FILTER ASSEMBLY FOR MEDICAL IMAGE SIGNAL AND DYNAMIC DECIMATION METHOD USING SAME

Номер: US20180035981A1
Принадлежит: SOGANG UNIVERSITY RESEARCH FOUNDATION

The present invention relates to a filter assembly for a medical image signal and a dynamic decimation method using the same. The filter assembly includes a decimation filter that includes an integer number of multiplier accumulators (MACs), changes a cut-off frequency depending on a bandwidth of the medical image signal received through a dynamic impulse response update, and performs a decimation with respect to the received signal according to a decimation ratio, wherein the decimation filter determines a filter coefficient corresponding to an integer interval so as to up-sample the received medical image signal and supplies the filter coefficient to the MACs. 1. A filter assembly for a medical image signal , comprising:an expander configured to receive the medical image signal and up-sample the medical image signal; anda decimation filter including an integer number of multiplier accumulators (MACs), configured to change a cutoff frequency according to bandwidth of the received medical image signal by dynamically updating an impulse response and perform decimation on the up-sampled signal according to a decimation ratio.2. The filter assembly according to claim 1 , wherein the decimation filter calculates a partial sum claim 1 , which is the sum of coefficients of a k-th (wherein k is a positive integer) location of a polyphase filter claim 1 , through each MAC.3. The filter assembly according to claim 1 , wherein each MAC includes:a shift register configured to receive and store coefficients of a polyphase filter;a multiplier configured to multiply the coefficients stored in the shift register by the up-sampled signal;a summer configured to cumulatively sum the multiplied results; anda decimator configured to decimate the summed result.4. The filter assembly according to claim 3 , wherein a frequency band of the received signal is determined by attenuation caused by depth of an object of the medical image signal and filter coefficients for calculating different ...

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30-01-2020 дата публикации

GLOBAL OPTIMAL PARTICLE FILTERING METHOD AND GLOBAL OPTIMAL PARTICLE FILTER

Номер: US20200034716A1
Автор: Li Lin, Li Yun
Принадлежит:

The invention relates to a global optimal particle filtering method and a global optimal particle filter. The problem of particle filter processing nonlinear and non-Gaussian signals is effectively solved. The main technical means is to use the Lamarck genetic natural law to construct a global optimal particle filter comprising: generating an initial particle set; using Unscented Kalman Filter to perform importance sampling on the initial particle set to obtain sampled particles; performing floating-point number encoding for each of the sampled particles to obtain an encoded particle set; setting an initial population; using the initial population as an original trial population to sequentially perform a Lamarck overwriting operation, a real number decoding operation, and an elite retention operation; using the real-number optimal candidate particle as a prediction sample for a next moment, and obtaining a state estimation value of a system. The invention is applicable to machine learning. 1. A global optimal particle filtering method , the method comprises steps of:step 1: generating an initial particle set;step 2: using an Unscented Kalman Filter to perform an importance sampling on the initial particle set to obtain sampled particles;step 3: performing a floating-point number encoding for each of the sampled particles to obtain an encoded particle set;step 4: setting an initial population according to the encoded particle set;step 5: using the initial population as an original trial population to sequentially perform a Lamarck overwriting operation, a real number decoding operation, and an elite retention operation; wherein the Lamarck overwriting operation refers to, according to a ratio between fitnesses of two parent candidate particles, passing a code of the parent with a higher fitness directly to an offspring of the parent with a lower fitness, replacing corresponding bits of its floating-point number, and retaining a parent particle with the higher fitness ...

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11-02-2016 дата публикации

CIRCUIT FOR DETECTING PHASE SHIFT APPLIED TO AN RF SIGNAL

Номер: US20160043703A1
Автор: TOURRET Jean-Robert
Принадлежит:

An RF circuit and method for detecting the amount of phase shift applied to an RF signal. An RF heating apparatus including the RF circuit. The RF circuit includes a phase shifter operable to apply a phase shift to a reference signal to produce a phase shifted reference signal. The RF circuit also includes a phase detector operable to detect a phase difference between the phase shifted RF signal and the phase shifted reference signal. The phase detector has a reduced input range at a frequency of the phase shifted RF signal. The RF circuit further includes a controller operable to control the phase shifter to set the phase of the phase shifted reference signal so that the phase difference between the phase shifted RF signal and the phase shifted reference signal falls within the reduced input range of the phase detector. 1. A circuit for detecting the amount of phase shift applied to an RF signal to produce a phase shifted RF signal in an RF signal path , the circuit comprising:a phase shifter operable to apply a phase shift to a reference signal to produce a phase shifted reference signal;a phase detector operable to detect a phase difference between the phase shifted RF signal and the phase shifted reference signal, wherein the phase detector has a reduced input range at a frequency of the phase shifted RF signal compared to the input range of the phase detector at a frequency lower than the frequency of the phase shifted RF signal, anda controller operable to control the phase shifter to set the phase of the phase shifted reference signal so that the phase difference between the phase shifted RF signal and the phase shifted reference signal falls within the reduced input range of the phase detector.2. The circuit of claim 1 , wherein the controller is operable to:control a phase shifter of the RF signal path for applying an intended phase shift applied to the RF signal to produce the phase shifted RF signal.3. The circuit of claim 2 , wherein the controller is ...

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09-02-2017 дата публикации

Delay Line

Номер: US20170040976A1
Автор: Julian Jenkins
Принадлежит: Perceptia Devices Inc

A delay line is constructed by combining a phase generator and a fabric. The phase generator splits a digital input signal in multiple incrementally delayed versions, which are input to the fabric. The fabric has an array of node filters. Inputs of filters in the first array column are inputs of the fabric. A node filter has a delay element and a cross-coupling element, whose output signals are added or subtracted to form a filter output signal. A node filter in a row is concatenated to the previous filter in the row through its delay element. Inputs of cross-coupling elements are connected to other array rows. Outputs of node filters form the outputs of the fabric. Delay times of delay elements and cross-coupling elements are nominally equal. Drive strengths of cross-coupling elements may be lower than drive strengths of delay elements.

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09-02-2017 дата публикации

Digital Filter With Confidence Input

Номер: US20170040977A1
Автор: Heim Axel, HOCH Martin
Принадлежит: MICROCHIP TECHNOLOGY GERMANY GMBH

A digital filter has an assigned filter function with assigned filter coefficients, an input receiving input samples, another input receiving confidence values, and an output. Each input sample value is associated to an input confidence value, wherein the filter output depends on the input samples, the input confidence values as well as the filter coefficients. The filter contains multiple accumulators, wherein an output sample is produced after a predetermined number of sample values wherein associated confidence values have been input to the filter. 1. A digital filter comprising an assigned filter function with assigned filter coefficients , an input receiving input samples , another input receiving confidence values , and an output ,wherein each input sample value is associated to an input confidence value and wherein each input sample is weighted with its associated confidence value;the filter output depends on both the input samples and the input confidence values, andwherein the filter comprises accumulators configured to accumulate a predefined number the confidence weighted input samples, the associated confidence values, the confidence values weighted with assigned filter coefficients, and the confidence weighted input samples further weighted with the assigned filter coefficients.2. The filter according to claim 1 , comprising:a first branch having a first accumulator receiving the input confidence values weighted with coefficients from a coefficient set and generating a first accumulated value;a second branch having a second accumulator receiving the input confidence values and generating a second accumulated value;a third branch having a third accumulator receiving input sample values weighted with coefficients from the coefficient set and the input confidence values and generating a third accumulated value;a fourth branch having a fourth accumulator receiving the confidence weighted input values and generating a fourth accumulated value.3. The filter ...

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08-02-2018 дата публикации

RATE CONVERTOR

Номер: US20180041196A1
Автор: Zhao Xudong
Принадлежит:

Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power. 1. A rate converter implemented in an audio processing circuit , the rate converter comprising:an input for receiving audio data sampled at an input sample rate;a sample index accumulator for determining a sample index for each output audio sample at an output sample rate different from the input sample rate;an error accumulator for determining and outputting an index error;a phase lock tracking loop for estimating a ratio between the input sample rate and the output sample rate;a gain value controller configured to adjust gain values during conversion between the first sample rate and the second sample rate; anda filter selector structured to select a filter from a plurality of filters for application to the audio data based on output of the gain value controller.2. The rate converter of claim 1 , in which each of the plurality of filters is configured to provide a different impulse response to the audio data during rate conversion.3. The rate converter of claim 2 , in which the plurality of filters are infinite impulse response (IIR) filters.4. The rate converter of claim 1 , in which the filter selector selects a new filter when an absolute value of the index error and a change of slope of the index error are both under or both over a threshold.5. The rate converter of claim 1 , in which ...

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07-02-2019 дата публикации

IN-VEHICLE DEVICE AND ESTIMATION METHOD

Номер: US20190041863A1
Автор: OKADA Kazuhiro
Принадлежит: Clarion Co., Ltd.

An object is to enable a state of a vehicle to be precisely estimated by a Kalman filter. A navigation system includes an observation unit that observes an observable concerning a variation of the vehicle, based on an output from a sensor, and an estimation unit that estimates a state quantity indicating a state of the vehicle by a Kalman filter, and the estimation unit calculates a prediction value of the state quantity of the vehicle, calculates an error covariance matrix of the prediction value, by the Kalman filter to which an error of the observable is inputted as an error of the state quantity which is in a relation of calculus with the observable, and calculates an estimation value of the state quantity of the vehicle and an error covariance matrix of the estimation value by the Kalman filter, based on the prediction value and the error covariance matrix of the prediction value which are calculated. 1. An in-vehicle device that is loaded on a vehicle , comprising:an observation unit that observes an observable concerning a variation of the vehicle, based on an output from a sensor; andan estimation unit that estimates a state quantity indicating a state of the vehicle by a Kalman filter,wherein the estimation unitcalculates a prediction value of the state quantity of the vehicle,calculates an error of the prediction value, by the Kalman filter to which an error of the observable is inputted as an error of the state quantity which is in a relation of calculus with the observable, andcalculates an estimation value of the state quantity of the vehicle and an error of the estimation value by the Kalman filter, based on the prediction value and the error of the prediction value which are calculated.2. The in-vehicle device according to claim 1 ,wherein the estimation unitcalculates the error of the prediction value, by the Kalman filter to which covariance of an error of the estimation value of the state quantity which is calculated at a previous time, and the ...

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24-02-2022 дата публикации

Method and apparatus for binaural rendering audio signal using variable order filtering in frequency domain

Номер: US20220059105A1

The present invention relates to a method and an apparatus for binaural rendering an audio signal using variable order filtering in frequency domain. To this end, provided are a method for processing an audio signal including: receiving an input audio signal; receiving a set of truncated subband filter coefficients for filtering each subband signal of the input audio signal, the set of truncated subband filter coefficients being constituted by one or more FFT filter coefficients generated by performing FFT by a predetermined block size; generating at least one subframe for each subband; generating at least one filtered subframe for each subband; performing inverse FFT on the filtered subframe for each subband; and generating a filtered subband signal by overlap-adding the transformed subframe for each subband and an apparatus for processing an audio signal using the same.

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24-02-2022 дата публикации

Digital Filterbank for Spectral Envelope Adjustment

Номер: US20220059111A1
Автор: EKSTRAND Per
Принадлежит: DOLBY INTERNATIONAL AB

An apparatus and method are disclosed for processing an audio signal. The apparatus includes an input interface, a digital filterbank having an analysis part and a synthesis part, a first phase shifter, a spectral envelope adjuster, a second phase shifter, and an output interface. The first phase shifter and the second phase shifter reduce a complexity of the digital filterbank, which includes both analysis and synthesis filters that are complex-exponential modulated versions of a prototype filter. 2. The signal processing device of wherein the prototype filter p(n) is a symmetric low pass prototype filter or an asymmetric low pass prototype filter.3. The signal processing device of wherein the analysis filter bank is a pseudo QMF bank.4. The signal processing device of wherein an order of the prototype filter p(n) equals the system delay D.5. The signal processing device of wherein the number of channels in the analysis filter bank is 32 and the number of channels in the synthesis filter bank is 64.7. A non-transitory computer readable medium containing instructions that when executed by a processor perform the method of . This application is a continuation of U.S. patent application Ser. No. 16/666,237 filed Oct. 28, 2019, which is a continuation of U.S. patent application Ser. No. 15/876,613 filed Jan. 22, 2018, now U.S. Pat. No. 10,460,742 issued Oct. 29, 2019, which is a continuation of U.S. patent application Ser. No. 15/441,652 filed Feb. 24, 2017, now U.S. Pat. No. 9,918,164 issued Mar. 13, 2018, which is a divisional application of U.S. patent application Ser. No. 14/810,174 filed Jul. 27, 2015, now U.S. Pat. No. 9,779,748 issued Oct. 3, 2017, which is a continuation of U.S. patent application Ser. No. 14/306,495 filed Jun. 17, 2014, now U.S. Pat. No. 9,449,608 issued Sep. 20, 2016, which is a continuation of U.S. patent application Ser. No. 13/201,572 filed Aug. 15, 2011, now U.S. Pat. No. 8,880,572 issued Nov. 4, 2014, which is a 371 National Phase ...

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01-05-2014 дата публикации

Arithmetic logic unit

Номер: US20140122551A1
Принадлежит: Mobileye Technologies Ltd

An arithmetic logic unit (ALU) including a first routing grid connected to multiple data lanes to drive first data to the data lanes. A second routing grid is connected to the data lanes to drive second data to the data lanes. Each of the data lanes include multiple, e.g. N, functional units with first inputs from the first routing grid and second inputs from the second routing grid. The functional units compute pairwise a function of the respective first data on the respective first inputs and the respective second data on the respective second inputs. Each of the data lanes include a reduction unit with inputs adapted to receive K′ bits per word from the functional units. The reduction unit is configured to perform a reduction operation configured to output an output result having a reduced number J′ bits per word, wherein J′ is less than N multiplied by K′.

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18-02-2021 дата публикации

SYSTEMS, APPARATUSES AND METHODS FOR ADAPTIVE NOISE REDUCTION

Номер: US20210049994A1
Принадлежит:

An apparatus includes a sensor module configured for receiving sensed information indicative of a sensed signal. The sensed signal includes a source signal component and a source noise component. The apparatus also includes a reference module configured for reference information indicative of a reference signal. The reference signal also includes a reference noise component. The apparatus also includes a filter module configured as a fixed lag Kalman smoother. The filter module is configured for adaptively filtering the reference signal to generate an estimate of the source noise component. The apparatus also includes a processing module configured for calculating an output signal based on the sensed signal and the estimate of the source noise component. The apparatus also includes an interface module configured for transmitting an indication of the output signal. The filter module is further configured for, based on the output signal, tuning the Kalman smoother. 119.-. (canceled)20. An apparatus , comprising:a memory; and receive sensed information indicative of a sensed signal, the sensed signal including a source signal component and a source noise component;', 'receive reference information indicative of a reference signal, the reference signal including a reference noise component correlated with the source noise component;', 'process, via an adaptive filter configured as a fixed lag Kalman smoother, the reference signal to generate an estimate of the source noise component;', 'determine an output signal indicative of an estimate of the source signal component by adjusting the sensed signal to account for the estimate of the source noise component; and, 'a processor operatively coupled to the memory, the processor configured totune one or more aspects of the fixed lag Kalman smoother based on the output signal.21. The apparatus of claim 20 , wherein the fixed lag Kalman smoother introduces a delay between the output signal and the reference signal such that the ...

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06-02-2020 дата публикации

SIGNAL PROCESSOR, FILTER, CONTROL CIRCUIT FOR POWER CONVERTER CIRCUIT, INTERCONNECTION INVERTER SYSTEM AND PWM CONVERTER SYSTEM

Номер: US20200044557A1
Принадлежит:

A signal processor is configured to perform a process equivalent to performing a series of fixed-to-rotating coordinate conversion, a predetermined process and then rotating-to-fixed coordinate conversion, while maintaining linearity and time-invariance. The signal processor performs a process given by the following matrix G: 130-. (canceled)32. The signal processor according to claim 31 , wherein the transfer function F(s) is equal to one of K/s (Krepresents an integral gain) claim 31 , K+K/s (Krepresents a proportional gain claim 31 , and Krepresents an integral gain) or K+K/s+K·s (Krepresents a proportional gain claim 31 , Krepresents an integral gain claim 31 , and Krepresents a differential gain).33. A control circuit for controlling a plurality of switching units inside a power converter circuit by a PWM signal claim 31 , comprising:{'claim-ref': {'@idref': 'CLM-00031', 'claim 31'}, 'a signal processor according to ; and'}a PWM signal generator configured to generate a PWM signal based on an output from the signal processor.34. The control circuit according to claim 33 , wherein the power converter circuit relates to a three-phase alternate current.35. The control circuit according to claim 33 , further comprising a divergence determination unit and an output control unit claim 33 ,wherein the divergence determination unit is configured to determine, based on output signals from the signal processor, if control for driving the plurality of switching units tends to diverge, andwherein when the divergence determination unit determines that the control for driving the plurality of switching units tends to diverge, the output control unit stops the output signal or changes a phase of the output signal to another phase whereby the control for driving the plurality of switching units does not diverge.36. The control circuit according to claim 33 , wherein the power converter circuit comprises a converter circuit for conversion of AC power supplied from an electrical ...

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18-02-2016 дата публикации

DIGITAL FILTER

Номер: US20160049923A1
Автор: MENKHOFF Andreas
Принадлежит:

Methods and apparatuses in which a first stage of a digital filter receives input data to be filtered, the first stage of a digital filter operating at a first clock; a second stage of the digital filter outputs filtered output data, the second stage of the digital filter operating on a second clock, wherein a ratio of a frequency of the first clock and a frequency of the second clock is a fractional number, and a frequency of the second clock is higher than a frequency of the first clock; the first stage receives an indication of a ratio of the first clock and the second clock; and the first stage receives an indication of a time offset between (1) a clock pulse of the second clock, which occurs between a first clock pulse and a second clock pulse of the first clock, and (2) the first clock pulse of the first clock. 125-. (canceled)26. An apparatus , comprising:a first stage to receive an input, the first stage including: a register, at most two multipliers, at least two adders, coupled together to provide first and second inputs in response to the received input;a first sampler to receive the first input and to sample it to provide a first sampled input;a second sampler to receive the second input and to sample it to provide a second sampled input;a second stage including an adder and a register which are to receive the first and second sampled inputs, respectively, and to generate an output.27. The apparatus of claim 26 , wherein the first stage is to operate on a first frequency claim 26 , wherein the second stage is to operate on a second frequency claim 26 , and wherein the first frequency is different from the second frequency.28. The apparatus of claim 27 , wherein the first frequency is lower than the second frequency.29. The apparatus of claim 27 , wherein a ratio of the first frequency relative to the second frequency is a fractional number.30. The apparatus of claim 27 , wherein the at most two multipliers are first and second multipliers claim 27 , and ...

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06-02-2020 дата публикации

Apparatuses and methods for shifting a digital signal by a shift time to provide a shifted signal

Номер: US20200044626A1
Принадлежит: Apple Inc, Intel IP Corp

An apparatus for shifting a digital signal having a first sample rate by a shift time to provide a shifted signal having a second sample rate is provided. The apparatus includes a sample rate converter configured to provide a value of an interpolated signal at a compensated sample time as a sample of the shifted signal, the interpolated signal being based on the digital signal. The sample rate converter is configured to modify a time interval between a sample time of the digital signal and the compensated sample time based on the shift time.

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16-02-2017 дата публикации

Apparatuses and methodologies for decision feedback equalization using particle swarm optimization

Номер: US20170048088A1

Methods and apparatuses are provided for channel equalization in a communication system. The method includes initializing, using processing circuitry, filter coefficients of an adaptive decision feedback equalizer randomly in a predetermined search space. Further, the method includes updating, using the processing circuitry, the filter coefficients. The filter coefficients are updated using a least mean square recursion when the filter coefficients are stagnant. The filter coefficients are updated using a particle swarm optimization procedure when the filter coefficients are not stagnant. Further, the updating step is repeated until a predetermined stopping criteria is met. Further, the method includes, filtering, using the processing circuitry, a received signal using the filter coefficients.

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14-02-2019 дата публикации

CONTROL APPARATUS FOR POWER STEERING APPARATUS AND POWER STEERING APPARATUS USING THE SAME

Номер: US20190047614A1
Принадлежит: Hitachi Automotive Systems, Ltd.

Provided is a control apparatus for a power steering apparatus, and a power steering apparatus using it that can reduce electromagnetic noise with the aid of a spread spectrum, thereby realizing stabilized motor control. The control apparatus for the power steering apparatus includes a PWM carrier period setting portion configured to set a natural number of PWM carrier periods within one period of a control period and also changeably set a length of the PWM carrier period, a motor current detection execution portion configured to detect a motor current during the control period, a motor rotational angle detection execution portion configured to detect a motor rotational angle during the control period, and an execution timing setting portion configured to set a timing at which the motor current is detected by the motor current detection execution portion or a timing at which the motor rotational angle is detected by the motor rotational angle detection execution portion, based on the control period set by the control period setting portion. 1. A control apparatus for a power steering apparatus , the control apparatus being configured to drive and control a brushless motor configured to provide a steering force to a steering mechanism configured to turn a turning target wheel according to a steering operation performed on a steering wheel , the control apparatus comprising:a current instruction value calculation portion configured to calculate a current instruction value directed to the brushless motor according to a driving condition of a vehicle;a voltage instruction value calculation portion configured to calculate a voltage instruction value directed to the brushless motor based on the current instruction value;a PWM control portion configured to output a PWM duty signal to each phase of the brushless motor according to the voltage instruction value;a bridge circuit including a switching circuit configured to be driven and controlled by the PWM duty signal, the ...

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08-05-2014 дата публикации

Systems and Methods for Partially Conditioned Noise Predictive Equalization

Номер: US20140129603A1
Автор: Xia Haitao, Yang Shaohua
Принадлежит: LSI Corporation

Various embodiments of the present invention provide systems and methods for equalization. As an example, a circuit for data equalization is described that includes a 2N state detector circuit that provides a series of detected bits based upon a conditioned input, and a noise predictive filter having a plurality of taps and operable to provide at least a portion of the conditioned input. At least a first of the plurality of taps uses a first subset of the series of detected bits, and a second of the plurality of taps uses a second subset of the series of detected bits. The first subset of the detected bits includes one more bit than the second subset of the detected bits. 1. A method for calibrating a partially conditioned equalization circuit , the method comprising:providing an equalizing circuit operable to equalize a data input to a three value (g2, g1, g0) target and to provide an equalized output;{'sub': −4', '−3', '−2', '−1', '0, 'providing a series of detected bits (a, a, a, a, a);'}{'sub': '1', 'claim-text': {'br': None, 'sub': 1', '−2', '2', '−1', '1', '0', '0, 'i': a', 'g', '+a', 'g', '+a', 'g, 'NC=−();'}, 'calculating a first noise component (NC) in accordance with the following equation{'sub': '2', 'claim-text': {'br': None, 'sub': 2', '−3', '2', '−2', '1', '−1', '0, 'i': a', 'g', '+a', 'g', '+a', 'g, 'NC=−();'}, 'calculating a second noise component (NC) in accordance with the following equation{'sub': '3', 'claim-text': {'br': None, 'sub': 3', '−4', '2', '−3', '1', '−2', '0, 'i': a', 'g', '+a', 'g', '+a', 'g, 'NC=−(); and'}, 'calculating a third noise component (NC) in accordance with the following equation{'sub': '4', 'claim-text': {'br': None, 'sub': 4', '−4', '1', '−3', '0, 'i': a', 'g', '+a', 'g, 'NC=−().'}, 'calculating a fourth noise component (NC) in accordance with the following equation2. The method of claim 1 , the method further comprising:{'sub': −2', '−1', '0, 'claim-text': {'br': None, 'sub': 1', '0', '2', '−1', '3', '−2, 'i': f', 'f', ' ...

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03-03-2022 дата публикации

SEAMLESS NON-LINEAR VOLTAGE REGULATION CONTROL TO LINEAR CONTROL APPARATUS AND METHOD

Номер: US20220069703A1
Принадлежит: Intel Corporation

A digital control scheme controls an integrator of a PID filter to implement non-linear control of saturating the duty cycle during which the proportional and derivative terms of the PID filter are set to 0 while the integrator and its internal states (previous values or memory) is set to a duty cycle that is the sum of the current nominal duty cycle plus a deltaD. The deltaD is the maximum duty cycle increment that is used to regulate a voltage regulator from ICCmin to ICCmax and is a configuration register that can be set post silicon. An FSM moves from a non-linear all ON state to an open loop duty cycle which maintains the output voltage slightly higher than the required Vref. After a certain period in this open loop, the FSM then ramps down the open loop duty cycle value until the output voltage is close to the Vref.

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03-03-2022 дата публикации

METHOD AND APPARATUS FOR REDUCED SIZE RF FILTER

Номер: US20220069856A1
Принадлежит:

A radio frequency (RF) unit and a method for RF isolation. The RF unit includes first and second RF couplers, an RF filter, and an RF canceler connected in parallel with the RF filter. The first RF coupler is configured to receive an input signal. The RF filter is configured to receive a first portion of the input signal from the first RF coupler and attenuate frequencies outside of a passband of the RF filter from the first portion of the input signal. The RF canceler is configured to receive a second portion of the input signal from the first RF coupler and generate a cancellation signal from the second portion of the input signal based on a target frequency band of the RF canceler. The second RF coupler is configured to combine the cancellation signal with an output of the RF filter to generate an output signal.

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22-02-2018 дата публикации

Method for reduction of aliasing introduced by spectral envelope adjustment in real-valued filterbanks

Номер: US20180053517A1
Принадлежит: DOLBY INTERNATIONAL AB

The present invention proposes a new method for improving the performance of a real-valued filterbank based spectral envelope adjuster. By adaptively locking the gain values for adjacent channels dependent on the sign of the channels, as defined in the application, reduced aliasing is achieved. Furthermore, the grouping of the channels during gain-calculation, gives an improved energy estimate of the real valued subband signals in the filterbank.

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25-02-2016 дата публикации

Control facility with adaptive fault compensation

Номер: US20160056794A1
Принадлежит: SIEMENS AG

A control facility for controlling a controlled system experiencing a disturbance includes a front nodal point receiving a target value and an actual value outputted by the controlled system and supplying a difference value corresponding to a difference between the target value and the actual value to a compensation circuit. The compensation circuit supplies a frequency-filtered and time-delayed signal formed as the sum of the weighted difference value and a weighted feedback signal as an input to a controller for the controlled system. The sum of a filter delay time and of first and second propagation delays is an integer multiple of the cycle duration of the disturbance, and a sum of the filter delay time and the first propagation delay is an integer multiple of the cycle duration minus a propagation time, which elapses until a change in the target value causes a change in the actual value.

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22-02-2018 дата публикации

METHODS AND SYSTEMS FOR EVENT-DRIVEN RECURSIVE CONTINUOUS-TIME DIGITAL SIGNAL PROCESSING

Номер: US20180054186A1
Автор: Chen Yu, TSIVIDIS Yannis
Принадлежит:

Continuous-time digital systems implemented with separate timing paths and data paths are disclosed. The disclosed continuous-time digital systems, can implement an event-grouping and detection method that can be used feedback systems with propagation delays. By implementing event-detection into a feedback loop of a continuous-time digital system, the system can automatically stop when there is no event in the system. When new events are detected the system can commence operation. 1. A continuous-time digital signal processor comprising:an event-grouping block, configured to receive a first input timing signal, a second input timing signal, and to generate an intermediate timing signal;a first time delay block, configured to receive the intermediate timing signal and generate an output timing signal;a second time delay block, configured to receive the output timing signal and generate the second input timing signal;a two-channel memory configured to receive a first data input and a second data input and to generate a first intermediate data signal and a second intermediate data signal;an arithmetic operation block, configured to receive the first intermediate data signal, the second intermediate data signal and to generate an output data signal, the arithmetic operation block comprising:a scalar block configured to receive the second intermediate data signal and generate a scaled version of the second intermediate data signal; andan adder configured to receive the first intermediate data signal and the scaled version of the second intermediate data signal, and generate the output data signal; anda first-in-first-out (FIFO) memory configured to receive the output data signal and to generate the second input data signal.2. The continuous-time digital signal processor of claim 1 , wherein the adder is configured to receive data at the first intermediate data signal and calculate the output data signal claim 1 , in response to a pulse on the intermediate timing signal.3 ...

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25-02-2016 дата публикации

AUDIO FILTERING WITH VIRTUAL SAMPLE RATE INCREASES

Номер: US20160057535A1
Автор: BARRATT Lachlan Paul
Принадлежит:

The present invention relates broadly to a method of digitally filtering an audio signal by applying a composite audio filter. The composite audio filter may be obtained by applying one audio filter to another audio filter each having the same predetermined sample rate including neighbouring sample points. The other audio filter may also include one or more intervening sample points between adjacent of its neighbouring sample points. The one audio filter may be applied to the other audio filter at an adjusted sampling rate relative to the other audio filter. The adjusted sampling rate may be inversely proportional to the number of intervening sample points relative to the number of neighbouring sample points for the other filter. The frequency response curve for the composite filter derived using the adjusted sampling rate may be more indicative of an idealised lowpass filter. The frequency response with the adjusted sampling rate may display a more bell-shaped characteristic compared with the frequency response without an adjusted sampling rate (shown in broken line detail). 1. A method of digitally filtering an audio signal , said method comprising the steps of:providing an audio filter at a predetermined sample rate including neighbouring sample points;providing another audio filter at the predetermined sample rate including an intervening sample point between adjacent of its neighbouring sample points;applying the audio filter to the other audio filter to provide a composite audio filter, said filter being applied at an adjusted sampling rate relative to the other audio filter; andfiltering the audio signal using the composite audio filter.2. A method as defined in any one of wherein the adjusted sampling rate is inversely proportional to the number of intervening sample points relative to the number of neighbouring sample points for the other filter.3. A method as defined in either of or wherein the step of applying the audio filter to the other audio filter ...

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