Logikschaltungen, die ausgelegt sind, um das Verhalten zu verbessern

Torschaltung mit Feldeffekt- und Bipolartransistoren.

Ratiod BiCMOS logic circuits

In a logic circuit 100, an optimum ratio is provided between the widths of the MOS pull-up 106 and pull-down 104 devices, with one or more bipolar devices 102 connected to the output 112. This optimum ratio substantially minimises the propagation delay of the circuit. An empirically derived ratio may be applied to circuits having different fanouts, different total MOS size, and different emitter lengths, but will remain substantially optimal. ...

Memory repair multiplexer with reduced propagation delay

The output 34 of a memory repair multiplexer 30 is fed directly to an output terminal 16a. After a short delay the output is buffered by enabling a non-inverting driver 36 coupled at its input and output to the multiplexer output node. The direct connection of the multiplexer output 34 to the output terminal 16a avoids the propagation delay of the driver 36. A data latch may be interposed between the multiplexer output 34 and the input of the driver 36 (figure 4), so that the circuit may be used in EDO mode SIMMs.

Logic circuits scaled to enhance performance

Level shifting circuit

Semiconductor device

A semiconductor device is provided which has a driving circuit operable to drive a circuit that has a delay, the semiconductor device including: an auxiliary driving circuit operable to accelerate drive of the driving circuit, which receives a drive signal of the driving circuit as an input signal.

ADAPTIVE CLOCKING SCHEME TO ACCOMMODATE SUPPLY VOLTAGE TRANSIENTS

Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.

Signal receiving and signal processing unit

A signal receiving and signal processing unit connected to one or several conductors is adapted to transmit information-carrying signals in the form of voltage pulses. A conductor is connected to a transistor belonging to a signal receiving circuit, to have an effect upon a current by using variations in the voltage pulses and the voltage value of a pulse. The current is in the form of pulses passing through the transistor. The current is generated by the voltage pulse variations and a voltage level, and the current is adapted to an information-carrying form in a signal processing circuit. The transistor belonging to the signal receiving circuit is coordinated with at least one other transistor to form a current mirror. The ability of the signal receiving circuit to receive, detect, and process the signals is adjustable through a current generating circuit such that an increasing current value provides detection of a voltage pulse at an increased transfer rate and vice versa.

Calibration methods and circuits for optimized on-die termination

Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Majority logic gate fabrication

A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.

Electronic circuit with a differential pair of transistors and logic gate comprising such a circuit

An electronic circuit includes at least one differential pair of transistors, a control transistor switch, a first current source and a second current source. The second current source is connected to a common emitter node of the pair of transistors in order to accelerate the discharge of parasitic capacitances during a switching operation.

Logic circuits scaled to enhance performance

Noise attenuation output buffer

ENABLING CIRCUITRY FOR LOGIC CIRCUITS

In order to reduce the time it takes on-chip circuitry to generate an internal enabling signal from an external clock signal and an external enabling signal, the external clock signal is applied directly to the non-inverting input of an (Alpha) AB gate (16). The output of the (Alpha) AB gate and an external enabling signal are provided to first and second inputs of a NOR gate (4) the output of which represents the internal enabling signal which is fed back to the inverting input of the (Alpha) AB gate. Thus, the clock signal propagates through only two stages of delay rather than three as is the case with prior an enabling circuitry.

Clock methods and circuits for optimized on-die termination

Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Модулярное устройство вычисления систем линейных алгебраических уравнений

Изобретение относится к вычислительной технике и может быть использовано в специализированных вычислительных машинах для вычисления слабообусловленных систем линейных алгебраических уравнений. Технический результат заключается в повышении быстродействия функционирования модулярного устройства при реализации слабообусловленных систем линейных алгебраических уравнений. Технический результат достигается за счет введения в устройство вычисления систем линейных алгебраических уравнений (СЛАУ) блоков формирования остатка по модулю, блока вычисления обратных матриц, выполняющих восстановление числа по избыточному модулю, и блока мажоритарных устройств, выполняющих реализацию вычислений СЛАУ в целочисленной неотрицательной форме. 1 ил.

Триггерный логический элемент ИЛИ

Изобретение относится к цифровой схемотехнике. Технический результат: повышение нагрузочной способности триггерного логического элемента ИЛИ. Триггерный логический элемент ИЛИ содержит пять транзисторов, пять резисторов, источник питающего постоянного напряжения и источник опорного постоянного напряжения. Новым является то, что в него введен р-n-р дополнительный транзистор, эмиттер которого подсоединен к общему выводу третьего резистора и коллектора третьего транзистора, база дополнительного транзистора подключена к общему выводу коллекторов первого, второго транзисторов и первого резистора, коллектор дополнительного транзистора подсоединен и к базе четвертого транзистора, и к одному из двух выводов пятого резистора, свободный вывод этого пятого резистора соединен со свободным выводом четвертого резистора и их общий вывод образует относительно «земли» выход логического элемента. 2 ил.

PROGRAMMABLE LEVEL SHIFTING INTERFACE DEVICE

... 12 A programmable logic shifting interface circuit provides programmable high and low level output signals from TTL input signals. Programmable upper and lower logic levels are available at the output so that a wide variety of different digital circuits may be tested by the invention.

Semiconductor device

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

A semiconductor integrated circuit device 1 includes a plurality of basic cells 5 each having therein a logic transistor 2 that performs logical operations, and a power switching transistor 3 that can interrupt leakage current when the logic transistor 2 is not operated. The semiconductor integrated circuit device 1 further includes a wiring 6 that connects virtual power nodes 4 as the connection points between the logic transistors 2 and the power switching transistors 3, between individual basic cells 5a and 5b included in a plurality of basic cells 5. Here, a basic cell includes a power switching transistors 3 that can interrupt leakage current when the logic transistors 2 are not operated, in addition to the logic transistors 2. Thereby, switching transistors 3 can be disposed in the optimal positions of the cells 5 and basic cells 5 having a small restriction in disposition and wide scope of application can be provided.

SEARCH DEVICE AND SEMICONDUCTOR DEVICE

To provide a search device with less memory consumption, the search device includes a first associative memory searched with a first search key, a second associative memory searched with a second search key, a concatenated search data generating unit that generates first search information based on hit information including multiple hits in the first associative memory, and a search key generating unit that includes a first key generating unit generating a portion of search data as the first search key and a second search key generating unit generating the first search information and another portion of the search data as the second search key.

Ausgangsschaltung

Driver circuit for a semiconductor power switch

A driver circuit (10) for controlling a semiconductor power switch (Q7) comprises a first power driver transistor (QS) and a second power driver transistor (Q5) complementary to the first power driver transistor (08). Both power driver transistors (Q5, Q6) have an output terminal connected to an input terminal {34} of the semiconductor power switch (Q7). An input terminal of the second power driver transistor (Q5) is connected to a half bridge circuit comprising a; first pre-driver transistor (Q3) and a second pre-driver transistor (04) complementary to the first pre-driver transistor Подробнее

SYSTEM AND METHOD FOR FACILITATING USE OF COMMERCIAL OFF-THE-SHELF (COTS) COMPONENTS IN RADIATION-TOLERANT ELECTRONIC SYSTEMS

A method for selecting components in a radiation tolerant electronic system, comprising, determining ionizing radiation responses of COTS devices under various radiation conditions, selecting a subset of the COTS devices whose radiation responses satisfy threshold radiation levels, applying mathematical models of the COTS devices for post-irradiation conditions to determine radiation responses to ionizing radiation; implementing a radiation-tolerant architecture using COTS devices from the selected subset, the implemented circuit may be tested for robustness to ionizing radiation effects without repeated destructive tests of the hardware circuit by using the mathematical models for simulating response to the ionizing radiation, and implementing a multi-layer shielding to protect the implemented circuit under various radiation conditions.

SEQUENTIAL CIRCUIT HAVING INCREASED NEGATIVE SETUP TIME

A sequential circuit includes a first gate circuit, a second gate circuit and an output circuit. The first circuit generates a first signal based on an input signal, an input clock signal and a second signal. The second circuit generates an internal clock signal by performing a NOR operation on the first signal and an inversion clock signal which is inverted from the input clock signal, and generates the second signal based on the internal clock signal and the input signal. The output circuit generates an output signal based on the second signal. Operation speed of the sequential circuit and the integrated circuit including the same may be increased by increasing the negative setup time reflecting a transition of the input signal after a transition of the input clock signal, through mutual controls between the first circuit and the second circuit. FIG. 1 ...

Band Segmented Bootstraps and Partitioned Frames

An apparatus and a method are provided for generating and transmitting one or more band segmented bootstrap signals. For example, a transmitter may be configured to generate a plurality of sequence numbers and apply cyclic shift to each of the plurality of sequence number. The transmitter is further configured to map each of the shifted sequence numbers to at least one frequency domain subcarrier of a plurality of frequency domain subcarriers, and translate each subcarrier of the plurality of subcarriers to a time domain sequence. Each subcarrier of the plurality of subcarriers may be shifted with respect to other subcarriers of the plurality of subcarriers, thereby aligning each segment of the band segmented bootstrap signals next to each other in the frequency domain.

Gate circuit of combined field-effect and bipolar transistors

A high-speed operation, low-space consumption gate circuit structure-comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.

Integrated circuit arrangements

Sequential circuit having increased negative setup time

A sequential circuit includes a first gate circuit, a second gate circuit and an output circuit. The first circuit generates a first signal based on an input signal, an input clock signal and a second signal. The second circuit generates an internal clock signal by performing a NOR operation on the first signal and an inversion clock signal which is inverted from the input clock signal, and generates the second signal based on the internal clock signal and the input signal. The output circuit generates an output signal based on the second signal. Operation speed of the sequential circuit and the integrated circuit including the same may be increased by increasing the negative setup time reflecting a transition of the input signal after a transition of the input clock signal, through mutual controls between the first circuit and the second circuit.

Synchrones, digitales Schaltwerk

PROGRAMMABLE LEVEL SHIFTING INTERFACE DEVICE

BAND SEGMENTED BOOTSTRAPS AND PARTITIONED FRAMES

Apparatuses and methods are provided for generating, transmitting, receiving, and decoding one or more band segmented bootstrap signals and one or more corresponding partitioned post bootstrap signals. For example, a transmitter is configured to generate a first set of symbols and a second set of symbols, where the first set of symbols includes information about the second set of symbols. The transmitter is further configured to generate a third set of symbols and a fourth set of symbols, where the third set of symbols includes information about the fourth set of symbols. The transmitter is also configured to generate a data frame including the first, second, third, and fourth set of symbols. A bandwidth of the data frame includes a first segment and a second segment.

Signal-Receiving and Signal Processing Unit

Band segmented bootstraps and partitioned frames

An apparatus and a method are provided for generating and transmitting one or more band segmented bootstrap signals. For example, a transmitter may be configured to generate a plurality of sequence numbers and apply cyclic shift to each of the plurality of sequence number. The transmitter is further configured to map each of the shifted sequence numbers to at least one frequency domain subcarrier of a plurality of frequency domain subcarriers, and translate each subcarrier of the plurality of subcarriers to a time domain sequence. Each subcarrier of the plurality of subcarriers may be shifted with respect to other subcarriers of the plurality of subcarriers, thereby aligning each segment of the band segmented bootstrap signals next to each other in the frequency domain.

Digital power multiplexer

Semiconductor integrated circuit

A semiconductor integrated circuit comprises logic cones having a structure in which substrates thereof are isolated from each other and substrate potentials can be controlled, and a potential switching section for supplying a substrate voltage from any of a first substrate bias supply potential and a second substrate bias supply potential to the logic cone. A signal output by a logic cone previous to a logic cone whose substrate potential is controlled is input as a trigger signal to the substrate supply potential switching section.

Calibration Methods and Circuits to Calibrate Drive Current and Termination Impedance

Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Noise attenuation output buffer

SIGNAL-RECEIVING AND SIGNAL-PROCESSING UNIT

The present invention comprises a signal-receiving and signal-processing unit connected to one or several conductors adapted to transmit information-carrying signals in the form of voltage pulses. A conductor is connected to a transistor belonging to a signal-receiving circuit, to have an effect upon a current by using variations in the voltage pulses and the voltage value of a pulse. The current is in the form of pulses passing through the transistor. The current is generated by the voltage pulse variations and a voltage level, and the current is adapted to an information-carrying form in a signal-processing circuit. The transistor belonging to the signal-receiving circuit is coordinated with at least one other transistor to form a current mirror. The ability of the signal-receiving circuit to receive, detect, and process the signals is adjustable through a currentgenerating circuit such that an increasing current value provides detection of a voltage pulse at an increased transfer rate ...

TERMINATION CALIBRATION SCHEME USING A CURRENT MIRROR

Systems, apparatuses, and methods for conveying and receiving information as electrical signals in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry.

Dynamically adjustable circuit with circuit of characterized-path and method for generating circuit of characterized-path

An integrated circuit and a method are provided. An integrated circuit comprises a first circuit, with a first character and at least one external control signal, and a character control unit. The character control unit controls the at least one external control signal and has a second circuit, with a second character essentially proportional to the first character, a character adjuster for adjusting the at least one external control signal, and a character monitor for monitoring the operation behavior of the second circuit to control the character adjuster to adjust the at least one external control signal accordingly.

Integrated circuit with pre-heating for reduced subthreshold leakage

Certain semiconductor processes provide for the use of multiple different types of transistors with different threshold voltages in a single IC. It can be shown that in certain ones of these semiconductor processes, the speed at which high threshold transistors can operate at decreases with decreasing temperature. Thus, the overall processing speed of an IC that implements high threshold transistors is often limited by the lowest temperature at which the IC is designed (or guaranteed) to properly function. Embodiments of a system and method that overcome this deficiency by "pre-heating" the IC (or at least portions of the IC that implement the high threshold transistors) such that the IC can operate at a frequency (once pre-heated) higher than what would otherwise be possible for a given, minimum temperature at which the IC is designed (or guaranteed) to properly function at are provided.

autocarregadores segmentados por faixa e quadros particionados

SYSTEM FOR CLOCKING AN INTEGRATED CIRCUIT

Embodiments provide systems and methods for dynamically regulating the clock frequency of an integrated circuit (IC) based on the IC supply voltage. By doing so, the clock frequency is no longer constrained by a worst-case voltage level, and a higher effective clock frequency can be supported, increasing the IC performance. Embodiments include a wave clocking system which uses a plurality of delay chains configured to match substantially the delays of respective logic paths of the IC. As the delays of the logic paths vary with supply voltage and temperature changes, the delay chains matched to the logic paths experience substantially similar changes and are used to regulate the clock frequency of the IC.

Search device includes associative memory, search data generating unit for generating search information based on hit information and a search key generating unit generating search keys based on search information and the search data

To provide a search device with less memory consumption, the search device includes a first associative memory searched with a first search key, a second associative memory searched with a second search key, a concatenated search data generating unit that generates first search information based on hit information including multiple hits in the first associative memory, and a search key generating unit that includes a first key generating unit generating a portion of search data as the first search key and a second search key generating unit generating the first search information and another portion of the search data as the second search key.

Scalable and configurable system on a chip interrupt controller

Embodiments include a system and method for an interrupt controller that propagates interrupts to a subsystem in a system-on-a-chip (SOC). Interrupts are provided to an interrupt controller that controls access of interrupts to a particular subsystem in the SOC that includes multiple subsystems. Each subsystem in the SOC generates multiple interrupts to other subsystems in the SOC. The interrupt controller processes multiple interrupts and generates an interrupt output. The interrupt output is then transmitted to a particular subsystem.

Noise attenuation output buffer

A noise attenuation output buffer comprising a signal delay circuit for delaying input data for a predetermined time period, a NOR gate for NORing an output signal from the signal delay circuit and an enable signal, a pull-up/down driver for performing a pull-up operation in response to the input data and a pull-down operation in response to an output signal from the NOR gate to provide output data, a noise attenuation controller for outputting a noise attenuation signal in response to a drive voltage, the input data and the output signal from the NOR gate, and a noise attenuator for forming a current path between an output terminal of the NOR gate and a ground terminal in response to the noise attenuation signal from the noise attenuation controller and the output data from the pull-up/down driver to suppress the generation of noise. According to the present invention, the noise attenuation output buffer effectively controls ON timing of the noise attenuator to effectively attenuate noise ...

High Speed and High Voltage Driver

Systems, methods, and apparatus for biasing a high speed and high voltage driver using only low voltage transistors are described. The apparatus and method are adapted to control biasing voltages to the low voltage transistors such as not to exceed operating voltages of the low voltage transistors while allowing for DC to high speed operation of the driver at high voltage. A stackable and modular architecture of the driver and biasing stages is provided which can grow with a higher voltage requirement of the driver. Capacitive voltage division is used for high speed bias voltage regulation during transient phases of the driver, and resistive voltage division is used to provide bias voltage at steady state. A simpler open-drain configuration is also presented which can be used in pull-up or pull-down modes.

Calibration Methods and Circuits to Calibrate Drive Current and Termination Impedance

Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Gate circuit of combined field-effect and bipolar transistors

A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors (10, 11) and bipolar transistors (14, 15) and discharge means (12, 13) for discharging accumulated charges from these transistors (10, 11, 14, 15) when the field-effect-transistors (10, 11) and bipolar transistors (14, 15) are turned off. The circuit structure may comprise additional field-effect transistors (123). The circuit structure can be provided in the form of an integrated circuit whereby the bipolar transistors are preferably of vertical type.

Hochgeschwindigkeits- und Hochspannungs-Treiber

Es werden Systeme, Verfahren und Vorrichtungen zum Vorspannen eines Hochgeschwindigkeits- und Hochspannungs-Treibers nur unter Verwendung von Niederspannungstransistoren beschrieben. Die Vorrichtung und das Verfahren sind ausgelegt zum Steuern von Vorspannungen zu den Niederspannungstransistoren, um Arbeitsspannungen der Niederspannungstransistoren nicht zu überschreiten, während ein DC- bis Hochgeschwindigkeitsbetrieb des Treibers bei hoher Spannung gestattet wird. Eine stapelbare und modulare Architektur des Treibers und der Vorspannstufen wird bereitgestellt, die mit einer höheren Spannungsanforderung des Treibers wachsen kann. Es wird eine kapazitive Spannungsteilung für eine Hochgeschwindigkeits-Vorspannungsregelung während Übergangsphasen des Treibers verwendet, und resistive Spannungsteilung wird zum Liefern einer Vorspannung im eingeschwungenen Zustand verwendet. Es wird auch eine einfachere Open-Drain-Konfiguration vorgelegt, die in Hochsetz- oder Tiefsetzmodi verwendet werden ...

DRIVER CIRCUIT FOR A SEMICONDUCTOR POWER SWITCH

A driver circuit (10) for controlling a semiconductor power switch (Q7) comprises a first power driver transistor (QS) and a second power driver transistor (Q5) complementary to the first power driver transistor (08). Both power driver transistors (Q5, Q6) have an output terminal connected to an input terminal {34} of the semiconductor power switch (Q7). An input terminal of the second power driver transistor (Q5) is connected to a half bridge circuit comprising a; first pre-driver transistor (Q3) and a second pre-driver transistor (04) complementary to the first pre-driver transistor Подробнее

Noise attenuation output buffer

A noise attenuation output buffer comprising a signal delay circuit 50 for delaying input data for a predetermined time period, a NOR gate 10 for NORing an output signal from the signal delay circuit and an enable signal, a pull-up/down driver 40 for performing a pull-up operation in response to the input data and a pull-down operation in response to an output signal from the NOR gate to provide output data, a noise attenuation controller 20 for outputting a noise attenuation signal in response to a drive voltage, the input data and the output signal from the NOR gate, and a noise attenuator 30 for forming a current path between an output terminal of the NOR gate 10 and a ground terminal in response to the noise attenuation signal from the noise attenuation controller 20 and the output data from the pull-up/down driver to suppress the generation of noise. The noise attenuation output buffer effectively controls ON timing of the noise attenuator to effectively attenuate noise in the output ...

Signal-receiving and signal-processing unit

ADAPTIVE CLOCKING SCHEME

Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.

Signal-receiving and signal-processing unit

DRIVER CIRCUIT FOR A SEMICONDUCTOR POWER SWITCH

A driver circuit (10) for controlling a semiconductor power switch (Q7) comprises a first power driver transistor (QS) and a second power driver transistor (Q5) complementary to the first power driver transistor (08). Both power driver transistors (Q5, Q6) have an output terminal connected to an input terminal (34) of the semiconductor power switch (Q7). An input terminal of the second power driver transistor (Q5) is connected to a half bridge circuit comprising a; first pre-driver transistor (Q3) and a second pre-driver transistor (04) complementary to the first pre-driver transistor Подробнее

半導体モジュールおよびスイッチング素子の駆動装置

Halbleitervorrichtung mit einer Leistungsschalterhalbleitervorrichtung

Eine Halbleitervorrichtung (100) ist versehen mit einer Leistungsschalter-Halbleitervorrichtung (11, 12; 21, 22; 31, 32), einer integrierten Steuerschaltung (IC1, IC2, IC3), einem Stromdetektorabschnitt (3) und einer Schutzschaltung (54, 55, 56, 57). Die integrierte Steuerschaltung (IC1, IC2, IC3) steuert die Leistungsschalter-Halbleitervorrichtung (11, 12; 21, 22; 31, 32) an, und der Stromdetktorabschnitt (3) erfasst einen Strom, der in der Leistungsschalter-Halbleitervorrichtung (11, 12; 21, 22; 31, 32) fließt. Die Schutzschaltung (54, 55, 56, 57) vergleicht eine von dem Stromdetektorabschnitt (3) erhaltene erfasste Spannung mit einer von einer vorbestimmten Referenzspannung erhaltenen Vergleichsreferenzspannung, und beendet das Ansteuern der Leistungsschalter-Halbleitervorrichtung (11, 12; 21, 22; 31, 32) durch die integrierte Steuerschaltung (IC1, IC2, IC3), wenn die erfasste Spannung höher ist als die Vergleichsreferenzspannung. Weiter ist ein Anschluss (RREF) vorgesehen, der eine ...

Calibration methods and circuits to calibrate drive current and termination impedance

Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

A semiconductor integrated circuit device 1 includes a plurality of basic cells 5 each having therein a logic transistor 2 that performs logical operations, and a power switching transistor 3 that can interrupt leakage current when the logic transistor 2 is not operated. The semiconductor integrated circuit device 1 further includes a wiring 6 that connects virtual power nodes 4 as the connection points between the logic transistors 2 and the power switching transistors 3 , between individual basic cells 5 a and 5 b included in a plurality of basic cells 5 . Here, a basic cell includes a power switching transistors 3 that can interrupt leakage current when the logic transistors 2 are not operated, in addition to the logic transistors 2 . Thereby, switching transistors 3 can be disposed in the optimal positions of the cells 5 and basic cells 5 having a small restriction in disposition and wide scope of application can be provided.

Apparatus and method to update a default time interval based on process corner, temperature and voltage

A processor arrangement changes its default time interval for entering a power saving mode based on sensed operating conditions and predetermined time intervals to be used under various operating conditions to optimize power saving.

High Speed and High Voltage Driver

Systems, methods, and apparatus for biasing a high speed and high voltage driver using only low voltage transistors are described. The apparatus and method are adapted to control biasing voltages to the low voltage transistors such as not to exceed operating voltages of the low voltage transistors while allowing for DC to high speed operation of the driver at high voltage. A stackable and modular architecture of the driver and biasing stages is provided which can grow with a higher voltage requirement of the driver. Capacitive voltage division is used for high speed bias voltage regulation during transient phases of the driver, and resistive voltage division is used to provide bias voltage at steady state. A simpler open-drain configuration is also presented which can be used in pull-up or pull-down modes.

Majority logic synthesis

A method for optimizing an implementation of a logic circuit, comprising steps of providing an interpretation of the logic circuit in terms of 3 Boolean variable majority operators M, with each of the majority operators being a function of a plurality of variables that returns a logic value assumed by more than half of the plurality of variables, and a single Boolean variable complementation operator ′. The method further comprises providing a commutativity, a majority (Ω.M), an associativity (Ω.A), a distributivity (Ω.D), an inverter propagation (Ω.I), a relevance (Ψ.R), a complementary associativity (Ψ.C), and a substitution (Ψ.S) transformation; and combining the Ω.M, Ω.C, Ω.A, Ω.D, Ω.I, Ψ.R, Ψ.C and Ψ.S transformations to reduce an area of the logic circuit via (i) a reshaping procedure consisting of the Ω.A, Ω.C, Ω.D, Ω.I, Ψ.R, Ψ.S and Ψ.C transformations, applied either left-to-right or right-to-left moving identical or complemented variables in neighbor locations of the logic circuit ...

Unit including a circuit, device, and transmitting/receiving system

A unit including one or more circuits a first circuit includes a first circuit, a first capacitor, a charge storage, and a charge supplier. The first capacitor is for stabilizing operation of the first circuit. The charge storage stores an electrical charge prior to startup of the first circuit. The charge supplier charges the first capacitor at the time of startup of the first circuit, by means of supplying the first capacitor with the electrical charge stored in the charge storage.

Serial transmission driving method

The present invention discloses a serial transmission driving method, wherein a serial transmission driving device (STD) is connected with a first terminal (FT) and a second terminal (ST) of an equivalent load capacitor through a first differential bus (FDB) and a second differential bus (SDB). FDB and SDB are respectively connected with a high-potential terminal (HPT) and a low-potential terminal (LPT) through a first equivalent resistor and a second equivalent resistor. STD receives a trigger signal (TS) appearing during the transition between a turn-on signal (Ton) and a turn-off signal (Toff), generates a first potential (FP) and a second potential (SP) greater than FP according to TS, and respectively applies FP and SP to SDB and FDB. FP and SP fast change the potential of FT to be greater than that of ST. HPT and LPT maintain potentials of FDB and SDB until Toff ends.

Schreiberkennungsschaltung mit einem Schreibdetektor und einem bistabilen Element für Vier-Phasen-Quittungssignalisierung.

Linear input and non-linear output majority logic gate

A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.

Clock methods and circuits for optimized on-die termination

Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Linear input and non-linear output majority logic gate

A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.

Calibration Methods and Circuits to Calibrate Drive Current and Termination Impedance

Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Calibration methods and circuits to calibrate drive current and termination impedance

Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Leakage current reduction method

The method for powering down a circuit for a data retention mode includes: changing a supply voltage node from an active power voltage level to an inactive power level; coupling a source of a P channel device to the supply voltage node; providing a retaining power supply voltage level to a back gate of the P channel device; changing a drain voltage of the P channel device to a reference voltage level, wherein the reference voltage level is different from the retaining power supply voltage level; and changing a gate voltage of the P channel device to the reference voltage level.

Wave clocking

Embodiments provide systems and methods for dynamically regulating the clock frequency of an integrated circuit (IC) based on the IC supply voltage. By doing so, the clock frequency is no longer constrained by a worst-case voltage level, and a higher effective clock frequency can be supported, increasing the IC performance. Embodiments include a wave clocking system which uses a plurality of delay chains configured to match substantially the delays of respective logic paths of the IC. As the delays of the logic paths vary with supply voltage and temperature changes, the delay chains matched to the logic paths experience substantially similar changes and are used to regulate the clock frequency of the IC.

Dynamically adjustable circuit with characterized path circuit and method for generating characterized path circuit

A method for generating a characterized path circuit and a dynamic adjustable circuit utilizing the method are disclosed. The disclosed method comprises selecting an original critical path circuit comprising a plurality of logic gates, and performing a characterizing process over the original critical path circuit to derive a characterized critical path circuit. A second characteristic of the characterized critical path circuit is proportional to a first characteristic of the original critical path. The characterized critical path circuit is used for indicting whether the first characteristic conforms to a circuit need.

High speed and high voltage driver

Systems, methods, and apparatus for biasing a high speed and high voltage driver using only low voltage transistors are described. The apparatus and method are adapted to control biasing voltages to the low voltage transistors such as not to exceed operating voltages of the low voltage transistors while allowing for DC to high speed operation of the driver at high voltage. A stackable and modular architecture of the driver and biasing stages is provided which can grow with a higher voltage requirement of the driver. Capacitive voltage division is used for high speed bias voltage regulation during transient phases of the driver, and resistive voltage division is used to provide bias voltage at steady state. A simpler open-drain configuration is also presented which can be used in pull-up or pull-down modes.

Enabling circuitry for logic circuits

In order to reduce the time it takes on-chip circuitry to generate an internal enabling signal from an external clock signal and an external enabling signal, the external clock signal is applied directly to the non-inverting input of an AB gate. The output of the AB gate and an external enabling signal are provided to first and second inputs of a NOR gate the output of which represents the internal enabling signal which is fed back to the inverting input of the AB gate. Thus, the clock signal propagates through only two stages of delay rather than three as is the case with prior art enabling circuitry.

Gate circuit of combined field-effect and bipolar transistors

A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors (10,11) and bipolar transistors (14, 15) and discharge means (12, 13) for discharging accumulated charges from these transistors (10, 11, 14, 15) when the field effect-transistors (10, 11) and bipolar transistors (14, 15) are turned off.

Ausgabepufferspeicher zur Rauschdämpfung

Semiconductor device with auxiliary driving circuit

A semiconductor device is provided which has a driving circuit operable to drive a circuit that has a delay, the semiconductor device including: an auxiliary driving circuit operable to accelerate drive of the driving circuit, which receives a drive signal of the driving circuit as an input signal.

Circuits and methods for reducing the effects of level shifter delays in systems operating in multiple voltage domains

A method of interfacing circuits operating in different voltage domains includes receiving a first signal with a first circuit operating in a first voltage domain and generating a second signal with a second circuit operating in a second voltage domain. The second signal is level shifted between the first and second voltage domains with a level shifter and synchronized with the first signal with a third circuit operating in the first voltage domain.

PROACTIVE POWER MANAGEMENT USING A POWER MANAGEMENT UNIT

Embodiments of the present disclosure provide systems and methods for proactively managing power in a device. A power management unit (PMU) receives information from various subsystems of a device and estimates the total power required by each subsystem of the device. Based on this information, the PMU can predict power requirements for a particular subsystem or for one or more application(s) to execute. Based on this prediction, the PMU can reconfigure the subsystems so that the device executes more efficiently given the current battery life of the device. Proactive power management advantageously gives the PMU the capability to predict power needs of various subsystems of a device so that the power supplied to these subsystems can be managed in an intelligent way before battery resources are exhausted.

PROGRAMMABLE LEVEL SHIFTING INTERFACE DEVICE

A programmable logic shifting interface circuit provides programmable high and low level output signals from TTL input signals (12). Programmable upper and lower logic levels (30, 30a) are available at the output so that a wide variety of different digital circuits (11) may be tested by the invention.

Gate circuit of combined field-effect and bipolar transistors with an improved discharge arrangement

A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.

High speed and high voltage driver

Systems, methods, and apparatus for biasing a high speed and high voltage driver using only low voltage transistors are described. The apparatus and method are adapted to control biasing voltages to the low voltage transistors such as not to exceed operating voltages of the low voltage transistors while allowing for DC to high speed operation of the driver at high voltage. A stackable and modular architecture of the driver and biasing stages is provided which can grow with a higher voltage requirement of the driver. Capacitive voltage division is used for high speed bias voltage regulation during transient phases of the driver, and resistive voltage division is used to provide bias voltage at steady state. A simpler open-drain configuration is also presented which can be used in pull-up or pull-down modes.

Synchronous digital circuit

The invention relates to a synchronous digital circuit with state-controlled storage elements which in each case exhibit a clock input, at least two mutually complementary outputs and at least two inputs which are connected to form a logical OR combination. At least two state-controlled storage elements (10, 11) are connected in series. A first storage element (10) carries out the OR combinations and a second storage element (11) carries out the AND combinations of a combinational logic function. The set time of one storage element and the delay time in each case coincide for forming the OR and, respectively, AND combinations. This provides for high processing speed in the circuit. ...

Signalmottagande och signalbehandlande enhet

Thyristor driving apparatus

An apparatus for driving a thyristor in an alternating-current power grid includes a non-isolated power supply circuit and a throttling circuit. One terminal of a power supply input of the non-isolated power supply circuit is connected to a first terminal of the thyristor. The other terminal of the power supply input is connected to another phase of the power supply relative to the first terminal or a neutral lead. The non-isolated power supply circuit forms a signal trigger loop through the throttling circuit, a second terminal of the thyristor and the first terminal of the thyristor. A control terminal of the throttling circuit is connected to a third terminal of the thyristor. The apparatus of the present invention has advantages of occupying a small space and having a simple circuit, a great instantaneous triggering current, a high cost effectiveness, and a low power consumption.

Write-acknowledge circuit including a write detector and a bistable element for four-phase handshake signalling

A write-acknowledge circuit includes a write detector and a bistable element. The write detector has two write inputs, two complementary inputs and an acknowledge output, and is constituted by only two transistors which are connected in series. The complementary inputs are the control inputs of the two transistors and the acknowledge output is output from their common connection point. The write inputs are respectively coupled to the two remaining terminals of the two transistors and also to the two respective inputs of the bistable element. The complementary inputs are coupled crosswise to the outputs of the bistable element. The write signals represent a 1-bit variable encoded according to the Double-Rail Encoding method. Four-phase handshake signalling is used for the write signals. The acknowledge output is activated by the complementary inputs to the write detector in response to a write signal on either of the two write inputs, the acknowledge signal denoting that the write signal ...

High speed bipolar-MOS logic circuit including a series coupled arrangement of a bipolar transistor and a logic block having a MOSFET

A high-speed bipolar MOS logic circuit is provided which includes a load resistance coupled between a first power supply voltage terminal and an output terminal and a bipolar transistor having a collector coupled to said output terminal and a base for receiving a predetermined voltage or an input signal a logic block is also provided including one or more MOSFETs having a source-drain path coupled in series between the emitter of said bipolar transistor and a second power supply voltage terminal.

Semiconductor integrated circuit device

A semiconductor integrated circuit device 1 includes a plurality of basic cells 5 each having therein a logic transistor 2 that performs logical operations, and a power switching transistor 3 that can interrupt leakage current when the logic transistor 2 is not operated. The semiconductor integrated circuit device 1 further includes a wiring 6 that connects virtual power nodes 4 as the connection points between the logic transistors 2 and the power switching transistors 3, between individual basic cells 5a and 5b included in a plurality of basic cells 5. Here, a basic cell includes a power switching transistors 3 that can interrupt leakage current when the logic transistors 2 are not operated, in addition to the logic transistors 2. Thereby, switching transistors 3 can be disposed in the optimal positions of the cells 5, and basic cells 5 having a small restriction in disposition and wide scope of application can be provided.

Генератор случайного полумарковского процесса с симметричными законами распределения

Полезная модель относится к области вычислительной техники и может быть использована при построении имитационных моделей систем, работающих в условиях случайных возмущений, настройке и эксплуатации различных устройств автоматики.Техническим результатом, получаемым в данном техническом решении, является упрощение генератора случайного полумарковского процесса путем уменьшения количества ячеек блока памяти, в котором задаются длительности моделируемого случайного процесса, в 2 раза и уменьшения их разрядности.Технический результат достигается тем, что в генератор случайного полумарковского процесса с симметричными законами распределения, содержащий блок синхронизации, первый выход которого подключен к входу синхронизации первого регистра памяти, выход которого является выходом генератора, выход первого регистра памяти соединен с информационным входом второго регистра памяти, выход которого подключен к первому адресному входу первого блока памяти, второй адресный вход которого соединен с выходом третьего регистра памяти, информационный вход которого соединен с выходом датчика равномерно распределенных случайных чисел, выход первого блока памяти соединен с информационным входом первого регистра памяти, три ключа, элемент ИЛИ-НЕ, второй блок памяти, счетчик, блок ключей, элемент ИЛИ, первый вход которого соединен с вторым выходом блока синхронизации, выход элемента ИЛИ соединен с входом "Опрос" датчика равномерно распределенных случайных чисел, выход которого соединен с информационным входом блока ключей, счетчик, счетный вход которого соединен с первым входом блока синхронизации, выход счетчика подключен к входу элемента ИЛИ-НЕ, выход которого соединен с управляющими входами первого, второго и третьего ключей, информационные входы первого и второго ключа объединены и подключены к третьему входу блока синхронизации, четвертый выход которого подключен к информационному входу третьего ключа, выход которого подключен к входу синхронизации третьего регистра памяти, ...

Semiconductor Device, and Display Device and Electronic Device Utilizing the Same

A semiconductor device having a normal function means is provided, in which the amplitude of an output signal is prevented from being decreased even when a digital circuit using transistors having one conductivity is employed. By turning OFF a diode-connected transistor 101, the gate terminal of a first transistor 102 is brought into a floating state. At this time, the first transistor 102 is ON and its gate-source voltage is stored in a capacitor. Then, when a potential at the source terminal of the first transistor 102 is increased, a potential at the gate terminal of the first transistor 102 is increased as well by bootstrap effect. As a result, the amplitude of an output signal is prevented from being decreased.

Universal Digital Input Module in a Process Automation Controller

In a process automation controller, a universal digital input module is provided. The universal digital input module comprises a plurality of digital input channels, each channel to sink a first current at a first voltage level associated with an input having a digital high value and to sink a second current at a second voltage level associated with the input having a digital high value, wherein the first current is greater than the second current and wherein the first voltage is less than the second voltage.

Receiver circuit with high input voltage protection

An integrated circuit 2 includes a receiver circuit 4 for receiving an input signal PAD and converting this to an output signal OUT. Conduction path circuitry 14 couples an input 10 to a first node 16 . Buffer circuitry 18 is coupled between the first node 16 and an output 12 carrying the output signal Out. The conduction path circuitry comprises a first PMOS transistor 24 and a second PMOS transistor 26 connected between the input 10 and the first node 16 . A first NMOS transistor 28 is connected between the input 10 and the first node 16 . The gate of the second PMOS transistor 26 is coupled to the output 12 to directly receive the output signal and thereby achieve rapid cut off of the charging of the node 16 when the input voltage rises beyond a certain level which switches the buffer circuitry 18.

Vol up-shifting level shifters

A representative level-shifter comprises a dynamically biased current source circuit that receives a first voltage, a first and a second unidirectional current-conducting devices, a first and a second pull-down devices, and a pull-up device. The first and second unidirectional current-conducting devices are coupled to the dynamically biased current source circuit. A voltage output of the level-shifter is located at a first node that is located between the current-constant circuit and the second unidirectional current-conducting device. The first and second pull-down devices are coupled to the first and second unidirectional current-conducting devices, respectively. The pull-up device receives a second voltage and is coupled to the dynamically biased current source circuit and the first unidirectional current-conducting device. The pull-up device is configured to dynamically bias the dynamically biased current source circuit such that a voltage drop of the second unidirectional current-conducting device is output at the voltage output responsive to the pull-up device outputting the second voltage to the dynamically biased current source circuit, the first pull-down device being non-conducting and the second pull-down device being conducting.

Semiconductor device and method of adjusting characteristic thereof

To suppress the number of clocks needed to adjust the impedance of an output buffer. A pull-up replica buffer is connected between a calibration terminal and power supply wiring, and is controlled in impedance by a DRZQP signal supplied from a counter. A pull-down replica buffer is connected between ground wiring and a connection node A, and is controlled in impedance by a DRZQN signal supplied from the counter. More specifically, the DRZQP signal and the DRZQN signal indicate count values. The impedances of the replica buffers are increased or decreased stepwise in proportion to the count values. The count values are updated according to a binary search method.

Highly efficient class-d amplifier

A simplistic low cost circuit that generates the necessary drive voltage for use in a source follower totem pole power switching circuit is described where the simplified gate drive circuit may have a dual charge pump and a complementary pair of low-power switching Mosfets.

Switching circuits, latches and methods

Switching circuits, latches and methods are provided, such as those that may respond to an input signal that transitions from a first binary level to a second binary level. One such switching circuit may have a metastable state that is closer to a first voltage corresponding to the first binary level than it is to a second voltage corresponding to the second binary level. In other embodiments, the metastable state may be dynamically adjustable so that it is at one voltage before the circuit switches and at a different voltage after the circuit switches. As a result, the switching circuit may respond relatively quickly to the input signal transitioning from the first binary level to the second binary level.

Electronic device and method for buffering

A buffer is provided. The buffer includes a first switch and a second switch coupled in series at a first output node, a third switch and a fourth switch coupled in series at a second output node, a first current source and a second current source. The first current source is coupled with one side to the first switch and the third switch and with another side to a first supply voltage, the second current source is coupled with one side to the second switch and the fourth switch and with a second side to a second supply voltage. The first current source is configured to adjust an output swing in a first operation mode and in a second operation. The second current source is configured to adjust a common mode voltage level of the output signal in the first operation mode and to provide maximum series resistance in the second operation mode.

Level shifter circuit, scanning line driver and display device

An object of the present invention is to achieve a scanning line drive device which allows further reduction of circuit scale and production costs. A gate driver ( 100 ) of the present invention includes: a shift register circuit ( 1 ) including g latch circuits ( 21 ) to ( 2 g ); g selection circuits ( 8 ); and g level shifter circuits ( 3 ). A level shifter circuit ( 3 ) of an output drive circuit (st 1 ) receives a pulse ( 61 ) from a NAND circuit ( 6 ) of a selection circuit ( 8 ) at its input terminal (N 1 ); a pulse ( 71 ) from a NAND circuit ( 7 ) of the selection circuit ( 8 ) at its input terminal (N 2 ); and a pulse (Q 1 ) from a latch circuit ( 21 ) at its input terminal (N 3 ). The level shifter circuit ( 3 ) of the output drive circuit (st 1 ) outputs a voltage signal obtained by converting the voltage level of the pulse ( 61 ) from its output terminal (O 1 ); and a voltage signal obtained by converting the voltage level of the pulse ( 71 ) from its output terminal (O 2 ).

Serial i/o using jtag tck and tms signals

The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC.

High resolution output driver

High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such “differential” or “non-uniform” sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC. In an additional set of implementations, equalization and impedance calibration functions are implemented bilaterally in respective parallel sets of driver branches, rather than in the nested “DAC within a DAC” arrangement of the hierarchical implementations. Through such bilateral arrangement, multiplication of the equalizer and calibrator quantizations is avoided, thereby lowering the total number of sub-driver slices required to meet the specified ranges and resolutions.

Semiconductor device, circuit board device, and information processing device

In a semiconductor device, a selector selects a different reference voltage depending on whether the impedance of a transmitter or of a receiver is to be adjusted, and causes a reference voltage generator to generate the selected reference voltage. The reference voltage generator generates the reference voltage selected by the selector and applies the generated reference voltage to an impedance adjuster. The impedance adjuster adjusts the impedance of the transmitter and the impedance of the receiver, separately from each other, in accordance with the input reference voltage.

Level conversion circuit and semiconductor integrated circuit device employing the level conversion circuit

In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.

Ieee 1149.1 and p1500 test interfaces combined circuits and processes

In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals.

Driver circuit and video system

In a driver circuit in a transmission system, an output circuit outputs a differential signal based on input data signals. A current source control circuit controls a constant current source so that a common-mode potential of the differential signal becomes equal to a predetermined reference potential. An overshoot reduction circuit is connected to an input line of the common-mode potential of the current source control circuit, and reduces an overshoot of the common-mode potential based on the control signal.

Electrical Circuit For Transmitting Signals Between Two Masters And One Or More Slaves

An electrical circuit for transmitting signals between two masters and one or more slaves is described. The two masters and the slave or slaves are connected to one another via a bus system. At least one master data signal can be generated by each of the two masters, which signal can be received by the slave or slaves. A three-state gate is present at each of the outputs of the two masters at which the respective master data signal is present. The three-state gates are effective either as closed or as open switches. The three-state gates are activated in such a way that the three-state gate associated with the one of the two masters acts as a closed switch, and the three-state gate associated with the other of the two masters acts as an open switch.

Output stage formed inside and on top of an soi-type substrate

A method for controlling an output amplification stage comprising first and second complementary SOI-type power MOS transistors, in series between first and second power supply rails, the method including the steps of: connecting the bulk of the first transistor to the first rail when the first transistor is maintained in an off state; connecting the bulk of the second transistor to the second rail when the second transistor is maintained in an off state; and connecting the bulk of each of the transistors to the common node of said transistors, during periods when this transistor switches from an off state to an on state.

Buffer circuit having switch circuit capable of outputting two and more different high voltage potentials

A buffer circuit includes a first node receiving a first voltage, a second node receiving a second voltage lower than the first voltage, a third node, an output node driving the first voltage and the second voltage, a first transistor coupled between the first node and the output node, a second transistor coupled between the second node and the output node, one end of the second transistor being connected to the second node, another end of the second transistor being connected to the third node, and a switch circuit coupled between the output node and the third node. Both of the first transistor and the switch circuit include a transistor having a first breakdown voltage. The second transistor has a second breakdown voltage being different from the first breakdown voltage.

Differential output buffer

According to one embodiment, a main driver is configured to shift the level of a differential signal. A bypass circuit is configured to bypass current flowing through the main driver in such a manner as to contain the change amount of current running through the main driver flowing from a high power supply potential to a low power supply potential within a fixed range upon transition between an operating state and a standby state of the main driver.

Symmetrical, Direct Coupled Laser Drivers

Symmetrical, direct coupled laser drivers for high frequency applications. The laser drivers are in integrated circuit form and use a minimum of relatively small (low valued) external components for driving a laser diode coupled to the laser driver through transmission lines. An optional amplifier may be used to fix the voltage at an internal node at data frequency spectrum to improve circuit performance. Feedback to a bias input may also be used to fix the voltage at the internal node. Programmability and a burst mode capability may be included.

Low Voltage Differential Signal Driving Circuit and Digital Signal Transmitter

A low voltage differential signal (LVDS) driving circuit and a digital signal transmitter with the LVDS driving circuit are provided. The LVDS driving circuit includes a positive differential output terminal and a negative differential output terminal and a transition accelerator. A differential output signal is provided by the positive and negative differential output terminals. When the differential output signal transits from low to high, the transition accelerator couples the positive differential output terminal to a high voltage source and couples the negative differential output terminal to a low voltage source. When the differential output signal transits from high to low, the transition accelerator couples the positive differential output terminal to the low voltage source and couples the positive output terminal to the high voltage source.

Receiver circuit

A receiver circuit is provided which receives an external signal of high voltage and provides a corresponding internal signal of low voltage. The receiver circuit includes a voltage limiter, a level down shifter and an inverter of low operation voltage. The level down shifter has a front node and a back node, and includes a transistor with a gate and a source respectively coupled to the voltage limiter and the inverter at the front node and the back node. The voltage limiter limits level of the external signal transmitted to the front node, the level down shifter shifts down a signal of the front node by a cross voltage to generate a signal of the back node, and the inverter inverts the signal of the back node to generate the internal signal.

Output circuit and output control system

An output circuit which outputs an output signal based on an input signal from an output terminal and brings the output terminal into a high impedance state in response to an impedance control signal. The output circuit includes an output pMOS transistor connected at a source thereof to a first power supply. The output circuit includes an output nMOS transistor connected between a drain of the output pMOS transistor and ground. The output circuit includes an output terminal connected between the drain of the output pMOS transistor and a drain of the output nMOS transistor. The output circuit includes a first level shifter circuit which outputs a first gate control signal from a first gate control terminal to control on/off of the output pMOS transistor. The output circuit includes a second level shifter circuit which outputs a second gate control signal from a second gate control terminal to control on/off of the output nMOS transistor.

Output stage circuit for outputting a driving current varying with a process

An output stage circuit includes a first P-type metal-oxide-semiconductor transistor, a second P-type metal-oxide-semiconductor transistor, an N-type metal-oxide-semiconductor transistor, and a current source. A voltage of a third terminal of the first P-type metal-oxide-semiconductor transistor is a first voltage minus a voltage drop between a first terminal and a second terminal of the first P-type metal-oxide-semiconductor transistor. The N-type metal-oxide-semiconductor transistor is coupled between the third terminal of the first P-type metal-oxide-semiconductor transistor and the current source. A second terminal of the second P-type metal-oxide-semiconductor transistor is coupled to the third terminal of the first P-type metal-oxide-semiconductor transistor. When a second terminal of the N-type metal-oxide-semiconductor transistor receives a kick signal, a driving current flowing through the second P-type metal-oxide-semiconductor transistor is relevant to the voltage of the third terminal of the first P-type metal-oxide-semiconductor transistor.

Coupling Circuit, Driver Circuit and Method for Controlling a Coupling Circuit

A coupling circuit has a first and a second transistor (P 1, P 2 ) of a p-channel field-effect transistor type. A drain terminal of the first transistor (P 1 ) is connected to a signal input ( 1 ), source terminals of the first and the second transistor (P 1, P 2 ) are commonly connected to a signal output ( 2 ), bulk terminals of the first and the second transistor (P 1, P 2 ) are commonly connected to a drain terminal of the second transistor (P 2 ), and a gate terminal of the first transistor (P 1 ) is connected to a gate terminal of the second transistor (P 2 ). The coupling circuit further comprises a gate control circuit ( 10 ) with a charge pump circuit ( 110 ) which is configured to generate a negative potential. The gate control circuit ( 10 ) is configured to control a gate voltage at the gate terminals of the first and the second transistor (P 1, P 2 ) based on a negative potential.

Differential output buffer having mixing and output stages

An exemplary differential output buffer includes a mixing stage and an output stage. The mixing stage includes a mixing circuit that mixes a differential data signal and an inverted delayed differential data signal to generate a mixed differential data signal. The output stage includes a first and a second output stage differential pair of transistors. Sources of the transistors in each of the output stage differential pairs are commonly coupled. Gates of the transistors in the first and second output stage differential pairs are supplied with the differential data signal and the mixed differential data signal, respectively. Drains of corresponding ones of the transistors in the first and second output stage differential pairs are commonly connected to form output nodes to output an emphasized differential data signal. The mixing stage includes a mixing ratio setting circuit that sets the mixing ratio to one of 1:0, 1:1, and 0:1.

Input circuit

The first input circuit detects an input signal to output a first output signal having the same phase as the input signal. The second input circuit is configured to detect a first strobe signal to output a second output signal. The third input circuit is configured to detect a second strobe signal as a reversed signal of the first strobe signal to output a third output signal. A data latch circuit includes a first latch circuit and a second latch circuit. It is configured to latch the first output signal in either one of the first latch circuit or the second latch circuit according to the first output signal, the second output signal and the third output signal. It also allows the other one of the first latch circuit or the second latch circuit to input the first output signal thereto.

High definition multimedia interface (hdmi) apparatus including termination circuit

A termination circuit for a HDMI transmitter includes a bias unit and a termination resistor unit connected in parallel between a positive transmission pin and a negative transmission pin. The bias unit generates a bias voltage by selecting the higher voltage among a first voltage received through the positive transmission pin and a second voltage received through the negative transmission pin. The termination resistor unit is formed on a well region biased by the bias voltage, and conditionally provides a termination resistance between the positive transmission pin and the negative transmission pin in response to a termination resistor control signal. The termination circuit conditionally provides a termination resistance without a leakage current. The termination resistance may be varied by using an n-bit control code.

Clamping circuit to a reference voltage for ultrasound applications

A clamping circuit includes a clamping core connected to an output terminal and having a central node connected to a voltage reference and at least one first and one second clamp transistor, connected to the central node and having respective control terminals, the clamping core being also connected at the input to a low voltage input driver block. The clamping core includes a first switching off transistor connected to the output terminal and to the first clamp transistor, as well as a second switching off transistor connected to the output terminal and to the second clamp transistor.

Controller

This invention relates to a controller, more particularly, to a controller for driving a power transistor for obtaining improving impedance matching. An embodiment of a flow chart is revealed for the operation of the controller. The controller has frequency modulation capability with Lenz current of a loop linking to the driven power transistor to function with, Miller effect cancelling capability to its driven power transistor and fault detecting capability by detecting the absence of a Lenz current of a loop linking to the driven power transistor to function with.

Level shifter and method of using the same

A level shifter and a method of operating a level shifter are provided. The level shifter includes a first-level shifter unit configured to convert an external input signal into a signal in a preset first-voltage range using a plurality of transistors and output the converted signal and a second-level shifter unit configured to convert the signal output from the first-level shifter unit into a signal in a preset second-voltage range using a plurality of transistors and output the converted signal.

Level shift circuit

A level shift circuit of the invention includes a CMOS inverter circuit that receives an input pulse signal having a crest value of a first potential, a latch circuit that operates on a power supply of a second potential which is higher than the first potential, and a power supply circuit that supplies a power supply of not less than the first potential and less than the second potential to the CMOS inverter circuit. The latch circuit has one end thereof connected to an output end of the CMOS inverter circuit and outputs from the other end thereof an output pulse signal having a crest value of the second potential and a same phase as the input pulse signal. The power supply circuit functions to limit the power supply when the input pulse signal assumes at least the ground level.

Clock Integrated Circuit

The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.

Current-Mode Active Termination

Embodiments of the present invention, as further described below, provide active termination circuits that can be used with power transmitter circuits. Embodiments reduce power loss due to impedance matching and increase power efficiency in power transmitter circuits. In particular, embodiments provide active termination circuits that can be configured to draw minimal amounts of the output current generated by the power transmitter circuits. At the same time, embodiments achieve optimal impedance matching, thus enabling optimal power transfer to the load. Further, embodiments can be controlled adaptively in real time to reduce parasitic effects on power transfer and to optimize impedance matching. Embodiments can be implemented using various transistor technologies (e.g., MOSFET, BJT, etc.), and can be used with a variety of power transmitter circuits, including, for example, power DACs, analog/digital RF transmitters, and analog/digital PAs.

Integrated Circuit With an Adaptable Contact Pad Reconfiguring Architecture

An apparatus and method are disclosed for providing test mode contact pad reconfigurations that expose individual internal functional modules or block groups in an integrated circuit for testing and for monitoring. A plurality of switches between each functional module switches between passing internal signals among the blocks and passing in/out signals external to the block when one or more contact pads are strapped to input a pre-determined value. Another set of switches between the functional modules and input/output contact pads switch between functional inputs to and from the functional modules and monitored signals or input/output test signals according to the selected mode of operation.

Output circuit

An output circuit includes first to fourth transistors, first and second constant current units, and a differential pain The gates of the first and second transistors are supplied with two input signals, respectively. The drain of the first transistor is coupled to the drain of the third transistor and the gate of the fourth transistor. The drain of the second transistor is coupled to the gate of the third transistor and the drain of the fourth transistor. The first constant current unit is coupled to the sources of the third and fourth transistors. The differential pair includes two transistors, and the gates of the two transistors are coupled to the drains of the first and second transistors, respectively. The second constant current unit is coupled to the sources of the two transistors. Two output signals are output from two nodes respectively corresponding to the drains of the two transistors.

Semiconductor device

A semiconductor device includes a code generator configured to generate a supplementary code with a value changing in response to a variation of an impedance code, a main driver configured to receive an output data and drive the received output data to a data output pad, wherein a driving force of the main driver is controlled according to the impedance code, and an auxiliary driver configured to receive the output data and drive the received output data to the data output pad, wherein a driving force of the auxiliary driver is controlled according to the supplementary code.

Device

A semiconductor device has a first controlled chip, including a first replica output circuit having the same configuration as a first output circuit, a first ZQ terminal connected to the first replica output circuit, a first through electrode connected to the first ZQ terminal, and a first control circuit which sets the impedance of the first replica output circuit. A control chip includes a second ZQ terminal connected to the first through electrode, a comparator circuit which compares a voltage of the second ZQ terminal with a reference voltage, and a second control circuit 123 which performs a process based on a comparison by the comparator circuit. The first control circuit and the second control circuit receive a common input signal to operate and sequentially change and set the impedance until the comparison result changes when an external resistance element is connected to the second ZQ terminal.

Cml to cmos conversion circuit

The present invention provides a CML to CMOS conversion circuit comprising a first differential unit, a second differential unit, and an output unit. The output unit comprises a series connection of a first inverter and a second inverter, wherein, a resistor is connected with the first inverter in parallel. The CML to CMOS conversion circuit of the present invention omits the amplifier in the conventional circuit and reduces the delay time to 34 ps, which is almost half of the delay time of 64 ps in the conventional circuit, and thus provides more clock delay redundancy for the high speed parallel-serial conversion circuit.

Output driver, devices having the same, and ground termination

An integrated circuit comprising an output driver including an output terminal, and a receiving circuit including a termination resistor connected between the output terminal and a ground. The output driver comprising a first NMOS transistor configured to pull up a voltage of the output terminal to a pull-up voltage in response to a pull-up signal, and a second NMOS transistor configured to pull down the output terminal to a ground voltage in response to a pull-down signal.

Voltage switch circuit

A voltage switch circuit uses PMOS transistors to withstand high voltage stress. Consequently, the NMOS transistors are not subject to high voltage stress. The lightly-doped PMOS transistors are compatible with a logic circuit manufacturing process. Consequently, the voltage switch circuit may be produced by a logic circuit manufacturing process.

Output buffer, operating method thereof and devices including the same

A method of buffering data from core circuitry includes generating a first sourcing control signal responsive to indication signals indicating an operating voltage and output data, generating a second sourcing control signal responsive to the indication signals, and applying the operating voltage to an output terminal in response to the first sourcing control signal and the second sourcing control signal. The first sourcing control signal swings between the operating voltage and a reference voltage. The reference voltage is a signal selected from among a plurality of internal voltages in response to selection signals generated as a result of decoding the indication signals.

DRIVING CIRCUIT WITH ZERO CURRENT SHUTDOWN AND A DRIVING METHOD THEREOF

Methods and circuits related to a driving circuit with zero current shutdown are disclosed. In one embodiment, a driving circuit with zero current shutdown can include: a linear regulating circuit that receives an input voltage source, and outputs an output voltage; a start-up circuit having a threshold voltage, the start-up circuit receiving an external enable signal; a first power switch receiving both the output voltage of the linear regulating circuit and the external enable signal, and that generates an internal enable signal, the internal enable signal being configured to drive a logic circuit; when the external enable signal is lower than a threshold voltage, the driving circuit is not effective; when the external enable signal is higher than the threshold voltage, the start-up circuit outputs a first current; and where the output voltage at the first output terminal is generated by the linear regulating circuit based on the first current. 1. A driving circuit comprising:a) a linear regulating circuit configured to receive an input voltage source, and to provide an output voltage based on a first current;c) a first power switch configured to receive said output voltage of said linear regulating circuit and an external enable signal, and to generate an internal enable signal configured to drive a logic circuit; andd) a start-up circuit configured to receive said external enable signal at a gate of a second power switch, wherein when said external enable signal is lower than a threshold voltage that is related to said second power switch, said start-up circuit is configured to disable said first current and said driving circuit, and when said external enable signal is higher than said threshold voltage, said start-up circuit is configured to a generate said first current and enable said driving circuit.2. The driving circuit of claim 1 , further comprising a first current mirror coupled to said input voltage source claim 1 , said linear regulating circuit claim ...

Power-up signal generation circuit

A power-up signal generation circuit includes a fixed level transition voltage generation unit, a variable level transition voltage generation unit, a comparison unit, and a selective output unit. The fixed level transition voltage generation unit is configured to generate a fixed level transition voltage changing at a constant level of an external voltage. The variable level transition voltage generation unit is configured to generate a variable level transition voltage changing at a level of an external voltage which varies depending on temperature. The comparison unit is configured to compare the level of the fixed level transition voltage with the level of the variable level transition voltage, and generate a selection signal. The selective output unit is configured to output the fixed level transition voltage or the variable level transition voltage as a power-up signal in response to the selection signal.

SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME

A device including first and second semiconductor chips, each of first and second semiconductor chips including first to M-th penetration electrodes, M being an integer equal to or greater than 3, each of the first to M-th penetration electrodes penetrating through a semiconductor substrate, and the first semiconductor chip including a first input circuit coupled to the M-th penetration electrode of the first semiconductor chip at an input node thereof, the first and second semiconductor chips being stacked with each other in which the first to M-th penetration electrodes of the second semiconductor chip are vertically arranged respectively with the first to M-th penetration electrodes of the first semiconductor chip, in which the first to (M−2)-th penetration electrodes of the second semiconductor chip are electrically coupled to the second to (M−1)-th penetration electrodes of the first semiconductor chip, respectively. 1. A device comprising: a semiconductor substrate; and', 'first to M-th penetration electrodes, M being an integer equal to or greater than 3, each of the first to M-th penetration electrodes penetrating through the semiconductor substrate,, 'first and second semiconductor chips, each of the first and second semiconductor chips comprisingthe first semiconductor chip further comprising a first input circuit coupled to the M-th penetration electrode of the first semiconductor chip at an input node thereof,the first and second semiconductor chips being stacked with each other to provide a chip-stack structure in which the first to M-th penetration electrodes of the second semiconductor chip are vertically arranged respectively with the first to M-th penetration electrodes of the first semiconductor chip, in which the first to (M−2)-th penetration electrodes of the second semiconductor chip are electrically coupled to the second to (M−1)-th penetration electrodes of the first semiconductor chip, respectively, and in which the M-th penetration electrode ...

Adaptive termination

A system for receiving data is provided the system includes an inductive data device, such as a device that receives high-speed data over an inductive coupling. An adjustable impedance is coupled to the inductive data device, where the adjustable impedance is used for dynamically controlling ringing in the inductive data device, such as by damping ringing signals generated by circuit inductances or capacitances.

SEMICONDUCTOR DEVICE AND OPERATION METHOD THEREOF

A semiconductor device includes a clock delay unit configured to delay a source clock by a given delay amount and generate a delayed source clock, a driving signal generation unit configured to decide logic levels of first and second driving signals based on a value of input data, to select one of the source clock and the delayed source clock based on current logic levels of the first and second driving signals, which are detected based on the source clock, and to use a selected clock as a reference of an operation for determining next logic levels of the first and second driving signals, and an output pad driving unit configured to drive a data output pad with a first voltage in response to the first driving signal, and to drive the data output pad with a second voltage in response to the second driving signal. 1. A semiconductor device comprising:a clock delay unit configured to delay a source clock by a given delay amount and generate a delayed source clock;a driving signal generation unit configured to decide logic levels of a first driving signal and a second driving signal based on a value of input data, to select one of the source clock and the delayed source clock based on current logic levels of the first driving signal and the second driving signal, which are detected based on the source clock, and to use a selected clock as a reference of an operation for determining next logic levels of the first driving signal and the second driving signal; andan output pad driving unit configured to drive a data output pad with a first voltage in response to the first driving signal, and to drive the data output pad with a second voltage in response to the second driving signal.2. The semiconductor device of claim 1 , wherein the driving signal generation unit comprises:a first driving signal output section configured to decide the logic level of the first driving signal in response to the input data, to determine transition to a second logic level based on the source ...

Slew rate modulation

Apparatus and methods may operate so that arrival times of a data signal at gates of transistors are controlled to switch the transistors at different times to modulate the slew rate of a signal on a node. Additional embodiments are also described.

Boolean logic in a state machine lattice

Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.

Method and Apparatus for Facilitating Communication Between Programmable Logic Circuit and Application Specific Integrated Circuit with Clock Adjustment

A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain. 1. A data processing device , comprising:an application specific integrated circuit (“ASIC”) configured to perform a specific function in accordance with a first clock domain;a configurable logic circuit (“CLC”) coupled to the ASIC and configured to perform a programmable logic function in accordance with a second clock domain; anda phase adjustment circuit coupled with the CLC, and able to facilitate communication between the ASIC and the CLC in accordance with the first clock domain and the second clock domain.2. The device of claim 1 , wherein the ASIC is a semiconductor based integrated circuit that is customized for a particular functionality.3. The device of claim 1 , wherein the CLC is a semiconductor based field custom-programmable gate array (“cFPGA”) having a plurality of lookup tables (“LUTs”) and a plurality of nonvolatile programmable bits wherein the cFPGA is an integrated circuit able to be configured to one of user selected logic functions.4. The device of claim 3 , wherein the phase adjustment circuit is fabricated together with the cFPGA.5. The device of claim 3 , wherein the phase adjustment circuit includes a delay clock circuit configured to adjust a first clock in the first clock domain and adjust a second clock in the ...

LEVEL SHIFT CIRCUIT AND DRIVE CIRCUIT OF DISPLAY DEVICE

In a level shift circuit, input signals are input into gates of a first and a second MOS transistors whose sources are coupled to a first supply voltage VSS. Gates of a third and a fourth MOS transistors whose sources are coupled to a second supply voltage are coupled to drains of the second and the first MOS transistors. A first voltage generation circuit is coupled between the drains of the first and the third MOS transistors, and a second voltage generation circuit is coupled between the drains of the second and the fourth MOS transistors. The gate of the fifth MOS transistor is coupled to a connection node NDB, and the source of the fifth MOS transistor is coupled to the second supply voltage. 1. A level shift circuit comprising:a first MOS transistor of a first conductivity type, into a gate of which an input signal having an amplitude between a third supply voltage indicating a voltage between a first supply voltage and a second supply voltage and the first supply voltage is input;a second MOS transistor of the first conductivity type, into a gate of which an inverted input signal which is an inverted signal of the input signal, is input, sources of the first and the second MOS transistors being commonly coupled to the first supply voltage;a third MOS transistor of a second conductivity type complementary to the first conductivity type, whose gate is coupled to a drain of the second MOS transistor;a fourth MOS transistor of the second conductivity type, whose gate is coupled to a drain of the first MOS transistor, sources of the third and the fourth MOS transistors being commonly coupled to the second supply voltage;a first voltage generation circuit coupled between the drain of the first MOS transistor and a drain of the third MOS transistor;a second voltage generation circuit coupled between the drain of the second MOS transistor and a drain of the fourth MOS transistor;a fifth MOS transistor of the second conductivity type, whose gate is coupled to a ...

Switching circuit

A switching circuit suitable for a low power oscillator circuit includes control and output circuits, the control circuit arranged to control the output circuit, the control circuit having input and output terminals, the output circuit having input and output terminals and control terminals; wherein the input terminal of the control circuit is connected to the input terminal of the output circuit, and the control terminal of the output circuit is connected to the output terminal of the control circuit, the output circuit first switches connected in series and arranged such that in use at least one of the switches is in a low impedance state at any given time, and the control circuit has second switches connected in series and arranged such that in use at least one of the switches is in a low impedance state at any given time.

LEVEL SHIFTER, INVERTER CIRCUIT, AND SHIFT REGISTER

A level shifter includes: an input terminal to which an input voltage is applied; a capacitor; a first transistor provided between the input terminal and one of electrodes of the capacitor, and having a gate electrode connected to the other of the electrodes of the capacitor; a second transistor provided between the input terminal and the other electrode of the capacitor; a signal generating unit which generates a signal for switching the second transistor between conduction and non-conduction and supply the signal to the gate electrode of the second transistor, in a period when the input voltage is provided to the input terminal; and an output terminal for outputting a voltage at the other electrode of the capacitor which is level-shifted by a change in the second transistor to a non-conducting state in the period as an output voltage. 1. A level shifter comprising:an input terminal to which an input voltage is applied;a first capacitor;a first transistor having a source electrode and a drain electrode that are provided between the input terminal and one of electrodes of the first capacitor, and a gate electrode connected to the other of the electrodes of the first capacitor;a second transistor having a source electrode and a drain electrode that are provided between the input terminal and the other electrode of the first capacitor;a signal generating unit configured to generate a signal for switching the second transistor between conduction and non-conduction and supply the signal to the gate electrode of the second transistor; andan output terminal for outputting, in a period when the input voltage is provided to the input terminal, a voltage at the other electrode of the first capacitor which is level-shifted as an output voltage.2. The level shifter according to claim 1 ,wherein a voltage corresponding to the input voltage is charged in the first capacitor in a period when the input voltage is provided to the input terminal and when the second transistor is in ...

Output buffer circuit

There is provided an output buffer circuit which can reduce the time differences of the rise time and fall time of the output voltages of a differential output signal and, furthermore, can make the rise time and fall time match with a good precision. To the resistance elements R 1, R 2, PMOS transistors Tr 5, Tr 6 are connected in parallel. At this time, if designating the resistance components of the resistance elements R 1, R 2 as r 1 (Ω), r 2 (Ω), designating the resistance components of the PMOS transistors Tr 5, Tr 6 as rTr 5 (Ω) and rTr 6 (Ω), and designating the resistance component of the current source I 1 as rI 1 (Ω), the conditions of (r1//rTr5)=(r2//rI1) and (r2//rTr6)=(r1//rI1) are satisfied. Due to this, the time differences between the rise time and fall time of the output voltages can be reduced and, furthermore, the rise time and fall time can be made to precisely match.

Level shifters and integrated circuits thereof

An integrated circuit including a first level shifter configured to receive a first input signal and a first power supply signal, and to output a first output signal. The integrated circuit further includes a first inverter configured to receive the first output signal, and to output a first inverter signal. The integrated circuit further includes a second level shifter configured to receive a second input signal and a second power supply signal, and to output a second output signal, wherein a voltage level of the second power supply signal is different from a voltage level of the first power supply signal. The integrated circuit further includes a second inverter configure to receive the second output signal, and to output a second inverter signal. The integrated circuit further includes an output buffer configured to receive the first inverter signal and the second inverter signal, and to output a buffer output signal.

Slew-rate limited output driver with output-load sensing feedback loop

Output driver feedback circuitry is configured to sense an amount of output capacitance of an output pad and to adjust the strength of the output driver accordingly. The feedback circuitry adjusts the output driver within a single cycle. A chain of delay reference signals is generated by representative capacitive loads that replicate a range of actual output loads. Adjustments to the output driver are based on a comparison of the delay reference signals with output of the output driver.

3x input voltage tolerant device and circuit

A voltage tolerant input/output circuit coupled to an input/output pad, and is able to support a voltage overdrive operation of approximately twice an operational voltage, and have an input tolerance of approximately three times the operational voltage. The circuit includes a pull-up driver, a P-shield, an N-shield, a pull-down driver and a cross-control circuit. The pull-up driver is coupled to a power supply. The P-shield has an N-well and is coupled to the pull-up driver at a node C, and coupled to the input/output pad. An N-shield is also coupled to the input/output pad. A pull-down driver is coupled between ground and the N-shield at a node A. A cross-control circuit is configured to detect voltage at: the node A, the node C, and the input/output pad. The cross-control circuit is configured to output control signals to the P-shield and the N-shield based on the detected voltages.

TECHNIQUES FOR SWITCHING BETWEEN AC-COUPLED CONNECTIVITY AND DC-COUPLED CONNECTIVITY

A circuit for switching between an AC-coupled connectivity and DC-coupled connectivity of a multimedia interface. The circuit comprises a current source connected in series to a wire of the multimedia interface and a coupling capacitor; and a termination resistor connected to the current source and to the coupling capacitor, wherein the circuit is connected in series between a source line driver and a sink line receiver of the multimedia interface, wherein the source line driver supports both the AC-coupled connectivity and the DC-coupled connectivity and the sink line receiver supports any one of the AC-coupled connectivity and the DC-coupled connectivity, wherein the current source and the termination resistor allows the setting of voltage levels of signals received at the sink line receiver to voltage levels defined by the multimedia interface thereby to switch to the coupling connectivity type required by the multimedia interface at which the sink line receiver operates. 1. A circuit for switching between an AC-coupled connectivity and a DC-coupled connectivity of a multimedia interface , comprising:a first current source connected in series to a first wire of the multimedia interface and a first tap of a first coupling capacitor; anda first termination resistor connected to the first current source and to the first tap of the first coupling capacitor, wherein the circuit is connected in series between a source line driver and a sink line receiver of the multimedia interface, wherein the source line driver supports both the AC-coupled connectivity and the DC-coupled connectivity and the sink line receiver supports any one of the AC-coupled connectivity and the DC-coupled connectivity, thereby the circuit switches to the coupling connectivity type required by the multimedia interface at which the sink line receiver operates, wherein the sink line receiver is connected to the first tap of the first coupling capacitor and the source line driver is connected to a ...

RE-CONFIGURABLE MIXED-MODE INTEGRATED CIRCUIT ARCHITECTURE

An analog portion of a mixed-mode integrated circuit system includes a plurality of analog input cells, a plurality of analog output cells, and an interconnect array. The input cells are configured to program analog functions. The output cells are configured to provide Analog and digital outputs corresponding to the programmed analog functions. The interconnect array processes the programmed analog functions into signals indicative of the analog functions. The interconnect array selectively provides the signals to the plurality of analog output cells. 1. A mixed-mode integrated circuit system , comprising:a plurality of analog input cells configured to program analog functions;a plurality of analog output cells configured to provide digital and/or analog outputs corresponding to said programmed analog functions;an interconnect array to process said programmed analog functions into signals indicative of said analog functions, said interconnect array selectively providing said signals to said plurality of analog output cells; anda programmable digital portion.2. The system of claim 1 , further comprising:a voltage-to-current converter to convert said programmed analog functions from voltage to current prior to being directed to the interconnect array for processing.3. The system of claim 1 , further comprising:a current-to-voltage converter to convert said signals indicative of said analog functions from current to voltage prior to being directed to said plurality of analog output cells.4. The system of claim 1 , wherein said interconnect array is configured to enable mixing of one or more of said programmed analog functions into one analog output cell.5. The system of claim 1 , wherein said interconnect array is configured to enable splitting of one programmed analog function into one or more analog output cells.6. The system of claim 1 , wherein said interconnect array is configured in a matrix format to select between mixing of one or more of said programmed analog ...

LOGIC SIGNAL TRANSMISSION CIRCUIT WITH ISOLATION BARRIER

A logic signal transmission circuit includes a driving circuit, an isolation section, and a latch section. The driving circuit converts an input digital signal to a differential digital signal. The isolation section blocks direct current and passes the differential digital signal. The latch section has even numbers of inverters which are connected in a loop and output a logic signal by turning ON and OFF a power supply voltage in a complementary manner. An input impedance of the latch section is set so that when a logic level of the differential digital signal changes, a transient voltage inputted through the isolation section to the latch section changes across a threshold voltage of the latch section. When the transient voltage changes across the threshold voltage, a logic level of the logic signal changes. 1. A logic signal transmission circuit comprising:a driving circuit configured to convert an input digital signal to a differential signal pair having a first digital signal and a second digital signal;an isolation section configured to block direct current and to pass the differential signal pair, the isolation section including a first isolation barrier and a second isolation barrier, the first isolation barrier configured to pass the first digital signal, the second isolation barrier configured to pass the second digital signal; anda latch section including a first latch circuit connected to an output terminal of the first isolation barrier and a second latch circuit connected to an output terminal of the second isolation barrier, whereinthe first latch circuit has even numbers of first inverters which are connected in a first loop and configured to output a first logic signal by turning ON and OFF a power supply voltage in a complementary manner,a first input impedance of the first latch circuit is set so that when a logic level of the first digital signal changes, a first transient voltage inputted through the first isolation barrier to the first latch ...

BUFFER CIRCUIT FOR SEMICONDUCTOR DEVICE

A buffer circuit is provided which is insensitive to a duty distortion regardless of the change of operation environment. The buffer circuit includes a current mode logic buffer and a differential-to-single-ended converter. The differential-to-single-ended converter receives first and second differential output signals to generate a single ended output signal and is configured so that an internal control node of the differential-to-single-ended converter is controlled in a negative feedback method to maintain a constant duty ratio of the single ended output signal regardless of the change of operation environment. According to some embodiments, a duty distortion of the single ended output signal due to the change of operation environment such as a process, a voltage, a temperature, etc. is reduced or minimized and thereby performance of the buffer circuit is improved and operation reliability is improved. 1. A buffer circuit comprising:a first buffer configured to receive first and second input signals and to generate first and second differential output signals and a common output signal, the common output signal having a level between an upper level of the first differential output signal and a lower level of the second differential output signal;a second buffer configured to receive the first and second differential output signals and generate third and fourth differential output signals, wherein the third and fourth differential output signals are fed back to an internal control node of the second buffer to drive the third and fourth differential output signals from a first voltage level to a predetermined voltage level; andan inverter configured to receive the third differential output signal and generate an output signal.2. The buffer circuit of claim 1 , wherein the inverter is configured to generate the output signal in response to the common output signal or a voltage signal having a predetermined voltage level.3. The buffer circuit of claim 1 , wherein the ...

Method for semiconductor memory interface device with noise cancellation circuitry having phase and gain adjustments

A memory interface circuit is provided, comprising: a first signal output circuit configured to output a first signal via a first signal line to a first I/O terminal; a second signal output circuit configured to output a second signal via a second signal line to a second I/O terminal; and a noise cancellation circuit having at least one phase adjusting element and at least one gain adjusting element to reduce a noise signal induced on the second signal line due to the presence of the first signal on the first signal line, wherein the second signal line is disposed adjacent to the first signal line.

PROGRAMMABLE LOGIC SWITCH

One embodiment provides a programmable logic switch in which a first nonvolatile memory and a second nonvolatile memory are formed in the same well, and in which to change the first nonvolatile memory from an erased state to a written state and leave the second nonvolatile memory being in the erased state, a first write voltage is applied to a first line connected with gate electrodes of the first and second nonvolatile memories, a second write voltage is applied to a second line connected to a source in the first nonvolatile memory, and a third write voltage lower than the second write voltage is applied to a fourth line connected to a source of the second nonvolatile memory. 1. A programmable logic switch comprising: a first channel region provided between a first source and a first drain;', 'a first insulating film formed on the first channel region;', 'a first charge storage film formed on the first insulating film;', 'a second insulating film formed on the first charge storage film; and', 'a first gate electrode formed on the second insulating film;, 'a first nonvolatile memory having a second channel region provided between a second source and a second drain;', 'a third insulating film formed on the second channel region;', 'a second charge storage film formed on the third insulating film;', 'a fourth insulating film formed on the second charge storage film; and', 'a second gate electrode formed on the fourth insulating film;, 'a second nonvolatile memory havinga first line connected to the first gate electrode and to the second gate electrode;a second line connected to the first source;a third line connected to the first drain and to the second drain;a fourth line connected to the second source;a substrate electrode through which a substrate voltage is applied to a well, the first nonvolatile memory and the second nonvolatile memory being formed in the well;one or more first logic transistors connected to the third line, each first logic transistor being ...

Semiconductor integrated circuit

A semiconductor integrated circuit includes a bypass circuit that forms a bypass path under a low voltage condition, and the bypass circuit includes first and second bypass MOS transistors respectively placed between drains of first and second PMOS transistors and a ground voltage terminal, each transistor having a gate to which a second power supply voltage is applied, and third and fourth bypass MOS transistors respectively placed between the first and second bypass MOS transistors and the ground voltage terminal, each transistor controlled to be ON and OFF in accordance with an input signal and a voltage condition.

INPUT BUFFER

An input buffer includes a first amplification block, a second amplification block, and a buffer block. The first amplification block is configured to be driven by an external voltage, to differentially amplify an input signal and a reference voltage in response to a bias voltage, and to subsequently generate first and second differential signals. The second amplification block is configured to be driven by an internal voltage, to differentially amplify the first and second differential signals, and to generate an output signal. The buffer block is configured to be driven by the internal voltage, to buffer the output signal, and to output an inverted output signal. 1. An input buffer comprising:a first amplification block configured to be driven by an external voltage and differentially amplify an input signal and a reference voltage in response to a bias voltage generated from the reference voltage, and generate first and second differential signals; anda second amplification block configured to be driven by an internal voltage and differentially amplify the first and second differential signals and generate an output signal.2. The input buffer of claim 1 , wherein the levels of the first and second differential signals are adjusted by the bias voltage.3. The input buffer of claim 1 , wherein the first amplification block comprises:a first switch unit configured to be turned on according to the bias voltage and control driving of a first node according to the external voltage; anda differential amplification unit coupled between the first node and a second node and configured to differentially amplify the input signal and the reference voltage and generate the first and second differential signals.4. The input buffer of claim 3 , wherein the differential amplification unit comprises:a load section coupled between the first node and a third node through which the first differential signal is outputted, and the load section coupled between the first node and a fourth ...

FLOATING GATE DRIVER WITH BETTER SAFE OPERATION AREA AND NOISE IMMUNITY, AND METHOD FOR LEVEL SHIFTING A SWITCH SIGNAL

A floating gate driver includes a level shifter to transmit a set signal and a reset signal to a first output terminal and a second output terminal, respectively. The level shifter includes a first high-voltage transistor, a first current limiter and a first input transistor connected in series between the first output terminal and a ground terminal, and a second high-voltage transistor, a second current limiter and a second input transistor connected in series between the second output terminal and the ground terminal, and the first and second high-voltage transistors are remained on. With this arrangement, the level shifter can transmit signals from low side to high side under better safe operating area and has better noise immunity. 1. A floating gate driver , comprising:an edge pulse generator detecting a rising edge and a falling edge of a switch signal to trigger a set signal and a reset signal, respectively;a level shifter having a first input transistor and a second input transistor connected to the edge pulse generator for transmitting the set signal and the reset signal to a first output terminal and a second output terminal to generate a first negative voltage pulse and a second negative voltage pulse, respectively; anda logic regeneration circuit connected to the first output terminal and the second output terminal, responsive to the first negative voltage pulse and the second negative voltage pulse to generate a signal as being level shifted from the switch signal; a first high-voltage transistor and a second high-voltage transistor connected to the first output terminal and the second output terminal, respectively, and remained on;', 'a first current limiter connected between the first high-voltage transistor and the first input transistor; and', 'a second current limiter connected between the second high-voltage transistor and the second input transistor., 'wherein the level shifter further comprises2. The floating gate driver of claim 1 , wherein ...

DELAY-INSENSITIVE ASYNCHRONOUS CIRCUIT

The asynchronous circuit includes a fork having at least two branches, each branch being connected to a logic gate so that the logic gate receives as input a branch-ending signal. It further includes a circuit for branching the branch-ending signal at the level of each logic gate to form a branched signal, and a blocking circuit comprising a Muller gate and receiving as input at least one branched signal, the blocking circuit being configured to prevent the propagation of an output signal when the branch-ending signals are in different logic states. 112-. (canceled)13. An asynchronous circuit comprising:a fork having at least two branches, each branch being connected to a logic gate so that the logic gate receives as input a branch-ending signal;a circuit for branching the branch-ending signal at the level of each logic gate to form a branched signal; anda blocking circuit comprising a Muller gate and receiving as input at least one branched signal, the blocking circuit being configured to prevent the propagation of an output signal when the branch-ending signals are in different logic states.14. The asynchronous circuit according to claim 13 , wherein the blocking circuit is separate from each logic gate.15. The asynchronous circuit according to claim 13 , wherein the blocking circuit receives all branch-ending signals claim 13 , one at least being branched by a branching circuit.16. The asynchronous circuit according to claim 15 , wherein the blocking circuit receives as input all the branched signals and a signal to be blocked claim 15 , the output signal being an acknowledgement signal.17. The asynchronous circuit according to claim 13 , comprising a blocking circuit for each logic gate claim 13 , each blocking circuit comprising a Muller gate and receiving as input the branched signal associated with the logic gate and a data signal to be blocked claim 13 , the output of the blocking circuit being connected to an input of the logic gate.18. The asynchronous ...

TRANSMISSION CIRCUIT

A transmission circuit includes a first drive part capable of switching to one of an on state that is driven by current and an off state, i.e., a high impedance state in accordance the value of a first input signal; and a first termination resistor part connected in series with the first drive part. The resistance values of the first drive part are switched in accordance with the state of the first drive part. 1. A transmission circuit comprising:a first drive part capable of switching to one of an on state that is driven by current and an off state, that is, a high impedance state in accordance the value of a first input signal; anda first termination resistor part connected in series with the first drive part and the resistance values of which are switched in accordance with the state of the first drive part.2. The transmission circuit according to the claim 1 , further comprising:a second drive part capable of switching to one of an on state that is driven by current and an off state, that is, a high impedance state in accordance the value of a second input signal and configured to enter the off state when the first drive part is in the on state and to enter the on state when the first drive part is in the off state; anda second termination resistor part connected in series with the second drive part and the resistance values of which are switched in accordance with the state of the second drive part.3. The transmission circuit according to claim 2 , whereinthe first termination resistor part has a first base resistor part and a first adjustment resistor part connected in parallel with the first base resistor part and the resistance values of which are switched in accordance with the state of the first drive part, andthe second termination resistor part has a second base resistor part and a second adjustment resistor part connected in parallel with the second base resistor part and the resistance values of which are switched in accordance with the state of the ...

Dual Path Level Shifter

Dual path level shifter methods and devices are described. The described level shifter devices can comprise voltage-to-current and current-to-voltage converters. 1. A dual path level shifter comprising:a dual path level shifter input terminal;a dual path level shifter output terminal;a first voltage-to-current converter;a second voltage-to-current converter;a third voltage-to-current converter;a first current-to-voltage converter; anda second current-to-voltage converter,wherein:in a first condition, during operation, an input signal having an input signal level swinging between an input signal low voltage level and an input signal high voltage level is routed from the dual path level shifter input terminal to an input of the first voltage-to-current-converter, from an output of the first voltage-to-current-converter to an input of the second current-to-voltage converter, from an output of the second current-to-voltage converter to an input of the third voltage-to-current converter, from an output of the third voltage-to-current converter to an input of the first current-to-voltage converter and from the output of the first current-to-voltage converter to the dual path level shifter output terminal;in a second condition, during operation, the input signal is routed from the dual path level shifter input terminal to an input of the second voltage-to-current converter, from an output of the second voltage-to-current converter to the input of the first current-to-voltage converter and from the output of first current-to-voltage converter to the dual path level shifter output terminal;during operation in the second condition, no current is flowing through an electrical path defined by the input signal routing of the first condition;the output signal is a replicate of the input signal swinging between an output signal low voltage level and an output signal high voltage level, so that the output signal low/high level is a shifted version of the input signal low/high level ...

INTERFACE CIRCUIT

According to an embodiment, an interface circuit is provided with an output buffer which generates an output waveform on the basis of the ON/OFF operation of a transistor and a driver circuit which drives the transistor and is capable of independently changing a turn-ON speed and a turn-OFF speed of the transistor. 1. An interface circuit comprising:an output buffer which generates an output waveform on the basis of the ON/OFF operation of a transistor; anda driver circuit which drives the transistor and is capable of independently changing a turn-ON speed and a turn-OFF speed of the transistor.2. The interface circuit according to claim 1 ,wherein the driver circuit is provided with a slew rate control unit which is capable of changing the turn-ON speed of the transistor, and a reset rate control unit which is capable of changing the turn-OFF speed of the transistor.3. The interface circuit according to claim 2 ,wherein the transistor is provided with a first P-channel field-effect transistor and a first N-channel field-effect transistor which is connected to the first P-channel field-effect transistor in series, andthe driver circuit is provided with a P-slew rate control unit which is capable of changing a turn-ON speed of the first P-channel field-effect transistor, a P-reset rate control unit which is capable of changing a turn-OFF speed of the first P-channel field-effect transistor, a N-slew rate control unit which is capable of changing a turn-ON speed of the first N-channel field-effect transistor, and a N-reset rate control unit which is capable of changing a turn-OFF speed of the first N-channel field-effect transistor.4. The interface circuit according to claim 3 , further comprising:a time lag generation circuit which adds a period of time in order to turn off both of the first P-channel field-effect transistor and the first N-channel field-effect transistor at the same time.5. The interface circuit according to claim 4 , further comprising:a level ...

SWITCHING ARRANGEMENT, INTEGRATED CIRCUIT COMPRISING SAME, METHOD OF CONTROLLING A SWITCHING ARRANGEMENT, AND RELATED COMPUTER PRORAM PRODUCT

There is disclosed a switching arrangement comprising a switch with a plurality of individually controllable elementary switches connected in parallel between a first supply rail and a second supply rail. Each of the elementary switches can be in either one of a closed state and an open state independently of the others. A controller is adapted to dynamically control the closing or opening of the elementary switches, depending on the intensity of a current flowing through the switch. The number of elementary switches in the closed state is variable. The higher is the intensity of the current, the higher the number of elementary switches in the closed state. Thus, the impedance of the switch decreases when the current increases, and vice versa, and the voltage drop across the switch may be kept substantially constant. 1. A switching arrangement , comprising:a switch comprising a plurality of individually controllable elementary switches connected in parallel between a first supply rail and a second supply rail, each of said elementary switches being in either one of a closed state and an open state independently of the others; and,a controller adapted to dynamically control the closing or opening of the elementary switches, depending on the intensity of a current flowing through the switch, wherein the number of elementary switches in the closed state is variable and wherein the higher is the intensity of the current the higher the number of elementary switches in the closed state.2. The switching arrangement of claim 1 , wherein the controller is further adapted to receive claim 1 , from a load supplied by the second supply rail claim 1 , a current value indication representative of the intensity of the current flowing through the switch claim 1 , and to control the closing or opening of the elementary switches responsive to said current value indication.3. The switching arrangement of claim 1 , wherein the controller comprises a current-sense block adapted to ...

LEVEL SHIFT CIRCUIT

Provided is a level shift circuit which includes: a first level shift module; a first signal input terminal for providing a first input signal for the first level shift module; a first signal output terminal for providing output from the first level shift module; a second level shift module; a second signal input terminal for providing a second input signal for the second level shift module; a second signal output terminal for providing output from the second level shift module; a drive module connected to the first signal output terminal and the second signal output terminal; and a drive signal output terminal from the drive module. The level shift circuit of the present invention can be applicable for the requirements of BCD process and prevent damages to the high-voltage device due to the excessively high gate voltage. 1. A level shift circuit , characterized in that , the level shift circuit comprising:a first level shift module;a first signal input terminal for providing a first input signal for the first level shift module;a first signal output terminal for providing output from the first level shift module;a second level shift module;a second signal input terminal for providing a second input signal for the second level shift module;a second signal output terminal for providing output from the second level shift module;a drive module connected to the first signal output terminal and the second signal output terminal; anda drive signal output terminal from the drive module;wherein, the first level shift module comprises:a first transistor having a gate connected to the first signal output terminal and a source connected to a low-voltage ground reference voltage source;a second transistor having a gate connected to its drain and a source connected to a high-voltage reference voltage source;a third transistor having a gate connected to the gate of the second transistor, a source connected to the high-voltage reference voltage source, and a drain connected to the ...

SEMICONDUCTOR DEVICE HAVING LEVEL SHIFTER

Disclosed herein is a semiconductor device that includes: an internal voltage generator configured to produce an internal voltage in a first mode and stop producing the internal voltage in a second mode; a level shifter configured to receive the internal voltage, a first voltage and a first signal, in order to convert the first signal from a voltage level of internal voltage to a voltage level of the first voltage and output the first signal with the voltage level of the first voltage; and a logic circuit configured to produce the first signal, the logic circuit being supplied with the internal voltage in the first mode and supplied with the first voltage in the second mode. 1. A semiconductor device comprising:a first circuit configured to generate, when a control signal is activated, an internal potential based on a first power-supply potential and to supply the internal potential to an internal node, and stops generating the internal potential when the control signal is inactivated;a second circuit configured to supply a second power-supply potential to the internal node when the control signal is inactivated; anda third circuit operating on a potential supplied from the internal node to generate an output signal, the third circuit being configured to maintain a logical level of the output signal when the potential supplied from the internal node is changed from the internal potential to the second power-supply potential.2. The semiconductor device as claimed in claim 1 , further comprising:a first terminal supplied with the first power-supply potential; anda second terminal supplied with the second power-supply potential,wherein the first power-supply potential and the second power-supply potential are different in potential level.3. The semiconductor device as claimed in claim 2 , wherein the first power-supply potential is higher than the second power-supply potential.4. The semiconductor device as claimed in claim 1 , wherein the first power-supply potential ...

ON-DIE SYSTEM AND METHOD FOR CONTROLLING TERMINATION IMPEDANCE OF MEMORY DEVICE DATA BUS TERMINALS

A system for controlling the termination impedance of memory device data bus terminals is fabricated on the same die as the memory device. The system includes a termination resistor connected to each data bus terminal, which is connected in parallel with several transistors that are selectively turned on to adjust the termination impedance. The transistors are controlled by a circuit that determines the resistance of the termination resistor and turns on the correct number of transistors to properly set the termination impedance. In one example, the resistance of the termination resistor is determined by measuring a resistor of the same type as the termination resistor. In another example, the resistance of the termination resistor is determined indirectly by measuring parameters that affect the resistance of the termination resistor. In either case, the system can maintain the termination impedance of the data bus terminals constant despite changes in the termination resistor. 1. A system comprising:an on-die termination (ODT) circuit coupled to an externally accessible terminal, wherein the ODT circuit is formed in a semiconductor die and is configured to control an impedance at the externally accessible terminal in accordance with digital activation signals; and a sensor configured to sense at least one of a temperature of the semiconductor die, a value of a supply supplied to the ODT circuit, or a resistance of the ODT circuit; and', 'control logic coupled to the sensor and configured to cause the digital activation signals to be provided, wherein the digital activation signals provided are based, at least in part, on data provided by the sensor., 'a termination resistance determining (TRD) circuit configured to provide the digital activation signals to the ODT circuit, the TRD circuit comprising2. The system of claim 1 , further comprising a plurality of ODT circuits claim 1 , each of the plurality of ODT circuits coupled to a different respective externally ...

Level shifter circuits capable of dealing with extreme input signal level voltage drops and compensating for device pvt variation

A level shifter circuit includes a level shifter unit and a first controlling unit. The level shifter unit has an input node for receiving an input signal having a predetermined level, an output node for outputting an output signal having a desired level and a complementary output node for outputting a complementary output signal complementary to the output signal. The first controlling unit is coupled to the level shifter unit and has a first transistor coupled between the complementary output node and a first control node for receiving a first control signal and a second transistor coupled between the input node for receiving the input signal and a ground.

Output driver, electrical device having the output driver, and method of evaluating the output driver

An output driver includes a data processing unit configured to perform a data processing on an input signal to generate processing result data; a D/A (Digital-to-Analog) conversion unit configured to apply D/A conversion on the processing result data to generate an analog signal; an output amplifier configured to amplify the analog signal to obtain an amplified analog signal as an output signal; a comparing unit configured to compare the processing result data with expected value data to obtain and output comparison result data; and an output control unit configured to select the comparison result data as the output signal instead of the amplified analog signal according to a comparison output selection signal.

Single power supply logic level shifter circuit

A system and method of shifting a data signal from a first voltage domain having a first logic level to a second voltage domain having a second logic level, the second logic level having a second logical high state greater than a first logical high state in the first logic level and a single power supply logic level shifter circuit having a single power supply source, an input node and an output node, the input node coupled to a sender circuit in the first voltage domain and the output node coupled to a receiver circuit in the second voltage domain, the single power supply source being coupled only to a single power grid in the second voltage domain.

SEMICONDUCTOR DEVICE HAVING CALIBRATION CIRCUIT THAT ADJUSTS IMPEDANCE OF OUTPUT BUFFER

Disclosed herein is a device that includes: a data terminal; an output buffer coupled to the data terminal, the output buffer including a first output unit having a plurality of first output transistors of a first conductivity type and a second output unit having a plurality of second output transistors of a second conductivity type; and a calibration circuit including a first code generation unit that generates a first control code that controls an impedance of the first output unit by performing a first calibration operation based on an impedance of a first reference unit and a second code generation unit that generates a second control code that controls an impedance of the second output unit by performing a second calibration operation based on an impedance of a second reference unit. The calibration circuit performs the first and second calibration operations in parallel. 1. A semiconductor device comprising:a data terminal;an output buffer coupled to the data terminal, the output buffer including a first output unit having a plurality of first output transistors of a first conductivity type and a second output unit having a plurality of second output transistors of a second conductivity type; anda calibration circuit including a first code generation unit that generates a first control code that controls an impedance of the first output unit by performing a first calibration operation based on an impedance of a first reference unit and a second code generation unit that generates a second control code that controls an impedance of the second output unit by performing a second calibration operation based on an impedance of a second reference unit,wherein the calibration circuit performs the first and second calibration operations in parallel.2. The semiconductor device as claimed in claim 1 , whereinthe calibration circuit further includes a replica power generation unit, andthe replica power generation unit supplies a first control signal to the first ...

PROGRAMMABLE HIGH-SPEED I/O INTERFACE

Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application. 1. An integrated circuit comprising:a differential input buffer having a first input coupled to a first pad and a second input coupled to a second pad;a first single-ended input buffer having an input coupled to the first pad;a second single-ended input buffer having an input coupled to the second pad;a first single-ended output buffer having an output coupled to the first pad;a second single-ended output buffer having an output coupled to the second pad;a serial-to-parallel converter having an input coupled to an output of the differential input buffer; anda parallel-to-serial converter having an output coupled to an input of the first single-ended output buffer.2. The integrated circuit of further comprising:a first output double data-rate register having an output coupled to the input of the first single-ended output buffer;a second output double data-rate register having an output coupled to the input of the second single-ended output buffer;a first tristate double data-rate register having an output coupled to an enable input ...

SIMULTANEOUS LVDS I/O SIGNALING METHOD AND APPARATUS

First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half. 1. A low voltage , differential signal circuit , comprising:A. a first low voltage differential signal lead;B. a second low voltage differential signal lead;C. a reference voltage lead;D. a first comparator having a non-inverting input connected to the first low voltage differential signal lead, an inverting input connected to the reference voltage lead, and an output;E. a second comparator having an inverting input connected to the second low voltage differential signal lead, a non-inverting input connected to the reference voltage lead, and an output; andF. an OR gate having one input connected to the output of the first comparator, another input connected to the output of the second comparator, and an output; andG. a multiplexer having a control input connected to the output of the OR gate.2. The circuit of in which the reference voltage is 250 millivolts.3. The circuit of in which the multiplexer has a first input coupled to an output signal lead claim 1 , and a second input coupled to the first and second low voltage differential signal leads through a comparator. This application is a divisional of prior application Ser. No. 13/196,355, filed Aug. 2, 2012, currently pending;Which was a divisional of prior application Ser. No. 12/892,261, filed Sep. 28, 2010, now ...

Buffering circuit, semiconductor device having the same, and methods thereof

A multipoint low-voltage differential signaling (mLVDS)receiver of a semiconductor device and a buffering circuit of a semiconductor device, includes: an even-number data buffering unit configured to: sample even-number data from input data, amplify and output the even-number data in a section in which a positive clock is activated, and latch the even-number data in a section in which the positive clock is inactivated, and an odd-number data buffering unit configured to: sample odd-number data from the input data, amplify and output the odd-number data in a section in which a negative clock is activated, and latch the odd-number data in a section in which the negative clock is inactivated.

ASYMMETRICAL BUS KEEPER

Various embodiments are described herein for an asymmetrical bus keeper circuit that provides asymmetrical drive towards one logic level. The asymmetrical bus keeper circuit comprises a first inverter stage having an input node and an output node, an asymmetrical inverter stage having an input node and an output node and a feedback stage with an input node and an output node. The input node of the asymmetrical inverter stage is connected to the output node of the first inverter stage. The input node of the feedback stage connected to the output node of the asymmetrical inverter stage and the output node of the feedback stage connected to the input node of the first inverter stage. The asymmetrical stage provides asymmetrical drive towards one logic level. 2. The asymmetrical bus keeper circuit of claim 1 , wherein the asymmetrical inverter stage is configured to provide the asymmetrical drive to a high logic level and the asymmetrical inverter stage comprises a single p-channel transistor wherein a gate of the p-channel transistor is connected to the input node of the asymmetrical inverter stage claim 1 , a source of the p-channel transistor is connected to a positive voltage supply level claim 1 , and a drain of the p-channel transistor is connected to the output node of the asymmetrical inverter stage.3. The asymmetrical bus keeper circuit of claim 1 , wherein the asymmetrical inverter stage is configured to provide the asymmetrical drive to a high logic level and the asymmetrical inverter stage comprises a p-channel transistor having a first drive and an n-channel transistor having a second drive claim 1 , the p-channel and n-channel transistors being oriented in an inverter configuration claim 1 , wherein the first drive is at least one order of magnitude larger than the second drive.4. The asymmetrical bus keeper circuit of claim 1 , wherein the asymmetrical inverter stage is configured to provide the asymmetrical drive to a low logic level and the asymmetrical ...

POWER STAGE

A power stage has a differential output stage driven by one or more buffer stages The buffer stages are implemented as high and low side buffers each of which is itself a differential buffer implemented using transistors formed in an isolated-well technology such as triple-well CMOS. 1. An apparatus , comprising:an input circuit configured and arranged to provide a drive signal in response to receiving an input voltage;a first set of isolation capacitive couplers provided with the drive signal from the input circuit;at least one differential buffer stage, having a high side buffer stage and a low side buffer stage, configured and arranged to receive the drive signal from the first set of isolation capacitive couplers; andan output stage, between a high voltage rail and a low voltage rail, configured and arranged to drive an isolation transformer through a second set of isolation capacitive couplers in response to the drive signal received from the at least one differential buffer stage.2. The apparatus of claim 1 , wherein the at least one differential buffer stage includes a first buffer stage having an inverting output that drives an inverting input of a second buffer stage.3. The apparatus of claim 1 , wherein the at least one differential buffer stage includes a self-biassing bias line connecting parallel ports of a first buffer stage and a second buffer stage and providing an intermediate voltage between the high side line and the low side line.4. The apparatus of claim 1 , wherein the input circuit is further configured and arranged between the low voltage rail and a digital power supply voltage.5. The apparatus of claim 1 , wherein the input circuit provides an input signal that includes a sinusoidal input voltage.6. The apparatus of claim 1 , wherein the at least one differential buffer stage includes a plurality of transistors which are each implemented with an isolated well.7. The apparatus of claim 1 , wherein the at least one differential buffer stage ...

System and method of controlling devices operating within different voltage ranges

Semiconductor devices, systems, and methods are disclosed to facilitate power management. A method includes operating a first voltage range island of a semiconductor device within a first voltage range. The first voltage range includes a first midpoint. The first voltage range is provided in part by a voltage source that includes a tracking voltage regulator. The method also includes operating a second voltage range island of the semiconductor device within a second voltage range. The second voltage range includes a second midpoint. The first voltage range is different than the second voltage range.

SIGNAL TRANSFER CIRCUIT

A signal transfer circuit includes a signal transfer unit configured to transfer an input signal applied to an input node to an output node in response to a control signal and a driving unit configured to drive an output signal of the output node to a level of the input signal in response to the control signal. 14-. (canceled)5. A signal transfer circuit comprising:a signal transfer unit configured to transfer an input signal applied to an input node to an output node in response to a control signal; anda driving unit configured to drive an output signal of the output node to a level of the input signal in response to the control signal,wherein the driving unit comprises:a pull-down driving section configured to pull down the output node when the input signal is at a logic low level in a period in which the control signal is activated.67-. (canceled)8. The signal transfer circuit of claim 5 , wherein the pull-down driving section comprises:a pull-down signal generation part configured to activate a pull-down signal when the input signal is at the logic low level in the period in which the control signal is activated; anda pull-down part configured to pull down the output node in a period in which the pull-down signal is activated.9. A flip-flop circuit comprising:a first pass gate configured to transfer an input signal applied to an input node to a first internal node in response to a control signal;a driving unit configured to drive a first signal of the first internal node to a level of the input signal in response to the control signal; anda signal output unit configured to store the first signal of the first internal node and invert the first signal of the first internal node to output an inverted signal to an output node in response to the control signal.10. The flip-flop circuit of claim 9 , wherein:the first pass gate is configured to transfer the input signal to the first internal node when the control signal is activated;the driving unit is configured to ...

Sensor Connection Circuit

A circuit for converting the state of a sensor into a signal interpretable by an electronic circuit, including: a comparator of the voltage level of an input terminal with respect to a reference level, the sensor being intended to be connected between a terminal of application of a first power supply voltage and the input terminal; a current-limiting element between said input terminal and the ground; and a switching element in series with the current source and intended to be controlled by a pulse train. 1. A sensor connection circuit comprising:an input node;an output node, the output node being sampled by an acquisition circuit;a comparator connected between the input node and the output node; anda switching element connected between the input node and a ground node, the switching element being controlled by a control signal, wherein the sampling of the output node is synchronized with the control signal.2. The sensor connection circuit of further comprising a level adapter connected between comparator and the output node.3. The sensor connection circuit of claim 1 , wherein the control signal has a duty cycle greater than 10%.4. The sensor connection circuit of claim 1 , wherein the comparator comprises two inputs claim 1 , a first input connected to the input node claim 1 , and a second input connected to a reference voltage.5. The sensor connection circuit of further comprising a current-limiting element connected in series with the switching element.6. The sensor connection circuit of claim 1 , wherein the acquisition circuit comprises a microcontroller.7. The sensor connection circuit of further comprising: a visual indicator; and', 'a second switching element, the second switching element connected in parallel with the visual indicator, the second switching element being controlled by an output of the comparator., 'an indicator circuit connected in series with the switching element, the indicator circuit comprising8. An integrated circuit comprising: an ...

MULTI-VALUED ON-DIE TERMINATION

An integrated circuit memory device stores a plurality of digital values that specify respective termination impedances. The memory device switchably couples respective sets of load elements to a data input/output (I/O) to apply the termination impedances specified by the digital values, including, applying a first termination impedance to the data I/O during an idle state of the memory device, applying a first one of two non-equal termination impedances to the data I/O while the memory device receives write data in a memory write operation and applying a second one of the two non-equal termination impedances to the data I/O while another memory device receives write data in a memory write operation. When outputting read data via the data I/O in a memory read operation, the memory device switchably couples to the data I/O at least a portion of the load elements included in the sets of load elements. 1. A method of operation within an integrated circuit memory device , the method comprising:storing a plurality of digital values that specify respective termination impedances; applying a first termination impedance to the data I/O during an idle state of the memory device, and', 'applying one of two non-equal termination impedances to the data I/O, including applying a first one of the non-equal termination impedances to the data I/O while the memory device receives write data in a memory write operation and applying a second one of the non-equal termination impedances to the data I/O while another memory device receives write data in a memory write operation; and, 'switchably coupling sets of load elements to a data input/output (I/O) to apply termination impedances specified by the digital values, wherein switchably coupling the sets of load elements to the data I/O includesoutputting read data via the data I/O in a memory read operation, wherein outputting read data includes switchably coupling to the data I/O at least a portion of the load elements included in the ...

Integrated driver and related method

A driver circuit may include a first node (VA), and a first circuit to generate on the first node (VA) an inverted replica of an input signal (VIN) during driver switching between a first supply voltage (Vdd 1 ) and ground, the inverted replica having a threshold voltage value based upon a reference voltage (Vref) greater than the first supply voltage (Vdd 1 ). The driver circuit may include a cascode stage (M 3 ) to be controlled by the reference voltage (Vref) and to be coupled between a second supply voltage (Vdd 2 ) and the first node, a delay circuit (D) to generate a delayed replica of the input signal (VIN), an amplifier, and a switching network (M 5, M 6 ) to couple a control terminal of an active load transistor (M 9 ) either to one of the reference voltage (Vref) or to ground, based upon the input signal (VIN).

Voltage compensated level-shifter

Described herein is a voltage compensated level-shifter with nearly constant duty cycle and matching rise and fall slopes of the output of the level-shifter, no meta-stability, and nearly constant propagation delay across power supply levels. The voltage compensated level-shifter comprises a first inverter to receive an input signal for level shifting from a first power supply level to a second power supply level, and to generate a first inverted signal, the first inverter operating on the first power supply level; a second inverter to receive the input signal and to generate a second inverted signal, the second inverter operating on the second power supply level; and a NOR logical gate to receive the first and second inverted signals and to generate an output signal, the NOR logical gate operating on the second power supply level, wherein the output signal is level shifted to the second power supply level.

Circuit Arrangements and Methods of Operating the Same

In various embodiments, a circuit arrangement may be provided. The circuit arrangement may include a level shifting stage configured to be coupled to a first reference voltage, the level shifting stage having an output node. The circuit arrangement may further include a first input electrode in electrical connection with the level shifting stage. The circuit arrangement may also include a second input electrode in electrical connection with the level shifting stage. The circuit arrangement may further include a load having a first end and a second end, the first end coupled to the level shifting stage and the second end for coupling to a second reference voltage. In addition, the circuit arrangement may include a bypass circuit element connected in parallel to the load. The bypass circuit element may be configured to allow current to flow through upon application of an external voltage for bypassing the load.

Bootstrap circuit

A bootstrap circuit includes an input terminal, an inverting input terminal, an output terminal, an inverting output terminal, a first sub-bootstrap circuit, a second sub-bootstrap circuit, and a charging path providing circuit. The first sub-bootstrap circuit includes a first bootstrap capacitor, a first charging path, a first discharging path, and a first high voltage providing path. The charging path providing circuit includes a third charging path. In response to a high voltage level inputted into the input terminal, the first charging path and the third charging path are turned on, the first bootstrap capacitor is charged to a capacitor voltage, and the first discharging path is turned on to discharge the output terminal. In response to a low voltage level inputted into the input terminal, a first superimposed voltage including the high voltage level and the capacitor voltage is provided to the output terminal.

Integrated circuit comprising at least one digital output port having an adjustable impedance, and corresponding adjustment method

An integrated circuit may include a digital output port including a buffer stage that includes subassemblies of MOSFET transistors. One subassembly may include two pull-up transistors having sources connected to a common high voltage, and having drains connected to a common node connected to the output terminal. Another subassembly may include pull-down transistors having sources connected to a common low voltage, and having drains connected to the common node. The pull-up and pull-down transistors are formed in a thin semiconductor layer of an FDSOI substrate. The substrate may include a thick semiconductor layer and an oxide layer separating the thin and thick semiconductor layers. Areas of the thick semiconductor layer facing the pull-up and pull-down transistors may be connected to a circuit configured to vary a threshold voltage of the pull-up and pull-down transistors.

On-package input/output clustered interface having full and half-duplex modes

An apparatus and system for controlling traffic on an on-chip network. Embodiments of the apparatus comprise single-ended transmission circuitry and single-ended receiving circuitry on a first chip for coupling with a second chip, the transmission circuitry having impedance matching and lacking equalization, the receiving circuitry lacking equalization, the transmission circuitry and the receiving circuitry having statically configurable features and organized in clusters, wherein the clusters have the same physical layer circuitry design for different configurations of the configurable features, the configurable features including half-duplex mode and full-duplex mode, wherein the first chip and the second chip are on the same package, and wherein a plurality of conductive lines for coupling the first chip with the second chip are matched.

INTERFACE IC AND MEMORY CARD INCLUDING THE SAME

A memory card includes a memory that stores data, a driver that transmits the data received from the memory, and at least one transmitter that transmits the data received from the driver to a receiver provided in an external main unit. The driver and the at least one transmitter are provided in a single IC (integrated circuit) chip and are not overlapped with each other in a planar view. 1. A memory card comprising:a memory that stores data;a driver that transmits the data received from the memory; andat least one transmitter that transmits the data received from the driver to a receiver provided in an external main unit,wherein the driver and the at least one transmitter are provided in a single IC (integrated circuit) chip and are not overlapped with each other in a planar view.2. The memory card according to claim 1 , wherein the at least one transmitter comprises a coil.3. The memory card according to claim 1 , wherein the at least one transmitter comprises a plurality of transmitters.4. The memory card according to claim 3 , wherein the plurality of transmitters transmit the data to the receiver alternately.5. The memory card according to claim 3 , wherein the plurality of transmitters transmit the data to the receiver randomly.6. The memory card according to claim 1 , further comprising a clock receiver that receives a clock signal from the external main unit.7. The memory card according to claim 6 , wherein a size of the at least one transmitter differs from a size of the clock receiver.8. The memory card according to claim 1 , further comprising an encrypting circuit that encrypts the data received from the memory and transmits the encrypted data to the driver.9. The memory card according to claim 8 , wherein the encrypting circuit is provided in the IC chip.10. The memory card according to claim 1 , wherein the memory is provided in the IC chip.11. The memory card according to claim 1 , wherein the data stored in the memory comprises a game software.12. An ...

SEMICONDUCTOR DEVICE BASED ON POWER GATING IN MULTILEVEL WIRING STRUCTURE

A semiconductor device includes: first and second circuit cell arrays extending in first direction; first and second power supply lines each extending in first direction and arranged over first circuit cell array, first power supply line being supplied with first power source voltage; third power supply line extending in first direction separately from second power supply line, arranged over second circuit cell array, and supplied with second power source voltage; first transistor coupled between second and third power supply lines; and first circuit arranged on first circuit cell array and operating on first and second power source voltages supplied from first and second power supply lines, respectively. 1. A device comprising: a first circuit cell array extending in a first direction,', 'a second circuit cell array extending in the first direction substantially in parallel to the first circuit cell array,', 'first and second power lines each of which extends in the first direction and arranged over the first circuit cell array,', 'third and fourth power lines each of which extends in the first direction and arranged over the second circuit cell array,', 'a first transistor coupled between the second and third power supply lines,', 'a plurality of first logic circuits arranged in the first cell array, each of the first logic circuits includes first and second power nodes coupled respectively to the first and second power lines,', 'a plurality of second logic circuits arranged in the second cell array, each of the second logic circuits includes third and fourth power nodes coupled respectively to the third and fourth power lines,', 'a first interconnection connecting an output node of a first one of the first logic circuits to an input node of a first one of the second logic circuits, and', 'a second interconnection connecting an output node of the first one of the second logic circuits to an input node of a second one of the first logic circuits., 'a circuit unit ...

SEMICONDUCTOR DEVICE HAVING FLOATING BODY TYPE TRANSISTOR

A semiconductor device includes a first circuit node supplied with a first signal changing between first and second logic levels, a second circuit node supplied with a second signal changing between the first and second logic levels, a third circuit node, a first transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the second and third circuit nodes, the first transistor being rendered conductive when the first signal is at the second logic level, a fourth circuit node supplied with a voltage level being close to or the same as the second logic level, and a second transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the third and fourth circuit nodes, the second transistor being rendered conductive when the first signal is at the first logic level. 1. A semiconductor device comprising:a first circuit node supplied with a first signal changing between first and second logic levels;a second circuit node supplied with a second signal changing between the first and second logic levels;a third circuit node;a first transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the second and third circuit nodes, the first transistor being rendered conductive when the first signal is at the second logic level;a fourth circuit node supplied with a voltage level being close to or the same as the second logic level; anda second transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the third and fourth circuit nodes, the second transistor being rendered conductive when the first signal is at the first logic level,the first transistor being configured as a floating body type in which a body between a source and a drain is in en electrically floating state.2. The semiconductor device as ...

INPUT CIRCUIT ARRANGEMENT, OUTPUT CIRCUIT ARRANGEMENT, AND SYSTEM HAVING AN INPUT CIRCUIT ARRANGEMENT AND AN OUTPUT CIRCUIT ARRANGEMENT

The invention relates to an input circuit arrangement (), which is designed for operation either in a first or a second operating mode (A, B) and comprises a connection () for supplying a connection signal (SWI) and a detection circuit (). The detection circuit () is coupled on the input side to the connection () and is designed to put the input circuit arrangement () into an operating mode from a group comprising the first and second operating modes (A, B) depending on the steepness of a change of the connection signal (SWI). 1. An input circuit arrangement , which is designed for operation either in a first or a second operating mode , the input circuit arrangement comprising:a connection for supplying a connection signal; anda detection circuit that is coupled on the input side to the connection and is designed to put the input circuit arrangement into an operating mode from a group comprising the first and second operating modes depending on a steepness of a change of the connection signal),wherein, in the first operating mode, via the connection, both data information and also clock information are supplied to the input circuit arrangement, and, in the second operating mode, the input circuit arrangement is designed to provide an input signal that corresponds to the connection signal.2. The input circuit arrangement according to claim 1 , wherein the detection circuit is designed to put the input circuit arrangement into a first operating mode if the steepness of the change of the connection signal is smaller than a predetermined value claim 1 , and to put the input circuit arrangement into the second operating mode if the steepness of the change of the connection signal is greater than the predetermined value.3. The input circuit arrangement according to or claim 1 , wherein the detection circuit is designed to put claim 1 , depending on the steepness of the falling edge of the connection signal claim 1 , the input circuit arrangement into an operating mode ...

ON-DIE TERMINATION

Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals. 1. A method of operating memory devices including first and second memory devices coupled in common to a signaling link , the method comprising:at the first memory device, applying a first termination load to the signaling link during a data communication on the signaling link, and asserting a termination control signal; andat the second memory device, in response to the termination control signal, applying a second termination load to the signaling link during the data communication.2. The method of further comprising enabling a first signaling current to flow via the signaling link while the first and second termination loads are coupled to the signaling link claim 1 , and wherein a first portion of the signaling current flows through the first termination load and a second portion of the signaling current flows through the second termination load.3. The method of wherein the first and second portions are substantially equal and sum to the first signaling current.4. The method of including maintaining state information on the first and second memory devices claim 1 , the state information including a first state responsive to detection of a write command to enable applying of the first termination load to the signaling link and to drive the termination control signal on an output of the memory device claim 1 , and a second state responsive to detection of a termination control signal asserted by another device on an input of the memory device to enable applying of the second termination load to the ...

APPARATUS FOR MIXED SIGNAL INTERFACE ACQUISITION CIRCUITRY AND ASSOCIATED METHODS

An integrated circuit (IC) includes a plurality of pads adapted to communicate signals with a circuit external to the IC, and a first mixed signal interface block coupled to a first pad in the plurality of pads, where the first mixed signal interface block is adapted to receive a first trigger signal from the circuit external to the IC and to provide a second trigger signal. The IC further includes a second mixed signal interface block coupled to a second pad in the plurality of pads, where the second mixed signal interface block is adapted to receive and track a first input signal from the circuit external to the IC in a first mode of operation of the IC. The second mixed signal interface block is further adapted to generate, in response to the second trigger signal, a first output signal based on the first input signal and to provide the first output signal to a digital core of the IC in a second mode of operation of the IC, where the power consumption of the IC is lower in the first mode of operation than in the second mode of operation. 1. An integrated circuit (IC) , comprising:a plurality of pads adapted to communicate signals with a circuit external to the IC;a first mixed signal interface block coupled to a first pad in the plurality of pads, the first mixed signal interface block adapted to receive a first trigger signal from the circuit external to the IC and to provide a second trigger signal; anda second mixed signal interface block coupled to a second pad in the plurality of pads, the second mixed signal interface block adapted to receive and track a first input signal from the circuit external to the IC in a first mode of operation of the IC, and to generate, in response to the second trigger signal, a first output signal based on the first input signal and to provide the first output signal to a digital core of the IC in a second mode of operation of the IC,wherein a power consumption of the IC is lower in the first mode of operation than in the ...