Impulsdifferenzzaehler aus ruhenden logischen Bausteinen

Gruppenwechselsperre mit zwei UEbertragungskanaelen fuer bidirektionale Impulszaehler

NAEHERUNGSEINSTELLMITTEL.

Schaltungsanordnung fuer eine Zaehlanordnung mit einer bistabilen Transistorschaltung

COUNT DISPLAY APPARATUS

... 1333856 Display systems IWATSU ELECTRIC CO Ltd 19 April 1971 [24 Feb 1970] 33903/72 Divided out of 1333855 Heading G4H In a display system in which the count in decimal counter stage DC1, DC2 (Fig. 1) is displayed in complementary form, counter stages DC2 . . . are incremented at a count of "1" in the immediately preceding counter stage. As described the binary coded decimal counts are decoded in decoders DEC1, DEC2, to pure decimal form and fed to the tens complement input of an associated display D1, D2. The input to the second counter DC2 is taken from a bistable FF1 set by a count of 1 in the first counter and reset by the overflow pulse from that counter. The arrangement ensures that although the complement of the number of input pulses is displayed a count of zero is displayed after a reset signal at input RE. The apparatus may be extended to any number of counting decades.

FLIP-FLOP STAGES

... 1345858 Bistable logic circuits VDO ADOLF SCHINDLING GmbH 27 Oct 1972 [9 Nov 1971] 49677/72 Heading H3P [Also in Division G4] The effects of interference voltages on a bistable 1 comprising four logic gates 5, 6, 7, 8, are reduced by introducing time constants 9, 10 into the cross-coupling of gates 5, 6, and relatively larger time constants 13, 14 into further feedback circuits from the outputs of gates 5, 6, to respective inputs of gates 8, 7. Four such bistables 1, 2, 3, 4, constitute a counter, and a further discrimination against noise is provided by a pulse shaper 12. This includes 1.p. filters 20, 21 and Schmitt triggers 18, 19 which drive a NAND gate 22. The gates used in the bistables are NAND gates. The time constants 13, 14 are preferably ten times those 9, 10. In operation, a 1 from an inverter 11 when NAND 22 output goes to 0 in response to an input 21, makes the inputs to NAND 7 all 1, the other two inputs being at 1 because of 1 from a NAND 16 and a 1 from NAND 6 output via ...

PULSE COUNTING SYSTEM

... 1367363 Counters WESTINGHOUSE ELECTRIC CORP 9 Aug 1971 [26 Aug 1970] 37280/71 Heading G4D Pulses, e.g. from watt-hour meters, are received by inputs P1-P1F and stored at P2- P2F. Interrogation devices P3-P3F are normally scanned at a constant rate until an active store is detected, when that store is reset and an output pulse delivered to bus B1. The output pulse operates a one-shot circuit X3 to close AND gate X1, so stopping the scanning for a time sufficient to enable a circuit 31 to operate the total demand meter DM. A pulse divider X5 may be used to scale down the output.

Article counting device

... 1,040,191. Counters. BROOKHIRST IGRANIC Ltd. Jan. 5, 1965 [Feb. 4, 1964], No. 399/65. Heading G4D. The leading edge of each newspaper 2 conveyed past a fixed arm 6 engages a tooth 28 to turn a magnetic rotor 26, movement of which energizes a magnetic pick-up 44 to activate a counter. Overthrow is prevented by a permanent magnet 52. In a modification, Fig. 5, overthrow is prevented by three magnets alternately poled in relation to the teeth of the rotor. This rotor operates a reed switch magnetically (Fig. 6, not shown).

Improvements relating to Electrical Signal Registering Arrangements

... 1,186,353. Storage circuits. ENGLISH ELECTRIC CO. Ltd. 4 July, 1967 [14 July, 1966], No. 27122/67. Heading G4H. A circuit arrangement for storing incoming signals on lead 14 (Fig. 1) in a second store 36 when the contents of a first store 10 are being read out to, for example, a printer 12 includes a control circuit 22 which enables a gate to the first register 10 when the printer is inoperative and enables a gate to the second register 36 when the printer is operating. In the embodiment described electrical pulses on lead 14 are normally fed through a gate 16 and an OR gate 18 to the counter 10. When the printer is operative the control circuit 22 enables a gate 30 so that the pulses on lead 14 are accumulated in the counter 36. When the printer next becomes inoperative the gate 16 is again enabled so that incoming pulses on lead 14 as well as being fed to the counter 10 are fed via a gate 42 (enabled when the counter 36 is storing a number other than one), a delay 46 and OR gate 18 to ...

Improvements in or relating to arrangements for the generation and counting of electrical impulses

... 650,435. Supply meters. GUNNING, P. F. Jan. 17, 1948, No. 1520. [Class 37] [Also in Group XIX] In an arrangement for generating electrical impulses in response to, e.g., the revolutions of an electric meter spindle, to facilitate the counting of such revolutions, a contact M1 is arranged to be connected alternately to potentials of opposite polarity, thus charging a condenser C1 in one direction or the other and sending an impulse to a relay 1A connected by a rectifier bridge RB1 to a point of neutral potential N. General operation. As shown, three contacts M and corresponding circuits are each associated with a kilowatt-hour meter (not shown) arranged to send an impulse to the relay 1A, 2A or 3A each time a given amount of energy is registered. A small quantity of energy (measured on meter 3) is to be subtracted from a larger quantity (measured on meters 1 and 2), e.g. for finding the net output of power-generating equipment. Relays 1A, 2A cause impulses to be sent to a relay X to operate ...

Improvements in or relating to vehicle distance measuring apparatus

... 1,020,081. Electric selective signalling. MASCHINENFABRIK OERLIKON. Nov. 6, 1962 [Nov. 7, 1961], No. 41994/62. Heading G4H. [Also in Division B7] Operation of a first monostable device resets a counter which is being fed with pulses and sets a bi-stable device to enable an AND-gate to pass a signal from the counter when it reaches a predetermined count, and when the counter reaches another predetermined count it resets the bi-stable device and triggers a second monostable device. In a railway vehicle, the first monostable device is operated manually and the pulses fed to the counter are produced by movement of the vehicle. Three lamps are energized through AND-gates (including the one above) to indicate different distances travelled after manual operation of the first monostable device. Triggering of the second monostable device (destination reached) actuates a bell, horn, main switch or brake valve. In a modification, opening of the dead-man's switch resets the counter and stops the train ...

Method and apparatus for controlling the frequency of a variable frequency oscillator

... 1129267 Frequency dividers AGA AB 14 Oct 1965 [28 Oct 1964] 43588/65 Headings G4D D7X D6C1 D6C2 and D6Y An oscillator 9 is set to operate at a multiple n of the frequency of a standard oscillator 12. The multiple n is made up of 2x + y, where x pulses pass through gate 3 and y pulses through gate 4, changeover from one gate to the other being effected first when the number x set up on switches 15 is attained by a counter 7 and changeover in the opposite direction when counter 7 reaches full capacity. Phase difference between the outputs of counter 7 and the standard oscillator 12 controls the oscillator 9 in known manner.

Improvements in or relating to Electric Signalling Systems

... 1,152,257. Selective signalling; counter. GENERAL ELECTRIC & ENGLISH ELECTRIC COMPANIES Ltd. 28 Nov., 1967 [30 Nov., 1966], No. 53593/66. Headings G4D and G4H. The angular position of a disc, carrying magnets 24, 25, Fig. 3, is digitized by an arrangement of four coils A, B, C, D, on ferrite cores, the inductance of each coil depending upon whether a magnet is adjacent to it or not. Adjacent to all the cores is a biasing magnet 23 which, by suitably positioning the working point on the permeability characteristic of the core, results in a larger change in inductance for a given strength of magnet 24 or 25 when it passes a core. Other arrangements of cores and magnets are described in the Specification. The state of each coil (i.e. whether its inductance is high or low) can be detected by arranging that each coil forms part of the resonant circuit of an oscillator. Alternatively, the coils could be coupled together (as in Fig. 4, not shown) and form part of a single oscillator. Each disc ...

Device for Counting Out A Zig-Zag Diagram

... 1198760 Electric selective signals KIENZLE APPARATE GmbH 10 Sept 1968 [14 Sept 1967] 42942/68 Headings G4D D7X D6Y D6C1 D6C2 D6L and D1D9E A device for evaluating a zig-zag line diagram Fig. 1 (not shown) in which the distance between two consecutive cusps represents one unit of measurement includes two scanning heads scanning the diagram along two parallel tracks the output signals from which are fed via conductors K1, K2 Fig. 3 to circuits 1, 11 controlling via a gate 11 a counter. In the embodiment described, the first pulse on input K1 derived from a photo-electric sensor at time a (Fig. 1) switches a bi-stable 5 to produce an output counting pulse at gate 11 and via leads B, C switches bi-stables 7, 8 which deliver positive signals on conductors D, E to bi-stable 6 which inhibits bi-stable 5. The next pulse on input K1 at time b switches bi-stable 6 which delivers a positive signal on conductor G to reset bi-stable 7 and switch bi-stables 71, 81 which via ...

A synchronizing circuit for controlling a counter circuit

... 932,222. Synchronizing counters. MONROE CALCULATING MACHINE CO. Oct. 24, 1961 [Nov. 9, 1960], No. 38016/61. Class 106 (1). A counting circuit is pulled into a desired synchronism by the application of pulses to gates controlled by the bi-stable circuits making up the counter. In the example shown a Gray-code counter comprises two stages D1, D2 with outputs D1, D11, D2, D21 which can be arranged in various ways, one of which is shown at 17, Fig. 2, to indicate a count. Gated clock pulses I1 are synchronous with normal clock pulses P except that one is missing whenever an external timing pulse I occurs. In the simple embodiment shown the absence of the pulses I1 has no effect on the counter if it is already in synchronism as in sequence A, Fig. 4, but causes the counter to skip one if not in synchronism. One, two, or three external timing pulses I will therefore bring sequence B, C or D into the desired synchronism. The invention is applicable to a magnetic ...

SWITCHING CONFIGURATION FOR THE DIGITAL PROCESSING OF POLYPHASE PULSE RATES OF A PULSE GENERATOR

ELECTRONIC UP/DOWN COUNTER

SCHALTUNGSANORDNUNG ZUR VERHINDERUNG DER KOINZIDENZ VON BEZUGSSIGNALIMPULSEN UND RUCKFUHRSIGNALIMPULSEN IN EINEM REGELSYSTEM

For switching configuration for the continuous representation of the respective relative deviation in the impulse number of two irregular (uncoded), arising next to each other, and at will trains of impulses are enough

Thyristor speedometer in ring counter arrangement, counting forwards and backwards

Mechanism for counting products of printering promoted along a promotion course to shed formation

DIGITAL COUNTER AVERAGING SYSTEM

SOLID STATE TOTALIZER

INTERVAL COUNTING CIRCUIT AND METHOD

Einrichtung zur Zählung und Messung von Stromimpulsen kurzer Dauer.

Einrichtung zur Ermittlung des Drehzahlverhältnisses an Maschinen mit mehreren, getrennt voneinander rotierenden Teilen

Elektro-optische Abtastvorrichtung

Einrichtung zur Zählung und Messung von Stromimpulsen kurzer Dauer.

Calculatrice électronique

Appareil d'enregistrement et de contrôle à impulsions

Impulsregistriergerät

Verfahren zur Bestimmung des Zeitintegrals des Produktes physikalischer Grössen und Einrichtung zur Durchführung dieses Verfahrens

Einrichtung zum Umformen von stochastisch verteilten Impulsen einer Impulsreihe in eine Impulsreihe mit vorgegebenen Mindestabständen

Einrichtung zum Messen von Längen mittels Impulszählung

Zählvorrichtung für gefaltete Papierbogen, insbesondere gefaltete Zeitungen

Auf magnetisierbare Körper und magnetische Felder ansprechende Vorrichtung und Verwendung derselben zum Zählen solcher Körper, beispielsweise der Zähne eines eisernen Zahnrades

Halbleiterthyratronzählwerk

Einrichtung zur fortlaufenden Subtraktion einer Impulsreihe von einer anderen

Schaltungsanordnung zum elektrischen Ablesen von impulsgesteuerten Zählwerken mit Ausgabekontakten

Mess- und Zählvorrichtung zum Summieren verschieden grosser Kolbenhübe

Elektronischer Impulsgeber für Fernzähleinrichtungen

Vorrichtung zur Gewinnung einer Impulsfolge

Compteur-décompteur à décades

Dispositif permettant de déterminer la différence entre le nombre de signaux électriques d'un premier type et le nombre de signaux électriques d'un second type, reçus par le dispositif

Anordnung zur Steuerung der Schlupffrequenz einer Asynchronmaschine

Schaltanordnung mit einem Stufenschalter

Impuls-Phasendiskriminator

Anordnung zum Auszählen eines zick-zack-förmigen Liniendiagramms

Dispositif de comptage à éléments bistables

Automatische Zählvorrichtung

Verfahren zum Summieren von Impulsen

PROCEDE ELECTRONIQUE DE COMPTAGE D'IMPULSIONS ET DISPOSITIF POUR SA MISE EN OEUVRE.

FLIPFLOP-SCHALTUNG.

DISPOSITIF DE COMPTAGE D'IMPULSIONS EMISES PAR UN DISPOSITIF DE MESURE DE PARCOURS.

Impulsuntersetzer

Apparat zur Untersuchung von in einer Flüssigkeit suspendierten Teilchen

Fernzählwerk, insbesondere zur Zählung elektrischer Energie

Vorwärts-Rückwärts-Zählwerk

Dispositif d'emmagasinage de signaux électriques

Weg-Messvorrichtung und deren Verwendung zur Steuerung einer Werkzeugmaschine

Einrichtung mit einer photoelektrischen Vorrichtung für das Anzeigen des Durchganges eines Gegenstandes durch eine Kontrollebene

Elektronische Schaltungsanordnung zum Steuern oder Regeln oder Zählen

Fadeneinlaufgeschwindigkeits-Abfragevorrichtung an Strick- und Wirkmaschinen

Regelanordnung mit wenigstens einem Regelkreis, mit frequenz- und zeitproportionalen Signalen

Regelanordnung mit wenigstens einem Regelkreis, mit frequenz- und zeitproportionalen Signalen

Impulszähler für Wechselstrom

Summiereinrichtung für mehrere Summanden

Einrichtung zur zeitlichen Trennung zweier koinzidenter Impulse

Dispositif de contrôle du passage d'organes en mouvement

Installation pour accumuler et transmettre des impulsions

Impuls-Zählvorrichtung

Empfangseinrichtung mit mechanischem Zählwerk für registrierende Fernzählgeräte

Schaltungsanordnung zum wahlweisen Anschalten wenigstens zweier Eingänge an eine wenigstens einen Vorbereitungs- und einen Auslöseeingang aufweisende Zählstufe

Regelanordnung zum Ansprechen auf frequenz- und zeitproportionale Signale

Einrichtung zum Zählen von längs einer Förderbahn in Schuppenformation geförderten Druckereierzeugnissen

Einrichtung zum Bilden der Summe von an mehreren Messstellen als Impulse auftretenden Messwerten

Schaltungsanordnung für elektronische Zähleinrichtung

Dispositif d'enregistrement de signaux électriques d'entrée successifs

Koinzidenzgatteranordnung zum Unterdrücken zeitlich sich überschneidender Impulse

Vor-Rückwärts-Zählanordnung

Einrichtung zum Addieren zweier Impulsfolgen

Verfahren zur Sicherstellung der gleichen Reihenfolge der auf Eingangsleitungen ankommenden Impulse mit der Reihenfolge ihrer Zuführung zu einem elektronischen Vor-Rückwärtszähler, wobei die genannten Impulse in dem Vor-Rückwärtszähler vorausgehenden Speichern zwischengespeichert werden und Schaltung zur Durchführung des Verfahrens

ELEKTRONISCHE LEERWEGKUPPLUNG MIT FREILAUF FUER ELEKTRONISCHE SUMMENFERNZAEHLGERAETE MIT POSITIVEN UND NEGATIVEN SUMMANDEN.

PROCEDE ET APPAREIL PERMETTANT D'OBTENIR A CHAQUE INSTANT LA MOYENNE DU NOMBRE DE SIGNAUX RECUS D'UNE SOURCE BIDIRECTIONNELLE.

DEVICE FOR DETECTING A QUANTITY OF ENERGY SUPPLIED TO A PHASE BODY AND ITS USE FOR DETECTING IMPACTS HITTING A TARGET.

Recording device of impulses

Process of remote sensing of metal masses, in particular of motor vehicles, and device for its use

Pulse counting circuit - using a Geiger-Muller detector with time base varying with pulse input frequency

Device of measurement of distances to teleindicator

Improvements with the circuits of comparison of frequencies

Electronic amplifier of impulses of counting and order intended for automatic plays

COUNTER CONTROL CIRCUIT FOR AN ANALOG TO DIGITAL CONVERTER

Semiconductor device

A stop of a detection object clock is detected by inverting a signal level of an output signal of a level output unit at a count completion time at a counter unit operated by a detection clock and of which count value is changeable, and by determining whether or not a signal level change passes through a clock detection unit operated by the detection object clock by comparing signal levels of an output signal of a level output unit and an output signal of a clock detection unit.

Counting device and counting method

A counter counts the run lengths of a binarized signal. A counting result correcting portion generates frequency distributions for run lengths for first run lengths, which are from a rising edge to a falling edge of the signal, and second run lengths, which are for a falling edge to a rising edge of the signal, calculates a total number of first run lengths of lengths that are no less than 0 times and less than 1 times a representative value for the first run lengths, calculates a total number of second run lengths of lengths that are no less than 0 times and less than 1 times a representative value for the second run lengths, calculates a total number of first run lengths, calculates a total number of second run lengths, and corrects the counting results.

INPUT CIRCUIT IN HIGH SPEED COUNTER MODULE IN PLC

An input circuit in high speed counter module for PLC is provided, the input circuit being configured such that various types of pulse signals are changed to a single type of pulse signal and transmitted to an MPU, whereby the type of input pulse is checked or an operation of checking addition/deduction is omitted to increase an interrupt process speed. 1. An input circuit in high speed counter module for PLC configured to input a pulse to an MPU , the input circuit comprising: a first multi-vibrator generating a pulse by detecting rising and falling edges of a first contact input; a second multi-vibrator generating a pulse by detecting rising and falling edges of a second contact input; a first buffer outputting an output of the first multi-vibrator in 3-state; a second buffer outputting an output of the second multi-vibrator in 3-state; a first multiplexer (MUX) outputting any one of an EX-OR signal of the first and second contact inputs and a reverse signal of the EX-OR signal; a second MUX outputting any one of an output of the first MUX and the second contact input; and a first switch outputting outputs of the first and second buffers as a first phase input or a second phase input.2. The input circuit of claim 1 , wherein the first and second contact inputs are any one signal of a 1-phase/2-input/1-multiplication mode claim 1 , a 1-phase/2-input/2-multiplication mode claim 1 , a 2-phase/1-multiplication mode claim 1 , a 2-phase/2-multiplication mode claim 1 , a 2-phase/4-multiplication mode claim 1 , and a CW/CCW mode.3. The input circuit of claim 1 , further comprising a second switch that switches by receiving LOW and HIGH signals.4. The input circuit of claim 3 , wherein the second switch receives the second contact input as a selection signal claim 3 , and receives a ‘LOW at a 1-phase/1-multiplication’ as a control signal.5. The input circuit of claim 4 , wherein the first multi-vibrator receives an output of the second switch as a control signal.6. The ...

HIGH SPEED COUNTER APPARATUS

Disclosed is a high speed counter apparatus. The high speed counter apparatus includes a first counter configured to perform a count on the lower bits of the final output signal in response to a first clock signal, a second counter configured to perform a count on the upper bits of the final output signal in response to a second clock signal, and a clock signal generator configured to generate the second clock signal from the first clock signal. In accordance with the present invention, power consumption and a bottleneck phenomenon in an upper bit counter can be reduced because a second clock signal for operating the upper bit counter is synchronized with a first clock signal for operating the lower bit counter at a frequency lower than that of the clock signal for operating the lower bit counter. 1. A high speed counter apparatus , comprising:a first counter configured to perform a count on lower bits of a final output signal in response to a first clock signal;a second counter configured to perform a count on upper bits of the final output signal in response to a second clock signal; anda clock signal generator configured to generate the second clock signal from the first clock signal.2. The high speed counter apparatus of claim 1 , wherein the second clock signal is synchronized with the first clock signal at a frequency lower than a frequency of the first clock signal.3. The high speed counter apparatus of claim 1 , wherein the lower bits are 2 bits.4. The high speed counter apparatus of claim 3 , wherein the second clock signal is synchronized with the first clock signal at a frequency that is a quarter of a frequency of the first clock signal.5. The high speed counter apparatus of claim 1 , wherein the first counter operates as a toggle incrementer.6. The high speed counter apparatus of claim 5 , wherein the first counter comprises one or more D flip-flops configured in a toggle manner.7. The high speed counter apparatus of claim 1 , wherein the second counter ...

Processing apparatus and valve operation checking method

A processing apparatus includes a processing chamber configured to accommodate a target object to be processed, gas supply paths provided in a corresponding relationship with the kinds of process gases supplied into the processing chamber, and valves respectively arranged in the gas supply paths to open and close the gas supply paths. The processing apparatus further includes valve drive units configured to independently drive the valves, sensor units configured to independently monitor opening and closing operations of the valves, and a control unit configured to determine operation statuses of the valves based on valve opening and closing drive signals transmitted to the valve drive units and/or valve opening and closing detection signals transmitted from the sensor units.

THRESHOLD VOLTAGE AND DELAY TIME SETTING CIRCUIT, AND BATTERY MANAGEMENT SYSTEM INCLUDING THE SAME

The present invention relates to a threshold voltage and delay time setting circuit, and a battery management system including the same. The setting circuit is connected to a set resistor and a set capacitor through a pin. The setting circuit includes a threshold voltage setter for setting a threshold voltage according to resistance of the set resistor, and a delay setter for determining a count frequency according to capacitance of the set capacitor and setting a delay time according to the determined count frequency. 1. A setting circuit connected to a set resistor and a set capacitor through a pin , comprising:a threshold voltage setter for setting a threshold voltage according to a resistance of the set resistor; anda delay setter for determining a count frequency according to a capacitance of the set capacitor and setting a delay time according to the count frequency.2. The setting circuit of claim 1 , wherein the threshold voltage setter supplies a set current to the set resistor and uses a dependent current following the set current to set the threshold voltage.3. The setting circuit of claim 2 , wherein the threshold voltage setter sums currents of a plurality of selected sink current sources selected from among a plurality of sink current sources to generate a summed sink current according to a result of comparing a set voltage generated from the dependent current and a plurality of reference voltages claim 2 , and sets the threshold voltage according to the summed sink current.4. The setting circuit of claim 3 , wherein the threshold voltage setter includes:a plurality of voltage comparators including a first input terminal for receiving the set voltage and a second input terminal for receiving a corresponding reference voltage from among the plurality of reference voltages;a plurality of SR latches for maintaining outputs of the voltage comparators, and generating a plurality of output signals according to the outputs of the voltage comparators; anda ...

RF LOGIC DIVIDER

An apparatus is provided. Latches are coupled in series with one another in a ring configuration. Each latch includes a tri-state inverter, a first resistor-capacitor (RC) network, and a second RC network. The tri-state inverter has a first clock terminal and a second clock terminal. The first RC network is coupled to the first clock terminal. The second RC network is coupled to the second clock terminal. A biasing network is also provided. The biasing network has a first bias voltage generator that is coupled to the first RC network for each latch and a second bias voltage generator that is coupled to the second RC network for each latch. 1. An apparatus comprising: a tri-state inverter with a first clock terminal and a second clock terminal;', 'a first resistor-capacitor (RC) network that is coupled to the first clock terminal; and', 'a second RC network that is coupled to the second clock terminal; and', 'a biasing network having:', 'a first bias voltage generator that is coupled to the first RC network for each latch; and', 'a second bias voltage generator that is coupled to the second RC network for each latch., 'a plurality of latches coupled in series with one another in a ring configuration, wherein each latch includeswherein the first RC network further comprises:a capacitor that is coupled to the first clock terminal and that is configured to receive a clock signal; anda resistor that is coupled to the first clock terminal and the first bias voltage generator. a capacitor that is coupled to the first clock terminal and that is configured to receive a second clock signal; and', 'a resistor that is coupled to the first clock terminal and the first bias voltage generator,', 'wherein each of the resistors allow inner transistors of a first latch of the plurality of latches and the second latch of the plurality of latches to be biased through coupled resistors such that the gate voltages of these transistors are near or above their respective threshold voltages ...

High speed dual modulus divider

Described is an apparatus comprising a plurality of logic units arranged in a ring, wherein an output terminal of each logic unit from the plurality of logic units is coupled to an input terminal of a next logic unit from the plurality of logic units, wherein the plurality of logic units includes a first multiple input logic unit having input nodes coupled to at least two output terminals of logic units from the plurality of logic units; and a plurality of latch units coupled to the output terminals of the plurality of logic units.

METHOD FOR GENERATING A PLURALITY OF OSCILLATING SIGNALS WITH DIFFERENT PHASES AND ASSOCIATED CIRCUIT AND LOCAL OSCILLATOR

A circuit for generating a plurality of oscillating signals with different phases includes a frequency divider, a first delay chain, a second delay chain and a calibration circuit. The frequency divider is arranged for frequency dividing a first input signal and a second input signal to generate a first frequency-divided input signal and a second frequency-divided input signal. The first delay chain is arranged for delaying the first frequency-divided input signal, and the second delay chain is arranged for delaying the second frequency-divided input signal. The calibration circuit is arranged for controlling delay amounts of the first delay chain and the second delay chain according to signals within the first delay chain or the second delay chain; wherein output signals of a portion delay cells within the first delay chain and the second delay chain serve as the plurality of oscillating signals with different phases. 1. A circuit for generating a plurality of oscillating signals with different phases , comprising:a frequency divider, for frequency dividing a first input signal and a second input signal to generate a first frequency-divided input signal and a second frequency-divided input signal;a first delay chain comprising a plurality of first delay cells connected in series, for receiving the first frequency-divided input signal;a second delay chain comprising a plurality of second delay cells connected in series, for receiving the second frequency-divided input signal; anda calibration circuit, coupled to the first delay chain and the second delay chain, for controlling delay amounts of the first delay chain and the second delay chain according to signals within the first delay chain or the second delay chain;wherein output signals of a portion of the first delay cells and the second delay cells serve as the plurality of oscillating signals with different phases.2. The circuit of claim 1 , wherein the frequency divider has an odd divisor claim 1 , and the ...

TIME DOMAIN INTEGRATED TEMPERATURE SENSOR

A time domain integrated temperature sensor described by the present invention adopts a shaped clock signal to control the charging time of capacitors, so that the capacitors generate charging time delay signals related to the cycle of an input clock, and a pulse signal related to pulse width, temperature and the cycle of the input clock is generated through logical XOR (Exclusive OR) operation on a time delay signal generated when the capacitors are charged by one way of PTAT (Proportional To Absolute Temperature) current in an above control manner and a time delay signal generated when the capacitors are charged by one way of CTAT (Complementary To Absolute Temperature) current in the same manner; then, the same input clock signal is adopted for quantifying the pulse width of the pulse signal, the relevance of the obtained quantization result and the cycle of the input clock is completely offset, namely, an output value of the temperature sensor is unrelated to the input clock signal, thereby solving the problem that the reading of the existing time domain integrated temperature sensor is inconsistent as the cycle of the clock signal changes and improving the precision of the time domain integrated temperature sensor to a certain degree. 1. A time domain integrated temperature sensor , comprising a PTAT (Proportional To Absolute Temperature) time delay circuit , a CTAT (Complementary To Absolute Temperature) time delay circuit , an XOR (Exclusive OR) gate and a counter , wherein two input ends of the XOR gate are respectively connected to an output end of the PTAT time delay circuit and an output end of the CTAT time delay circuit , an output end of the XOR gate is connected with an enable end of the counter , and a clock signal input end of the counter is connected to a clock input port of the temperature sensor;the PTAT time delay circuit comprises a PTAT current generation circuit, a first capacitor, a first switch and a first level-detection circuit, an output ...

DUAL CLOCK SIGNAL TO PULSE-WIDTH MODULATED SIGNAL CONVERSION CIRCUIT

Disclosed is a dual clock signal to pulse-width modulated signal conversion circuit, comprising: a first counter, an input end of which inputs a first clock signal, and an output end of which outputs a divided signal; an edge reset circuit, an input end of which inputs the divided signal, the output end of which outputs a first reset pulse signal and a second reset pulse signal, the first reset pulse signal being configured for resetting a second counter, and the second reset pulse signal being configured for resetting a third counter; a second counter, an input end of which inputs the second clock signal and the first reset pulse signal, and an output end of which outputs the first pulse-width modulated signal; a third counter, an input end of which inputs the second clock signal and the second reset pulse signal, and an output end of which outputs the second pulse-width modulated signal; a logic processing circuit, an input end of which inputs the first pulse-width modulated signal and the second pulse-width modulated signal, and an output end of which outputs a pulse-width modulated signal PWM_OUT. The disclosure offers high precision, system stability, and good anti-interference. 1. A dual clock signal to pulse-width modulated signal conversion circuit comprising:an input end configured to receive a first clock signal and a second clock signal, andan output end configured to provide a pulse-width modulated signal;wherein a first clock cycle of the first clock signal is greater than or equal to a second clock cycle of the second clock signal; and {'br': None, 'K×(T0/T1); and'}, 'a high level average duty cycle of the first pulse-width modulated signal is equal to at least one of a ratio of the second clock cycle of the second clock signal to the first clock cycle of the first clock signal cycle, multiplied by a proportionality coefficient, and 1 minus the ratio of the second clock cycle of the second clock signal to the first clock cycle of the first clock signal ...

SIGNAL PROCESSING APPARATUS AND METHOD

The present technology relates to a signal processing apparatus and method capable of increasing a harmonic rejection ratio while suppressing an increase in power consumption. 1. A signal processing apparatus , comprisinga mixing section that has a differential configuration, mixes two local signals with each signal of a differential signal, and calculates a difference between results of the mixing of the two local signals, the two local signals having a 1/3 duty ratio and phases mutually shifted by a 1/2 period.2. The signal processing apparatus according to claim 1 , further comprisinga resonance section that resonates with the differential signal, with which the local signals are mixed by the mixing section, at a predetermined resonant frequency.3. The signal processing apparatus according to claim 2 , whereinthe resonance section resonates at a sixfold frequency of a frequency of the local signals.4. The signal processing apparatus according to claim 2 , whereinthe resonance section includes a parallel LC circuit.5. The signal processing apparatus according to claim 2 , whereinthe resonant frequency is variable.6. The signal processing apparatus according to claim 2 , further comprisinga voltage/current conversion section that converts a voltage into a current with respect to the differential signal, whereinthe mixing section mixes the local signals with the differential signal output from the voltage/current conversion section.7. The signal processing apparatus according to claim 6 , further comprisinga capacitor between an output of the voltage/current conversion section and a ground potential.8. The signal processing apparatus according to claim 1 , further comprisinga differential amplification section that amplifies the differential signal, with which the local signals are mixed by the mixing section.9. The signal processing apparatus according to claim 1 , whereinthe mixing section includes a path of an I channel and a path of a Q channel and mixes the ...

METHOD AND APPARATUS TO MONITOR GAIN OF A PROPORTIONAL COUNTER

A method and apparatus in accordance with the present disclosure relate to monitoring gain of a proportional counter. The method includes generating a pulse height spectrum of the proportional counter, defining a first window and a second window within the pulse height spectrum, counting electrical pulses outputted by the proportional counter within the first window of the pulse height spectrum, thereby defining a first window count, counting electrical pulses outputted by the proportional counter within the second window of the pulse height spectrum, thereby defining a second window count, and determining a difference between the first window count and the second window count. 1. A method for monitoring gain of a proportional counter , the method comprising:generating a pulse height spectrum of the proportional counter;defining a first window and a second window within the pulse height spectrum;counting electrical pulses outputted by the proportional counter within the first window of the pulse height spectrum, thereby defining a first window count;counting electrical pulses outputted by the proportional counter within the second window of the pulse height spectrum, thereby defining a second window count; anddetermining a difference between the first window count and the second window count.2. The method of claim 1 , further comprising:correcting thresholds defining the first window and the second window of the pulse height spectrum based upon the determined difference.3. The method of claim 2 , wherein claim 2 , if the first window count is more than the second window count claim 2 , the correcting the thresholds defining the first window and the second window of the pulse height spectrum comprises:decreasing the thresholds defining the first window and the second window of the pulse height spectrum in proportion to the determined difference.4. The method of claim 2 , wherein claim 2 , if the first window count is less than the second window count claim 2 , the ...

MEDICAL DEVICE WITH SELF-SUSTAINING POWER SOURCE

A medical device with a self-sustaining power source is disclosed herein. The medical device includes a pump and at least one mechanical activation mechanism for engaging the pump to cause a dose event. An energy generator coupled to the activation mechanism generates energy each time the activation mechanism is actuated. The generated energy is supplied to a dose counter of the infusion device. 1. An infusion device , comprising:a housing having a reservoir that is sized to retain a quantity of liquid medicament;a mechanical pump that displaces a portion of the liquid medicament when mechanically actuated;a mechanically driven activation mechanism disposed on the housing for actuating the pump in order to deliver a dose of liquid medicament and thereby signifying a dose event; andan energy generator coupled to the activation mechanism, the energy generator being configured to generate energy upon each operation of the mechanically driven activation mechanism in order to power a dose counter that is configured to record dose events.2. The infusion device of claim 1 , wherein the energy generator comprises at least one piezo crystal coupled to the activation mechanism claim 1 , the at least one piezo crystal being configured to produce a predetermined amount of energy when the activation mechanism is actuated.3. The infusion device of claim 2 , further comprising an energy storage device configured to store energy generated by the energy generator.4. The infusion device of claim 3 , wherein the energy storage device comprises at least one capacitor.5. The infusion device of claim 3 , wherein the dose counter comprises a microcontroller and wherein the energy storage device is coupled to the microcontroller.6. The infusion device of claim 2 , wherein the activation mechanism comprises at least one depressible button coupled to the pump wherein at least one said piezo crystal is coupled to the at least one depressible button.7. The infusion device of claim 2 , in which ...

FREQUENCY SYNTHESIZER WITH TUNABLE ACCURACY

An apparatus includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first code by counting a number of cycles of an input clock signal during a period. The period may be determined by an output clock signal and a second code. The second circuit may be configured to generate a third code by a delta-sigma modulation of the first code. The third circuit may be configured to generate the output clock signal in response to the third code. An accuracy of a frequency of the output clock signal may be determined by a current value of the second code. 1. An apparatus comprising:a first circuit configured to generate a first code by counting a number of cycles of an input clock signal during a period, wherein said period is determined by an output clock signal and a second code;a second circuit configured to generate a third code by a delta-sigma modulation of said first code; anda third circuit configured to generate said output clock signal in response to said third code, wherein an accuracy of a frequency of said output clock signal is determined by a current value of said second code.2. The apparatus according to claim 1 , wherein said first circuit is further configured to adjust said second code to change a duration of said period.3. The apparatus according to claim 1 , wherein said first circuit is further configured to set said second code to an initial value that establishes a short duration of said period in which said frequency of said output clock signal is adjusted to a coarse accuracy.4. The apparatus according to claim 1 , wherein a coarse accuracy of said frequency of said output clock signal is achieved when said number of cycles of said input clock during said period minus an expected number falls below a threshold.5. The apparatus according to claim 1 , wherein said first circuit is further configured to set said second code to a subsequent value that establishes a long duration of said period in ...

DRIVER CIRCUIT HAVING OVERCURRENT PROTECTION FUNCTION AND CONTROL METHOD OF DRIVER CIRCUIT HAVING OVERCURRENT PROTECTION FUNCTION

According to one aspect of embodiments, a driver circuit having an overcurrent protection function includes a control signal generating circuit that outputs a Pulse Width Modulation (PWM) control signal for controlling turning ON and OFF of the output transistor that supplies output current to a load; and a control circuit that generates a signal indicating an overcurrent state when a count value of an overcurrent detecting signal exceeds a predetermined number, which indicates that a value of an output current of the output transistor within the predetermined time interval exceeds a predetermined threshold value. 1. A driver circuit having an overcurrent protection function , the circuit comprising:an output transistor that supplies output current to a load;a control signal generating circuit that outputs a Pulse Width Modulation (PWM) control signal, the PWM control signal controlling turning ON and OFF of the output transistor;a current detecting circuit that detects a current flowing through the output transistor;an overcurrent detecting circuit that outputs an overcurrent detecting signal when a value of the current detected by the current detecting circuit exceeds a predetermined threshold value;a counter that counts a number of outputs from the overcurrent detecting signal; anda control circuit that generates, when a count value of the counter exceeds a predetermined number within a predetermined time interval, a signal indicating an overcurrent state.2. The driver circuit having the overcurrent protection function according to claim 1 , further comprising:an interval setting circuit that outputs, in response to the PWM control signal and the overcurrent detecting signal, an output signal that turns ON the output transistor after a predetermined time interval from a timing at which the overcurrent detecting signal is output in a control state where the PWM control signal turns ON the output transistor.3. The driver circuit having the overcurrent protection ...

CIRCUIT TECHNIQUE TO TRACK CMOS DEVICE THRESHOLD VARIATION

Methods and systems for independently tracking NMOS device process variation and PMOS device process variation are described herein. In one embodiment, a method for tracking process variation includes measuring a frequency of an NMOS-based ring oscillator on a chip, and determining a threshold voltage or switching speed for NMOS transistors on the chip based on the measured frequency of the NMOS-based ring oscillator. The method also includes measuring a frequency of a PMOS-based ring oscillator on the chip, and determining a threshold voltage or switching speed for PMOS transistors on the chip based on the measured frequency of the PMOS-based ring oscillator. 1. A method for tracking process variation , comprising:measuring a frequency of an NMOS-based ring oscillator on a chip;determining a threshold voltage or switching speed for NMOS transistors on the chip based on the measured frequency of the NMOS-based ring oscillator;measuring a frequency of a PMOS-based ring oscillator on the chip; anddetermining a threshold voltage or switching speed for PMOS transistors on the chip based on the measured frequency of the PMOS-based ring oscillator.2. The method of claim 1 , wherein the NMOS-based ring oscillator includes a plurality of inverters coupled in a closed loop claim 1 , each of the inverters comprising:a first NMOS transistor, wherein the NMOS transistor is diode-connected; anda second NMOS transistor having a gate coupled to an input of the inverter, and a drain coupled to a source of the first NMOS transistor and an output of the inverter.3. The method of claim 1 , wherein the PMOS-based ring oscillator includes a plurality of inverters coupled in a closed loop claim 1 , each of the inverters comprising:a first PMOS transistor, wherein the PMOS transistor is diode-connected; anda second PMOS transistor having a gate coupled to an input of the inverter, and a drain coupled to a source of the first PMOS transistor and an output of the inverter.4. The method of ...

Apparatus of preventing esd and emp using semiconductor having a wider band gap and method thereof

An apparatus of preventing ESD and EMP coupled between a signal input and a signal output is provided with a first diode of forward bias including a positive terminal and a negative terminal connected to the signal input and ground respectively; and a first diode of reverse bias including a negative terminal and a positive terminal connected to the signal input and the ground respectively. The semiconductor is a diode including a p-type semiconductor region made of semiconductor material having a predetermined band gap and an n-type semiconductor region made of semiconductor material having a predetermined band gap. The predetermined band gap is greater than 3 eV. The diode operates in forward bias to discharge current generated by ESD and/or EMP. A method of preventing ESD and EMP is also provided.

Counting circuit, delay value quantization circuit, and latency control circuit

A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio.

DOUBLE DATA RATE COUNTER, AND ANALOG-TO-DIGITAL CONVERTER AND CMOS IMAGE SENSOR USING THE SAME

A Double Data Rate (DDR) counter includes an input clock control portion suitable for generating a first clock corresponding to a state of a input clock based on a counter enable signal, and an LSB control portion suitable for holding a least significant bit based on the counter enable signal and successively performing a counting operation on the first clock in multiple sections. 1. A Double Data Rate DDR counter , comprising:an input clock control portion suitable for generating a first clock corresponding to a state of a input clock based on a counter enable signal; anda Least Significant Bit (LSB) control portion suitable for holding an LSB based on the counter enable signal and successively performing a counting operation on the first clock in multiple sections.2. The DDR counter of claim 1 , wherein the input clock control portion detects the state of a neighboring clock of the input clock based on a first edge of the counter enable signal and inverts or non-inverts the input clock based on a detected state of the neighboring clock.3. The DDR counter of claim 1 , wherein the input clock control portion includes:a counting section determination block suitable for receiving the input clock and the counter enable signal and determining a counting section;a clock sampling block suitable for sampling the state of the input clock based on the counter enable signal; anda first inversion/non-inversion block suitable for inverting or non-inverting an output of the counting section determination block based on a clock sampling result obtained from the clock sampling block and outputting the first clock to the LSB control portion.4. The DDR counter of claim 3 , wherein the input clock control portion further includes:a third inversion/non-inversion block suitable for inverting or non-inverting a cross-correlation double sampling output based on a control signal and outputting the counter enable signal.5. The DDR counter of claim 3 , wherein the counting section ...

SIGNAL GENERATION CIRCUIT SYNCHRONIZED WITH A CLOCK SIGNAL AND A SEMICONDUCTOR APPARATUS USING THE SAME

A signal generation circuit includes a clock divider circuit, an off-pulse generation circuit, and an output signal generation circuit. The on-pulse generation circuit delays an input signal in synchronization with the first and second divided clock signals and generates an even on-pulse signal and an odd on-pulse signal. The off-pulse generation circuit delays the even on-pulse signal and the odd-on pulse signal in synchronization with the first divided clock signal and the second divided clock signal and generates a plurality of delay signals. The output signal generation circuit generates a first pre-output signal based on the delay signals delayed in synchronization with the first divided clock signal, generate a second pre-output signal based on the delay signals delayed in synchronization with the second divided clock signal, and generate an output signal based on the first and second pre-output signals. 1. A signal generation circuit comprising:a clock divider circuit configured to generate a first divided clock signal, a second divided clock signal, a third divided clock signal, and a fourth divided clock signal based on a clock signal;an on-pulse generation circuit configured to delay an input signal in synchronization with the first and second divided clock signals to generate an even on-pulse signal and an odd on-pulse signal, based on first delay information;an off-pulse generation circuit configured to sequentially delay the even on-pulse signal alternately in synchronization with the second divided clock signal and the first divided clock signal to generate a plurality of even delay signals, based on second delay information, and to sequentially delay the odd on-pulse signal alternately in synchronization with the first divided clock signal and the second divided clock signal to generate a plurality of odd delay signals, based on the second delay information; andan output signal generation circuit configured to generate a first pre-output signal based ...

Wide Range Glitchless Switchable Clock Divider With Modified 2/3 Divider Stages

A divider includes 2/3 divider stages that may be turned off without toggling to extend the divide range of the divider while also reducing the impact of spurs on the divider output, and preserving the timing margin to update the divide ratio glitchlessly. A 2/3 divider stage responds to an input enable signal being deasserted and a modulus input signal being asserted to remain in a disabled state in which the divider stage does not toggle by ensuring storage elements outputs in the divider stage remain constant. The divider further selects an update clock for the divide ratio of the divider utilizing an output from a most downstream stage that remains enabled. 1. A divider comprising:a plurality of 2/3 divider stages configured in a divider chain;a divider stage of the 2/3 divider stages responsive, in part, to a deasserted input enable signal to remain in a disabled state, wherein the divider stage does not toggle when in the disabled state by having storage elements outputs in the divider stage remain constant; andwherein a divide range of the divider chain is extended when the divider stage is disabled.2. The divider claim 1 , as recited in claim 1 , wherein the divider stage is responsive to a modulus input signal received from a downstream stage being asserted and the deasserted input enable signal being to remain in the disabled state.3. The divider claim 1 , as recited in claim 1 , wherein the divider stage is implemented as a state machine and a first state of the state machine is a reset state claim 1 , the reset state being the disabled state claim 1 , and the state machine in the divider stage is responsive to the deasserted input enable signal and a modulus input signal being asserted to remain in the reset state claim 1 , wherein a second state of the state machine is used to divide by two and a third state of the state machine is used for a divide by three once during a period of an output of the divider.4. The divider claim 1 , as recited in claim 1 ...

HIERARCHICAL STATISTICALLY MULTIPLEXED COUNTERS AND A METHOD THEREOF

Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life. 135-. (canceled)36. A network device comprising:a common memory pool, wherein memories from the common memory pool are separated into a plurality of banks; anda counter architecture for extending counter life, wherein the counter architecture includes a hierarchy of levels of statistically multiplexed counters, wherein each of the hierarchy of levels includes N counters arranged in N/P rows, wherein each of the N/P rows includes P base counters and S subcounters, wherein any of the P base counters can be dynamically concatenated with one or more of the S subcounters to flexibly extend the counting capacity.37. The network device of claim 36 , wherein counters in the same row in one level of the hierarchy of levels are shuffled into different rows in a next level above of the hierarchy of levels.38. The network device of claim 37 , wherein a randomization of the shuffle is a bit reverse of a counter identifier of a counter claim 37 , a hash function or a bit arrangement in another order.39. The network device of claim 36 , wherein the counter architecture further includes a mirrored shift logic to extend the P counters to a full width such that a full range of shifting is reduced.40. The network device of claim 36 , wherein the counter architecture is configured to update a counter by:determining whether a corresponding row of the counter in a current level of the ...

CAPACITIVE DIGITAL ISOLATOR CIRCUIT WITH ULTRA-LOW POWER CONSUMPTION BASED ON PULSE-CODING

A capacitive digital isolator circuit includes: a signal emitting module; a signal receiving module; and a capacitive isolation module. The signal emitting module includes an edge Pulse-Coding modulator circuit, which modulates an input signal to generate a pair of differential modulated signals based on the input signal and transmits the pair of differential modulated signals to the signal receiving module. Each of the pair of differential modulated signals has twelve high-frequency pulses when the input signal has a rising edge and has six high-frequency pulses when the input signal has a falling edge. The signal receiving module includes an ultra-low power consumption high-speed comparator, a timer and a pulse counter. An output signal of the pulse counter has a rising edge when the pulse number of the comparator output signal is larger than nine and a falling edge when the pulse number is equal to or smaller than nine. 1. A capacitive digital isolator circuit with ultra-low power consumption based on Pulse-Coding comprising:a signal emitting module having a signal input terminal;a signal receiving module having a signal output terminal; and{'claim-text': ['the signal emitting module includes an edge Pulse-Coding modulator circuit, the edge Pulse-Coding modulator circuit modulating an input signal to generate a pair of differential modulated signals based on the input signal and transmitting the pair of differential modulated signals to the signal receiving module via the capacitive isolation module, each of the pair of differential modulated signals having twelve high-frequency pulses when the input signal has a rising edge, each of the pair of differential modulated signals having six high-frequency pulses when the input signal has a falling edge; and', 'the signal receiving module includes an ultra-low power consumption high-speed comparator, a timer and a pulse counter, the ultra-low power consumption high-speed comparator comparing the received pair of ...

DYNAMIC PRESCALING FOR PERFORMANCE COUNTERS

A method of configuring a prescaling circuit in a performance counter circuit for a computer processing system can include receiving a first number of signaled events at a prescaling circuit configured to generate event counts for a performance counter circuit. The method can include generating event counts at a current event-count rate for the first number of signaled events and determining a detected event-count rate for the signaled events based on a rate at which the first number of signaled events are received at the prescaling circuit. The method can include determining that the detected event-count rate is greater than the current event-count rate. The method can include increasing the current event-count rate in response to determining that the detected event-count rate is greater than the current event-count rate. 1. A method of configuring a prescaling circuit in a performance counter circuit for a computer processing system , the method comprising:receiving a first number of signaled events at a prescaling circuit configured to generate event counts for a performance counter circuit;generating event counts at a current event-count rate for the first number of signaled events;determining a detected event-count rate for the signaled events based on a rate at which the first number of signaled events are received at the prescaling circuit;determining that the detected event-count rate is greater than the current event-count rate; andincreasing the current event-count rate in response to determining that the detected event-count rate is greater than the current event-count rate.2. The method of claim 1 , further comprising:receiving a second number of signaled events at the prescaling circuit;generating event counts at the current event-count rate for the second number of signaled events;determining the detected event-count rate for the signaled events based on a rate at which the second number of signaled events are received at the prescaling circuit; ...

FREQUENCY ADJUSTING DEVICE AND METHOD FOR ADJUSTING FREQUENCY

A frequency adjusting device includes a voltage droop detector and a frequency divider. The voltage droop detector compares a supply voltage with a lower threshold voltage to output a comparison result. When the supply voltage is greater than the threshold voltage, the frequency divider outputs a result of dividing a basic clock signal by a first value as a clock signal. When the supply voltage is smaller than the threshold voltage, the frequency divider outputs a result of dividing the basic clock signal by a second value as the clock signal. 1. A frequency adjusting device , comprising:a voltage droop detector, receiving a supply voltage, comparing the supply voltage with a lower threshold voltage to output a comparison result; anda frequency divider, receiving a basic clock signal, outputting a result clock signal according to the comparison result;wherein, when the supply voltage is greater than the lower threshold voltage, the frequency divider outputs a result of the basic clock signal divided by a first value as the result clock signal; when the supply voltage is smaller than the lower threshold voltage, the frequency divider outputs a result of the basic clock signal divided by a second value as the result clock signal.2. The frequency adjusting device according to claim 1 , further comprising a frequency dividing signal generator claim 1 , and the frequency dividing signal generator generates a down-conversion indication signal that comprises a down-conversion starting pulse and a down-conversion ending pulse.3. The frequency adjusting device according to claim 2 , wherein the frequency divider comprises a first D-flip-flop claim 2 , a second D-flip-flop and an XOR gate claim 2 , the first D-flip-flop receives the comparison result and has its output end connected to an input end of the second D-flip-flop claim 2 , and the OR gate receives the comparison result and an output of the second D-flip-flop to perform an XOR operation to output the down-conversion ...

SYNCHRONIZATION SYSTEM AND FREQUENCY DIVIDER CIRCUIT

In a synchronization system, a frequency divider circuit generates a divided clock by dividing a reference clock in a first division ratio. First and second devices operate in synchronization with the reference clock and the divided clock. A division ratio detection circuit, for each period of the divided clock, detects a division ratio of the divided clock based on a count value counted in synchronization with the reference clock and output the division ratio as a second division ratio. A decoder generates a strobe signal, which is for controlling a timing at which the first device transmits and receives a signal to and from the second device, based on the count value and the second division ratio. The first device communicates with the second device through a bus, which operates in synchronization with the divided clock, based on the strobe signal. 1. A synchronization system , comprising:a frequency divider circuit that generates a divided clock by dividing a reference clock in a first division ratio set by a division ratio setting signal;a first device that operates in synchronization with the reference clock;a second device that operates in synchronization with the divided clock;a division ratio detection circuit that, for each period of the divided clock, outputs a count value counted in synchronization with the reference clock, and detects a division ratio of the divided clock based on the count value and output the division ratio as a second division ratio; anda decoder that generates a strobe signal, which is for controlling a timing at which the first device transmits and receives a signal to and from the second device, based on the count value and the second division ratio,wherein the first device communicates with the second device through a bus, which operates in synchronization with the divided clock, based on the strobe signal.2. The synchronization system according to claim 1 ,wherein the frequency divider circuit comprises:a division ratio changing ...

LOW POWER DIGITAL FRACTIONAL DIVIDER WITH GLITCHLESS OUTPUT

A digital circuit that divides a high speed digital clock by a fractional value is described. The circuit utilizes a divider circuit and shifts the divider clock by a fraction of a phase to achieve the desired fractional division. A clock mux is used to perform the clock shift, and a masking mux is used to eliminate glitches during the clock shift. 1. A system for dividing a clock signal , the system comprising:a first multiplexor configured to receive a plurality of phases of a clock signal and output a shifted clock signal based on the plurality of phases of the clock signal, the shifted clock signal including a glitch;a second multiplexor configured to receive a masking signal and the shifted clock signal including the glitch, and is configured to output the shifted clock signal without the glitch using the masking signal; anda divider circuit configured to receive the shifted clock signal without the glitch and output a fractionally divided clock signal based on the shifted clock signal without the glitch.2. The system of claim 1 , wherein the first multiplexor is configured to output the shifted clock signal by outputting at least a first phase from the plurality of phases of the clock signal based on a selection signal selecting the first phase for output by the first multiplexor and subsequently outputting a second phase from the plurality of phases of the clock signal based on the selection signal selecting the second phase for output by the first multiplexor.3. The system of claim 2 , wherein the glitch is an unwanted transition of the shifted clock signal that occurs in the shifted clock signal responsive to a transition from the selection signal selecting the first phase for output by the first multiplexor to selecting the second phase for output by the first multiplexor.4. The system of claim 1 , further comprising:a digital control logic configured to generate a selection signal to control which of the plurality of phases of the clock signal is ...

LOW DROPOUT VOLTAGE (LDO) REGULATOR INCLUDING A DUAL LOOP CIRCUIT AND AN APPLICATION PROCESSOR AND A USER DEVICE INCLUDING THE SAME

A low dropout voltage (LDO) regulator including: a coarse loop circuit configured to receive an input voltage, generate a coarse code and adjust a coarse current according to the coarse code; a digital controller configured to receive the coarse code and generate a fine loop control signal according to the coarse code; and a fine loop circuit configured to receive the input voltage and the fine loop control signal and adjust a fine current according to the input voltage and the fine loop control signal, wherein the coarse current and the fine current adjust a level of an output voltage. 1. A low dropout voltage (LDO) regulator , comprising:a fine loop circuit configured to receive an input voltage, provide a fine loop current to an output voltage node and to be disabled in response to a disable signal when an output voltage at the output voltage node changes;a coarse loop circuit configured to receive the input voltage, provide a coarse current to the output voltage node in response to a coarse code when the fine loop circuit is disabled; anda digital controller configured to generate an initialization signal to be set an initial fine current of the fine loop circuit in a way that reduces a transition effect due to a loop change while the coarse current is being varied and to provide an enable signal to the fine loop circuit to activate the fine loop circuit when the coarse current enters a steady state,wherein the LDO regulator receives a power supply voltage from a power management integrated circuit (PMIC) through a power line and provides the output voltage as an internal power supply voltage to a load circuit through the output voltage node.2. The LDO regulator of claim 1 , wherein the low dropout voltage (LDO) regulator is integrated in an application processor.3. The LDO regulator of claim 1 , wherein the coarse loop circuit comprises:a reference voltage changer configured to receive the coarse code and change a coarse reference voltage;an analog-to-digital ...

FREQUENCY DIVIDER AND RELATED ELECTRONIC DEVICE

A frequency divider may include the following elements: a first inverter, a second inverter, and a third inverter, which are connected in a ring structure, wherein the second inverter is connected to an output terminal of the frequency divider; a fourth inverter connected to a first input terminal of the frequency divider and to a power supply terminal of the first inverter; a fifth inverter connected to a second input terminal of the frequency divider and to a power supply terminal of the third inverter; a first transistor connected to the second input terminal of the frequency divider and to a ground terminal of the first inverter; and a second transistor connected to the first input terminal of the frequency divider and to a ground terminal of the third inverter. The second inverter, the fourth inverter, and the fifth inverter may receive a power supply voltage. 1. A frequency divider comprising:a first inverter;a second inverter, wherein an input terminal of the second inverter is electrically connected to an output terminal of the first inverter, wherein an output terminal of the second inverter is electrically connected to an output terminal of the frequency divider, wherein a power supply terminal of the second inverter is configured to receive a power supply voltage, wherein a ground terminal of the second inverter is configured to receive a reference voltage or is grounded;a third inverter, wherein an input terminal of the third inverter is electrically connected to the output terminal of the second inverter, and wherein an output terminal of the third inverter is electrically connected to an input terminal of the first inverter;a fourth inverter, wherein an input terminal of the fourth inverter is electrically connected to a first input terminal of the frequency divider, wherein an output terminal of the fourth inverter is electrically connected to a power supply terminal of the first inverter, wherein a power supply terminal of the fourth inverter is ...

SHARED DIVIDE BY N CLOCK DIVIDER

A method of providing multiple clock frequencies for an integrated circuit having a plurality of modules. A reference clock signal (fin) is frequency division processed to generate sub-divider outputs of fin divided by a plurality of different (i) prime numbers and (ii) prime numbers raised to an integer power to collectively provide a plurality of prime number-based clock signals that each have a frequency divider factor (divider factor) in a predetermined divider range. For at least a portion of other divider factors, two or more of the sub-divider outputs are combined to generate additional clock signals that each provide an additional divider factor. A first module frequency selects at least a first selected clock signal from the prime number-based clock signals and additional clock signals, and a second module frequency selects at least a second selected clock signal from the prime number-based clock signals and additional clock signals. 1. A method of providing multiple clock frequencies for an integrated circuit (IC) including a plurality of modules , comprising:{'sup': 'N', 'frequency division processing of at least one reference clock signal (fin) to generate sub-divider outputs of said fin divided by a plurality of different (i) prime numbers and (ii) prime numbers raised to an integer power to collectively provide a plurality of prime number-based clock signals each providing a frequency divider factor (divider factor) in a predetermined divider range including at least one divider factor that is not equal to 2, and'}for at least a portion of others of said divider factors that are not said prime numbers or said prime numbers raised to an integer power, combining combinations of two or more of said sub-divider outputs to generate additional clock signals that each provide an additional divider factor;a first of said plurality of modules frequency selecting at least a first selected clock signal from said plurality of prime number-based clock signals and ...

MULTI-MODULUS FREQUENCY DIVIDER AND ELECTRONIC APPARATUS INCLUDING THE SAME

A multi-modulus frequency divider includes a frequency division module, a frequency selection module, and a retiming module. The frequency division module is configured to receive an input signal and perform mufti-mode frequency processing on the input signal, so as to generate and output a plurality of divided signals to the frequency selection module. The frequency selection module is configured to receive the plurality of divided signals from the frequency division module, select a divided signal having a desired frequency from among the plurality of divided signals, and output the selected divided signal to the retiming module. The retiming module is configured to receive the selected divided signal from the frequency selection module, perform a retiming operation on the selected divided signal, and output a retimed selected divided signal. 1. A multi-modulus frequency divider comprising:a frequency division module, a frequency selection module, and a retiming module,wherein the frequency division module is configured to receive an input signal and perform multi-mode frequency processing on the input signal, so as to generate and output a plurality of divided signals to the frequency selection module,wherein the frequency selection module is configured to receive the plurality of divided signals from the frequency division module, select a divided signal having a desired frequency from among the plurality of divided signals, and output the selected divided signal to the retiming module; andwherein the retiming module is configured to receive the selected divided signal from the frequency selection module, perform a retiming operation on the selected divided signal, and output a retimed selected divided signal.2. The multi-modulus frequency divider according to claim 1 , wherein the frequency division module comprises N number of differential cascading frequency divider cells configured to divide by 2 or by 3 claim 1 ,wherein the frequency divider cells include ...

INTEGRATED CIRCUIT ASSOCIATED WITH CLOCK GENERATOR, AND ASSOCIATED CONTROL METHOD

An integrated circuit includes a data sampler and a digital logic circuit. The data sampler provides multiple signal samples at a speed twice a symbol rate according to a local clock signal and the inverted local clock signal. The signal samples include a first symbol sample, and a second symbol sample that occurs later than the first symbol sample. The signal samples further include an interpolated sample between the first and second symbol samples. The digital logic circuit compares the first symbol sample with the interpolated sample to generate pre phase correction data, and compares the second symbol sample with the interpolated sample to generate post phase correction data. The pre phase correction data is generated earlier than the post phase correction data. The local clock signal and the inverted local clock signal have substantially a phase difference of 180 degrees. 1. An integrated circuit associated with a clock generator providing a local clock signal , comprising:a data sampler, configured to provide a plurality of signal samples at a speed that is twice a symbol rate according to the local clock signal and an inverted local clock signal, the signal samples comprising a first symbol sample and a second symbol sample, the second symbol sample being later than the first symbol sample by one symbol period, the signal samples further comprising an interpolated sample between the first and second symbol samples; anda digital logic circuit, configured to compare the first symbol sample with the interpolated sample to generate pre phase correction data, and to compare the second symbol sample with the interpolated sample to generate post phase correction data, wherein the pre phase correction data is generated earlier than the post phase correction data;wherein, the local clock signal and the inverted local clock signal have substantially a phase difference of 180 degrees.2. The integrated circuit according to claim 1 , wherein the data sampler comprises:a ...

RE-TIMING BASED CLOCK GENERATION AND RESIDUAL SIDEBAND (RSB) ENHANCEMENT CIRCUIT

Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may include a first transistor connected in cascode with a second transistor, wherein an input clock node of the circuit is coupled to gates of the first and second transistors. The clock generation circuit may also include a frequency divider circuit having an input coupled to the input clock node, wherein an output of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node of the circuit is coupled to drains of the first and second transistors. 1. A clock generation circuit , comprising:a first transistor coupled to a second transistor, wherein an input clock node of the circuit is coupled to gates of the first and second transistors; anda frequency divider circuit having an input coupled to the input clock node, wherein an output of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node of the clock generation circuit is coupled to drains of the first and second transistors.2. The clock generation circuit of claim 1 , wherein the frequency divider circuit is configured to:generate a divided clock signal based on a signal at the input clock node; andprovide the divided clock signal to the source of the second transistor, wherein a frequency of the divided clock signal is lower than a frequency of the signal at the input clock node.3. The clock generation circuit of claim 1 , wherein the frequency divider circuit comprises a divide-by-two (DIV2) frequency divider circuit.4. The clock generation circuit of claim 1 , further comprising a residual sideband (RSB) enhancement circuit having an input coupled to the input clock node claim 1 , wherein an output of the RSB enhancement circuit is coupled to the gates of the first and second ...

REGULATOR, SERIALIZER, DESERIALIZER, SERIALIZER/DESERIALIZER CIRCUIT, AND METHOD OF CONTROLLING THE SAME

According to an embodiment, a regulator includes: a voltage control circuit to supply a voltage; a clock signal output circuit to output a clock signal controlled by the voltage supplied from the voltage control circuit; and a current control circuit to supply the voltage supplied from the voltage control circuit to the clock signal output circuit, the current control circuit make to flow a dummy current which is determined based on the voltage, and stopping flowing the dummy current at a timing when the clock signal output circuit outputs the clock signal. 1. A regulator comprising:a voltage control circuit to supply a voltage;a clock signal output circuit to output a clock signal controlled by the voltage supplied from the voltage control circuit; anda current control circuit to supply the voltage supplied from the voltage control circuit to the clock signal output circuit, the current control circuit making to flow a dummy current which is determined based on the voltage, and stopping flowing the dummy current at a timing when the clock signal output circuit outputs the clock signal.2. The regulator according to claim 1 , wherein the current control circuit controls an amount of the dummy current based on an amount of a load current flowing when the clock signal output circuit output the clock signal without being controlled.3. The regulator according to claim 1 , wherein the current control circuit controls the amount of the dummy current based on a clock frequency of the clock signal inputted into the clock signal output circuit.4. The regulator according to claim 3 , wherein the current control circuit comprises one or a plurality of dummy current flowing circuits to allow the dummy current to flow from an output of the current control circuit.5. The regulator according to claim 4 , further comprising a dummy current flowing control circuit to select one or plurality of the dummy current flowing circuits based on the clock frequency of the clock signal so as ...

FRACTIONAL FREQUENCY DIVIDER AND FLASH MEMORY CONTROLLER

The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values. The control signal generator is configured to generate a control signal based on an input clock signal and values in the at least a portion of the registers, wherein the control generator sequentially generates the control signal during each cycle of the input clock signal. The clock gating circuit is configured to refer to the control signal to mask or not mask the input clock signal to generate an output clock signal. 1. A fractional frequency divider , comprising:a plurality of registers, wherein at least a portion of the registers are set to have values;a control signal generator, configured to generate a control signal based on an input clock signal and values in the at least a portion of the registers, wherein the control signal generator sequentially generates the control signal during each cycle of the input clock signal; anda clock gating circuit, configured to refer to the control signal to mask or not mask the input clock signal to generate an output clock signal.2. The fractional frequency divider of claim 1 , further comprising:a counter, configured to sequentially generate a plurality of counter values according to the input clock signal and the number of the at least a portion of the registers set to have values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly.3. The fractional frequency divider of claim 2 , wherein a number of the plurality of counter values is the same as a number of the at least a portion of the registers; and if the register corresponding to the counter value received by the control signal generator has a first value claim 2 ...

PHOTON-COUNTING DETECTOR AND READOUT CIRCUIT

A photon-counting detector configured to detect photons included in multi-energy radiation. The photon-counting detector includes a pixel area configured to absorb photons incident thereto, and bias circuits configured to supply one of a bias voltage and a bias current to electronic devices in the pixel area, wherein the bias circuits are in the pixel area. 1. A photon-counting detector configured to detect photons included in multi-energy radiation , the photon-counting detector comprising:a pixel area configured to absorb the photons incident thereto; and 'the bias circuits are in the pixel area.', 'bias circuits configured to supply one of a bias voltage and a bias current to electronic devices in the pixel area, wherein'}2. The photon-counting detector of claim 1 , wherein the pixel area comprises:a plurality of pixels, each of the plurality of pixels having one of the bias circuits therein.3. The photon-counting detector of claim 1 , wherein the pixel area comprises a plurality of pixels claim 1 ,wherein the bias circuits are included in at least one of the plurality of pixels.4. The photon-counting detector of claim 1 , wherein the pixel area is divided into M×N pixels claim 1 ,M and N are natural numbers, andone of the bias circuits are included in one of the pixels of the M×N pixels, andthe one of the bias circuits is shared between of the M×N pixels.5. The photon-counting detector of claim 4 , wherein the bias circuit included in the M×N pixels supplies the bias voltage to each of the M×N pixels.6. The photon-counting detector of claim 1 , wherein the pixel area is divided into units of 2×2 pixels claim 1 ,wherein one of the bias circuits are included in each of the 2×2 pixels,wherein the bias circuit supplies the bias voltage to the 2×2 pixels.7. The photon-counting detector of claim 1 , wherein one bias circuit is included in two pixels claim 1 ,wherein the bias circuit supplies the bias voltage to the two pixels.8. The photon-counting detector of claim 1 ...

CLOCK GENERATING APPARATUS AND FRACTIONAL FREQUENCY DIVIDER THEREOF

A clock generating apparatus and a fractional frequency divider thereof are provided. The fractional frequency divider includes a frequency divider (FD), a plurality of samplers, a selector and a control circuit. An input terminal of the FD is coupled to an output terminal of a multi-phase-frequency generating circuit. Input terminals of the samplers are coupled to an output terminal of the FD. Trigger terminals of the samplers receive the sampling clock signals. The input terminals of the selector are coupled to output terminals of the samplers. An output terminal of the selector is coupled to a feedback terminal of the multi-phase-frequency generating circuit. The control circuit provides a fraction code to a control terminal of the selector, so as to control the selector for selectively coupling the output terminal of one of the samplers to the feedback terminal of the multi-phase-frequency generating circuit. 1. A fractional frequency divider , comprising:a frequency divider, having an input terminal coupled to an output terminal of a multi-phase-frequency generating circuit for receiving an output clock signal;a plurality of samplers, having input terminals coupled to an output terminal of the frequency divider for receiving a frequency-divided clock signal, and trigger terminals of the samplers coupled to the multi-phase-frequency generating circuit for receiving a plurality of sampling clock signals, wherein the sampling clock signals have a same frequency and different phases;a selector, having a plurality of input terminals respectively coupled to output terminals of the samplers, and an output terminal coupled to a feedback terminal of the multi-phase-frequency generating circuit; anda control circuit, providing a fraction code to a control terminal of the selector, so as to control the selector to selectively couple the output terminal of one of the samplers to the feedback terminal of the multi-phase-frequency generating circuit.2. The fractional ...

PHYSICAL QUANTITY MEASUREMENT APPARATUS, ELECTRONIC APPARATUS, AND VEHICLE

A physical quantity measurement apparatus includes a first resonator, a second oscillator, and an integrated circuit device. The integrated circuit device includes a first oscillation circuit that causes the first resonator to oscillate, and thus generate a first clock signal having a first clock frequency, a second oscillation circuit that causes the second oscillator to oscillate, and thus generate a second clock signal having a second clock frequency which is different from the first clock frequency, and a measurement unit that is provided with a time-to-digital conversion circuit which converts time into a digital value by using the first clock signal and the second clock signal. 1. A physical quantity measurement apparatus comprising:a first resonator;a second oscillator; andan integrated circuit device, a first oscillation circuit configured to cause the first resonator to oscillate and generate a first clock signal having a first clock frequency,', 'a second oscillation circuit configured to cause the second oscillator to oscillate and generate a second clock signal having a second clock frequency, the second clock frequency being different from the first clock frequency, and', 'a measurement unit having a time-to-digital conversion circuit configured to convert time into a digital value based on the first clock signal and the second clock signal., 'wherein the integrated circuit device includes2. The physical quantity measurement apparatus according to claim 1 , a first terminal that connects one end of the first resonator to the first oscillation circuit;', 'a second terminal that connects the other end of the first resonator to the first oscillation circuit;', 'a third terminal that connects one end of the second oscillator to the second oscillation circuit; and', 'a fourth terminal that connects the other end of the second oscillator to the second oscillation circuit., 'wherein the integrated circuit device includes3. The physical quantity measurement ...

FREQUENCY DIVIDER CIRCUIT, COMMUNICATION CIRCUIT, AND INTEGRATED CIRCUIT

A frequency divider circuit includes: a first latch circuit that including: a pair of input transistors each having a gate thereof configured to connect to a signal line to which a first voltage is supplied; and a pair of output nodes, and configured to receive a single-phase clock signal; and a second latch circuit of SR-type, the second latch circuit having a set input thereof and a reset input thereof configured to connect to the pair of output nodes of the first latch circuit, and configured to output differential clock signals of which frequency is half a frequency of the single-phase clock signal. The first latch circuit is configured to perform amplification and reset operations alternately repeatedly in response to the single-phase clock signal. 1. A frequency divider circuit , comprising: a pair of input transistors each having a gate thereof configured to connect to a signal line to which a first voltage is supplied; and', 'a pair of output nodes,, 'a first latch circuit, the first latch circuit includingthe first latch circuit configured to receive a single-phase clock signal; anda second latch circuit of SR-type, the second latch circuit having a set input thereof configured to connect to one output node of the pair of output nodes, having a reset input thereof configured to connect to the other output node of the pair of output nodes, and configured to output differential clock signals of which frequency is half a frequency of the single-phase clock signal, whereinthe first latch circuit is configured to perform amplification and reset operations alternately repeatedly in response to the single-phase clock signal, and configured not to reset nodes to which drains of the pair of input transistors are connected in the reset operation.2. The frequency divider circuit according to claim 1 , whereinthe first latch circuit includes a pair of inverters which are cross-connected, each of the pair of inverters including two transistors, a source of one ...

Counter circuit and semiconductor device including the same

A counter circuit includes a lower count signal generation unit suitable for generating a lower bit, an upper count signal generation unit suitable for generating an upper bit, and a control unit suitable for determining a counting route in response to a control signal and controlling the lower and upper count signal generation units based on a determined route, wherein in a first route, the upper bit is generated in response to the lower bit, and in a second route, the lower bit is generated in response to the upper bit.

SEMICONDUCTOR DEVICE AND CONTROL METHODS THEREOF

A semiconductor device includes a first oscillator circuit, a clock monitoring circuit and a timing signal generation circuit for periodically switching the operating mode of the clock monitoring circuit to one of the first to third modes. The clock monitoring circuit includes: a clock counter configured for counting the number of oscillations of the clock signal in the first mode and configured for shifting the pulses of the input signal to the output signal at normal time in the third mode; a comparison circuit for comparing whether the count value per predetermined period by the clock counter is within an expected value in the second mode; and an edge detection circuit for detecting whether the pulses of the input signal are shifted to the output signal of the clock counter in the third mode. 1. A semiconductor device comprising:a first oscillator circuit generates an internal clock signal;a plurality of first clock monitoring circuit; anda mode switching circuit periodically switches an operation mode of the plurality of the first monitoring circuit to any of the first mode to third mode. a first clock counter;', 'a first comparison circuit; and', 'a first detection circuit;, 'wherein the first clock monitoring circuit compriseswherein one of the plurality of the first monitoring circuit executes a count processing which counts the number of the oscillation times by using the first clock counter at the first mode, executes a comparison processing which determines whether the number of the oscillation times is in a predetermined range by using the first comparison at the second mode, and executes a detection processing which detects whether a pulse from the output signal to the input signal is shifted or not by using the first detection circuit at the third mode.2. The semiconductor device according to ; a plurality of cascaded flip-flops, and', 'a plurality of selectors switch the signal is inputted to each of the plurality of flip-flops according to the ...

Apparatuses and Methods for Conversion of Radio Frequency (RF) Signals to Intermediate Frequency (IF) Signals

Various embodiments implement apparatuses and methods for conversion of radio frequency (RF) signals to intermediate frequency (IF) signals. More particularly, some embodiments are directed toward down conversion of RF signals to IF signals in a multi-band radio receiver, such as a satellite receiver, using a single oscillator for different frequency bands. For example, some of the apparatuses and methods presented are suitable for integration into monolithic RF integrated circuits in low-cost satellite receivers for home entertainment use. 1. An apparatus for conversion of radio frequency (RF) signals in a plurality of frequency bands to intermediate frequency (IF) signals , comprising:an oscillator capable of generating an oscillator frequency LO; [{'sub': 1', 'a, 'a first first-stage mixer coupled to the oscillator and configured to down convert a received RF signal RFusing the oscillator frequency LO to generate a first first-stage IF signal IF,'}, 'a first frequency divider coupled to the oscillator and configured to generate a first divided oscillation frequency by dividing the oscillator frequency LO, and', {'sub': a', '1, 'a first second-stage mixer coupled to the first frequency divider and configured to down convert the first first-stage IF signal IFusing the second divided oscillation frequency to generate a first second-stage IF signal IFusing the first divided oscillation frequency; and'}], 'a first down conversion chain, comprising [{'sub': 2', 'b, 'a second first-stage mixer coupled to the oscillator and configured to down convert a received RF signal RFusing the oscillator frequency LO, to generate a second first-stage IF signal IF,'}, 'a second frequency divider coupled to the oscillator and configured to generate a second divided oscillation frequency by dividing the oscillator frequency LO, and', {'sub': b', '2, 'a second second-stage mixer coupled to the second frequency divider and configured to down convert the second first-stage IF signal ...

Counter, pixel circuit, display panel and display device

Counter, pixel circuit, display panel, display device are provided. The counter includes: start-up circuit generating and outputting start-up signal by clock signal; M first and M second combinational logic circuits, alternate and cascaded, where M is integer no less than 1. Input terminal of first combinational logic circuit is coupled to output terminal of start-up circuit or second combinational logic circuit of previous stage, input terminal of second combinational logic circuit is coupled to output terminal of first combinational logic circuit of previous stage. Clock signal terminals of first, second combinational logic circuits are for inputting clock signal. First combinational logic circuit is for outputting clock signal in first time period and continuously outputting low level signal in second time period. Second combinational logic circuit is for outputting inverted signal of clock signal in third time period and continuously outputting low level signal in fourth time period.

COMMON MODE LOGIC BASED QUADRATURE COUPLED INJECTION LOCKED FREQUENCY DIVIDER WITH INTERNAL POWER-SUPPLY JITTER COMPENSATION

A circuit includes a clock generator, a frequency divider, and a first biasing circuit. The clock generator generates a clock signal of a first frequency. The frequency divider includes a first pair of cross coupled transistors. The frequency divider produces the clock signal of a second frequency. The first biasing circuit is coupled with the first pair of cross coupled transistors of the frequency divider. The first biasing circuit is adapted to enable a change in a transconductance of the first pair of cross coupled transistors to stabilize a phase angle between the clock signal at the first frequency and the clock signal at the second frequency. 1. A circuit , comprising:a clock generator configured to generate a clock signal of a first frequency;a frequency divider comprising a first pair of cross coupled transistors, wherein the frequency divider is configured to produce the clock signal of a second frequency; anda first biasing circuit coupled with the first pair of cross coupled transistors of the frequency divider, wherein the first biasing circuit is adapted to enable a change in a transconductance of the first pair of cross coupled transistors to stabilize a phase angle between the clock signal at the first frequency and the clock signal at the second frequency.2. The circuit of claim 1 , wherein the frequency divider further comprises a first transistor coupled to a source terminal of the first pair of cross coupled transistors claim 1 , and wherein the first biasing circuit comprises a first biasing resistor coupled in parallel to the first transistor.3. The circuit of claim 1 , wherein the frequency divider further comprises a first transistor coupled to a source terminal of the first pair of cross coupled transistors claim 1 , and wherein the first biasing circuit comprises a first biasing transistor coupled in parallel to the first transistor.4. The circuit of claim 1 , wherein the frequency divider further comprises a second pair of cross coupled ...

METHOD AND DEVICE FOR DATA TRANSMISSION AND COUNTER UNIT

The method is used for transmitting signals and data within at least one first and one second transmission phase (TP, TP), which follow one another synchronously or asynchronously, between a first communication unit (L) and at least one second communication unit (Z), which comprises a central processor unit (CPU), a memory unit (M), in which an operating program (OP) is stored, and at least one first event generator (EG), which monitors signal sequences (SL, SZ) transmitted via a transmission line (W) between the two communication units (L, Z) independently of the central processor unit (CPU) and generates event notifications (e, e) for events during the data transmission, which occur in accordance with the applied transmission protocol, which event notifications are transmitted to the central processor unit (CPU) and/or to at least one event user (EU). 115-. (canceled)16. A method for transmitting data signals within at least one first and one second transmission phase , which transmission phases follow one another synchronously or asynchronously , between a first communication unit and a second communication unit , comprising the steps of:providing in the second communication unit a central processor unit, a memory unit connected to the central processor unit in which an operating program is stored, and a first event generator;operating the first event generator to monitor signal sequences of the data signals transmitted via a transmission line between the first and second communication units independently of the central processor unit;operating the first event generator to generate event notifications for events during the data signals transmission, which events occur in accordance with an applied transmission protocol; andoperating the first event generator to transmit the event notifications to at least one of the central processor unit and a first event user in the second communication unit.17. The method according to wherein during the first transmission ...

DIGITAL FRACTIONAL FREQUENCY DIVIDER

A digital fractional frequency divider for fractionally dividing a digital frequency signal can include a plurality of clock division counter modules, a plurality of sampling modules, and a summing module. The plurality of clock division counter modules can each receive an input clock signal that is phase-shifted from a remaining plurality of input clock signals. Each clock division counter module can generate a long periodic pulse from the received input clock signal. Each sampling module can couple to an output of one of the plurality of clock division counter modules and can generate a short periodic pulse from the long periodic pulse. The summing module can sum the plurality of short periodic pulses to generate a fractional frequency clock signal. 1. A digital fractional frequency divider , comprising:a plurality of clock division counter modules each receiving an input clock signal that is phase-shifted from a remaining plurality of input clock signals, wherein each clock division counter module generates a long periodic pulse from the received input clock signal;a plurality of sampling modules, wherein each sampling module couples to an output of one of the plurality of clock division counter modules and generates a short periodic pulse from the long periodic pulse; anda summing module for summing the plurality of short periodic pulses to generate a fractional frequency clock signal.2. The digital fractional frequency divider of claim 1 , further comprising at least one tunable delay module claim 1 , wherein each tunable delay module couples to an output of the sampling module and aligns a phase of the short periodic pulse to a desired phase.3. The digital fractional frequency divider of claim 1 , wherein the tunable delay module includes a time-to-digital converter.4. The digital fractional frequency divider of claim 1 , wherein the plurality of short periodic pulses are non-overlapping periodic pulses with each other.5. The digital fractional frequency ...

HAND-ACTIVATED COUNTING DEVICE

A hand-activated counting device includes a pressing module having an elastic assembly and a counting module coupled to the pressing module. The elastic assembly includes a first deformable elastic membrane with a first connecting portion, a second deformable elastic membrane with a second connecting portion, and an insulating element. The counting module includes a housing, a circuit board supported by the housing, a counter, a power supply, and a display. The first deformable elastic membrane is positioned opposite the second deformable elastic membrane with the insulating element separating the first deformable elastic membrane from the second deformable elastic membrane. The power supply is electronically connected to the display and electronically connected to the counter by the elastic assembly. The first connecting portion is coupled to a first contact of the counter and the second connecting portion is coupled to a second contact of the counter. 1. A hand-activated counting device comprising: a first deformable elastic membrane with a first connecting portion;', 'a second deformable elastic membrane with a second connecting portion; and', 'an insulating element; and, 'a pressing module, the pressing module comprising an elastic assembly, the elastic assembly comprising a housing;', 'a circuit board supported by the housing;', 'a counter;', 'a power supply; and', 'a display;, 'a counting module coupled to the pressing module, the counting module havingwherein, the first deformable elastic membrane is positioned opposite the second deformable elastic membrane with the insulating element separating the first deformable elastic membrane from the second deformable elastic membrane;wherein, the power supply is electronically connected to the display and connected to the counter by the elastic assembly, with the display electronically connected to the counter to display a number counted by the counter;wherein, the first connecting portion is coupled to a first ...

PLC HIGH SPEED COUNTER AND OPERATING METHOD THEREOF

Disclosed herein are a PLC high speed counter and an operating method thereof. The PLC high speed counter includes: an input circuit configured to convert and output a high-speed pulse train input from an encoder into a CMOS level; a micro processor unit configured to receive the pulse train from the input circuit, generate a count value by counting the pulse train in a linear count manner and calculate a current ring count value based on the count value; and a buffer configured to receive the count value from the micro processor unit and store the same as a current linear count value, wherein, when a current value request is received from an external device, the micro processor unit determines an operation mode and transmits, if the operation mode is a ring counter mode, the current ring count value. 1. An operating method of a programmable logic controller (PLC) high speed counter configured to count a pulse and transmit a generated count value to an external device , the method comprising:counting, when the pulse is input, the pulse in a linear count manner and generating account value;storing the count value in a buffer as a current linear count value;determining, when a current value request is input from the external device, a mode of the PLC high speed counter; andtransmitting, when the mode of the PLC high speed counter is determined to be a ring counter mode as a result of the determining, a current ring count value corresponding to the current linear count value to the external device.2. The method according to claim 1 , further comprising:calculating the current ring count value based on the count value and storing the same in the buffer before performing the determining of the mode of the PLC high speed counter.3. The method according to claim 2 , wherein the transmitting of the current ring count value comprises:transmitting the current ring count value stored in the buffer to the external device.4. The method according to claim 1 , wherein the ...

QUADRATURE CLOCK GENERATING MECHANISM OF COMMUNICATION SYSTEM TRANSMITTER

A quadrature clock generating apparatus connected to a local oscillator generating an input clock signal and an inverted input clock signal includes a fractional dividing circuit and a quadrature signal generating circuit. The fractional dividing circuit is configured for receiving the input clock signal and the inverted input clock signal, and for performing frequency-division upon the input clock signal and the inverted input clock signal to generate a frequency-divided clock signal according to a fractional dividing parameter. The quadrature signal generating circuit is configured for receiving the input clock signal, the inverted input clock signal, and the frequency-divided clock signal to generate a plurality of quadrature clock signals. 1. A quadrature clock generating apparatus coupled to a local oscillator generating an input clock signal and an inverted input clock signal , the quadrature clock generating apparatus comprising:a fractional dividing circuit, configured for receiving the input clock signal and the inverted input clock signal, and for performing frequency-division upon the input clock signal and the inverted input clock signal to generate a frequency-divided clock signal according to a fractional dividing parameter; anda quadrature signal generating circuit, coupled to the fractional dividing circuit and the local oscillator, configured for receiving the input clock signal, the inverted input clock signal, and the frequency-divided clock signal to generate a plurality of quadrature clock signals.2. The apparatus of claim 1 , wherein the quadrature signal generating circuit is arranged for generating the quadrature clock signals by delaying a phase of the frequency-divided clock signal with different phase shifts according to the input clock signal and the inverted input clock signal.3. The apparatus of claim 1 , wherein the fractional dividing circuit comprises:a divider with an integer dividing parameter which is multiple of the fractional ...

SIGNAL SOURCE, TEST SYSTEM AND METHOD FOR TESTING A DEVICE UNDER TEST

A signal source is described. The signal source comprises a signal generator, a first frequency divider and a second frequency divider. The first and the second frequency divider are each connected to the signal generator. The signal generator is configured to generate a source signal having a source frequency and to selectively forward the source signal to at least one of the first frequency divider and the second frequency divider. The first frequency divider is established as an integer frequency divider and is configured to generate a first output signal from the source signal. The second frequency divider is different from the first frequency divider and is configured to generate a second output signal from the source signal, wherein a phase noise of the second output signal is considerably lower than a phase noise of the first output signal. Moreover, a test system and a method for testing a device under test are described. 1. A signal source , comprising:a signal generator, a first frequency divider and a second frequency divider, the first second frequency divider and the second frequency divider each being connected to the signal generator,the signal generator being configured to generate a source signal having a source frequency and to selectively forward the source signal to at least one of the first frequency divider or the second frequency divider;the first frequency divider being established as an integer frequency divider and being configured to generate a first output signal from the source signal; andthe second frequency divider being different from the first frequency divider and being configured to generate a second output signal from the source signal,wherein a phase noise of the second output signal is considerably lower than a phase noise of the first output signal.2. The signal source of claim 1 , wherein the second frequency divider is established as a fractional frequency divider.3. The signal source of claim 1 , wherein the signal generator ...

Synchronizing pulse-width modulation control

In described examples, a pulse width modulation (PWM) system includes an initiator and a receiver. The initiator includes an initiator counter and an initiator PWM signal generator. The initiator counter advances an initiator count in response to an initiator clock signal. The initiator PWM signal generator generates an initiator PWM signal in response to the initiator count. The receiver includes a receiver counter, a receiver PWM signal generator, and circuitry configured to reset the receiver count. The receiver counter advances a receiver count in response to a receiver clock signal. The receiver PWM signal generator generates a receiver PWM signal in response to the receiver count. The circuitry resets the receiver count in response to a synchronization signal and based on an offset.

Annular time-to-digital converter and method thereof

An annular time-to-digital converter includes a pulse shaper that shapes an input start pulse and an input stop pulse to form fixed-width pulses for output. The annular time-to-digital converter also includes at least two differential comparing units that enable, during matching enabling, triggers of the differential comparing units to set setting ends to 1. A circle counter counts the number of times a pulse is propagated in a loop. A matching enabling logical device generates a matching enabling signal, and sends the generated matching enabling signal to comparing enabling ports of the differential comparing units. At least two in-loop position encoders find a position of a first matched unit according to matching signals sent by the differential comparing units. Result recording registers record the number of circles and in-loop positions when matching occurs. High resolution is realized using a differential chain, and wafer area is saved by the annular design.

FREQUENCY DIVIDER WITH SELECTABLE FREQUENCY AND DUTY CYCLE

A frequency divider system and method includes a split-divisor frequency divider module. The split-divisor frequency divider module receives a clock signal and generates an output signal based on a first divisor and a second divisor. The clock signal and output signal each have rectangular waveforms characterized by a respective frequency and pulse width. The frequency of the output signal is a selectable integer fraction of the frequency of the clock signal, the frequency of the output signal being selected based on a sum of the first and second divisors. The pulse width of the output signal is a selectable integer number of clock cycles, the pulse width of the output signal being selected based on at least one of the first divisor and the second divisor. 1. A frequency divider system comprising:a split-divisor frequency divider module that receives a clock signal and generates an output signal based on a first divisor and a second divisor, the clock signal and output signal each having rectangular waveforms characterized by a respective frequency and pulse width; the frequency of the output signal is a selectable integer fraction of the frequency of the clock signal, the frequency of the output signal being selected based on a sum of the first and second divisors; and', 'the pulse width of the output signal is a selectable integer number of clock cycles, the pulse width of the output signal being selected based on at least one of the first divisor and the second divisor., 'wherein2. The frequency divider system of claim 1 , wherein the frequency of the output signal is times the frequency of the clock signal claim 1 , where N is the sum of the first and second divisors.30101. The frequency divider system of claim 1 , wherein the pulse width of the output signal is N or N clock cycles claim 1 , where N and N are the first and second divisors claim 1 , respectively.4. The frequency divider system of claim 1 , wherein the split-divisor frequency divider module ...

MONITORING DEVICE AND MOTOR VEHICLE INCLUDING THE SAME

A monitoring device includes a monitoring part configured to detect an abnormality of a monitoring target, a self-diagnosis part configured to diagnose whether or not the monitoring part operates normally during a period from a startup time point of a power supply to an elapse time point at which a reset release waiting time elapses, and a reset control part configured to release a reset of a reset output signal on or after the elapse time point. 1. A monitoring device , comprising:a monitoring part configured to detect an abnormality of a monitoring target;a self-diagnosis part configured to diagnose whether or not the monitoring part operates normally during a period from a startup time point of a power supply to an elapse time point at which a reset release waiting time elapses; anda reset control part configured to release a reset of a reset output signal on or after the elapse time point.2. The device of claim 1 , wherein the self-diagnosis part is further configured to repeatedly diagnose the monitoring part until the self-diagnosis part determines that the monitoring part operates normally.3. The device of claim 1 , wherein claim 1 , while sequentially switching a diagnosis target claim 1 , to which a test signal is inputted claim 1 , from among a plurality of monitoring mechanisms included in the monitoring part claim 1 , the self-diagnosis part is further configured to determine whether or not an output signal from a monitoring mechanism serving as the diagnosis target matches a first expected value and also to determine whether or not an output signal from each of the plurality of monitoring mechanisms other than the monitoring mechanism serving as the diagnosis target matches a second expected value.4. The device of claim 1 , wherein the monitoring part includes:an upper comparator configured to detect whether or not an input signal is higher than an upper threshold value; anda lower comparator configured to detect whether the input signal is lower than a ...

FILM BULK ACOUSTIC RESONATOR OSCILLATORS AND GAS SENSING SYSTEMS USING THE SAME

A resonator oscillator that may be included in a gas sensing system may include an oscillator that may be electrically connected to an external resonator through a conductive line. The oscillator may generate an oscillating signal having a frequency corresponding to a resonance frequency of the external resonator in an oscillating path. A spurious resonance removal circuit on the oscillating path may remove spurious resonance caused by the conductive line from the oscillating path. A gas sensing system may include the oscillator, a resonator that includes a sensor configured to sense a gas, and a frequency counting logic that receives the oscillating signal and a reference clock signal, performs a counting operation on the oscillating signal according to a logic state of the reference clock signal to generate a counted value, and generate a gas sensing output indicating a sensed gas based on the counted value. 1. An oscillator electrically connected to an external resonator through a conductive line , the oscillator comprising:a first cross-coupled amplifier including a first transistor having a gate connected to a first output terminal of the oscillator and a second transistor having a gate connected to a second output terminal of the oscillator, the first cross-coupled amplifier configured to establish an oscillating path; anda spurious resonance removal circuit including at least one circuit device on the oscillating path in the first cross-coupled amplifier, the spurious resonance removal circuit configured to remove spurious resonance caused by the conductive line.2. The oscillator of claim 1 , wherein claim 1 ,the oscillating path includes a first oscillating path between the gate of the first transistor and the first output terminal, andthe spurious resonance removal circuit includes a first resistor between the gate of the first transistor and the first output terminal.3. The oscillator of claim 2 , wherein the spurious resonance removal circuit further ...

VOLTAGE GLITCH DETECTION CIRCUIT

A voltage glitch detector includes a ring oscillator, a plurality of counters, a combined result circuit, and a result evaluation circuit. The ring oscillator includes a plurality of series-connected stages. An output of a last stage of the ring oscillator is coupled to an input of a first stage of the ring oscillator. Each counter of the plurality of counters has an input coupled to a node located between two stages of the plurality of series-connected stages. The combined result circuit is coupled to each of the plurality of counters. The combined result circuit combines the count values received from each counter of the plurality of counters to provide a combined result. The result evaluation circuit is coupled to compare the combined result with a reference value to determine when a voltage glitch is detected. 1. A voltage glitch detector comprising:a ring oscillator having a plurality of series-connected stages, wherein an output of a last stage of the ring oscillator is coupled to an input of a first stage of the ring oscillator;a plurality of counters, each counter of the plurality of counters having an input coupled to a node located between two stages of the plurality of series-connected stages;a combined result circuit coupled to each of the plurality of counters for combining count values received from each counter of the plurality of counters into a combined result; anda result evaluation circuit coupled to compare the combine result with a reference value to determine when a voltage glitch is detected.2. The voltage glitch detector of claim 1 , wherein the plurality of series-connected stages is equal to the plurality of counters.3. The voltage glitch detector of claim 1 , wherein the plurality of counters further comprises a first counter and a second counter coupled to a same node located between two stages of the plurality of stages claim 1 , wherein the first counter triggers upon receiving a positive clock edge at the same node and the second ...

INTEGRATED CIRCUIT, METHOD FOR DRIVING THE SAME, AND SEMICONDUCTOR DEVICE

An integrated circuit which can be switched to a resting state and can be returned from the resting state rapidly is provided. An integrated circuit whose power consumption can be reduced without the decrease in operation speed is provided. A method for driving the integrated circuit is provided. The integrated circuit includes a first flip-flop and a second flip-flop including a nonvolatile memory circuit. In an operating state in which power is supplied, the first flip-flop retains data. In a resting state in which supply of power is stopped, the second flip-flop retains data. On transition from the operating state into the resting state, the data is transferred from the first flip-flop to the second flip-flop. On return from the resting state to the operating state, the data is transferred from the second flip-flop to the first flip-flop. 1. (canceled)2. A semiconductor device comprising:a substrate including a semiconductor material; wherein the first flip-flop comprises a first transistor, and', 'wherein a first channel formation region of the first transistor is formed in the substrate; and, 'a first flip-flop on the substrate,'} wherein the second flip-flop comprises a memory circuit,', 'wherein the memory circuit comprises a second transistor, and', 'wherein a second channel formation region of the second transistor comprises an oxide semiconductor,, 'a second flip-flop over the first flip-flop,'}wherein in an operating state in which power is supplied to the first flip-flop and the second flip-flop, the first flip-flop retains data,wherein in a resting state in which supply of power to the first flip-flop and the second flip-flop is stopped, the second flip-flop retains data,wherein on transition from the operating state into the resting state, the data is transferred from the first flip-flop to the second flip-flop, andwherein on transition from the resting state into the operating state, the data is transferred from the second flip-flop to the first flip- ...

Radiation measurement device

First and second pulse height detection circuits output pulse height detection signals which rise when a detection pulse obtained from a radiation detector becomes greater than a lower threshold Lsh or an upper threshold Hsh, and fall when the detection pulse is smaller than the lower threshold Lsh or the upper threshold Hsh. Next, first and second rising and falling detection circuits detect rising and falling edges of the pulse height detection signals from the first and second pulse height detection circuits in synchronization with a clock pulse from a crystal oscillator, and a combining circuit outputs a signal corresponding to the detection pulse that is within a range between the lower threshold Lsh and the upper threshold Hsh by combining both outputs from the first and second rising and falling detection circuits, in synchronization with the clock pulse.

MULTIPLEXER BASED FREQUENCY EXTENDER

The disclosure discloses a multiplexer based frequency extender comprising a preamplifier to receive a RF input signal and output a pre-amplified RF signal, at least one frequency multiplier or at least one frequency divider, and a multiplexer. The multiplexer comprises multiple differential pairs, each differential pair comprises a corresponding bias current control circuit that switches ON or OFF a bias current flowing through a corresponding differential pair. The at least one frequency multiplier or the at least one frequency divider receives the pre-amplified RF signal and outputs a frequency-multiplied RF signal or a frequency-divided signal. The multiplexer couples to receive the pre-amplified RF signal, the frequency-multiplied RF signal and/or the frequency-divided signal, the multiplexer selects a signal from the received signals and outputs based on the selected signal a multiplexer output signal. 1. A multiplexer based frequency extender comprising:a preamplifier that receives a radio frequency (RF) input signal having an input frequency and that outputs a pre-amplified RF signal;at least one frequency multiplier coupled in series with the preamplifier, the at least one frequency multiplier receives the pre-amplified RF signal and outputs at least one frequency-multiplied RF output signal;a multiplexer coupled to receive the pre-amplified RF signal and the at least one frequency-multiplied RF signal and comprising a plurality of differential circuits and corresponding bias current control circuits, the corresponding bias current control circuits control the plurality of differential circuits such that a path through the multiplexer is defined to select the pre-amplified RF signal or the at least one frequency-multiplied RF output signal and the multiplexer outputs a multiplexer output signal based on the selected pre-amplified RF signal or the at least one frequency-multiplied signal.2. The multiplexer based frequency extender of claim 1 , wherein:each ...

CIRCUIT AGING DETECTION SENSOR BASED ON LOOKUP TABLE

The disclosure discloses a lookup table-based circuit aging detection sensor, including a control circuit, two voltage controlled oscillators (VCOs), two shaping circuits, a phase comparator, a 3-digit voter, a beat-frequency oscillator, an 8-digit counter, a latch, a lookup table array and a digital-analogue converter. The control circuit respectively connects with the phase comparator, the 3-digit voter, the 8-digit counter, the first and the second VCOs. The first and second VCOs connect with the first and second shaping circuits respectively. The first and second shaping circuits connect with the phase comparator. The phase comparator connects with the 3-digit voter. The 3-digit voter connects with the beat-frequency oscillator. The beat-frequency oscillator respectively connects with the 8-digit counter and the latch. The 8-digit counter connects with the latch. The latch connects with the lookup table array. The lookup table array connects with the digital-analogue converter. 1. A circuit aging detection sensor based on a lookup table (LUT) , comprising:a control circuit for generating a clock signal and two paths of control voltage,a first voltage controlled oscillator,a second voltage controlled oscillator,a first shaping circuit,a second shaping circuit,a phase comparator,a 3-digit voter,a beat-frequency oscillator,an 8-digit counter,a latch,a lookup table array, anda digital-analogue converter,whereinthe control circuit has a clock signal output terminal, a first voltage output terminal and a second voltage output terminal;the phase comparator has a clock terminal, a first input terminal, a second input terminal and an output terminal;the 3-digit voter has a clock terminal, an input terminal and an output terminal;the 8-digit counter has an input terminal, a setting terminal and an 8-digit parallel output terminal;the latch has a setting terminal, an 8-digit parallel input terminal and an 8-digit parallel output terminal;the lookup table array has an 8- ...

MEMORY DEVICE AND METHOD OF OPERATING THE SAME FOR LATENCY CONTROL

A memory device and method of operation for latency control in which a source clock signal having a first frequency is divided to provide a divided clock signal having a second frequency that is less than the first frequency as an input to a delay-locked loop circuit in an initialization mode. A locking operation may be performed to align the divided clock signal and a feedback clock signal that is generated by delaying the divided clock signal through the delay-locked loop circuit. A loop delay of the delay-locked loop circuit is measured after the locking operation is completed. The latency control is performed efficiently by measuring the loop delay using the divided clock signal in the initialization mode. 1. A method of operating a memory device , the method comprising:dividing a source clock signal having a first frequency into a divided clock signal for input to a delay-locked loop circuit in an initialization mode, the divided clock signal having a second frequency less than the first frequency of the source clock signal;aligning the divided clock signal and a feedback clock signal by performing a locking operation, wherein the feedback clock signal is generated by delaying the divided clock signal through the delay-locked loop circuit; andmeasuring a loop delay of the delay-locked loop circuit after performing the locking operation, the loop delay corresponding to a delay of the feedback clock signal with respect to the divided clock signal.2. The method of claim 1 , wherein performing the locking operation includes:aligning the divided clock signal and the feedback clock signal in same phases.3. The method of claim 2 , wherein the loop delay comprises an even number multiple of a clock cycle period of the source clock signal.4. The method of claim 1 , wherein measuring the loop delay includes:disabling the divided clock signal during a freezing window time period; andcounting a number of clock cycles of the feedback clock signal during the freezing window ...

ELECTRONIC CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT AND MONITORING CIRCUIT MOUNTED WITH THE SAME, AND ELECTRONIC DEVICE

An electronic circuit is configured to output an output signal after elapse of a predetermined time from a received trigger signal, and includes an oscillator configured to output a pulse signal having a predetermined oscillation frequency; a counter circuit configured to count the pulse signal from the oscillator upon receiving the trigger signal and to output the output signal in response to a count value reaching a predetermined value; and a trimming circuit including a plurality of trimming elements which includes a cuttable conductive part and configured to output a selection signal corresponding to a trimming element having a cut conductive part. In the trimming circuit, the trimming element, which corresponds to the oscillation frequency of the pulse signal output from the oscillator among the plurality of trimming elements, is cut, and the counter circuit is configured to set the predetermined value according to the selection signal. 1. An electronic circuit configured to output an output signal after elapse of a predetermined time from a received signal , the electronic circuit comprising:an oscillator configured to output a pulse signal;a counter circuit configured to count the pulse signal from the oscillator and to output the output signal; anda trimming circuit including a plurality of trimming elements which includes a plurality of cuttable conductive parts and configured to output a selection signal corresponding to a trimming element having a cut conductive part,wherein the counter circuit is configured to set a count value according to the selection signal.2. The electronic circuit of claim 1 , wherein the counter circuit is arranged adjacent to the oscillator claim 1 , andwherein the trimming circuit is arranged adjacent to the counter circuit.3. The electronic circuit of claim 2 , wherein the counter circuit is arranged between the oscillator and the trimming circuit.4. The electronic circuit of claim 1 , wherein the trimming circuit is arranged ...

FRACTIONAL-N SYNTHESIZER

One embodiment of the present invention provides a synthesizer. The synthesizer includes one or more tunable oscillators, a frequency-dividing circuit coupled to the tunable oscillators, and a multiplexer coupled to the frequency-dividing circuit. The frequency-dividing circuit includes a number of frequency dividers, and is configured to generate a number of frequency-dividing outputs. At least one frequency-dividing output has a different frequency division factor. The multiplexer is configured to select a frequency-dividing output 1. A synthesizer configured to output a sinusoidal wave , comprising:one or more tunable oscillators;a frequency-dividing circuit coupled to the tunable oscillators, wherein the frequency-dividing circuit is configured to generate a number of frequency-dividing outputs; anda multiplexer coupled to the frequency-dividing circuit, wherein the multiplexer is configured to select, from the frequency-dividing outputs, a frequency-dividing output as the sinusoidal wave outputted by the synthesizer.2. The synthesizer of claim 1 , wherein the frequency-dividing circuit comprises a plurality of frequency-diving branches claim 1 , and wherein a respective frequency-dividing branch includes one or more frequency dividers claim 1 , and wherein the frequency-dividing branch is configured to output a sinusoidal wave whose frequency is a fraction of an output of the tunable oscillators.3. The synthesizer of claim 1 , wherein the tunable oscillators are voltage-controlled oscillators (VCOs).4. The synthesizer of claim 3 , wherein at least one of the VCOs includes a complementary metal-oxide semiconductor (CMOS) capacitor.5. The synthesizer of claim 4 , wherein the oscillators claim 4 , the frequency-dividing circuit claim 4 , and the multiplexer are integrated onto a single application-specific integrated circuit (ASIC) chip.6. The synthesizer of claim 1 , wherein the frequency-dividing circuit includes multiple frequency dividers that have a same ...

CLOCK GENERATION CIRCUIT

The present technique relates to a clock generation circuit including a phase difference comparison circuit configured to compare a phase of each of an input clock signal and a feedback signal, and provides a phase difference signal indicating a phase difference between the input clock signal and the feedback signal, a filter circuit configured to suppress a high frequency component in the phase difference signal, an output circuit configured to modulate the phase difference signal in such a manner as to decrease a noise component of a low frequency band and increase a noise component of a high frequency band, and generate and output an output clock signal from the modulated phase difference signal and a reference clock signal, and a frequency dividing circuit configured to divide a frequency of the output clock signal, at a predetermined frequency dividing ratio, and feed it back to the phase comparison circuit. 1. A clock generation circuit comprising:a phase difference comparison circuit configured to compare a phase of each of an input clock signal and a feedback signal which have been received, and provides a phase difference signal indicating a phase difference between the input clock signal and the feedback signal;a filter circuit configured to suppress a high frequency component, of which frequency is higher than a predetermined cutoff frequency, in the phase difference signal;an output circuit configured to modulate the phase difference signal, of which high frequency component is suppressed, in such a manner as to decrease a noise component of a low frequency band and increase a noise component of a high frequency band, and generate and output an output clock signal from the modulated phase difference signal and a reference clock signal; anda frequency dividing circuit configured to divide a frequency of the output clock signal, which has been output, at a predetermined frequency dividing ratio, and feed the output clock signal back to the phase comparison ...

State Machine for Low-Noise Clocking of High Frequency Clock

Methods, apparatus, and fabrication techniques relating to management of noise arising from capacitance in a clock tree of an integrated circuit. In some embodiments, the methods comprise receiving a signal to adjust a clock having a first rate to a second rate; and ramping, in response to receiving the signal, the clock from the first rate to the second rate, wherein the ramping comprises changing the frequency of the clock to at least one third rate between the first and second rates. 1. A method , comprising:receiving a signal to adjust a clock having a first rate to a second rate, wherein the first rate is zero and the second rate is a reference clock rate, and wherein the first rate, the second rate, and a third rate are related to the reference clock rate such that the first rate equals a first multiplier times the reference clock rate, the second rate equals a second multiplier times the reference clock rate, and the third rate equals a third multiplier times the reference clock rate;ramping, in response to receiving the signal, the clock from the first rate to the second rate, wherein the ramping comprises changing the frequency of the clock to at least one third rate between the first and second rates, wherein ramping comprises ramping up the clock from the reference clock rate divided by 7 to the reference clock rate divided by 2;dithering up the clock from the reference clock rate divided by 2 to the reference clock rate; andoperating the clock at the second rate.2. The method of claim 1 , wherein changing the frequency of the clock comprises changing a multiplier of the first rate.34.-. (canceled)5. The method of claim 1 , wherein each of the first multiplier claim 1 , the second multiplier claim 1 , and the third multiplier are independently an integer from 0 to about 10 or the inverse of an integer from 1 to about 10.6. (canceled)7. The method of claim 1 , wherein the ramping comprises sequentially changing the frequency of the clock to a plurality of ...

SEMICONDUCTOR APPARATUS

A semiconductor apparatus includes a pipe input/output signal generation block configured to generate a plurality of pipe input signals and a plurality of pipe output signals according to a pipe enable signal, and be initialized according to an error detection signal; a pipe latch group including a plurality of pipe latches, each of the plurality of pipe latches being configured to receive and store an input signal according to a corresponding pipe input signal and output a stored signal as an output signal according to a corresponding pipe output signal; and an error detection block configured to generate the error detection signal according to a pipe end signal, the pipe enable signal, the plurality of pipe input signals and the plurality of pipe output signals. 1. A semiconductor apparatus comprising:a pipe input/output signal generation block configured to generate a plurality of pipe input signals and a plurality of pipe output signals according to a pipe enable signal, and be initialized according to an error detection signal;a pipe latch group including a plurality of pipe latches, each of the plurality of pipe latches being configured to receive and store an input signal according to a corresponding pipe input signal and output a stored signal as an output signal according to a corresponding pipe output signal; andan error detection block configured to generate the error detection signal according to a pipe end signal, the pipe enable signal, the plurality of pipe input signals and the plurality of pipe output signals.2. The semiconductor apparatus according to claim 1 , wherein each of the plurality of pipe latches are initialized according to the error detection signal.3. The semiconductor apparatus according to claim 1 , wherein the pipe input/output signal generation block comprises:a pipe input signal generation unit configured to sequentially enable the plurality of pipe input signals in response to the pipe enable signal; anda pipe output signal ...

Automatic Protection Against Runt Pulses

An apparatus includes an adjustment circuit configured to receive a pulsed-width modulation (PWM) input, generate an adjusted PWM signal based upon the PWM input, and determine that a first pulse of the PWM input is shorter than a runt signal limit. The adjustment circuit is further configured to, in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit, and output the adjusted PWM signal to an electronic device. 1. An apparatus , comprising: receive a pulsed-width modulation (PWM) input;', 'generate an adjusted PWM signal based upon the PWM input;', 'determine that a first pulse of the PWM input is shorter than a runt signal limit;', 'in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit; and', 'output the adjusted PWM signal to an electronic device., 'an adjustment circuit configured to2. The apparatus of claim 1 , further comprising a counter claim 1 , the counter configured to begin a determination of a length of the first pulse of the PWM input after a prescribed delay between the PWM input and the output of the adjusted PWM signal.3. The apparatus of claim 1 , where the adjustment circuit is further configured to claim 1 , based upon extension of the first pulse claim 1 , shorten a second pulse of the PWM input as included in the adjusted PWM signal claim 1 , the second pulse immediately following the first pulse.4. The apparatus of claim 1 , wherein:the PWM input includes a PWML signal and a PWMH signal;the adjusted PWM signal includes an adjusted PWML signal and an adjusted PWMH signal;the PWMH signal and the PWML signal to include PWM signals and to be complements of each other during a plurality of clock cycles;the adjusted PWMH signal and the adjusted PWML signal to include PWM signals and to be complements of each other during a plurality of clock cycles; andthe ...

Correction circuit and real-time clock circuit

The present invention provides a correction circuit. The correction circuit includes a frequency dividing circuit, a frequency dividing coefficient operation circuit, a built-in temperature collection circuit, and a power-on and power-off detection circuit. The built-in temperature collection circuit is configured to collect a temperature of the chip; the power-on and power-off detection circuit is configured to detect power-on and power-off of the chip; the frequency dividing coefficient operation circuit is configured to calculate, according to the temperature of the chip collected by the built-in temperature collection circuit when the power-on and power-off detection circuit detects that the chip is powered off, a frequency dividing coefficient, and output the frequency dividing coefficient to the frequency dividing circuit; and the frequency dividing circuit is configured to provide, according to the frequency dividing coefficient output by the frequency dividing coefficient operation circuit, a timing pulse for a real-time clock.

Clock signal generating circuit, image forming apparatus, and clock signal generating method of clock signal generating circuit

A clock signal generating circuit that generates a clock signal, the clock signal generating circuit including a clock signal generator configured to generate a reference clock signal; and a plurality of dividers to which the reference clock signal is to be input. A division ratio of at least one of the plurality of dividers varies based on division ratio data that defines the division ratio of the at least one of the plurality of dividers. The division ratio data represents a value that fluctuates around reference division ratio data with respect to time.

DIGITAL SERIAL READ-OUT ARCHITECTURE

Techniques are described for implementing read-out architectures to support high-speed serialized read-out of a large number of digital bit values, such as for high-resolution pixel conversions in CMOS image sensor applications. For example, outputs from a large number of digital data sources (e.g., counters) are coupled with transmission gates of the read-out architecture, and the transmission gates are sequentially enabled, thereby shifting in bit data from the data sources one at a time. The transmission gates are grouped into gate groups. For each gate group, embodiments seek balance total path delay across the gate groups by controlling clock and data path delays to be inversely related, and ensuring that total path delays for all gate groups are within a single clock period. Some embodiments include a partitioned bus for further gate group-level control over the path delay and data bus capacitance. 1. A system for serialized read-out of bit data from a plurality of digital data sources , the system comprising:an output flop configured to output a serialized output data signal responsive to a buffered data signal and an input clocking signal;a data path comprising a plurality of gate groups, each having a respective subset of a plurality of transmission gates, each transmission gate to selectively output bit data from a respective one of a plurality of digital data sources in response to assertion of a respective gate enable signal, the data path providing the data signal from the respective gate outputs of the transmission gates to the output flop by adding an amount of data path delay to the data signal to generate the buffered data signal;a clock delay block configured to generate a buffered clocking signal by adding a amount of clock path delay to the input clocking signal; anda gate selector block coupled with the clock delay block to sequentially assert each respective gate enable signal in response to the buffered clocking signal, such that a selected ...

MULTI-MODULUS FREQUENCY DIVIDERS

Various embodiments relate to multi-modulus frequency dividers, devices including the same, and associated methods of operation. A method of operating a multi-modulus divider (MMD) may include receiving, at the MMD, an input signal at a first frequency. The method may also include generating, via the MMD, an output signal at a second, lower frequency based on a divisor value. Further, the method may include receiving, at the MMD, an integer value. Moreover, the method may include setting the divisor value equal to the integer value in response to a current state of the MMD matching a common state for the MMD, wherein the MMD is configured to enter the common state regardless of the divisor value. 1. A method of operating a multi-modulus divider , the method comprising:receiving, at a multi-modulus divider (MMD), an input signal at a first frequency;generating, via the MMD, an output signal at a second, lower frequency based on a divisor value;receiving, at the MMD, an integer value; andsetting the divisor value equal to the integer value in response to a current state of the MMD matching a common state for the MMD, the MMD configured to enter the common state regardless of the divisor value.2. The method of claim 1 , further comprising detecting a current state of the MMD.3. The method of claim 2 , wherein detecting the current state of the MMD comprises sensing at least one signal within the MMD.4. The method of claim 2 , further comprising:comparing the current state of the MMD to the common state;generating, via a first logic gate, a first digital signal in response to the current state matching the common state; andgenerating, via the first logic gate, a second, different digital signal in response to the current state not matching the common state.5. The method of claim 4 , further comprising generating claim 4 , via a second logic gate claim 4 , a third digital signal in response to receipt of at least one of the first digital signal and a reset signal claim 4 ...

DOUBLE DATA RATE COUNTER, AND ANALOG-TO-DIGITAL CONVERTER AND CMOS SENSOR INCLUDING THE SAME

A double data rate (DDR) counter includes a first control block suitable for toggling a counter clock according to a count mode signal and a previous state value of a sampling block; a second control block suitable for determining whether to toggle a clock signal inputted to a counting block corresponding to an (LSB+1) bit or higher; a third control block suitable for determining an enable period of the counting block; the sampling block suitable for sampling a state of the clock signal and outputting an LSB value, when an input signal transits; and the counting block suitable for performing counting according to output signals of the second and third control blocks and outputting a counter output signal having the (LSB+1) bit or higher. 1. A double data rate (DDR) counter comprising:a first control block suitable for toggling a counter clock according to a count mode signal and a previous state value of a sampling block;a second control block suitable for determining whether to toggle a clock signal inputted to a counting block corresponding to an (LSB+1) bit or higher;a third control block suitable for determining an enable period of the counting block;said sampling block suitable for sampling a state of the clock signal and outputting an LSB value when an input signal transits; andsaid counting block suitable for performing counting according to output signals of the second and third control blocks and outputting a counter output signal having the (LSB+1) bit or higher.2. The DDR counter of claim 1 , wherein the first and second control blocks determine whether to toggle the clock signal between first and second counting operations.3. The DDR counter of claim 1 , wherein the counting block performs counting at rising edges of the clock signal from the (LSB+1) bit during a first counting operation claim 1 , and performs counting at falling edges of the clock signal from the (LSB+1) bit during a second counting operation.4. The DDR counter of claim 1 , wherein the ...

INTEGRATED CIRCUIT HAVING TRIM FUNCTION FOR COMPONENT

Disclosed is an integrated circuit having a trim function for an embedded analog component or digital component. The integrated circuit includes a trim value generator configured to provide a varying trim value, a measurement target selected from a digital component and an analog component and configured to provide a measured value as a result of an internal operation corresponding to the trim value, a determination unit configured to determine the measured value based on a reference value received from the outside and to provide a trim control signal when the measured value corresponds to a preset target value, and a storage configured to store a current trim value as a measured result value in response to the trim control signal. 1. An integrated circuit having a trim function for a component , comprising:a trim value generator configured to provide a varying trim value;a measurement target selected from a digital component and an analog component and configured to provide a measured value as a result of an internal operation corresponding to the trim value;a determination unit configured to determine the measured value based on a reference value received from an outside and to provide a trim control signal when the measured value corresponds to a preset target value; anda storage configured to store a current trim value as a measured result value in response to the trim control signal.2. The integrated circuit of claim 1 , wherein the trim value generator provides a digital value as the trim value.3. The integrated circuit of claim 1 , wherein the trim value generatorreceives the trim control signal, andprovides the current trim value to the storage in response to the trim control signal.4. The integrated circuit of claim 1 , wherein:the measured result value is set for an internal operation of the measurement target; andthe measurement target performs the internal operation based on the measured result value after the measured result value is set.5. An ...

FREQUENCY DIVIDER AND A TRANSCEIVER INCLUDING THE SAME

A frequency divider may include: a core circuit including a first flip-flop loop and a second flip-flop loop, wherein each of the first flip-flop loop and the second flip-flop loop divides a frequency of a clock signal received via a control terminal of a flip-flop, wherein the core circuit is configured to: output a frequency-divided signal, based on a first signal output by the first flip-flop loop and a second signal output by the second flip-flop loop, the first and second signals having same frequency-division ratios and different phases, and feed back the frequency-divided signal via an input terminal of each of the first and second flip-flop loops; a duty correction circuit that receives the frequency-divided signal and outputs a differential output signal that is generated by correcting a duty ratio of the frequency-divided signal; and an output circuit that outputs a first output signal, which is a signal amplified from the differential output signal, and a second output signal that is a quadrature signal of the first output signal. 1. A frequency divider , comprising:a core circuit comprising a first flip-flop loop and a second flip-flop loop, wherein each of the first flip-flop loop and the second flip-flop loop divides a frequency of a clock signal received via a control terminal of a flip-flop, wherein the core circuit is configured to:output a frequency-divided signal, based on a first signal output by the first flip-flop loop and a second signal output by the second flip-flop loop, the first and second signals having same frequency-division ratios and different phases, and feed back the frequency-divided signal via an input terminal of each of the first and second flip-flop loops;a duty correction circuit that receives the frequency-divided signal and outputs a differential output signal that is generated by correcting a duty ratio of the frequency-divided signal; andan output circuit that outputs a first output signal, which is a signal amplified ...

ASSEMBLY OF INTEGRATED CIRCUIT MODULES AND METHOD FOR IDENTIFYING THE MODULES

An assembly including a carrier substrate and at least one group of interconnected integrated circuit modules mounted thereon is disclosed. The modules are provided with a connection for transmitting a clock signal through the group of interconnected modules. The modules are also provided with digital input ports and output ports and a logic circuit configured for identifying the position of the modules in the group on the basis of a count of the clock pulses, and on the basis of the logic state of the input and output ports. In one aspect, a method involves the transfer of a token in the form of one or more logic states, through the group of modules, from a first module to a last module, resulting in the identification of all modules in a progressive manner. 1. An assembly comprising a carrier substrate and on the substrate one or more groups of interconnected integrated circuit modules , each group comprising a first module , a last module , and one or more intermediate modules , wherein each module comprises:a clock connection;a logic circuit connected to the clock connection and provided with a counter for counting the pulses of a clock signal transmitted through the clock connection;at least an input port and at least an output port , the input and output ports being coupled to the logic circuit, in such a manner that a logic state of the input port can be read by the circuit and a logic state of the output port can be driven by the circuit; anda memory for storing at least an identifier of the module,wherein for each group of modules:the carrier substrate comprises circuitry for accessing the input port of the first module of the group;the clock connections are interconnected to form a single connection from the first module to the last module of the group;except for the last module of the group, the output port on each module is directly connected to the input port of a module adjacent to it, so that the group of modules forms a chain of sequentially ...

APPARATUS FOR SIMPLIFICATION OF INPUT SIGNAL

The present disclosure relates to an apparatus for simplification of input signal configured to simplify a process of microprocessor and to enhance a speed by transforming six input modes of 1-phase/2-input/1-multiplication mode, 1-phase/2-input/2-multiplication mode, CW/CCW mode, 2-phase/1-multiplication mode, 2-phase/2-multiplication mode and 2-phase/4-multiplication mode to a same shape according to types of encoder connected to a PLC high speed counter, and transmitting to the microprocessor, and by adding the six types of input modes to a logic gate circuit of a high speed counter input circuit. 1. An apparatus for simplification of input signal configured to input , to an MPU (Micro Processing Unit) , an output of an input circuit at a PLC high speed counter module by converting the input to a single signal , the apparatus comprising:a first detector configured to output a single pulse in response to a rising edge or a falling edge by detecting the rising edge or the falling edge of a reference signal, which is a reference of adding or deducting calculation in response to an operation mode of the high speed counter module;a second detector configured to detect, from an output of the first detector, a pulse of rising edge or falling edge configured to perform an actual adding or deducting calculation in response to an operation mode of the high speed counter module; anda switching unit configured to output an output of the second detector using the adding or deducting calculation.2. The apparatus of claim 1 , wherein the first detector includes a first oscillation unit configured to output a signal pulse by detecting a rising edge of a first input claim 1 , a second oscillation unit configured to output a signal pulse by detecting a falling edge of a first input claim 1 , a third oscillation unit configured to output a signal pulse by detecting a rising edge of a second input claim 1 , a fourth oscillation unit configured to output a signal pulse by detecting a ...

LOAD COMPENSATION TO REDUCE DETERMINISTIC JITTER IN CLOCK APPLICATIONS

A method for reducing deterministic jitter in a clock generator includes providing a load current through a regulated voltage node to a circuit responsive to a divide ratio. The method includes providing an auxiliary current through the regulated voltage node. The auxiliary current has a first current level during a first period corresponding to a first value of the divide ratio and the auxiliary current has a second current level during a second period corresponding to a second value of the divide ratio. 1. A method for reducing deterministic jitter in a clock generator , the method comprising:providing a load current through a regulated voltage node to a circuit responsive to a divide ratio; andproviding an auxiliary current through the regulated voltage node, the auxiliary current having a first current level during a first period corresponding to a first value of the divide ratio and the auxiliary current having a second current level during a second period corresponding to a second value of the divide ratio.2. The method claim 1 , as recited in claim 1 , wherein the method further comprisesproviding a frequency modulated clock signal based on the load current, the frequency modulated clock signal having a frequency vacillating between a first frequency and a second frequency,wherein the auxiliary current is load compensation for a load difference generated by providing the frequency modulated clock signal, the load difference being a difference between a first load corresponding to the first frequency and a second load corresponding to the second frequency.3. The method claim 2 , as recited in claim 2 ,wherein providing the frequency modulated clock signal comprises frequency dividing an input clock signal based on a regulated voltage on the regulated voltage node and a divide value vacillating between a first divide value and a second divide value,wherein the providing the regulated voltage includes providing a regulated current through the regulated voltage ...

DITHERED M BY N CLOCK DIVIDERS

A method for dithering a fractional clock divider includes generating a first clock enable sequence based on a seed pattern of M ones and N minus M zeros, selecting a cyclic rotation of the seed pattern after N input clock cycles, and generating a second clock enable sequence based on the cyclic rotation. A clock gate receives the input clock signal and the clock enable sequences and outputs M clock cycles for every N input clock cycles. A random number generator indicates the cyclic rotation of the seed pattern. The seed pattern can be replaced with an updated seed pattern of M ones and N minus M zeros in a different order. In some examples, the clock enable sequence is generated using a cyclic shift register containing the seed pattern and a multiplexor. In other examples, the clock enable sequence is generated using a modulo N counter and a comparator. 1. A method for dithering a fractional clock divider , comprising: wherein the seed pattern comprises M ones and N minus M zeros, and', 'wherein the clock gate receives an input clock signal and a clock enable sequence and outputs M clock cycles for every N input clock cycles;, 'generating a first clock enable sequence for a clock gate based on a seed pattern,'}selecting, after N input clock cycles, a cyclic rotation of the seed pattern; andgenerating a second clock enable sequence for the clock gate based on the cyclic rotation of the seed pattern.2. The method of claim 1 , wherein selecting claim 1 , after N input clock cycles claim 1 , the cyclic rotation of the seed pattern comprises:comparing a value of a modulo N counter using a comparator, wherein over N input clock cycles, an output signal from the comparator comprises a value of one for one input clock cycle and a value of zero for a remainder of the N input clock cycles; andin response to the output signal from the comparator having a value of one, generating a random number between zero and N minus one, wherein the random number indicates the cyclic ...

SYSTEM AND METHOD FOR PROVIDING PROGRAMMABLE SYNCHRONOUS OUTPUT DELAY IN A CLOCK GENERATION OR DISTRIBUTION DEVICE

A clock frequency division circuit receives delay value, synchronization signal, and external clock signal of a given frequency. The clock division circuit includes (a) a decode circuit receiving delay value and providing set of initial count values; (b) one or more counters each receiving input clock signal derived from the external clock signal and providing frequency divided output signal having a frequency a fraction of the given frequency, and each receiving a corresponding one of the initial count values, and wherein, subsequent to detecting a transition in the synchronization signal, each counter provides transition in the frequency divided output signal after a time period represented by corresponding initial count value; and (c) synchronization circuit that is reset by the synchronization signal, the synchronization circuit providing a gating signal enabling output of the frequency divided output signal after expiration of initial count value. The one or more counters may be cascaded. 1. A clock frequency division circuit , which receives a delay value , a synchronization signal , and an external clock signal of a given frequency , comprising:a decode circuit receiving the delay value and providing a set of initial count values;one or more counters each (a) being associated with a corresponding programmable divisor, (b) receiving an input clock signal derived from the external clock signal and a corresponding one of the initial count values, and (c) providing a frequency divided output signal that has a frequency that is the given frequency divided by the corresponding programmable divisor, wherein, subsequent to detecting a transition in the synchronization signal, each counter provides a transition in the respective frequency divided output signal after a time period represented by the corresponding initial count value; anda synchronization circuit that is reset by the synchronization signal, the synchronization circuit providing a gating signal that ...

MODULUS DIVIDER WITH DETERMINISTIC PHASE ALIGNMENT

An apparatus includes a plurality of latches and a plurality of logic gates. Each latch may be setable and resettable. The logic gates may be connected to the latches to form a multi-modulus divider that generates an output clock signal by dividing an input clock signal in response to a command signal. Each latch may be commanded into a corresponding initial state while the command signal is in an initialization state. Each latch is generally free to change states while the command signal is in a run state. A modulus division operation of the multi-modulus divider may start upon an initial edge of the input clock signal after the command signal changes from the initialization state to the run state. 1. An apparatus comprising:a plurality of latches each being setable and resettable; anda plurality of logic gates connected to said latches to form a multi-modulus divider that generates an output clock signal by dividing an input clock signal in response to a command signal, wherein (i) each of said latches is commanded into a corresponding initial state while said command signal is in an initialization state, (ii) each of said latches is free to change states while said command signal is in a run state and (iii) a modulus division operation of said multi-modulus divider starts upon an initial edge of said input clock signal after said command signal changes from said initialization state to said run state.2. The apparatus according to claim 1 , wherein said output clock signal always has a correct phase alignment to said initial edge of said input clock signal.3. The apparatus according to claim 1 , wherein a particular one of said logic gates receives both a feedback signal generated external to said multi-modulus divider and an intermediate clock signal generated by one of said latches.4. The apparatus according to claim 3 , wherein said intermediate clock signal transitions in response to said initial edge of said input clock signal.5. The apparatus according to ...

Time to digital converter, phase difference pulse generator, radio communication device, and radio communication method

A time to digital converter has a counter to measure the number of cycles of a first signal, a first phase difference detector to generate a phase difference signal having a pulse width corresponding to a phase difference, a first capacitor to be charged with an electric charge, a second capacitor including capacitance N times the capacitance of the first capacitor, the N being a real number larger than 1, a comparator to compare a charge voltage of the first capacitor and a charge voltage of the second capacitor, a first charge controller to continue to charge the second capacitor until the comparator detects that the charge voltage of the second capacitor has reached the charge voltage of the first capacitor or more, and a first phase difference arithmetic unit to operate the phase difference between the first signal and the second signal.

WINDOW TYPE WATCHDOG TIMER AND SEMICONDUCTOR DEVICE

A window type watchdog timer includes a frequency dividing circuit for generating a frequency-divided clock signal by dividing a frequency of a reference clock signal; a monitoring circuit for monitoring occurrence of a first error in which clear control from a target device is interrupted for a first time or more, and occurrence of a second error in which an interval between two consecutive clear controls from the target device is shorter than a second time shorter than the first time, based on the frequency-divided clock signal; and outputting an error signal when the first error or the second error is detected; and a setting circuit for variably setting the first time and the second time by variably setting a frequency division ratio in the frequency dividing circuit and variably setting a detection condition of the first error and the second error. 1. A window type watchdog timer for monitoring a target device , comprising:an oscillation circuit configured to generate a predetermined reference clock signal;a frequency dividing circuit configured to generate a frequency-divided clock signal by dividing a frequency of the reference clock signal; monitor occurrence of a first error in which clear control from the target device is interrupted for a first time or more, and occurrence of a second error in which an interval between two consecutive clear controls from the target device is shorter than a second time, which is shorter than the first time, based on the frequency-divided clock signal; and', 'output a predetermined error signal when the first error or the second error is detected; and, 'a monitoring circuit configured toa setting circuit configured to variably set the first time and the second time by variably setting a frequency division ratio in the frequency dividing circuit and variably setting a detection condition of the first error and the second error.2. The window type watchdog timer of claim 1 , wherein the setting circuit is configured to variably ...

PULSE COUNTING CIRCUIT

A circuit includes a random oscillation number generator (RONG) configured to generate first and second pulse signals at first and second RONG outputs. A first counter is coupled to the first RONG output and generates a first count at a first counter output. A second counter is coupled to the second RONG output and generates a second count at a second counter output. A selection circuit is coupled to the first and second counter outputs and to the first and second RONG outputs. A first pulse shaper is connected between the first RONG output and the first counter, and a second pulse shaper is connected between the second RONG output and the second counter. 1. A circuit , comprising:a random oscillation number generator (RONG) configured to generate first and second pulse signals at first and second RONG outputs, respectively;a first counter coupled to the first RONG output and configured to generate a first count at a first counter output;a second counter coupled to the second RONG output and configured to generate a second count at a second counter output; anda selection circuit coupled to the first and second counter outputs and to the first and second RONG outputs and configured to select one of the first and second counts.2. The circuit of claim 1 , further comprising a first pulse shaper connected between the first RONG output and the first counter claim 1 , and a second pulse shaper connected between the second RONG output and the second counter.3. The circuit of claim 2 ,wherein the first pulse shaper comprises:a first flip flop having a clock input connected to the first RONG output, a D input connected to a supply voltage, a Q output connected to the first counter, a complemented Q output, and a reset input;a first delay circuit having an input coupled to the complemented Q output; anda first logic gate having a first input coupled to the first delay circuit, a second input coupled to a reset signal, and an output coupled to the reset input of the first flip ...

CIRCUIT SYSTEM FOR CONTROLLING AN ELECTRICAL CONSUMER

A circuit system for controlling an electrical consumer, the circuit system including an up-down counter, and the circuit system being configured to generate a control signal for controlling the electrical consumer, in particular for shutting off the electrical consumer, as a function of a counter content of the up-down counter. The circuit system includes a controllable clock divider circuit, with the aid of which the circuit system is configured to predefine a counting direction and a counting speed of the up-down counter as a function of at least one variable characterizing an actual current and/or a nominal current of the electrical consumer. 113-. (canceled)14. A circuit apparatus for controlling an electrical consumer , comprising: an up-down counter, wherein the circuit system is configured to generate a control signal for controlling the electrical consumer, in particular for shutting off the electrical consumer, as a function of a counter content of the up-down counter; and', 'a controllable clock divider circuit, by which the circuit system is configured to predefine a counting direction and a counting speed of the up-down counter as a function of at least one variable characterizing an actual current and/or a nominal current of the electrical consumer., 'a circuit system, including15. The circuit apparatus of claim 14 , wherein the circuit system is configured to predefine at least one division factor of the controllable clock divider circuit as a function of the at least one variable characterizing the actual current and/or the nominal current of the electrical consumer.16. The circuit apparatus of claim 15 , wherein the division factor is incrementally variable by a respective factor of 2.17. The circuit apparatus of claim 14 , wherein the controllable clock divider circuit includes a first and a second controllable clock divider claim 14 , and wherein the first controllable clock divider is configured to clock the up-down counter for counting up claim ...

PULSE WIDTH MODULATION SIGNAL GENERATION CIRCUIT AND METHOD

A pulse width modulation signal generation circuit and a pulse width modulation signal generation method are provided. A clock generator is configured for generating a clock signal including a plurality of pulses. The counting unit is coupled to the clock generator, and configured for storing a period parameter and outputting a counting value by counting the pulses of the clock signal based on the period parameter and a bidirectional counting mode. The comparing unit is coupled to the counting unit and is configured for comparing the counting value and a comparing threshold to output a level control signal. The signal generating unit is coupled to the comparing unit and configured for generating a pulse width modulation signal according to the level control signal. When the period parameter is odd, the counting value outputted by the counting unit is equal to a middle value in the two continuous clock cycles. 1. A pulse width modulation signal generation circuit , comprising:a clock generator, generating a clock signal comprising a plurality of pulses;a counting unit, coupled to the clock generator, storing a period parameter, and counting the pulses of the clock signal based on the period parameter and a bidirectional counting mode to output a counting value;a comparing unit, coupled to the counting unit and comparing the counting value and a comparing threshold to output a level control signal accordingly; anda signal generating unit, coupled to the comparing unit and generating a pulse width modulation signal based on the level control signal, wherein when the period parameter is an odd number, the counting value output by the counting unit is a middle value in two consecutive clock cycles.2. The pulse width modulation signal generation circuit as claimed in claim 1 , wherein when the period parameter is an even number claim 1 , the counting value output by the counting unit is the middle value in one single clock cycle.3. The pulse width modulation signal ...

ANALOG COUNTER WITH PULSED CURRENT SOURCE FOR A DIGITAL PIXEL

An analog counter circuit for use with a digital pixel includes an input; an output; a first inverter connected to the input that produces on a first inverter output a time delayed inverted signal (RP*) from an input signal received at the input; a second inverter connected to the first inverter output that produces a time delayed signal (RP) at a second inverter output from the input signal and that is delayed relative to RP* and a control switch connected between a source voltage and a floating node. The control switch is controlled by the signal RP* on the first inverter output. The analog counter also includes a feedback capacitor connected between the second inverter output and the floating node; an accumulating capacitor that accumulates at least some of a charge that passes through the control switch; and an injection switch connected between the control switch and the accumulating capacitor. 1. An analog counter circuit for use with a digital pixel , the analog counter circuit comprising:an input;an output;a first inverter connected to the input that produces on a first inverter output a time delayed inverted signal (RP*) from an input signal received at the input;a second inverter connected to the first inverter output that produces a time delayed signal (RP) at a second inverter output from the input signal and that is delayed relative to RP*;a control switch connected between a source voltage and a floating node, wherein the control switch is controlled by the signal RP* on the first inverter output;a feedback capacitor connected between the second inverter output and the floating node;an accumulating capacitor that accumulates at least some of a charge that passes through the control switch; andan injection switch connected between the control switch and the accumulating capacitor.2. The analog counter circuit of claim 1 , wherein the accumulating capacitor is connected between the output and a reset voltage.3. The analog counter circuit of claim 2 , ...

APPARATUS AND METHODS FOR SINGLE PHASE SPOT CIRCUITS

Provided herein are apparatus and methods for single phase spot circuits. In certain implementations, a single phase spot circuit propagates a spot from input to output in response to a clock edge of a single phase clock signal. The single phase spot circuit holds the spot for about one clock cycle, thereby providing higher maximum operating frequency relative to multiphase spot circuits that hold a spot for about half of a clock cycle. Two or more single phase spot circuits can be electrically connected in a ring to operate as a spot divider. The single phase spot circuits can be used to advance a spot, represented using either a one or a zero, from one spot circuit to the next in response to a clock edge. In certain implementations, as the spot advances, a single phase spot circuit clears the spot from its input via a feedback element. 1. (canceled)2. An electronic circuit comprising: a first spot moving stage comprising a first spot input, a first spot output, and a first plurality of field-effect transistors (FETs) configured to selectively control the first spot output based on a logic value of the first spot input and on timing of the single phase clock signal; and', 'a second spot moving stage comprising a second spot input electrically connected to the first spot output, a second spot output, and a second plurality of FETs configured to selectively control the second spot output based on a logic value of the second spot input and on timing of the single phase clock signal,, 'a plurality of spot moving stages configured to move a spot represented by a logically high value based on timing of a single phase clock signal, wherein the plurality of spot moving stages comprisewherein when the first spot input has the logically high value indicating presence of the spot, the first plurality of FETs control the first spot output to the logically high value in response to a falling edge of the single phase clock signal, and wherein when the first spot input has a ...

CLOCK DIVIDER

Aspects of the disclosure provide a circuit including a logic circuit. The logic circuit is configured to operate without inputs from a first clock signal. The logic circuit is further configured to frequency-divide the first clock signal to generate a second clock signal based on a logic combination of a first pattern provided by a first circuitry driven by the first clock signal, and a second pattern provided by a second circuitry driven by the first clock signal. 1. A circuit , comprising:a logic circuit configured to operate without inputs from a first clock signal, the logic circuit being further configured to frequency-divide the first clock signal to generate a second clock signal based on a logic combination of a first pattern provided by a first circuitry driven by the first clock signal, and a second pattern provided by a second circuitry driven by the first clock signal.2. The circuit of claim 1 , wherein the first circuitry includes a first sampling flip-flop driven by the first clock signal claim 1 , and the second circuit includes a second sampling flip-flop driven by an inversed first clock signal.3. The circuit of claim 2 , wherein the first sampling flip-flop and the second sampling flip-flop have a substantially equal delay in response input clocks.4. The circuit of claim 3 , whereina first inverter configured to inverse the first clock signal to generate the inversed first clock signal; andthe first circuitry includes a second inverter configured to compensate for a delay of the first inverter.5. The circuit of claim 2 , wherein the first sampling flip-flop is configured to drive the first pattern in response to rising edges of the first clock signal and the second sampling flip-flop is configured to drive the second pattern in response to falling edges of the clock signal.6. The circuit of claim 1 , wherein the logic circuit includes a logic gate to provide the second clock signal with a substantially equal delay in response to the first pattern ...

SEMICONDUCTOR DEVICE

A semiconductor device may include an input control circuit, a counting circuit, an output control circuit, and a counting operation control circuit. The input control circuit may output a counting input signal based on an input signal and a counting over signal. The counting circuit may generate a preliminary counting code based on the counting input signal. The output control circuit may generate a counting code based on the preliminary counting code. The counting operation control circuit may generate the counting over signal based on a part of the counting code. 1. A semiconductor device comprising:an input control circuit configured to output a counting input signal based on an input signal, an enabling signal, and a counting over signal;a counting circuit configured to generate a preliminary counting code based on a reset signal and the counting input signal;an output control circuit configured to generate a counting code based on the counting over signal and the preliminary counting code; anda counting operation control circuit configured to generate the counting over signal based on the reset signal and a part of the counting code.2. The semiconductor device of claim 1 , wherein the input control circuit outputs the input signal as the counting input signal or fixes the counting input signal to a specific level in response to the enabling signal and the counting over signal.3. The semiconductor device of claim 2 , wherein the input control circuit outputs the input signal as the counting input signal based on the enabling signal being enabled and the counting over signal being disabled claim 2 , and the input control circuit fixes the counting input signal to the specific level based on the enabling signal being disabled or the counting over signal being enabled.4. The semiconductor device of claim 1 , wherein the counting circuit increases a code value of the preliminary counting code based on the reset signal being disabled and the counting input signal ...

BY ODD INTEGER DIGITAL FREQUENCY DIVIDER CIRCUIT AND METHOD

The present application relates to a circuit of a frequency divider arranged to divide a frequency of an input clock signal by odd integer N and a method of operating the circuit. A shift register comprises a number of N+1 clock gating cells, which are connected in series to each other, and a shift logic. An input clock signal is fed into clock signal inputs of each one of the number of N+1 clock gating cells. The shift logic is configured to receive enable signals from a set of the number of N+1 clock gating cells and to generate a feedback signal, which is supplied to a gate enable input of the first one of the number of N+1 clock gating cells. A multiplexer is configured to receive at input ports N+1 gated clock signals and to output a rotation clock signal, which has a frequency of 2/N of the frequency of the input clock signal. A frequency generator is configured to receive the rotation clock signal and to generate an output clock signal having a frequency of 1/N. 1. A circuit of a frequency divider arranged to divide a frequency of an input clock signal by odd integer N , comprising:a shift register comprising a number of N+1 clock gating cells being connected in series to each other and a shift logic,wherein an input clock signal is fed into clock signal inputs of each one of the number of N+1 clock gating cells,wherein the shift logic is configured to receive enable signals from a set of the number of N+1 clock gating cells and to generate a feedback signal, which is supplied to a gate enable input of the first one of the number of N+1 clock gating cells;a multiplexer configured to receive at input ports N+1 gated clock signals and to output a rotation clock signal, which has a frequency of 2/N of the frequency of the input clock signal,a frequency generator configured to receive the rotation clock signal and to generate an output clock signal having a frequency of 1/N.2. The circuit according to claim 1 ,wherein a gate enable input of each one of the number ...

FREQUENCY SYNTHESIZER WITH TUNABLE ACCURACY

An apparatus includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first code by counting a number of cycles of an input clock signal in a period determined by (i) an output clock signal and (ii) a second code. The second code may be variable. The second circuit may be configured to generate a third code by a delta-sigma modulation of the first code. The third circuit may be configured to generate the output clock signal (i) in response to the third code and (ii) within an accuracy determined the second code. 1. An apparatus comprising:a first circuit configured to generate a first code by counting a number of cycles of an input clock signal during a period, wherein (a) said period is determined by (i) an output clock signal and (ii) a second code, and (b) said second code (i) is read from a memory internal to said first circuit and (ii) has a variable multi-bit value;a second circuit configured to generate a third code by a delta-sigma modulation of said first code; anda third circuit configured to generate said output clock signal (i) in response to said third code and (ii) within a frequency accuracy determined by a current value of said second code.2. The apparatus according to claim 1 , wherein said first circuit is further configured to adjust said second code to change a duration of said period.3. The apparatus according to claim 1 , wherein said first circuit is further configured to set said second code to an initial value that establishes a short duration of said period in which a frequency of said output clock signal is adjusted to a coarse accuracy.4. The apparatus according to claim 3 , wherein said coarse accuracy is achieved when said number of cycles of said input clock during said period minus an expected number falls below a threshold.5. The apparatus according to claim 3 , wherein said first circuit is further configured to set said second code to a subsequent value that establishes a ...

WIDE-RANGE LOCAL OSCILLATOR (LO) GENERATORS AND APPARATUSES INCLUDING THE SAME

A local oscillator generator (LO generator) may be configured to transmit an LO signal to a mixer. The LO generator may include an input buffer configured to generate a first internal oscillator signal based on the input oscillator signal. The LO generator may include a frequency dividing circuit configured to generate a second internal oscillator signal based on dividing a frequency of the first internal oscillator signal. The LO generator may include an output buffer configured to generate the LO signal based on the second internal oscillator signal. The input buffer and the frequency dividing circuit may each be configured to receive a power voltage independently of the output buffer. 1. A local oscillator generator (LO generator) configured to transmit an LO signal to a mixer , the LO generator comprising:an input buffer configured to generate a first internal oscillator signal based on an input oscillator signal;a frequency dividing circuit configured to generate a second internal oscillator signal based on dividing a frequency of the first internal oscillator signal; andan output buffer configured to generate the LO signal based on the second internal oscillator signal,wherein the input buffer and the frequency dividing circuit are each configured to receive a power voltage independently of the output buffer.2. The LO generator of claim 1 , wherein the input buffer and the frequency dividing circuit are further configured to mutually independently receive power voltages claim 1 , respectively.3. The LO generator of claim 1 , wherein the output buffer includes an AC-coupled buffer claim 1 , the AC-coupled buffer configured to AC-couple the second internal oscillator signal.4. The LO generator of claim 3 , wherein the AC-coupled buffer includesan inverter;a feedback resistor having two ends connected to an input terminal of the inverter and an output terminal of the inverter, respectively; anda capacitor having a first end and a second end, the first end ...

LOW DROPOUT VOLTAGE (LDO) REGULATOR INCLUDING A DUAL LOOP CIRCUIT AND AN APPLICATION PROCESSOR AND A USER DEVICE INCLUDING THE SAME

A low dropout voltage (LDO) regulator including: a coarse loop circuit configured to receive an input voltage, generate a coarse code and adjust a coarse current according to the coarse code; a digital controller configured to receive the coarse code and generate a fine loop control signal according to the coarse code; and a fine loop circuit configured to receive the input voltage and the fine loop control signal and adjust a fine current according to the input voltage and the fine loop control signal, wherein the coarse current and the fine current adjust a level of an output voltage. 1. A low dropout voltage (LDO) regulator , comprising:a coarse loop circuit configured to receive an input voltage, generate a coarse code and adjust a coarse current according to the coarse code;a digital controller configured to receive the coarse code and generate a fine loop control signal according to the coarse code; anda fine loop circuit configured to receive the input voltage and the fine loop control signal and adjust a fine current according to the input voltage and the fine loop control signal,wherein the coarse current and the fine current adjust a level of an output voltage.2. The LDO of claim 1 , further comprising a voltage divider configured to receive the output voltage to generate the input voltage.3. The LDO of claim 1 , wherein the level of the output voltage is maintained in a steady state when the coarse loop circuit and the fine loop circuit operate at the same time.4. The LDO of claim 1 , wherein the coarse loop circuit comprises:a reference voltage changer configured to receive the coarse code and change a coarse reference voltage according to the coarse code;an analog-to-digital converter (ADC) configured to receive the coarse reference voltage and the input voltage and generate the coarse code according to the coarse reference voltage and the input voltage; anda coarse current driver configured to receive the coarse code and generate the coarse current ...

FREQUENCY DIVIDING CIRCUIT AND PHASE SYNCHRONIZATION CIRCUIT

A frequency dividing circuit includes: a mode selection section configured to determine an exclusive OR of a first clock signal and a first signal and output the exclusive OR as a second signal in a first operation mode, and to output the first clock signal as the second signal in a second operation mode; and a clock generation section configured to generate and output a second clock signal, based on the second signal and the second clock signal, and to output one of the second clock signal and a third clock signal, as the first signal, the third clock signal having a phase same as a phase of the second clock signal. 1. A frequency dividing circuit comprising:a mode selection section configured to determine an exclusive OR of a first clock signal and a first signal and output the exclusive OR as a second signal in a first operation mode, and to output the first clock signal as the second signal in a second operation mode; anda clock generation section configured to generate and output a second clock signal, based on the second signal and the second clock signal, and to output one of the second clock signal and a third clock signal, as the first signal, the third clock signal having a phase same as a phase of the second clock signal.2. The frequency dividing circuit according to claim 1 , whereinthe clock generation section includes a first sampling circuit and a second sampling circuit,the first sampling circuit samples the second clock signal at a timing of a transition of the second signal in a first transition direction and outputs a resultant signal, andthe second sampling circuit samples an output signal of the first sampling circuit at a timing of a transition of the second signal in a second transition direction, and outputs an inverted logic signal of a sampling result, as the second clock signal.3. The frequency dividing circuit according to claim 2 , wherein each of the first sampling circuit and the second sampling circuit is a latch circuit.4. The ...

NEUROMORPHIC ARITHMETIC DEVICE

Provided is a neuromorphic arithmetic device. The neuromorphic arithmetic device may include a synapse circuit, a metal line having an inherent capacitance component, an oscillator, a comparator, and a capacitance calibrator. The synapse circuit may be configured to perform a multiplication operation on a PWM signal and a weight to generate a current. The metal line may include a metal line capacitor in which a charge of the current is stored. The oscillator generates a plurality of pulses on the basis of the charge stored in the metal line capacitor. The comparator may compare a frequency of the plurality of pulses and a target frequency, and may generate a control signal on the basis of a result of the comparison. The capacitance calibrator may adjust a capacitance value of the metal line capacitor on the basis of the control signal. 1. A neuromorphic arithmetic device comprising:a synapse circuit configured to perform a multiplication operation on a PWM signal and a weight to generate a current;a metal line comprising a metal line capacitor in which a charge corresponding to the current is stored;an oscillator configured to generate a plurality of pulses on the basis of the charge stored in the metal line capacitor; anda capacitance calibrator configured to adjust a capacitance value of the metal line capacitor on the basis of a result of comparison between a frequency of the plurality of pulses and a target frequency.2. The neuromorphic arithmetic device of claim 1 , wherein the capacitance calibrator comprises:a plurality of capacitors connected in parallel to each other; anda plurality of switches corresponding to the plurality of capacitors respectively.3. The neuromorphic arithmetic device of claim 2 , wherein at least part of the plurality of switches is turned on so that the capacitance value of the metal line capacitor becomes a target value.4. The neuromorphic arithmetic device of claim 3 , wherein the plurality of capacitors have capacitance values ...

OSCILLATOR FREQUENCY DIVIDER WITH IMPROVED PHASE NOISE

A gated divider circuit includes a windowing unit configured to generate windowing waveforms from input oscillator waveforms having a fixed duty cycle. Additionally, the gated divider circuit includes a gated output unit coupled to the windowing unit and configured to provide selected ones of the input oscillator waveforms as controlled by corresponding selected ones of the windowing waveforms. Also included are a method of operating a gated divider circuit and a frequency conversion system employing a gated divider circuit as a local oscillator divider. 1. A gated divider circuit , comprising:a windowing unit configured to generate windowing waveforms from input oscillator waveforms having a fixed duty cycle; anda gated output unit coupled to the windowing unit and configured to provide selected ones of the input oscillator waveforms as controlled by corresponding selected ones of the windowing waveforms.2. The circuit as recited in wherein the corresponding selected ones of the windowing waveforms provide a windowing delay with respect to the selected ones of the input oscillator waveforms.3. The circuit as recited in wherein the input oscillator waveforms are local oscillator waveforms.4. The circuit as recited in wherein the windowing waveforms are 50 percent duty cycle waveforms.5. The circuit as recited in wherein the fixed duty cycle of the input oscillator waveforms is a 50 percent duty cycle.6. The circuit as recited in wherein the selected ones of the input oscillator waveforms correspond to a 25 percent duty cycle waveform.7. The circuit as recited in wherein the selected ones of the input oscillator waveforms are selected from the group consisting of:in-phase waveforms;complementary in-phase waveforms;quadrature-phase waveforms; andcomplementary quadrature-phase waveforms.8. A method of operating a gated divider circuit claim 1 , comprising:providing oscillator waveforms having a fixed duty cycle;generating windowing waveforms based on the oscillator ...

APPARATUSES AND METHODS FOR LOW POWER COUNTING CIRCUITS

Apparatuses and methods for low power counting circuits are described herein. An example apparatus may include a frequency divider configured to receive an input clock signal and adjust a frequency of the clock signal to provide an intermediate clock signal. The apparatus may further include a counter coupled to the frequency divider and configured to receive the intermediate clock signal. The counter may further be configured to provide a plurality of timing signals based on the intermediate clock signal. The apparatus may further include a frequency multiplier including a plurality of logic gates. Each of the plurality of logic gates may be coupled to the counter and configured to receive a respective first timing signal of the plurality of timing signals and at least one of the intermediate clock signal or a respective second timing signal of the plurality of timing signals. 1. An apparatus comprising:a frequency divider configured to receive an input clock signal and adjust a frequency of the clock signal to provide an intermediate clock signal;a counter coupled to the frequency divider and configured to receive the intermediate clock signal, the counter further configured to provide an incrementing count value as a plurality of timing signals based on the intermediate clock signal; anda frequency multiplier including a plurality of logic gates, each of the plurality of logic gates coupled to the counter and configured to receive a respective first timing signal of the plurality of timing signals and at least one of the intermediate clock signal or a respective second timing signal of the plurality of timing signals.2. The apparatus of claim 1 , wherein the frequency divider is configured to provide the intermediate clock signal with a frequency lower than a frequency of the input clock signal.3. The apparatus of claim 1 , wherein the frequency multiplier is configured to provide a plurality of output signals based on the plurality of timing signals claim 1 , ...

Clock Dividing Device

A clock dividing device includes an accumulator that accumulates a first accumulated value and a denominator value and stores a second accumulated value, a register that stores a delayed accumulated value obtained by delaying the second accumulated value, a first comparison operation unit that performs a comparative operation on the second accumulated value and a numerator value and stores the second accumulated value as a greater value if the second accumulated value is greater than or equal to the numerator value, a second comparison operation unit that performs a comparative operation on the delayed accumulated value and the numerator value and stores the delayed accumulated value as a delay greater value if the delayed accumulated value is greater than or equal to the numerator value, and a third comparison operation unit that performs a comparative operation on the greater value and the delay greater value and determines the shape of a clock, wherein the shape of the clock is one of a bypass, a rising edge, and a falling edge.

FREQUENCY DIVIDING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT

A plurality of latch circuits driven at rising of a clock signal and a plurality of latch circuits driven at falling of the clock signal are alternately connected, and generation circuit generates a plurality of frequency divided clock signals with different phases based on combinations of levels of outputs of the plurality of latch circuits. 1. A frequency dividing circuit comprising:a plurality of latch circuits that are connected in series in a loop in which the latch circuit driven at rising of a clock signal and the latch circuit driven at falling of the clock signal are alternately connected; anda generation circuit configured to generate a plurality of frequency divided clock signals with different phases, based on combinations of levels of outputs of the plurality of latch circuits.2. The frequency dividing circuit according to claim 1 ,wherein the generation circuit is configured to generate each of the plurality of frequency divided clock signals by performing a logical operation of outputs of the adjacent latch circuits among the plurality of latch circuits.3. The frequency dividing circuit according to claim 1 ,wherein the latch circuit driven at rising of the clock signal is an inverter configured to come to be in a continuity state when the clock signal is at a low level and to come to be in a non-continuity state when the clock signal is at a high level, andwherein the latch circuit driven at falling of the clock signal is an inverter configured to come to be in a continuity state when the clock signal is at the high level and to come to be in a non-continuity state when the clock signal is at the low level.4. The frequency dividing circuit according to claim 3 ,wherein the inverter includes a first P-channel type transistor, a second P-cannel type transistor, a first N-channel type transistor, and a second N-channel type transistor that are connected in series in an order thereof between a supply node of a power supply voltage and a supply node of a ...