ЦИФРОВОЙ ДЕЛИТЕЛЬ ЧАСТОТЫ

Изобретение относится к области электротехники. Техническим результатом изобретения является создание синтезируемого цифрового делителя частоты с увеличенным предельным значением частоты тактового сигнала за счет установки логического вентиля на сигнале обратной связи. 3 ил.

Elektronische Frequenzregelschaltung

Time generator for data processor - has clock driving counter which is reset by comparator at given count

The time generator has a clock generator driving a counter coupled at its output to a comparator. The counter is reset when it reaches a given count determined by the comparator. At this point a message signal is released. The message signal from the comparator disables the counter and is passed together with an external sync. pulse to a gate for enabling the counter and passing a message to a data processor. When data is changed, the output of the counter id diabled via a display circuit. A second counter counts the external sync. pulses.

FREQUENCY DIVIDER CIRCUIT SYSTEM

... 1300078 Frequency divider MATSUSHITA ELECTRIC INDUSTRIAL CO Ltd 19 Dec 1969 62134/69 Headings G4D D7X D6Y D6C1 and D6C2 A frequency divider includes a delay circuit T, a counter consisting of several cascaded flip-flops F o -F n , and an AND gate G for producing the logical product of the flip-flop outputs and the undelayed input pulses, the output of the AND gate being selectively applied to the inputs of the flip-flops. The arrangement ensures that feedback pulses to the flip-flop always precede the corresponding input pulse applied to the counter by a time equal to the delay T and malfunctions due to coincident pulses at flip-flop inputs are prevented. As described flip-flops F 1 -F 3 are provided with input gates G 1 -G 3 so that the counter can be set initially to a count of 15. Succeeding input pulses set stages F 4 -F n before gate G produces an output which, via selected ones of gates R o -R n-1 resets the counter. The frequency of the output is controlled by the circuit H which ...

A dividing circuit for dividing by even numbers

A dividing circuit and transistor stage therefor

Film scanning system

FREQUENCY CHANGER

FREQUENCY GENERATING CIRCUIT

Binary counter

... 1,057,770. Electric digital calculators. GENERAL PRECISION Inc. Oct. 12, 1964, No. 41505/64. Heading G4A. A number is entered into a dynamic store such as a magnetic drum and counted down at successive rotations of the drum until a zero registration produces an output pulse. When read-in flip-flop 38 is set the number to be entered is applied in serial real and complemental binary form over leads N, N, respectively, i.e. through AND gates 28, 26. During each subsequent circulation the bits in elements t0-ty are read to energize lead Rc or Rc and AND gate 18 or 22, respectively. Bit timing signal t0 sets control flip-flop 32 at the beginning of each circulation to enable AND gates 22, 26 whereby input or recirculated information is inverted before application to write amplifier. This condition continues until 1 is detected when inverter 19, delay line 20 and AND gate 36 are operated to restore flip-flop 32. Gates 18, 28 are then opened and 22, 26 closed so that the rest of the information ...

PROGRAMMABLE FREQUENCY DIVIDING APPARATUS

Method and apparatus for controlling the frequency of a variable frequency oscillator

... 1129267 Frequency dividers AGA AB 14 Oct 1965 [28 Oct 1964] 43588/65 Headings G4D D7X D6C1 D6C2 and D6Y An oscillator 9 is set to operate at a multiple n of the frequency of a standard oscillator 12. The multiple n is made up of 2x + y, where x pulses pass through gate 3 and y pulses through gate 4, changeover from one gate to the other being effected first when the number x set up on switches 15 is attained by a counter 7 and changeover in the opposite direction when counter 7 reaches full capacity. Phase difference between the outputs of counter 7 and the standard oscillator 12 controls the oscillator 9 in known manner.

PHASENUMSCHALT DOPPELMODUL MORE VORSKALIERER

PULSE GENERATOR

PRINTING MACHINE WITH VARIABLE COUNTER CONTROL SYSTEM

PROGRAMMABLE FREQUENCY DIVIDING APPARATUS

SHOW ELECTRONIC, IN PARTICULAR ELECTRONIC WRIST WATCH.

MONTRE ELECTRONIQUE, NOTAMMENT MONTRE-BRACELET ELECTRONIQUE.

Frequenzteiler

Impulsfrequenzteiler

Mouvement d'horlogerie électronique

GARDE-TEMPS COMPRENANT UN DIVISUER DE FREQUENCE AU RAPPORT DE DIVISION AJUSTABLE PAR DES MOYENS L'ETALONNAGE EXTERNES ET PROCEDE DE MISE EN ACTION DE CE GARDE TEMPS.

Diviseur de fréquence à rapport numérique variable

Einrichtung zum Feststellen der Übereinstimmung einer gegebenen Zahl mit dem Stand eines elektronischen Zählers

Schaltungsanordnung für elektronische Zähleinrichtung

SHOW ELECTRONIC, IN PARTICULAR ELECTRONIC WRIST WATCH.

Generator of isochronous reference periods which can be used for measuring time and can be readjusted, and use of this generator

A counter logs the number of vibrations per second of the generator of periods and records it in a memory of the watch, which is part of the readjusting device. Whenever the number of vibrations reached corresponds to that entered into the memory, a signal is transmitted to the liquid-crystal analog display, the counter of the number of vibrations is then reset to zero and a new normal counting cycle is started. An apparatus for transmitting low-frequency radio waves produces synchronisation signals acting on the readjusting device of the watch, if it is within range of the transmitter. Resetting the watch to time on passing in front of the shop of a retailer keeping his transmitter going. ...

DIVIDING CIRCUIT OF FREQUENCY.

Clock generating method in time clock production circuit

Improvements with the electronic devices of control in frequency

Multi-clock real-time counter

A shared real-time counter is configured to provide an accurate counter output based on a fast clock period when driven by a fast clock signal or by a slow clock signal. Combinational logic circuitry provides glitch free switching between a fast clock signal input to the counter and a slow clock input to the counter. The counter is always on and increases its count by an appropriate rational number of counts representing fast clock cycles for every cycle of the fast clock while in a fast clock mode, and by an appropriate rational number of fast clock periods for every cycle of the slow clock signal while in a slow clock mode.

FREQUENCY DIVIDER

The present invention relates to a frequency divider having an adjustable divider ratio (TV). Such circuits are subject to requests for ever higher clock frequencies. For fulfilling said requests, the inventive circuit generates the output signal (OUT) block by block, converts said signal into a sequential signal in a parallel-serial converter (MUX) and outputs said signal bit by bit, whereby said converter is situated on the output side. The essential part of the frequency divider circuit can thus be operated by means of a frequency (C4) that is slower than the input frequency (C) and, as a result, higher input frequencies are possible.

Detection arrangement, counter unit, phase locked loop, detection method and method for generating an oscillator signal

A detection arrangement includes a counter unit which receives a first clock signal and a reference clock signal. The counter unit derives a first data word as a function of a time deviation between clock edges of the first clock signal and the reference clock signal. The detection arrangement further includes a signal processing unit to determine a phase deviation word as a function of the first data word and a second data word, the second data word based on the duration of a clock period of the reference clock signal.

Variable-ratio frequency divider

A variable-ratio frequency divider has a D flip-flop which makes possible high-speed operation, and the number of frequency divisions is made variable by changing the transmission delay time of a delay element included in a feedback loop from the output &upbar& Q to a predetermined terminal of the D flip-flop.

SIGNAL SYNTHESIZING CIRCUIT

PURPOSE: To lower operating input frequency, to simplify a circuit constitution and to reduce power consumption by adjusting an output pulse width transmitted from a counter every time a delay compensating counter counts up. CONSTITUTION: A signal generator 10 transmits a reference signal S11, a signal S2 that is inverted signal S1, a signal S3 that is advanced in phase signal S1 by 1/4 period, and a signal S4 that is inverted signal S3, to a signal input circuit 11. The signals S1∼S4 are selected cyclicly from the circuit 11, and fed to the post-stage by the control of an input signal selecting circuit 13. A counter 12 counts decimally an output of the circuit 11 and also outputs a reference signal. Further, a count-up signal of the counter 12 is fed to a delay compensating counter 14, which corrects the delay in the output pulse outputted from the counter every time the counter 14 counts the 25 signals. Then, the frequency of the input pulse signal is decreased. COPYRIGHT: (C)1984,JPO ...

VARIABLE FREQUENCY DEMULTIPLIER

PURPOSE: To simplify circuit and to give flexibility to the unit, by forming the variable frequency demultiplier having the functions of addition equivalently, through the provision of the data selector and the 1/M counter. COPYRIGHT: (C)1978,JPO&Japio ...

Делитель частоты с переменным коэффициентом деления

Изобретение относится к автоматике и вычислительной технике, а также к системам автоматического управления и может найти применение в системах числового программного управления, в измерительных и вычислительных устройствах, устройствах обработки аудио- и видеосигналов, а также при первичной обработке сигналов фазированных антенных решеток радаров. Техническим результатом является повышение быстродействия работы устройства при его схемотехническом упрощении. Устройство содержит элемент ИЛИ с n входами, сдвиговый регистр на 2n–1 разрядов, входы синхронизации, установки в начальное состояние, разрешения деления, являющиеся соответствующими входами регистра, n логических трехвходовых элементов И, n–1 элементов ИЛИ на два, четыре, …, 2n–1 входов, элемент ИЛИ-НЕ на 2n–1 входов. 2 ил.

FREQUENZTEILER MIT VARIABLEM MODULUS

FREQUENCY DIVIDER PROGRAMMABLE FOR NON-INTEGER DIVISION

Frequenzteileranordnung

Multistage frequency pulse divider - has shift register with NAND: gate feeding stage outputs back to input

The pulse frequency divider has an n-stage shift register with feedback. The outputs of k >=2 stages (FF1, FF2) of the register are connected to the k inputs of a NAND-gate (T3) whose output is coupled back to the input of the registers first stage. The registers first to (n-k) stages have no feedback. The divided pulse sequence is taken from the output (A) of one stage (FF2). In another version inverters are located between the outputs of the second and nth stages and the inputs of the NAND-gate. A further NAND-gate is connected in series after each inverter. This second version allows pulse trains with variable duty factor and frequency to be generated.

TONGENERATOR ZUM ERZEUGEN AUSGEWAEHLTER FREQUENZEN

Improvements in or relating to electric pulse counting arrangements

... 987, 694. Electronic counters. NATIONAL RESEARCH DEVELOPMENT CORPORATION. June 19, 1962 [March 21, 1961], No. 10292/61. Heading G4A. To prevent a predetermined count being indicated erroneously, an interrogation pulse corresponding to each count pulse is delayed sufficiently to ensure the dissipation of any spurious signal, a gate circuit fed by the interrogation pulse and a pulse from the predetermined conditions of the counter responding to produce an output pulse. Negative potential output from the energized halves of the stages of a cascade counter CC are connected through a diode matrix to a selector SS, shown as a mechanical rotary selector, set to the predetermined number. It is possible that spurious pulses X, Fig. 2c, might appear on lead 14 in contrast to the predetermined count pulse S. This is allowed for in the following manner. Each count pulse at 15 is shaped by blocking oscillator BO, transformer TR1 and diodes D1, D2 into count pulses, Fig. 2(b), and delayed interrogation ...

BINARY COUNTING CIRCUIT

A binary counting circuit comprises a binary counter C having selected ones of its outputs connected via switches S0-S11 to respective inputs of a logic circuit NAND, and other inputs of this logic circuit being maintained at a predetermined logic level, so that the logic circuit produces an output signal at a predetermined count. However, diode means D3 responds to each input pulse to the counter to disable the logic circuit output signal until after the triggering edge of the input pulse corresponding to the predetermined count. As shown, input pulses are used to produce fixed-length pulses at the output of a monovibrator MV1, and a resetting output of the circuit taken via a further monovibrator MV2 is inhibited until the arrival of trailing edge of a desired pulse from the first monovibrator MV1. A timing circuit and multiplying circuit are described with reference to Figs 3, 4 (not shown). ...

TONE GENERATOR FOR GENERATING SELECTED FREQUENCIES

... 1399200 Tone generators; keysets PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 7 June 1973 [10 June 1972] 27174/73 Headings G4D D7X D6Y D6C1 and D6C2 A tone generator comprises a pulse oscillator feeding an integer frequency divider formed from a non-integer adjustable subdivider and an integer subdivider the latter serving as part of a digital-toanalogue converter to produce a representation of the tone. The embodiment is for generating two tones, one selected from each of two sets of four tones, in a push-button telephone set and accordingly has two dividers connected to a common crystal controlled pulse oscillator, Fig. 1 (not shown). By selecting tone frequencies different from the design centre values but within the tolerance range, smaller dividers and a lower oscillator frequency may be used in the two divider circuits, Figs. 3 and 4 (not shown). The embodiment is formed from current injection logic units in which a multi-collector transistor has a current supply at its base so ...

VARIABLE FREQUENCY DIVIDING CIRCUIT

... 1411770 Variable frequency dividers NIPPON GAKKI SEIZO KK 28 Dec 1972 [30 Dec 1971(2)] 59822/72 Heading G4A A variable frequency divider comprises a chain of bi-stable circuits 20 to which is fed the frequency from 10 to be divided; a register 40 in which is temporarily held the value by which the frequency is to be divided; a plurality of coincidence gates 30a-30n arranged to compare states of the counter 20 and register 40 and to issue an output pulse at T 0 and reset counter 20 to zero each time the value in counter reaches that in the register 40. As shown the frequency divider is employed in an electronic musical instrument. A 61-note keyboard 90 and gate circuits 60, 80 co-operate to transfer a selected one of 61 values stored in a main memory 70 to the register 40 whereby the divider A delivers a selected one of 61 notes. As indicated, in a polyphonic instrument, as many dividers A are required as notes can be sounded simultaneously. Simultaneously actuated keys cause various values ...

ELECTRONIC TIMEPIECES

... 1370564 Electronic timepieces EBAUCHES SA 13 April 1972 [22 April 1971 ] 17013/72 Headings G4D D6Y D6C1 D6C2 and D7X To permit adjustment of the rate of an electronic timepiece having a Piezo-electric oscillator as time base and a frequency division chain controlling a time display H, means are provided to adjust the scale of division comprising a digital comparator for comparing the logic state of a binary reference of M bits with that of stages N+I to N+M of the division chain. The comparator has a blocking input BLO which receives the output Q from a flip-flop FFC which is controlled alternately by the outputs of the comparator and the division chain. When the comparator input is blocked, the division chain counts up to the limit of its flip-flop stages FFD whereupon monostable multi-vibrator MONO 1 emits a pulse which actuates the display H and clears FFC, thus reducing output Q to zero and unblocking the comparator. During the next period of division, when the comparator senses that ...

MULTIPLE-DIVIDING FREQUENCY SLICING

FREQUENCY DIVIDER WITH CHANGEABLE PARTIAL RELATIONSHIP AND ADAPTED POWER ABSORPTION

SHEET NUMBER DEVICE

Multi-divide frequency division

TOTALIZER

... of the Invention A totalizer is provided which is adapted to accept a variety of process signals at the input thereof, which process signals will be in analog form. The signals are then first converted into digital form by first converting all of the types of input signals to a voltage signal that is proportional to the value of the input signal and then converting this voltage signal to a series of pulses whose repetition rate is proportional to the voltage input and then counting these pulses on a decade counter which is provided with a decimal decoder through which a scale factor may be introduced into the counter. The output of the inital decade counter is then fed into a memory bank having a visual readout.

PULSE GENERATOR

PULSE GENERATOR A pulse generator for producing two output pulse trains A and B where the total number of pulses in both train A and B over a fixed time period remains a constant. The two pulse trains axe derived from a master clock which gates a plurality of cascade connected synchronous decade rate multipliers. A selector is set either statically or dynamically to the value N where N is the number of pulses desired in one pulse train out of every M pulses produced by the master clock. A summing means is coupled to all the multipliers to produce a first intermediate pulse train with N pulses for every M clock pulses. A difference means is coupled to each multiplier and to the master clock to produce a pulse in a second intermediate pulse train every time a clock pulse occurs and a pulse in the first pulse train does not occur. A pulse counter is coupled to each intermediate pulse train output to produce two output pulse trains A and B each having a substantially constant pulse frequency ...

CLOCK PULSE GENERATOR FOR MICROCOMPUTER

The output of a single source of pulses is sequentially frequency divided and gate circuits arranged so that one of the plurality of divisions can be selectively supplied to an output terminal of the device.

Device allowing to note the coincidence of a number given with the position of an electronic meter

Electronic meter for division of frequency to variable divider

DIVISEUR DE FREQUENCE INTEGRE

La présente invention se rapporte aux circuits démultiplicateurs de la fréquence de signaux périodiques. Le circuit selon l'invention permet la division de la fréquence de deux signaux en opposition de phase diamétre 1 (t) et O2 (t). Un registre à décalage 10 comprend un ensemble de transistors, et de condensateurs qui forment une pluralité de chaînons branchés les uns à la suite des autres, chaque chaînon étant constitué de deux demi-chaînons identiques qui sont connectés en série et peuvent être alimentés respectivement par lesdits signaux périodiques. Des moyens de détection d'états particuliers du registre comportent les transistors MOS T8 T9 ; T10 Des moyens de production d'un signal de fréquence sous-multiple de celle desdits signaux périodiques comprennent les transistors T11 et T12 , le transistor Tl3 , le condensateur C7 et le condensateur C9 . Application notamment dans les montres à quartz.

PULSE COUNT DETECTOR HAVING FAIL-SAFE FEATURES

Electric device, such as divider with variable ratio

Symmetric clock system for a data processing system including dynamically switchable frequency divider

A dynamically switchable clock system having a symmetrical output signal includes a frequency doubler which couples the input frequency to provide greater resolution and synchronization of an output signal to an input signal in the frequency divider and the facility to handle odd divides as even divides at double frequency, a counter controlled by a divisor select signal, first and second compare circuits which compare against the preprogrammed count for division, the compare circuits receiving an input from the divisor select circuits, and having outputs to a counter reset line and to an output clock S/R latch which provides the frequency divided symmetrical output signal.

RING COUNTER

An electronic ring counter driven by a source of pulses and having controls to bypass some of the stages of the ring counter, each stage employing a single transistor.

High-speed divider with pulse-width control

In at least one embodiment of the invention, a method for dividing a first signal having a first frequency by a divide ratio to generate a lower frequency signal includes generating a first plurality of signals having a common frequency, a first pulse width, and different phases. The first plurality of signals is based, at least in part, on at least one signal having a second pulse width. The first pulse width is selected from a plurality of pulse widths based, at least in part, on the divide ratio. The method includes sequentially selecting individual pulses of the first plurality of signals as an output signal of a select circuit to generate an output signal having a frequency lower than the first frequency.

Frequency generating circuit

A frequency generating circuit comprises a piezoelectric buzzer (18) which is driven by a driving signal having a desired frequency and a desired pulse width; a frequency dividing circuit (1) made up of a multi-stage flip-flop array for frequency dividing a reference frequency signal; logic setting means (31 to 36, 4) which is responsive to a plurality of externally generated setting signals (C1 to C6) to effect a logic setting for obtaining the desired frequency; control means (5, 6, 7, 10, 11, 12) for outputting a control signal to reset terminals of the flip-flops on the basis of an output signal of the logic setting means for resetting the frequency dividing circuit to obtain the desired frequency; pulse width setting means (15) coupled to output terminals of at least two predetermined flip-flop stages of the frequency dividing circuit to set the pulse width of a driving signal to the desired pulse width; and driving signal generating means (8, 13, 14, 16) for delivering a driving signal ...

Method and mechanism for generating a clock signal with a relatively linear increase or decrease in clock frequency

A method and mechanism for generating a clock signal with a relatively linear increase or decrease in clock frequency. A first clock signal is generated with a first frequency which is then used to generate a second clock signal with a second frequency. The second frequency is generated by dropping selected pulses of the first clock signal. Particular patterns of bits are stored in a storage element. Bits are then selected and conveyed from the storage element at a frequency determined by the first clock signal. The conveyed bits are used to construct the second clock signal. By selecting the particular pattern of bits selected and conveyed, the frequency of the second clock signal may be determined. Further, by changing the patterns of bits within the registers at selected times, the frequency of the second clock signal may be made to change in a relatively linear manner.

Variable frequency pulse generator - has programmable frequency divider between two fixed frequency dividers

The variable-frequency pulse generator has a programmable frequency divider (SM) coupled by its input via a fixed freq. divider (T1) to the pulse source (Ig) and by its output via a negator (GN) to one input of an AND circuit (Vs). The AND circuits second input is connected directly to the pulse source and its output is coupled to a second fixed freq. divider (T2). The range over which the frequency can be adjusted if the programmable divider has unity denominator is given by f/m.k, where f is the pulse source frequency and m and k the denominators of the fixed frequency dividers.

Teilerschaltung zum Teilen durch gerade Zahlen

SCHALTUNGSANORDNUNG FUER EINEN. BINAEREN ELEKTRONISCHEN IM PULSZAEHLER

Digital frequency divider with adjustable division ratio can process high clock rates

The present invention relates to a frequency divider having an adjustable divider ratio (TV). Such circuits are subject to requests for ever higher clock frequencies. For fulfilling said requests, the inventive circuit generates the output signal (OUT) block by block, converts said signal into a sequential signal in a parallel-serial converter (MUX) and outputs said signal bit by bit, whereby said converter is situated on the output side. The essential part of the frequency divider circuit can thus be operated by means of a frequency (C4) that is slower than the input frequency (C) and, as a result, higher input frequencies are possible.

Programmable frequency dividing apparatus

DIGITAL TIMER

COPY COUNTING APPARATUS FOR A REPRODUCTION MACHINE

... 1451992 Copying XEROX CORP 15 March 1974 [20 March 1973] 11577/74 Heading B6C An apparatus for producing copies of an original, e.g. a xerographic machine, comprises a counting system to produce the data needed for a rental accounting. The counting system counts the total number of copies produced on one counter, and the total number of copies produced in runs of less than a specified number for each original, in another counter. A further counter may be provided to count the total number of copies produced in runs less than a different specified number, and a counter to count the number of originals from which have been produced runs of copies of more than a specified number. The counting system may be electrical, and exchangeable plug-in modules be provided for changing the numbers.

MAXIMUM DEMAND COMPARITOR

... 1468259 Counting electric pulses; electricity meters A J COLEMAN 9 June 1975 [17 June 1974 23 Sept 1974] 26648/74 and 41394/74 Heading G4D A predetermined counter is employed to prevent an electrical load exceeding a preset maximum demand; the counter counts pulses generated for each increment of electricity consumed until the counter is reset by an external time signal or the count exceeds a value determined by the preset maximum demand when it issues a signal which can be used to disconnect or reduce the load. In a first embodiment (Fig. 1, not shown) the maximum demand is set by a set of selector switches, comparators comparing the value set in the switches with that in the counter. In a second embodiment (Fig. 2, not shown) the set of switches selects the rate of an oxilator whose output pulses are counted by another counter to provide a steadily increasing maximum; if the count in the main counter exceeds that in the other the comparator issues the signal. A further counter records ...

An arrangement for reducing the pulse frequency of a pulse sequence

... 1002733 Electronic counters LICENTIA PATENT VERWALTUNGS GmbH 25 April 1962 [28 April 1961] 15733/62 Headings G4D D7X D6C1 D6C2 and D6Y A frequency dividing system for selecting a predetermined number of pulses from a continuous train, comprises one or more decade counters fed from the continuous train, the counter output being fed to switching matrices so as to provide a different number of pulses on each of a plurality of lines and switching means for selectively connecting the output terminal to the line carrying the required number of pulses. In Fig. 1, a continuous pulse train or sine wave is fed via a pulse shaping bi-stable circuit 1 to decade counters 2, 2', each comprising four bi-stable stages, the two outputs from each bi-stable stage being fed to matrices of AND gates 2a, 2a' and OR circuits 3, 3'. Suitable diode matrices are given in Figs. 3, 4, 5, 9 (not shown). Lines 81-89 respectively provide 0À1- 0-9 of the number of pulses in the original train whilst the outputs from matrix ...

DIGITAL FREQUENCY INDICATION IN COMMUNICATIONS RECEIVERS

... 1483654 Receiver digital frequency indicator; transistor limiters and sinewave to pulse circuits LICENTIA PATENT-VERWALTUNGS-GmbH 20 Nov 1974 [24 Nov 1973] 50236/74 Headings H3Q and H3T In a circuit arrangement for the digital indication of frequency in an AM and FM receiver including AM and FM local oscillators 3 and 1 the oscillations provided by each of the oscillators are fed via an amplifier 8 to an electronic counter 12 and a display 13 co-operates with the counter 12 to indicate a frequency to which the receiver is tuned and the coupling of the amplifier 8 to the oscillators 1, 3 is such that the oscillators are not detuned by changes in capacitance of the amplifier. As shown Fig. 1 the coupling is by capacitors 5 and 6 and the capacitance of a lead 14 to ground is indicated by 7. The outputs of the oscillators 1 and 3 can be coupled to series connected inductances (17, 18, Fig. 2, not shown) connected by a lead (19) to the input of amplifier 8. The division ratio of a predivider ...

COINCIDENT COUNTING SYSTEM

... 1283157 Counters CENTAUR MINI DEVICES Inc 20 May 1970 [26 May 1969] 24388/70 Headings G4A and G4D Count pulses are supplied simultaneously to a plurality of ring counters 10, 12, 14 of different radix, the attainment simultaneously of specified stages in all the counters producing a signal. In batch counting a start signal sets the counters to a start condition and the attainment of the specified stages energizes a gate 42 to stop the drive motor 36. The ring counter may be of S.C.R. diode type with lamp indicators.

Arrangement for proportional impulse reduction

BLATTZAHLVORRICHTUNG

TONE GENERATOR FOR GENERATING SELECTED FREQUENCIES

FUNCTION GENERATORS

ELECTRONIC TIMEPIECE

ELECTRONIC REFERENCE ISOCHRONOUS PERIOD GENERATOR AND APPLICATIONS

Universal divider of frequency

Dynamic pulse difference circuit

A digital electronic circuit of especial use for subtracting background activity pulses in gamma spectrometry comprises an up-down counter connected to count up with signal-channel pulses and to count down with background-channel pulses. A detector responsive to the count position of the up-down counter provides a signal when the up-down counter has completed one scaling sequence cycle of counts in the up direction. In an alternate embodiment, a detector responsive to the count position of the up-down counter provides a signal upon overflow of the counter.

Asynchronously programmable frequency divider circuit with a symmetrical output

A programmable divider circuit having an adjustable shift register is coupled to a clock and to an output. The shift register receives a clock signal having a clock signal frequency and outputs an output signal with an output frequency corresponding to a user selected divide ratio of the clock signal frequency. Control inputs are coupled to the adjustable shift register to receive control data for adjusting a length of the shift register, the length of the shift register corresponding to the user selected divide ratio.

Method and system for a digital frequency divider

Methods and systems for generating a signal are disclosed herein and may comprise digitally frequency dividing a input signal by a factor value specified as an N+1-bit value, utilizing a counter of N bits. A count value may be generated based on a number of cycles of the input signal and a generated count value compared with the factor value to generate a match signal comprising a pipelined match signal. The comparison may be performed utilizing a pipelined count value. An output signal from the digitally frequency dividing may be toggled utilizing the match signal. The digital frequency dividing may be performed utilizing a single comparator and may be performed utilizing a single counter. One of two clock signals may be selected and utilized to toggle the output signal. One bit of the factor value, and the output signal, may be utilized to select one of two clock signals.

VARIABLE FREQUENCY DIVIDER

PURPOSE: To enable high accuracy without increasing resolution, by sectioning the variable frequency divider consisting of the counter, D/A converter and comparator. CONSTITUTION: The counter is sectioned into two digits, the counter 111 counts frequency divided input, and the counter 112 counts the carry output of the counter 111. The D/A converter 121 converts the parallel output of thecounter 111 into analog voltage. The comparator 131 compares the output of the D/A converter 121 with the reference voltage of the reference voltage source 141 and the comparator 132 compares the output of the D/A converter 122 with the reference voltage of the reference voltage source 142. Further, the reset of the counters 111,112 and the frefuency divided output are obtained by detecting the coincidence of both outputs of the comparators 131, 132. COPYRIGHT: (C)1981,JPO&Japio ...

Electronic apparatus

An electronic apparatus includes a first frequency division portion that frequency-divides a clock signal by a first frequency division ratio, a second frequency division portion that frequency-divides the first clock signal which has been frequency-divided by the first frequency division portion by a second frequency division ratio, and a regulation frequency division portion that performs logical regulation of the clock signal using a second clock signal which has been frequency-divided by the second frequency division portion.

FREQUENCY DIVIDER CIRCUIT, DEMULTIPLEXER CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT

A frequency divider circuit includes: a first frequency dividing circuit configured to divide a first clock signal to generate a first frequency-divided clock signal; a second frequency dividing circuit configured to divide a second clock signal having the same frequency as the first clock signal and having a first phase difference with respect to the first clock signal to generate a second frequency-divided clock signal; a detection circuit configured to detect a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; and a selection circuit configured to select and output one of the second frequency-divided clock signal and an inverted signal of the second frequency-divided clock signal which are generated by the second frequency dividing circuit, based on the phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal detected by the detection circuit 1. A frequency divider circuit comprising:a first frequency dividing circuit configured to divide a first clock signal to generate a first frequency-divide clock signal;a second frequency dividing circuit configured to divide a second clock signal having the same frequency as the first clock signal and having a first phase difference with respect to the first clock signal to generate a second frequency-divided clock signal;a detection circuit configured to detect a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; anda first selection circuit configured to select and output one of the second frequency-divided clock signal and an inverted signal of the second frequency-divided clock signal which are generated by the second frequency dividing circuit, based on the phase relationship detected by the detection circuit.2. The frequency divider circuit according to claim 1 , whereinthe detection circuit is configured to detect whether the phase ...

Counter circuit, analog-to-digital converter, and image sensor including the same and method of correlated double sampling

A counter circuit includes a first counter and a second counter. The first counter is configured to count a first counter clock signal which toggles with a first frequency to generate upper (N−M)-bit signals of N-bit counter output signals, in response to a first counting enable signal based on a first comparison signal during a coarse counting interval. N and M are natural numbers, N is greater than M, and M is greater than or equal to 3. The second counter is configured to count a second counter clock signal which toggles with a second frequency which is higher than the first frequency to generate lower M-bit signals of the N-bit counter output signals, in response to a second counting enable signal based on the first comparison signal and a second comparison signal during a fine counting interval which follows the coarse counting interval.

RESETTING CLOCK DIVIDER CIRCUITRY PRIOR TO A CLOCK RESTART

A divider and buffer circuit uses a receive command to initiate a reset of buffer circuitry prior to restarting to avoid a metastable state. For example, the divider and buffer circuit includes a first buffer circuit, a second buffer circuit, and a reset circuit. The reset circuit receives a command and provide a pulse on a reset signal in response to the command. In response to the reset pulse, the first buffer circuit provides a first divided clock signal having a first logical value based on respective logical values of received complementary clock signals and the second buffer circuit provides a second divided clock signal having a second logical value based on the respective logical values of the complementary clock signals. The command is a CAS SYNC command, in some examples. 1. An apparatus , comprising:a first buffer circuit configured to receive complementary clock signals and a reset signal, wherein, in response to a pulse on the reset signal, the first buffer circuit is configured to provide a first divided clock signal having a first logical value based on respective logical values of the complementary clock signals;a second buffer circuit configured to receive the complementary clock signals and the reset signal, wherein, in response to the pulse on the reset signal, the second buffer circuit is configured to provide a second divided clock signal having a second logical value based on respective logical values of the complementary clock signals; anda reset circuit configured to receive a command, wherein, in response to the command, the reset circuit is configured to provide the pulse on the reset signal.2. The apparatus of claim 1 , wherein the reset circuit is further configured to receive a reset pulse end time and to determine a duration of the pulse based on the reset pulse end time.3. The apparatus of claim 1 , wherein the command is a column access strobe synchronization (CAS SYNC) command.4. The apparatus of claim 1 , wherein the first buffer ...

FREQUENCY-DIVIDER CIRCUITRY

There is disclosed configurable frequency-divider circuitry for generating a target signal of a frequency Fr/Di based on a reference signal of a frequency Fr, where Di is an integer divider ratio, the frequency-divider circuitry comprising: N divider stages organised into a ring, each stage configured to receive an input signal and generate an output signal, with the output signal of each successive stage in the ring being the input signal of the next stage in the ring, wherein: the ring of stages is controlled by the reference signal so that the output signals are governed by the reference signal; the target signal is one of the output signals or a signal derived therefrom; and at least one of the stages is a configurable stage, whose mode of operation is configurable based on a configuration signal to configure the value of Di. 1. Configurable frequency-divider circuitry for generating a target signal of a frequency Fr/Di based on a reference signal of a frequency Fr , where Di is an integer divider ratio , the frequency-divider circuitry comprising:N divider stages organized into a ring, each stage configured to receive an input signal and generate an output signal, with the output signal of each successive stage in the ring being the input signal of the next stage in the ring,wherein:the ring of stages is controlled by the reference signal so that the output signals are governed by the reference signal;the target signal is one of the output signals or a signal derived therefrom; andat least one of the stages is a configurable stage, whose mode of operation is configurable based on a configuration signal to configure the value of Di.2. Configurable frequency-divider circuitry according to claim 1 , wherein a plurality or all of the stages are configurable stages.35.-. (canceled)6. Configurable frequency-divider circuitry according to claim 1 , wherein each stage is arranged to operate in at least one of a set of modes of operation claim 1 , a combination of the ...

SIGNAL DIVIDER, SIGNAL DISTRIBUTION SYSTEM, AND METHOD THEREOF

A signal divider includes: a dividing circuit arranged to generate an output oscillating signal according to a first input oscillating signal; and a signal generating circuit, coupled to the dividing circuit, for generating an injection signal to the dividing circuit. The dividing circuit is arranged to generate the output oscillating signal with a predetermined phase according to the injection signal and the first input oscillating signal. 1. A signal divider , comprising:a dividing circuit, arranged to generate an output oscillating signal according to a first input oscillating signal; anda signal generating circuit, coupled to the dividing circuit, for generating an injection signal to the dividing circuit;wherein the dividing circuit is arranged to generate the output oscillating signal with a predetermined phase according to the injection signal and the first input oscillating signal.2. The signal divider of claim 1 , wherein the signal generating circuit is arranged to generate the injection signal according to a second input oscillating signal claim 1 , the first input oscillating signal has a first frequency claim 1 , the second input oscillating signal has a second frequency claim 1 , and the second frequency is smaller than the first frequency.3. The signal divider of claim 2 , wherein the first frequency is a multiple of the second frequency.4. The signal divider of claim 1 , wherein the injection signal is a pulse signal with a pulse width claim 1 , and the pulse width is not greater than a period of the output oscillating signal.5. The signal divider of claim 1 , wherein the injection signal is arranged to pull a voltage level of the output oscillating signal to a reference voltage level of the dividing circuit.6. The signal divider of claim 2 , further comprising:a detecting circuit, coupled to the dividing circuit and the signal generating circuit, for generating a detecting signal according to a first phase of the first input oscillating signal and a ...

FREQUENCY DIVIDER CIRCUIT, DEMULTIPLEXER CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT

A frequency divider circuit includes: a first frequency dividing circuit configured to divide a first clock signal to generate a first frequency-divided clock signal; a second frequency dividing circuit configured to divide a second clock signal having the same frequency as the first clock signal and having a first phase difference with respect to the first clock signal to generate a second frequency-divided clock signal; a detection circuit configured to detect a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; and a selection circuit configured to select and output one of the second frequency-divided clock signal and an inverted signal of the second frequency-divided clock signal which are generated by the second frequency dividing circuit, based on the phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal detected by the detection circuit. 19-. (canceled)10. A demultiplexer circuit comprising:a first demultiplexing circuit configured to convert a first input signal having a first bit width into a first intermediate signal having a second bit width larger than the first bit width, based on a first conversion clock signal generated by dividing a first clock signal;a second demultiplexing circuit configured to convert a second input signal having the first bit width and having a first phase difference with respect to the first input signal into a second intermediate signal having the second bit width, based on a second conversion clock signal generated by dividing a second clock signal having the same frequency as the first clock signal and having the first phase difference with respect to the first clock signal;a first frequency divider circuit configured to divide the first conversion clock signal to generate a third conversion clock signal having a lower frequency than the first conversion clock signal;a third demultiplexing circuit ...

Dynamic frequency divider circuit

The invention relates to a Frequency Divider Circuit for dividing an input RF signal to a frequency divided RF signal. The circuit comprises a RF pair, a switching-quad pair coupled in series with a transimpedance amplifier and a double pair of emitter followers. The circuit comprises coupling elements for providing first DC paths to first amplifier paths of the RF pair and for providing second DC paths to second amplifier paths of the series arrangement of the switching-quad pair and the transimpedance amplifier. The first DC paths are independent of the second DC paths. RF connections are provided to couple the first and the second amplifier paths for transferring a signal from the first amplifier paths to the second amplifier paths.

CORRECTION ARITHMETIC CIRCUIT AND A SIGNAL PROCESSOR

A correction arithmetic circuit disclosed herein includes an offset temperature characteristic correction unit that corrects an offset temperature characteristic of an input signal according to an input signal characteristic at a specific temperature and a temperature characteristic at a specific input signal. A signal processor disclosed herein includes a pulse count number setting circuit that generates a pulse count number setting signal in accordance with an input signal and a pulse generation unit that generates a pulse signal by counting a pulse number of a reference clock signal according to the pulse count number setting signal. The pulse count number setting circuit corrects the pulse count number setting signal so as to cancel a frequency temperature characteristic of the pulse signal. 110-. (canceled)11. A signal processor comprising:a pulse count number setting circuit that generates a pulse count number setting signal in accordance with an input signal; anda pulse generation unit that generates a pulse signal by counting a pulse number of a reference clock signal according to the pulse count number setting signal,wherein the pulse count number setting circuit corrects the pulse count number setting signal so as to cancel a frequency temperature characteristic of the pulse signal.12. The signal processor according to claim 11 , a reference pulse count number setting unit that sets a reference pulse count number according to a signal value of the input signal,', 'a correction coefficient calculation unit that calculates a correction coefficient at a current temperature based on a frequency temperature characteristic of the reference clock signal, and', 'a multiplication unit that generates the pulse count number setting signal by multiplying the reference pulse count number and the correction coefficient together., 'wherein the pulse count number setting circuit includes'}13. The signal processor according to claim 12 ,wherein the correction coefficient ...

SIGNAL DISTRIBUTION SYSTEM, AND RELATED PHASED ARRAY RADAR SYSTEM

A signal distribution system includes: a first signal divider arranged to generate a first output oscillating signal according to a first input oscillating signal; a second signal divider arranged to generate a second output oscillating signal according to the first input oscillating signal; a first transmitting channel coupled to the first signal divider and the second divider for transmitting the first input oscillating signal to the first signal divider and the second signal divider; and a second transmitting channel coupled to the first signal divider and the second divider for transmitting a second input oscillating signal to the first signal divider and the second signal divider; wherein the first input oscillating signal has a first frequency, the second input oscillating signal has a second frequency, and the second frequency is smaller than the first frequency. 1. A signal distribution system , comprising:a first signal divider, arranged to generate a first output oscillating signal according to a first input oscillating signal;a second signal divider, arranged to generate a second output oscillating signal according to the first input oscillating signal;a first transmitting channel, coupled to the first signal divider and the second divider, for transmitting the first input oscillating signal to the first signal divider and the second signal divider; anda second transmitting channel, coupled to the first signal divider and the second divider, for transmitting a second input oscillating signal to the first signal divider and the second signal divider;wherein the first input oscillating signal has a first frequency, the second input oscillating signal has a second frequency, and the second frequency is smaller than the first frequency.2. The signal distribution system of claim 1 , wherein the first frequency is a multiple of the second frequency.3. The signal distribution system of claim 1 , wherein the first signal divider comprises:a first dividing circuit ...

Frequency Division

A frequency divider comprises a signal generation stage arranged to employ a clock at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal. A synchronisation stage is arranged to generate an output signal having an output frequency divided from the clock frequency by switching between the first reference signal and the second reference signal once per cycle of the output signal.

Frequency divider and phase-locked loop including the same

A frequency divider includes a first shifter and a second shifter. The first shifter includes first to M-th clock control components connected together to form a first ring. The control components in the first shifter are controlled by an input clock signal such that signals are shifted along the first ring. An output of selected clock control components in the first shifter is provided as a carry signal of the first shifter. The second shifter includes first to N-th clock control components connected together to form a second ring. The control components in the second shifter are controlled by the carry signal of the first shifter such that the signals are shifted along the second ring. An output of selected clock control components in the second shifter is provided as a carry signal of the second shifter. M and N are integers greater than one.

Frequency Divider, Phase-Locked Loop, Transceiver, Radio Station and Method of Frequency Dividing

An electronic circuit arranged to receive an oscillating signal and output an output signal at a frequency having a frequency relation with the oscillating signal defined by a divide ratio is provided. The electronic circuit comprises a first frequency divider arranged to receive the oscillating signal and output N frequency divided signals of different phases, a second frequency divider arranged to receive one of the N signals and frequency divide the received signal by a value given by a first control signal provided to the second frequency divider, N latch circuits each being arranged to receive a respective one of the N signals at a clocking input of the respective latch circuit and to receive an output of the second frequency divider at an input of the respective latch circuit, a multiplexer circuit arranged to receive outputs of the N latch circuits and to output a signal, on which the output signal is based, selected from the received signals based on a second control signal provided to the multiplexer circuit, and a control circuit arranged to provide the first control signal and the second control signal based on the divide ratio. A phase-locked loop circuit, a transceiver circuit, a radio station, and a method of frequency dividing an oscillating signal are also provided. 115.-. (canceled)16. An electronic circuit arranged to receive an oscillating signal and output an output signal at a frequency having a frequency related to the oscillating signal by a divide ratio , the electronic circuit comprisinga first frequency divider arranged to receive the oscillating signal and output N frequency-divided signals of different phases;a second frequency divider arranged to receive one of the N frequency-divided signals and further frequency-divide the received signal by a value indicated by a first control signal provided to the second frequency divider;N latch circuits, each being arranged to receive one of the N frequency-divided signals at a clocking input and ...

N-bit counter and frequency divider

Disclosed is an N-bit counter including: an N-bit counting circuit starting counting from an initial value to generate a count value composed of N bits, and being loaded with the initial value to restart counting from the initial value when a reload signal changes from a first reload level to a second reload level; a reload signal generating circuit having the reload signal change from the first reload level to the second reload level when the logical conjunction of K bit(s) among the N bits changes from a first value to a second value; and a reset circuit having a reset signal change from a first reset level to a second reset level so as to have the reload signal change from the second reload level to the first reload level and thereby allow the N-bit counting circuit to restart counting. 1. An N-bit counter , comprising:an N-bit counting circuit configured to start counting from an initial value according to an input clock to generate a count value composed of N bits, and the N-bit counting circuit configured to be loaded with the initial value to restart counting from the initial value when a level of a reload signal changes from a first reload level to a second reload level, in which the N is an integer greater than one;a reload signal generating circuit configured to output the reload signal, and the reload signal generating circuit configured to have the level of the reload signal change from the first reload level to the second reload level when a logical conjunction of K bit(s) among the N bits changes from a first value to a second value, in which the K is a positive integer not greater than the N; anda reset circuit configured to generate a reset signal and have a level of the reset signal change from a first reset level to a second reset level when the level of the reload signal changes from the first reload level to the second reload level so that the reload signal generating circuit is reset and the level of the reload signal returns from the second ...

LOAD COMPENSATION TO REDUCE DETERMINISTIC JITTER IN CLOCK APPLICATIONS

A method for reducing deterministic jitter in a clock generator includes providing a load current through a regulated voltage node to a circuit responsive to a divide ratio. The method includes providing an auxiliary current through the regulated voltage node. The auxiliary current has a first current level during a first period corresponding to a first value of the divide ratio and the auxiliary current has a second current level during a second period corresponding to a second value of the divide ratio. 1. A method for reducing deterministic jitter in a clock generator , the method comprising:providing a load current through a regulated voltage node to a circuit responsive to a divide ratio; andproviding an auxiliary current through the regulated voltage node, the auxiliary current having a first current level during a first period corresponding to a first value of the divide ratio and the auxiliary current having a second current level during a second period corresponding to a second value of the divide ratio.2. The method claim 1 , as recited in claim 1 , wherein the method further comprisesproviding a frequency modulated clock signal based on the load current, the frequency modulated clock signal having a frequency vacillating between a first frequency and a second frequency,wherein the auxiliary current is load compensation for a load difference generated by providing the frequency modulated clock signal, the load difference being a difference between a first load corresponding to the first frequency and a second load corresponding to the second frequency.3. The method claim 2 , as recited in claim 2 ,wherein providing the frequency modulated clock signal comprises frequency dividing an input clock signal based on a regulated voltage on the regulated voltage node and a divide value vacillating between a first divide value and a second divide value,wherein the providing the regulated voltage includes providing a regulated current through the regulated voltage ...

CLOCK OPERATION METHOD AND CIRCUIT

In a clock generating circuit, a variable frequency division circuit generates a variable divided clock by dividing a source clock in accordance with a division ratio setting signal. A first clock synchronization circuit generates a first delayed clock that is delayed by a maximum number of clocks from the variable divided clock in synchronization with the source clock and supplies the first delayed clock to a control circuit. One or more second clock synchronization circuits generate one or more second delayed clocks, each of which is delayed by the maximum number of clocks from the variable divided clock in synchronization with the source clock, and supply each of the one or more second delayed clocks to each of one or more functional modules. 1. A clock generating method of generating delayed clocks to be supplied to each of one or more functional modules and a control circuit that controls operations of the one or more functional modules in a semiconductor chip on which the one or more functional modules and the control circuit are mounted , the method comprising:generating a variable divided clock by dividing a source clock in accordance with a division ratio setting signal;calculating one or more numbers of clocks by each of which the variable divided clock is delayed in synchronization with the source clock for each of the variable divided clocks connected to the one or more functional modules depending on a wiring distance of each of the variable divided clocks connected to the one or more functional modules from a variable frequency division circuit that generates the variable divided clock when a clock synchronization circuit delaying the variable divided clock is not provided, in order to operate the control circuit and each of the one or more functional modules in synchronization with the variable divided clock;calculating a maximum number of clocks that is a number of clocks greater than or equal to a largest number of clocks out of the calculated ...

TIME-INTERLEAVED MULTI-MODULUS FREQUENCY DIVIDER

Described are a multi-modulus frequency divider and event counter that are based on time-interleaved signals generated from a received signal. For the frequency divider, each time-interleaved clock signal generated from a received clock signal is provided to a bit counter and the output signal from each bit counter is provided to a multiplexer. A multiplexer selection module controls over time which one of the output signals from the bit counters is presented at the output of the multiplexer. The transition frequency of the bits in the time-interleaved clock signals allows various circuit components such as the bit counters to be implemented as CMOS components. Thus the frequency divider is more power-efficient than conventional frequency divider circuits operating at high clock frequencies. 1. A multi-modulus frequency divider , comprising:a time-interleaved multi-clock generator configured to generate a plurality of time-interleaved clock signals from a received clock signal;a plurality of bit counters each having an input in communication with the time-interleaved multi-clock generator to receive a respective one of the time-interleaved clock signals, each of the bit counters having an output to provide a counter output signal;a multiplexer having a plurality of multiplexer inputs each in communication with the output of a respective one of the bit counters, the multiplexer having a multiplexer output; anda multiplexer selection module in communication with the multiplexer and generating a selection signal based on a divider ratio, the selection signal controlling which one of the counter output signals at the multiplexer inputs is provided to the multiplexer output.2. The multi-modulus frequency divider of wherein each of the bit counters is a multi-bit counter.3. The multi-modulus frequency divider of wherein the time-interleaved multi-clock generator claim 1 , bit counters claim 1 , multiplexer and multiplexer selection module are fabricated in complementary ...

Frequency dividing apparatus and related method

A frequency dividing apparatus includes: a plurality of latching devices arranged to selectively generate an output signal having a first oscillating frequency or a second oscillating frequency different from the first oscillating frequency according to an input clock signal and a first reset signal; and a controlling device arranged to generate the first reset signal at least according to a programming input signal; wherein the first reset signal is arranged to reset a first latching device in the plurality of latching devices to make the plurality of latching devices to generate the output signal having the second oscillating frequency.

Frequency synthesizer with dynamic phase and pulse-width control

An agile frequency synthesizer with dynamic phase and pulse-width control is disclosed. In one aspect, the frequency synthesizer includes a count circuit configured to modify a stored count value by an adjustment value. The frequency synthesizer also includes an output clock generator configured to generate an output clock signal having rising and falling edges that are based at least in part on the stored count value satisfying a count threshold. The count circuit is further configured to alter at least one of the period or phase of the output clock signal based at least in part on modifying an adjustment rate of the count circuit.

RESETTING CLOCK DIVIDER CIRCUITRY PRIOR TO A CLOCK RESTART

A divider and buffer circuit uses a receive command to initiate a reset of buffer circuitry prior to restarting to avoid a metastable state. For example, the divider and buffer circuit includes a first buffer circuit, a second buffer circuit, and a reset circuit. The reset circuit receives a command and provide a pulse on a reset signal in response to the command. In response to the reset pulse, the first buffer circuit provides a first divided clock signal having a first logical value based on respective logical values of received complementary clock signals and the second buffer circuit provides a second divided clock signal having a second logical value based on the respective logical values of the complementary clock signals. The command is a CAS SYNC command, in some examples. 1. An apparatus comprising:a clock input buffer configured to receive a command, and in response to receipt of the command, to set a first clock signal to a first logical value and a second clock signal to a second logical value at a first time, wherein the clock input buffer is further configured to receive third and fourth clock signals at a third time and is configured to provide the first and second clock signals having values based on the third and fourth clock signals; anda divider and buffer circuit configured to receive the first and second clock signals and the command, wherein, in response to the command, the divider and buffer circuit is configured to provide a divided clock signal having the first logical value based on the first and second clock signals having the first and second logical values, respectively, at a second time after the first time.2. An apparatus , comprising:a clock input buffer configured to receive a command, and in response to receipt of the command, to set a first clock signal to a first logical value and a second clock signal to a second logical value at a first time; anda divider and buffer circuit configured to receive the first and second clock ...

Clock swallowing device for reducing voltage noise

Systems and methods for controlling a frequency of a clock signal by selectively swallowing pulses in the clock signal are described herein. In one embodiment, a method for adjusting a frequency of a clock signal comprises receiving the clock signal, and swallowing pulses in the clock signal according to a repeating clock-swallowing pattern, wherein the pattern is defined by a sequence of numbers.

Digital Controlled Oscillator Based Clock Generator For Multi-Channel Design

A clock divider includes, in part, a pair of counters and a programmable delay line. A first one of the counters operates at a first frequency and is configured to count using a first integer portion of the divisor. The second counter operates at a second frequency smaller than the first frequency and is configured to count using a second integer portion of the divisor. The programmable delay includes, in part, a chain of delay elements configured to generate a multitude of delays at the output of the second counter. A multiplexer selects one of the generated delays in accordance with the fractional portion of the divisor. The second counter increases its count only when the first counter reaches a terminal count. The first and second integer portions are loaded respectively into the first and second counters when the second counter reaches its terminal count. 1. A clock divider configured to divide a frequency of a received clock signal by a number having an integer portion and a fractional portion , the clock divider comprising:a first counter configured to generate a first output signal at a first frequency, where the first frequency is based on the received clock signal and a first portion of the integer portion of the number;a second counter configured to receive the first output signal and the clock signal to generate a second output signal at a second frequency, where the second frequency is based on the received clock signal and a second portion of the integer portion of the number; anda programmable delay line comprising a chain of delay elements and adapted to delay the second output signal based on the fractional portion of the number.2. The clock divider of wherein the first counter is a down counter.3. The clock divider of wherein the second counter is an up counter.4. The clock divider of wherein the first counter is a roll counter.5. The clock divider of wherein said second counter is enabled to increase its count only when the first counter reaches a ...

Clock generation circuit

A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.

PROGRAMMABLE FREQUENCY DIVIDER, PLL SYNTHESIZER AND RADAR DEVICE

A programmable frequency divider includes a modulus frequency divider, a pulse counter, and a swallow counter. The pulse counter is configured to count an output signal from the modulus frequency divider, and output a frequency division signal, and the swallow counter is configured to count the output signal from the modulus frequency divider and perform resetting on the basis of the frequency division signal from the pulse counter, the programmable frequency divider being configured to control the modulus frequency divider on the basis of a signal from the swallow counter. The programmable frequency divider includes a control signal delay circuit, disposed between an output terminal of the swallow counter and a control terminal of the modulus frequency divider, configured to delay a signal from the swallow counter, and generate a control signal for controlling the modulus frequency divider. 1. A programmable frequency divider comprising:a modulus frequency divider;a pulse counter configured to count an output signal from the modulus frequency divider, and output a frequency division signal; and 'the programmable frequency divider includes a control signal delay circuit, disposed between an output terminal of the swallow counter and a control terminal of the modulus frequency divider, configured to delay a signal from the swallow counter, and generate a control signal for controlling the modulus frequency divider.', 'a swallow counter configured to count the output signal from the modulus frequency divider and perform resetting on the basis of the frequency division signal from the pulse counter, the programmable frequency divider being configured to control the modulus frequency divider on the basis of a signal from the swallow counter, wherein'}2. The programmable frequency divider according to claim 1 , wherein the control signal delay circuit includes:a plurality of delay lines with different delay amounts; anda selector configured to select any one of the ...

Electronic Circuit, Phase-Locked Loop, Transceiver Circuit, Radio Station and Method of Frequency Dividing

Exemplary embodiments include an electronic frequency-divider circuit comprising a multi-phase generator circuit configured to: receive an oscillating input signal having a frequency f; determine an integer divide ratio Q based on a first control signal input; and based on the oscillating input signal, generate an N-phase output signal having a frequency f-divided-by-M, wherein M is an integer and adjacent phases of the N-phase output signal are separated by 360-divided-by-(M-times-Q) degrees. The divider circuit can also include a control circuit configured to receive a control input and, based on the control input: provide the first control signal to the multi-phase generator circuit; and select a particular phase of the N-phase output signal. Exemplary embodiments also include a phase-locked loop circuits, transceiver circuits, radio stations, and methods of frequency-dividing an oscillating signal. 1. An electronic frequency-divider circuit comprising: receive an oscillating input signal having a frequency f;', 'determine an integer divide ratio Q based on a first control signal input; and', 'based on the oscillating input signal, generate an N-phase output signal having a frequency f-divided-by-M, wherein M is an integer and adjacent phases of the N-phase output signal are separated by 360-divided-by-(M-times-Q) degrees;, 'a multi-phase generator circuit configured to provide the first control signal to the multi-phase generator circuit; and', 'select a particular phase of the N-phase output signal., 'a control circuit configured to receive a control input and, based on the control input2. The electronic frequency-divider circuit of claim 1 , wherein the multi-phase generator circuit comprises a first frequency divider arranged to receive the oscillating input signal and generate a first N-phase signal having a frequency f-divided-by-M claim 1 , wherein adjacent phases of the first N-phase signal are separated by 360-divided-by-M degrees.3. The electronic ...

RADAR SYSTEM AND RELATED METHOD OF SCANNING REMOTE OBJECTS

A radar system includes: a plurality of first receiving devices for generating a plurality of first digital signals according to a plurality of first incoming signals, respectively; and a plurality of second receiving devices for generating a plurality of second digital signals according to a plurality of second incoming signals, respectively. A processing device is arranged to perform a first beamforming operation to generate a plurality of first beamforming signals according to the plurality of first digital signals and a first gain matrix, and to perform a second beamforming operation to generate a plurality of second beamforming signals according to the plurality of second digital signals and a second gain matrix; and to determine an altitude angle of a first object and a second object, and to determine a first azimuth angle of the first object and a second azimuth angle of the second object. 1. A radar system , comprising:a processing device;a plurality of first receiving devices, coupled to the processing device, for generating a plurality of first digital signals according to a plurality of first incoming signals, respectively, during a receiving mode, wherein the plurality of first receiving devices are disposed on a first axis; anda plurality of second receiving devices, coupled to the processing device, for generating a plurality of second digital signals according to a plurality of second incoming signals, respectively, during the receiving mode, wherein the plurality of second receiving devices are disposed on a second axis different from the first axis;wherein, based on the plurality of first digital signals and the plurality of second digital signals, the processing device is further arranged to distinguish a first object and a second object, and the first object and the second object have a same radial speed and are located at a same range; and the processing device is further arranged to perform a first beamforming operation to generate a plurality ...

分周器

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Coincidence circuit for time sharing type counter

一种时钟分频方法及装置

本发明公开了一种时钟分频方法，通过输入时钟信号和输出时钟信息实时确定当前的分频系数，再由分频系数的整数部分、小数部分及小数部分的小数进位阈值，对输入时钟信号进行计数，并根据计数结果开始对以小数部分为累加值的累加计算，最后根据计数结果以及累加计算结果，控制输出时钟。本发明还公开了一种时钟分频装置，通过本发明的方法及装置可以根据输入信号动态调整输出信号，并可以根据需要增加分频系数整数部分、小数部分及小数部分的小数进位阈值的位宽来调节分频系数的精度。

Clock dividing circuit

본 발명은 클럭 분주 회로에 관한 것으로, 종래 기술에 있어서 짝수 분주 회로를 이용하여 홀수 분주된 클럭을 출력하지 못하고, 또한, 홀수 분주 회로는 분주되는 클럭의 분주비에 따라 각각 다른 회로 구성을 가짐으로써, 홀수 분주 회로와 짝수 분주 회로간에 호환성 및 확장성이 없는 문제점이 있었다. 따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 입력클럭을 분주비 선택 신호에 의해 선택된 분주비로 인에이블신호에 의해 분주한 분주 클럭을 출력함과 아울러 상기 분주 클럭의 듀티비를 50%로 제어하는 클럭 분주 및 듀티 제어기와; 상기 클럭 분주 및 듀티 제어기의 듀티비 제어 신호에 의해 상기 분주 클럭의 듀티비를 50%로 만들어 출력하는 듀티 클럭 발생기로 구성한 클럭 분주 회로를 제공하여 상기 분주비 선택 신호에 의해 클럭 분주부내 스테이트를 순차적으로 증가시켜 짝수 분주 및 홀수 분주후 그 클럭의 듀티비를 50%로 만들어 출력함으로써, 분주 회로의 호환성 및 확장성이 향상되는 효과가 있다. The present invention relates to a clock divider circuit, and in the prior art, an odd divided circuit cannot be output using an even divider circuit, and the odd divider circuit has a different circuit configuration according to the division ratio of the divided clocks. However, there is a problem in that there is no compatibility and expandability between odd and even division circuits. Accordingly, the present invention has been made to solve the above-mentioned problems, and outputs the divided clock divided by the enable signal at the division ratio selected by the division ratio selection signal and the duty of the division clock. A clock division and duty controller for controlling the ratio to 50%; Provides a clock division circuit composed of a duty clock generator for outputting a 50% duty ratio of the divided clock by the duty ratio control signal of the clock division and the duty controller to sequentially output the state in the clock division by the division ratio selection signal. After the even and odd divisions, the duty ratio of the clock is increased to 50% and outputted, thereby improving the compatibility and expandability of the division circuit.

Modulating method phase and frequency of pll

내용 없음. No content.

주파수 분주기 및 이를 이용한 위상 동기 루프 장치

본 발명은 디지털방식으로 동작하여 지그비 표준을 만족시킬 수 있는 주파수 분주기 및 이를 이용한 위상 동기 루프 장치에 관한 것으로서, 본 발명에 의한 주파수 분주기는 상호 입력단과 출력단이 캐스케이드 연결되고, 최종단에 위치한 래치의 출력은 초단에 위치한 래치의 입력으로 연결하여 링 순환구조로 연결되는 복수의 래치; 상기 래치들의 클럭단에 동시에 연결되며, 상기 분주할 신호를 입력받는 입력단; 및 상기 복수 래치의 출력단에 각각 연결되어 서로 다른 위상의 분주 신호를 출력하는 복수의 출력단으로 구성되고, 본 발명의 위상 동기 루프 장치는 상기 주파수 분주기를 이용하여 출력주파수를 1/P, 1/P+0.5로 분주하는 분주 수단을 구비함으로써, 5MHz의 채널 간격을 갖는 지그비 채널 주파수들을 발생시킬 수 있는 것이다. 위상 동기 루프(PLL), 디지털 주파수 분주기, 링 오실레이터, 펄스 스왈로, 위상 선택기(phase selector)

Phase locked detected for pll

내용 없음. No content.

Control signal generation unit

Frequency divider, automatic phase frequency adjustment scheme, transmitter, radio station and method of frequency division

FIELD: computer equipment.SUBSTANCE: group of inventions relates to computer technology and can be used to receive an oscillation signal and output the output signal at a frequency having a frequency relation to the oscillation signal determined by the separation factor. Device comprises a first frequency divider receiving an oscillating signal and outputting N signals divided in frequency with different phases, a second frequency divider receiving one of the N signals, wherein frequency division of the received signal by a value set by the first control signal is provided for the second frequency divider, N of the trigger locking circuits configured to receive the corresponding one of the N signals to the synchronized input of the corresponding trigger locking circuit and receive the output signal of the second frequency divider at the input of the corresponding trigger locking circuit, the multiplexer circuit and the control circuit.EFFECT: technical result is a reduction in power consumption.15 cl, 10 dwg РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (51) МПК H03K 23/66 H03L 7/099 H03L 7/191 H03L 7/197 (11) (13) 2 668 737 C1 (2006.01) (2006.01) (2006.01) (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ИЗОБРЕТЕНИЯ К ПАТЕНТУ (52) СПК H03L 7/0996 (2006.01); H03L 7/191 (2006.01); H03L 7/1974 (2006.01); H03K 23/667 (2006.01); H03K 23/68 (2006.01) (21)(22) Заявка: 2018101290, 16.06.2015 16.06.2015 Дата регистрации: Приоритет(ы): (22) Дата подачи заявки: 16.06.2015 (56) Список документов, цитированных в отчете о поиске: US 2012/0056644 A1, 08.03.2012. US (45) Опубликовано: 02.10.2018 Бюл. № 28 2007/0041486 A1, 22.02.2007. US 2004/0036513 A1, 26.02.2004. US 6542013 B1, 01.04.2003. RU 2058667 C1, 20.04.1996. SU 1259482 A1, 23.09.1986. (85) Дата начала рассмотрения заявки PCT на национальной фазе: 16.01.2018 (86) Заявка PCT: 2 6 6 8 7 3 7 R U (87) Публикация заявки PCT: WO 2016/202367 (22.12.2016) C 1 C 1 EP 2015/063497 (16.06.2015) 2 6 6 8 7 3 7 (73) ...

Clock dividing circuit, clock distributing circuit, clock dividing method and clock distributing method

Frequency synthesizer

Patent JPS53143549U

Pulse generator

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Counter enable to program

본 발명은 프로그램가능한 카운터를 공개한다. 그 회로는 클럭신호에 응답하여 0에서부터 2 n -1까지의 값을 1씩 증가하면서 카운팅하는 n개의 플립플롭들로 구성된 카운터, 카운터의 n개의 출력신호들과 카운팅 범위를 나타내는 n개의 신호들을 각각 비교하여 n개의 비교 출력신호들을 발생하기 위한 n개의 비교기들로 구성된 비교부, 및 리셋신호에 응답하여 카운터를 리셋하거나 비교부의 n개의 비교 출력신호들이 모두 동일함을 나타내는 신호인 경우에 반전 클럭신호에 응답하여 제어신호를 발생하여 카운터를 리셋하기 위한 리셋부로 구성되어 있다. The present invention discloses a programmable counter. The circuit consists of a counter consisting of n flip-flops that count in increments of 0 to 2 n -1 by 1 in response to a clock signal, n output signals of the counter, and n signals representing the counting range, respectively. A comparison unit composed of n comparators for comparing and generating n comparison output signals, and an inverted clock signal when the counter resets in response to a reset signal or a signal indicating that the n comparison output signals of the comparison unit are all the same And a reset section for generating a control signal and resetting the counter in response.

Programmable counter

Programable counter

Programmable counter

Frequency demultiplication circuit

Up/down conversion counter

본 발명은 소정 주기로 논리 상태가 전환되는 임의의 신호의 정신호와 부신호를 동기신호로 입력받아 해당 클럭의 제1논리상태 변환위치에서 데이터 입력단에 입력되는 신호를 정상태와 부상태로 출력하며 자신의 부상태 출력신호가 자신의 데이터 입력단에 궤환되는 다수개의 지연수단을 구비하고 최전단의 지연수단에는 임의의 주파수 대역을 갖는 클럭신호의 정신호와 부신호를 동기신호로 입력받고 이후의 지연수단은 전단의 지연수단에서 출력되는 정상태와 부상태 출력신호를 동기신호로 입력받는 다운카운터부와, 다운카운터부를 구성하는 각각의 지연수단에 일대일로 연결되어 있으며 카운팅 동작 모드를 업 또는 다운으로 결정하는 모드 선택 신호의 정신호와 부신호를 제어신호로 입력받아 그 신호의 상태에 따라 연결되어 있는 각 지연수단에서 출력되는 정상출력 신호를 반전 또는 비반전시켜 출력하되 모드 선택 신호의 상태가 제1논리 상태인 경우 입력신호를 반전하여 출력시키는 다수개의 출력신호 상태 변경수단을 포함하는 업/다운 전환 카운터를 제공하는 것으로, 종래 기술에서 발생되었던 문제점 즉, 업 또는 다운 카운팅 모드를 선택하기 위해 많은 개수의 논리게이트들이 필요하였음에 따라 칩화시 칩사이즈가 증가를 해소하는 효과가 있다.

Integrated circuit chip and system including the same

집적회로 칩은, 내부회로; 스트로브 신호에 응답해 상기 내부회로의 데이터 패킷을 칩 외부로 출력하기 위한 데이터 출력회로; 제1클럭을 생성하는 오실레이터; 상기 제1클럭을 분주해 제2클럭을 생성하는 분주기; 및 상기 데이터 패킷의 전송구간 중 초기구간 동안에는 상기 제2클럭을 상기 스트로브 신호로 공급하고, 상기 초기구간 이후에는 상기 제1클럭을 상기 스트로브 신호로 공급하는 스트로브 신호 공급부를 포함한다.

Frequency dividing system

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Programmable frequency divider

Frequency setting equipment generating various frequencies

Mold capacitor

(57)【要約】 【課題】 出力信号に生じるジッタ量を抑えることがで きる分周回路を提供する。 【解決手段】 直列に接続されたＤ−ＦＦ７，９，１１ を、入力信号Ｓ０を基準クロック信号として駆動し、分 周比決定信号Ｓ２１によって選択された分周比で入力信 号Ｓ０を分周して第１の分周信号Ｓ７を生成する回路モ ジュール３と、直列に接続されたＤ−ＦＦ４７，４９， ５１，５３を、第１の分周信号Ｓ７を基準クロック信号 として駆動し、当該直列に接続されたＤ−ＦＦの段数に 応じた分周比である８分周で、第１の分周信号Ｓ７を分 周して出力信号Ｓ５７を生成する回路モジュール４５ と、回路モジュール４５のＤ−ＦＦの出力および４／５ 選択信号Ｓ２４に基づいて、分周比決定信号Ｓ２１を生 成するＯＲ回路５５とを有する。

Frequency divider device

Frequency Division Circuit and Digital PLL Circuit

본 발명은 출력신호에 생기는 지터(jitter)량을 억제할 수 있는 분주회로(分周回路) 및 이러한 분주회로를 포함하는 디지털 PPL회로를 제공한다. The present invention provides a divider circuit capable of suppressing the amount of jitter generated in an output signal and a digital PPL circuit including such a divider circuit. 본 발명의 분주회로는 입력신호를 기준클록신호로 사용하는 직렬로 접속된 D-FF를 구동하고, 분주비 결정신호에 의해 선택된 분주비로 입력신호를 분주하여 제1 분주신호를 생성하는 제1 회로모듈과, 제1 분주신호를 기준클록신호로 사용하는 직렬로 접속된 D-FF를 구동하고, 직렬로 접속된 D-FF의 단수(段數)에 대응하는 분주비로, 제1 분주신호를 분주하여 출력신호를 생성하는 제2 회로모듈과, 제2 회로모듈의 D-FF의 출력 및 분주비선택신호에 따라 분주비 결정신호를 생성하는 OR회로를 포함한다. The division circuit of the present invention drives a D-FF connected in series using an input signal as a reference clock signal, and divides the input signal at a division ratio selected by the division ratio determination signal to generate a first division signal. A module and a D-FF connected in series using the first divided signal as a reference clock signal are driven, and the first divided signal is divided at a division ratio corresponding to the number of stages of the D-FF connected in series. And a second circuit module for generating an output signal, and an OR circuit for generating a division ratio determination signal according to the output of the D-FF and the division ratio selection signal of the second circuit module.

Frequency divider

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Clock generator

내용 없음. No content.

1-to-n clock dividing circuit using single clock path

본 발명은 반도체 집적회로에 관한 것으로, 특히 반도체 집적회로에서 입력된 클록을 분주하여, 임의의 분주비의 클록을 발생시키는 클록 분주 회로에 관한 것이다. 상기 본 발명에 따른 반도체 집적회로에서 입력클록을 소정의 분주비로 분주하여 출력클록을 발생시키는 클록 분주 회로는, 상기 입력클록의 펄스를 상기 분주비에 따라 정해지는 값까지 카운트하여 상기 카운트가 끝나는 시점을 알리는 제1 신호를 발생하는 카운터와, 상기 제1 신호가 발생한 시점에서 이전 출력클럭의 반전클럭을 선택하고, 상기 제1 신호가 발생하지 않은 동안에는 상기 이전 출력클럭을 선택하여, 제2 신호로서 출력하는 제1 선택기와, 상기 입력클럭과 상기 입력클럭을 분주한 클럭 중 하나를 선택하기 위한 디바이드 이네이블(DIV_EN) 신호에 따라 상기 제2 신호와 상기 반전클럭 중 하나를 선택하여, 제3 신호로서 출력하는 제2 선택기와, 상기 DIV_EN 신호에 따라 상기 이전 출력클럭을 선택적으로 출력하는 앤드(AND) 게이트와, 상기 AND 게이트의 출력 신호를 적어도 최소펄스폭만큼 지연시켜 제4 신호로서 출력하는 지연기와, 상기 입력클럭과 상기 제4 신호를 배타적 논리합(XOR) 연산하여 제5 신호를 출력하는 XOR 게이트와, 상기 제5 신호를 클록으로 하고 상기 제3 신호를 입력으로 하여 상기 출력클록을 발생하는 지연(D) 플리플롭을 포함한다. 상기 설명한 바와 같이, 본 발명에 따른 단일 경로를 사용한 클럭 분주 회로는 타임밍 클로저 단계에서 수행되는 상대 딜레이를 맞추는 반복작업을 최소화 시킬 수 있다. 또한 본 발명에 따른 단일 경로를 사용한 클럭 분주 회로는 입력클럭의 주파수를 증대시키지 않아도 되므로 종래와 2분주비 이상의 클럭을 지원하는 클럭 분주 회로와 동일한 전력소모를 갖는다. 분주 회로, 단일 클럭경로, 1분주비. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to a clock divider circuit for dividing a clock input from a semiconductor integrated circuit to generate a clock having an arbitrary division ratio. In the semiconductor integrated circuit according to the present invention, a clock division circuit for generating an output clock by dividing an input clock at a predetermined division ratio comprises: counting a pulse of the input clock to a value determined according to the division ratio and ending the count. A counter for generating a first signal for indicating a signal and an inverted clock of a previous output clock at the time when the first signal is generated, and selecting the previous output clock while the first signal is not generated, as a second signal. A third signal is selected by selecting one of the second signal and the inverted clock according to a first selector for outputting and a divide enable (DIV_EN) signal for selecting one of the input clock and the clock ...

Counter circuit, ADC and Image sensor incluing the same and method of correlated double sampling

카운터 회로는 제1 카운터 및 제2 카운터를 포함한다. 상기 제1 카운터는 제1 비교 신호에 기초한 제1 카운팅 인에이블 신호에 응답하여 코스(coarse) 카운팅 구간 동안, 제1 주파수로 토글링하는 제1 카운터 클럭 신호를 카운팅하여 N 비트의 카운터 출력 신호 중 상위 N-M 비트 신호들을 발생한다(N은 M 보다 큰 자연수, M은 3이상의 자연수). 상기 제2 카운터는 제1 비교 신호 및 제2 비교 신호에 기초한 제2 카운팅 인에이블 신호에 응답하여 상기 코스 카운팅 구간에 연속하는 파인(fine) 카운팅 구간 동안 상기 제1 주파수보다 높은 제2 주파수로 토글링하는 제2 카운터 클럭 신호를 카운팅하여 상기 N 비트의 카운터 출력 신호 중 하위 M 비트 신호들을 발생한다. The counter circuit includes a first counter and a second counter. The first counter counts a first counter clock signal toggling to a first frequency during a coarse counting period in response to a first counting enable signal based on a first comparison signal, and among the N bit counter output signals Generates high-order NM bit signals (N is a natural number greater than M, M is a natural number greater than 3). The second counter toggles to a second frequency higher than the first frequency during a fine counting period subsequent to the course counting period in response to the first comparison signal and the second counting enable signal based on the second comparison signal. Counting the second counter clock signal to ring generates low-order M bit signals among the N bit counter output signals.

Dual modulus prescaler

듀얼 모듈러스 프레스칼러(100)가 고속 동작과 관련한 성능을 개선했다. 타이밍 신호는 프레스칼러의 최종단이 클럭되기 전 2½ 클럭 사이클 동안 플립플롭 회로(106)으로부터 발생된다. 이 타이밍 신호는 셀렉트 신호를 발생하여 멀티플렉서(112)를 게이트하는데 사용된다. 초기에 타이밍 신호가 발생되므로 멀티플렉서 선택 처리는 크리티컬 패스(critical path)로부터 제거된다. 멀티플렉서를 통한 나머지 지연은 프레스칼러의 크리티컬 패스를 최소로하도록 최소화된다. The dual modulus press collar 100 has improved performance with respect to high speed operation. The timing signal is generated from the flip-flop circuit 106 for 2½ clock cycles before the final stage of the press color is clocked. This timing signal is used to generate a select signal to gate the multiplexer 112. Since the timing signal is initially generated, the multiplexer selection process is removed from the critical path. The remaining delay through the multiplexer is minimized to minimize the critical path of the press color.

Frequency division circuit

Patent JPS6250006B2

Lock detector for a digital phase locked loop

An improved multiple frequency digital phase-locked loop circuit 10 is described. The improved digital phase-locked loops utilizes a single circuit 12 to effect both phase and frequency adjustments. The multiple frequency digital phase-locked loop effects phase adjustments by selectively combining or subtracting a reference clock signal 30 with a derived programmable clock signal thereby generating a composite digital phase-locked loop clock signal. The multiple frequency provides frequency adjustments by selectively adding or subtracting pulses from the composite clock signal at a rate determined by a programmably controllable clock signal. The improved multifrequency digital phase-locked loop is suitable for use as a tone detector with the addition of a lock detector 22 wherein the phase-locked loop can be programmed for a plurality of known operating frequencies.

Counting device

High speed prescaler

내용 없음.

Clock dividing circuit

본 발명은 고주파 신호의 클럭분주시 출력되는 데이터의 손실을 방지하는 클럭분주회로에 관한것으로서, 클럭신호가 반전제어신호단에 인가되고, 반전클럭신호가 제어신호단에 인가되고, 입력단이 제 1 노드에 연결되고, 출력단이 제 2 노드에 연결된 제 1 삼상버퍼와, 일입력단에 리셋신호가 인가되고, 타입력단이 제 2 노드에 연결되고, 출력단이 제 3 노드에 연결된 제 1 노어 게이트와, 상기 반전클럭신호가 반전제어신호단에 인가되고, 입력단이 제 3 노드에 연결되고 출력단이 제 2 노드에 연결된 제 2 삼상버퍼와, 상기 클럭신호가 제어신호단에 인가되고, 반전클럭신호가 반전제어신호단에 인가되고, 입력단이 제 3 노드에 연결되고, 출력단이 제 1 노드에 연결되는 제 3 삼상버퍼와, 일입력단에 상기 리셋신호가 인가되고, 타입력단이 제 1 노드에 연결되고, 출력단이 제 4 노드에 연결되는 제 2 노어 게이트와, 상기 클럭신호가 반전제어신호단에 인가되고, 반전클럭신호가 제어신호단에 인가되고, 입력단이 제 4 노드에 연결되고, 출력단이 제 1 노드에 연결된 제 4 삼상버퍼와, 입력단이 제 1 노드에 연결된 제 1 인버터와, 입력단이 제 4 노드에 연결된 제 2 인버터를 포함한다. 이와 같은 장치에 의해서, 고주파 신호의 클럭을 분주하여 출력하는 클럭분주회로에서 데이터가 손실되는 것을 방지할 수 있다. The present invention relates to a clock division circuit for preventing the loss of data output during clock division of a high frequency signal, wherein a clock signal is applied to the inversion control signal terminal, an inverted clock signal is applied to the control signal terminal, and the input terminal is the first terminal. A first three-phase buffer connected to the node, the output terminal connected to the second node, a reset signal applied to one input terminal, the first force gate connected to the second node, and the first NOR gate connected to the third node; The inverted clock signal is applied to the inversion control signal stage, an input terminal is connected to the third node, an output terminal is connected to the second node, the clock signal is applied to the control signal terminal, and the inverted clock signal is inverted. A third three-phase buffer applied to the control signal terminal, the input terminal connected to the third node, the output terminal connected to the first node, the reset signal applied to one input terminal, and the type force terminal connected to the first node. A second NOR gate having an output terminal connected to a fourth node, the clock signal applied to an inversion control signal terminal, an inversion clock signal applied to a control signal ...

Frequency divider and phase-locked loop including the same

주파수 분주기는 제1 에지 검출부, 제2 에지 검출부, 펄스 트리거드 버퍼부 및 모드 선택부를 포함한다. 제1 에지 검출부는 분주 제어 신호를 기초로 입력 신호의 제1 에지를 검출하여 제1 카운트 신호를 발생한다. 제2 에지 검출부는 선택 신호 및 상기 분주 제어 신호를 기초로 입력 신호의 제1 에지 또는 제2 에지를 검출하여 제2 카운트 신호를 발생한다. 펄스 트리거드 버퍼부는 제1 및 제2 카운트 신호를 기초로 출력 노드의 논리 레벨을 천이하여, 입력 신호를 미리 정해진 분주비로 분주한 출력 신호를 발생한다. 모드 선택부는 선택 신호에 기초하여 미리 정해진 분주비를 홀수 분주비 또는 짝수 분주비로 설정한다.

Counter of information record reproducing device

High speed latch circuit and frequency divider having the same

리셋 기능이 구비된 래치 회로 및 이를 구비한 주파수 분주기에 있어서, 버스트 모드의 입력 클록 신호의 오프 구간동안, 논리 '0' 또는 논리 '1'로 고정된 출력 클록 신호가 생성된다. 따라서, 리셋 기능이 구비된 래치 회로 및 이를 구비한 주파수 분주기가 채용된 버스트 모드의 시스템은 입력 클록의 입력 시점과 동시에 정확한 분주 동작을 수행할수 있다. In a latch circuit with a reset function and a frequency divider having the reset function, an output clock signal fixed to logic '0' or logic '1' is generated during an off period of an input clock signal in a burst mode. Therefore, the burst mode system employing the latch circuit having the reset function and the frequency divider having the reset function can perform the accurate division operation simultaneously with the input timing of the input clock.

Digital switch

Clock scaling circuit

본 발명은 클럭 분주 회로에 관한 것으로, 종래의 회로에 있어서는 분주회로가 피엘엘의 출력신호(PLL OUT)를 가지고 분주하는 경우 정상적으로 피엘엘이 동작할 때 리셋을 걸게 되면 궤환신호(Feedback CLK)가 비정상적으로 동작해 피엘엘이 오동작을 일으킬 수 있기 때문에 분주회로를 초기화 시키지 못하게 되는 문제점이 있었다. 따라서, 본 발명은 외부로 부터 들어오는 신호에 의해 임의의 주파수와 위상의 동기를 취하는 피엘엘과; 바이패스신호에 의해 상기 피엘엘부에서 출력하는 출력신호(PLL OUT) 또는 그 입력신호(PLL CLK)를 선택하여 출력하는 멀티플렉서와; 상기 멀티플렉서를 통해 출력되는 클럭을 분주하는 분주부로 구성된 클럭 분주 회로에 있어서, 상기 바이패스신호와 시스템 리셋신호를 입력받아 바이패스 모드일 경우 시스템 리셋신호에 의해 상기 분주부를 리셋하는 초기화부를 더 포함하여 클럭이 피엘엘을 통하지 않고 바이패스 되는 경우에 클럭 분주부를 초기화 하도록 하여 테스트가 용이하도록 하는 효과가 있다. The present invention relates to a clock divider circuit. In the conventional circuit, when the divider circuit divides with the output signal (PLL OUT) of the PEL, the feedback signal (Feedback CLK) is reset when the PEL operates normally. There was a problem in that it can not initialize the frequency division circuit because abnormal operation may cause the PL to malfunction. Accordingly, the present invention provides a PEL that synchronizes an arbitrary frequency and phase by a signal from an external source; A multiplexer for selecting and outputting an output signal (PLL OUT) or its input signal (PLL CLK) output from the PEL unit by a bypass signal; A clock divider circuit comprising a divider for dividing a clock output through the multiplexer, the clock divider comprising: an initialization unit configured to receive the bypass signal and a system reset signal and reset the divider by a system reset signal in a bypass mode; In addition, when the clock is bypassed through PEL, the clock divider is initialized to facilitate the test.

Frequency counter

게이트 신호 자동조정 기능을 구비하는 주파수 카운터에 관한 것으로, 피측정신호를 입력받아 직류성분을 제거하는 신호 결합부와, 상기 신호결합부에서 출력되는 신호를 구형파로 변환하는 레벨조정부와, 상기 레벨조정부에서 출력되는 구형파 신호의 주파수를 카운트하는 제1동기 카운터부와, 상기 제1동기 카운터부에서 출력되는 카운트 값과 사전에 정해진 값을 비교하는 비교부와, 상기 비교부의 출력과 상기 제1동기 카운터부의 카운트 시작신호를 입력으로 하는 플립플롭과, 상기 비교부의 출력과 상기 카운트 시작신호를 지연시키는 제1 및 제2 지연소자들과, 상기 지연소자들의 출력을 오아 연산하여 상기 플립플롭의 클록신호로 인가하는 오아 게이트와, 기준 클록신호를 발생시키는 기준 클록 발생부와, 상기 플립플롭의 축적과 기준 클록 발생부의 출력을 앤드하는 앤드 게이트와, 상기 앤드 게이트의 출력을 카운트하는 제2동기 카운터부와, 상기 동기 카운터부의 카운트 값과 상기 사전에 정해진 값의 비에 상기 기준클록의 주파수를 곱하여 피측정신호의 주파수로 하는 제어부와, 상기 제어부의 입출력신호를 인터페이스하는 인터페이스부로 구성된다. A frequency counter having an automatic gate signal adjustment function, comprising: a signal combiner for receiving a signal to be measured and removing a DC component; a level adjuster for converting a signal output from the signal combiner into a square wave; and the level adjuster A first synchronous counter unit for counting a frequency of the square wave signal output from the first synchronous counter, a comparator for comparing a count value output from the first synchronous counter unit with a predetermined value, an output of the comparator and the first synchronous counter A flip-flop for inputting a negative count start signal, first and second delay elements for delaying the output of the comparator and the count start signal, and an output of the delay elements to be computed as a clock signal of the flip-flop An OR gate to be applied, a reference clock generator for generating a reference clock signal, accumulation of the flip-flop and reference clock generation A signal to be measured by multiplying a frequency of the reference clock by a ratio of an AND gate for ANDing the output of the raw part, a second synchronous counter part for counting the output of the AND gate, a count value of the synchronization counter part, and a predetermined value; And a control unit configured to have a frequency of, and an interface unit for interfacing the input / output signals of the control unit.

Device for presetting an electrical pulse counter

Multiple frequency digital phase locked loop

내용 없음. No content.

Programmable counter

Programable frequency divider using sigma-delta modulator

A programmable frequency divider using sigma-delta modulator is provided to reduce the quantization noise and a fractional spurious, by using a high quantization resolution of sigma-delta modulator and varying the variable dividing ratio of a prescaler. A programmable frequency divider divides an oscillation signal by using a sigma-delta modulator(110) having 0.5 step resolution and provides an output signal. The programmable frequency divider using the sigma-delta modulator(110) comprises a prescaler(200), a main counter(300) and a pulse swallow counter(400). The prescaler(200) divides the oscillation signal by the decided variable dividing ratio. The variable dividing ratio is decided to 0.5 step according to the output signal level, a pulse swallow signal(SW) and an up-dividing signal(SUP) or a down-dividing signal(SDN) of the sigma-delta modulator. The main counter(300) divides the frequency signal from the prescaler(200) into a main dividing ratio(M) decided previously. The pulse swallow counter(400) is synchronized to the clock of the main counter(300), provides the pulse swallow signal(SW) to a low level and outputs the pulse swallow signal(SW) to a high level when the count value of the clock corresponds to the preset pulse swallow value(S).

counter

본 발명에 따른 카운터는 외부 클럭 신호에 의해 제어되는 제 1 카운터와 상기 제 1 카운터의 최상위 출력 신호의 반전 신호에 의해 제어되는 제 2 카운터를 포함한다. 상기 제 1 및 제 2 카운터들은 상기 쉬프트 레지스터의 원리를 이용하여 구현하였으며, 플립플롭의 수를 감소시키기 위하여 상기 제 2 카운터는상기 제 1 카운터의 최상위 출력 신호를 클럭 신호로 받아들이는 비동기식 구조를 사용하였다. 이러한 구조는 높은 비트의 카운터일수록 카운터가 차지하는 면적을 줄일 수 있고 그리고 카운터에서 리플되어 발생하는 지연 시간을 감소시켜 카운팅 속도를 향상시킬 수 있다.

Variable dividing circuit

To provide a variable dividing circuit having a high operational speed. The variable dividing circuit includes a shift register configured by cascade connection of D-type flip-flops (D 11 , D 12 , . . . , D 1 n) with an initializing means by clock synchronization; and a multiplexer 12 for selecting any one of output signals at respective stages of the shift register; wherein the variable dividing circuit initializes each stage of the D-type flip-flops. In this case, in an input terminal 10 of the flip-flop at the first stage, a signal at an H level or at an L level is inputted in accordance with an initializing means.

Timer device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Counting circuit

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Fast programmable divider with a new 5-gate flip-flop

An N-bit programmable divider comprising N "T" flip-flops, N load gates, N-2 enable gates, an output JK flip-flop and a least-significant-bit input inverter; the least-significant-bit flip-flop being enabled by Q of said output flip-flop, the second-least-significant-bit flip-flop being enabled by Q of said least-significant-bit flip-flip, each of said remaining T flip-flops being enabled by NORed Q outputs of all less-significant-bit flip-flops, said output flip-flop having a J input only when the outputs of said N T flip-flops are indicative of a count of 2 and having a K input only with a Q output of said output flip-flop; the divider being loaded by application during Q of the output flip-flop of the complement of the least-significant-bit signal to the clear of the least-significant-bit T flip-flop and higher-significant-bit signals to preset of respective higher-significant-bit T flip-flops.

PROGRAMMABLE FREQUENCY DIVIDING DEVICE

Le réseau de division de fréquence programmable comprend une pluralité d'étages de division de fréquence programmables reliés en cascade, chacun d'eux divisant la fréquence d'une impulsion d'horloge par deux ou par trois, sur la base d'un niveau logique d'un signal d'entrée préfixé, utilisé pour modifier un rapport de division variable, afin de passer d'une valeur à une autre. Il comporte en outre des moyens à porte logique 25, 26, 27 pour détecter si chacune des sorties des étages de division de fréquence programmables qui suivent un deuxième étage de division de fréquence programmable du réseau de division de fréquence programmable, présente une forme prédéterminée, de façon à diviser la fréquence de l'impulsion d'horloge par trois si le signal de sortie est positif dans la procédure de détection. Application à des systèmes de verrouillage de fréquence à grande vitesse.

Well logging tool scale selection circuit

1362898 Scale selection TEXACO DEVELOPMENT CORP 4 Sept 1972 41005/72 Heading G4H The division factor of a divider comprising a chain of bi-stables is set remotely by changing the count in a counter, the output of which enables one of a set of gates connected one to each bi-stable. The system may be used for altering the output count of an oil well radioactivity logging tool. As shown, pulses proportional to radiation are generated in " logging tool electronics " 10 and fed via line 11 to bistables 12-17 which act as divide by two circuits. The output of each bi-stable is also connected to the input of an AND gate 44-49 and the outputs of these gates are connected via OR gate 52 to " logging tool electronics ". One gate at a time can be enabled and the output pulses are either logged in 10 or passed to the surface via cable 30. The gate that is enabled is determined by the state of the binary counter comprising bi-stables 55, 56, 57 which are connected to the gates 44-49 so that six of the eight possible slots of the counter enable gates, the other two being used for reference, A.C. pulses are transmitted from the surface to step the counter. These pulses pass low-pass filter 36 and resonant circuit 36 and are converted to D.C. pulses in differential amplifier 40 and trigger 41.

Frequency divider circuit

본 발명은 주파수 분주 회로에 관한 것으로, 클록 신호를 입력으로 받아 이를 반전시켜 출력하는 제1인버터와, 클록 신호를 입력으로 받아 이를 반전시켜 출력하는 제1인버터와, 클록 신호를 입력으로 받아 이를 반전시켜 출력하는 제2인버터와, 입력된 신호의 출력이 상기 클록 신호와 반전된 클록 신호에 따라 제어되며, 출력 신호가 주파수 분주 회로의 출력 신호인 제3인버터와, 상기 제3인버터의 출력 신호를 반전시켜 상기 제3인버터에 입력되도록 연결된 제4인버터와, 상기 클록 신호와 반전된 클록 신호에 의하여 온·오프 제어되고, 상기 제4인버터의 출력 신호를 입력받아 전송하도록 이루어진 제1트랜스미션 게이트와, 상기 제1트랜스미션 게이트를 통해 전송되는 신호를 입력으로 받아 이를 반전시켜 출력하는 제5인버터와, 상기 클록 신호와 반전된 클록 신호에 의하여 온·오프 제어되고, 상기 제5인버터에서 출력되는 신호를 입력으로 받아 이를 반전시켜 출력하는 제6인버터와, 상기 클록 신호와 반전된 클록 신호에 의하여 온·오프 제어되고, 상기 제6인버터에서 출력되는 신호를 입력받아 전송하도록 이루어진 제2트랜스미션 게이트를 포함하여 이루어져서, 플립플롭을 사용하지 않고서 주파수의 분주가 이루어지도록 하여 스파이크가 발생하는 문제를 원천적으로 해결하고, 적은 수의 논리 소자만을 사용하여 주파수 분주 회로를 구현함으로써 회로의 레이아웃 면적을 크게 감소시키며, 입력된 신호가 출력되는 과정에서 시간 지연이 극히 적어 매우 빠른 응답 속도를 얻을 수 있도록 하는 효과가 제공된다. The present invention relates to a frequency divider circuit, comprising: a first inverter that receives a clock signal as an input and inverts it and outputs it, a first inverter that receives the clock signal as an input and inverts it and outputs it; A second inverter outputting a second inverter, an output of the input signal is controlled according to the clock signal and an inverted clock signal, and an output signal is a third inverter that is an output signal of a frequency division circuit, and an output signal of the third inverter A fourth inverter connected to be inverted and input to the third inverter, a first transmission gate controlled on and off by the clock signal and an inverted clock signal, and configured to receive and transmit an output signal of the fourth inverter; A fifth inverter that receives a signal transmitted through the first transmission gate as an input, inverts the signal, and outputs the inverted signal; A sixth inverter that is turned on and off by a clock signal that has been turned on, receives a signal output from the fifth inverter as an input, and inverts and outputs it as an input, and is turned on and off by the clock signal and an inverted clock signal, It includes a ...

Fifty percent duty cycle divided-by-m counter

Disclosed is a divide-by-m counter for generating an ouptut clock signal having a fifty percent duty cycle from a higher frequency source clock signal having m cycles for each single cycle of the output clock signal and wherein m may be an odd or even integer number, the divide-by-m counter including a modulo binary counter for counting up to a predetermined number, circuitry for presetting the modulo binary counter by another predetermined number, counter clock selector for providing a counter clock signal to the modulo binary counter which, when m is odd, will be either an non-inverted source clock or an inverted source clock based upon the occurrence of either the HIGH or LOW intervals of the output clock, and interval defining circuitry for defining the beginning of such HIGH and LOW intervals of the output clock based upon the occurrence of a ripple carry pulse from the modulo binary counter.

Variable frequency divider

FREQUENCY DIVIDER FOR ELECTRONIC WATCH

A divider for an electronic timepiece comprises a multistage divider circuit having a plurality of 1/2 dividing stages connected in cascade. Logic circuitry connected to the first and last stages develops a preselected number of pulse signals smaller in number than the dividing number of the divider circuit to effect selective stopping of the counting of only one input signal pulse applied to the divider circuit to thereby obtain fine adjustment of the final output signal pulses.

Clock operation method and circuit

本发明提供一种时钟生成方法及时钟生成电路，在所述时钟生成电路中，可变分频电路根据分频比设定信号生成将源时钟进行分频的可变分频时钟。本发明的第1时钟同步电路与源时钟同步而生成将可变分频时钟延迟最大时钟数的第1延迟时钟，并供给于控制电路。1个以上的第2时钟同步电路与源时钟同步而生成将可变分频时钟分别延迟最大时钟数的1个以上的第2延迟时钟，并供给于1个以上的各功能模块。

Phase-switched dual-mode divider counter circuit for a frequency synthesizer

本发明涉及一种用于频率合成器的双模分频器计数器电路，其包括几个串联连接的1∶2异步分频器，一个插入在两个1∶2分频器(10，12)之间的相位选择器块(11)和用以根据所选模式提供控制信号(S0，S1，S2)给选择器块的一个控制块(13)。所述选择器块从第一主从式分频器接收四个彼此相比相移90°的信号同时从四个相移信号中提供一个选中的信号。控制信号(S0，S1，S2)提供给选择器块用来在特定的分频周期中从四个相移信号中选择一个信号(F2)。基于在所选模式中由控制块(13)提供的控制信号，选择器块在每个分频周期中，操作由每个支路所选的两个相移信号间的相位切换。所选的第二柑移信号与第一相移信号相比相位超前90°。

FREQUENCY DIVIDER

L'invention concerne les diviseurs numériques de fréquence. Un diviseur de fréquence comporte essentiellement un compteur binaire synchrone programmable 22, et deux bascules 28, 36 qui commandent des portes 16, 18 branchées à l'entrée d'horloge du compteur. Le compteur divise par 3,25 ce qui permet d'obtenir un signal dont fréquence est voisine d'une puissance entière de 10, à partir d'un oscillateur dont la fréquence est égale à une puissance entière de 2. Application aux circuits électroniques. The invention relates to digital frequency dividers. A frequency divider essentially comprises a programmable synchronous binary counter 22, and two flip-flops 28, 36 which control gates 16, 18 connected to the clock input of the counter. The counter divides by 3.25 which makes it possible to obtain a signal whose frequency is close to an integer power of 10, from an oscillator whose frequency is equal to an integer power of 2. Application to electronic circuits.

FREQUENCY DIVISION DEVICE WITH PREDIVISOR FOLLOWED BY A PROGRAMMABLE COUNTER, PREDIVISOR AND CORRESPONDING FREQUENCY SYNTHESIZER

PROGRAMMABLE FREQUENCY DIVIDER.

DIGITAL FREQUENCY DIVIDER CIRCUIT

DIVIDER CIRCUIT

a. Diviseur. b. Diviseur caractérisé par une horloge donnant deux signaux d'horloge de fréquence N, sans chevauchement, une première logique coopérant avec une transmission de la première cadence pour créer une première sortie, une seconde logique répondant au premier et au second signal de cadence pour créer une seconde sortie, une troisième logique coopérant avec la présence de la première ou de la seconde sortie et donnant une troisième sortie. c. L'invention s'applique notamment à l'affichage Vidéo. at. Divider. b. Divider characterized by a clock giving two clock signals of frequency N, without overlap, a first logic cooperating with a transmission of the first rate to create a first output, a second logic responding to the first and to the second rate signal to create a second output, a third logic cooperating with the presence of the first or the second output and giving a third output. vs. The invention applies in particular to video display.

External programming system for forwards-backwards counters - with inaccessible set-inputs and comparator gating pulses to direct reversing circuit

The external programming system, for programming separate forwards-backwards counters, has the outputs of the forwards-backwards counter (1) and the data transmitter (4) connected to a comparator (2). The comparator coincidence output is connected to the control input of a gate (3) connected between a pulse generator output (5) and a count-direction reversing circuit input (6). The direction reversing circuit output is connected to the forwards-backwards counter count input. The system allows counters to be programmed externally with accessible counter-contents but inaccessible set inputs. This system in conjunction with other circuits reduces the counter sensitivity to noise.

Adjustable frequency divider

Patent FR2246122A1

Patent FR2423091B3

METHOD FOR DIGITALLY ADJUSTING THE FREQUENCY OF AN OSCILLATOR IN AN ELECTRONIC MEASURING DEVICE

L'INVENTION CONCERNE UN PROCEDE D'AJUSTEMENT DE LA FREQUENCE D'UN OSCILLATEUR A CRISTAL PIEZO-ELECTRIQUE. LA FREQUENCE EFFECTIVE DE L'OSCILLATEUR 1 EST AJUSTEE PAR BLOCAGE PERIODIQUE DES IMPULSIONS DESTINEES A UN ETAGE DIVISEUR 9. LE CIRCUIT D'INHIBITION D'IMPULSIONS COMPORTE UNE MEMOIRE FIXE PROGRAMMABLE REMANENTE 13 QUI MEMORISE DES INFORMATIONS COMPLEMENTAIRES BINAIRES CORRESPONDANT AU NOMBRE D'IMPULSIONS DE L'OSCILLATEUR A SUPPRIMER. UN COMPTEUR 10 EST PERIODIQUEMENT PREPOSITIONNE AU MOYEN DE L'INFORMATION COMPLEMENTAIRE BINAIRE, ET LE COMPTAGE SE DEROULE EN REPONSE AUX IMPULSIONS DE L'OSCILLATEUR. LE NOMBRE DE COMPTAGE EXPRIMANT LA DIFFERENCE ENTRE LE NOMBRE COMPLEMENTAIRE ET LE NOMBRE MAXIMAL DU COMPTEUR COMMANDE LE NOMBRE D'IMPULSIONS QUI SONT PERIODIQUEMENT SUPPRIMEES. LA PROGRAMMATION DE LA MEMOIRE FIXE EST EFFECTUEE PENDANT LA FABRICATION DU DISPOSITIF DE MESURE DU TEMPS. L'INVENTION S'APPLIQUE NOTAMMENT AUX MONTRES-BRACELETS DESTINEES A ETRE FABRIQUEES EN SERIE. THE INVENTION RELATES TO A PROCESS FOR ADJUSTING THE FREQUENCY OF A PIEZO-ELECTRIC CRYSTAL OSCILLATOR. THE EFFECTIVE FREQUENCY OF OSCILLATOR 1 IS ADJUSTED BY PERIODIC LOCKING OF THE PULSES INTENDED FOR A DIVIDING STAGE 9. THE PULSE INHIBITION CIRCUIT INCLUDES A FIXED PROGRAMMABLE MEMORY REMANTED 13 WHICH STORES ADDITIONAL BINARY INFORMATION IN THE CORRESPONDING NUMBER OF BINARY THE OSCILLATOR TO BE DELETED. A COUNTER 10 IS PERIODICALLY PREPOSITIONED BY MEANS OF THE COMPLEMENTARY BINARY INFORMATION, AND THE COUNTING TAKES PLACE IN RESPONSE TO THE PULSES OF THE OSCILLATOR. THE NUMBER OF COUNTING EXPRESSING THE DIFFERENCE BETWEEN THE ADDITIONAL NUMBER AND THE MAXIMUM NUMBER OF THE COUNTER CONTROLS THE NUMBER OF PULSES WHICH ARE PERIODICALLY REMOVED. THE FIXED MEMORY PROGRAMMING IS CARRIED OUT DURING THE MANUFACTURE OF THE TIME MEASURING DEVICE. THE INVENTION APPLIES IN PARTICULAR TO BRACELET WATCHES INTENDED TO BE MANUFACTURED IN SERIES.

COINCIDENCE LOGIC PORT, TRIPLET OF LOGIC DOORS AND SEQUENTIAL LOGIC CIRCUIT IMPLEMENTING THIS LOGIC PORT

Electronic counter

Sound generating frequency converter - has groups of dividers for rising or falling flanks of input pulses

The dividers input is connected to the first input of a first series of gate circuits. A suppressor circuit comprises one input receiving a series of pulses, an output leading via an inverter circuit to the divider group and a second input connected to the first gate circuit. A pulse received at the second input causes suppression of a pulse at the first input. Each divider provides a frequency 2-x times that of the series of pulses at the input of the divider series, where x is the ordinal number of the divider. The divider groups are formed by the adjacent dividers where 2-x in the binary counting system is an even number (0 or 1) and the binary number is formed by the frequency which must be subtracted from the series of pulses, in order to obtain the frequency of the desired range at the input of the divider series, the latter frequency being standardised at 1.

ASYNCHRONOUS QUEUE WITH STACK OF REGISTERS

LA FILE D'ATTENTE, UTILISABLE EN INFORMATIQUE ET TRAITEMENT NUMERIQUE DU SIGNAL, COMPREND UN EMPILEMENT EN CASCADE DE REGISTRES IDENTIQUES 10 DE STOCKAGE DE DONNEES ET UNE CHAINE LOGIQUE DE COMMANDE DE SOUS-ENSEMBLES IDENTIQUES ASSOCIES CHACUN A UN DE REGISTRES. LES REGISTRES 10 SONT DU TYPE A VERROUILLAGE AYANT UN ETAT TRANSPARENT ET UN ETAT VERROUILLLE, CHAQUE SOUS-ENSEMBLE COMPORTANT UN COMMUTATEUR 16 CONSTITUE DE FACON A FOURNIR, SUR SA SORTIE A RELIEE AU REGISTRE ASSOCIE, UN SIGNAL LOGIQUE REPRESENTATIF DE L'ETAT DU SOUS-ENSEMBLE AMONT OU AVAL SUIVANT QUE LE REGISTRE ASSOCIE AU SOUS-ENSEMBLE COMPRENANT LE COMMUTATEUR EST LIBRE OU OCCUPE. THE WAITING QUEUE, USABLE IN COMPUTER SYSTEMS AND DIGITAL SIGNAL PROCESSING, INCLUDES A CASCADED STACK OF IDENTICAL DATA STORAGE REGISTERS AND A LOGIC CHAIN FOR ORDERING IDENTICAL SUB-SETS EACH ASSOCIATED WITH ONE OF THE REGISTERS. THE REGISTERS 10 ARE OF THE LOCKING TYPE HAVING A TRANSPARENT STATE AND A LOCKED STATE, EACH SUB-ASSEMBLY INCLUDING A SWITCH 16 CONSTITUTES IN A MANNER TO BE PROVIDED, ON ITS OUTPUT CONNECTED TO THE ASSOCIATED REGISTER, A LOGICAL SIGNAL OF THE REPRESENTATIVE OF THE STATE - UPSTREAM OR DOWNSTREAM ASSEMBLY AS THE REGISTER ASSOCIATED WITH THE SUBASSEMBLY INCLUDING THE SWITCH IS FREE OR OCCUPIED.