CRYSTAL OSCILLATOR WITH CONTROLLED DUTY CYCLE

An oscillator circuit has a temperature and voltage compensating circuit (33), a variable current source (37), a duty cycle monitor and control circuit (35), a pull-down transistor (31) and an amplifier (39). Duty cycle monitor and control circuit (35) adjusts ramp-up current (Irmp) such that node (Va) reaches the threshold level of amplifier (39) at the same time during each cycle regardless of the duty cycle of pulse sequence (OSC).

CRYSTAL OSCILLATOR WITH CONTROLLED DUTY CYCLE

An oscillator circuit has a temperature and voltage compensating circuit (33), a variable current source (37), a duty cycle monitor and control circuit (35), a pull-down transistor (31) and an amplifier (39). Duty cycle monitor and control circuit (35) adjusts ramp-up current (Irmp) such that node (Va) reaches the threshold level of amplifier (39) at the same time during each cycle regardless of the duty cycle of pulse sequence (OSC).

APPARATUSES AND METHODS FOR COMMAND DECODING

In some examples, command decoders may have multiple command paths. In some examples, command signals from one command path may be provided to another command path from a node located between two latches of the command decoder, such as two latches of a flip-flop. In some examples, the command decoder may include separate flip-flops for different command modes. In some examples, the separate flip-flops may be tristate flip-flops. In some examples, the command decoder may include alternate logic circuits rather than a multiplexer.

A DIFFERENTIAL KASKODE SWITCH OF UTILIZATION PULSED FLIP-FLOPS OF THE D-TYPS

МНОГОЗНАЧНЫЙ ТРИГГЕР

Изобретение относится к области вычислительной техники. Технический результат заключается в повышении быстродействия специализированных вычислителей таких как многозначный триггер. Указанный результат достигается за счет использования многозначного триггера, который содержит первый логический элемент с первым и вторым токовыми входами, а также первым и вторым токовыми выходами, второй логический элемент с первым и вторым токовыми входами, а также первым и вторым токовыми выходами, причем первый токовый вход второго логического элемента соединен с первым токовым выходом первого логического элемента, второй токовый вход первого логического элемента соединен с первым входом предустановки логического элемента памяти, второй вход второго логического элемента связан со вторым входом предустановки состояния устройства, второй токовый выход первого логического элемента связан с первым токовым выходом состояния устройства, второй токовый выход второго логического элемента связан со вторым токовым ...

SAW-TOOTH GENERATOR WITH LOW TENSION

Through the comparator generates a pulse of half-duplex RFID oscillation maintaining circuit

MULTI-LEVEL DRIVE DATA TRANSMISSION CIRCUIT AND METHOD

The disclosed multi-level driving data transmission circuit and operating method include: a first driving module including a first signal generating unit and a first three-state driver, and a second driving module, including a second three-state driver. The first input terminal of the second three-state driver is coupled to the output terminal of the first three-state driver. The first signal generating unit includes a first and second input terminals, and an output terminal. The output terminal of the first signal generating unit couples to the second input terminal of the first three-state driver. The first signal generating unit receives the first signal through its first input terminal and the first feedback signal of the first signal from the second driving module through its second input terminal. The resultant first control signal has an effective signal width wider than the first signal. The first control signal inputs to the first three-state driver. 1. A multi-level drive data transmission circuit , comprising:a first driving module comprising a first signal generating unit and a first three-state driver; anda second driving module comprising a second three-state driver;wherein a first input terminal of the second three-state driver is coupled to an output terminal of the first three-state driver;wherein the first signal generating unit comprises: a first input terminal, a second input terminal, and an output terminal;wherein the output terminal of the first signal generating unit couples with the second input terminal of the first three-state driver;wherein the second driving module comprises a second input terminal,wherein the first signal generating unit is configured to receive a first signal through the first input terminal and a first feedback signal of the first signal from the second driving module through the second input terminal;wherein a first control signal is generated based on the first signal and the first feedback signal of the first ...

PERSISTENT NODES FOR RFID

An RFID transponder in one embodiment comprises a radio frequency (RF) transceiver, processing logic coupled to the RF transceiver, a switch coupled to the processing logic, a tunneling device coupled to the switch and a differential sensing circuit having a first input coupled to the tunneling device and a second input coupled to a predetermined reference voltage. In one embodiment, the tunneling device can discharge to a voltage below the predetermined reference voltage.

Integrated, bistable flip=flop with differential amplifier - has current mirror in output branch of each amplifier switching transistor

The differential amplifier consist of two pnp transistors (T1,2) acting as switches, which are alternately made conductive by supplied current pulses. In the output branch of each switching transistor is fitted an active load of a current mirror (T3, 4) between collector and supply voltage (+V). The mirror two conductive transistors have their output current fed back to the switching transistor(s) input that it remains conductive. For the flip-flop switching, the base-emitter voltage of each non-conductive switching transistor is lifted for a short period such that the respective transistor becomes conductive. ADVANTAGE - No rapid switching and no substrate current injection.

Oscillator with controlled duty cycle

An oscillator circuit having a first node oscillating with a first indeterminate duty cycle and having a second node oscillating with a predetermined second duty cycle. Both nodes oscillate at similar frequencies. A variable current source and a switch are coupled in series between Vcc and ground with the output of the variable current source being the second node. The first node controls the switch, which is closed when the first node is at a first logic state and is opened when it is at a second logic state. During each cycle, a monitoring circuit measures the time span that the first node is at the first logic state and adjusts the magnitude of the variable current source to make it directly proportional to the measured time span. By adjusting the variable current source, the second node can be made to reach a desired voltage level in a desired amount of time during each cycle. In a second embodiment, a current limiting transistor is inserted between the second node and the switch. The ...

AN OSCILLATION MAINTENANCE CIRCUIT WITH COMPARATOR-BASED PULSE GENERATION IN HALF-DUPLEX RFID TRANSPONDERS

An oscillation maintenance circuit with comparator-based pulse generation is provided. By sampling an RF signal and controlling a pulse generation circuit to generate a pulse signal of the same frequency as the RF signal, a switch unit is controlled to be ON/OFF at a same frequency as the RF signal, achieving synchronization between change of the current injection and the RF signal. Thus, the oscillation frequency is not affected by current injection, ensuring the FSK communication performance. At the same time, two comparators are respectively compared with two reference voltage levels to obtain an output pulse signal, and the reference voltage levels can be adjusted according to practical requirements, so that the switch-on point of time and current injection time duration are adjustable, maximizing the efficiency of current injection, resulting in simple circuit structure, low power consumption, and increased communication distance of an HDX passive RFID transponder. 1. A half-duplex RFID oscillation maintenance circuit with comparator-based pulse generation , comprising:a resonance inductor and a resonance capacitor connected in parallel between a first antenna end and a second antenna end, wherein the resonance inductor and the resonance capacitor form a resonance circuit that is coupled to an external radio frequency field to generate an alternating current, and inputs the alternating current to a rectifier circuit;wherein an output end of the rectifier circuit is connected to an energy-storage capacitor and an internal circuit;wherein the first antenna end and the second antenna end are connected to an end-of-burst detection circuit, an output end of end-of-burst detection circuit is connected to a control end of a pulse generation circuit, so as to detect an RF signal of the first antenna end and the second antenna end and to control an operation state of the pulse generation circuit according to the RF signal;wherein the first antenna end and the second ...

REFRESH CIRCUIT, REFRESH METHOD AND SEMICONDUCTOR MEMORY

A refresh circuit includes: a signal generation module, configured to generate an inversion signal and a carry signal based on a refresh command; an adjustment unit, configured to generate, if a first refresh signal and a second refresh signal are generated based on the refresh command, an inversion adjustment signal according to the inversion signal, and generate, if only the first refresh signal is generated based on the refresh command, the inversion adjustment signal according to an inversion signal corresponding to a first refresh signal generated based on a current refresh command, and generate the inversion adjustment signal only according to an inversion signal corresponding to a second refresh signal generated based on a next refresh command; and a counting module, configured to generate a first output signal and a second output signal, and invert the first output signal based on the inversion adjustment signal.

Latch

Tunable timer for memory arrays

The present invention is directed to a tunable delay element incorporating one-half of a bipolar SRAM cell and a reference generator. In operation, the rising edge and incoming clock pulse sets the receiver/latch, latching the internal clock (i.e., the write pulse). The same rising edge of the clock pulse also functions to initiate the switching of the half memory cell in the tunable delay. When the half memory cell is switched halfway to its second state (relative to the referenced generator) the latch is disabled and the ICL write pulse goes low. The ICL write pulse is thus self-timed to be operational in the actual memory cell. Some delay circuitry is also provided for controlling the switching speed of the half memory cell in the tunable delay in order to selectively adjust the ICL pulse width.

Precision multivibrator using stabilized amplifier system

The object of this invention are bistable, monostable and astable multivibrator in which the switching transition level is stable and relatively independent of ambient temperature. This reduction is accomplished by using an auto-zero amplifier system with an input offset voltage of substantially zero volts.

Persistent nodes for rfid

The invention discloses persistent nodes for RFID. An RFID transponder in one embodiment comprises a radio frequency (RF) transceiver, processing logic coupled to the RF transceiver, a switch coupled to the processing logic, a tunneling device coupled to the switch and a differential sensing circuit having a first input coupled to the tunneling device and a second input coupled to a predetermined reference voltage. In one embodiment, the tunneling device can discharge to a voltage below the predetermined reference voltage.

CLOCKED COMPARATOR AND METHOD THEREOF

COMPARATOR AND OSCILLATION CIRCUIT

A comparator includes a first constant current source, a first transistor having a drain connected to the first constant current source, a gate connected to a non-inverted input terminal, and a source connected to an inverted input terminal, a second constant current source connected between the inverted input terminal and a second power supply terminal, a second transistor having a source connected to a first power supply terminal, a gate connected to the drain of the first transistor, and a drain connected to an output terminal, and a third constant current source connected between the drain of the second transistor and the second power supply terminal. An oscillation circuit includes comparators in which at least one of the comparators is a comparator described above.

Switching circuit

Double Data Rate Interpolating Analog to Digital Converter

A double data rate comparator includes a double data rate comparator core, the comparator core configured to compare a voltage of an input signal to a reference signal during each of a rising edge and a falling edge in a single clock cycle of a clock input to the comparator core, and a double data rate set-reset flip flop circuit, the set-reset flip flop circuit comprising a set input and a reset input connected to respective outputs of the double data rate comparator core, the set-reset flip flop circuit configured to perform a set-reset operation during the rising edge in the single clock cycle and the falling edge in the single clock cycle.

BUFFER CIRCUIT, CLOCK DIVIDING CIRCUIT INCLUDING THE BUFFER CIRCUIT, AND SEMICONDUCTOR DEVICE INCLUDING THE BUFFER CIRCUIT

A buffer circuit may include: an amplifying circuit configured to change, based on a first input signal and a second input signal, voltage levels of a first output node and a second output node in a range between a first power voltage and a second power voltage; a latch circuit configured to latch the voltage levels of the first output node and the second output node; a first variable load configured to adjust, based on a reset signal, an amount of current provided by a first power voltage terminal at the first power voltage to the first output node; a second variable load configured to adjust, based on the reset signal, an amount of current provided by the first power voltage terminal to the second output node; and a reset circuit configured to drive the first output node to the second power voltage based on the reset signal.

HIGH SPEED VARIABLE FREQUENCY DIVIDER

PURPOSE: To attain high speed variable frequency division by connecting a frequency divider having plural fixed frequency division ratios to a mixer operated by an analog signal. CONSTITUTION: Let an input frequency be (f), an output frequency be (x) and frequency division ratio of a frequency divider 2 be 1/n, then the relation of x=f-x/n in the input/output of a mixer 1, and the frequency shown in equation is obtained as the frequency division output frequency (x) and a fractional number of frequency division is attained. In selecting the value (n), an optional fractional number of frequency division is attained. Thus, different values (n) are assigned to plural frequency dividers 21, 22, the output is switched by a changeover switch 3 to give a feedback to the mixer 1 so as to attain variable frequency division. Since it is not required to adjust the timing of the counter by using a logic circuit, the variable frequency divider operationable at a higher speed is formed. COPYRIGHT: (C ...

Power saving terminated bus

A bus termination method and apparatus, specifically, a terminator circuit, a driver/terminator circuit, and appropriate control logic. The terminator circuit and the driver/terminator circuit provide termination of an interface node to one of a first and a second voltage potential selected according to a previous logic value sampled on the input node at a time determined by a clock signal. The driver/terminator circuit also drives data values on the interface node. The terminator circuit and the driver/terminator circuit can be used in bus agents in a computer system. In one computer system configuration, a driving bus agent drives a signal line which is terminated by a predetermined terminating bus agent. Each bus agent compares its device identification to a bus master identification to determine whether to drive, terminate, or tristate the bus.

APPARATUS AND METHOD FOR SWITCHING MODE OF BUCK CONVERTER

The present technology discloses a mode switching device of a buck converter. According to a specific example of the present invention, a response speed of feedback control for a load current variation can be improved by performing the feedback control based on one of a PFM frequency signal with a variable switching frequency characteristic and an HYS frequency signal with a fixed switching frequency characteristic based on a comparison result of a reference voltage and a charging voltage of a capacitor for the PFM frequency signal (PFM_D) or a sensing signal (VZDC) of a zero current sensing unit detected according to a load current, thereby maximizing the efficiency of the buck converter. COPYRIGHT KIPO 2018 (110) 1. Reference voltage (120) 2. Soft start (210) PFM signal generator (220) HYS signal generator (300) Zero current sensing unit (400) Mode control unit (500) Gate driving unit ...

LATCHED COMPARATOR, CLOCK GENERATION CIRCUIT AND SEMICONDUCTOR APPARATUS RELATING TO THE LATCHED COMPARATOR

A latched comparator includes a first amplification circuit, a second amplification circuit and a latch circuit. The first amplification circuit changes voltage levels of first and second output nodes based on first and second input signals when an operation speed of a semiconductor apparatus is relatively slow. The second amplification circuit changes voltage levels of third and fourth output nodes based on the first and second input signals when the operation speed of the semiconductor apparatus is relatively fast. The latch circuit generates first and second latch signals based on the voltage levels of the first and second output nodes or based on the voltage levels of the third and fourth output nodes according to the operation speed of the semiconductor apparatus. 1. A latched comparator comprising:a first amplification circuit configured to change one between voltage levels of a first output node and a second output node to a first voltage level by amplifying a first input signal and a second input signal based on a frequency detection signal;a second amplification circuit configured to change one between voltage levels of a third output node and a fourth output node to a second voltage level by amplifying the first input signal and the second input signal based on the frequency detection signal, the second voltage level being lower than the first voltage level; anda latch circuit configured to generate a first latch signal and a second latch signal based on the voltage levels of the first output node and the second output node or generate the first latch signal and the second latch signal based on the voltage levels of the third output node and the fourth output node, based on the frequency detection signal.2. The latched comparator of claim 1 , wherein the first amplification circuit includes:a first differential circuit configured to change one between voltage levels of the first output node and the second output node to the first voltage level based on the ...

Set and reset pulse generator circuit

A set and reset pulse generator circuit receives an input signal to generate a set signal and a reset signal pair. The set and reset pulse generator circuit includes a set circuit and a reset circuit. A cross-coupling circuit connects a voltage signal of the reset circuit to an output circuit of the set circuit, and another cross-coupling circuit connects a voltage signal of the set circuit to an output circuit of the reset circuit. The output circuit of the set circuit generates the set signal from the input signal, the voltage signal of the reset circuit, and the voltage signal of the set circuit. The output circuit of the reset circuit generates the reset signal from an inverted input signal, the voltage signal of the reset circuit, and the voltage signal of the set circuit.

Low Latency Comparator with Local Clock Circuit

A low latency comparator circuit with a local clock circuit is disclosed. A comparator circuit configured to compare a first input signal to a second input signal. The comparator circuit includes at least one regenerative latch circuit having a first and second inputs configured to receive the first and second input signals, respectively. The comparator circuit further includes a clock circuit configured to generate and provide a clock signal exclusively to circuitry in the comparator circuit, including the at least one regenerative latch circuit. At least one output latch circuit coupled to the at least one regenerative latch circuit and configured to provide a first output signal indicative of a comparison of the first and second input signals.

Latched comparator, clock generation circuit and semiconductor apparatus relating to the latched comparator

A latched comparator includes a first amplification circuit, a second amplification circuit and a latch circuit. The first amplification circuit changes voltage levels of first and second output nodes based on first and second input signals when an operation speed of a semiconductor apparatus is relatively slow. The second amplification circuit changes voltage levels of third and fourth output nodes based on the first and second input signals when the operation speed of the semiconductor apparatus is relatively fast. The latch circuit generates first and second latch signals based on the voltage levels of the first and second output nodes or based on the voltage levels of the third and fourth output nodes according to the operation speed of the semiconductor apparatus.

Signal receiving device

A signal receiving device includes a first amplifier, a duty cycle adjuster and a common mode feedback circuit. The first amplifier receives an input signal, a reference voltage and a bias voltage. The first amplifier generates a first common current based on the bias voltage and, based on the first common current, generates a first output signal and a second output signal complementary to each other by comparing the input signal and the reference voltage. The duty cycle adjuster charges and discharges a selected capacitor according to the first output signal or the second output signal to generate a sensing voltage, and generates a common reference voltage according to the sensing voltage. The common mode feedback circuit generates the bias voltage by comparing the common reference voltage and the reference voltage.

Current mode logic latch

A current mode logic latch may include a sample stage and a hold stage, the hold stage comprising first and second stage transistors, first and second hold stage current sources, and a hold stage switch. The first hold stage transistor may be coupled at its drain terminal to the drain terminal of a first sample stage transistor. The second hold stage transistor may be coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. The first hold stage current source may be coupled to a source terminal of the first hold stage transistor. The second hold stage current source may be coupled to a source terminal of the second hold stage transistor. The hold stage switch may be coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage ...

Common mode voltage level shifting and locking circuit

A common mode voltage level shifting and locking circuit is provided. The common mode voltage level shifting and locking circuit includes an operational amplifier, a source follower, a first feedback circuit, and a second feedback circuit. The operational amplifier generates a first common mode voltage. The source follower shifts the first common mode voltage to generate a second common mode voltage. The first feedback circuit generates a first control signal according to the second common mode voltage. The operational amplifier adjusts the first common mode voltage according to the first control signal. The second feedback circuit generates a second control signal according to an external reference voltage provided by a next stage circuit. The source follower adjusts the second common mode voltage according to the second control signal such that the next stage circuit reaches a maximum input common mode range.

CRYSTAL OSCILLATOR WITH CONTROLLED DUTY CYCLE

Flip-Flop-Schaltungsanordnung

Flip-Flop-Schaltungsanordnung, umfassend - ein Paar von Eingangsanschlüssen (CP, CN), ausgelegt zum Zuführen eines differentiellen Taktsignals, - ein Paar von Ausgangsanschlüssen (QP, QN), ausgelegt zum Abgreifen eines differentiellen Ausgangssignals, - vier Differenzverstärker (1, 2, 3, 4) mit je zwei Transistoren (5, 6; 7, 8; 9, 10; 11, 12), deren gesteuerte Strecken in je einer Serienschaltung mit einem Widerstand (R1, R2, R3, R4) angeordnet sind, wobei die Serienschaltungen zwischen einem Versorgungspotentialanschluß (VCC) und einem ersten beziehungsweise zweiten gemeinsamen Emitterknoten (E1, E2) angeordnet sind, deren Steueranschlüsse unter Bildung einer D-Flipflop-Struktur miteinander gekoppelt sind und bei denen am Ausgang von zumindest einem Differenzverstärker (3) das Paar von Ausgangsanschlüssen (QP, QN) gebildet ist, - eine erste Stromquelle (Q1), die den ersten gemeinsamen Emitterknoten (E1) mit einem Bezugspotentialanschluß (VEE) verbindet, - eine zweite Stromquelle (Q2), ...

Latch circuit

A latch circuit includes an input circuit, an output circuit, and a switch circuit. The input circuit is configured to receive a clock signal and a data signal. The output circuit couples with the input circuit, couples between a first power node and a second power node, and is configured to generate an output signal according to the clock signal and the data signal. The switch circuit couples with the output circuit, wherein when a voltage level of the data signal is switched, the switch circuit disconnects a conductive path from the first power node to the second power node.

High-sensitivity clocked comparator and method thereof

A clocked comparator includes a first clocked transconductance amplifier configured to receive a first voltage signal and output a first current signal to an internal node in accordance with a clock; a clocked regenerative load configured to enable a second voltage signal at the internal node to self-regenerate in accordance with the clock; a SR (set-reset) latch configured to receive the second voltage signal at the internal node and output a third voltage signal; and a second clocked transconductance amplifier configured to receive the third voltage signal and output a second current signal to the internal node.

Clock generation circuit and latch using same, and computing device

A clock generation circuit, a latch using same, and a computing device are provided. The clock generation circuit includes an input end, configured to input a pulse signal; a first output end, configured to output a first clock signal; a second output end, configured to output a second clock signal; and an input drive circuit, a latch circuit, an edge shaping circuit, a feedback delay circuit, and an output drive circuit, where the input drive circuit, the latch circuit, the edge shaping circuit, the feedback delay circuit, and the output drive circuit are sequentially connected between the input end and the first output end as well as the second output end in series. A clock pulse can be effectively shaped, the use of a clock buffer can be reduced, and the correctness and accuracy of data transmission and latching can be improved.

KRISTALLOSZILLATOR MIT GESTEUERTEM TASTVERHÄLTNIS

Persistent nodes for RFID

An RFID transponder in one embodiment comprises a radio frequency (RF) transceiver, processing logic coupled to the RF transceiver, a switch coupled to the processing logic, a tunneling device coupled to the switch and a differential sensing circuit having a first input coupled to the tunneling device and a second input coupled to a predetermined reference voltage. In one embodiment, the tunneling device can discharge to a voltage below the predetermined reference voltage.

Flip-flop circuit that includes differential amplifiers

A flip-flop circuit includes a first differential amplifier with first emitter-coupled transistors having emitters connected to a first emitter node, where the first emitter-coupled transistors include collector terminals that form at last parts of a first circuit node and a second circuit node, and base terminals that are cross-connected to collector terminals of the first emitter-coupled transistors. A second differential amplifier includes second emitter-coupled transistors having emitters connected to a second emitter node, where the second emitter-coupled transistors include collector terminals that are connected to the first circuit node and/or to the second circuit node, and base terminals that form at least part of a third circuit node and a fourth circuit node. A third differential amplifier includes third emitter-coupled transistors having emitters connected to the second emitter node, where the third emitter-coupled transistors include collector terminals that are connected to ...

SIGNAL RECEIVING CIRCUIT, SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SIGNAL RECEIVING CIRCUIT AND SEMICONDUCTOR APPARATUS

A signal receiving circuit includes a summing circuit, a clocked latch circuit and a feedback circuit. The summing circuit generates a summing signal based on an input signal and a feedback signal. The clocked latch circuit generates a sampling signal by sampling the summing signal in synchronization with a clock signal. The feedback circuit generates the feedback signal by selecting one among a plurality of coefficients based on the sampling signal. 1. A signal receiving circuit comprising:a summing circuit configured to generate a summing signal based on an input signal and a feedback signal;a clocked latch circuit configured to generate a sampling signal by sampling the summing signal in synchronization with a clock signal; anda feedback circuit configured to select one between a first coefficient and a second coefficient having a different value from the first coefficient based on a logic level of the sampling signal that is generated on a basis of a previously received input signal and configured to generate the feedback signal based on a selected coefficient and the sampling signal.2. The signal receiving circuit of claim 1 , wherein the summing circuit is configured to generate the summing signal based on the input signal and a reference voltage and configured to change a voltage level of the summing signal based on the feedback signal.3. The signal receiving circuit of claim 2 ,further comprising a reference voltage generation circuit configured to generate the reference voltage,wherein a voltage level of the reference voltage is determined on a basis of at least one among the first coefficient, the second coefficient, and a swing range of the summing signal.4. The signal receiving circuit of claim 1 , wherein the summing circuit is configured to generate the summing signal and a complementary of the summing signal based on the input signal and a complementary signal of the input signal and configured to change a voltage level of the summing signal and the ...

DESIGNING SINGLE EVENT UPSET LATCHES

One example of the present disclosure is an integrated circuit (IC). The IC includes an inverter with an input and an output, a clock transmission gate coupled to the output of the inverter; and a plurality of storage cells. The clock transmission gate is coupled to each of the plurality of storage cells, wherein each of the plurality of storage cells comprises a plurality of nodes arranged based on a minimum spacing.

Low-power relaxation oscillator

L'invention concerne un oscillateur de relaxation basse puissance comprenant un premier module (21) comportant un générateur de rampe formée par une source de courant de référence (31) et une capacité de stockage (32) définissant une tension de rampe (Vramp1), et un comparateur de tension (m1, m2) pour comparer la tension de rampe à une tension de référence, un deuxième module (22, 41, 42, Vramp2, m3, m4) semblable au premier module et une bascule asynchrone (23) recevant, à une première entrée (s), le signal de sortie du comparateur du premier module et, à une deuxième entrée (r), le signal de sortie du comparateur du deuxième module, caractérisé en ce que, pour chaque module, un générateur de ladite tension de référence est réalisé par adjonction d'une résistance de référence (33, 43) entre la source de courant de référence et la capacité de stockage du générateur de rampe.

Persistent nodes for RFID

An RFID transponder in one embodiment comprises a radio frequency (RF) transceiver, processing logic coupled to the RF transceiver, a switch coupled to the processing logic, a tunneling device coupled to the switch and a differential sensing circuit having a first input coupled to the tunneling device and a second input coupled to a predetermined reference voltage. In one embodiment, the tunneling device can discharge to a voltage below the predetermined reference voltage.

PULSE GENERATOR USING LATCH AND CONTROL SIGNAL GENERATOR HAVING THE SAME

An exemplary embodiment of the present invention provides a pulse generator generating a control signal to control a latch unit included in a source driver for sequentially latching input data applied to a source data line of a display device, wherein the pulse generator includes a latch circuit latching an input signal in response to an N-divided clock signal and applying the latched input signal as an output signal, and a logic unit generating a pulse signal by logically multiplying the input signal by the N-divided clock signal, wherein the output signal is provided as an input signal to the latch circuit of another pulse generator, and the pulse signal is provided to the latch unit as the control signal.

LATCH AND ISOLATION CIRCUIT

A latch and an isolation circuit are provided. The latch includes a first-level substructure and at least one second-level substructure, the number of the at least one second-level substructure is k, and k is a positive integer greater than or equal to 1. The first-level substructure includes a first load having a first terminal coupled with a first port, a second load having a first terminal coupled with the first port, a first driving circuit having a control terminal coupled with a second terminal of the first load and a second terminal coupled with a second port, a second driving circuit having a control terminal coupled with a second terminal of the second load and a second terminal coupled with the second port. Each of the at least one second-level substructure includes a third load, a fourth load, a third driving circuit and a fourth driving circuit.

Multi-level drive data transmission circuit and method

The disclosed multi-level driving data transmission circuit and operating method include: a first driving module including a first signal generating unit and a first three-state driver, and a second driving module, including a second three-state driver. The first input terminal of the second three-state driver is coupled to the output terminal of the first three-state driver. The first signal generating unit includes a first and second input terminals, and an output terminal. The output terminal of the first signal generating unit couples to the second input terminal of the first three-state driver. The first signal generating unit receives the first signal through its first input terminal and the first feedback signal of the first signal from the second driving module through its second input terminal. The resultant first control signal has an effective signal width wider than the first signal. The first control signal inputs to the first three-state driver.

FLIP-FLOP-SCHALTUNGSANORDNUNG

Safety mechanism for digital reset state

A system is provided, comprising: a plurality of flip-flops that are configured to receive a reset signal, each of the plurality of flip-flops having a respective output port, and each of the plurality of flip-flops being configured to assume a respective default state when the reset signal is set to a predetermined value; and a reset monitor circuit that is coupled to the respective output port of each of the plurality of flip-flops, the reset monitor circuit being configured to generate a status signal indicating whether each of the flip-flops has assumed the flip-flop's respective default state after the reset signal is set to the predetermined value, wherein assuming a respective default state by each of the plurality of flip-flops results in a predetermined bit string being stored in the plurality of flip-flops.

Flip-flop circuit assembly

A flip-flop circuit arrangement having a total of four differential amplifiers ( 1, 2, 3, 4 ), which are connected to one another to produce a D flip-flop, is specified. According to the suggested principle, the two shared emitter nodes (E 1, E 2 ) of the differential amplifiers ( 1, 2, 3, 4 ) are connected via a switch pair (S 1, S 2 ) to supply potential and are activated by a differential input clock signal at a control input (CN, CP). The present flip-flop circuit is operable using especially low supply voltage (VCC) and is preferably suitable for constructing frequency dividers or shift registers.

CURRENT MODE LOGIC LATCH

A current mode logic latch may include a sample stage and a hold stage, the hold stage comprising first and second stage transistors, first and second hold stage current sources, and a hold stage switch. The first hold stage transistor may be coupled at its drain terminal to the drain terminal of a first sample stage transistor. The second hold stage transistor may be coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. The first hold stage current source may be coupled to a source terminal of the first hold stage transistor. The second hold stage current source may be coupled to a source terminal of the second hold stage transistor. The hold stage switch may be coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage ...

Relaxation oscillator

A relaxation oscillator shares charging current and comparator biasing current between just two current sources, thereby relaxing requirements on total supply current. The resulting reduction in power consumption has no adverse effect on the speed and accuracy of the oscillator. A switching arrangement directs charging and biasing currents between the two current sources and two charging capacitors and their associated comparators.

COMMON MODE VOLTAGE LEVEL SHIFTING AND LOCKING CIRCUIT

A common mode voltage level shifting and locking circuit is provided. The common mode voltage level shifting and locking circuit includes an operational amplifier, a source follower, a first feedback circuit, and a second feedback circuit. The operational amplifier generates a first common mode voltage. The source follower shifts the first common mode voltage to generate a second common mode voltage. The first feedback circuit generates a first control signal according to the second common mode voltage. The operational amplifier adjusts the first common mode voltage according to the first control signal. The second feedback circuit generates a second control signal according to an external reference voltage provided by a next stage circuit. The source follower adjusts the second common mode voltage according to the second control signal such that the next stage circuit reaches a maximum input common mode range. 1. A common mode voltage level shifting and locking circuit , comprising:an operational amplifier, configured to generate a first common mode voltage affected by a feedback;a source follower, coupled to the operational amplifier, and configured to shift a voltage level of the first common mode voltage to generate a second common mode voltage;a first feedback circuit, coupled to the source follower, and configured to generate a first control signal according to a voltage level of the second common mode voltage, wherein the operational amplifier adjusts the voltage level of the first common mode voltage according to the first control signal; anda second feedback circuit, coupled to the source follower, and configured to generate a second control signal according to an external reference voltage provided by a next stage circuit,wherein the source follower adjusts the voltage level of the second common mode voltage according to the second control signal such that the next stage circuit reaches a maximum input common mode range.2. The common mode voltage level ...

KRISTALLOSZILLATOR MIT GESTEUERTEM TASTVERHÄLTNIS

Latch resisting against two-bit node flipping

Frequency dividing apparatus for high frequency

A frequency dividing apparatus having an input signal terminal and a divided signal terminal, whereby a high frequency input to the input signal terminal is divided by a mixer having a first input terminal connected to the input signal terminal having a second input terminal, and having an output terminal connected to the divided signal terminal. A frequency divider is provided having a fixed frequency dividing ratio. The frequency divider has an input terminal connected to the divided signal terminal and an output terminal connected to the second input terminal of the mixer.

Latch mit bipolaren Differenzverstärkern für hohe Geschwindigkeit

... 1. Latch mit bipolarem Differenzverstärker für hohe Geschwindigkeit 2.1. Die Steigerung der Taktraten schneller Latches mit bipolarem Differenzverstärker (und daraus aufgebauter D-Flipflops) geschieht bisher vor allem durch Verbesserungen der Wirkung der Verstärkung der enthaltenen Differenzverstärker in ihrem stromführenden Zustand. Weiter wird die maximale Taktrate aber begrenzt durch die Zeitdauer, die nach einer Umschaltung des Takteingangs zum Abbau der im stromlosen Zustand entstandenen Potentialbarriere über dem Basis-Emitter-pn-Übergang der nunmehr stromführenden Transistoren nötig ist, d. h. der Zeit zur Aktivierung des jeweiligen Differenzverstärkers. Die Erfindung soll diese Zeitdauer reduzieren und damit die Taktrate weiter steigern, wobei die hierzu bekannten Ansätze weiter möglich sein sollen. 2.2. Die vorhandenen Differenzverstärker (212, 213 und 232, 233) werden jeweils mit einer zusätzlichen Stromquelle (226 und 224) versehen, die verhindert, dass diese in den jeweiligen ...

High speed sampling receiver with reduced output impedance

A sampling receiver includes: at least one slave latch circuit; and at least one master latch circuit which further includes: at least one differential input transistor pair, and at least one bistable circuit. Output terminals of the at least one differential input transistor pair and output terminals of the at least one bistable circuit are coupled to the at least one slave latch circuit but in parallel to each other with reference to the at least one slave latch circuit for the purpose of reducing an output impedance to allow the sampling receiver to exhibit a high speed latch operation.

EINEN DIFFERENTIELLEN KASKODE-SCHALTER VERWENDENDER GEPULSTER FLIP-FLOP DES D-TYPS

Verriegelungsschaltung und D-Flipflop

Dynamic comparator

A dynamic comparator includes two sets of input transistors of opposite conductivity types, where a control electrode of one transistor of each set is coupled to a first input of the comparator and a control input of a second transistor of each set is coupled to a second input of the comparator. The comparator includes bypass transistors for pulling current electrodes of either the first set or second set of input transistors to a power supply terminal depending which input voltage is higher as determined by the output.

Comparator and oscillation circuit

A comparator includes a first constant current source, a first transistor having a drain connected to the first constant current source, a gate connected to a non-inverted input terminal, and a source connected to an inverted input terminal, a second constant current source connected between the inverted input terminal and a second power supply terminal, a second transistor having a source connected to a first power supply terminal, a gate connected to the drain of the first transistor, and a drain connected to an output terminal, and a third constant current source connected between the drain of the second transistor and the second power supply terminal. An oscillation circuit includes comparators in which at least one of the comparators is a comparator described above.

Level voltage generation circuit, data driver, and display apparatus

The display apparatus includes: N differential amplifiers having output ends, amplifying N input voltages and outputting amplified voltages, and a resistor ladder having N voltage supply points connected to the output ends of the N differential amplifiers and M voltage output points outputting M level voltages. The M voltage output points are connected to capacitive loads on input sides of the amplifiers, and at least one N differential amplifier has an input pair and an output end connected to one of the N voltage supply point. One of the N input voltages is received by one of the input pair, the other one of the input pair is connected to one of the M voltage output points outputting a level voltage closest to a voltage at the one voltage supply point. The one voltage supply point and the one voltage output point are at different positions on the resistor ladder.

Flip-Flop-Schaltungsanordnung

Es ist eine Flip-Flop-Schaltungsanordnung mit insgesamt vier miteinander zur Bildung eines D-Flip-Flops verschalteten Differenzverstärkern (1, 2, 3, 4) angegeben. Gemäß dem vorgeschlagenen Prinzip sind die beiden gemeinsamen Emitterknoten (E1, E2) der Differenzverstärker (1, 2, 3, 4) über ein Schalterpaar (S1, S2) gegen Versorgungspotential geschaltet und werden von einem differentiellen Eingangstaktsignal an einem Steuereingang (CN, CP) angesteuert. Die vorliegende Flip-Flop-Schaltung ist mit besonders geringer Versorgungsspannung (VCC) betreibbar und bevorzugt zum Aufbau von Frequenzteilern oder Schieberegistern geeignet.

Flipflop-Impulsgeberschaltung

Flipflop-Impulsgeberschaltung, umfassend: eine Setzschaltung, die dazu ausgelegt ist, ein Eingangssignal zu empfangen, unter Verwendung des Eingangssignals eine Spannung an einem Knoten der Setzschaltung zu erzeugen und einen Setzimpuls gemäß dem Eingangssignal, der Spannung an dem Knoten der Setzschaltung und einer Spannung an einem Knoten einer Rücksetzschaltung zu erzeugen; eine Rücksetzschaltung, die dazu ausgelegt ist, das Eingangssignal zu empfangen, unter Verwendung des Eingangssignals die Spannung an dem Knoten der Rücksetzschaltung zu erzeugen und einen Rücksetzimpuls gemäß dem Eingangssignal, der Spannung an dem Knoten der Setzschaltung und der Spannung an dem Knoten der Rücksetzschaltung zu erzeugen; eine erste Kreuzkopplungsschaltung, die dazu ausgelegt ist, die Spannung an dem Knoten der Setzschaltung mit der Rücksetzschaltung zu koppeln; und eine zweite Kreuzkopplungsschaltung, die dazu ausgelegt ist, die Spannung an dem Knoten der Rücksetzschaltung mit der Setzschaltung zu ...

Square wave-to-sine wave converter

A circuit includes a bandpass filter and a self-tracking circuit. The bandpass filter has a first input node configured to receive an input square wave signal and an output node configured to provide an output sine wave signal. The bandpass filter includes a first binary-weighted programmable resistor array. The self-tracking circuit includes a second input node coupled to the output node. The self-tracking circuit includes a counter, and the counter includes an output node coupled to the first binary weighted programmable resistor array.

Frequency dividing apparatus for high frequency

Pulse generator using latch and control signal generator having the same

An exemplary embodiment of the present invention provides a pulse generator generating a control signal to control a latch unit included in a source driver for sequentially latching input data applied to a source data line of a display device, wherein the pulse generator includes a latch circuit latching an input signal in response to an N-divided clock signal and applying the latched input signal as an output signal, and a logic unit generating a pulse signal by logically multiplying the input signal by the N-divided clock signal, wherein the output signal is provided as an input signal to the latch circuit of another pulse generator, and the pulse signal is provided to the latch unit as the control signal.

LATCH CIRCUIT

A latch circuit includes a switch circuit, an input circuit, and an output circuit. The switch circuit is coupled between a first power node and a second power node, and includes a non-inverting output node and an inverting output node. The input circuit couples with the non-inverting output node and the inverting output node, and conducts the non-inverting output node with the second power node according to a clock signal and a data signal. The output circuit couples with the non-inverting output node, the inverting output node, the first power node, and the second power node. The output circuit conducts the non-inverting output node with the first power node according to the clock signal and the data signal. When the data signal is switched, the switch circuit sets a conductive path from the first power node to the second power node as an open circuit.

LEVEL SHIFT DEVICE AND IC DEVICE

A level shift device includes a high breakdown voltage element in which a voltage of an internal power supply part is applied to a gate, an external input signal is input from outside to one of a source and a drain, and the other one of the source and the drain outputs an intermediate output signal of the same phase as that of the external input signal, and a comparator comparing the intermediate output signal with a threshold value so as to perform conversion into a Hi/Lo signal defined by a voltage of the internal power supply part and outputting the signal to an internal processing circuit. The high breakdown voltage element, the comparator, the processing circuit, and the internal power supply part are enclosed in the device. 1. A level shift device , comprising:a high breakdown voltage element in which a voltage of an internal power supply part is applied to a gate, an external input signal is input from outside to one of a source and a drain, and the other one of the source and the drain outputs an intermediate output signal of the same phase as that of the external input signal; anda comparator comparing the intermediate output signal with a threshold value so as to perform conversion into a Hi/Lo signal defined by a voltage of the internal power supply part and outputting the signal to an internal processing circuit,wherein the high breakdown voltage element, the comparator, the processing circuit, and the internal power supply part are enclosed in the device.2. The level shift device according to claim 1 , wherein the high breakdown voltage element comprises a Double-Diffused MOS (DMOS) element.3. The level shift device according to claim 1 , wherein the high breakdown voltage element is configured to be in a saturation range claim 1 , in which a drain current flowing between the drain and the source is saturated claim 1 , when a voltage of the internal power supply part is applied to the gate and the external input signal is a Hi level signal.4. The level ...

Signal input circuit

CLOCK GENERATION CIRCUIT AND LATCH USING SAME, AND COMPUTING DEVICE

A clock generation circuit, a latch using same, and a computing device are provided. The clock generation circuit includes an input end, configured to input a pulse signal; a first output end, configured to output a first clock signal; a second output end, configured to output a second clock signal; and an input drive circuit, a latch circuit, an edge shaping circuit, a feedback delay circuit, and an output drive circuit, where the input drive circuit, the latch circuit, the edge shaping circuit, the feedback delay circuit, and the output drive circuit are sequentially connected between the input end and the first output end as well as the second output end in series. A clock pulse can be effectively shaped, the use of a clock buffer can be reduced, and the correctness and accuracy of data transmission and latching can be improved.

Clocked comparator and method thereof

NON-OSCILLATING COMPARATOR

A comparison circuit includes an input interface configured to receive input signals and an output interface configured to deliver an output signal. A comparator is coupled between the input interface and the output interface. An amplifier is coupled between the input interface and the comparator. A neutralization circuit is configured to neutralize any change of state of the output signal starting from each moment in time at which the change of state of the output signal occurs and lasting for a second duration of propagation that compensates for a duration of propagation of signals within the amplifier.

Method and arrangement for protecting a digital circuit against time errors

Digital values obtained from an output of a preceding circuit element are temporarily stored and made available for a subsequent circuit element at a controlled moment of time. A digital value is received for temporary storage, as well as a triggering signal, a triggering edge of which defines an allowable time limit before which a digital value must appear at said data input to become available for said subsequent circuit element. A sequence of first and second pulse-enabled subregister stages is used to temporarily store said digital value. Said triggering signal is provided to said first pulse-enabled subregister stage delayed with respect to the triggering signal received by said second pulse-enabled subregister stage. The length of the delay is a fraction of a cycle of the triggering signal. A timing event observation signal is output as an indicator of said digital value at said data input having changed within a time window that begins at said allowable time limit and is shorter ...

Signal inputting circuit

The present invention provides a signal processing unit with a small chip area and a stable circuit characteristics. The signal input circuit of the present invention has a bias circuit. The bias circuit is configured with components identical to those for a CMOS inverter to constitute an input circuit. Thus, even when the signal input circuit is affected by a manufacturing provided or external factors or the like, a DC voltage V1 that is outputted from the bias circuit and on which an AC input signal Vin is superimposed and threshold voltages VIH, VIL of the input circuit have similar variations, thus a stable circuit characteristic is obtained. Furthermore, NMOS transistors 17, 28 are subject to ON/OFF control properly by 1st and 2nd control signals to stop a through-current of the bias circuit and the input circuit thereby reducing the current consumption. Even when operation of the input circuit is stopped, the output from the input circuit is latched by a latch circuit 18 to prevent ...

Pulsed D-Flip-Flop using differential cascode switch

A differential cascode structure is configured to propagate a data state to a static latch at each active edge of a clock. A clock generator enables the communication of the data state and its inverse to the latch for a predetermined time interval. In a first embodiment, each cascode structure includes three gates in series, the gates being controlled by the clock signal, a delayed inversion of the clock signal, and the data state or its inverse. In an alternative embodiment, each cascode structure includes two gates in series, the gates being controlled by the clock signal and the delayed inversion of the clock signal. In this alternative embodiment, each of these cascode structures is driven directly by the data signal or its inverse. The static latch obviates the need to precharge nodes within the device, thereby minimizing the power consumed by the device. The latch preferably comprises cross-coupled inverters, which, being driven by the differential cascode structure, enhance the switching ...

Semiconductor integrated circuit and semiconductor storage device

A semiconductor integrated circuit of an embodiment includes: a delay element array circuit in which a plurality of delay elements having a delay amount Tw are connected in series; a flip-flop group including a plurality of flip-flops each of which an input is connected to an output of a corresponding delay element; a delay element group configured to generate, from an input clock signal, a plurality of output clock signals each having a delay difference of a second delay amount smaller than the delay amount Tw; and a delay unit configured to set a third delay amount smaller than the second delay amount, and the delay element group and the delay unit are connected in series between an output terminal of an input signal CLK_DET and an input terminal of the flip-flop group.

Verriegelungsschaltung und D-Flipflop

Current mode logic latch

A current mode logic latch may include a sample stage and a hold stage, the hold stage comprising first and second stage transistors, first and second hold stage current sources, and a hold stage switch. The first hold stage transistor may be coupled at its drain terminal to the drain terminal of a first sample stage transistor. The second hold stage transistor may be coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. The first hold stage current source may be coupled to a source terminal of the first hold stage transistor. The second hold stage current source may be coupled to a source terminal of the second hold stage transistor. The hold stage switch may be coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage ...

COMPARATOR AND A/D CONVERTER

A comparator includes: a differential amplifier of which operational state is switched in response to a clock-signal, and which outputs a first intermediate-output corresponding to a first input-signal and a second intermediate-output corresponding to a second input-signal; a differential latch circuit of which operational state is switched in response to the clock-signal, and a state of which is changed depending on the first intermediate-output and the second intermediate-output; a first adjuster configured to adjust a threshold of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output; and a second adjuster configured to adjust a threshold variation of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output. 1. A comparator , comprising:a differential amplifier of which operational state is switched in response to a clock signal, and which outputs a first intermediate output corresponding to a first input signal and a second intermediate output corresponding to a second input signal;a differential latch circuit of which operational state is switched in response to the clock signal, and a state of which is changed depending on the first intermediate output and the second intermediate output;a first adjuster configured to adjust a threshold of the differential latch circuit with respect to a change of a state of the first intermediate output and a change of a state of the second intermediate output; anda second adjuster configured to adjust a threshold variation of the differential latch circuit with respect to a change of a state of the first intermediate output and a change of a state of the second intermediate output.2. The comparator according to claim 1 , wherein: a latch circuit which includes a first line including a first PMOS transistor and a first NMOS ...

Clocked register

A J-K flip/flop type storage register includes an input register and an output register. The input register is active when a clock pulse applied thereto is below a predetermined level defining a logic 0 state and inactive when the clock pulse signal is above the first predetermined level. The output register is active when the level of the clock pulse signal is above a second predetermined level and inactive when the clock pulse signal is below the second predetermined level. There exists a well-defined voltage range during which both the input and output registers are inactive. The transfer of information from the input register to the output register only occurs during the transition from a logic 0 level to a logic 1 level clock pulse signal. The SET and RESET inputs are only enabled when the clock pulse signal is at a logic 0 level. This register management helps to ensure that noise on the clock pulse line does not erroneously trigger the input or output registers and further helps ...

CURRENT MODE LOGIC LATCH

A current mode logic latch may include a sample stage and a hold stage, the hold stage comprising first and second stage transistors, first and second hold stage current sources, and a hold stage switch. The first hold stage transistor may be coupled at its drain terminal to the drain terminal of a first sample stage transistor. 1. A latch , comprising:a sample stage having a differential input and a differential output; anda hold stage coupled to the differential output of sample stage and configured to provide an effective resistance at the differential output that is positive during a first phase of the latch and negative during a second phase of the latch.2. The latch of claim 1 , wherein the hold stage comprises:a hold circuit configured to have a transconductance that is larger during the second phase than during the first phase; anda current source configured to bias the hold circuit during the first phase and during the second phase.3. The latch of claim 1 , wherein the sample stage comprises:a sample circuit configured to have a consistent transconductance across the first phase and the second phase; anda sample-stage current source configured to bias the sample circuit during the first phase and during the second phase.4. A latch claim 1 , comprising:a sample stage having a differential input and a differential output; and a first current source and a second current source;', 'a hold-stage resistor coupled between the first current source and the second current source;', 'a hold-stage switch coupled between the first current source and the second current source, the hold-stage switch configured to be open during the first phase and to be closed during the second phase; and', 'a cross-coupled pair of transistors coupled to the differential output of the sample stage and configured to be biased by the first current source and the second current source during the first phase and during the second phase., 'a hold stage configured to alternate between a first ...

High speed input receiver/latch

A high-speed receiver/latch is implemented by incorporating a differential amplifier/comparator directly into the feedback loop of a latch function. Both transparent and edge-triggered variants are possible. The resulting circuit is capable of extremely high-speed operation by virtue of very small setup time and small propagation delay.

Flip-flop with improved operating speed

A flip-flop with an improved operating speed is disclosed. The flip-flop includes a switch unit, a latch unit and a reset controller. The switch unit transfers data to a first node in response to a clock signal. The latch unit latches the data apparent at the first node at a second node and outputs the data through an output node in response to the clock signal. The reset controller resets the output node in response to a reset control signal. The reset controller is connected between the second node and a first voltage and includes a transistor having a gate receiving the inverted form of the reset control signal.

Persistent nodes for RFID

An RFID transponder in one embodiment comprises a radio frequency (RF) transceiver, processing logic coupled to the RF transceiver, a switch coupled to the processing logic, a tunneling device coupled to the switch and a differential sensing circuit having a first input coupled to the tunneling device and a second input coupled to a predetermined reference voltage. In one embodiment, the tunneling device can discharge to a voltage below the predetermined reference voltage.

Refresh circuit and refresh method of a semiconductor memory having a signal generation module configured to generate an inversion signal and carry signals based on a refresh command; an adjustment unit to generate an inversion adjustment signal according to the inversion

A refresh circuit includes: a signal generation module, configured to generate an inversion signal and a carry signal based on a refresh command; an adjustment unit, configured to generate, if a first refresh signal and a second refresh signal are generated based on the refresh command, an inversion adjustment signal according to the inversion signal, and generate, if only the first refresh signal is generated based on the refresh command, the inversion adjustment signal according to an inversion signal corresponding to a first refresh signal generated based on a current refresh command, and generate the inversion adjustment signal only according to an inversion signal corresponding to a second refresh signal generated based on a next refresh command; and a counting module, configured to generate a first output signal and a second output signal, and invert the first output signal based on the inversion adjustment signal.

Clocked comparator and method thereof

A clocked comparator and method thereof are provided. The clocked comparator includes a first clocked transconductance amplifier, a clocked regenerative load, a SR latch, and a second clocked transconductance amplifier. The first clocked transconductance amplifier configured to receive a first voltage signal and output a first current signal to an internal node in accordance with a clock. The clocked regenerative load configured to enable a second voltage signal at the internal node to self-regenerate in accordance with the clock. The SR latch configured to receive the second voltage signal at the internal node and output a third voltage signal. The second clocked transconductance amplifier configured to receive the third voltage signal and output a second current signal to the internal node.

Tunable timer for memory arrays

The present invention is directed to a tunable delay element incorporating one-half of a bipolar SRAM cell and a reference generator. In operation, the rising edge and incoming clock pulse sets the receiver/latch, latching the internal clock (i.e., the write pulse). The same rising edge of the clock pulse also functions to initiate the switching of the half memory cell in the tunable delay. When the half memory cell is switched halfway to its second state (relative to the referenced generator) the latch is disabled and the ICL write pulse goes low. The ICL write pulse is thus self-timed to be operational in the actual memory cell. Some delay circuitry is also provided for controlling the switching speed of the half memory cell in the tunable delay in order to selectively adjust the ICL pulse width.

High-speed digital logic circuit for SAR_ADC and sampling adjustment method

The present disclosure belongs to the technical field of analog or digital-analog hybrid integrated circuits, and relates to a high-speed SAR_ADC digital logic circuit, in particular to a high-speed digital logic circuit for SAR_ADC and a sampling adjustment method. The digital logic circuit includes a comparator, a logic control unit parallel to the comparator, and a capacitor array DAC. The comparator and the logic control unit are simultaneously triggered by a clock signal. The comparator outputs a valid comparison result Dp/Dn, the logic control unit outputs a corresponding rising edge signal, the rising edge signal is slightly later than Dp/Dn output by the comparator through setting a delay match, Dp/Dn is captured by the corresponding rising edge signal, thereby settling a capacitor array. The present disclosure eliminates the disadvantage of the improper settling of the capacitor array of the traditional parallel digital logic.

Comparator and oscillation circuit

A comparator includes a first constant current source, a first transistor having a drain connected to the first constant current source, a gate connected to a non-inverted input terminal, and a source connected to an inverted input terminal, a second constant current source connected between the inverted input terminal and a second power supply terminal, a second transistor having a source connected to a first power supply terminal, a gate connected to the drain of the first transistor, and a drain connected to an output terminal, and a third constant current source connected between the drain of the second transistor and the second power supply terminal. An oscillation circuit includes comparators in which at least one of the comparators is a comparator described above.

Set and reset pulse generator circuit

Signal receiving circuit, semiconductor apparatus and semiconductor system including the signal receiving circuit and semiconductor apparatus

A signal receiving circuit includes a summing circuit, a clocked latch circuit and a feedback circuit. The summing circuit generates a summing signal based on an input signal and a feedback signal. The clocked latch circuit generates a sampling signal by sampling the summing signal in synchronization with a clock signal. The feedback circuit generates the feedback signal by selecting one among a plurality of coefficients based on the sampling signal.

Logic configuration techniques

Various implementations described herein are directed to a device having logic circuitry with multiple inversion stages. One or more of the multiple inversion stages may be configured to operate as first inversion logic with a first number of transistors. One or more of the multiple inversion stages may be configured to operate as second inversion logic with a second number of transistors that is greater than the first number of transistors.

Method and apparatus for symmetric aging of clock trees

In certain aspects, an apparatus includes a gating circuit having an enable input, a signal input, and an output, wherein the enable input is configured to receive an enable signal. The apparatus also includes a toggle circuit having an output, wherein the toggle circuit is configured to toggle a logic state at the output of the toggle circuit based on the enable signal. The apparatus further includes a multiplexer having a first input, a second input, and an output, wherein the first input of the multiplexer is coupled to the output of the gating circuit, the second input of the multiplexer is coupled to the output of the toggle circuit. The multiplexer is configured to select one of the first input and the second input based on the enable signal, and couple the selected one of the first input and the second input to the output of the multiplexer.

HIGH-SPEED DIGITAL LOGIC CIRCUIT FOR SAR_ADC AND SAMPLING ADJUSTMENT METHOD

The present disclosure belongs to the technical field of analog or digital-analog hybrid integrated circuits, and relates to a high-speed SAR_ADC digital logic circuit, in particular to a high-speed digital logic circuit for SAR_ADC and a sampling adjustment method. The digital logic circuit includes a comparator, a logic control unit parallel to the comparator, and a capacitor array DAC. The comparator and the logic control unit are simultaneously triggered by a clock signal. The comparator outputs a valid comparison result Dp/Dn, the logic control unit outputs a corresponding rising edge signal, the rising edge signal is slightly later than Dp/Dn output by the comparator through setting a delay match, Dp/Dn is captured by the corresponding rising edge signal, thereby settling a capacitor array. The present disclosure eliminates the disadvantage of the improper settling of the capacitor array of the traditional parallel digital logic.

Clocked comparator and method thereof

A clocked comparator and method thereof are provided. The clocked comparator includes an upper-side sampling latch, a lower-side sampling latch, and a decision-arbitrating latch. The upper-side sampling is latch configured to output a first decision in accordance with a detection of a sign of an input voltage signal plus an offset voltage at an edge of a clock signal. The lower-side sampling latch is configured to output a second decision in accordance with a detection of a sign of the input voltage signal minus the offset voltage at the edge of the clock signal. The decision-arbitrating latch is configured to receive the first decision and the second decision and output a final decision in accordance with whichever one of the first decision and the second decision that is resolved earlier.

METHOD AND ARRANGEMENT FOR PROTECTING A DIGITAL CIRCUIT AGAINST TIME ERRORS

Digital values obtained from an output of a preceding circuit element are temporarily stored and made available for a subsequent circuit element at a controlled moment of time. A digital value is received for temporary storage, as well as a triggering signal, a triggering edge of which defines an allowable time limit before which a digital value must appear at said data input to become available for said subsequent circuit element. A sequence of first and second pulse-enabled subregister stages is used to temporarily store said digital value. Said triggering signal is provided to said first pulse-enabled subregister stage delayed with respect to the triggering signal received by said second pulse-enabled subregister stage. The length of the delay is a fraction of a cycle of the triggering signal. A timing event observation signal is output as an indicator of said digital value at said data input having changed within a time window that begins at said allowable time limit and is shorter ...

LOW-POWER RELAXATION OSCILLATOR

The low-power relaxation oscillator comprises a first module (21) having a ramp generator formed by a reference current source (31) and a storage capacitor (32) defining a ramp voltage (Vramp1), and a voltage comparator (m1, m2) for comparing the ramp voltage with a reference voltage, a second module (22, 41, 42, Vramp2, m3, m4) similar to the first module and an asynchronous flip-flop (23) receiving the output signal of the comparator of the first module at a first input (s) and the output signal of the comparator of the second module at a second input (r). For each module a generator of said reference voltage is configured by adding a reference resistance (33, 43) between the reference current source and the storage capacitor. Thus, the generation of the reference voltage and the ramp voltage is conducted on the very same current branch. This enables the electrical power consumption of the oscillator to be reduced.

Level shift device and IC device

A level shift device includes a high breakdown voltage element in which a voltage of an internal power supply part is applied to a gate, an external input signal is input from outside to one of a source and a drain, and the other one of the source and the drain outputs an intermediate output signal of the same phase as that of the external input signal, and a comparator comparing the intermediate output signal with a threshold value so as to perform conversion into a Hi/Lo signal defined by a voltage of the internal power supply part and outputting the signal to an internal processing circuit. The high breakdown voltage element, the comparator, the processing circuit, and the internal power supply part are enclosed in the device.

Устройство для формирования выборки мгновенного значения напряжения

Устройство для формирования выборки мгновенного значения напряжения, содержащее: операционный усилитель (ОУ); генератор тактовых импульсов, который через логический инвертор подключен к входу управления второго ключа, а через формирователь импульсов соединен с входом установки в единичное состояние триггера, вход установки в нулевое состояние которого соединен с выходом компаратора; выход триггера соединен со входом управления первого ключа; источник входного напряжения, через первый резистор и первый ключ, соединен с первыми выводами второго ключа и запоминающего конденсатора, отличающееся тем, что в устройство введены второй, третий и четвертый резисторы, буферный повторитель на ОУ, причем первый вывод второго резистора соединен с первыми выводами второго ключа и запоминающего конденсатора, вторым выводом первого ключа и неинвертирующим входом ОУ; второй вывод второго резистора соединен с неинвертирующим входом буферного повторителя на ОУ, выходом ОУ и, через четвертый резистор, с инвертирующим входом ОУ и вторым выводом третьего резистора, первый вывод которого заземлен; инвертирующий вход компаратора соединен с источником входного напряжения и первым выводом первого резистора; неинвертирующий вход компаратора соединен с выходом устройства, выходом буферного повторителя на ОУ и его инвертирующим входом; вторые выводы второго ключа и запоминающего конденсатора заземлены. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 160 870 U1 (51) МПК G11C 27/02 (2006.01) H03K 3/02 (2006.01) H03L 5/00 (2006.01) H03K 9/00 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ТИТУЛЬНЫЙ (21)(22) Заявка: ЛИСТ ОПИСАНИЯ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ 2015152000/08, 03.12.2015 (24) Дата начала отсчета срока действия патента: 03.12.2015 (45) Опубликовано: 10.04.2016 Бюл. № 10 1 6 0 8 7 0 R U (57) Формула полезной модели Устройство для формирования выборки мгновенного значения напряжения, содержащее: операционный усилитель (ОУ); генератор тактовых импульсов, который через логический ...

HYSTERESIS COMPARATOR, SEMICONDUCTOR DEVICE, AND POWER STORAGE DEVICE

To provide a hysteresis comparator having a small circuit area and low power consumption. The hysteresis comparator includes a comparator, a switch, a first capacitor, a second capacitor, and a logic circuit. A first terminal of the switch is electrically connected to one of a pair of conductive regions of the first capacitor, one of a pair of conductive regions of the second capacitor, and a first input terminal of the comparator. An output terminal of the comparator is electrically connected to an input terminal of the logic circuit. An output terminal of the logic circuit is electrically connected to the other of the pair of conductive regions of the second capacitor. The logic circuit has a function of generating an inverted signal of a signal input to the input terminal of the logic circuit and outputting the inverted signal to the output terminal of the logic circuit. A reference potential is input to the first input terminal of the comparator and the reference potential is held by the switch. Due to change in the potential of the output terminal of the comparator, the reference potential is changed by capacitive coupling of the second capacitor. 1. A hysteresis comparator comprising a comparator , a switch , a first capacitor , a second capacitor , and a logic circuit ,wherein a first terminal of the switch is electrically connected to one of a pair of conductive regions of the first capacitor, one of a pair of conductive regions of the second capacitor, and a first input terminal of the comparator,wherein an output terminal of the comparator is electrically connected to an input terminal of the logic circuit,wherein an output terminal of the logic circuit is electrically connected to the other of the pair of conductive regions of the second capacitor, andwherein the logic circuit is configured to generate an inverted signal of a signal input to the input terminal of the logic circuit and output the inverted signal to the output terminal of the logic circuit. ...

Signal Converter Circuit and Method for Evaluating a Sensor Signal of a Safety-Oriented Device

A signal converter circuit includes a sensor connection, two comparator circuits, each having a signal input for an electric connection to the sensor connection, a reference input for an electric connection to a respectively assigned reference signal source and a signal output for a provision of an output signal, with a feedback line being formed between the respective signal output and the respective reference input, and further including two reference signal sources, each of the comparator circuits being configured for comparing a signal level at the signal input to a signal level at the reference input and for outputting a digital output signal as a function of a comparison result between the signal levels, wherein the two reference signal inputs are connected to one another via a coupling line being configured to transmit a presettable fraction of the respective signal level present at one reference input to the other reference input. 1. A signal converter circuit for processing a sensor signal into an output signal , the circuit comprising a sensor connection for receiving a sensor signal , and further comprising two comparator circuits , each having a signal input for an electric connection to the sensor connection , a reference input for an electric connection to a respectively assigned reference signal source and a signal output for a provision of an output signal , with a feedback line being formed between the respective signal output and the respective reference input , and further comprising two reference signal sources , each of which is configured to provide a reference signal to the reference input , each of the comparator circuits being configured to compare a signal level at the signal input to a signal level at the reference input and for outputting a digital output signal as a function of a comparison result between the signal levels , wherein the two reference signal inputs are electrically connected to one another via a coupling line , the ...

PERSISTENT NODES FOR RFID

An RFID transponder in one embodiment comprises a radio frequency (RF) transceiver, processing logic coupled to the RF transceiver, a switch coupled to the processing logic, a tunneling device coupled to the switch and a differential sensing circuit having a first input coupled to the tunneling device and a second input coupled to a predetermined reference voltage. In one embodiment, the tunneling device can discharge to a voltage below the predetermined reference voltage. 1. A state storage circuit for storing a state in an RFID circuit , the state storage circuit comprising:a switch coupled to a first reference voltage;a capacitance circuit coupled to the switch, the capacitance circuit comprising a capacitor that discharges through a tunneling current, wherein the discharging of the capacitance circuit is dominated by the tunneling current when the state storage circuit's temperature is in the range of −25 degrees to +40 degrees C.2. The state storage circuit as in further comprising:a differential sensing circuit coupled to an output of the capacitance circuit and coupled to an output of a reference generator circuit which generates a predetermined reference voltage independently of any tunneling device, the differential sensing circuit configured to sense whether the output of the capacitance circuit is above the predetermined reference voltage and wherein the capacitance circuit discharges from a voltage which is about the first reference voltage to a voltage below the predetermined reference voltage; andwherein the capacitance circuit comprises a thin oxide MOS capacitor with an oxide thickness between 10 nm and 50 nm, wherein the tunneling current is through the thin gate oxide.3. The state storage circuit as in wherein the state storage circuit is configured to store the state for a predetermined period of time which is substantially independent of temperature.4. The state storage circuit as in wherein at least one of the first reference voltage and the ...

CONTROL CIRCUITRY FOR CONTROLLING A POWER SUPPLY

Control circuitry for controlling a current through an inductor of a power converter, the control circuitry comprising: comparison circuitry configured to compare a measurement signal, indicative of a current through the inductor during a charging phase of the power converter, to a signal indicative of a target average current through the inductor for the charging phase and to output a comparison signal based on said comparison; detection circuitry configured to detect, based on the comparison signal, a crossing time indicative of a time at which the current through the inductor during the charging phase is equal to the target average current for the charging phase; and current control circuitry configured to control a current through the inductor during a subsequent charging phase based on the crossing time. 1. Control circuitry for controlling a current through an inductor of a power converter , the control circuitry comprising:comparison circuitry configured to compare a measurement signal, indicative of a current through the inductor during a charging phase of the power converter, to a signal indicative of a target average current through the inductor for the charging phase and to output a comparison signal based on said comparison;detection circuitry configured to detect, based on the comparison signal, a crossing time indicative of a time at which the current through the inductor during the charging phase is equal to the target average current for the charging phase; andcurrent control circuitry configured to control a current through the inductor during a subsequent charging phase based on the crossing time.2. Control circuitry according to claim 1 , further comprising monitoring circuitry configured to monitor a duration of the charging phase.3. Control circuitry according to claim 2 , wherein the monitoring circuitry is configured to monitor the duration of the charging phase based on an on-time of a switch that controls a flow of current through the ...

ADAPTIVE HYSTERETIC CONTROL FOR A POWER CONVERTER

An apparatus includes a first control circuit having an output and including a first comparator and a second control circuit coupled to the output of the first control circuit. The second control circuit includes a second comparator configured to: compare a first value to a reference frequency value, the first value indicating a frequency of a signal at the output of the first control circuit; and provide an adjustment value to change a hysteresis window of the first comparator. 1. An apparatus comprising:a first control circuit having an output and including a first comparator; and compare a first value to a reference frequency value, the first value indicating a frequency of a signal at the output of the first control circuit; and', 'provide an adjustment value to change a hysteresis window of the first comparator., 'a second control circuit coupled to the output of the first control circuit, the second control circuit including a second comparator configured to2. The apparatus of claim 1 , wherein the first control circuit further includes an adjustable resistor coupled to a comparator output of the second comparator.3. The apparatus of claim 2 , wherein the adjustable resistor is a first resistor claim 2 , and the first control circuit further includes:first and second switches, each having respective first and second switch terminals and a respective control terminal, the respective second switch terminals coupled to an input of the first comparator, the respective control terminals coupled to the output of the first control circuit; andsecond and third resistors, the first resistor coupled between the second and third resistors, the first resistor having first and second resistor terminals, the first resistor terminal coupled to the first terminal of the first switch, and the second resistor terminal coupled to the first terminal of the second switch.4. The apparatus of claim 3 , wherein the first control circuit further includes a filter circuit having a ...

STORAGE CIRCUIT WITH HARDWARE READ ACCESS

A method for configuring a storage circuit, including: writing data via an input line into the storage circuit by a software write access; writing a bit-wise inverted form of the data via the input line into the storage circuit by a subsequent software write access; and generating an error signal if a comparison based on the written data and the written bit-wise inverted form of the data indicates a storage circuit configuration error, wherein the storage circuit permits hardware read access and lacks software read access. 2. The method of claim 1 , further comprising:masking the error signal for a clock cycle during the writing of the data.3. The method of claim 1 , further comprising:generating a configuration signal that indicates when the storage circuit is being configured.4. The method of claim 3 , further comprising:controlling a timer to determine a configuration time during which the storage circuit is being configured; andgenerating an alarm signal if the configuration time exceeds a threshold configuration time limit.5. The method of claim 3 , further comprising:controlling a timer to determine a configuration time during which the storage circuit is being configured; andconfiguring the storage circuit to output default data or data written to the storage circuit during a prior configuration of the storage circuit, if the configuration time exceeds a threshold configuration time limit.6. The method of claim 1 , further comprising:reading, via an outline line of the storage circuit, the written data by a hardware read access.7. The method of claim 1 , further comprising:prior to writing the data during the software write access, writing reset data via the input line into the storage circuit by a software reset write access; andallowing the writing of the data if the reset data corresponds with prior data written via the input line into the storage circuit by a software access.8. The method of claim 1 , further comprising:prior to the writing the data ...

HIGH SPEED SYNC FET CONTROL

A circuit arrangement is disclosed for controlling the switching of a field effect transistor (FET). A current controlled amplifier may be configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET. A comparator may be coupled to the current sense amplifier to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off. 1. An apparatus for controlling a field effect transistor (FET) , the apparatus comprising:a current controlled amplifier configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET;a comparator coupled to the current controlled amplifier, the comparator configured to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off; anda hysteresis resistance coupled to an output of the comparator, wherein the hysteresis resistance is configured to effect hysteresis in the output of the comparator.2. The apparatus of claim 1 , wherein the current sense device is a copper trace claim 1 , and wherein the apparatus further comprises:a compensation device configured to compensate for a change in resistance in the copper trace, and wherein the compensation device includes at least one of a negative temperature coefficient (NTC) thermistor and a positive temperature coefficient (PTC) thermistor; andcircuitry configured to selectively enable or disable compensation for the change in the resistance in the copper trace.3. The apparatus of claim 1 , wherein the current sense device is a shunt resistor.4. The apparatus of claim 1 , wherein ...

Method and Apparatus for Measuring Biosignal

Provided is a method and apparatus for measuring a biosignal. The biosignal measurement method may include measuring, at a biosignal measurement apparatus, a biosignal using a biosignal measurement sensor; processing, at the biosignal measurement apparatus, the biosignal and converting the biosignal to a pulse signal using a first voltage distribution time constant circuit and a waveform converter; and counting, at the biosignal measurement apparatus, the pulse signal using a counter and generating first biometric information. The first voltage distribution time constant circuit may filter a signal of a specific frequency band from the biosignal based on voltage distribution using a series resistance included in the first voltage distribution time constant circuit. 1. A method of measuring a biosignal , the method comprising:measuring, at a biosignal measurement apparatus, a biosignal using a biosignal measurement sensor;processing, at the biosignal measurement apparatus, the biosignal and converting the biosignal to a pulse signal using a first voltage distribution time constant circuit and a waveform converter; andcounting, at the biosignal measurement apparatus, the pulse signal using a counter and generating first biometric information,wherein the first voltage distribution time constant circuit filters a signal of a specific frequency band from the biosignal based on voltage distribution using a series resistance included in the first voltage distribution time constant circuit.2. The method of claim 1 , wherein the converting of the biosignal to the pulse signal comprises:generating, at the biosignal measurement apparatus, the biosignal as a first wave signal using the first voltage distribution time constant circuit; andconverting, at the biosignal measurement apparatus, the first wave signal to the pulse signal using the waveform converter,wherein the first voltage distribution time constant circuit comprises a first series resistance and a second series ...

Dynamic Biasing Techniques

Various implementations described herein are related to a device having header circuitry with first transistors that are configured to receive a supply voltage and provide a dynamically biased voltage. The device may include reference generation circuitry having multiple amplifiers that are configured to receive the supply voltage and provide reference voltages based on the supply voltage. The device may include bias generation circuitry having second transistors configured to track changes in the dynamically biased voltage and adjust the dynamically biased voltage by generating bias voltages based on the reference voltages and by applying the bias voltages to the header circuitry so as to adjust the dynamically biased voltage. 1. A device , comprising:header circuitry having first transistors configured to receive a supply voltage and provide a dynamically biased voltage;reference generation circuitry having multiple amplifiers configured to receive the supply voltage and provide reference voltages based on the supply voltage;bias generation circuitry having second transistors configured to track changes in the dynamically biased voltage and adjust the dynamically biased voltage by generating bias voltages based on the reference voltages and by applying the bias voltages to the header circuitry so as to adjust the dynamically biased voltage; andboost circuitry having third transistors that are configured to receive boost control signals.2. The device of claim 1 , wherein the bias generation circuitry is configured to provide the bias voltages so as to avoid stress or reliability issues related to one or more transistors in the device including the first transistors and the second transistors.3. The device of claim 1 , wherein the device comprises a level shifter that operates within a multi-voltage range associated with different voltage levels related to one or more of 1.8V claim 1 , 2.5V and 3.3V.4. The device of claim 1 ,wherein the third transistors generate ...

OSCILLATION CIRCUIT

An oscillation circuit for generating a clock signal of a switching power supply circuit is provided. The oscillation circuit includes a circuit configured to perform frequency spreading control of the clock signal in synchronization with an output operation control signal for periodically turning on/off an output operation of the switching power supply circuit. 1. An oscillation circuit for generating a clock signal of a switching power supply circuit , comprising:a circuit configured to perform frequency spreading control of the clock signal in synchronization with an output operation control signal for periodically turning on/off an output operation of the switching power supply circuit.2. The oscillation circuit of claim 1 , wherein the circuit comprises:a variable voltage generating part configured to generate a variable voltage in synchronization with the output operation control signal; anda clock signal generating part configured to determine an oscillation frequency of the clock signal based on the variable voltage.3. The oscillation circuit of claim 2 , wherein the variable voltage generating part samples/holds the variable voltage in synchronization with the output operation control signal.4. The oscillation circuit of claim 3 , wherein the variable voltage generating part includes:a first current source configured to generate a charging current of a capacitor;a second current source configured to generate a discharging current of the capacitor;a hysteresis comparator configured to generate a comparison signal by comparing a charging voltage appearing on a first terminal of the capacitor with a threshold voltage;a charging/discharging control part configured to control charging/discharging of the capacitor in response to the comparison signal and the output operation control signal; anda switch which is connected between the first terminal of the capacitor and an output terminal of the variable voltage and is configured to be switched on/off in response ...

Method of forming a semiconductor device and structure therefor

In one embodiment, a semiconductor device may include forming a first inverter and a second inverter to selectively receive separate inputs of a differential input signal and directly connecting each of the first and second inverters to receive power directly from a voltage input and a voltage return. The first inverter may be configured to include a first control switch that is configured to selectively couple together an upper transistor and a lower transistor of the first inverter. The second inverter may be configured to include a second control switch that is configured to selectively couple together an upper transistor and a lower transistor of the second inverter.

Level Shifter with Bypass Control

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include level shifting circuitry for translating an input signal from a first voltage domain to an output signal for a second voltage domain. The integrated circuit may include input logic circuitry for receiving multiple input signals and providing an inverted input signal to the level shifting circuitry based on the multiple input signals. The integrated circuit may include bypass switching circuitry for activating and deactivating the level shifting circuitry based on a bypass control signal and at least one of the multiple input signals. 1. An integrated circuit , comprising:level shifting circuitry for translating an input signal from a first voltage domain to an output signal for a second voltage domain;input logic circuitry for receiving multiple input signals and providing an inverted input signal to the level shifting circuitry based on the multiple input signals; andbypass switching circuitry for activating and deactivating the level shifting circuitry based on a bypass control signal and at least one of the multiple input signals.2. The integrated circuit of claim 1 , wherein the second voltage domain is different than the first voltage domain.3. The integrated circuit of claim 1 , wherein the first voltage domain is derived from a system-on-a-chip (SOC) logic voltage supply (VDDSOC) claim 1 , and wherein the second voltage domain is derived from a core voltage supply (VDDCE).4. The integrated circuit of claim 1 , wherein the input logic circuitry comprises a NOR gate that receives the multiple input signals and provides the inverted input signal to the level shifting circuitry based on the multiple input signals.5. The integrated circuit of claim 1 , wherein the level shifting circuitry comprises a plurality of transistors arranged for translating the input signal from the first voltage domain to the output signal for the second voltage domain.6. ...

Brown-out detector and power-on-reset circuit

A brown-out detector and power-on-reset circuit can be used to monitor a supply voltage to determine when brown-out and power-on events occur and provide the appropriate reset signal in response. The circuit can include a comparator to generate the reset signal and a first monitoring circuit that operates in conjunction with a second monitoring circuit to provide an input voltage to the comparator. The first monitoring circuit can incorporate a bandgap circuit and can be used to control the input voltage based on the comparison of the supply voltage and a corresponding supply voltage threshold. The second monitoring circuit can incorporate a diode and can be used when the supply voltage is lower than a threshold voltage for the bandgap circuit. The second monitoring circuit can be used to control the input voltage based on a comparison of the supply voltage and a threshold voltage for the diode.

Hysteresis comparator circuit and power supply apparatus

A hysteresis comparator circuit includes: a first switch that is coupled between a power supply line and an output terminal, is turned off when a supplied voltage on the power supply line is below a first value and is turned on when the supplied voltage is equal to or above the first value; a second switch coupled between the output terminal and a reference power line at a reference potential; and a control circuit that includes a third switch coupled between the power supply line and the reference power line. The third switch is turned off when the supplied voltage is below a second value that is smaller than the first value, and is turned on when the supplied voltage is equal to or above the second value. The control circuit turns the second switch on when the third switch is off, and turns the second switch off when the third switch is on.

Methods and Apparatus for a Configurable High-Side NMOS Gate Control with Improved Gate to Source Voltage Regulation

In described examples, a transistor has: a source and a drain coupled between a supply voltage and an output terminal; and a gate terminal. A charge pump has: an output node coupled to the gate terminal; and a clock input. An oscillator is coupled to generate a clock signal. A clock enable circuit is coupled to: receive the clock signal; and selectively output the clock signal to the clock input, responsive to an enable signal. A comparator is coupled to output the enable signal in response to a comparison between a reference current and a current through a series resistor. The series resistor is coupled to the gate terminal. 1. Apparatus , comprising:a transistor having: a source and a drain coupled between a supply voltage and an output terminal; and a gate terminal;a charge pump having: an output node coupled to the gate terminal; and a clock input;an oscillator coupled to generate a clock signal;a clock enable circuit coupled to: receive the clock signal; and selectively output the clock signal to the clock input, responsive to an enable signal; anda comparator coupled to output the enable signal to the clock enable circuit in response to a comparison between a reference current and a current through a series resistor; wherein the series resistor is coupled to the gate terminal.2. The apparatus of claim 1 , wherein the comparator is coupled to output the enable signal to the clock enable circuit in response to a voltage at the gate terminal being lower than a predetermined gate voltage level.3. The apparatus of claim 1 , wherein the comparator is a Schmitt trigger.4. The apparatus of claim 3 , wherein a voltage at an input node of the comparator falls in response to the current through the series resistor being lower than the reference current.5. The apparatus of claim 4 , wherein the Schmitt trigger is coupled to output a high signal in response to a voltage at the input node falling below a threshold voltage.6. The apparatus of claim 4 , wherein the Schmitt ...

LOOP INDEPENDENT DIFFERENTIAL HYSTERESIS RECEIVER

A delay independent differential hysteresis receiver. The differential hysteresis receiver uses two parallel paths in a first receiver stage, each path having a comparator with a dedicated offset on the complimentary inputs. A second receiver stage includes a hold circuit that brings the two parallel paths of the first receiver stage together to form a receiver hysteresis output. 1. A device , comprising: 'an input having a first input offset;', 'a first comparator that receives a differential voltage, the first comparator including 'an input having a second input offset;', 'a second comparator that receives the differential voltage, the second comparator including a first input coupled to an output of the first comparator;', 'a second input coupled to an output of the second comparator; and', 'an output voltage that is activated in response to a first voltage of the first input being greater than the first input offset and the second voltage of the second input being greater than the second input offset., 'a hold circuit, including2. The device of claim 1 , wherein the second input offset is greater than the first input offset.3. The device of claim 1 , wherein the hold circuit includes:a multiplexer, including: a second select input coupled to the output of the second comparator;', 'a first multiplexed input;', 'a second multiplexed input, the multiplexer configured to output the first multiplexed input in response to a first combination of the first select input and the second select input, and the multiplexer configured to output the second multiplexed input in response to a second combination of the first select input and the second select input., 'a first select input coupled to the output of the first comparator;'}4. The device of claim 3 , wherein the first multiplexed input is coupled to a first supply claim 3 , the second multiplexed input is coupled to a second supply.5. The device of claim 3 , wherein the hold circuit further includes a latch having an ...

Clock and Periodic Computing Machines

A new computational machine is invented, called a clock machine, that is a novel alternative to computing machines (digital computers) based on logic gates. In an embodiment, computation is performed with one or more clock machines that use time, and can perform any Boolean function. In an embodiment, a cryptographic cipher is implemented with random clock machines, constructed from a non-deterministic process, wherein the compiled set of instructions (i.e., the implementation of the cryptographic procedure) is distinct on each device or chip that executes the cryptographic cipher. In an embodiment, by using a different set of clock machines to execute two different instances of the same cryptographic procedure, each execution of a procedure looks different to malware that may try to infect and subvert the cryptographic procedure. This cryptographic process helps hinder timing attacks. In an embodiment, a detailed implementation of the Midori cipher with random clock machines is described. 1. A computing system for performing a computational procedure comprising:wherein a procedure performs a finite number of Boolean operations;constructing a first method of a multiplicity of possible methods for a first instance of the procedure;performing the first instance of the procedure with one or more clock or periodic machines;constructing a second method of the multiplicity of possible methods for a second instance of the procedure;and performing the second instance of the procedure with the one or more clock or periodic machines;wherein the one or more periodic machines performing the first instance of the procedure are not identical to the one or more periodic machines performing the second instance of the procedure;wherein the first instance of the procedure and the second instance of the procedure perform a same Boolean function, but the first instance of the procedure performs the Boolean function, via the first method, and the second instance of the procedure ...

MODULATORS

This application relates to time-encoding modulators () having a self-oscillating modulator module configured to receive an input signal and output a pulse-width modulated signal (S) where the pulse-width modulated signal is synchronised to a first clock signal (CLK). A hysteretic comparator module () located in a feedforward path is configured to generate the time encoded signal (S) at a first node () based on the input signal (S) and a feedback signal (S). A feedback path is coupled to the first node to provide the feedback signal, which is either applied to an input of the hysteretic comparator module via a loop filter () in the feedback path or applied to the feedforward path prior to a loop filter () upstream of the hysteretic comparator module (). The hysteretic comparator module () is configured such that any change in state of the time encoded signal at the first node is synchronised to the first clock signal (CLK). 1. A time-encoding modulator comprising:a feedforward path for receiving an input signal and outputting a time encoded signal;a hysteretic comparator module in the feedforward path configured to generate the time encoded signal at a first node based on the input signal and a feedback signal;a feedback path coupled to the first node to provide the feedback signal; and the feedback path; or', 'the feedforward path upstream of the hysteretic comparator module;, 'a loop filter configured to apply filtering to one ofwherein the hysteretic comparator module is configured such that any change in state of the time encoded signal at the first node is synchronised to a first clock signal.2. A time-encoding modulator as claimed in wherein the hysteretic comparator module comprises a latched comparator configured to receive the first clock signal claim 1 , wherein any changes in output state of the latched comparator is synchronised to the first clock signal.3. A time-encoding modulator as claimed in wherein the hysteretic comparator module comprises a ...

MASTER READ FROM SLAVE OVER PULSE-WIDTH MODULATED HALF-DUPLEX 1-WIRE BUS

Systems, methods, and apparatus for one wire communication are disclosed. A method performed at a master device includes driving a wire coupling the master device to a slave device from a first voltage to a second voltage, causing a line driver in the master device to present a high impedance to the wire after the wire has been driven to the second voltage, determining that the slave device is communicating a first bit-value when the wire has been driven to the first voltage before a threshold time period has elapsed, determining that the slave device is communicating a second bit-value when the wire is at the second voltage after the threshold time period has elapsed, and driving the wire to transition from the second voltage to the first voltage when the wire is at the second voltage after the threshold time period has elapsed. 1. A method of data communication performed at a master device , comprising:driving a wire coupling the master device to a slave device from a first voltage level to a second voltage level;causing a line driver in the master device to present a high impedance to the wire after the wire has been driven to the second voltage level;determining that the slave device is communicating a first bit-value when the wire has been driven to the first voltage level before a threshold duration of time has elapsed;determining that the slave device is communicating a second bit-value when the wire is at the second voltage level after the threshold duration of time has elapsed; anddriving the wire from the second voltage level to the first voltage level when the wire is at the second voltage level after the threshold duration of time has elapsed.2. The method of claim 1 , wherein the wire is driven by the master device to the second voltage level as a bit transmission interval begins.3. The method of claim 1 , further comprising:coupling a first resistor to the wire prior to causing the line driver in the master device to present the high impedance to the ...

REVERSE CURRENT SWITCH

Provided is a reverse current switch. The reverse current switch includes: a comparison unit including a first input end, a second input end, and a first output end; and a switch resistance unit, where a first end of the switch resistance unit is connected to the first input end, a second end of the switch resistance unit is connected to the second input end, and a third end of the switch resistance unit is connected to the output end of the comparison unit, and the switch resistance unit is controlled by a voltage of the first output end. This reverse current switch has a simple structure and can implement working under low voltage conditions. 1. A reverse current switch , comprising:a comparison unit comprising a first input end, a second input end, and a first output end; anda switch resistance unit, wherein a first end of the switch resistance unit is connected to the first input end, a second end of the switch resistance unit is connected to the second input end, and a third end of the switch resistance unit is connected to the first output end,wherein the switch resistance unit is controlled by a voltage of the first output end:when a voltage of the first input end is greater than a voltage of the second input end, the voltage of the first output end controls the switch resistance unit to be in an on state; orwhen a voltage of the first input end is less than a voltage of the second input end, the voltage of the first output end controls the switch resistance unit to be in an off state.2. The reverse current switch according to claim 1 , further comprising:a voltage controlled unit comprising a voltage controlled resistance unit and a voltage controlled voltage generation unit, wherein the voltage controlled resistance unit and the switch resistance unit are connected in series between the first input end and the second input end, the voltage controlled voltage generation unit is connected in parallel with the comparison unit, and voltage controlled voltage ...

LEVEL VOLTAGE GENERATION CIRCUIT, DATA DRIVER, AND DISPLAY APPARATUS

The display apparatus includes: N differential amplifiers having output ends, amplifying N input voltages and outputting amplified voltages, and a resistor ladder having N voltage supply points connected to the output ends of the N differential amplifiers and M voltage output points outputting M level voltages. The M voltage output points are connected to capacitive loads on input sides of the amplifiers, and at least one N differential amplifier has an input pair and an output end connected to one of the N voltage supply point. One of the N input voltages is received by one of the input pair, the other one of the input pair is connected to one of the M voltage output points outputting a level voltage closest to a voltage at the one voltage supply point. The one voltage supply point and the one voltage output point are at different positions on the resistor ladder. 1. A level voltage generation circuit , which generates , based on N (N is an integer greater than or equal to 2) different input voltages , M (M is an integer greater than N) level voltages , the level voltage generation circuit comprising:N differential amplifiers having output ends, which receive the N input voltages respectively, amplify the N input voltages respectively and output amplified N input voltages, anda resistor ladder having N voltage supply points respectively connected to the output ends of the N differential amplifiers and M voltage output points for outputting the M level voltages;wherein the M voltage output points are connected to capacitive loads on input sides of load amplifiers, and at least one of the N differential amplifiers has an input pair and an output end connected to one of the N voltage supply points,one of the N input voltages is received by one of the input pair, the other one of the input pair is connected to one of the M voltage output points for outputting a level voltage closest to a voltage at the one voltage supply point, and the one voltage supply point and the ...

SEMICONDUCTOR DEVICE INCLUDING DIFFERENTIAL INPUT CIRCUIT AND CALIBRATION METHOD THEREOF

According to an embodiment, a semiconductor device includes a differential input circuit suitable for receiving first and second input signals respectively inputted to first and second input transistors, and outputting an output signal; a comparison circuit suitable for generating a first judge signal by comparing the output signal with a first comparison voltage, and generating a second judge signal by comparing the output signal with a second comparison voltage, in a calibration mode; an offset control circuit suitable for adjusting coarse codes and fine codes, according to the first and second judge signals; and an offset adjusting circuit suitable for adjusting a drivability of each of the first and second input transistors by a first strength, according to the coarse codes, and adjusting the drivability of each of the first and second input transistors by a second strength smaller than the first strength, according to the fine codes.

Sequential circuit with timing event detection and a method of detecting timing events

A sequential circuit with timing event detection is disclosed. The sequential circuit has an input that is asserted to the output during the second clock phase of a two phase clock signal. A timing event detector is coupled to the sequential element input to assert a timing event signal if a transition occurs at the sequential element input during the second clock phase but not to assert during the first clock phase.

Activity detection

This application relates an activity detector ( 100 ) for detecting signal activity in an input audio signal (S IN ), such as may be used for always-on speech detection. The activity detector has a first time-encoding modulator (TEM) 101 including a first hysteretic comparator ( 201 ) for generating a PWM (pulse-width modulation) signal based on the input audio signal. A second TEM ( 103 ) having a second hysteretic comparator ( 401 ) is arranged to receive a reference voltage (V MID ) and generate a clock signal (S CLK ). A time-decoding converter ( 102 ) receives the clock signal and generates count values of a number of cycles of the clock signal in periods defined by the PWM signal. An activity monitor ( 104 ) is responsive to a count signal (S CT ) from the TDC 102 to determine whether the input audio signal comprises signal activity above a defined threshold.

Level shifter

The present disclosure provides a level shifter including: a level shifter section that is driven by a first power source voltage, and that, in accordance with switching of an input signal of a voltage lower than the first power source voltage, switches an output signal that has been level-shifted, from the first power source voltage to a voltage lower than the first power source voltage; and a threshold voltage changing circuit that, in accordance with a switching direction of the input signal, changes a threshold voltage of the input signal for switching the output signal.

Persistent nodes for rfid

An RFID transponder in one embodiment comprises a radio frequency (RF) transceiver, processing logic coupled to the RF transceiver, a switch coupled to the processing logic, a tunneling device coupled to the switch and a differential sensing circuit having a first input coupled to the tunneling device and a second input coupled to a predetermined reference voltage. In one embodiment, the tunneling device can discharge to a voltage below the predetermined reference voltage.

COMPARATOR CIRCUITS WITH LOCAL RAMP BUFFERING FOR A COLUMN-PARALLEL SINGLE-SLOPE ADC

A comparator circuit suitable for use in a column-parallel single-slope analog-to-digital converter comprises a comparator, an input voltage sampling switch, a sampling capacitor arranged to store a voltage which varies with an input voltage when the sampling switch is closed, and a local ramp buffer arranged to buffer a global voltage ramp applied at an input. The comparator circuit is arranged such that its output toggles when the buffered global voltage ramp exceeds the stored voltage. Both DC- and AC-coupled comparator embodiments are disclosed. 1. A comparator circuit suitable for use in a column-parallel single-slope analog-to-digital converter , said comparator circuit comprising:an input node;a comparator;an input voltage sampling switch coupled to said input node;a sampling capacitor arranged to store a voltage which varies with an input voltage applied to said input node when said sampling switch is closed; anda local ramp buffer having an associated input and arranged to buffer a global voltage ramp applied directly to said local ramp buffer's input;said comparator circuit arranged such that the output of said comparator toggles when said buffered global voltage ramp exceeds said stored voltage.2. The comparator circuit of claim 1 , wherein said stored voltage is applied at a first input terminal of said comparator and said buffered global voltage ramp is applied at said comparator's second input terminal.3. The comparator circuit of claim 2 , wherein said sampling capacitor is connected between said comparator's first input terminal and a circuit common point and said sampling switch is connected between said input voltage and said comparator's first input terminal.4. The comparator circuit of claim 3 , said comparator circuit arranged to receive timing signals which operate said sampling switch such that said voltage is stored on said sampling capacitor before said global voltage ramp starts to ramp.5. A comparator circuit suitable for use in a column- ...

CYCLIC CONTROL OF CELLS OF AN INTEGRATED CIRCUIT

An embodiment of the present disclosure relates to a circuit of cyclic activation of an electronic function comprising a hysteresis comparator controlling the charge of a capacitive element powering the function. 1. A circuit for cyclic activation of an electronic function , the circuit comprising:a capacitive element configured to power the electronic function; anda hysteresis comparator configured to control charging of the capacitive element.2. The circuit of claim 1 , wherein the electronic function is configured to be activated according to a result of a comparison performed by the hysteresis comparator.3. The circuit of claim 1 , comprising a constant current source configured to charge the capacitive element.4. The circuit of claim 3 , further comprising a switch interposed between the constant current source and the capacitive element.5. The circuit of claim 1 , wherein the hysteresis comparator is powered with a voltage different from a voltage of the capacitive element.6. A method of cyclic activation of an electronic function claim 1 , the method comprising:generating a voltage ramp; andrepeatedly activating and deactivating the electronic function on each change of direction of the voltage ramp.7. The method of claim 6 , wherein generating the voltage ramp comprises charging and discharging a capacitive element.8. (canceled)9. The method of claim 7 , wherein repeatedly activating and deactivating the electronic function comprises repeatedly activating and deactivating claim 7 , respectively claim 7 , a switch interposed between the capacitive element and a constant current source.10. The method of claim 7 , wherein the voltage ramp is generated by a hysteresis comparator that is configured to control the charging and discharging of the capacitive element.11. The method of claim 10 , wherein the hysteresis comparator is coupled to repeatedly activate and deactivate the electronic function.12. The method of claim 11 , further comprising powering the ...

SWITCHING REGULATOR BASED ON LOAD ESTIMATION AND OPERATING METHOD THEREOF

A switching regulator may be used to generate an output voltage from an input voltage. The switching regulator includes; an inductor including a first terminal and a second terminal that passes an inductor current from the first terminal to the second terminal, a first switch that applies the input voltage to the first terminal when turned ON, a second switch that applies a ground potential to the first terminal when turned ON, a feedback circuit configured to estimate a load receiving the output voltage, detect when the inductor current reaches an upper bound or a lower bound, and adjust the lower bound based on the estimated load, and a switch driver configured to control the first switch and the second switch, such that the inductor current is between the upper bound and the lower bound in response to at least one feedback signal provided by the feedback circuit. 1. A switching regulator that generates an output voltage from an input voltage , the switching regulator comprising:an inductor including a first terminal and a second terminal, wherein the inductor passes an inductor current from the first terminal to the second terminal;a first switch that applies the input voltage to the first terminal when turned ON;a second switch that applies a ground potential to the first terminal when turned ON;a load estimator that estimates a load receiving the output voltage and provides load information corresponding to the load;a first current detector that detects when the inductor current reaches a lower bound and generates a first detection signal, the lower bound being adjusted based on the load information; anda switch driver configured to turn OFF the second switch in response to the first detection signal when the inductor current reaches the lower bound.2. The switching regulator of wherein the load estimator estimates the load based on a period in which the inductor current is equal to or greater than the lower bound.3. The switching regulator of claim 2 , further ...

ASYMMETRIC HYSTERETIC CONTROLLERS

An asymmetric hysteretic controller comprises an analog comparator coupled with a fast slew rate DAC, or a digital comparator coupled with an ADC plus some digital control logic. The comparator, analog or digital, operates as a sequential windowed comparator having high and low limits. The sense parameter is compared to a high or a low limit and when the sense parameter reaches the selected high or low limit, the controlled device is turned off or on, respectively. When the hysteretic controller state comparison reversal occurs: (a) the comparator output may be blanked by the control logic, (b) the comparator polarity may be reversed by the control logic, (c) the control logic may command the other process limit to be selected for comparison with the sense parameter, and (d) then the comparator output may be re-enabled. 1. A method for hysteretic control of a pulse width modulation (PWM) generator , said method comprising the steps of:monitoring an output of a PWM generator;determining when the output of the PWM generator changes from a low to a high level;starting a blanking timer when the output of the PWM generator changes from the low to the high level;selecting a high limit value from a high limit register as an input to a digital-to-analog converter (DAC);determining when the blanking timer has timed out;enabling an output of a comparator when the blanking timer has timed out for indicating a comparison of an output of the DAC representing the high limit value with a process feedback signal;determining when the process feedback signal is greater than the DAC output;signaling the PWM generator to change its output to the low level when the process feedback signal is greater than the DAC output;determining when the output of the PWM generator changes from the high to the low level;starting the blanking timer when the output of the PWM generator changes from the high to the low level;reversing the output of the comparator;selecting a low limit value from a low ...

High speed sync fet control

A circuit arrangement is disclosed for controlling the switching of a field effect transistor (FET). A current controlled amplifier may be configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET. A comparator may be coupled to the current sense amplifier to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off.

LOW POWER CIRCUIT FOR TRANSISTOR ELECTRICAL OVERSTRESS PROTECTION IN HIGH VOLTAGE APPLICATIONS

Described is an apparatus which comprises a pass-gate; and a control unit to control gate terminal of the pass-gate according to first availability of first or second power supplies, the control unit including: a voltage detector to detect the second power supply; and a supply switching circuit to generate a local supply for controlling the gate terminal of the pass-gate according to an output of the voltage detector. 1. An apparatus to provide an electrical overstress protection comprising:a control unit to receive a first power supply and a second power supply, the control unit comprising an input stage to receive the second power supply, and', 'a voltage divider coupled to the input stage, the voltage divider to receive the first power supply and generate a bias voltage to control the input stage; and, 'a voltage detector comprising'}a supply switching circuit coupled to an output of the voltage detector to generate a local supply according to the output of the voltage detector.2. The apparatus of claim 1 , further comprisinga transistor coupled to the control unit, wherein the local supply causes the transistor to turn OFF, if the second power supply is less than a predetermined threshold.3. The apparatus of claim 2 , further comprisinga driver coupled to the transistor.4. The apparatus of claim 1 , wherein the voltage detector comprises a hysteresis circuit to receive the output of the input stage claim 1 , the hysteresis circuit to generate the output of the voltage detector.5. The apparatus of claim 4 , wherein the hysteresis circuit comprises a Schmitt Triggered device.6. The apparatus of claim 4 , wherein the hysteresis circuit is powered by the bias voltage.7. The apparatus of claim 1 , wherein the voltage divider comprises a plurality of diode connected devices.8. The apparatus of claim 1 , wherein the voltage divider comprises a switch to receive an output of the input stage.9. The apparatus of claim 1 , wherein the supply switching circuit comprises:a ...

LOW-POWER FLIP FLOP CIRCUIT

A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal. 1. A method to operate a flip-flop circuit , comprising:receiving a scan-in signal and a data signal;selectively coupling either the scan-in signal or the data signal to coupled master and slave latches; andbased on a clock signal, selectively activating either the master latch or the slave latch so as to latch either the scan-in signal or the data signal as an output signal of the flip-flop circuit.2. The method of claim 1 , wherein the master latch circuit comprises a pair of cross-coupled OR-AND-Inverter (OAI) logic gates claim 1 , and the slave latch circuit comprises a pair of cross-coupled AND-OR-Inverter (AOI) logic gates claim 1 , and wherein the master and slave latch circuits each comprises at most two transistors configured to receive the clock signal.3. The method of claim 2 , wherein the at most two transistors of the first and second latch circuits claim 2 , respectively claim 2 , each receives the clock signal at a respective gate.4. The method of claim 2 , further comprising:selecting either a data signal or a scan-in signal as the input signal in response to an enable signal.5. The method claim 4 , further comprising:providing a logically inverted clock signal to the at most two transistors of the first latch circuit and the at most two transistors of the second latch circuit, respectively.6. The method of claim 1 , wherein the at most two transistors of the first and second latch circuits claim 1 , respectively claim 1 , comprise a p-type metal-oxide-semiconductor ...

Ring amplitude measurement and mitigation

An apparatus includes a voltage divider circuit including a plurality of series-connected capacitors and including an input terminal of one of the capacitors configured to receive a first voltage from a switch, and a ring node comprising the connection between at least two of the series-connected capacitors. The apparatus further includes a negative clamp circuit coupled to the ring node of the voltage divider circuit and a bias voltage node. The bias voltage node is configured to receive a bias voltage and responsive to a ring voltage on the ring node being less than the bias voltage, the negative clamp circuit is configured to clamp the ring voltage at a first threshold voltage. The apparatus also includes a peak detector circuit coupled to the ring node of the voltage divider circuit and configured to detect a peak amplitude of the ring voltage. The apparatus further includes a switch driver coupled to the peak detector circuit and configured to adjust a control signal to the switch responsive to the detected peak amplitude.

ADJUSTABLE OVER-CURRENT DETECTOR CIRCUIT FOR UNIVERSAL SERIAL BUS (USB) DEVICES

In an example embodiment, a universal serial bus (USB) Type-C controller comprises a current detector circuit configured to provide over-current protection on a voltage bus (VBUS) line. The current detector circuit comprises a current sense amplifier, a reference voltage generator, and a comparator coupled to the current sense amplifier and to the reference voltage generator. The current sense amplifier is configured to receive a pair of input voltages from the VBUS line and to output an indicator signal responsive to an input voltage difference between the pair of input voltages. The reference voltage generator is configured to generate a reference voltage in response to a voltage selector signal. The comparator is configured to output an interrupt signal responsive to the indicator signal exceeding the reference voltage. 120-. (canceled)21. A universal serial bus (USB) Type-C controller configured to provide over-current protection on a voltage bus (VBUS) line , the controller comprising: a current sense amplifier configured to receive a pair of input voltages from the VBUS line and to output an indicator signal responsive to an input voltage difference between the pair of input voltages;', 'a reference voltage generator configured to generate a reference voltage in response to a voltage selector signal; and', 'a comparator coupled to the current sense amplifier and to the reference voltage generator, wherein the comparator is configured to generate an output signal responsive to the indicator signal exceeding the reference voltage., 'a current detector circuit comprising22. The controller of claim 21 , wherein the reference voltage generator is configured to generate the reference voltage based on one of a plurality of preset reference voltages indicated by the voltage selector signal.23. The controller of claim 21 , wherein:the voltage selector signal is a binary input signal comprising multiple bit values; andthe reference voltage generator comprises a digital- ...

ACTIVITY DETECTION

This application relates an activity detector () for detecting signal activity in an input audio signal (S), such as may be used for always-on speech detection. The activity detector has a first time-encoding modulator (TEM) including a first hysteretic comparator () for generating a PWM (pulse-width modulation) signal based on the input audio signal. A second TEM () having a second hysteretic comparator () is arranged to receive a reference voltage (V) and generate a clock signal (S). A time-decoding converter () receives the clock signal and generates count values of a number of cycles of the clock signal in periods defined by the PWM signal. An activity monitor () is responsive to a count signal (S) from the TDC to determine whether the input audio signal comprises signal activity above a defined threshold. 1. An activity detector for detecting signal activity in an input audio signal comprising:a first time-encoding modulator comprising a first hysteretic comparator for generating a PWM (pulse-width modulation) signal based on the input audio signal;a second time-encoding modulator comprising a second hysteretic comparator for receiving a reference voltage and generating a clock signal based on the reference voltage;a time-decoding converter configured to receive the clock signal, generate count values of a number of cycles of the clock signal in periods defined by the PWM signal and output a count signal based on said count values; andan activity monitor responsive to the count signal to determine whether the input audio signal comprises signal activity above a defined threshold.2. An activity detector as claimed in wherein the second time-encoding modulator is configurable so as to vary the frequency of the clock signal and wherein the activity detector is configured so as to operate:in a first mode, with the second time-encoding modulator controlled to generate the clock signal at a first frequency, when the input audio signal comprises no signal activity ...

METHOD FOR SYNCHRONISING COMMUTATED CONTROL CIRCUITS CONTROLLED BY PWM CONTROL SIGNALS

Disclosed is a method for synchronising at least one slave control circuit, controlled by a slave control signal having pulse width modulation, with a master control circuit, controlled by a master control signal having pulse width modulation, including the following steps: the master control circuit emitting a synchronisation signal indicating a master edge of an electrical quantity; the slave control circuit receiving the synchronisation signal; measuring a delay between a slave edge of the same electrical quantity and the master edge of the electrical quantity; time-shifting the slave control signal so as to reduce the delay; and repeating the measurement step until the delay is eliminated. 112341234. A method for synchronizing at least one slave control circuit (S) , of switched type , controlled by a slave control signal (S) having pulse width modulation exhibiting a slave period (S) and controlling a slave load (S) , with a master control circuit (M) , of switched type , controlled by a master control signal (M) having pulse width modulation exhibiting a master period (M) and controlling a master load (M) , the method comprising the following steps:{'b': 1', '5', '67', '68', '7', '8', '1, 'the master control circuit (M) transmitting a synchronization signal () that is indicative of a master edge (M, M) of an electrical quantity (M, M) of the master circuit (M);'}{'b': 1', '5, 'the slave control circuit (S) receiving the synchronization signal ();'}{'b': 9', '67', '68', '7', '8', '1', '67', '68', '7', '8', '1', '5, 'measuring an interval (SM) between a slave edge (S, S) of the same electrical quantity (S, S) of the slave circuit (S) and the master edge (M, M) of the electrical quantity (M, M) of the master circuit (M), such as indicated by the synchronization signal ();'}{'b': 92', '92', '2', '9, 'time-shifting (E, T) the slave control signal (S) so as to decrease said interval (SM);'}{'b': '9', 'repeating the measurement step until said interval (SM) is ...

CELL OF TRANSMISSION GATE FREE CIRCUIT AND INTEGRATED CIRCUIT LAYOUT INCLUDING THE SAME

A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings. 1. A semiconductor standard cell of a flip-flop circuit , the semiconductor standard cell comprising:semiconductor fins extending substantially parallel to each other along a first direction;lower electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction;gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and disposed on a second level different from the first level; andupper electrically conductive wirings disposed on a third level above the first level, with reference to the semiconductor fins, and extending substantially parallel to each other along the second direction,wherein the flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, andonly ...

CELL OF TRANSMISSION GATE FREE CIRCUIT AND INTEGRATED CIRCUIT LAYOUT INCLUDING THE SAME

A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings. 1. A semiconductor standard cell of a flip-flop circuit , the semiconductor standard cell comprising:a plurality of semiconductor fins extending substantially parallel to each other along a first direction;a plurality of electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction; anda plurality of gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level,wherein the flip-flop circuit includes a plurality of transistors made of the plurality of semiconductor fins and the plurality of gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal,the clock signal is the only clock signal received by the semiconductor standard cell, andthe data input signal, the clock signal, and the ...

Minimum pulse-width assurance

Various methods and devices that involve pulsed signals are disclosed. An example minimum pulse-width (MPW) circuit comprises a first and second logic circuit. A first input of the first logic circuit is connected to an input of the MPW circuit. A first input of the second logic circuit is communicatively coupled to an output of the first logic circuit. The MPW circuit also comprises a MPW filter circuit communicatively coupled to an output of the second logic circuit, a one-shot circuit communicatively coupled to an output of the minimum pulse-width filter circuit and located on a first feedback path, and another one-shot circuit communicatively coupled to the output of the minimum pulse-width filter circuit and located on a second feedback path. A second input of the first logic circuit is on the first feedback path. A second input of the second logic circuit is on the second feedback path.

CURRENT CONTROLLED AMPLIFIER

A circuit arrangement is disclosed for controlling the switching of a field effect transistor (FET). A current controlled amplifier may be configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET. A comparator may be coupled to the current sense amplifier to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off. 1. A current-controlled amplifier (CCA) comprising: a differential input configured to sense current flowing through a sense resistance that is coupled between the differential input;', 'an output configured to sink an output current that is an amplified version of the sensed current;, 'a modified Wilson current mirror includingand a first transistor, wherein the output of the modified Wilson current mirror is coupled to first transistor, and wherein the first transistor is configured to source a CCA output current based on the output of the modified Wilson current mirror.2. The CCA of claim 1 , wherein a positive node of the differential input is coupled to ground and to a first side of the sense resistance claim 1 , and wherein a negative node of the differential input is coupled to a second side of the sense resistor through a gain resistor.3. The CCA of claim 1 , further comprising:temperature compensation configured to compensate for a drift in a resistance of the sense resistance.4. The CCA of claim 3 , wherein the temperature compensation includes at least one of: a negative temperature coefficient (NTC) claim 3 , a positive temperature coefficient (PTC) claim 3 , or a PN junction.5. The CCA of claim 1 , further comprising:a biasing resistor coupled between a voltage supply node and a node of the modified Wilson current mirror, wherein the biasing resistor improves a speed of the ...

LEVEL VOLTAGE GENERATION CIRCUIT, DATA DRIVER, AND DISPLAY APPARATUS

A level voltage generation circuit, a data driver and a display are provided. The level voltage generation circuit generates, based on N different input voltages, M (M>N) level voltages. The level voltage generation circuit comprises N differential amplifiers having output ends, which receive the N input voltages respectively, amplify the N input voltages respectively and output amplified N input voltages, and a resistor ladder having N voltage supply points respectively connected to the output ends of the N differential amplifiers and M voltage output points for outputting the M level voltages. The resistor ladder comprises a first wiring, connected to the output end of one of the N differential amplifiers through one of the N voltage supply points; and a second wiring, connected between one of the M voltage output points and one of an input pair of one of the N differential amplifiers. 1. A level voltage generation circuit , which generates , based on N (N is an integer greater than or equal to 2) different input voltages , M (M is an integer greater than N) level voltages , the level voltage generation circuit comprising:N differential amplifiers having output ends, which receive the N input voltages respectively, amplify the N input voltages respectively and output amplified N input voltages, anda resistor ladder having N voltage supply points respectively connected to the output ends of the N differential amplifiers and M voltage output points for outputting the M level voltages;wherein the resistor ladder comprises:a first wiring, connected to the output end of one of the N differential amplifiers through one of the N voltage supply points; anda second wiring, connected between one of the M voltage output points and one of an input pair of one of the N differential amplifiers.2. The level voltage generation circuit according to claim 1 , wherein the resistor ladder has a wiring group including the second wiring claim 1 ,the first wiring and the second wiring ...

ADJUSTABLE OVER-CURRENT DETECTOR CIRCUIT FOR UNIVERSAL SERIAL BUS (USB) DEVICES

In an example embodiment, a device comprises a gate driver and a current detector circuit. The gate driver is configured to be coupled to a power switch on the VBUS line of a USB connector. The current detector circuit is configured to be coupled to the VBUS line and comprises a current sense amplifier, a reference voltage generator circuit, and a comparator. The current sense amplifier is configured to receive a pair of input voltages and to output an indicator signal responsive to the input voltage difference. The reference voltage generator circuit comprises a digital-to-analog converter configured to generate a reference voltage signal based on a received voltage selector signal that is a binary input signal comprising multiple bit values. The comparator is configured to receive the indicator signal and the reference voltage signal and to output an interrupt signal responsive to the indicator signal exceeding the reference voltage signal. 120-. (canceled)21. A device comprising:a gate driver configured to control a power switch on a voltage bus (VBUS) line of a universal serial bus (USB) connector; and a current sense amplifier configured to receive a pair of input voltages and to output an indicator signal responsive to an input voltage difference that is sensed based on the pair of input voltages;', 'a reference voltage generator circuit comprising a digital-to-analog converter and configured to receive a voltage selector signal, wherein the digital-to-analog converter is configured to generate a reference voltage signal based on the voltage selector signal, and wherein the voltage selector signal is a binary input signal comprising multiple bit values; and', 'a comparator coupled to the current sense amplifier and to the reference voltage generator circuit, wherein the comparator is configured to receive the indicator signal and the reference voltage signal and to output an interrupt signal responsive to the indicator signal exceeding the reference voltage ...

SIGNAL SELF-CALIBRATION CIRCUITS AND METHODS

A signal self-calibration circuit and a signal self-calibration method are provided. The signal self-calibration circuit includes a comparator, a switcher, and an output-stage circuit. The comparator has a non-inverting input terminal and an inverting input terminal. An input signal and a reference signal are alternately input to the non-inverting input terminal and the inverting input terminal of the comparator. The switcher switches the input signal and the reference signal which are input to the non-inverting input terminal and the inverting input terminal of the comparator when a rising edge occurs at an output signal of the comparator. The output-stage circuit generates a square-wave signal with a duty ratio of 50% according to the output signal of the comparator. 1. A signal self-calibration circuit , comprising:a comparator having a non-inverting input terminal and an inverting input terminal, wherein an input signal and a reference signal are alternately input to the non-inverting input terminal and the inverting input terminal of the comparator;a switcher, configured for switching the input signal and the reference signal which are input to the non-inverting input terminal and the inverting input terminal of the comparator when a rising edge occurs at an output signal of the comparator; andan output-stage circuit, configured for generating a square-wave signal with a duty ratio of 50% according to the output signal of the comparator.2. The signal self-calibration circuit as claimed in claim 1 , wherein the output signal of the comparator comprises a series of pulses claim 1 , and a time interval between any two adjacent pulses of the series of pulses is equal to a half of a period of the square-wave signal.3. The signal self-calibration circuit as claimed in claim 1 , wherein when a rising edge occurs at the output signal of the comparator claim 1 , the voltage level of the square-wave signal is inverted.4. The signal self-calibration circuit as claimed in ...

METHODS AND SYSTEMS FOR OPERATING AN ELECTRONIC SYSTEM

In one example, an electronic system includes, a user interface comprising an input device, a first actuator and a second actuator, the first and second actuators dually actuated by the input device, and a controller, including a comparator, a programmable device, and executable instructions residing in non-transitory memory thereon to, receive first and second output signals from the first and second actuators, respectively, convert the first and second output signals to first and second real-time logic states at the comparator, input the first and second real-time logic states from the comparator to the programmable device, and determine a fault status of the first and second actuators based on the first and second logic states input to a state machine of the programmable device, wherein the first and second logic states input to the state machine include the real-time logic states and historical logic states stored at the controller. 1. An electronic system including:a user interface comprising an input device,a first actuator and a second actuator, the first and second actuators dually actuated by the input device, and a comparator,', 'a programmable device including a state machine, and', receive first and second output signals from the first and second actuators, respectively,', 'convert the first and second output signals to first and second real-time logic states at the comparator,', 'input the first and second real-time logic states from the comparator to the programmable device,, 'executable instructions residing in non-transitory memory thereon to,'}, 'and, 'a controller, including'}determine a fault status of the first and second actuators based on the first and second logic states input to the state machine, wherein the first and second logic states input to the state machine include the real-time logic states and historical logic states stored at the controller.2. The electronic system of claim 1 , wherein the historic logic states include logic states ...

Controllers for Regulated Power Inverters, AC/DC, and DC/DC Converters

Methods and corresponding apparatus for regulation, control, and management of DC-to-AC, AC-to-DC, and/or DC-to-DC switching power conversion. 1. A switching converter capable of converting a 3-phase AC source voltage into a DC output voltage and providing a DC power output , wherein said 3-phase AC source voltage is characterized by three AC voltages , wherein an AC voltage is one of said three AC voltages , wherein said DC output voltage is characterized by a DC common mode voltage , wherein said switching converter comprises a 3-phase bridge comprising three pairs of switches and capable of providing three switching voltages , wherein a switching voltage is provided by a pair of switches controlled by a controller providing a 1st control signal and a 2nd control signal , and wherein a 1st switch of said pair of switches is controlled by said 1st control signal and a 2nd switch of said pair of switches is controlled by said 2nd control signal , said switching converter further comprising a digital signal processing apparatus performing numerical functions including:a) a numerical integrator function operable to receive an integrator input and to produce an integrator output, wherein said integrator output is proportional to a numerical antiderivative of said integrator input;b) a 1st numerical Schmitt trigger characterized by a hysteresis gap and a 1st reference level, and operable to receive a Schmitt trigger input and to produce said 1st control signal; andc) a 2nd numerical Schmitt trigger characterized by said hysteresis gap and a 2nd reference level, and operable to receive said Schmitt trigger input and to produce said 2nd control signal;wherein said integrator input comprises a sum of a digital representation of said AC voltage and a digital representation of the difference between said switching voltage and said DC common mode voltage, and wherein said Schmitt trigger input comprises said integrator output.2. The switching converter of wherein said DC ...

LLC CONVERTER WITH WAKE-UP CIRCUITRY

A circuit arrangement is disclosed for controlling the switching of a field effect transistor (FET). A current controlled amplifier may be configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET. A comparator may be coupled to the current sense amplifier to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off. 1. An LLC converter comprising:a transformer including a primary side and a secondary side, wherein the secondary side includes a first secondary winding and a second secondary winding;an output capacitor coupled to the first secondary winding and to the second secondary winding, the output capacitor configured to store an output charge;a first switch serially coupled between the first secondary winding and the output capacitor, wherein the first switch is configured to control charging the output capacitor;a first controller coupled to the first secondary winding, the first controller configured to control whether the first switch is open or closed, wherein the first controller includes a first current controlled amplifier to amplify a sensed first current flowing through the first switch;a second switch serially coupled between the second secondary winding and the output capacitor, wherein the second switch is configured to control charging the output capacitor;a second controller coupled to the second secondary winding, the second controller configured to control whether the second switch is open or closed, wherein the second controller includes a second current controlled amplifier to amplify a sensed second current flowing through the second switch; anda wake-up circuit configured to deliver a pulse to wake up the LLC converter.2. The LLC converter of claim 1 , wherein a first gain ...

FLYBACK CONVERTER WITH WAKE-UP CIRCUITRY

A circuit arrangement is disclosed for controlling the switching of a field effect transistor (FET). A current controlled amplifier may be configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET. A comparator may be coupled to the current sense amplifier to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off. 1. A flyback power converter comprising:a transformer including a primary side and a secondary side;an output capacitor coupled to the secondary side of the transformer, the output capacitor configured to store an output charge;a switch serially coupled between the second side of the transformer and the output capacitor, wherein the switch is configured to allow current to flow to charge the output capacitor when the switch is closed and to prevent current to flow when the switch is open;a controller coupled to the secondary side of the transformer, the controller configured to control whether the switch is open or closed, wherein the controller includes a current controlled amplifier to amplify a sensed current flowing through the switch; anda wake-up circuit configured to deliver a pulse to wake up the flyback power converter.2. The flyback power converter of claim 1 , wherein a gain of the current controlled amplifier is controllable to tune a turn-on point at which the switch is turned on and to tune a turn-off point at which the switch is turned off.3. The flyback power converter of claim 1 , wherein the switch is a field effect transistor (FET).4. The flyback power converter of claim 3 , wherein the controller includes gate drive circuitry configured to drive a gate of the FET based at least in part on the sensed current flowing through the FET.5. The flyback converter of claim 4 , ...

LATCH CIRCUIT, SCAN TEST CIRCUIT AND LATCH CIRCUIT CONTROL METHOD

A latch circuit includes: a data latch that holds data that has been input according to a first control signal or a second control signal; and a latch controller that includes a first input terminal to which a first operation signal is input, the first operation signal operating the data latch in a first scan method, and a second input terminal to which a second operation signal is input, the second operation signal operating the data latch in a second scan method; wherein when a prescribed value is input to the first input terminal, the latch controller outputs the second control signal to control the data latch, and when a prescribed value is input to the second input terminal, the latch controller outputs the first control signal to control the data latch. 1. A latch circuit , comprising:a data latch that holds data that has been input according to one of a first control signal and a second control signal; and a first input terminal to which a first operation signal is input, the first operation signal operating the data latch in a first scan method, and', when a prescribed value is input to the first input terminal and the second operation signal is input to the second input terminal, the latch controller outputs the second control signal to control the data latch, and', 'when a prescribed value is input to the second input terminal and the first operation signal is input to the first input terminal, the latch controller outputs the first control signal to control the data latch., 'a second input terminal to which a second operation signal is input, the second operation signal operating the data latch in a second scan method; wherein'}], 'a latch controller that comprises2. The latch circuit according to claim 1 , wherein:the data latch comprises:a first switch that operates to retrieve first data,a second switch that operates to retrieve second data,a first latch that holds the first data retrieved from the first switch or the second data retrieved from the ...

Safety mechanism for digital reset state

A system is provided, comprising: a plurality of flip-flops that are configured to receive a reset signal, each of the plurality of flip-flops having a respective output port, and each of the plurality of flip-flops being configured to assume a respective default state when the reset signal is set to a predetermined value; and a reset monitor circuit that is coupled to the respective output port of each of the plurality of flip-flops, the reset monitor circuit being configured to generate a status signal indicating whether each of the flip-flops has assumed the flip-flop's respective default state after the reset signal is set to the predetermined value, wherein assuming a respective default state by each of the plurality of flip-flops results in a predetermined bit string being stored in the plurality of flip-flops.

RING AMPLITUDE MEASUREMENT AND MITIGATION

An apparatus includes a voltage divider circuit including a plurality of series- connected capacitors and including an input terminal of one of the capacitors configured to receive a first voltage from a switch, and a ring node comprising the connection between at least two of the series-connected capacitors. The apparatus further includes a negative clamp circuit coupled to the ring node of the voltage divider circuit and a bias voltage node. The bias voltage node is configured to receive a bias voltage and responsive to a ring voltage on the ring node being less than the bias voltage, the negative clamp circuit is configured to clamp the ring voltage at a first threshold voltage. The apparatus also includes a peak detector circuit coupled to the ring node of the voltage divider circuit and configured to detect a peak amplitude of the ring voltage. The apparatus further includes a switch driver coupled to the peak detector circuit and configured to adjust a control signal to the switch responsive to the detected peak amplitude. 2. The ring amplitude adjustment circuit of claim 1 , further comprising a positive clamp circuit coupled to the ring node of the voltage divider circuit and configured to clamp the ring voltage at a second threshold voltage responsive to the ring voltage being greater than the second threshold voltage.3. The ring amplitude adjustment circuit of claim 2 , wherein the positive clamp circuit comprises:a first switch configurable, responsive to the ring voltage being greater than the second threshold voltage, to form a first current sink path for a first sink current between the ring node and a ground; anda second switch configurable, responsive to the first sink current, to form a second current path for a second sink current between the ring node and the ground.4. The ring amplitude adjustment circuit of claim 1 , wherein the switch driver includes:an amplifier coupled to the peak detector, wherein, responsive to the detected peak amplitude ...

HYSTERESIS CONTROL METHOD FOR INVERTER AND AN INVERTER WITH HYSTERESIS CONTROL

A hysteresis control method for inverter and an inverter based on hysteresis control are disclosed. The inverter is electrically connected to a power grid, and the method includes: Step S, sampling a grid voltage V(z) and an output current I(z) of the inverter; Step S, calculating a present period hysteresis bandwidth H(z) based on the grid voltage V(z) sampled in step S; Step S, predicting a next period hysteresis bandwidth H(z+1); Step S, correcting the present period hysteresis bandwidth H(z) based on the next period hysteresis bandwidth H(z+1) obtained in step S, to obtain a final hysteresis bandwidth H(z); and Step S, controlling an output driving signal according to the output current I(z) of the inverter and the final hysteresis bandwidth H(z) to control the operation of the inverter. 1. A hysteresis control method for an inverter electrically connected to a power grid , comprising:{'b': '1', 'sub': g', 'g, 'Step S, sampling a grid voltage V(z) and an output current I(z) of the inverter;'}{'b': 2', '1, 'sub': 'g', 'Step S, calculating a present period hysteresis bandwidth H(z) based on the grid voltage V(z) sampled in step S;'}{'b': '3', 'Step S, predicting a next period hysteresis bandwidth H(z+1);'}{'b': 4', '3, 'sub': 'out', 'Step S, correcting the present period hysteresis bandwidth H(z) according to the next period hysteresis bandwidth H(z+1) obtained in step S, to obtain a final hysteresis bandwidth H(z);'}{'b': '5', 'sub': g', 'out, 'Step S, outputting a driving signal according to the output current I(z) and the final hysteresis bandwidth H(z), to control an operation of the inverter.'}23. The hysteresis control method according to claim 1 , wherein the Step further comprising:{'sub': g', 'g, 'predicting a next period grid voltage V(z+1) online, and calculating the next period hysteresis bandwidth H(z+1) based on the next period grid voltage V(z+1).'}33. The hysteresis control method according to claim 1 , wherein the Step further comprising: ...

ANALOG-TO-DIGITAL CONVERTER WITH HYSTERESIS

A circuit includes an analog-to-digital converter (ADC) and a hysteresis circuit. The ADC is configured to generate a series of digital codes. The hysteresis circuit is configured to: (a) determine that a first digital code of the series of digital codes represents a change in a same direction as previous digital codes and store the first digital code in the register; and (b) determine that a second digital code of the series of digital codes represents a change in direction from previous digital codes, determine that the second digital code is less than a hysteresis value different than a preceding digital code, and not store the second digital code in the register. 1. A circuit , comprising:an analog-to-digital converter (ADC) having an ADC output;a direction detection circuit having a direction detection circuit input and a first direction detection circuit output, the first direction detection circuit input coupled to the ADC output;an adder having first and second adder inputs and an adder output, the first adder input coupled to the first direction detection circuit output, and the second adder input coupled to a hysteresis storage element;a first latch having a first latch input and a first latch output, the first latch input coupled to the adder output; anda first comparator having first and second comparator inputs, the first comparator input coupled to the ADC output, and the second comparator input coupled to the first latch output.2. The circuit of claim 1 , further comprising:a multiplexer coupled to the first comparator; anda register coupled to the multiplexer.3. The circuit of claim 1 , wherein the first latch has a first clock input claim 1 , and the circuit further comprises:a positive edge detect circuit having a positive edge detect input and a positive edge detect output;a first logic gate having a first logic gate input and a first logic gate output, the first logic gate input is coupled to the positive edge detect output, and the first logic ...

SEMICONDUCTOR DEVICE

A hysteresis comparator that has a small circuit area and low power consumption is provided. A differential pair in the comparator is formed using transistors each including a back gate. The comparator is configured to apply an inverted signal of a logic value of an output signal of the comparator to the back gate of the transistor. That is, the threshold voltage of the transistor is controlled by the inverted signal. By the change of the threshold voltage, hysteresis can be added to an input comparison voltage. 1. A semiconductor device comprising:a first transistor;a second transistor;a third transistor;a first circuit;a second circuit;a first inverter circuit;a first constant current circuit; anda second constant current circuit,wherein the second transistor comprises a gate and a back gate,wherein each of the first transistor and the second transistor is an n-channel transistor,wherein the third transistor is a p-channel transistor,wherein the first circuit has a first terminal, a second terminal, and a third terminal,wherein the first circuit is configured to output a potential corresponding to current flowing through the first terminal and current flowing through the second terminal from the third terminal,wherein the second circuit has a fourth terminal and a fifth terminal,wherein the second circuit is configured to output one of two potentials from the fifth terminal in accordance with a potential applied to the fourth terminal,wherein the first constant current circuit is configured to make constant current flow from an input terminal of the first constant current circuit to an output terminal of the first constant current circuit,wherein the second constant current circuit is configured to make constant current flow from an input terminal of the second constant current circuit to an output terminal of the second constant current circuit,wherein one of a source and a drain of the first transistor is electrically connected to the first terminal,wherein the ...

VOLTAGE COMPARATOR

A voltage comparator () has a high switching speed and simplicity of design. It minimizes pulse-width distortion of input digital signals when functioning as a digital input buffer in high speed communications applications. In addition it provides a simple hysteresis circuit () that is easily tuneable with a reference current. The hysteresis circuit () is dependent on a reference current. This current may be chosen to have a proportionality to temperature, supply, or another selectable parameter, and may be programmable, in order to create the desired hysteresis performance. 2. The voltage comparator as claimed in claim 1 , wherein the final stage amplifier is biased by either the first stage amplifier or an intermediate stage amplifier between said first stage amplifier and final stage amplifier.3. The voltage comparator as claimed in claim 1 , wherein the final stage amplifier is biased by either the first stage amplifier or an intermediate stage amplifier between said first stage amplifier and final stage amplifier; and wherein the voltage comparator comprises two or more intermediate stage amplifiers.4. The voltage comparator as claimed in claim 1 , wherein the final stage amplifier is biased by either the first stage amplifier or an intermediate stage amplifier between said first stage amplifier and final stage amplifier; and in which an intermediate stage amplifier further comprises a bias current source coupled to its load switches.5. The voltage comparator as claimed in claim 1 , wherein the gate and drain of the first stage amplifier load switches are connected to equal current sources.6. The voltage comparator as claimed in claim 1 , wherein each switch is a PMOS device or an NMOS device.7. The voltage comparator as claimed in claim 1 , wherein the hysteresis circuit is biased by a current with a proportionality to an operating condition in order to control the behaviour of the hysteresis.8. The voltage comparator as claimed in claim 1 , wherein the ...

DEVICE FOR PROVIDING A POWER SUPPLY

A first terminal receives a first DC voltage. A switch selectively couples the first terminal to a second terminal providing an output. A control circuit selectively actuates the switch in response to a comparison of the first DC voltage to a second DC voltage. A low-dropout (LDO) linear voltage regulator, connected between the first and third terminals, operates to provide the second DC voltage from the first DC voltage. 1. A device , comprising:a first terminal configured to receive a first DC voltage;a switch configured to selectively couple the first terminal to a second terminal in order to deliver the first DC voltage to the second terminal;a control circuit configured to control actuation of the switch, the control circuit comprising a third terminal configured to receive a second DC voltage; anda low-dropout (LDO) linear voltage regulator connected between the first and third terminals and configured to provide the second DC voltage based on the first DC voltage;wherein the control circuit is further configured to compare the first DC voltage to the second DC voltage and control an open or closed state of the switch as a function of the result of the comparison.2. The device according to claim 1 , wherein the control circuit comprises a hysteresis comparator having a first input receiving the first DC voltage from the first terminal claim 1 , a second input receiving the second DC voltage from the third terminal claim 1 , and an output coupled to a control terminal of the switch.3. The device according to claim 1 , wherein claim 1 , in response to the first DC voltage increasing from a target value claim 1 , the LDO linear voltage regulator is configured to maintain the second DC voltage lower than or equal to a threshold voltage that is higher than the target value.4. The device according to claim 3 , wherein the threshold voltage is determined based on the target value.5. The device according to claim 3 , wherein the LDO linear voltage regulator comprises: ...

OSCILLATION CONTROL APPARATUS AND OSCILLATION APPARATUS

Provided is an oscillation apparatus and an oscillation control apparatus including a first control section that generates a first control signal that controls an oscillation frequency of an oscillator, based on a temperature detection result of a temperature detecting section; an encoder that generates a feedback signal; a second control section that generates a second control signal that controls the oscillation frequency of the oscillator, based on the temperature detection result of the temperature detecting section, an external input signal input from outside, and the feedback signal; an oscillation circuit that sets the oscillation frequency of the oscillator, based on the first control signal and the second control signal; and a reference voltage generating section that generates a reference voltage, wherein the encoder generates the feedback signal by comparing the second control signal and the reference voltage. 1. An oscillation control apparatus comprising:a first control section that generates a first control signal that controls an oscillation frequency of an oscillator, based on a temperature detection result of a temperature detecting section;an encoder that generates a feedback signal;a second control section that generates a second control signal that controls the oscillation frequency of the oscillator, based on the temperature detection result of the temperature detecting section, an external input signal input from outside, and the feedback signal;an oscillation circuit that sets the oscillation frequency of the oscillator, based on the first control signal and the second control signal; anda reference voltage generating section that generates a reference voltage, whereinthe encoder generates the feedback signal by comparing the second control signal and the reference voltage.2. The oscillation control apparatus according to claim 1 , whereinthe encoder outputs digital data indicating a difference between the reference voltage and the second ...

LOAD DRIVE DEVICE, SEMICONDUCTOR DEVICE, LOAD DRIVE SYSTEM AND VEHICLE

A driver IC () includes a pair of output terminals in each of a plurality of channels and in each of the channels, power is supplied from the pair of output terminals (OUT and OUT, OUT and OUT, OUT and OUT or OUT and OUT) to a load (M, M, M or M). In each of the channels, the pair of output terminals are adjacent to each other. 1. A load drive device which includes a pair of output terminals in each of a plurality of channels and in which in each of the channels , power can be supplied from the pair of output terminals to a load ,wherein in each of two or more channels included in the plurality of channels, the pair of output terminals are arranged adjacent to each other.2. The load drive device according to claim 1 ,wherein in two target channels which are included in the two or more channels and in which the corresponding output terminals are provided on a same surface of a housing of the load drive device, between a pair of output terminals forming one of the target channels and a pair of output terminals forming the other target channel, one or more terminals different from the output terminals are arranged.3. The load drive device according to claim 2 , comprising:one or more first power supply terminals which receive supply of a first voltage;one or more second power supply terminals which receive supply of a second voltage different from the first voltage;a ground terminal which is kept at a predetermined reference potential;a plurality of external connection terminals which are connected to an external device for the load drive device; anda separate terminal which is different from the first power supply terminal, the second power supply terminal, the ground terminal and the external connection terminals,wherein in each of the channels, power based on the first voltage is supplied from the pair of output terminals to the load,the second voltage itself or a signal based on the second voltage is applied to the external connection terminals,on the same surface, ...

WIDE COMMON MODE HIGH RESOLUTION COMPARATOR

A comparator. The comparator includes two back-to-back inverters, a differential pair, and a first common mode compensation transistor. The differential pair has two outputs configured to receive respective series currents from, or supply respective series currents to, the back-to-back inverters. The first common mode compensation transistor is configured to supply a compensating current to, or draw a compensating current from, a first output of the two outputs of the differential pair. 1. A comparator , comprising: a first input, connected to a control terminal of the first transistor,', 'a second input connected to a control terminal of the second transistor,', 'a first output connected to a main terminal of the first transistor,', 'a second output connected to a main terminal of the second transistor, and', 'a common node,, 'a differential pair comprising a first transistor and a second transistor and havinga clock enabling transistor, connected to the common node of the differential pair, an input,', 'an output,', 'a first series path terminal, and', 'a second series path terminal,, 'a first inverter having an input,', 'an output,', 'a first series path terminal, and', 'a second series path terminal,, 'a second inverter havinga first common mode compensation transistor, anda second common mode compensation transistor,the input of the first inverter being connected to the output of the second inverter,the input of the second inverter being connected to the output of the first inverter,the second series path terminal of the first inverter being connected to the first output of the differential pair,the second series path terminal of the second inverter being connected to the second output of the differential pair,the first common mode compensation transistor being connected between a first voltage source and the first output of the differential pair,the second common mode compensation transistor being connected between the first voltage source and the second ...

Modulators

This application relates to time-encoding modulators ( 301,700 ) having a self-oscillating modulator module configured to receive an input signal and output a pulse-width modulated signal (S PWM ) where the pulse-width modulated signal is synchronised to a first clock signal (CLK 1 ). A hysteretic comparator module (302) located in a feedforward path is configured to generate the time encoded signal (S PWM ) at a first node ( 304 ) based on the input signal (S IN ) and a feedback signal (S FB ). A feedback path is coupled to the first node to provide the feedback signal, which is either applied to an input of the hysteretic comparator module via a loop filter ( 701 ) in the feedback path or applied to the feedforward path prior to a loop filter ( 202 ) upstream of the hysteretic comparator module ( 302 ). The hysteretic comparator module ( 302 ) is configured such that any change in state of the time encoded signal at the first node is synchronised to the first clock signal (CLK 1 ).

AMPLIFYING CIRCUIT

An amplifying circuit according to an embodiment includes a sample and hold circuit, an operational amplifier, a feedback capacitance, and a level shift circuit. The sample and hold circuit includes a sampling capacitance to sample an analog input signal in a sampling phase. The operational amplifier amplifies and outputs the analog input signal held by the sampling capacitance in the amplifying phase. The feedback capacitance is connected between the input terminal of the operational amplifier and the analog output terminal. The level shift circuit includes a level shift capacitance to sample the analog input signal in the sampling phase. A plurality of level shift capacitances is provided and connected in cascade between the output terminal of the operational amplifier and the analog output terminal. 1. An amplifying circuit , comprising:an analog input terminal to receive an analog input signal;an analog output terminal to output an analog output signal;a sample and hold circuit including a sampling capacitance to sample the analog input signal in a sampling phase and to hold the sampled signal in an amplifying phase, and a plurality of switches, each switching between the sampling phase and the amplifying phase;an operational amplifier including an input terminal connected to the sample and hold circuit, an output terminal, the operational amplifier amplifying and outputting the analog input signal held by the sampling capacitance in the amplifying phase;a feedback capacitance connected between the input terminal of the operational amplifier and the analog output terminal; anda level shift circuit including at least one level shift capacitance to sample the analog input signal in the sampling phase and to hold the sampled analog input signal in the amplifying phase, and a plurality of switches, each switching between the sampling phase and the amplifying phase, whereinthe at least one level shift capacitance comprises a plurality of level shift capacitances ...

CELL OF TRANSMISSION GATE FREE CIRCUIT AND INTEGRATED CIRCUIT LAYOUT INCLUDING THE SAME

A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings. 1. A semiconductor standard cell , comprising:a plurality of fins extending along a first direction;a plurality of gate electrodes, each of the plurality of gate electrodes disposed over at least one of the plurality fins, wherein the plurality of gate electrodes extend along a second direction substantially perpendicular to the first direction;a plurality of wirings extending along the second direction disposed over the fins and gate electrodes; anda plurality of transistors made of the fins and the gate electrodes configured to receive a data input signal, store the data input signal, and output a data output signal indicative of the stored data in response to a clock signal,wherein only one of the plurality of wirings receives the clock signal.2. The semiconductor standard cell of claim 1 , wherein the plurality of gate electrodes include a first gate electrode continuously extending across two or more of the semiconductor fins.3. The semiconductor standard cell of claim 2 , wherein one or ...

ADJUSTABLE OVER-CURRENT DETECTOR CIRCUIT FOR UNIVERSAL SERIAL BUS (USB) DEVICES

A current detector circuit includes a current sense amplifier, coupled to a sense resistor, to receive a pair of input voltages and to output a first indicator signal responsive to a sensed input voltage difference produced by a sensed current passing through the sense resistor. The current detector circuit includes a comparator coupled to the current sense amplifier, the comparator to compare the first indicator signal to a reference voltage signal and output an interrupt signal responsive to the first indicator signal exceeding the reference voltage signal; and a reference voltage generator circuit coupled to the comparator, the reference voltage generator circuit to select the reference voltage signal from a plurality of reference voltages according to a first selector signal received from a configuration channel of a serial bus connector device. 1. A current detector circuit , comprising:a current sense amplifier, coupled to a sense resistor, to receive a pair of input voltages and to output a first indicator signal responsive to a sensed input voltage difference produced by a sensed current passing through the sense resistor;a comparator coupled to the current sense amplifier, the comparator to compare the first indicator signal to a reference voltage signal and output an interrupt signal responsive to the first indicator signal exceeding the reference voltage signal; anda reference voltage generator circuit coupled to the comparator, the reference voltage generator circuit to select the reference voltage signal from a plurality of preset reference voltages according to a first selector signal received from a configuration channel of a serial bus connector device.2. The current detector circuit of claim 1 , wherein the comparator is further to provide an output signal to continuously track the sensed input voltage difference versus a voltage of the reference voltage signal.3. The current detector circuit of claim 2 , further comprising an analog-to-digital ...

MINIMUM PULSE-WIDTH ASSURANCE

Various methods and devices that involve pulsed signals are disclosed. An example minimum pulse-width (MPW) circuit comprises a first and second logic circuit. A first input of the first logic circuit is connected to an input of the MPW circuit. A first input of the second logic circuit is communicatively coupled to an output of the first logic circuit. The MPW circuit also comprises a MPW filter circuit communicatively coupled to an output of the second logic circuit, a one-shot circuit communicatively coupled to an output of the minimum pulse-width filter circuit and located on a first feedback path, and another one-shot circuit communicatively coupled to the output of the minimum pulse-width filter circuit and located on a second feedback path. A second input of the first logic circuit is on the first feedback path. A second input of the second logic circuit is on the second feedback path. 1. A method for assuring a minimum pulse-width using a minimum pulse-width assurance circuit , the method comprising:receiving a first signal at a first input of a first logic circuit, wherein the first input of the first logic circuit is coupled to an input of the minimum pulse-width assurance circuit;receiving, at a second input of the first logic circuit, a second signal from a first one-shot circuit;receiving, at a first input of a second logic circuit, a third signal from the first logic circuit, wherein the third signal is based on the first signal and the second signal;receiving, at a second input of the second logic circuit, a fourth signal from a second one-shot circuit;receiving, at an input of a minimum pulse-width filter circuit, a fifth signal from the second logic circuit, wherein the fifth signal is based on the third signal and the fourth signal, and wherein an output of the minimum pulse-width filter circuit is communicatively coupled to an output of the minimum pulse-width assurance circuit;receiving, at an input of the first one-shot circuit and at an input ...

HIGH VOLTAGE POWER SYSTEM WITH ENABLE CONTROL

Disclosed is a high voltage power system with enable control, comprising a high voltage start-up circuit, a PWM control module, and a driving module; the high voltage start-up circuit comprises a first transistor, a third transistor, a fourth transistor, a resistor, a diode, a VDD detection unit and an I/O interface unit; the high voltage start-up circuit is controlled by an input of a pin EN; when the pin EN is set, the high voltage start-up circuit stops working; the power system is shut off and doesn't restart, and enters a zero standby state; when the pin EN is reset, the high voltage start-up circuit restores to work, and the power system restarts and enters a normal working state. The power system having the high voltage start-up circuit with enable control has characteristics that the standby input power consumption and standby input current are both close to zero. 1. A high voltage power system with enable control , comprising:{'b': '1', 'a high voltage start-up circuit ();'}{'b': '2', 'a PWM control module (); and'}{'b': '3', 'a driving module ();'}{'b': '1', 'claim-text': [{'b': '1', 'a first transistor (M),'}, {'b': '3', 'a third transistor (M),'}, {'b': '4', 'a fourth transistor (M),'}, {'b': '1', 'a resistor (R),'}, {'b': '1', 'a diode (D),'}, {'b': '101', 'a VDD detection unit () and'}, {'b': '102', 'an I/O interface unit ();'}], 'wherein the high voltage start-up circuit () comprises{'b': 1', '1, 'wherein a drain of the first transistor (M) is connected with a first end of the resistor (R) and with a pin HV;'}{'b': 1', '1', '1', '3', '4, 'wherein a gate of the first transistor (M) is connected with a second end of the resistor (R), a cathode of the diode (D), a drain of the third transistor (M) and a drain of the fourth transistor (M);'}{'b': 1', '101', '1, 'wherein a source of the first transistor (M) is connected with an input end of the VDD detection unit (), a pin VDD and a capacitor C connected with the pin VDD;'}{'b': 1', '3', '4, 'wherein an ...

ENHANCEMENT MODE FET GATE DRIVER IC

A fully integrated GaN driver comprising a digital logic signal inverter, a level shifter circuit, a UVLO circuit, an output buffer stage, and (optionally) a FET to be driven, all integrated in a single package. The level shifter circuit converts a ground reference 0-5 V digital signal at the input to a 0-10 V digital signal at the output. The output drive circuitry includes a high side GaN FET that is inverted compared to the low side GaN FET. The inverted high side GaN FET allows switch operation, rather than a source follower topology, thus providing a digital voltage to control the main FET being driven by the circuit. 1. An integrated gate driver circuit for driving an enhancement mode GaN field effect transistor , comprising the following elements fully integrated in a single chip: a logic inverter circuit;', 'a level shifter circuit having an input and an output, the level shifter circuit converting a ground reference 0-5 V digital signal at the input to a 0-10 V digital signal at the output; and', 'an output stage for driving an FET; and, 'a gate driver, comprising a voltage reference circuit for generating a predetermined voltage reference; and', 'a comparator for receiving the output of the voltage reference circuit and for preventing operation of the gate driver if the supply voltage falls below said predetermined voltage reference., 'an undervoltage lockout circuit connected to the gate driver, comprising2. The integrated gate driver circuit of claim 1 , wherein all transistors in the circuit are enhancement mode GaN field-effect transistors.3. The integrated gate driver circuit of claim 2 , further comprising the enhancement mode GaN field-effect transistor to be driven.4. The integrated gate driver circuit of claim 1 , wherein the output stage comprises a half bridge circuit formed of a high side enhancement mode GaN transistor and a low side enhancement mode GaN transistor claim 1 , with the high side enhancement mode GaN transistor inverted relative ...

SYSTEMS AND METHODS FOR HARNESSING ANALOG NOISE IN EFFICIENT OPTIMIZATION PROBLEM ACCELERATORS

Systems and methods are provided for implementing a hardware accelerator. The hardware accelerator emulates a neural network, and includes a memristor crossbar array, and a non-linear filter. The memristor crossbar array can be programmed to calculate node values of the neural network. The nodes values can be calculated in accordance with rules to reduce an energy function associated with the neural network. The non-linear filter is coupled to the memristor crossbar array and programmed to harness noise signals that may be present in analog circuitry of the hardware accelerator. The noise signals can be harnessed such that the energy function associated with the neural network converges towards a global minimum and modifies the calculated node values. In some embodiments, the non-liner filter is implemented as a Schmidt trigger comparator. 1. A circuit , comprising:an array of analog elements programmed to calculate node values of a neural network, wherein the nodes values are output by the array of analog elements and calculated in accordance with rules to reduce an energy function associated with the neural network; anda circuit element coupled to the array of analog elements, the circuit element programmed to permit a noise signal to effect the calculated node values such that the energy function associated with the neural network converges towards a global minimum and modifies the calculated node values output by the array of analog elements.2. The circuit of claim 1 , wherein the circuit element comprises a Schmidt trigger comparator programmed to permit the noise signal to effect the calculated node values output by the array of analog elements in accordance with a tolerance to an amount of the noise signal for triggering a modification to the calculated node values.3. The circuit of claim 2 , wherein the Schmidt trigger comparator is programmed to permit the noise signals to effect the calculated node values output by the array of analog elements such that ...

Fast pre-amp latch comparator

A fast latched comparator may include an amplifier portion and a latch portion. A switch activated by a reset pulse may short together outputs of the latched comparator.

Non-Oscillating Comparator

A method for controlling operation of a comparator that includes an amplifier that is connected at an input of the comparator includes neutralizing any change of state of a signal output by the comparator starting from each moment in time at which the change of state of the output signal occurs and lasting for a duration of propagation to compensate for a duration of propagation of signals within the amplifier. 1. A method for controlling operation of a comparator that includes an amplifier that is connected at an input of the comparator , the method comprising:neutralizing any change of state of a signal output by the comparator starting from each moment in time at which the change of state of the output signal occurs and lasting for a second duration of propagation to compensate for a duration of propagation of signals within the amplifier.2. The method according to claim 1 , wherein the second duration of propagation is equal to the duration of propagation of signals within the amplifier.3. The method according to claim 1 , wherein the second duration of propagation is equal to a first duration of propagation that is equal to a duration of propagation of signals within the comparator to within a certain tolerance.4. The method according to claim 3 , wherein the certain tolerance is between 0 and 5%.5. The method according to claim 1 , wherein the signal output by the comparator has a frequency that is higher than 200 MHz.6. The method according to claim 1 , wherein neutralizing any change of state of the signal output by the comparator comprises delaying arrival of an instruction to change state at the input of the comparator.7. A method of operating a comparison circuit claim 1 , the method comprising:outputting an output signal at an output terminal of the comparison circuit;receiving an input signal at an input terminal of a first amplifier of the comparison circuit;propagating the input signal through the first amplifier during a first propagation duration; ...

Periodic Kick-Starter For A Crystal Oscillator

A cyclical pulsing oscillator having a pulse repetition rate close to a crystal resonant frequency in an oscillator provides more useful start-up energy to the crystal oscillator circuit and thus provides much faster start-up time. The start-up pulsing oscillator runs for a number of cycles or until the crystal oscillator amplitude as built up to a desired value. The pulsing oscillator may have a repetition rate of from about one-third to about one-half the crystal resonant frequency, thus providing more useful start-up energy to the crystal oscillator circuit. 1. An integrated oscillator configured to be coupled with an external crystal , comprising:an oscillator circuit coupled with the external crystal; anda start-up circuit comprising a kick-start pulser coupled to the oscillator circuit and pulsing start-up energy thereto.2. The integrated oscillator according to claim 1 , wherein the kick-start pulser comprises a current source charging a capacitor claim 1 , a discharging switch coupled in parallel with the capacitor wherein a node between the current source and the capacitor is coupled to an input of a comparator whose output controls the discharging switch claim 1 , and a pulsing switch controlled by the comparator and coupled to the oscillator circuit.3. The integrated oscillator according to claim 1 , wherein the comparator has hysteresis.4. The integrated oscillator according to claim 2 , further comprising a digital counter which disables the start-up circuit after a predetermined number of pulses generated by the start-up circuit.5. The integrated oscillator according to claim 4 , wherein the predetermined number of pulses is from about 16 to about 32 pulses.6. The integrated oscillator according to claim 4 , wherein the predetermined number of pulses is from about 32 to about 64 pulses.7. The integrated oscillator according to claim 1 , wherein a frequency of the kick-start pulser is from about one-third to about one-half of a center frequency of the ...

Double Data Rate Interpolating Analog to Digital Converter

A double data rate comparator includes a double data rate comparator core, the comparator core configured to compare a voltage of an input signal to a reference signal during each of a rising edge and a falling edge in a single clock cycle of a clock input to the comparator core, and a double data rate set-reset flip flop circuit, the set-reset flip flop circuit comprising a set input and a reset input connected to respective outputs of the double data rate comparator core, the set-reset flip flop circuit configured to perform a set-reset operation during the rising edge in the single clock cycle and the falling edge in the single clock cycle. 1. A double data rate comparator device , comprising:{'sub': 'N', 'a double data rate comparator core configured to compare a voltage of an input signal (IN) to a reference signal (REF) during each of a rising edge and a falling edge in a single clock cycle of a clock input (CLK) to the double data rate comparator core; and'} a set input (S); and', {'sub': N', 'N, 'a reset input (R) connected to respective outputs (P, M) of the double data rate comparator core.'}], 'a double data rate set-reset flip flop circuit configured to perform a set-reset operation during the rising edge in the single clock cycle and the falling edge in the single clock cycle, wherein the double data rate set-reset flip flop circuit comprises2. The double data rate comparator device according to claim 1 , wherein the double data rate comparator core comprises a p-type metal-oxide-semiconductor (PMOS) differential amplifier stage and an n-type metal-oxide-semiconductor (NMOS) differential amplifier stage connected together in a push-pull configuration.3. The double data rate comparator device according to claim 2 , wherein the double data rate comparator core further comprises:a first node (DM) connecting a first drain of the PMOS differential amplifier stage to a first drain of the NMOS differential amplifier stage; anda second node (DP) connecting a ...

FUSE ARRAY AND MEMORY DEVICE

A fuse array and a memory device are provided in the invention. The fuse array includes a plurality of fuses and a plurality of first D flip-flops. The fuses are configured to generate a plurality of data signals. Each of the first D flip-flops is respectively coupled to one corresponding fuse of the fuses to receive the data signal from the corresponding fuse and the first D flip-flops transmit a clock signal and the data signal to a plurality of second D flip-flops comprised in a plurality of memory cells. The first D flip-flops are connected in series and the second D flip-flops are connected in series. 1. A fuse array , comprising:a plurality of fuses, generating a plurality of data signals; anda plurality of first D flip-flops, respectively coupled to a corresponding fuse of the fuses to receive the data signals generated by the corresponding fuse, receiving a clock signal from a clock generator and transmitting the clock signal and the data signals to a plurality of second D flip-flops of a plurality of memory cells, wherein the first D flip-flops are connected in series and the second D flip-flops are connected in series.2. The fuse array of claim 1 , further comprising:a data line, configured to transmit the data signals from the first D flip-flops to the second D flip-flops; anda clock line, configured to provide the clock signal to the first D flip-flops and the second D flip-flops.3. The fuse array of claim 1 , wherein the fuse array is divided into a plurality of blocks claim 1 , and data corresponding to each of the blocks are processed at the same time.4. The fuse array of claim 3 , wherein each block comprises a different part of the fuses and each block is allocated a corresponding data line and a corresponding clock line.5. The fuse array of claim 1 , wherein the fuses are laser fuses or electronic fuses.6. A memory device claim 1 , comprisinga plurality of memory cells, wherein each of the memory cells comprises a memory array and a redundancy ...

Comparator System

A comparator system and a method for comparing an input signal and a reference signal are presented. The system has a controller to adjust a rising output delay and/or a falling output delay of a system output signal. The system output signal is dependent on the comparison between the input signal and the reference signal. This system provides a more efficient comparator with reduced power consumption whilst still providing the required rising output delay and falling output delay for a given application. Techniques used in prior art will always resort to running the comparators at a speed that supports the speed requirements in the worst case conditions and does not exploit any asymmetries in the required rising output delay and falling output delay for a given application. When these asymmetries are exploited, further increases in power efficiency can be achieved. 1. A comparator system for comparing an input signal and a reference signal , comprising:a controller configured to adjust a rising output delay and/or a falling output delay of a system output signal; wherein:the system output signal is dependent on the comparison between the input signal and the reference signal.2. The comparator system of claim 1 , wherein:the system output signal comprises a high state and a low state;the rising output delay comprises a rising delay time and a rise time;the falling output delay comprises a falling delay time and a fall time;the rising delay time is a time taken from the comparison between the input signal and the reference signal triggering a low-to-high transition of the system output signal from the low state to the high state until the low-to-high transition begins;the rise time is a time taken for the system output signal to transition from the low state to the high state from the beginning of the low-to-high transition;the falling delay time is a time taken from the comparison between the input signal and the reference signal triggering a high-to-low transition ...

LEVEL SHIFTER SYSTEM AND CAPACITIVE-COUPLED LEVEL SHIFTER

A capacitive-coupled level shifter includes a capacitive divider circuit having a first capacitive divider branch configured to couple a first input terminal to a first comparator terminal and a second capacitive divider branch configured to couple a second input terminal to a second comparator terminal. The first capacitive divider branch and the second capacitive divider branch are symmetric so as to cancel out a common mode voltage of a modulated signal input to the capacitive divider circuit. A level shifter system which includes the capacitive-coupled level shifter is also described. 1. A capacitive-coupled level shifter , comprising:a capacitive divider circuit comprising a first capacitive divider branch configured to couple a first input terminal to a first comparator terminal and a second capacitive divider branch configured to couple a second input terminal to a second comparator terminal,wherein the first capacitive divider branch and the second capacitive divider branch are symmetric so as to cancel out a common mode voltage of a modulated signal input to the capacitive divider circuit.2. The capacitive-coupled level shifter of claim 1 , a first capacitor configured to couple the first input terminal to the first comparator terminal;', 'a second capacitor configured to couple a voltage supply to the first comparator terminal; and', 'a third capacitor configured to couple a switched voltage node to the first comparator terminal,, 'wherein the first capacitive divider branch comprises a fourth capacitor configured to couple the second input terminal to the second comparator terminal;', 'a fifth capacitor configured to couple the voltage supply to the second comparator terminal; and, 'wherein the second capacitive divider branch comprisesa sixth capacitor configured to couple the switched voltage node to the second comparator terminal.3. The capacitive-coupled level shifter of claim 2 , further comprising a resistor ladder connected between the voltage ...

Square wave-to-sine wave converter

A circuit includes a bandpass filter and a self-tracking circuit. The bandpass filter has a first input node configured to receive an input square wave signal and an output node configured to provide an output sine wave signal. The bandpass filter includes a first binary-weighted programmable resistor array. The self-tracking circuit includes a second input node coupled to the output node. The self-tracking circuit includes a counter, and the counter includes an output node coupled to the first binary weighted programmable resistor array.

Electronic Fuse for a Power Supply

An electronic fuse for a power supply includes at least two switching elements and a regulation unit, wherein a first switching element is arranged in a main branch, where the regulation unit is switches off the first switching element when a predetermined threshold value is exceeded by a prevailing current value, and a second switching element that is also actuated by the regulation unit, which is arranged in an auxiliary branch parallel to the first switching element and assumes a substantial proportion of a resulting power loss when an overload occurs, and the second switching element, which is arranged in at least one auxiliary branch, is configured or optimized for linear operation, and where the at least two switching elements are configured such that the line resistance of the second switching element is at least twice the line resistance of the first switching element. 1. An electronic fuse for a power supply at least comprising:at least two switching elements, a first switching element of the at least two switching elements being arranged in a main branch via which a supply voltage is supplied to at least one output; anda regulation unit configured to switch a current of the first switching element when a predetermined threshold value is exceeded by a prevailing current value;wherein at least one second switching element, which is actuated by the regulation unit, is arranged in an auxiliary branch parallel to the first switching element and assumes a substantial proportion of a resulting power loss in the event of an overload, the first switching element and the at least second switching element being produced using different technology;wherein the at least second switching element is configured for linear operation; andwherein the at least two switching elements are configured such that a line resistance of the second switching element has at least twice the amount of a line resistance of the first switching element.2. The electronic fuse as claimed in ...

SWITCHING CIRCUIT WITH IMPROVED LINEARITY

A circuit including a switch and a level shift circuit is provided. The switch includes a control terminal and an input terminal. The input terminal is arranged to receive an input voltage, and the control terminal is arranged to receive a control voltage that controls a state of the switch. The level shift circuit includes a level-shifting input terminal and a level-shifting output terminal. The level-shifting input terminal is coupled to the input terminal for receiving the input voltage, and the level shift circuit is arranged to shift the input voltage to generate a shifted voltage on the level-shifting output terminal, and the control voltage is generated based on the shifted voltage. 1. A circuit , comprising:a switch including a control terminal and an input terminal, the input terminal being arranged to receive an input voltage and the control terminal being arranged to receive a control voltage that controls a state of the switch; anda level-shifting circuit including a level-shifting input terminal and a level-shifting output terminal, the level-shifting input terminal being coupled to the input terminal for receiving the input voltage, the level-shifting circuit being arranged to shift the input voltage for generating a shifted voltage at the level-shifting output terminal, and the control voltage being generated based on the shifted voltage.2. The circuit of claim 1 , wherein the switch comprises a Metal Oxide Semiconductor Field Effect Transistor (MOSFET).3. The circuit of claim 2 , wherein the control terminal is coupled to a gate of the MOSFET.4. The circuit of claim 2 , wherein the input terminal is coupled to a source of the MOSFET.5. The circuit of claim 1 , further comprising:a buffering circuit, coupled between the level-shifting output terminal and the control terminal, the buffering circuit arranged to receive the shifted voltage at the level-shifting output terminal, for generating the control voltage at the control terminal.6. The circuit of ...

CURRENT CONTROLLED AMPLIFIER

A circuit arrangement is disclosed for controlling the switching of a field effect transistor (FET). A current controlled amplifier may be configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET. A comparator may be coupled to the current sense amplifier to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off. 1. A method of current-controlled amplification , the method comprising:sensing, by a differential input of a modified Wilson current mirror, a current flowing through a sense resistance;sinking, by an output of the modified Wilson current mirror, a first output current that is an amplified version of the sensed current; andsourcing, by a first transistor coupled to the output of the modified Wilson current mirror, a current-controlled amplifier output current based on the first output current.2. The method of claim 1 , wherein the sensing the current flowing through the sense resistance uses a gain resistor that is coupled between the sense resistance and a negative input of the differential input of the modified Wilson current mirror.3. The method of claim 1 , further comprising compensating for a drift in a resistance of the sense resistance.4. The method of claim 3 , wherein the compensating includes using at least one of: a negative temperature coefficient (NTC) claim 3 , a positive temperature coefficient (PTC) claim 3 , or a PN junction.5. The method of claim 4 , wherein the compensating includes using the NTC in parallel with a first limit resistor.6. The method of claim 5 , wherein the compensating includes using the PTC in parallel with a second limit resistor.7. The method of claim 6 , wherein the first limit resistor claim 6 , the second limit resistor claim 6 , the NTC claim ...

COMPARATOR WITH NEGATIVE CAPACITANCE COMPENSATION

A high-speed comparator circuit is provided. The circuit includes an amplifier portion, a latch portion, and a negative capacitance portion. The amplifier portion includes an input coupled to receive an analog signal and an output. The latch portion is coupled to the amplifier portion. The latch portion is configured to provide at the output a digital value based on the analog signal. The negative capacitance portion is coupled to the output. The negative capacitance portion is configured to cancel parasitic capacitance coupled at the first output. 1. A circuit comprising:an amplifier portion having a first input coupled to receive a first analog signal and a first output;a latch portion coupled to the amplifier portion, the latch portion configured to provide at the first output a digital value based on the first analog signal; anda negative capacitance portion coupled to the first output, the negative capacitance portion configured to cancel parasitic capacitance coupled at the first output.2. The circuit of claim 1 , wherein the negative capacitance portion further comprises: a first transistor having a first current electrode coupled to the first output;a second transistor having a first current electrode coupled to a control electrode of the first transistor and a control electrode coupled to the first output; anda capacitor having a first terminal coupled to a second current electrode of the first transistor and a second terminal coupled to a second current electrode of the second transistor.3. The circuit of claim 2 , wherein the capacitor has a capacitance value substantially equal to the parasitic capacitance coupled at the first output.4. The circuit of claim 2 , wherein the negative capacitance portion further comprises:a first current source having a first terminal coupled to a first voltage supply terminal and a second terminal coupled to the second current electrode of the first transistor; anda second current source having a first terminal coupled to ...

온도 보상 히스테리시스를 갖는 비교기(a comparator with temperature-compensated hysteresis)

본 발명은 온도의 변화에 따라 변하지 않는 히스테리시스를 갖는 비교기에 관한 것으로, 본 발명의 비교기는 저항(R5)을 포함하고 입력 전압 신호를 그에 대응되는 출력 전류 신호로 변환하여 출력하는 전압-전류 변환부(5)와, 이 전압-전류 변환부(5)의 출력 전류 신호(Iref)에 상응하는 제 1 내지 제 4 정전류 신호들을 공급하는 정전류 공급부(10a)와, 입력 신호(Vin)의 크기와 기준 전압 신호(Vref)의 크기를 비교하고 그 결과에 대응되는 신호를 출력하는 신호 비교부(20)와, 저항(R1)올 포함하고 정전류 공급부(10a)의 출력 신호가 제공되는 것에 응답하여 상기 신호 비교부(20)의 출력 신호에 대응되는 히스테리시스 전압을 생성하는 히스테리시스 생성부(30)와, 이 히스테리시스 생성부(30)로부터의 히스테리시스 전압에 대응되는 신호를 출력하는 신호 출력부(40)와, 이 신호 출력부(40)의 출력 신호를 안정화시키는 신호 안정화부(50)으로 구성되어서, 히스테리시스 전압이 저항들(R1, R5)의 비에 의해 결정된다.

Oscillator based on jittering

PURPOSE: An oscillator of jittering mode is provided to obtain jitter effect on oscillator without an additional jitter generating circuit by adding a divider, a resistance, and a capacitor to a basic fixed frequency oscillator. CONSTITUTION: A current source(101) comprises an integrator(100). A capacitor(102) charges the current flowing out from the current source. Two comparators(121, 122) transmits output by comparing the output of integrator with the reference voltage. A latch(123) transmits the final output according to the outputs of the two comparators. A divider(124) divides the final output to 1/N.

Voltage comparing circuit with hysteresis characteristic

내용 없음. No content.

コンパレ−タ回路

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Oscillator and method of driving the same

본 발명은 정밀도가 높은 주파수의 클럭 신호를 생성할 수 있는 오실레이터 및 그 구동 방법에 관한 것으로, 일 측면에 따른 오실레이터는 제1 정전류를 이용하여 클럭 신호에 따라 제1 오실레이션 신호를 생성하고, 제2 정전류를 이용하여 반전 클럭 신호에 따라 제2 오실레이션 신호를 생성하는 충방전 회로; 비교 레퍼런스 전압을 기준으로 한 제1 오실레이션 신호의 변화량이 반영된 제1 비교 전압과, 비교 레퍼런스 전압을 기준으로 한 제2 오실레이션 신호의 변화량이 반영된 제2 비교 전압을 생성하는 적분회로; 및 제1 오실레이션 신호와 제1 비교 전압의 비교 결과와, 제2 오실레이션 신호와 제2 비교 전압의 비교 결과에 따라 클럭 신호 및 반전 클럭 신호를 생성하는 비교 회로를 포함할 수 있다.

Buffer circuit, clock dividing circuit and semiconductor device using the same

버퍼 회로는 증폭 회로, 래치 회로, 제 1 가변 로드, 제 2 가변 로드 및 리셋 회로를 포함할 수 있다. 상기 증폭 회로는 제 1 입력 신호 및 제 2 입력 신호에 기초하여 제 1 출력 노드 및 제 2 출력 노드의 전압 레벨을 제 1 전원전압 및 제 2 전원전압 사이에서 변화시킬 수 있다. 상기 래치 회로는 상기 제 1 및 제 2 출력 노드의 전압 레벨을 래치할 수 있다. 상기 제 1 가변 로드는 리셋 신호에 기초하여 상기 제 1 전원전압 단자로부터 상기 제 1 출력 노드로 공급되는 전류의 양을 조절할 수 있다. 상기 제 2 가변 로드는 상기 리셋 신호에 기초하여 상기 제 1 전원전압 단자로부터 상기 제 2 출력 노드로 공급되는 전류의 양을 조절할 수 있다. 상기 리셋 회로는 상기 리셋 신호에 기초하여 상기 제 1 출력 노드를 상기 제 2 전원전압으로 구동할 수 있다. The buffer circuit may include an amplifier circuit, a latch circuit, a first variable load, a second variable load, and a reset circuit. The amplification circuit may change the voltage levels of the first output node and the second output node between the first power voltage and the second power voltage based on the first input signal and the second input signal. The latch circuit may latch voltage levels of the first and second output nodes. The first variable load may adjust an amount of current supplied from the first power voltage terminal to the first output node based on a reset signal. The second variable load may adjust an amount of current supplied from the first power voltage terminal to the second output node based on the reset signal. The reset circuit may drive the first output node to the second power voltage based on the reset signal.

Electronic switch assembly

A piezoelectric switch assembly and method of manufacture. A piezoelectric module is provided which is comprised of a carrier disk and a wafer of piezoelectric material disposed thereon, with electrical leads connected thereto. The piezoelectric module is disposed inside a hollow recess formed in a switch plug, with the periphery of the carrier disk supported on a rim thereof. A disk of compressible material is disposed between the body of the plug and the piezoelectric module. The switch plug is inserted into a hollow chamber formed in a switch insert, said switch insert having a pressure receiving front wall. A front member is provided which is formed with an aperture for receiving the switch insert. Pressure on the pressure receiving front wall of the socket causes deformation of the piezoelectric wafer to generate an electrical signal which is received by circuitry attached to the electrical leads to effect one or more preselected switch functions.

Comparator circuit and infrared signal receiver

Asymmetric hysteretic controller

一种非对称滞后控制器包括与快速变动速率DAC耦合的模拟比较器，或与ADC加上某一数字控制逻辑耦合的数字比较器。所述模拟或数字比较器操作为具有上限及下限的顺序窗口化比较器。将感测参数与上限或下限进行比较，且当所述感测参数达到所述选定上限或下限时，分别地将受控装置关断或接通。当滞后控制器状态比较反转发生时：(a)比较器输出可被所述控制逻辑消隐，(b)比较器极性可被所述控制逻辑反转，(c)所述控制逻辑可命令选择另一过程极限以用于与所述感测参数进行比较，以及(d)接着可重新启用所述比较器输出。

Asymmetric hysteretic controllers

비대칭 히스테리시스 컨트롤러는 고 슬루레이트 DAC와 결합된 아날로그 비교기 또는 ADC와 결합된 디지털 비교기, 그리고 몇몇의 디지털 제어 로직을 포함한다. 아날로그 또는 디지털 비교기는 상한 및 하한을 구비한 순차 윈도우 비교기로서 동작한다. 감지 파라미터는 상한 또는 하한과 비교되고, 감지 파라미터가 선택된 상한 또는 하한에 도달할 때에는 피제어 디바이스가 각각 턴 오프 또는 턴 온 된다. 히스테리시스 컨트롤러 상태 비교 반전이 발생할 때에는: (a) 비교기 출력이 제어 로직에 의해 블랭킹될 수 있고, (b) 비교기 극성이 제어 로직에 의해 반전될 수 있고, (c) 제어 로직은 감지 파라미터와 비교하기 위해 나머지 프로세스 한계값이 선택되도록 명령할 수 있으며, 그리고 (d) 비교기 출력은 다시 인에이블될 수 있다.

Patent JPS6356723B2