Schaltung zur Detektion von phasenumgetasteten Impulsen

CMOS-Klemmschaltungen

Noise suppressor and pulse shaper - has inverter between input differentiator and output integrator to compensate for noise

The pulse shaper suppresses noise and shapes pulses (Trigger and signal pulses) used in motor vehicle diagnostic equipment and does so with few components and a relatively high input impedance. The input signal, e.g. from an ignition coil (10) and breaker (11), passes over an input circuit (13, 15) to a differentiator (22, 23). The differentiator is coupled to an inverter (20) that produces a signal to compensate for noise and passes it to an integrator (17) at the output of the pulse shaper. The differentiator is coupled via a diode (25) to a capacitor (24) connected in parallel with the input circuit.

GEBER UND VERFAHREN ZUR ERZEUGUNG EINES DYNAMISCHEN GERAEUSCHGRENZNIVEAUS

Schaltungsanordnung zur Begrenzung der Ausgangsspannung einer logischen Schaltung

HALBLEITERVORRICHTUNG UND SCHALTUNGSSCHUTZVERFAHREN

Eine Halbleitervorrichtung umfasst einen ersten Transistor und eine Klemmschaltung. Der erste Transistor ist dazu eingerichtet, ein Ausgangssignal gemäß einem Steuersignal zu erzeugen. Die Klemmschaltung ist dazu eingerichtet, das Steuersignal gemäß einem Eingangssignal zu erzeugen, und das Steuersignal an einen vorherbestimmten Signalpegel zu klemmen, wenn das Eingangssignal den vorherbestimmten Signalpegel übersteigt.

TRIGGERSCHALTUNG

SCHALTUNGSANORDNUNG ZUR BEREITSTELLUNG EINES AUSGANGSSIGNALS MIT EINSTELLBARER FLANKENSTEILHEIT

Protection circuit for analog and digital signals

A protection circuit for analog or digital signals which are applied to the input of an electrically controlled apparatus, having two transistors (T1, T2) of mutually opposite polarity, which are connected in series with one another and whose emitters, which are connected to one another, are connected via a bias resistor (Rv) to the signal voltage, and having a voltage divider which is connected across the operating voltage (UB) or a limiting voltage (Ulimit) and consists of a first resistor (R1), a second resistor (R2) and a third resistor (R3), the bases of the transistors being connected in a crossed over manner to the connecting points of these resistors (Figure 1). …… ...

REGEESCHALTUNG FUER IMPULSENDSTUFEN, INSBESONDERE FUER IN BRUECKENSCHALTUNG BETRIEBENE TRANSISTORPULSSTELLER FUER KLEINANTRIEBE

Variable frequency AC converter - has differential amplifier voltage divider to convert AC signals of variable frequency and amplitude into rectangular pulses

The converter has a differential amplifier (15) connected by two inputs via two oppositely poled diodes (13, 19) and a shared d.c.-coupling capacitor (12) to the single input (10). A four-resistor voltage divider (R1-R4) is connected between the supply poles and has the first tapping connected to the inverting input. The second (middle) tapping is connected to ground, and the third tapping is connected to the non-inverting input. The rectangular pulses appear at the output of the amplifier. The voltage divider defines thresholds. The advantage lies in few components and in eliminating noise signals whose amplitude is insufficient to forward bias the diodes. The a.c. voltage signals can corresponds to Korotkov signals derived by amplified signals from a microphone applied to a part of the body. Systolic and diastolic blood pressure values are ascertained from the converted rectangular pulses.

Schaltungsanordnung zur Mittelwertbildung

Schaltungsanordnung zur Bestimmung des Mittelwerts eines Eingangssignals (s), mit einem Signaleingang (1) zur Aufnahme des Eingangssignals (s) und einem Signalausgang (13) zur Ausgabe eines den Mittelwert des Eingangssignals (s) wiedergebenden Ausgangssignals (g). Es wird vorgeschlagen, dass zwischen dem Signaleingang (1) und dem Signalausgang (13) zur Mittelwertbildung ein Zähler (10) angeordnet ist, der vorzugsweise von einem Sigma-Delta-Modulator (2) angesteuert wird.

STRAMPELSACK FUER KLEINKINDER.

GETASTETER LESERVERSTAERKER

IMPULSUEBERTRAGUNGSSCHALTUNG MIT AUSGLEICH VON SIGNALAMPLITUDENVERLUSTEN

Circuit arrangement for limiting the output voltage of a logical circuit

... 1,119,310. Transistor limiter circuits. PHILIPS ELECTRONICS & ASSOCIATED INDUSTRIES Ltd. 26 June, 1967 [29 June, 1966], No. 29401/67. Heading H3T. The output of an amplifier is limited to a potential equal to the base-emitter potential of a transistor, the collector of which is connected to provide negative feedback to the amplifier. The output from OR circuit T1, T2, T3 is fed to a push-pull amplifier comprising field-effect transistors F1, F2 and NPN transistors T4, T5. The base-emitter diodes of transistors T6, T7 limit the output U, and further stabilization of the output is provided by the negative feedback from their collectors to the source electrodes of F1, F2.

Controllable limiter

A limiter for limiting an input signal includes a first clamping circuit for clamping the input signal at a first level so that the input signal cannot rise substantially above such first level, a second clamping circuit for clamping the input signal at a second level less than the first level so that the input signal cannot drop substantially below such second level and a single operational amplifier having an input which receives the clamped input signal and an output at which is developed an output signal that is a scaled version of the clamped input signal. The limiter may be used as either a static or dynamic limiter, is simple in design, inexpensive, and can be used in a wide variety of applications.

Digital modulation signal reading device

A data reading device for reading out data modulated according to a system wherein the time ratio of low to high level signals is substantially unity employs a time ratio detector and an intermediate level detector. A comparator compares the reproduced output level with a synthesized signal which may represent a combination of the outputs of the time ratio detector and the intermediate level detector.

Improvement process for the preparation of Ethylene Oxide

... 1,052,800. Oxidation catalysts. DOW CHEMICAL CO. March 12, 1964 [March 22, 1963], No. 10465/64. Heading B1E. [Also in Divisions C2 and C7] An oxidation catalyst comprises silver and 160-400 parts of lead per million parts by weight of silver calculated as silver oxide. The catalyst is carried on a conventional support, e.g. porous alumina. The catalyst may be prepared by wetting a porous carrier with an aqueous glycol solution, adding a reducible silver compound which contains the required amount of lead and heating the mixture until the silver compound is reduced. Promoters, e.g. alkali metal and alkaline earth metal oxides and carbonates, and noble metal oxides, may be added to the catalyst.

VOLTAGE CLIPPER CIRCUITS

... 1,255,103. Amplitude limiters. SOC. NATIONALE D'ETUDE ET DE CONSTRUCTION DE MOTEURS D'AVIATION. 3 July, 1969 [5 July, 1968], No. 33541/69. Heading H3T. In an amplitude limiter for a square wave signal 2(a) supplied at 1, the signal is added at S1 to a reference wave 2(b) of opposite source applied at 2 so that a combined wave 2(c) is produced which decreases as the signal amplitude increases. This wave is added in S2 to a second reference wave of the opposite phase so that normally the original wave is restored 2(e) but when the signal falls through zero the path for the combined wave is blocked at K and the output (from 4) remains constant at the level of the second reference wave. The level of the reference waves may be varied, as shown the blocking circuit K is controlled by a zero level detector D2 and the summing is effected by emitter followers or operational amplifiers.

CIRCUIT ARRANGEMENT FOR DETERMINING THE RELATIVE PACKED CELL VOLUME IN BLOOD

... 1469306 Integrating electric signals KOMBINAT MEDIZIN-UND LABORTECHNIK LEIPZIG VEB 17 July 1974 [23 July 1973] 31710/74 Heading G1U A switch 7, Fig. 1, is so controlled by upper and lower threshold circuits 4, 5, that only those signals from an amplifier 2 lying between the two threshold levels are passed to an integrator 8.

Power supply output device

A power supply output device 500 converts an input from a DC-DC convertor into a bipolar voltage output, particularly for a gate driver circuit driving a power switch. The power output supply device contains an adjusting circuit which measures the output of the gate driver circuit at the gate of the power switch, and adjusts the bipolar voltage to maintain the output of the gate driver circuit at a predetermined voltage. The power supply output device regulates the peak positive voltage input into the gate of the power switch at a required voltage regardless of fluctuations or losses. The power output supply device includes a voltage dividing element 502 converting the supply voltage into a bipolar voltage output, a voltage clamping circuit 504, e.g. Zener diode, setting one of the first or second output voltage values of the bipolar voltage output at a first predetermined voltage, and an adjustment circuit 506 to adjust one of the first or second output voltage values in order to maintain ...

INTEGRATED CIRCUIT ELEMENT FOR BERWACHUNG CURRENT SUPPLY

Vorrichtung zur Erzeugung von Zufallszahlen

Die Erfindung betrifft ein Verfahren zur Erzeugung von Zufallszahlen, wobei a) eine Quelle (1), die zu nicht vorhersagbaren Zeitpunkten mit einer vorgegebenen Verteilung Energie, insbesondere in Form von Impulsen, abgibt, b) ein Detektor (3), der der Quelle (1) nachgeschaltet ist, und der die von der Quelle (1), insbesondere in Form von Impulsen, abgegebene Energie in Form von Impulsen detektiert, wobei c) gegebenenfalls von der Quelle (1) abgegebene Energie von einem zwischen der Quelle (1) und dem Detektor (3) befindlichen Abschwächer (2) unterdrückt oder abgeschwächt wird, d) wobei die Zeitspanne zwischen einem vorgegebenen Startzeitpunkt (t0) und dem Zeitpunkt der Detektion eines Impulses durch den Detektor (3) ermittelt wird, wobei das Ergebnis der Zeitmessung als Zufallszahl herangezogen wird.

SWITCHING CONFIGURATION FOR THE RECOVERY OF COLOR DIFFERENCE SIGNAL INFORMATION

AMPLITUDE DETECTOR FOR PULSE-TYPE SIGNALS WITH HIGH PULSE RECURRENCE FREQUENCY.

ENTRANCE BUFFER AND VOLTAGE LEVEL DETECTION PROCEDURE

Pedalling bag od.dgl. for children

Signal clamping circuit with level shifting and error detection for multiple inputs

CIRCUIT FOR DECIDING ABOUT THE POSITION OF THE REPETITION FREQUENCY OF SIGNAL TRANSITIONS IN AN INPUT SIGNALS

RECEIVER FOR DIGITAL SIGNALS

CIRCUIT DEVICE AND METHOD OF CONTROLLING A VOLTAGE SWING

In particular illustrative embodiments, circuit devices and methods of co ntrolling a voltage swing are disclosed. The method includes receiving a sig nal at an input of a digital circuit device including a capacitive node. The method also includes selectively activating a voltage level adjustment elem ent to regulate an electrical discharge path from the capacitive node to an electrical ground to prevent complete discharge of the capacitive node. In a particular illustrative embodiment, the received signal may be a clock sign al.

TRANSISTOR-TRANSISTOR LOGIC CLIPPING CIRCUIT

FAIL-SAFE ELECTRONIC POLARIZED RELAY

Schaltungsanordnung zur Erzeugung einer Spannung von angenähert rechteckiger Kurvenform, insbesondere zur Steuerung von Stromrichtern.

Alliage d'aluminium

Elément d'emmagasinage filiforme et son utilisation

Procédé et dispositif de sélection d'impulsions

Circuit électrique de commande, à impulsions de sortie de durée réglable

Schaltungsanordnung zur Erzeugung von zwei regelmässigen Folgen von Rechteckimpulsen

SCHALTUNGSANORDNUNG FUER EINEN MEHRFREQUENZCODESIGNALEMPFAENGER.

Mémoire magnétique pour données numériques

Circuit de détection d'impulsions

Breitbandverstärker

Regelbarer Verstärker

Amplificateur-calibrateur d'impulsions, notamment pour l'alimentation pulsée de tubes Geiger-Muller

SCHALTUNGSANORDNUNG, DIE AUF ANSTEUERUNG EINES EINGANGSSIGNALS, BEI DEM SIGNALDURCHGAENGE DURCH EINEN FESTEN BEZUGSWERT AUFTRETEN, EIN SIGNAL ERZEUGT, DAS VOM VERHAELTNIS DES ZWISCHEN JE ZWEI AUFEINANDERFOLGENDEN SIGNALDURCHGAENGEN LIEGENDEN ZEITINTERVALLS ZU EINEM BEZUGSZEITINTERVALL ABHAENGIG IST.

Comparator, analog-to-digital convertor, solid-state imaging device, camera system, and electronic apparatus

A comparator includes a first amplifier and a level holding part. The first amplifier includes differential-pair transistors and outputs a signal of a level corresponding to a comparison result from a first output node. The differential-pair transistors serve as a comparison part that receives a reference voltage, a signal level of which changes with a slope, at a gate of one of the differential-pair transistors, receives an input signal at a gate of the other of the differential-pair transistors, and compares the reference voltage with a potential of the input signal. The level holding part holds a level of the first output node such that the other transistor having an output part thereof connected to the first output node out of the differential-pair transistors of the first amplifier does not fall into a level at which a saturated operation condition is not satisfied.

Semiconductor device

Clipping device

Non-linear amplifier for recurrent pulses - has linear amplifier at output of blocking trigger with periodically varied threshold

METHOD FOR GENERATING A PULSE AND MOUNTING THEREFOR

Voltage level shift circuit for logic signals - allows interfacing of basically different processing circuits using transistor circuit

REPRODUCE HEAD WITH PEAK SENSING CIRCUIT

Control circuits automatic of profit for the electric impulses

DEVICE OF LIMITATION OF the AMPLITUDE Of a SIGNAL PER HIGHER AND LOWER CHOPPING

TENSION DETECTOR OF DIFFERENTIAL THRESHOLD

Circuit de détection de niveau de tension de seuil différentiel recevant une paire de tensions différentielles comme entrée, appliquant chaque composante de la paire différentielle à un circuit de décalage de tension individuel (300). Chaque circuit de décalage de tension est configuré avec un courant régulé produisant une version décalée et non décalée en phase. Pour un jeu décalé de tensions différentielles de sortie, la valeur de décalage est proportionnelle au courant entrant dans un circuit de décalage et est configurée pour être inférieure à une valeur crête-à-crête de la tension différentielle à détecter. Un miroir de courant à l'intérieur du détecteur comprend une référence de courant (360) configurée pour produire un courant destiné à traverser un générateur de tension (355). La valeur de courant est suffisante pour générer une sortie de tension régulée pour les deux régulateurs de courant alimentant les circuits de décalage de tension. Un détecteur de chevauchement (500) recevant ...

고전압 내성 입력 전압 버퍼 회로

... 신호를 수신하는 제1 노드; 출력 신호를 제공하는 제2 노드; 제1 공급 전압 하에서 동작하는 전압 리미터 회로 - 전압 리미터 회로는 제1 노드 및 제2 노드에 결합됨 -; 및 제1 공급 전압 하에서 동작하는 바이패스 회로 - 바이패스 회로는 전압 리미터 회로에 결합되고, 바이패스 회로는 제1 노드를 제2 노드에 전기적으로 단락시키도록 인에이블될 수 있음 - 를 포함하는 장치가 개시된다.

INTEGRATED CIRCUIT USING METHOD FOR SETTING THE LEVEL OF REFERENCE VOLTAGE

A signal converter and the method thereof

A signal converter and the method thereof are disclosed, which is to be applied in voltage signal conversion environment. The present invention of signal converter and the method thereof can convert high-voltage sinusoidal signal into low-voltage all-wave and/or half-wave signals and improve circuit stability. The signal converter is an integrated circuit type, and can be integrated with other integrated circuits to improve the system integration.

Power clamp circuit and semiconductor device

A power clamp circuit for preventing unnecessary power supply leak current at a tolerable power supply noise level. A reference voltage circuit generates a reference voltage by reducing a positive voltage supplied from a first power supply terminal by a predetermined potential and supplies the reference voltage to a buffer circuit. The buffer circuit activates a transistor functioning as a clamp element based on the reference voltage to short-circuit the first and second power supply terminals.

Limiter circuit

A limiter circuit includes a differential amplifier circuit having a non-inverting and an inverting inputs, the inverting input fed with an input signal to the limiter circuit, a driving circuit fed with an output of the differential amplifier, a MOS transistor having a source, a drain and a gate, one of the source and the drain of the MOS transistor connected to an output of the driving circuit, the other of the source and the drain of the MOS transistor connected to the non-inverting input of the differential amplifier, the gate of the MOS transistor applied with a predetermined voltage, and a load circuit connected to the other of the source and the drain of the MOS transistor.

Comparator circuit, a/d conversion circuit, and display device

Disclosed is a comparator circuit having: a first switch unit that selectively picks up a signal voltage; a second switch unit that selectively picks up a control waveform; a differential amplifier, the non-inverting input terminal of which is connected to the output terminals of the first switch unit and the second switch unit; a capacitance unit, one terminal of which is connected to the inverting input terminal of the differential amplifier, and the other terminal of which is supplied with a reference voltage; and a third switch unit that selectively provides a short-circuit between the inverting input terminal and the output terminal of the differential amplifier.

Relay adaptive to alternative current and direct current input signals

A relay includes a first contact for receiving an input signal, a second contact for receiving a power signal, a rectifier coupled to the first and second contacts for converting the power signal into a direct-current power signal when the power signal is an alternative-current power signal, a voltage clamping circuit coupled to the rectifier for clamping a voltage of the input signal and the power signal, a Schmidt trigger coupled to the voltage clamping circuit for generating a trigger signal according to the input signal and the power signal, and a power outputting circuit coupled to the Schmidt trigger for generating an output voltage according to the trigger signal and a supply power.

Circuits de commande automatique de gain pour les impulsions électriques

LOW POWER 32 KHZ OSCILLATOR

A CMOS low frequency oscillator circuit comprising an amplifier (10) and an interface for connecting a first and a second terminal of an external crystal oscillator (14) in a feedback path of the amplifier (10). The oscillator circuit further comprises a regulated current source (24) supplying a regulated current to the amplifier (10) controlled by the voltage swing across the external crystal oscillator (14); and a constant current source (32) supplying a minimum constant current to the amplifier (10) independent of the voltage swing across the external crystal oscillator (14). Alternatively, the oscillator circuit further comprises an output stage (34) for converting an analog oscillator signal provided at the first and second terminal of the external crystal oscillator into a digital clock signal; wherein the output stage has a differential input (36) and a single-ended output (38) and includes a comparator (40) coupled with its differential input to the two terminals of the external ...

DELAY CIRCUIT AND TEST APPARATUS

A delay circuit for delaying an input signal with a desired delay and outputting the delayed signal. The delay circuit includes a light emitting element for emitting light according to an input signal and outputting a delay signal, a bias current source for supplying in advance a first light emitting element with a bias current smaller than a light emission threshold current of the first light emitting element, a bias current controller for controlling the bias current according to a desired delay time, a modulation current source for supplying the light emitting element with a modulation current for making the light emitting element emit light in accordance with the input signal, and a modulation current controller for controlling the modulation current in accordance with a delay resolution in the delay circuit. The modulation current controller controls the modulation current further according to a variable delay range in the delay circuit.

Input buffer and method for voltage level detection

An improved input buffer circuit and method configured for voltage detection is provided that can facilitate use of a mid-level voltage for testing purposes. An exemplary input buffer configured for voltage detection comprises a reference generator and a multi-state detector. The reference generator is configured to generate at least two reference voltages to be provided as input signals to the multi-state detector. The multi-state detector is suitably configured to receive an input reference signal, and through comparison of the input reference signal to the two reference voltages, provide output signals to three output terminals representing a high, low and mid-level state of operation. An exemplary input buffer circuit can comprise two differential pairs of transistors configured in a back-to-back arrangement and sharing a common node, thus resulting in lower current requirements. In addition, the input buffer can provide for multiple operations from the same die pad without requiring ...

MOS driver circuit having clamp means to hold the output voltage constant regardless of variations in the operating voltage

A MOS driver circuit comprises a pull-up NMOS transistor, a pull-down NMOS transistor, and a clamper circuit. The pull-up NMOS transistor has a source connected to an output terminal and a gate connected to a boosting node supplied with a boosted voltage when the output terminal is driven to a "high" state. The pull-down NMOS transistor has a drain connected to the output terminal and a source connected to the ground voltage, and is turned on when the output terminal is driven to a "low" state. The clamper circuit clamps the boosted voltage to a predetermined voltage by opening a current path from the boosting node to the output node when the boosted voltage supplied to the boosting node is greater than the predetermined voltage. In the circuit, the noise in the power and ground lines, which is generated due to the variation of the output voltage caused by the variation of the supply voltage, is prevented. Also, since the clamper circuit of the present invention discharges the charge of ...

Current sensing circuit and method of a high-speed driving stage

The present invention discloses a current sensing circuit and method of a high-speed driving stage, which comprises an input stage, a level converting unit, a feedback unit, a current mirror unit and a current shunting unit. The current sensing circuit is capable of linearly detecting the output current of the driving stage transistors, and directly condensing the detected current to an appropriate value using the geometric ratio of the transistors, so as to facilitate the subsequent signal processing circuit to use it for control purposes.

Potential detecting circuit

An object of the present invention is to enable detection of a precise substrate potential even when the substrate potential of the detecting circuit is at a lower level than the substrate to be measured, and to allow free setting of the stable detection level without being affected by fluctuation in the power supply potential. To that end, there are provided an operational amplifier for differential amplification when the ground potential and the positive power supply potential are supplied, a first resistor for transmitting the substrate potential to the first input terminal of the operational amplifier, a constant voltage circuit, and a reference voltage generating circuit for supplying a positive reference voltage to the second input terminal of the operational amplifier.

Comparator and a control circuit for a power MOSFET

A control circuit for a power MOSFET includes a voltage divider for dividing an input voltage, a fixed voltage generator for generating a fixed voltage, a comparator having a differential pair including first and second depletion transistors each receiving the divided voltage or the fixed voltage and a current mirror including first and second enhancement transistors connected in series with the first and second depletion transistors, respectively, an inverter for receiving the output from the comparator, and a power MOSFET controlled for the ON/OFF control thereof by the inverter.

Semiconductor device

A semiconductor device includes: a power supply; a circuit block that has at least one storage element and operates by receiving a power supply voltage from the power supply; a power management unit that controls the power supply to change the power supply voltage; and a storage element monitor circuit that generates a first malfunction signal at a first margin voltage that is higher than a voltage at which the storage element does not normally operate in a case where the power supply voltage lowers, wherein the power management unit controls the power supply so that the power supply voltage does not become lower than the first margin voltage.

Delay circuit having function of filter circuit

A first PMOS transistor is connected between a supply terminal of a power supply voltage VCC and a connection node MON. A first NMOS transistor and a second NMOS transistor are connected between the connection node MON and ground. The first PMOS transistor and the first NMOS transistor are driven by an input signal. The second NMOS transistor is driven by a constant current IREF. In cooperation with the first NMOS transistor, the second NMOS transistor discharges the charge across a capacitor C 1 connected to the connection node MON. A differential amplifier. compares a potential at the connection node MON with a potential depending upon the constant current IREF, and outputs a result of the comparison.

Local X-decoder and related memory system with a voltage clamping transistor

A local X-decoder for a memory system including a decoding unit configured to generate a word line signal to a memory cell of a memory array of the memory system; and a voltage clamping transistor coupled to the decoding unit, and configured to reduce a voltage difference across a global word line signal and the word line signal by an amount of a threshold voltage of the voltage clamping transistor.

SIGNAL POTENTIAL CONVERTER

Disclosed herein is a signal potential converter which may perform high-speed operation and which may still maintain intended signal amplitude and operate normally even while operating at a low rate or receiving a burst signal. In this signal potential converter, a capacitor receives an input signal CIN at one terminal thereof and has the other terminal thereof connected to a terminal node. A clamp circuit defines a potential at the terminal node, i.e., a signal IN, within the range of a first potential to a second potential. If a potential at the terminal node is higher than a third potential, a voltage holder circuit operates to raise the potential at the terminal node. If the potential at the terminal node is lower than the third potential, the voltage holder circuit operates to lower the potential at the terminal node.

Converting large input analog signals in an analog-to-digital converter without input attenuation

In an example embodiment, an apparatus includes: a first sampling capacitor and a comparator to compare a sum voltage at a first input terminal to a voltage level at a second input terminal according to a thermometer cycle. The sum voltage is based at least in part on an analog input voltage and a divided reference voltage, where the analog input voltage and the reference voltage (VREF) are of a first voltage range and the divided reference voltage is according to ( ( 2 M - 1 ) ⁢ V REF / 2 M ) , to enable the comparator to operate at a second voltage range, the second voltage range less than V REF / 2 M , and M is a number of bits of a digital output to be decided in the thermometer cycle and is greater than one.

METHODS AND CIRCUITRY FOR DRIVING A DEVICE

Methods and circuitry for driving a device through drive cycles wherein each drive cycle has a plurality of drive stages are disclosed. An example of the circuitry includes an output for coupling the circuitry to the device and a plurality of drive slices coupled in parallel to the output. Control circuitry selectively activates individual drive slices in the plurality of drive slices during each stage of a drive cycle. 1. Circuitry comprising:drive slices coupled in parallel to an output;a shift register coupled to the drive slices, the shift register comprising a first flip-flop and a second flip-flop, the first flip-flop for storing first information for a first drive stage of a drive cycle and the second flip-flop for storing information for a second drive stage of the drive cycle, the shift register for moving the information for the second drive stage from the second flip-flop to the first flip-flop while shifting the shift register;control circuitry coupled to the shift register, to activate a combination of drive slices of the drive slices during corresponding drive stages of the drive cycle, in response to shifting the shift register.2. The circuitry of claim 1 , wherein the output of the control circuitry couples to a gate of a transistor.3. The circuitry of claim 1 , wherein a drive slice of the drive slices comprises:a node coupled to a power supply; anda transistor coupled between the node and the output, a gate of the transistor coupled to the control circuitry.4. The circuitry of claim 1 , wherein the control circuitry varies drive power at the output.5. The circuitry of claim 1 , wherein a first drive slice of the drive slices outputs a first drive power and a second drive slice of the drive slices outputs a second drive power claim 1 , wherein the first drive power is different from the second drive power.6. The circuitry of claim 5 , wherein the first drive slice outputs twice the drive power as the second drive slice.7. (canceled)8. The circuitry ...

Semiconductor integrated circuit device and pulse width changing circuit

A semiconductor integrated circuit device comprises a plurality of MIS transistors, and an integrated circuit unit including logic gate circuits configured by a combination of the plurality of MIS transistors. Each of the MIS transistors has a gate including a circuit element represented by an equivalent circuit in which a capacitance and resistance are parallel-connected.

INPUT STAGE OF CHIP AND METHOD FOR CONTROLLING SOURCE DRIVER OF CHIP

An input stage of a chip includes a source driver and a sensing and clamping circuit. The source follower is arranged for receiving an AC-coupled signal to generate an output signal at an output terminal. The sensing and clamping circuit is coupled to the source follower, and is arranged for clamping the output terminal of the source follower at a fixed DC voltage. 1. An input stage of a chip , comprising:a source follower, for receiving an AC-coupled signal to generate an output signal at an output terminal; anda sensing and clamping circuit, coupled to the source follower, for clamping the output terminal of the source follower at a fixed DC voltage.2. The input stage of claim 1 , wherein the chip comprises a pad claim 1 , and the source follower directly receives the AC-coupled signal from the pad.3. The input stage of claim 1 , wherein the sensing and clamping circuit comprises an operational amplifier claim 1 , one input terminal of the operational amplifier is coupled to a reference voltage claim 1 , and another input terminal of the operational amplifier is coupled to the output terminal of the source follower.4. The input stage of claim 3 , wherein an output terminal of the operational amplifier is coupled to an input terminal of the source follower.5. The input stage of claim 4 , wherein the sensing and clamping circuit further comprises a switch coupled between the input terminal of the source follower and the output terminal of the operational amplifier claim 4 , and the switch is arranged to selectively connect the input terminal of the source follower to the output terminal of the operational amplifier or not.6. The input stage of claim 1 , wherein a DC voltage of an input terminal of the source follower is determined based on the fixed DC voltage at the output terminal of the source follower.7. The input stage of claim 6 , wherein the DC voltage of the input terminal of the source follower is not directly clamped by any voltage clamping circuit.8. The ...

Peak-detector circuit and method for evaluating a peak of a first input voltage

A peak-detector circuit may include a first input terminal for providing a first input voltage, a first rectifying element with an anode connected to the first input terminal, a first capacitor with a first electrode connected to a cathode of the first rectifying element, a first terminal coupled to the first electrode of the first capacitor, a second rectifying element with a cathode connected to the first input terminal, a second capacitor, a first switch coupling an anode of the second rectifying element to a first electrode of the second capacitor, and a second terminal coupled to the first electrode of the second capacitor.

Method for detecting with a high temporal accuracy a threshold crossing instant by a signal

A method for detecting, through an electronic detection device (1), a threshold crossing instant (TOA) at which an electrical signal (V) crosses a threshold S is described. Such method comprises the steps of: defining, by a clock signal (CL), a sequence of discrete clock instants (Tn) such that two consecutive clock instants of the sequence are time spaced from one another by a clock period (T); then, sampling the electrical signal (V) with a sampling period (T) equal to the clock period (T), at a plurality of sampling instants (Ts) belonging to the sequence of clock instants (Tn); then detecting a first sampling instant (Ts1) and a subsequent consecutive second (Ts2) sampling instant, such that at one of said first (Ts1) and second sampling instant (Ts2) the sampled signal value has a first signal value (V1) lower than or equal to threshold (S), and at the other one of said first (Ts1) and second (Ts2) sampling instant the sampled signal value has a second signal value (V2) higher than ...

Deglitching network for digital logic circuits

A deglitching network for digital logic circuits includes a voltage actuated current source coupled to a linear tracking, constant voltage column clamp circuit. The deglitching network threshold level tracks closely with the predetermined voltage of the column clamp, which also acts as a current sink. When heavy current loads are switched from the column clamp and its voltage falls briefly, the deglitching network is actuated to inject current into the column clamp circuit and restore the preset voltage.

INPUT STAGE OF A PROCESSING UNIT

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PULSE WIDTH REVISION CIRCUIT

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device that can reduce the pulse width with a delay smaller than a delay of a logic gate circuit. SOLUTION: The semiconductor integrated circuit device includes an integrated circuit section including a basic unit element (1) configured with MIS (Metal- Insulator-Semiconductor) transistors (TRs) (2, 3) each having a gate including a circuit element (4) comprising a parallel connection of a capacitor (C) and a resistor (R) as an equivalent circuit. COPYRIGHT: (C)2002,JPO ...

VARIABLE DELAY CIRCUIT

PROBLEM TO BE SOLVED: To provide a variable delay circuit in which a delay time is set precisely. SOLUTION: When an input signal to anode N11 is switched from H to L and the potential of N13 is shifted from H to L to turn off a transistor Q13, an electric charge charged to a capacity element C11 is discharged by a constant current source 5. By the variation of voltage applied between the base-emitter of the transistor Q13, an electric charge stored in the parasitic capacitance Cje11 is varied. At this time, an electric charge stored in a parasitic capacitance Cje12 existing in an NPN transistor where p-n connection is reverse-bias- connected between a terminal N14 outputting the signal of the inverse logic of the output of an amplitude magnifying buffer and a ramp waveform generation node is varied with a phase inverse to the variation of the electric charge stored in the parasitic capacitance Cje11 of the transistor Q13. Since the variation of the electric charges stored in the parasitic ...

УСТРОЙСТВО С ОБРАТНОЙ СВЯЗЬЮ ДЛЯ КЛИППИРОВАНИЯ ЗНАКОПЕРЕМЕННЫХ СИГНАЛОВ (ВАРИАНТЫ)

... 1. Устройство с обратной связью для клиппирования знакопеременных сигналов, содержащее два компаратора и D-триггер, выход которого является выходом устройства, а входом - объединенные прямой вход первого компаратора и инвертирующий вход второго компаратора, отличающееся тем, что в него введены второй D-триггер, элемент задержки и элемент И, выход первого компаратора соединен с тактовым входом первого D-триггера, D-вход которого является входом фиксированного уровня логической единицы, выход второго компаратора соединен с обнуляющим входом второго D-триггера, тактовый вход которого соединен с выходом элемента И, первый вход которого соединен с выходом элемента задержки, вход которого соединен с выходом первого D-триггера, обнуляющий вход которого соединен с выходом второго D-триггера, D-вход которого является входом фиксированного уровня логической единицы, второй вход элемента И соединен с инверсным выходом второго компаратора, инвертирующий вход первого компаратора является входом первого ...

ПРИЕМНИК В ШИННОМ УЗЛЕ ШИННОЙ СЕТИ

... 1. Приемник в шинном узле шинной сети, прежде всего EIB-сети, который подключен к шинной линии (Bus+, Bus-), которая предоставляет в распоряжение приемника образованный из битовых импульсов сигнал, с дифференциальным усилителем (Q1A, Q1B, Q2A, Q2B), который имеет первый вход (Е1) и второй вход (Е2) и по меньшей мере один выход (RxD),при этом к первому входу (Е1) приложено опорное напряжение (Uref), а ко второму входу приложено несущее сигнал напряжение, которое рассчитано так, что сигнал на выходе (RxD) появляется лишь тогда, когда абсолютное значение напряжения на втором входе (Е2) больше, чем абсолютное значение опорного напряжения (Uref) на первом входе,отличающийся тем, чтопредусмотрен источник (+U2) напряжения, который, с одной стороны, предоставляет в распоряжение несущее сигнал напряжение и из которого, с другой стороны, отводится опорное напряжение (Uref),при этом между выходом (RxD) и первым входом (Е1) дифференциального усилителя включено сопротивление (R6) обратной связи.2. Приемник ...

Vorrichtung und Verfahren zur Signalspitzenbegrenzung

SCHALTUNGSANORDNUNG ZUM UMWANDELN EINES ANALOGEN SIGNALS IN EIN BINAERES SIGNAL

TWO-LEVEL THRESHOLD CIRCUITRY FOR LARGE SCALE INTEGRATED CIRCUIT MEMORIES

Begrenzer fuer elektrische Signale

RAUSCHARMER UEBERTRAGUNGSLEITUNGS-ABSCHLUSSKREIS.

Schutzschaltkreis für integrierte Schaltungen

LEVEL CONVERTER

Detektionsschaltung für Radiofrequenzenergie.

RINGING-UNTERDRÜCKUNGSSCHALTUNG

Eine Ringing-Unterdrückungsschaltung ist mit einer Übertragungsleitung (3) verbunden, um ein differentielles Signal, das auf einen hohen Pegel oder einen niedrigen Pegel als einer von Binärpegeln geändert wurde, durch ein Paar aus Signalleitungen zu übertragen, um bei Übertragung des differentiellen Signals auftretendes Ringing zu unterdrücken. Die Ringing-Unterdrückungsschaltung beinhaltet: ein einzelnes durch eine Spannung angesteuertes Leitungsschaltelement (15) das zwischen dem Paar aus Signalleitungen verbunden ist; eine Steuereinrichtung (6), die eine Änderung eines Pegels des differentiellen Signals erfasst und das einzelne Leitungsschaltelement einschaltet, um eine Impedanz zwischen dem Paar aus Signalleitungen zu verringern; einen Periodenerfassungseinrichtung (10, 33, 43), die eine Länge einer Unterdrückungsperiode erfasst, die durch ein Einstellsignal angegeben wird, das eine Eingabe ist; und einen Unterdrückungsperiodenspeicher (11, 54), der die Länge der Unterdrückungsperiode ...

Impulsformerschaltung und Apparat zur digitalen Signalanalyse für diese Schaltung

CLAMP CIRCUIT USING PMOS and NMOS DEVICES

A MOS-type semiconductor clamping circuit is disclosed. The clamping circuit comprises a pmos device coupled to a nmos device in series to form the clamping circuit to selectively clamp a signal to a reference voltage, the signal configured to swing between a first voltage and a second voltage about the reference voltage. When the signal is swung between the first voltage and the second voltage, the pmos device and the nmos device are subjected to a voltage swing less than the voltage swing between the first voltage and the second voltage.

Low phase noise buffer for crystal oscillator

A buffer for converting sinusoidal waves to square waves with reduced phase noise is described herein. The buffer shunts current from the outputs of a differential amplifier during sinusoidal state transition periods at the differential amplifier inputs to increase the finite slope of square wave transition periods of the output square wave. More particularly, a sinusoidal wave having alternating peaks and valleys connected by sinusoidal state transition periods is applied to differential inputs of a differential amplifier to generate a square wave at the differential outputs, where the output square wave comprises alternating high and low states connected by square wave state transition periods having a finite slope. The output square wave is shaped to increase the finite slope of the square wave transition periods by providing additional paths between the differential outputs and ground that shunt current from the differential amplifier during the sinusoidal state transition periods.

Bipolar transistor anti-saturation clamp using auxiliary bipolar stage, and method

An output stage ( 1 - 2 ) includes a gain circuit (Q 1 ,Q 2 ) for driving a base of a main transistor (Q 3 ) having a collector coupled to an output ( 18 ) in response to an input signal V 11 ) which also controls a base of an auxiliary transistor (Q 7 ) having a collector coupled to the output. A clamping transistor (Q 6 ) has a control electrode coupled to the base of the auxiliary transistor, a first electrode coupled to the output, and a second electrode coupled to provide feedback from the output via the gain circuit to the base of the main transistor and to provide feedback from the output to the base of the auxiliary transistor. When the auxiliary transistor goes into deep saturation it causes the clamping transistor to provide negative feedback from the output to the main output stage so as to prevent the main transistor from going into deep saturation.

Method and circuit for recovering a sync signal fed via a cable to a raster scan display device

In a method and circuit for recovering a sync signal from an input sync signal passing through a cable to a display device, an average value of the input sync signal is obtained during a predetermined time period so as to obtain a sync threshold, which is compared with the input sync signal. A sync signal is output when the input sync signal is greater than the sync threshold.

Optical transceiver ic

A power management arrangement for low power optical transceiver such as those that may be integrated into a personal computer or server may periodically put itself into a power conservation or sleep mode which assures the transceiver is available upon wake-up.

Comparator of a difference of input voltages with at least a threshold

A comparator is configured to generate an output voltage representing the comparison between the absolute value of the difference between two input voltages with an adjustable reference voltage. The comparator includes an input differential amplifier, receiving the two input voltages and connected to an active load network controlled by a control voltage, a control circuit that generates the control voltage representing the adjustable reference voltage, and an output stage having a logic circuit configured to produce the output voltage of the comparator as a logic combination of the output voltages of the differential amplifier.

Circuit with passive components for high-speed drive of an optoelectronic device

A circuit for the ultra-quick control of an optoelectronic device, includes a generator of voltage pulses having a pulse duration of less than 400 ps, and a circuit ( 17 ) for shaping control pulses including: an output suitable for being connected in series to a line terminal ( 13 ) of the optoelectronic device, and an input connected to the voltage-pulse generator and receiving the voltage pulses formed by the latter, between a terminal of the input and a terminal of the output, mounted in parallel in relation to one another: a first branch ( 20 ) made up of a passive rectifier circuit ( 22 a, 22 b ) having non-zero threshold voltage and, in series in the first branch in forward direction relative to the line terminal ( 13 ) of the optoelectronic device, a second capacitive branch ( 21 ).

Switching regulator device and method with adaptive frequency foldback

A control circuit for a switching regulator includes a clock circuit, a pulsewidth modulation (PWM) circuit, and a reduction monitor. The clock circuit provides a clock signal at a variable frequency. The PWM circuit produces a drive signal of at least a first predetermined duration once every period of the clock signal. The reduction monitor controls the clock circuit to reduce the variable frequency in response to a sense signal that indicates that at least one of a voltage and a current is outside a limit during the first predetermined duration of said drive signal.

Laser diode driver damping circuit

A damping circuit having an input terminal and an output terminal is described. The damping circuit comprises a driver having an input and an output; an RC circuit coupled between the input terminal and the output; and a resistor coupled between the output and the output terminal, wherein the RC circuit delays passing a signal from the output terminal to the input terminal and a low impedance associated with the driver generally reduces ringing.

CLIPPING CIRCUIT, DIFFERENTIAL AMPLIFYING CIRCUIT, AND AMPLIFYING CIRCUIT

There is provided a clipping circuit in which a first input terminal receives a first signal, a second input terminal receives a second signal, a first variable resistive element has a control terminal electrically connected to the second input terminal and has a threshold, first and second ends of the first variable resistive element are connected to first input terminal and a reference voltage, respectively, the second variable resistive element has a control terminal electrically connected to the first input terminal and has a threshold, first and second ends thereof are connected to a second input terminal and the reference voltage, respectively, a first bias applying unit applies a bias voltage lower than the threshold to the control terminal regarding the first variable resistive element, and a second bias applying unit applies a bias voltage lower than the threshold to the control terminal regarding the second variable resistive element. 1. A clipping circuit , comprising:a first input terminal to receive a first signal, a pair of the first signal and a second signal forming a differential signal as a clipping target;a second input terminal to receive the second signal;a first variable resistive element having a control terminal electrically connected to the second input terminal and having a threshold, a first end of the first variable resistive element being connected to the first input terminal and a second end of the first variable resistive element being connected to a reference voltage;a second variable resistive element having a control terminal electrically connected to the first input terminal and having a threshold, a first end of the second variable resistive element being connected to the second input terminal, and a second end of the second variable resistive element being connected to the reference voltage;a first bias applying unit to apply a bias voltage lower than the threshold of the first variable resistive element to the control terminal ...

TRIMMING OF OPERATIVE PARAMETERS IN ELECTRONIC DEVICES BASED ON CORRECTIONS MAPPINGS

An embodiment of an electronic device having a plurality of operative parameters is provided. The electronic device includes means for applying a plurality of trimming actions to each parameter for causing a corresponding correction of the parameter, for at least one reference parameter, means for measuring the reference parameter responsive to the application of at least part of the trimming actions, and means for forcing the application of the selected trimming action for the reference parameter. For each non-reference parameter different from the at least one reference parameter, the electronic device includes means for selecting one of the trimming actions for the non-reference parameter corresponding to the selected trimming action for the at least one reference parameter, and means for forcing the application of the selected trimming action for each non-reference parameter. 111.-. (canceled)12. An electronic device , comprising:a trimming circuit for applying a plurality of trimming actions to each of a plurality of parameters, each trimming action causing a corresponding correction of each respective parameter,a measuring circuit for measuring at least one parameter as a reference parameter in response to the application of at least one of the trimming actions such that the at least one trimming action provides a target value of the reference parameter, anda selection circuit operable to select a trimming action for each non-reference parameter different from the at least one reference parameter, and further operable to select one of the trimming actions for the non-reference parameter corresponding to the selected trimming action for the at least one reference parameter according to a predetermined mapping of each group of multiple corrections of the at least one reference parameter on a single correction of the non-reference parameter, anda biasing circuit for forcing the application of the selected trimming action for the reference parameter and for ...

Data reproduction circuit and data transmission device

Disclosed herein is a data reproduction circuit including: a comparator configured to compare input data resulting from capacitive coupling with a comparison voltage as a threshold voltage and output a comparison result; and a comparison voltage variable section configured to change the comparison voltage along a mark rate of the input data and supply the changed comparison voltage to the comparator.

METHOD AND APPARATUS FOR ACTIVE RIPPLE CANCELATION

Various embodiments of the invention allow for active AC ripple noise cancellation. In certain embodiments, noise cancellation is accomplished by modulating an LED driver output in a polarity opposite to the ripple, thereby, preventing interference with ripple-sensitive loads. Certain embodiments take advantage of a filter network to prevent the LED driver from modulating LED current in response to ripple that falls within a visible frequency range so as to prevent flicker in an LED backlight display. 1. A driver circuit for canceling ripple in a signal , the circuit comprising:a filter network coupled to receive a first input signal, the first input signal having a ripple, the filter network modifies the first input signal to exclude frequencies in a first set of prescribed ranges to generate a modified input signal;a controller coupled to receive both the modified input signal from the filter network and a setpoint signal, the controller modulates the setpoint signal in a relationship opposite to the ripple to generate a control signal; andan output stage coupled to receive the first input signal and the control signal to generate an output signal comprising a reduced ripple when compared to the first input signal.2. The circuit according to claim 1 , wherein the filter network comprises an amplifier circuit claim 1 , the amplifier circuit amplifies frequencies in a second set of prescribed ranges.3. The circuit according to claim 1 , the filter network comprising a combination of high pass and low pass elements that are independently adjustable to exclude frequencies in the first set of prescribed ranges.4. The circuit according to claim 1 , wherein the setpoint signal is a programmable current signal.5. The circuit according to claim 1 , wherein the filter network comprises at least one stopband filter characteristic adapted to suppress an amplification of frequencies in the second set of prescribed ranges.6. The circuit according to claim 5 , wherein the second ...

SWITCHING CIRCUIT FOR A TRANSMISSION CHANNEL FOR ULTRASOUND APPLICATIONS, TRANSMISSION CHANNEL AND PROCESS FOR DRIVING A SWITCHING CIRCUIT

A switching circuit for transmission channel for ultrasound applications is electrically coupled between a connection terminal and a low voltage output terminal. The switching circuit includes a receiving switch, a high voltage clamp circuit electrically coupled between the connection terminal and a central node, and a low voltage clamping switch electrically coupled between said central node and a reference voltage. The receiving switch is a low voltage switch and is electrically coupled between the central node and the low voltage output terminal. The clamping switch and the receiving switch are controlled in a complementary way with respect to each other. A transmission channel for ultrasound applications includes the switching circuit 1. A switching circuit for a transmission channel for ultrasound applications , comprising:a connection terminal configured to be electrically coupled to the transmission channel;a low voltage output terminal;a reference voltage terminal;a high voltage clamp circuit electrically coupled between said connection terminal and an inner node;a low voltage clamping switch electrically coupled between said inner node and the reference voltage terminal; anda low voltage receiving switch electrically coupled between said inner node and said low voltage output terminal, said clamping switch and said receiving switch being configured to be controlled in a complementary way with respect to each other.2. The switching circuit according to claim 1 , wherein said clamp circuit comprises a first and a second switching transistor electrically coupled between said connection terminal and said inner node and having respective control terminals claim 1 , said first and second switching transistors being high voltage MOS transistors claim 1 , the switching circuit further comprising a driving block electrically coupled to the control terminals of the first and second switching transistors.3. The switching circuit according to claim 2 , wherein: a third ...

CLAMP CIRCUIT AND METHOD FOR CLAMPING VOLTAGE

The disclosure provides a clamp circuit and a method for clamping voltage. The clamp circuit includes: a first switch control unit, connected with the high-potential terminal of the first stage output of a comparator and configured to clamp the voltage of the high-potential terminal to Vwhen the voltage of the high-potential terminal is lower than a first pre-set value V, and a second switch control unit, connected to the low-potential terminal of the first stage output of the comparator and configured to clamp the voltage of the low-potential terminal to Vwhen the voltage of the low-potential terminal is higher than a second pre-set value V, wherein the voltages of the first stage output of the comparator are between Vand V. By the disclosure, the output voltage swings of the first stage of the comparator are limited, and thereby the processing speed of the comparator is improved. 1. A clamp circuit , comprising:{'sub': Gate1', '1, 'a first switch control unit, connected with a high-potential terminal of a first stage output of a comparator and configured to clamp the voltage of the high-potential terminal to Vwhen the voltage of the high-potential terminal is lower than a first pre-set value V; and'}{'sub': Gate2', '2, 'a second switch control unit, connected to a low-potential terminal of the first stage output of the comparator and configured to clamp the voltage of the low-potential terminal to Vwhen the voltage of the low-potential terminal is higher than a second pre-set value V;'}{'sub': GND', 'CC, 'wherein the voltage of the first stage output of the comparator is between Vand V.'}2. The circuit according to claim 1 , wherein the first switch control unit is a first Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and the second switch control unit is a second MOSFET claim 1 , wherein{'sub': 1', '1, 'the first MOSFET is turned off when the voltage of the high-potential terminal is higher than or equal to V, and is turned on when the voltage of the ...

COMMON MODE TRIMMING WITH VARIABLE DUTY CYCLE

A resistive divider circuit may be operatively coupled with a modulated resistor circuit, wherein the resistive divider circuit and the modulated resistor circuit for an effective resistor circuit providing an effective attenuation. A variable duty cycle signal modulates the modulated resistor circuit to control the effective attenuation. 1. An apparatus comprising:a resistive divider circuit, comprising a first resistor and a second resistor;a modulated resistor circuit, operatively coupled to the resistive divider circuit, wherein the second resistor and the modulated resistor circuit form an effective resistor circuit providing an effective attenuation; anda variable duty cycle generator, to generate a variable duty cycle signal, wherein the variable duty cycle signal modulates the modulated resistor circuit to control the effective attenuation.2. The apparatus of claim 1 , wherein the variable duty cycle generator is a delta-sigma modulator circuit.3. The apparatus of claim 1 , further comprising:a differential circuit, wherein the resistive divider circuit is operatively coupled to an input of the differential circuit.4. The apparatus of claim 3 , wherein the differential circuit comprises a delta-sigma converter circuit.5. The apparatus of claim 3 , further comprising:an input of the resistive divider circuit, wherein a voltage received at the input is attenuated to an operational voltage of the differential circuit.6. The apparatus of claim 3 , further comprising:a second resistive divider circuit, comprising a third resistor and a fourth resistor;a second modulated resistor circuit, operatively coupled to the resistive divider circuit, wherein the fourth resistor and the second modulated resistor circuit form a second effective resistor circuit providing a second effective attenuation; anda second variable duty cycle signal, generated by the variable duty cycle generator, wherein the second variable duty cycle signal modulates the second modulated resistor ...

ADAPTIVE CASCODE CIRCUIT USING MOS TRANSISTORS

The present invention relates to a cascode circuit using MOS transistors. In one embodiment, an adaptive cascode circuit can include: (i) a main MOS transistor; (ii) n adaptive MOS transistors coupled in series to the drain of the main MOS transistor, where n can be an integer greater than one; (iii) a shutdown clamping circuit connected to the gates of the n adaptive MOS transistors, where the shutdown clamping circuit may have (n+1) shutdown clamping voltages no larger than rated gate-drain voltages of the main MOS transistor and n adaptive MOS transistors; and (iv) n conduction clamping circuits coupled correspondingly to the gates of the adaptive MOS transistors, where the n conduction clamping circuits may have n conduction clamping voltages no larger than the conduction threshold voltages of the adaptive MOS transistors. 1. An adaptive cascode circuit , comprising:a) a main MOS transistor, wherein a source of said main MOS transistor is configured as a first terminal of said adaptive cascode circuit, and wherein a gate of said main MOS transistor is configured as a control terminal of said adaptive cascode circuit;b) n adaptive MOS transistors coupled in series to a drain of said main MOS transistor, wherein a drain of a first adaptive MOS transistor is configured as a second terminal of said adaptive cascode circuit, and wherein n is an integer greater than one;c) a shutdown clamping circuit coupled to gates of said n adaptive MOS transistors, wherein said shutdown clamping circuit comprises (n+1) shutdown clamping voltages that are less than corresponding rated drain-gate voltages of said main MOS transistor and said n adaptive MOS transistors, wherein said shutdown clamping circuit is configured to clamp drain-gate voltages of said main MOS transistor and said adaptive MOS transistors to corresponding said shutdown clamping voltages when said main MOS transistor and said n adaptive MOS transistors are shutdown; andd) n conduction clamping circuits coupled ...

SEMICONDUCTOR DEVICE, LIQUID CRYSTAL DISPLAY AND ELECTRONIC APPARATUS

A semiconductor device includes: a trimming object circuit configured to use a trimming circuit to adjust an output based on a trimming value; and a trimming value setting circuit configured to set the trimming value. The trimming value setting circuit includes: a register configured to volatilely store a pseudo-trimming value set with reference to a trimming table such that an output value of the trimming object circuit becomes equal to a target value; a trimming value storage configured to non-volatilely store a final trimming value, wherein the final trimming value is set by correcting the pseudo-trimming value with reference to a trimming value correction table such that the output value of the trimming object circuit, which is obtained based on the pseudo-trimming value, becomes equal to the target value; and a selector configured to select one of the pseudo-trimming value and the final trimming value as the trimming value. 1. A semiconductor device comprising:a trimming object circuit configured to use a trimming circuit to adjust an output based on a trimming value; and a register configured to volatilely store a pseudo-trimming value set with reference to a trimming table such that an output value of the trimming object circuit becomes equal to a target value;', 'a trimming value storage configured to non-volatilely store a final trimming value with a predetermined trimming process, wherein the final trimming value is set by correcting the pseudo-trimming value with reference to a trimming value correction table such that the output value of the trimming object circuit, which is obtained based on the pseudo-trimming value, becomes equal to the target value; and', 'a selector configured to select one of the pseudo-trimming value and the final trimming value as the trimming value., 'a trimming value setting circuit configured to set the trimming value, the trimming value setting circuit including2. A semiconductor device comprising:a trimming object circuit ...

Circuit Arrangement with a First Semiconductor Device and with a Plurality of Second Semiconductor Devices

A circuit arrangement includes a first semiconductor device having a load path and a number of second semiconductor devices. Each second semiconductor device has a control terminal and a load path between a first load terminal and a second load terminal. The second semiconductor devices have their load paths connected in series and connected in series with the load path of the first semiconductor device. Each of the second semiconductor devices has a load terminal of one of the first semiconductor device and of one of the second semiconductor devices associated thereto and a voltage limiting element coupled between the control terminal of one of the second semiconductor devices and the load terminal associated with that one of the second semiconductor devices.

INTERFACE CIRCUIT

An interface circuit includes a receiver, a first terminal resistor, a second terminal resistor, a switch circuit and a switch control circuit. The receiver has a first channel and a second channel. The first channel receives a first channel voltage, and the second channel receives a second channel voltage. According to the first channel voltage and the second channel voltage, the switch control circuit controls the switch circuit to discharge a common mode capacitor before the first terminal resistor or the second terminal resistor couple to the common mode capacitor. 1. An interface circuit , comprising: a first channel, for receiving a first channel voltage; and', 'a second channel, for receiving a second channel voltage;, 'a receiver, comprising;'}a common mode capacitor;a first terminal resistor;a second terminal resistor;a switch circuit; anda switch control circuit, for controlling the switch circuit to discharge the common mode capacitor according to the first channel voltage and the second channel voltage before the first terminal resistor or the second terminal resistor couples to the common mode capacitor.2. The interface circuit according to claim 1 , wherein the switch circuit comprises:a first switch, for coupling the first terminal resistor and the common mode capacitor;a second switch, for coupling the second terminal resistor and the common mode capacitor;a third switch, for providing a first discharge path between the common mode capacitor and the first channel; anda fourth switch for providing a second discharge path between the common mode capacitor and the second channel.3. The interface circuit according to claim 2 , wherein the switch control circuit controls the third switch and the fourth switch to turn on before the first switch and the second switch are turned on.4. The interface circuit according to claim 2 , wherein the switch control circuit controls the third switch and the fourth switch to turn on after the first channel voltage ...

SEMICONDUCTOR DEVICE

The present invention is directed to prevent occurrence of a problem on a withstand voltage in a circuit group which receives supply of an internal power supply voltage. An error amplifier outputs a control voltage obtained by amplifying a difference voltage between a reference voltage and a divided voltage obtained by dividing an internal power supply voltage to an output node. A drive transistor supplies a drive current according to the control voltage of the output node of the error amplifier from an external power supply line to an internal power supply line. When the divided voltage exceeds a predetermined voltage, a clamp circuit changes the control voltage in the direction of decreasing the drive current. 1. A semiconductor device comprising:a first power supply line receiving supply of a first DC voltage;a second power supply line for transmitting a second DC voltage lower than the first DC voltage;a drive transistor coupled between the first and second power supply lines and supplying a drive current according to a voltage of a control electrode from the first power supply line to the second power supply line;an error amplifier which changes the voltage of the control electrode toward either a first voltage in a direction of increasing the drive current or a second voltage in a direction of decreasing the drive current on the basis of a difference voltage between a reference voltage and the second DC voltage; anda clamp circuit, when the second DC voltage exceeds a predetermined voltage higher than the reference voltage, which changes the voltage of the control electrode toward the second voltage.2. The semiconductor device according to claim 1 ,wherein the drive transistor is an n-type field effect transistor, andwherein when the second DC voltage exceeds the predetermined voltage, the clamp circuit decreases the voltage of the control electrode.3. The semiconductor device according to claim 1 ,wherein the drive transistor is a p-type field effect ...

APPARATUS, SYSTEM, AND METHOD FOR VOLTAGE SWING AND DUTY CYCLE ADJUSTMENT

Described herein are an apparatus, system, and method for compensating voltage swing and duty cycle of a signal on an input-output (I/O) pad of a processor by adjusting the voltage swing and duty cycle of the signal. The apparatus comprises a driver to transmit a signal on an I/O pad, the signal on the I/O pad having a voltage swing and a duty cycle; and an adjustment unit, coupled to the driver, to receive the signal from the I/O pad transmitted by the driver and to generate voltage swing and duty cycle control signals for adjusting the voltage swing and duty cycle of the signal on the I/O pad respectively. Described herein is also an analog-to-digital (A2D) converter for measuring and/or calibrating various signal attributes including current, voltage, and time. 1. An analog-to-digital (A2D) converter comprising:a capacitor with first and second terminals;a comparator to compare a voltage signal on the first terminal with a reference voltage signal level;a current source to charge or discharge the capacitor; anda first switch, coupled between the current source and the first terminal, the first switch to control the speed of charging or discharging the capacitor.2. The A2D converter of further comprises a phase detector to compare phases of two signals and to generate a signal to control the switching speed of the first switch.3. The A2D converter of further comprises a multiplexer to generate the two signals by selecting the two signals from multiple signals including phase delayed signals and clock signals.4. The A2D converter of further comprises a counter to receive an output of the comparator and to count up or down in response to a reset signal claim 1 , where the counter to output a signal which represents one of:a current input to the current source;a pulse width of a signal input to the first switch; anda voltage, on the first terminal of the capacitor, relative to a reference voltage.5. The A2D converter of further comprises a second switch to discharge ...

BALANCED AUXILIARY ON TIME GENERATOR FOR MULTIPHASE STACKABLE CONSTANT ON TIME CONTROL ARCHITECTURE

A control circuit configured to control a switching power supply including a ramp generator configured to generate a triangular waveform. A comparator is configured to generate a series of pulse width modulated (PWM) pulses at a first frequency and to regulate the switching power supply. The ramp generator includes a capacitor, a charging current source configured to provide a charging current to charge the capacitor, and a discharging current source configured to provide a discharging current to discharge the capacitor. The ramp generator also includes a closed loop current balancing current source configured to balance the currents from the charging and discharging current sources to establish a substantially zero direct current (DC) bias across the capacitor. The controller also includes a multi-phase configuration to provide a stackable multi-channel architecture. 1. A control circuit configured to control a switching power supply having an output , the control circuit comprising:a ramp generator configured to generate a triangular waveform;a comparator having a first input configured to receive the triangular waveform and a second input configured to receive a first reference voltage, the comparator configured to generate a series of pulse width modulated (PWM) pulses at a first frequency and to regulate the switching power supply;wherein the ramp generator comprises a capacitor, and a current source configured to provide a charging current or discharging current to the capacitor; andwherein the ramp generator further comprises a closed loop current balancing source configured to provide a charging current or discharging current to the capacitor to establish a substantially zero direct current (DC) bias across the capacitor.2. The control circuit as specified in claim 1 , wherein the current balancing source is configured to reduce DC bias at the capacitor.3. The control circuit as specified in claim 1 , wherein the ramp generator comprises a controller ...

Methods and Apparatus for Continuous Current Limiting for FETS in High Inductive Load Systems

An apparatus includes a FET device having a drain terminal, source terminal and a gate terminal; a first supply voltage coupled to the drain terminal of the FET; an output terminal coupled to the source terminal of the FET; a bias current supply coupled to the gate terminal of the FET; a second supply voltage coupled to the gate terminal of the FET; a current sensing circuit coupled to output a sense current proportional to the current flowing through the FET; a current limit comparator coupled to the sense current and comparing the sense current to a predetermined limit current; a pull down current circuit coupled to remove current from the gate terminal of the FET; a current time derivative circuit coupled to the sense current and outputting a sense rate current; and a circuit coupled to receive the sense rate current and coupled to the bias current supply. 1. An apparatus , comprising:an FET having a drain terminal, a source terminal and a gate terminal;a first supply voltage coupled to supply current to a current conduction path between the source terminal and the drain terminal of the FET;an output terminal coupled to receive current flowing through the current conduction path of the FET;a bias current supply coupled to the gate terminal of the FET;a second supply voltage coupled to the gate terminal of the FET;a current sensing circuit coupled to output a sense current proportional to the current flowing through the FET;a current limit comparator coupled to the sense current and comparing the sense current to a predetermined limit current;a pull down current circuit coupled to the current limit comparator and coupled to remove current from the gate terminal of the FET;a current time derivative circuit coupled to the sense current and outputting a sense rate current; anda circuit coupled to receive the sense rate current and coupled to the bias current supply.2. The apparatus of claim 1 , and further including an enable output coupled from the current limit ...

APPARATUS AND METHODS FOR COMPENSATION OF SIGNAL PATH DELAY VARIATION

Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation. 1. An electronic system with compensation for signal path delay variation , the electronic system comprising: a timing circuit configured to generate an output signal based on timing of an input reference signal;', 'an output pin configured to receive the output signal from the timing circuit and', 'a delay compensation circuit configured to provide one or more compensation signals to the timing circuit; and, 'an integrated circuit (IC) comprisinga signal path configured to route the output signal from the output pin to a destination node,wherein the one or more compensation signals are operable to digitally compensate the timing circuit for a variation in delay of the signal path.2. The electronic system of claim 1 , wherein the delay compensation circuit comprises a delay model configured to generate an estimate of the variation in delay based on one or more operating conditions.3. The electronic system of claim 2 , wherein the delay model is configured to receive a temperature signal indicating a temperature condition.4. The electronic system of claim 2 , wherein the IC further comprises an interface ...

SAMPLE-AND-HOLD CIRCUIT WITH RTS NOISE REDUCTION BY PERIODIC MODE SWITCHING

A sample-and-hold-circuit includes an amplifier transistor, a resistor connected between a source terminal of the amplifier and a voltage, a first switch connected in parallel with the resistor, and a second switch connected between a gate terminal of the amplifier transistor and the voltage. When the first switch is closed and the second switch is open, the amplifier transistor is in an inversion mode; and when the first switch is open and the second switch is closed, the amplifier transistor is in an accumulation mode. 1. A sample-and-hold circuit , comprising:an amplifier transistor;a resistor connected between a source terminal of the amplifier transistor and a predetermined voltage;a first switch connected in parallel with the resistor; anda second switch connected between a gate terminal of the amplifier transistor and the predetermined voltage.2. The sample-and-hold circuit according to claim 1 , whereinin a case where the first switch is closed and the second switch is open, the amplifier transistor is in an inversion mode, andin a case where the first switch is open and the second switch is closed, the amplifier transistor is in an accumulation mode.3. The sample-and-hold circuit according to claim 2 , wherein the first switch and the second switch are controlled such that when the first switch is open claim 2 , the second switch is closed;and when the first switch is closed, the second switch is opened.4. The sample-and-hold circuit according to claim 2 , wherein the amplifier transistor is switched between the inversion mode and the accumulation mode in an alternating manner.5. The sample-and-hold circuit according to claim 1 , wherein the source terminal of the amplifier transistor is connected to a bottom terminal of the amplifier transistor.6. The sample-and-hold circuit according to claim 1 , further comprising a clamping transistor claim 1 ,wherein a drain terminal of the clamping transistor is connected to the source terminal of the amplifier ...

LASER DIODE DRIVER DAMPING CIRCUIT

A damping circuit having an input terminal and an output terminal is described. The damping circuit comprises a driver having an input and an output; an RC circuit coupled between the input terminal and the output; and a resistor coupled between the output and the output terminal, wherein the RC circuit delays passing a signal from the output terminal to the input terminal and a low impedance associated with the driver generally reduces ringing. 1. A damping circuit , comprising:an output terminal;a first transistor having a first control node connected to form a first diode, and a first current node coupled with the output terminal;a second transistor having a second control node connected to form a second diode, and a second current node coupled to the first control node of the first transistor;a buffer circuit coupled with the output terminal and the first transistor; anda resistive-capacitive (RC) circuit coupled between the buffer circuit and the second control node of the second transistor.2. The damping circuit of claim 1 , wherein the buffer circuit includes:a third transistor configured to generate a feedback voltage controlled by the second control node of the second transistor and having a delay established by the RC circuit; anda fourth transistor coupled to the third transistor, the fourth transistor configured to damp the output terminal based on the feedback voltage.3. The damping circuit of claim 1 , wherein the first transistor includes a first NPN transistor having:a first collector node configured to receive a first bias current;a first base node as the first control node, the first base node connected to the first collector node to form the first diode; anda first emitter node as the first current node coupled with the output terminal.4. The damping circuit of claim 3 , wherein the second transistor includes a first PNP transistor having:a second emitter node as the second current node coupled to the first base node of the first NPN transistor;a ...

COMPARATOR, AD CONVERTER, SOLID-STATE IMAGE PICKUP DEVICE, ELECTRONIC DEVICE, METHOD OF CONTROLLING COMPARATOR, DATA WRITING CIRCUIT, DATA READING CIRCUIT, AND DATA TRANSFERRING CIRCUIT

The present disclosure relates to a comparator, an AD converter, a solid-state image pickup device, an electronic device, a method of controlling the comparator, a data writing circuit, a data reading circuit, and a data transferring circuit, capable of improving the determining speed of the comparator and reducing power consumption. The comparator includes: a differential input circuit configured to operate with a first power supply voltage, the differential input circuit configured to output a signal when an input signal is higher than a reference signal in voltage; a positive feedback circuit configured to operate with a second power supply voltage lower than the first power supply voltage, the positive feedback circuit being configured to accelerate transition speed when a compared result signal indicating a compared result between the input signal and the reference signal in voltage, is inverted, on the basis of the output signal of the differential input circuit; and a voltage conversion circuit configured to convert the output signal of the differential input circuit into a signal corresponding to the second power supply voltage. The present disclosure can be applied to, for example, a comparator of a solid-state image pickup device. 1. A comparator comprising:a differential input circuit configured to operate with a first power supply voltage, the differential input circuit configured to output a signal when an input signal is higher than a reference signal in voltage;a positive feedback circuit configured to operate with a second power supply voltage lower than the first power supply voltage, the positive feedback circuit being configured to accelerate transition speed when a compared result signal indicating a compared result between the input signal and the reference signal in voltage, is inverted, on the basis of the output signal from the differential input circuit; anda voltage conversion circuit configured to convert the output signal of the ...

WAVEFORM CONVERSION CIRCUIT FOR GATE DRIVER

A waveform conversion circuit for turning a switch device on and off by applying a control signal from a controller to a gate terminal of the switch device is provided. The switch device has the wile terminal, a drain terminal, and a source terminal. The waveform conversion circuit includes a parallel circuit of a first capacitor and a first resistor and a voltage clamp unit. The parallel circuit is coupled between the controller and the gate terminal. The voltage clamp unit is coupled between the gate terminal and the source terminal and configured to clamp a voltage across the gate terminal to the source terminal at a first voltage in an OFF pulse of the control signal and at a second voltage in an ON pulse of the control signal. 1. A waveform conversion circuit for turning a switch device on and off by applying a control signal from a controller to a gate terminal of the switch device , the switch device having the gate terminal , a drain terminal , and a source terminal , the waveform conversion circuit comprising:a parallel circuit of a first capacitor and a first resistor, wherein the parallel circuit is coupled between the controller and the gate terminal of the switch device; anda voltage clamp unit, coupled between the gate terminal and the source terminal of the switch device and configured to clamp a voltage across the gate terminal to the source terminal.2. The waveform conversion circuit of claim 1 , wherein the control signal ranges from a high voltage level to a low voltage level claim 1 , a first voltage is converted from the low voltage level of the control signal claim 1 , and a second voltage is converted from the high voltage level of the control signal.3. The waveform conversion circuit of claim 2 , wherein the waveform conversion circuit converts the control signal to a driving signal ranging from the second voltage to the first voltage.4. The waveform conversion circuit of claim 3 , wherein the voltage is not greater than the low voltage level ...

COMPARATOR, ANALOG-TO-DIGITAL CONVERTER, SOLID-STATE IMAGE PICKUP DEVICE, AND IMAGE PICKUP APPARATUS

In a comparator of an analog-to-digital converter, an input signal is input to a control terminal of each of a plurality of signal input transistors. A signal input transistor selection section selects any one of the plurality of signal input transistors, and generates a current in response to a difference between the input signal and a reference signal to flow in the differential pair configured with the selected signal input transistor and a reference input transistor. A load section converts, at a time of a change of a current flowing in any one of the plurality of signal input transistors and the reference input transistor in response to the difference, the change of the current into a change of a voltage, and outputs the change of the voltage as a result of comparison between the input signal and the reference signal. 1. A comparator comprising:a plurality of signal input transistors each having a control terminal to which an input signal is input;a reference input transistor configuring, together with each of the plurality of signal input transistors, a differential pair, and having a control terminal to which a reference signal is input;a signal input transistor selection section selecting any one of the plurality of signal input transistors, and generating a current in response to a difference between the input signal and the reference signal to flow in the differential pair configured with the selected signal input transistor and the reference input transistor; anda load section converting, at a time of a change of a current flowing in any one of the plurality of signal input transistors and the reference input transistor in response to the difference, the change of the current into a change of a voltage, and outputting the change of the voltage as a result of comparison between the input signal and the reference signal.2. The comparator according to claim 1 , wherein the signal input transistor selection section selects the one signal input transistor by ...

Delay Line System and Switching Apparatus with Embedded Attenuators

Systems, methods, and apparatus for reducing standing wave reflections between delay line modules are described. The delay line modules include semiconductor switches, particularly MOSFET switches fabricated on silicon-on-insulator (“SOI”) and silicon-on-sapphire (“SOS”) substrates and embedded attenuators.

HIGH PERFORMANCE REPEATER

A redriver device is provided to receive signals from a first device and forward the signals to a second device on a differential link. Detection circuitry is provided to detect presence of the second device on the link by detecting a pulldown voltage generated from termination of the second device on the link, and pulldown relay circuitry is provided to generate an emulated version of the pulldown voltage of the second device on pins to connect to the first device in response to detecting presence of the second device on the link. 1. An apparatus comprising:a redriver device to receive signals from a first device and forward the signals to a second device on a differential link;detection circuitry to detect presence of the second device on the link, wherein detecting the presence of the second device comprises detecting a pulldown voltage generated from termination of the second device on the link; andpulldown relay circuitry to generate an emulated version of the pulldown voltage of the second device on pins to connect to the first device in response to detecting presence of the second device on the link.2. The apparatus of claim 1 , wherein the emulated voltage corresponds to a voltage identifiable by the first device to determine that the second device is present on the link.3. The apparatus of claim 2 , wherein the emulated voltage corresponds to a voltage defined for a receiver detect link state.4. The apparatus of claim 3 , wherein the emulated voltage is to cause a transition from the receiver detect link state to another link state defined in a link state machine.5. The apparatus of claim 4 , wherein the other link state comprises another link training state prior to entry into an active link state.6. The apparatus of claim 1 , wherein the redriver device interrupts electrical propagation of the pulldown voltage from the second device to the first device on the link.7. The apparatus of claim 1 , wherein the redriver device comprises an AC-coupled redriver ...

Method and Apparatus for Reducing the Contribution of Noise to Digitally Sampled Signals

The contribution of noise to digitally sampled signals is reduced using a statistical processor and a slope limiter. The statistical processor determines an average value (mean and/or standard deviation) of the filtered signal which is used to determine a slope limit corresponding to an expected maximum first derivative value of a target signal frequency. This slope limit is applied to constrain the output of an analog to digital converter, to prevent the output of the analog to digital converter from exceeding this maximum rate of rise or fall. By constraining the output of the analog to digital converter, it is possible to digitally sample analog signals without first utilizing an anti-aliasing filter, since the post processing of the digitally sampled signals limits the contribution of the higher frequency components of the signal to thereby enable a fully digital sampling and filtering circuit to be provided for receiving signals. 119-. (canceled)20. Apparatus for reducing noise in digitally sampled signals , the apparatus comprising:an analog to digital converter configured to sample an analog signal to create a digital representation of the signal without first passing the analog signal through an anti-aliasing filter; anda bandwidth limiter coupled to an output of the analog to digital converter and configured to constrain a bandwidth of an output signal of the analog to digital converter.21. The apparatus of claim 20 , wherein the bandwidth limiter comprises a slope limiter configured to constrain within a limit a rate of rise or fall of the output signal of the analog to digital converter.22. The apparatus of claim 21 , wherein the limit corresponds to a maximum first derivative value of a maximum frequency of an input signal of the analog to digital converter.23. The apparatus of claim 22 , wherein:the analog to digital converter is configured to sample the analog signal at a sampling frequency; andthe maximum frequency of the input signal of the analog to ...

Multi-Voltage to Isolated Logic Level Trigger

Various systems may benefit from interfaces for handling multiple types of inputs. For example, a device with a trigger input from an external device may benefit from an isolated logic level trigger that is capable of addressing multiple types and values of voltage. An apparatus can include an input configured to receive an external trigger input signal having a trigger input voltage. The apparatus can also include circuitry configured to automatically adjust the trigger input voltage to a value configured to be compatible with a provided attached system. A working range of the trigger input voltage can exceed a compatible working range of the provided attached system. 1. An apparatus , comprising:an input configured to receive an external trigger input signal having a trigger input voltage; andcircuitry configured to automatically adjust the trigger input voltage to a value configured to be compatible with a provided attached system, wherein the circuitry comprises a current limiting device;wherein a working range of the trigger input voltage exceeds a compatible working range of the provided attached system.2. The apparatus of claim 1 , wherein the circuitry comprises a rectification section claim 1 , wherein the rectification section is configured to adjust claim 1 , for the trigger input voltage claim 1 , at least one of a polarity or a current type.3. The apparatus of claim 2 , wherein the rectification section of the circuitry comprises a full wave bridge rectifier.4. The apparatus of claim 2 , wherein the circuitry comprises an external ground trigger selection section.5. The apparatus of claim 4 , wherein the external ground trigger selection section comprises a switch configured to enable an external ground trigger when selected.6. The apparatus of claim 2 , wherein the circuitry comprises an isolation section configured to isolate the trigger input voltage from the provided attached system.7. The apparatus of claim 6 , wherein the isolation section ...

SLOPE ENHANCEMENT CIRCUIT FOR SWITCHED REGULATED CURRENT MIRRORS

An object of the disclosure is to provide a slope enhancement circuit, comprising an amplifier and a specific arrangement of capacitors and switches, further comprising a current digital to analog converter (IDAC), in a switched regulated current mirror. A method of sample and hold exploits the transient dynamics of the switched current mirror, to enhance the output current slope during PWM operation. A further object of the disclosure is to provide a low power, high speed switching type of regulated current mirror architecture. Still further, another object of the disclosure is to provide quick response to a sudden demand in current with a high degree of accuracy. Still further, another object of the disclosure is to provide a significant savings in circuit area. 1. A slope enhancement circuit in a switched regulated current mirror , comprising:an operational amplifier, wherein a non-inverting input is configured to receive a reference voltage, and an inverting input is configured to receive a feedback voltage;a first, second, and third switch, wherein said first switch is connected between an output of said operational amplifier and said second switch, said second switch is connected to a gate of an NMOS follower, and said third switch is connected between said gate of said follower and ground; anda first and second capacitor, wherein said first capacitor is connected to said output of said operational amplifier, and said second capacitor is connected to a junction of said first switch and said second switch.2. The circuit of claim 1 , wherein said NMOS follower has a drain connected to an output and a source connected at said inverting input of said operational amplifier.3. The circuit of claim 2 , wherein a current digital to analog converter (IDAC) is configured between said source of said follower and ground.4. The circuit of claim 3 , wherein said first and said second switches are configured to be closed by a pulse-width modulation (PWM) signal claim 3 , ...

CIRCUIT FOR CLAMPING CURRENT IN A CHARGE PUMP

A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump. 1. A charge pump comprising:a first capacitor coupled to an output of the charge pump; a first transistor coupled between a first power supply and a first node, the gate of the first transistor coupled to a first output of a phase detector, and', 'a second transistor coupled between the first node and said first capacitor, the gate of the second transistor coupled to a first bias input; a pump down current path comprising:', 'a third transistor coupled between a second power supply and a second node, the gate of the third transistor coupled to a second output of said phase detector, and', 'a fourth transistor coupled between the second node and the first capacitor, the gate of the fourth transistor coupled to a second bias input;, 'a pump up current path comprisinga first alternate current path coupled to a first intermediate node and said first bias input, the first alternate current path configured to conduct current when said first transistor is switched to an off state;a second alternate current path coupled to a second intermediate node and said second bias input, the second alternate current path configured to conduct current when said third transistor is switched to an off state;wherein said first alternate current path comprises a fifth transistor coupled between the first node and an output node of an analog repeater circuit,wherein said second alternate current path comprises a sixth transistor ...

System and Method for a Power Inverter with Controllable Clamps

A system and method for a power inverter with controllable clamps comprises a first voltage swing path, the first voltage swing path including a first plurality of power transistors, the first voltage swing path producing portions of a positive half-wave of an output signal when active; a second voltage swing path, the second voltage swing path including a second plurality of power transistors, the second voltage swing path producing portions of a negative half-wave of the output signal when active; a first clamping component coupled to the first voltage swing path, the first clamping component forming a freewheeling path for the first voltage swing path, the first clamping component comprising a control terminal, the first clamping component having a first stored charge when the control terminal is in a first state and a second stored charge when the control terminal is in a second state, the first stored charge being greater than the second stored charge; and a second clamping component coupled to the second voltage swing path, the second clamping component forming a freewheeling path for the second voltage swing path, the second clamping component comprising a control terminal, the second clamping component having the first stored charge when the control terminal is in the first state and the second stored charge when the control terminal is in the second state. 1. A device comprising:a first voltage swing path, the first voltage swing path including a first plurality of power transistors, the first voltage swing path producing portions of a positive half-wave of an output signal when active;a second voltage swing path, the second voltage swing path including a second plurality of power transistors, the second voltage swing path producing portions of a negative half-wave of the output signal when active;a first clamping component coupled to the first voltage swing path, the first clamping component forming a freewheeling path for the first voltage swing path, the ...

Image sensor and photodetector

An object of the present technology is to provide an image sensor and a photodetector that are capable of reducing power consumption of an AD conversion unit. The image sensor includes a comparator, in which the comparator includes a differential input unit that includes a first input unit connected to a first capacitance unit and a second input unit connected to a second capacitance unit, a current mirror unit that includes a first resistance element connected to the differential input unit and an NMOS transistor diode-connected via the first resistance element, a second resistance element connected to the differential input unit, and a switch unit provided between the first input unit and a junction between the first resistance element and the NMOS transistor, and between the second input unit and a junction between the second resistance element and the current mirror unit.

Oscillator system

An oscillator system includes a voltage controlled oscillator (VCO) circuit. The VCO circuit includes an output for providing an oscillation signal and input to receive a voltage that controls the frequency of the oscillation signal. The oscillator system includes a frequency to voltage circuit that receives the oscillation signal and produces a voltage that is dependent upon the frequency of the oscillation signal. The oscillator system includes a comparison circuit including an amplifier. The amplifier includes an inverting input, a non inverting input, and an output. During a first phase of the comparison circuit, the non inverting input receives a reference voltage and the inverting input is coupled to the output of the amplifier via a switch and to a capacitor wherein the capacitor samples the voltage of the output. During a second phase of the comparison circuit, the non inverting input receives the voltage produced by the frequency to voltage circuit and the switch between amplifier output and inverting input is open wherein the inverting input is coupled to the capacitor to receive the sampled voltage value. During the second phase, the output of the amplifier is provided to the input of the VCO circuit.

SWITCHING ELEMENT DRIVING CIRCUIT

A switching element driving circuit includes a charge pump circuit and a drive voltage generating circuit. The charge pump circuit generates a boosted voltage. The drive voltage generating circuit generates a drive voltage for driving a switching element from the boosted voltage. The drive voltage generating circuit applies a current to a control terminal of the switching element through a resistor at least in an initial stage and an end stage of an output period during which a signal instructing the switching element to be turned on is outputted, and alleviates a rising and a falling of the drive voltage. A switching frequency of the charge pump circuit is set from 2 MHz to 30 MHz. As a result, generation of radio noise can be restricted in both of the drive voltage generating circuit and the charge pump circuit. 1. A switching element driving circuit comprising:a charge pump circuit that generates a boosted voltage; and generates a drive voltage, for driving at least one voltage driven switching element having an input capacitance at a control terminal, from the boosted voltage generated in the charge pump circuit', 'applies a current to the control terminal of the voltage-driven switching element through a resistor at least in an initial stage and an end stage of an output period during which a signal instructing the voltage-driven switching element to be turned on is outputted, and', 'alleviates a rising and a falling of the drive voltage using the input capacitance, wherein, 'at least one drive voltage generating circuit that'}the charge pump circuit includes a plurality of capacitors and a control circuit,the control circuit switches a voltage, which is applied to one electrode of each of the plurality of capacitors, between a high-potential-voltage and a low-potential-voltage at a predetermined switching frequency to alternately perform a charging and a discharging of each of the plurality of capacitors, the control circuit integrates charges of the plurality ...

POWER SUPPLY CIRCUIT

A power supply circuit has, for example, an overshoot suppressor , a control circuit , a first transistor M, a second transistor M, an inductor L, a capacitor C, resistors R and R, and an error amplifier ERR. As the load becomes light, the ON-period of the second transistor M increases. When the load RL turns from a heavy load to a light or no load, the overshoot suppressor detects an increase in the ON-period of the second transistor M, and then forcibly turns OFF the second transistor M. Thus, an overshoot in the output voltage Vo is suppressed. Detecting an increase in the period for which the driving signal S2 remains at high level H helps reduce malfunctioning due to noise. 1. A power supply circuit , comprising:a first transistor connected between a high-potential terminal and a first node;a second transistor connected between a low-potential terminal and the first node;a smoothing circuit connected between the first node and the low-potential terminal;a control circuit configured to turn ON and OFF the first and second transistors alternately such that an output voltage at an output terminal connected to the smoothing circuit equals a predetermined voltage; andan overshoot suppressor configured to turn OFF the second transistor on detecting an increase in an ON-period of the second transistor as observed when the second transistor is turned ON this time compared with the ON-period of the second transistor as observed when the second transistor was turned ON last time.2. The power supply circuit of claim 1 , wherein the overshoot suppressor includes:a pulse width-voltage converter configured to convert the ON-period of the second transistor as observed when the second transistor is turned ON into a voltage;a holder configured to hold a peak value of the voltage generated by the pulse width-voltage converter and to output a voltage that was held last time; anda comparator configured to compare the voltage generated by the pulse width-voltage converter with the ...

METHOD AND APPARATUS FOR CONTROLLING THRESHOLD VOLTAGE

A method and an apparatus for controlling a threshold voltage are provided. The method includes receiving noise event signals from a sensing core, the sensing core sensing a portion of a moving object, and generating an event signal. The method further includes determining a type of the noise event signals, determining a number of the noise event signals based on the type of the noise event signals, determining whether the number of the noise event signals satisfies a condition, and controlling a threshold voltage value corresponding to the noise event signals in response to the determining that the number of the noise event signals does not satisfy the condition. 1. A threshold voltage control method comprising:receiving noise event signals from a sensing core, the sensing core sensing a portion of a moving object, and generating an event signal;determining a type of the noise event signals;determining a number of the noise event signals based on the type of the noise event signals;determining whether the number of the noise event signals satisfies a condition; andcontrolling a threshold voltage value corresponding to the noise event signals in response to the determining that the number of the noise event signals does not satisfy the condition.2. The threshold voltage control method of claim 1 , wherein the noise event signals are output from the sensing core on which light having a constant intensity is incident.3. The threshold voltage control method of claim 1 , wherein the determining the type of the noise event signals comprises determining each of the noise event signals as either an ON event signal or an OFF event signal.4. The threshold voltage control method of claim 1 , wherein the determining the number of the noise event signals comprises:determining a number of ON event signals among the noise event signals; anddetermining a number of OFF event signals among the noise event signals.5. The threshold voltage control method of claim 1 , wherein the ...

ISOLATED OUTPUT SWITCHING CIRCUIT

A semiconductor device includes an output switching device having an input node, an output node, and a control input node. The control input node enables an input voltage applied to the input node to be switched to the output node. A gate pull-down circuit controls the control input node of the output switching device in response to at least one control signal. The gate pull-down circuit activates the output switching device by raising the voltage level of the control input node above the voltage level of the output node and deactivates the output switching device by clamping the control input node to the voltage level of the output node. A gate pull-up circuit receives an enable signal and generates the at least one control signal to the gate pull-down circuit in response to the enable signal. 1. A semiconductor device comprising:an output switching device having an input node, an output node, and a control input node, the control input node enables an input voltage applied to the input node to be switched to the output node;a gate pull-down circuit to control the control input node of the output switching device in response to at least one control signal, the gate pull-down circuit activates the output switching device by raising the voltage level of the control input node above the voltage level of the output node and deactivates the output switching device by clamping the control input node to the voltage level of the output node; anda gate pull-up circuit that receives an enable signal and generates the at least one control signal to the gate pull-down circuit in response to the enable signal.2. The semiconductor device of claim 1 , wherein the gate pull-down circuit includes at least one transistor device to apply a voltage to the control input node to activate and deactivate the output switching device.3. The semiconductor device of claim 2 , wherein the gate pull-up circuit further comprises a slope control circuit to control a slope of the rise and fall ...

SLICER AND METHOD OF OPERATING THE SAME

A slicer includes a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal. The first latch further includes a developing transistor configured to receive a second clock signal, wherein the first clock signal is different from the second clock signal. The first latch further includes a first input transistor configured to receive a first input. The first latch further includes a second input transistor configured to receive a second input, wherein the first and second input transistors are connected with the developing transistor. The first latch further includes at least one pre-charging transistor configured to receive a third clock signal, wherein the at least one pre-charging transistor is connected to a first output node and a second output node. The slicer further includes a second latch connected to the first and second output nodes and to a third output node. 1. A slicer comprising: [{'b': 1', '2, 'an evaluating transistor (N) configured to receive a first clock signal (CKP);'}, {'b': 2', '2, 'i': 'X', 'a developing transistor (N) configured to receive a second clock signal (CKP), wherein the first clock signal is different from the second clock signal;'}, {'b': '3', 'a first input transistor (N) configured to receive a first input (IN);'}, {'b': '4', 'a second input transistor (N) configured to receive a second input (IP), wherein the first and second input transistors are connected with the developing transistor;'}, {'b': 1', '2', '2', '3, 'at least one pre-charging transistor (P and P) configured to receive a third clock signal (CKP or CKP), wherein the at least one pre-charging transistor is connected to a first output node (A) and a second output node (B); and'}], 'a first latch, the first latch comprisinga second latch connected to the first and second output nodes and to a third output node.25. The slicer of claim 1 , wherein the first latch further comprises a connecting transistor (P) configured to ...

LEVEL SHIFTER

A level shifter () is presented comprising an input branch () and an output branch (). The input branch comprises a first switch (), a voltage clamping unit () and a controllable current source () in series. The output branch () comprises a second switch () and a third switch () in series, the second switch () and third switch () having opposite polarities. An output (OUT, ) is provided between the second and the third switch (). The current source () is controlled by an input signal (IN) and the output signal (OUT). The first switch () is controlled by the input signal (IN). Switching control terminals () of the second and the third switch are connected on either side of the clamping unit (). This reduces voltage swing of switching control units, thus resulting in fast switching, less power consumption and wider voltage ranges. The input branch () draws a current only during level transitions, enabling fast switching and power saving in steady state of the level shifter (). 2. The level shifter according to claim 1 , further comprising a second voltage clamping unit for providing a second clamping voltage claim 1 , such that the first voltage clamping unit and the second voltage clamping unit are provided between the first output control input and the second output control input.3. The level shifter according to claim 2 , further comprising a fourth switch provided in parallel to the second voltage clamping unit claim 2 , the fourth switch comprising a third control input for receiving a third control signal.4. The level shifter according to claim 1 , further comprising a fifth switch provided in parallel to the first clamping unit and the first switch claim 1 , the fifth switch having a fourth control input for receiving the second control signal.5. The level shifter according to claim 4 , wherein the fifth switch and the first switch have the same polarity.6. The level shifter according to claim 1 , wherein the first voltage clamping unit comprises a MOS ...

Systems and Methods to Provide Enhanced Diode Bypass Paths

Systems and methods for efficiently allowing current to bypass a group of solar cells having one or more malfunctioning or shaded solar cells without overwhelming a bypass diode. This can be done using a switch (e.g., a MOSFET) connected in parallel with the bypass diode. By turning the switch on and off, a majority of the bypass current can be routed through the switch, which is configured to handle larger currents than the bypass diode is designed for, leaving only a minority of the current to pass through the bypass diode. 1. A system comprising:one or more bypass diodes connected in series with one another and connected in parallel with a group of series-connected solar cells; andone or more bypass transistors connected in parallel with the one or more bypass diodes and configured to turn on for a predetermined time period, in response to a bypass current passing through the one or more bypass diodes, and to reroute the bypass current from the one or more bypass diodes to the one or more bypass transistors.2. The system of claim 1 , further comprising a one-cell converter connected in parallel with the one or more bypass diodes and the one or more bypass transistors and configured to:upconvert a portion of a voltage drop across the one or more bypass diodes to generate an upconverted voltage when the one or more bypass diodes are forward biased to allow the bypass current to pass through the one or more bypass diodes; andcharge a capacitor using the upconverted voltage to control the time period.3. The system of claim 2 , wherein the capacitor is configured to turn the one or more bypass transistors on when a timer allows a control signal from the capacitor to reach the one or more bypass transistors.4. The system of claim 2 , wherein the capacitor is not charged when the one or more bypass diodes are not sufficiently forward biased to allow a bypass current to pass through the one or more bypass diodes.5. A method comprising:charging a capacitor of a controller ...

WAVEFORM CONVERSION CIRCUIT FOR GATE DRIVER

A waveform conversion circuit for converting a control signal of a control node ranging from a high voltage level to a low voltage level of a reference node into a driving signal of a first node is provided. The waveform conversion circuit includes a first resistor, a first capacitor, a unidirectional conducting device, and a voltage clamp unit. The first resistor and the first capacitor are in parallel and coupled between the control node and the first node. The unidirectional conducting device unidirectionally discharges the first node to the control node. The voltage clamp unit is coupled between the first node and the reference node and configured to clamp a driving signal. 1. A waveform conversion circuit for converting a control signal of a control node ranging from a high voltage level to a low voltage level of a reference node into a driving signal of a first node , the waveform conversion circuit comprising:a first resistor, coupled between the control node and the first node;a first capacitor, coupled between the control node and the first node;a unidirectional conducting device, unidirectionally discharging the first node to the control node; anda voltage clamp unit, coupled between the first node and the reference node, wherein the voltage clamp unit is configured to clamp the driving signal.2. The waveform conversion circuit of claim 1 , further comprising:a second resistor, coupled between the control node and the first capacitor.3. The waveform conversion circuit of claim 1 , further comprising:a third resistor, coupled between the unidirectional conducting device and the control node.4. The waveform conversion circuit of claim 1 , wherein a first voltage is converted from the low voltage level of the control signal and a second voltage is converted from the high voltage level of the control signal claim 1 , wherein the driving voltage ranges from the second voltage to the first voltage.5. The waveform conversion circuit of claim 4 , wherein the ...

SWITCH BIASING USING ISOLATED NEGATIVE AND POSITIVE BIAS CIRCUITRY

A switch control circuit includes a positive voltage bias node, a voltage-regulated positive supply rail coupled to the positive voltage bias node, a charge pump coupled to a charge pump supply node, and a current source positive supply rail coupled to the charge pump supply node and configured to supply the charge pump. 1. A switch control circuit comprising:a positive voltage bias node;a voltage-regulated positive supply rail coupled to the positive voltage bias node;a charge pump coupled to a charge pump supply node; anda current source positive supply rail coupled to the charge pump supply node and configured to supply the charge pump.2. The switch control circuit of claim 1 , wherein the positive voltage bias node is at least partially isolated from the charge pump supply node.3. The switch control circuit of further comprising over-voltage protection clamp circuitry coupled to the charge pump supply node.4. The switch control circuit of wherein the over-voltage protection clamp circuitry includes a diode and a capacitor in parallel.5. The switch control circuit of wherein the over-voltage protection clamp circuitry includes a comparator circuit.6. The switch control circuit of wherein the over-voltage protection clamp circuitry includes a diode stack.7. The switch control circuit of further comprising level shifter circuitry configured to receive a positive bias voltage from the positive voltage bias node and receive a negative bias voltage from the charge pump.8. The switch control circuit of wherein the level shifter circuitry is further configured to provide a bias output to control one or more transistors of a switch circuit.9. The switch control circuit of further comprising a first transistor having a drain or source coupled to the positive voltage bias node and a second transistor having a drain or source coupled to the charge pump supply node.10. The switch control circuit of further comprising an amplifier having an output coupled to a gate of the ...

Superconducting clock conditioning system

One example includes a superconducting clock conditioning system. The system includes a plurality of inductive stages. Each of the plurality of inductive stages includes an inductive signal path that includes at least one inductor and a Josephson junction. The superconducting clock conditioning system is configured to receive an input AC clock signal and to output a conditioned AC clock signal having an approximately square-wave characteristic and having a peak amplitude that is less than a peak amplitude of the input AC clock signal.

HIGH VOLTAGE FAIL-SAFE IO DESIGN USING THIN OXIDE DEVICES

A high-voltage fail-safe input/output (I/O) interface circuit includes a voltage-divider circuit coupled to an I/O pad of the I/O interface circuit, and a selector circuit configured to couple, to a power supply line of the I/O interface circuit one of an output of the voltage-divider circuit or and I/O supply voltage. The voltage-divider circuit and the selector circuit are implemented on the same chip with the I/O interface circuit. 1. A high-voltage fail-safe input/output (I/O) interface circuit , the circuit comprising:a voltage-divider circuit coupled to an I/O pad of the I/O interface circuit; anda selector circuit configured to couple, to a power supply line of the I/O interface circuit one of an output of the voltage-divider circuit or an I/O supply voltage, wherein:the voltage-divider circuit and the selector circuit are implemented on the same chip as the I/O interface circuit.2. The circuit of claim 1 , wherein the I/O supply voltage comprises a high supply voltage and is used to generate a lower supply voltage claim 1 , wherein the lower supply voltage is larger than a core supply voltage.3. The circuit of claim 1 , the selector circuit comprises a multiplexer claim 1 , wherein the multiplexer is configured to select one of an output of the voltage-divider circuit or the I/O supply voltage based on a fail-safe detection signal.4. The circuit of claim 3 , further comprising a fail-safe detection logic circuit claim 3 , wherein the fail-safe detection logic circuit is configured to generate the fail-safe detection signal based on the I/O supply voltage not being available.5. The circuit of claim 1 , wherein the voltage-divider circuit is configured to generate a voltage that is a percentage of a magnitude of an input signal coupled to the I/O pad.6. The circuit of claim 1 , further comprising an internal clamp circuit configured to clamp the I/O supply voltage to a low voltage to prevent voltage overstresses on the I/O interface circuit during a fail-safe ...

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Provided is a semiconductor integrated circuit device that has a high-voltage analog switch circuit and is operable at a low power-supply voltage. 1. A semiconductor integrated circuit device , including a high-voltage MOSFET in a semiconductor region arranged on a main surface of a semiconductor substrate via an insulating substrate , the semiconductor integrated circuit device comprising:a first high-voltage MOSFET of a first conductive type having a source terminal, a drain terminal, and a gate terminal;a second high-voltage MOSFET of the first conductive type having a source terminal connected to the source terminal of the first high-voltage MOSFET, a gate terminal connected to the gate terminal of the first high-voltage MOSFET, and a drain terminal; anda first floating gate voltage control circuit configured to operate at a voltage within the range between a voltage exceeding a ground voltage and a voltage of 5 V or lower as a power-supply voltage and control on/off states of the first high-voltage MOSFET and the second high-voltage MOSFET according to a first control signal, the first floating gate voltage control circuit being connected to a source terminal of the first high-voltage MOSFET and a gate terminal of the first high-voltage MOSFET, andwhen turning on the first high-voltage MOSFET and the second high-voltage MOSFET, the first floating gate voltage control circuit setting a voltage in the source terminal of the first high-voltage MOSFET as a reference voltage, adding a floating voltage corresponding to the power-supply voltage to the reference voltage, and supplying the floating voltage to the gate terminals of the first high-voltage MOSFET and the second high-voltage MOSFET.2. The semiconductor integrated circuit device according to claim 1 , whereinthe first floating gate voltage control circuit includes a latch circuit that holds the voltage to be supplied to the gate terminals of the first high-voltage MOSFET and the second high-voltage MOSFET,a ...

SENSORS, AUTONOMOUS SENSORS AND RELATED SYSTEMS, METHODS AND DEVICES

Disclosed embodiments relate to sensing states and changes of states of a signal and sensors for the same, including but not limited to, autonomous sensors. Such sensor may include an analog signal threshold detection circuit, a state detection circuit, and a measurement circuit. The analog signal threshold detection circuit may be configured to alternately assert and de-assert a threshold detected indication in response to an input signal and a state thereof. The state detection circuit may be configured to generate a signal state indication about a state of the input signal. The measurement circuit may be configured to generate a measurement in response to assertions of the threshold detected indication and the signal state indication, such as a count, a slew rate, or a frequency. In some embodiments, disclosed sensors may have programmable thresholds for sensing the signal states and changes therein. 1. A sensor , comprising:a state detection circuit configured to generate a signal state indication about a state of an observed signal;an analog signal threshold detection circuit configured to alternately assert and de-assert a threshold detected indication responsive to the observed signal and the signal state indication; anda measurement circuit configured to generate a measurement responsive to assertions and de-assertions of the threshold detected indication and the signal state indication.2. The sensor of claim 1 , wherein the state detection circuit is configured to generate the signal state indication responsive to assertions and de-assertions of the threshold detection indication and a previous state of the observed signal.3. The sensor of claim 1 , wherein the analog signal threshold detection circuit comprises an analog signal threshold detector configured to:assert the threshold detected indication responsive to a first relationship between a fixed-level reference signal and the observed signal; andde-assert the threshold detected indication responsive ...

METHODS AND APPARATUS FOR A TRACK AND HOLD AMPLIFIER

Various embodiments of the present technology may comprise methods and apparatus for a track-and-hold amplifier configured to sample and amplify an analog signal. Methods and apparatus for a track-and-hold amplifier according to various aspects of the present invention may comprise an isolation circuit configured to isolate transient current in a track-and-hold capacitor during a track phase. According to various embodiments, selective activation of the isolation circuit provides a settling time that is independent of the gain of the amplifier. 1. A track-and-hold amplifier circuit configured to be coupled to a supply voltage and a first reference voltage and receive an input signal , comprising:a gain setting element coupled to the input signal;a cascode circuit coupled to the gain setting element; a first capacitor terminal; and', 'a second capacitor terminal; and, 'a track-and-hold capacitor comprisingan isolation circuit, coupled to the track-and-hold capacitor and the cascode circuit, and configured to selectively isolate transient current in the track-and-hold capacitor and redirect the transient current through at least a portion of the cascode circuit.2. The track-and-hold amplifier according to claim 1 , further comprising a first current source claim 1 , wherein the first current source is:coupled to the cascode circuit and the gain setting element at a first node; andselectively coupled to the track-and-hold capacitor.3. The track-and-hold amplifier according to claim 1 , wherein the isolation circuit comprises: a first terminal; and', 'a second terminal;', the first terminal is coupled to the second capacitor terminal at a third node; and', 'the second terminal is coupled to the cascode circuit;, 'wherein], 'a third transistor comprisinga second current source coupled to the third node; anda switch coupled between the second terminal and the first reference voltage.4. The track-and-hold amplifier according to claim 3 , wherein:the third transistor ...

Memory Interface Receivers Having Pulsed Control Of Input Signal Attenuation Networks

Receivers for memory interfaces and related methods are disclosed having pulsed control of input signal attenuation networks. Embodiments include a DC common mode attenuation network, an AC coupling network, a pulse generator, and an amplifier. The pulse generator receives the output of the amplifier and generates a pulse signal that in part controls the operation of the attenuation network. The attenuation network generates an attenuated signal having reduced DC common mode levels. This attenuated signal is combined with an AC component passed by the AC coupling network. The resulting combined signal is detected and amplified by the amplifier. Different voltage domains are used for the attenuation network and the AC coupling network as compared to the amplifier and the pulse generator. By attenuating DC common mode levels while maintaining AC signal levels, the disclosed embodiments allow for proper signal detection over a wide range of DC common mode levels. 1. An interface receiver , comprising:an attenuation network coupled to receive an input signal having a voltage swing around a DC common mode voltage level within a first voltage domain, the attenuation network being configured to attenuate the DC common mode voltage level and the voltage swing for the input signal and to output an attenuated signal;an amplifier configured to receive the attenuated signal and to output an amplified signal within a second voltage domain; anda pulse generator configured to generate a pulse signal within the second voltage domain based upon the amplified signal and to provide the pulse signal to the attenuation network to at least in part control operation of the attenuation network;wherein the second voltage domain has a lower supply voltage level than the first voltage domain.2. The interface receiver of claim 1 , wherein the pulse signal is coupled to control one or more switches within the attenuation network.3. The interface receiver of claim 2 , where in the attenuation ...

APPARATUS COMPRISING A DIFFERENTIAL AMPLIFIER

To make it possible to use a transistor with relatively low gate withstand voltage at an output stage in an apparatus including a differential amplifier. An apparatus is provided. The apparatus includes: a differential amplifier having a first current path and a second current path that form a differential pair; a first output-stage transistor that has: a first main terminal connected on a power-supply potential side; a second main terminal connected on a reference-potential side; and a control terminal connected to the second current path; and a first voltage-clamp circuit connected between the control terminal and second main terminal of the first output-stage transistor. 1. An apparatus comprising:a differential amplifier having a first current path and a second current path that form a differential pair;a first output-stage transistor that has: a first main terminal connected on a power-supply potential side; a second main terminal connected on a reference-potential side; and a control terminal connected to the second current path; anda first voltage-clamp circuit connected between the control terminal and second main terminal of the first output-stage transistor.2. The apparatus according to claim 1 , further comprising a second voltage-clamp circuit connected between the first current path of the differential amplifier and a reference potential.3. The apparatus according to claim 2 , wherein a first differential-input transistor including: a first main terminal provided on the power-supply potential side in the first current path; a second main terminal provided on the reference-potential side in the first current path; and a control terminal that receives first differential input;', 'a second differential-input transistor including: a first main terminal provided on the power-supply potential side in the second current path; a second main terminal provided on the reference-potential side in the second current path; and a control terminal that receives second ...

Reverse Current Protection Circuit

In described examples, a power interface subsystem includes power transistors, each having: a conduction path coupled between a battery terminal and an accessory terminal; and a control terminal. A differential amplifier has: a first input coupled to the battery terminal; a second input coupled to the accessory terminal; and an output node. An offset voltage source is coupled to cause an offset of a selected polarity at one of the inputs to the differential amplifier. The offset has a first polarity in a first operating mode and a second polarity in a second operating mode. Gate control circuitry is coupled to apply a control level at the control terminal(s) of selected one(s) of the power transistors responsive to a voltage at the output node, and to apply an off-state control level to the control terminal(s) of unselected one(s) of the power transistors. 1. A power interface subsystem for a battery-powered electronic system , comprising:a power transistor having: a source/drain path coupled between a battery terminal and an accessory terminal; and a gate; and an input differential amplifier stage, including first and second input legs, the first leg coupled to the battery terminal, the second leg coupled to the accessory terminal, the first leg including first and second transistors with their source/drain paths connected in series, the second leg including third and fourth transistors with their source/drain paths connected in series, and the first and third transistors having gates connected together at the drain of the second transistor;', 'first and second load devices coupled to the first and second input legs, respectively;', 'an offset voltage source, coupled to the input differential amplifier stage to cause an offset of a selected polarity between the first and second input legs;', 'a replica bias leg including: a replica load device; and first and second replica transistors having their source/drain paths connected in series between the battery terminal ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a first circuit block that is connected between a first power supply voltage line and a first reference voltage line, a second circuit block that is connected between a second power supply voltage line and a second reference voltage line and transmits and receives signals with the first circuit block, a first clamp circuit that clamps a potential difference between the second power supply voltage line and the first reference voltage line, a resistor circuit that is connected between the second power supply voltage line and the second circuit block and includes a resistance value that is greater than an impedance of the first clamp circuit, and a second clamp circuit that clamps a potential difference between a line connected between the resistor circuit and the second circuit block and the first reference voltage line. 1. A semiconductor device comprising:a first circuit block that is connected between a first power supply voltage line and a first reference voltage line;a second circuit block that is connected between a second power supply voltage line and a second reference voltage line and transmits and receives signals with the first circuit block;a first clamp circuit that is connected between the second power supply voltage line and the first reference voltage line and clamps a potential difference between the second power supply voltage line and the first reference voltage line;a resistor circuit that is connected between the second power supply voltage line and the second circuit block and includes a resistance value that is greater than an impedance of the first clamp circuit; anda second clamp circuit that is connected between a line connected between the resistor circuit and the second circuit block and the first reference voltage line and clamps a potential difference between the line connected between the resistor circuit and the second circuit block and the first reference voltage line.2. The semiconductor device ...

Bidirectional Semiconductor Switch with Passive Turnoff

A symmetrically-bidirectional bipolar transistor circuit where the two base contact regions are clamped, through a low-voltage diode and a resistive element, to avoid bringing either emitter junction to forward bias. This avoids bipolar gain in the off state, and thereby avoids reduction of the withstand voltage due to bipolar gain.

PULSE WIDTH MODULATION GENERATED BY A SIGMA DELTA LOOP

A sigma delta (SD) pulse-width modulation (PWM) loop includes a loop filter implementing a linear transfer function to generate a loop filter signal, wherein the loop filter is configured to receive an input signal and a first feedback signal and generate the loop filter signal based on the input signal, the first feedback signal, and the linear transfer function; and a hysteresis comparator coupled to an output of the loop filter, the hysteresis comparator configured to receive the loop filter signal and generate a sigma delta PWM signal based on the loop filter signal, wherein the first feedback signal is derived from the sigma delta PWM signal.

CURRENT LIMITING I/O INTERFACE AND ISOLATED LOAD SWITCH DRIVER IC

Disclosed examples include isolated load switch driver circuits to drive a load, including an impedance circuit that receives a digital input voltage signal from a signal source, and selectively allows a current signal to flow from the signal source to charge a buffer capacitor. An impedance control circuit controls the impedance circuit to limit the current signal in response to the buffer capacitor reaching a first threshold voltage, and an output circuit provides an output isolated from the digital input voltage signal to switch the load. A signaling circuit selectively enables the output circuit to draw power from the buffer capacitor in response to the voltage of the buffer capacitor reaching the first threshold voltage. 1. An integrated circuit (IC) , comprising:a first input pin having a reference voltage;a second input pin to receive a digital input voltage signal having a first voltage relative to the reference voltage in a first state, and a different second voltage relative to the reference voltage in a second state; an impedance circuit, including an input connected to the second input pin, and an output to deliver a current signal to a buffer capacitor, the impedance circuit operative in a first mode to connect the second input pin to the buffer capacitor, and in a second mode to provide a controlled impedance between the second input pin and the buffer capacitor to limit an amplitude of the current signal,', 'a precharge circuit to provide a first signal in response to a supply voltage across the buffer capacitor reaching a first threshold voltage, and', 'an impedance connection control circuit to switch the impedance circuit from the first mode to the second mode in response to the first signal;, 'a current limiter circuit, includingan output circuit, including an input connected to the buffer capacitor to receive the supply voltage, and an output isolated from the supply voltage, the output being connected to third and fourth pins of the IC; anda ...

CURRENT LIMITING I/O INTERFACE AND ISOLATED LOAD SWITCH DRIVER IC

Disclosed examples include isolated load switch driver circuits to drive a load, including an impedance circuit that receives a digital input voltage signal from a signal source, and selectively allows a current signal to flow from the signal source to charge a buffer capacitor. An impedance control circuit controls the impedance circuit to limit the current signal in response to the buffer capacitor reaching a first threshold voltage, and an output circuit provides an output isolated from the digital input voltage signal to switch the load. A signaling circuit selectively enables the output circuit to draw power from the buffer capacitor in response to the voltage of the buffer capacitor reaching the first threshold voltage. 1. An isolated load switch driver circuit , comprising:a signal input to receive a digital input voltage signal;an output circuit to provide a digital output voltage signal isolated from the digital input voltage signal;a buffer capacitor having a first terminal connected to a reference voltage and a second terminal;current limiter circuit, including first and second transistors connected in a back-to-back configuration between the signal input and the second terminal of the buffer capacitor; a first output to provide a first signal to a control terminal of the first transistor to turn the first transistor on in response to the digital input voltage signal transitioning from the reference voltage to a second voltage, and', 'a second output to provide a second signal to a control terminal of the second transistor to turn the second transistor on in response to the digital input voltage signal transitioning from the reference voltage to the second voltage until a voltage of the second terminal of the buffer capacitor reaches a first threshold voltage; and, 'a first control circuit, includinga second control circuit to provide a third signal to the control terminal of the second transistor to limit an amplitude of a current signal flowing from the ...

PHASE INTERPOLATOR

A phase interpolator includes differential pairs, a switching circuit, an output stage, and a correction circuit. The differential pairs generate a first signal and a second signal according to a first group of input signals and a second group of input signals. The switching circuit is turned on or turned off, according to control signals, to transmit the first signal and the second signal to a current source circuit, in order to control a value of the first signal and a value of the second signal. The output stage generates a first output signal according to the first signal and the second signal. The correction circuit provides and stables a common mode voltage of the first output signal according to the first output signal. 1. A phase interpolator , comprising:a plurality of differential pairs configured to generate a first signal and a second signal according to a first group of input signals and a second group of input signals;a switching circuit configured to transmit the first signal and the second signal to a current source circuit and control a value of the first signal and a value of the second signal according to a plurality of control signals;an output stage configured to generate a first output signal according to the first signal and the second signal; anda correction circuit configured to provide a common mode voltage of the first output signal according to the first output signal.2. The phase interpolator of claim 1 , wherein the correction circuit comprises:an amplifier coupled to the output stage, and configured to generate the common mode voltage according to the first output signal and a predetermined voltage.3. The phase interpolator of claim 1 , wherein the correction circuit comprises:a capacitor configured to receive the first output signal, and to output an AC signal;a self-bias resistor configured to generate the common mode voltage according to the AC signal;a buffer configured to generate a second output signal according to the AC signal; ...

DIFFERENTIAL RECEIVER

One example discloses A differential receiver, including: a set of high voltage differential inputs configured to receive a first range of differential voltages; a first level shifter configured to generate a second range of differential voltages that are less than the first range of differential voltages; and a first low voltage differential comparator coupled to the first level shifter and configured to generate a first differential receiver output based on the second range of differential voltages. 1. A differential receiver , comprising:a set of high voltage differential inputs configured to receive a first range of differential voltages;a first level shifter configured to generate a second range of differential voltages that are less than the first range of differential voltages; anda first low voltage differential comparator coupled to the first level shifter and configured to generate a first differential receiver output based on the second range of differential voltages.2. The differential receiver of :wherein the first level shifter includes a set of MOSFETs whose gate-source voltages are configured to reduce the first range of differential voltages to less than the second range of differential voltages.3. The differential receiver of :wherein the first and second first low voltage differential comparators operate at a voltage which is less than a signal range of the high voltage differential inputs.4. The differential receiver of :further comprising a set of voltage clamps;wherein the voltage clamps are configured to limit a voltage received by at least one of the differential comparators.5. The differential receiver of :wherein the differential receiver is embedded in at least one of: a USB connector, or a USB-Type C connector.6. The differential receiver of claim 1 , further comprising:a second level shifter coupled to the first level shifter and configured to generate a third range of differential voltages that are less than the second range of ...

PULSE NOISE SUPPRESSION CIRCUIT AND PULSE NOISE SUPPRESSION METHOD THEREOF

Provided is a pulse noise suppression circuit. The pulse noise suppression circuit includes a filter circuit converting an input signal of a pulse type into an increasing or decreasing filter signal, a level reset circuit resetting the filter signal in response to the input signal and an output signal and an output circuit converting the filter signal into the output signal of a pulse type, wherein the level reset circuit resets the filter signal to have a high level when the input signal and the output signal all have a high level, and resets the filter signal to have a low level when the input signal and the output signal all have a low level. 1. A pulse noise suppression circuit , comprising:a filter circuit converting an input signal of a pulse type into an increasing or decreasing filter signal;a level reset circuit resetting the filter signal in response to the input signal and an output signal; andan output circuit converting the filter signal into the output signal of a pulse type,wherein the level reset circuit resets the filter signal to have a high level when the input signal and the output signal all have a high level, and resets the filter signal to have a low level when the input signal and the output signal all have a low level.2. The circuit of claim 1 , wherein the level reset circuit does not reset the filter signal when the input signal and the output signal have different levels.3. The circuit of claim 1 , wherein the filter circuit comprises a driver circuit adjusting a current amount flowing through the filter circuit.4. The circuit of claim 3 , wherein the driver circuit comprises an inverter lowering a rate of voltage rise of the filter signal.5. The circuit of claim 3 , wherein the driver circuit comprises:a P-channel metal-oxide-semiconductor (PMOS) switch lowering a rate of voltage rise of the filter signal;an N-channel metal-oxide-semiconductor (NMOS) switch lowering the rate of voltage rise of the filter signal;a current source connected ...

CHARGE PUMP MODULE AND VOLTAGE GENERATION METHOD THEREOF

A charge pump module including a ratio control circuit and a charge pump circuit is provided. The ratio control circuit provides a boost ratio based on a control signal. The ratio control circuit includes at least two ratio generation circuits having different boost ratios. The ratio control circuit dynamically switches between the ratio generation circuits to adjust the provided boost ratio based on the control signal. The charge pump circuit is coupled to the ratio control circuit. The charge pump circuit receives an input voltage and converts the input voltage into an output voltage based on the boost ratio provided by the ratio control circuit. Furthermore, a voltage generation method of a charge pump module is also provided. 1. A charge pump module , comprising:a ratio control circuit, providing a boost ratio according to a control signal, wherein the ratio control circuit comprises at least two ratio generation circuits having different boost ratios, and the ratio control circuit dynamically switches between the ratio generation circuits according to the control signal to adjust the provided boost ratio; anda charge pump circuit, coupled to the ratio control circuit, receiving an input voltage, and converting the input voltage into an output voltage according to the boost ratio provided by the ratio control circuit.2. The charge pump module according to claim 1 , wherein the control signal comprises a first period and a second period claim 1 , during the first period claim 1 , the ratio control circuit switches to one of the ratio generation circuits according to the control signal claim 1 , and during the second period claim 1 , the ratio control circuit switches to another one of the ratio generation circuits according to the control signal.3. The charge pump module according to claim 1 , further comprising:a voltage detection circuit, coupled to the charge pump circuit and the ratio control circuit, wherein the voltage detection circuit detects the output ...

LOW LATENCY FILTER

In an embodiment, a set of input samples are filtered to provide a set of filtered samples using an N-tap filter. A steady-state-response-output sample of the N-tap filter is determined from a N/2th sample of the set of filtered samples. 120.-. (canceled)21. An apparatus , comprising:a signal processor configured to generate a value of a transient portion of a processed signal; anda predictor configured to generate a value of a steady-state portion of the signal in response to the value of the transient portion.22. The apparatus of wherein the signal processor is configured to generate the value of the transient portion of the processed signal in response to an input signal.23. The apparatus of wherein the signal processor includes a filter.24. The apparatus of wherein the signal processor includes a finite-impulse-response filter.25. The apparatus of wherein the signal processor includes a low-pass filter.26. The apparatus of wherein:the signal processor is configured to generate a number of samples of the transient portion of the processed signal; andthe value of the transient portion of the processed signal is equal to a value of one of the samples.27. The apparatus of wherein:the signal processor includes a number of taps and is configured to generate, in response to a sample of an input signal, a number of samples of the processed signal that is less than the number of taps; andthe value of the transient portion of the processed signal is equal to a value of one of the samples of the processed signal.28. The apparatus of wherein:the signal processor includes a number of taps and is configured to generate, in response to a sample of an input signal, a number of samples of the processed signal that is equal to half the number of taps; andthe value of the transient portion of the processed signal is equal to a value of a most-recent sample of the processed signal.29. The apparatus of wherein the predictor is configured to generate the value of the steady-state ...

VOLTAGE CLAMPING CIRCUIT

In a general aspect, a circuit can include a pass device configured to receive an input voltage and provide an output voltage. The circuit can further include a current sink coupled with a control terminal of the pass device, the current sink being configured to discharge the control terminal of the pass device to limit the output voltage in response to the input voltage exceeding a threshold voltage. The circuit can also include a switch coupled in series with the current sink, the switch being configured to enable the current sink in response to the input voltage exceeding the threshold voltage. 1. A circuit comprising:a pass device configured to receive an input voltage and provide an output voltage;a current sink coupled with a control terminal of the pass device, the current sink being configured to discharge the control terminal of the pass device to limit the output voltage in response to the input voltage exceeding a threshold voltage; anda switch coupled in series with the current sink, the switch being configured to enable the current sink in response to the input voltage exceeding the threshold voltage.2. The circuit of claim 1 , wherein the switch is configured to disable the current sink in response to the input voltage being less than or equal to the threshold voltage.3. The circuit of claim 1 , further comprising a voltage reference circuit coupled with a control terminal of the current sink claim 1 , the voltage reference circuit being configured to generate a voltage corresponding with the threshold voltage.4. The circuit of claim 3 , wherein the voltage reference circuit is configured to:be enabled in response to the input voltage being greater than the threshold voltage; andbe disabled in response to the input voltage being less than or equal to the threshold voltage.5. The circuit of claim 1 , further comprising an overvoltage detection circuit coupled to a control terminal of the switch claim 1 , the overvoltage detection circuit being ...

REVERSE CURRENT PROTECTION CIRCUIT

In described examples, a power interface subsystem includes power transistors, each having: a conduction path coupled between a battery terminal and an accessory terminal; and a control terminal. A differential amplifier has: a first input coupled to the battery terminal; a second input coupled to the accessory terminal; and an output node. An offset voltage source is coupled to cause an offset of a selected polarity at one of the inputs to the differential amplifier. The offset has a first polarity in a first operating mode and a second polarity in a second operating mode. Gate control circuitry is coupled to apply a control level at the control terminal(s) of selected one(s) of the power transistors responsive to a voltage at the output node, and to apply an off-state control level to the control terminal(s) of unselected one(s) of the power transistors. 1. A power interface subsystem for a battery-powered electronic system , comprising:a power transistor having: a source/drain path coupled between a battery terminal and an accessory terminal; and a gate; and an input differential amplifier stage, including first and second input legs, the first leg coupled to the battery terminal, the second leg coupled to the accessory terminal, the first leg including first and second transistors with their source/drain paths connected in series, the second leg including third and fourth transistors with their source/drain paths connected in series, and the first and third transistors having gates connected together at the drain of the second transistor;', 'first and second load devices coupled to the first and second input legs, respectively;', 'an offset voltage source, coupled to the input differential amplifier stage to cause an offset of a selected polarity between the first and second input legs;', 'a replica bias leg including: a replica load device; and first and second replica transistors having their source/drain paths connected in series between the battery terminal ...

WINDOW REFERENCE TRIMMING FOR ACCESSORY DETECTION

This document discusses, among other things, a detection circuit configured to receive an output of a window comparator over a range of input values and to measure a difference between first and second thresholds of the window comparator, and a trim circuit configured to adjust at least one of the first or second thresholds using the measured difference between the first and second thresholds. 1. An apparatus , comprising:a detection circuit configured to receive an output of a window comparator over a range of input values and to measure a difference between first and second thresholds of the window comparator; anda trim circuit configured to adjust at least one of the first or second thresholds using the measured difference between the first and second thresholds.2. The apparatus of claim 1 , wherein the range of input values includes a voltage across an ID resistor of an accessory device in response to a range of identification (ID) current values.3. The apparatus of claim 1 , wherein the detection circuit is configured to measure the difference between first and second thresholds as a difference between a first input value associated with a first change at the output of the window comparator and a second input value associated with a second change at the output of the window comparator.4. The apparatus of claim 1 , wherein the trim circuit includes a programmable resistor including a plurality of switched resistance units claim 1 , and wherein the trim circuit is configured to adjust at least one of the first or second thresholds using the programmable resistor.5. The apparatus of claim 4 , wherein the detection circuit is configured to detect a median value between the first and second thresholds claim 4 ,wherein the trim circuit includes a programmable current source including a plurality of switched current sources, and wherein the trim circuit is configured to adjust, using the programmable current source, the median value between the first and second ...

PREAMPLIFIER OUTPUT CURRENT CONTROL

One embodiment includes a preamplifier system. The system includes a reference stage configured to set a magnitude of a clamping voltage for a reference node based on a reference current generated in an adjustable reference current path. The system also includes an output stage comprising an adjustable slew current source that is configured to provide an activation current to the reference node in response to at least one activation signal, the output stage to generate an output current at an output of the output stage with a magnitude that is based on the clamping voltage. 1. A preamplifier system comprising:a reference stage configured to set a magnitude of a clamping voltage for a reference node based on a reference current generated in an adjustable reference current path; andan output stage comprising an adjustable slew current source that is configured to provide an activation current to the reference node in response to at least one activation signal, the output stage to generate an output current at an output of the output stage with a magnitude that is based on the clamping voltage.2. The system of claim 1 , wherein the adjustable slew current source is configured to provide the activation current to the reference node to provide the output current with a slew-rate that is based on a magnitude of the activation current.3. The system of claim 2 , wherein the adjustable slew current source is a first adjustable slew current source claim 2 , wherein the output stage comprises a second adjustable slew current source that is configured to generate a deactivation current that is provided from the reference node to provide the output current with a deactivation slew-rate that is based on a magnitude of the deactivation current.4. The system of claim 1 , wherein the adjustable slew current source comprises:a first adjustable slew current source that is activated in response to a first activation signal to provide the activation current to the reference node to ...

COMPARATOR AND LOW POWER CONSUMPTION OSCILLATOR THEREOF

The present invention discloses a comparator and low power consumption oscillator thereof. Wherein, the comparator comprises a current mirror module, a comparison module and a buffering and outputting module, the low power consumption oscillator comprises a capacitor, a current bias module, a switch module and the comparator, the comparison module comprises a positive input end, a first negative input end and a second negative input end, the capacitor connects to the positive input end of the comparator, when a voltage of the capacitor is less than a low threshold voltage of the first negative input end of the comparator, the comparator outputs a low voltage to the switch module, which controls the current bias module to charge the capacitor, when a voltage of the capacitor is greater than a high threshold voltage of the second negative input end of the comparator, the comparator outputs a high voltage to the switch module, which controls the current bias module to discharge the capacitor, thus, through one comparator, a periodic charging and discharging to the capacitor is achieved, and an oscillation signal is output, thus a number of the comparators is reduced, a structure of the circuit is simplified, a power consumption of the circuit and a cost of a product is reduced. 1. A comparator , wherein , it comprises a current mirror module , a comparison module and a buffering and outputting module , the current mirror module provides a bias current to the comparison module , the comparison module comprises a positive input end , a first negative input end and a second negative input end , the positive input end connects to an external terminal , the first negative input end and the second negative input end input a low threshold voltage and a high threshold voltage , respectively , the comparison module compares a voltage of the positive input end to the low threshold voltage and the high threshold voltage , and outputs a comparison result to the buffering and ...

HIGH FREQUENCY SWITCH

There is provided a high frequency switch including: a first signal transferring unit including a plurality of first switching devices; a second signal transferring unit including a plurality of second switching devices; a first shunting unit including a plurality of third switching devices; and a second shunting unit including a plurality of fourth switching devices. 1. A high frequency switch comprising:a first signal transferring unit including a plurality of first switching devices connected to each other in series to enable or block signal flow between a common port and a first port according to a first gate signal controlling the plurality of first switching devices;a second signal transferring unit including a plurality of second switching devices connected to each other in series to enable or block signal flow between the common port and a second port according to a second gate signal controlling the plurality of second switching devices;a first shunting unit including a plurality of third switching devices connected to each other in series to enable or block signal flow between the first port and a ground according to a plurality of third gate signals controlling the plurality of third switching devices; anda second shunting unit including a plurality of fourth switching devices connected to each other in series to enable or block signal flow between the second port and the ground according to a plurality of fourth gate signals controlling the plurality of fourth switching devices.2. The high frequency switch of claim 1 , wherein when the signal flow between the first port and the ground is blocked claim 1 , at least one of the plurality of third switching devices is turned off claim 1 , and at least one thereof is turned on.3. The high frequency switch of claim 1 , wherein when the signal flow between the second port and the ground is blocked claim 1 , at least one of the plurality of fourth switching devices is turned off claim 1 , and at least one ...

Providing Information About A Target Object In A Formatted Output Signal

In one aspect, an integrated circuit (IC) includes a sensor. The sensor includes a processor configured to provide speed and/or direction of a target object based on the speed of the target object; monitor for a diagnostic fault; provide information if the diagnostic fault is detected; monitor for critical faults; and provide information if a critical fault is detected and the sensor recovers from the critical fault. 1. An integrated circuit (IC) comprising: provide speed and/or direction of a target object based on the speed of the target object;', 'monitor for a diagnostic fault;', 'provide information if the diagnostic fault is detected;', 'monitor for critical faults; and', 'provide information if a critical fault is detected and the sensor recovers from the critical fault., 'a sensor comprising a processor configured to2. The IC of claim 1 , wherein the processor is configured to provide speed and/or direction of a target object based on the speed of the target object comprises providing speed and direction of the target in response to the speed of the target being less than or equal to a predetermined speed.3. The IC of claim 2 , wherein the processor is configured to provide speed and/or direction of a target object based on the speed of the target object comprises providing speed only of the target in response to the speed of the target being above the predetermined speed.4. The IC of claim 3 , wherein providing speed only of the target in response to the speed of the target being above the predetermined speed comprises providing speed only of the target in response to the speed of the target being above a first predetermined speed and less than equal to a second predetermined speed.5. The IC of claim 4 , wherein the first predetermined speed is 1 kHz and the second predetermined speed is 10 kHz.6. The IC of claim 1 , wherein the processor is configured to provide information if a diagnostic fault is detected comprises:determining if the diagnostic fault ...

Capacitor Reconfiguration Of A Single-Input, Multi-Output, Switched-Capacitor Converter

A switched capacitor converter and a method for configuring the switched capacitor converter are disclosed. The switched capacitor converter includes a capacitance resource with a cathode and an anode and a switching matrix with a first terminal, a second terminal, a third terminal, and at least one switch configured to switch among two or more connections selected from the group consisting of a connection of the first terminal to the anode and the second terminal to the cathode and a connection of the second terminal to the anode and the third terminal to the cathode. 1. A capacitor bank , comprising:a capacitance resource comprising a cathode and an anode; and a connection of the first terminal to the anode and the second terminal to the cathode;', 'a connection of the first terminal to the anode and the third terminal to the cathode; and', 'a connection of the second terminal to the anode and the third terminal to the cathode., 'a switching matrix comprising a first terminal, a second terminal, a third terminal, and at least one switch configured to switch among two or more connections selected from the group consisting of2. The capacitor bank of claim 1 , wherein the switching matrix further comprises:a first pair of switches configured to switch between connecting the first terminal and the second terminal to the anode; anda second pair of switches configured to switch between connecting the second terminal and the third terminal to the cathode.3. The capacitor bank of claim 2 , wherein the first pair of switches and/or the second pair of switches further comprises a pair of thin-oxide transistors.4. The capacitor bank of claim 3 , wherein for the first and/or second pair of switches claim 3 , a gate of a first thin-oxide transistor of the pair of thin-oxide transistors is connected to a gate of the second thin-oxide transistor of the pair of thin-oxide transistors.5. A single-input multi-output switched-capacitor (SC) power supply claim 3 , comprising:a ...

DETECTOR CIRCUIT AND WIRELESS COMMUNICATION APPARATUS

A detector circuit includes a first inverter including an input node coupled via a first capacitor to a transmission path for transmitting an AC signal, the first inverter outputting an output voltage in accordance with power of the AC signal, wherein the output voltage increases with increasing temperature, a second inverter including an input node coupled to the transmission path, the second inverter outputting an output voltage in accordance with power of the AC signal, wherein the output voltage decreases with increasing temperature, a third capacitor including one electrode coupled to either an output electrode of the first inverter or an output node of the second inverter, a first resistor coupled between the output node of the first inverter and an output node of the detector circuit, and a second resistor coupled between the output node of the second inverter and the output node of the detector circuit. 1. A detector circuit comprising:a first inverter including an input node coupled via a first capacitor to a transmission path for transmitting an AC signal, the first inverter outputting an output voltage in accordance with power of the AC signal, wherein the output voltage increases with increasing temperature;a second inverter including an input node coupled via a second capacitor to the transmission path, the second inverter outputting an output voltage in accordance with power of the AC signal, wherein the output voltage decreases with increasing temperature;a third capacitor including one electrode coupled to either an output electrode of the first inverter or an output node of the second inverter;a first resistor coupled between the output node of the first inverter and an output node of the detector circuit; anda second resistor coupled between the output node of the second inverter and the output node of the detector circuit.2. The detector circuit according to claim 1 ,wherein the first resistor and the second resistor have resistances in accordance ...

COMPARATOR, AD CONVERTER, SOLID-STATE IMAGE PICKUP DEVICE, ELECTRONIC DEVICE, METHOD OF CONTROLLING COMPARATOR, DATA WRITING CIRCUIT, DATA READING CIRCUIT, AND DATA TRANSFERRING CIRCUIT

The present disclosure relates to a comparator, an AD converter, a solid-state image pickup device, an electronic device, a method of controlling the comparator, a data writing circuit, a data reading circuit, and a data transferring circuit, capable of improving the determining speed of the comparator and reducing power consumption. The comparator includes a differential input circuit configured to operate with a first power supply voltage, the differential input circuit configured to output a signal when an input signal is higher than a reference signal in voltage; a positive feedback circuit configured to operate with a second power supply voltage lower than the first power supply voltage, the positive feedback circuit being configured to accelerate transition speed when a compared result signal indicating a compared result between the input signal and the reference signal in voltage, is inverted, on the basis of the output signal of the differential input circuit; and a voltage conversion circuit configured to convert the output signal of the differential input circuit into a signal corresponding to the second power supply voltage. The present disclosure can be applied to, for example, a comparator of a solid-state image pickup device. 1. An imaging device , comprising: a pixel, wherein the pixel includes:', 'a photoelectric converter;', 'a transfer transistor; and', 'a reset transistor; and', 'a first portion of a comparator, wherein the first portion of the comparator includes:', 'a second differential transistor; and', 'a first differential transistor; and'}], 'a first substrate including a second portion of the comparator, wherein the second portion of the comparator includes a first output node; and', 'a feedback circuit coupled to the first output node., 'a second substrate bonded to the first substrate, wherein the second substrate includes2. The imaging device according to claim 1 , wherein the reset transistor is coupled to a gate of the first ...

VOLTAGE CONTROL

This application relates to methods and apparatus for voltage control, and in particular to maintain safe voltages for components of audio driving circuits that are operable in a high voltage mode. An audio driving circuit () may include a power supply module () and may be operable such that, in use, a voltage magnitude at a source terminal of at least a first transistor () of the audio driving circuit can exceed its gate-source voltage tolerance. A voltage generator ( P) is configured to output a first intermediate voltage (V) to an intermediate voltage path for use as a gate control voltage for at least the first transistor, to maintain its gate-source voltage below tolerance. An intermediate path voltage clamp (P) is provided for selectively clamping the intermediate voltage path to a voltage level, so as to maintain the magnitude of the gate-source voltage of the first transistor below tolerance. The voltage clamp (P) is enabled by a reset condition (RST) for the audio driving circuit. 124.-. (canceled)25. An audio driving circuit comprising:a plurality of transistors;a power supply module operable in a first mode to generate at least a first voltage having a first voltage magnitude, wherein the first voltage magnitude is such that, in use in the first mode, for a first set of one or more transistors of said plurality of transistors, a voltage at a source terminal of the transistor of the first set can exceed a gate-source voltage tolerance of that transistor;an intermediate voltage generator configured to, in the first mode, output a first intermediate voltage to an intermediate voltage path to provide a voltage that can be used as a gate control voltage for the one or more transistors of the first set, wherein the first intermediate voltage differs from the first voltage by an amount which is less than the gate-source voltage tolerance of a transistor of the first set; andan intermediate path voltage clamp for selectively voltage clamping the intermediate ...

TRANSMITTER AND RECEIVER

According to one embodiment, a transmitter includes a 1st circuit configured to execute a 1st band limitation by waveform shaping in a time region with respect to 1st data relating to a 1st channel to generate a 1st signal; a 2nd circuit configured to execute a 2nd band limitation by the waveform shaping in the time region with respect to 2nd data relating to a 2nd channel to generate a 2nd signal; a 3rd circuit configured to generate a 3rd signal based on the 1st signal and a 1st frequency relating to the 1st channel; a 4th circuit configured to generate a 4th signal based on the 2nd signal and a 2nd frequency relating to the 2nd channel; and a 5th circuit configured to generate a 5th signal by multiplexing the 3rd signal and the 4th signal. 1. A transmitter comprising:a first circuit configured to execute a first band limitation by waveform shaping in a time region with respect to first data relating to a first channel to generate a first signal;a second circuit configured to execute a second band limitation by the waveform shaping in the time region with respect to second data relating to a second channel to generate a second signal, the second channel differing from the first channel;a third circuit configured to generate a third signal based on the generated first signal and a first frequency relating to the first channel;a fourth circuit configured to generate a fourth signal based on the generated second signal and a second frequency relating to the second channel; anda fifth circuit configured to generate a fifth signal by multiplexing the generated third signal and the generated fourth signal.2. The transmitter of claim 1 , wherein the first circuit is configured:to generate a first waveform relating to the first data;to compare the first data and the second data; andto generate the first signal by increasing an amplitude of the first waveform when the first data and the second data are identical, and by decreasing the amplitude of the first waveform when ...

Method and Apparatus to Clip Incoming Signals in Opposing Directions When in an Off State

A MOSFET active-disable switch is configured to clip an incoming signal in opposing directions when in an off state. By one approach the clipping is symmetrical and accordingly the switch clips both positive and negative peaks of the incoming signal. In many application settings it is useful for the clipping to serve to decrease a predetermined kind of resultant distortion such as even order distortion. In the on state this MOSFET active-disable switch is configured to not clip the incoming signal in opposing directions. 1. A dual metal-oxide-semiconductor field-effect transistor (MOSFET) active-disable switch comprising:a first configuration where the dual MOSFET active-disable switch is in an on state and a second configuration where the dual MOSFET active-disable switch is in an off state;the dual MOSFET active-disable switch further configured to clip an amplitude of an incoming signal in opposing directions when the dual MOSFET active-disable switch is in the off state.2. The dual MOSFET active-disable switch of wherein the dual MOSFET active-disable switch is configured to symmetrically clip the incoming signal when in the off state.3. The dual MOSFET active-disable switch of wherein the dual MOSFET active-disable switch is configured to clip the incoming signal to thereby decrease a predetermined kind of distortion.4. The dual MOSFET active-disable switch of wherein the predetermined kind of distortion comprises even order distortion.5. The dual MOSFET active-disable switch of wherein the dual MOSFET active-disable switch is configured to not clip the incoming signal in opposing directions when in an on state.6. The dual MOSFET active-disable switch of wherein the dual MOSFET active-disable switch includes a first MOSFET having a source claim 1 , drain claim 1 , and gate and a second MOSFET having a source claim 1 , drain claim 1 , and gate claim 1 , wherein:the source of the first MOSFET and the drain of the second MOSFET are connected and comprise a signal ...

Variable Attenuator

A variable attenuator comprises a series resistance, and an adjustable shunt resistance, wherein the adjustable shunt resistance comprises a series circuit of a fixed resistor and a semiconductor element having an adjustable resistance. 1130. A variable attenuator () , comprising:{'b': 132', '1, 'a series resistance (-); and'}{'b': '134', 'an adjustable shunt resistance (),'}{'b': 134', '136', '138, 'sub': '2A', 'wherein the adjustable shunt resistance () comprises a series circuit of a fixed resistor () and a semiconductor element () having a adjustable resistance (R), and'}{'b': 138', '134', '138', '137', '135', '138, 'wherein the semiconductor element () of the first series circuit of the adjustable shunt resistance () is a field-effect transistor (FET) and wherein the field-effect transistor () is configured such that, for a minimum attenuation value in a range of 1 to 3 dB, a voltage applied between a drain () and a source () of the field-effect transistor () is reduced by a voltage reduction value in a range of 10 to 60% as compared to a voltage applied between the drain and source of the field-effect transistor alone.'}21301322101132110213221321132210110213413211322. The variable attenuator () according to claim 1 , further comprising a further series resistance (-) claim 1 , wherein a first port () is connected to the series resistance (-) claim 1 , and wherein a second port () is connected to the further series resistance (-) claim 1 , wherein the second series resistance (-) and the further series resistance (-) are connected in series between the first port () and the second port () claim 1 , and wherein the adjustable shunt resistance () is connected between the series resistance (-) and the further series resistance (-).313013211341321. The variable attenuator () according to claim 1 , wherein the series resistance (-) is connected between a first port and a second port claim 1 , and wherein the adjustable shunt resistance () is connected between the ...

FREQUENCY SELECTIVE LIMITER HAVING REDUCED SPIKE LEAKAGE

Described is a frequency selective limiter (FSL) module comprising a cascade of an FSL and a functional limiter (e.g. a conventional semiconductor limiter comprising a PIN diode) with steady state limiting and power threshold values selected such the FSL module provides suppression of a spike leakage power and while still enabling frequency selective limiting. 1. A frequency selective limiter (FSL) module comprising:an RF ferrite-based FSL; andan RF functional limiter coupled to an output of the ferrite-based FSL, the functional limiter having a power threshold characteristic which is higher than the steady-state limited output power characteristic of the FSL.2. The FSL module of wherein the functional limiter having a power threshold characteristic which is at least 0.25 dB higher than the steady-state limited output power characteristic of the FSL.3. The FSL module of wherein the functional limiter having a power threshold characteristic which is in the range of about 0.25 dB to about 2 db higher than the steady-state limited output power characteristic of the FSL.4. The FSL module of wherein the RF ferrite-based FSL is one of: a polycrystalline ferrite FSL; and a single crystal ferrite FSL claim 1 ,5. The FSL module of wherein the RF ferrite-based FSL is a first one of a plurality of serially coupled RF ferrite-based FSLs.6. The FSL module of wherein the functional limiter is coupled to the RF ferrite-based FSL closest to an output port of the FSL module.7. The FSL module of wherein at least one of the plurality of RF ferrite-based FSLs is a polycrystalline ferrite FSL.8. The FSL module of wherein at least one of the plurality of RF ferrite-based FSLs is a single crystal FSL.9. The FSL module of wherein the RF ferrite-based FSL is a first RF ferrite-based FSL and comprises a polycrystalline ferrite FSL10. The FSL module of further comprising:a second RF ferrite-based FSL corresponding to a single crystal FSL wherein the polycrystalline ferrite FSL is cascade ...

SWITCHING POWER CONVERTER WITH MAGNETIZING CURRENT SHAPING

A switching power converter is provided that uses at least two peak current thresholds. In particular, the switching power converter clamps a desired peak current to not fall below a low peak current threshold value while a rectified input voltage is decreasing and to not fall below a high peak current threshold value subsequent to zero crossing times for an AC input voltage. 1. A method , comprisingrectifying an AC input voltage to produce a rectified input voltage;determining a desired peak current through a power factor control (PFC) feedback loopsetting a peak current threshold to equal a first threshold value prior to a zero crossing time for the AC input voltage and to equal a second threshold value after the zero crossing time, wherein the first threshold value is less than the second threshold value; andcycling a power switch so that power switch conducts a magnetizing current equaling the desired peak current when the desired peak current exceeds the peak current threshold and so that the power switch conducts a magnetizing current equaling the peak current threshold when the desired peak current is less than the peak current threshold.2. The method of claim 1 , wherein the rectified input voltage is decreasing from a maximum value prior to the zero crossing time and is increasing following the each zero crossing time.3. The method of claim 1 , wherein cycling the power switch conducts the magnetizing current through a primary winding in a flyback converter.4. The method of claim 1 , wherein cycling the power switch conducts the magnetizing currents through an inductor in a DC-DC switching power converter.5. The method of claim 4 , wherein the cycling the power switch conducts the magnetizing currents through an inductor in a buck-boost converter.6. The method of claim 1 , wherein determining the desired peak current comprises comparing a feedback voltage to a reference voltage to determine an error signal.7. The method of claim 6 , wherein determining the ...

Current limiter

A current limiter circuit for limiting current through a pass device is disclosed. The current limiter circuit includes a accurate/fast current limiter circuit, a coarse/slow current limiter control circuit and a pass device having an input port, an output port and an on/off control port. A control circuit couple to the accurate/fast current limiter circuit and the on/off control port is also included. The accurate/fast current limiter circuit is coupled to the input port and the output port and the coarse/slow current limiter control circuit is coupled to the input port and the output port and an on/off control port of the accurate/fast current limiter circuit.

SENSOR CONTROLLED TRANSISTOR PROTECTION

A circuit for protecting a transistor is enclosed. The circuit includes a temperature sensing device coupled to the transistor and a tunable clamping circuit connected between transistor terminals, wherein the tunable clamping circuit is configured to provide an adjustable clamping voltage. A temperature controller coupled to the temperature sensing device and the tunable clamping circuit is also included. The temperature controller is configured to trigger a change in a clamping voltage of the tunable clamping circuit based on a feedback from the temperature sensing device. 1. A circuit for protecting a transistor , comprising:a temperature sensing device coupled to the transistor;a tunable clamping circuit connected between transistor terminals, wherein the tunable clamping circuit is configured to provide an adjustable clamping voltage; anda temperature controller coupled to the temperature sensing device and the tunable clamping circuit, the temperature controller is configured to trigger a change in a clamping voltage of the tunable clamping circuit based on a feedback from the temperature sensing device.2. The circuit of claim 1 , wherein the temperature sensing device includes a sense diode that is biased with a pre-selected constant current.3. The circuit of claim 2 , wherein the temperature controller includes a voltage comparator that is coupled to the sense diode.4. The circuit of claim 3 , wherein the voltage comparator includes a first input and a second input claim 3 , the first input is connected to the output of the temperature sensing circuit and the second input is connected to a reference voltage source.5. The circuit of claim 1 , wherein the tunable clamping circuit is connected between the drain and gate terminals of the transistor.6. The circuit of claim 1 , wherein the temperature controller comprises a proportional-integral-derivative (PID) controller to maintain the transistor temperature below a selected maximum temperature.7. The circuit ...

HIGH POWER, SINUSOIDAL LED DRIVER WITH TEMPERATURE STABILIZATION FEEDBACK AND PHOTOMULTIPLIER SYSTEM

A high intensity, ultra-short LED pulsing driver circuit is developed for use with a system designed to perform real-time time-resolved, transient recording of fluorescence. Details of the timing circuitry used to pulse the LED and to provide synchronized PMT gating and ADC trigger pulses are also developed. The LED pulses are intended for fluorophores with lifetimes on the order of about 1.6 ns or longer and gating is used to maintain the detector off or partially off during excitation, thereby maximizing the available detector gain without saturation of the detector by the excitation light. 1. A system effective for time-resolved , transient recording of fluorescent lifetimes , the system comprising:{'b': 101', '101', '102', '101', '102, 'a. a personal computer (PC) graphical interface (), operatively coupled to a microcontroller, wherein the PC () initiates a series of pulses from the microcontroller (), the PC () and microcontroller () collectively referred to as a microcontroller edge trigger;'}{'b': '102', 'b. the microcontroller ();'}{'b': 300', '304, 'claim-text': [{'b': '302', 'i. a signal shaping circuit (), configured to generate a positive rectangular wave pulse signal upon receiving the microcontroller edge trigger, wherein the timing of a rising edge and a falling edge of the positive rectangular wave pulse signal are controlled by adjustable delay elements;'}, {'b': 303', '302', '303', '302, 'ii. a buffer circuit (), operatively connected to the signal shaping circuit (), wherein the buffer circuit () is configured to convert the positive rectangular wave pulse signal of the signal shaping circuit () to a differential pulse,'}], 'c. a light emitting diode (LED) pulsing driver circuit (), operatively connected to an LED (), triggered by the microcontroller edge trigger, the LED pulsing driver circuit comprising{'b': 302', '303', '303', '303', '304, 'wherein when the microcontroller edge trigger is received, the signal shaping circuit () generates a ...

Broadband Power Limiter

A broadband power limiter having a distributed architecture of multiple segments of self-actuating, adjustable power limiters, where the limiter segments are separated from each other along a signal path by intermediate matching inductors. The intermediate matching inductors are chosen to form, in combination with the capacitances of the limiter segments, an impedance matched, low-loss, broadband transmission line. Optionally, limiter segments may be configured with different sizes and stack depths in a “tapered” architecture, such that different limiter segments have different power limiting response times and power handling capabilities. As each limiter segment initiates its power limiting action, power is reflected back toward the signal line, helping to trigger the power limiting action of the remaining limiter segments. Optionally, a power detector circuit may provide a more ideal limiting function by modulating the threshold power point of the limiter segments as a function of the transient signal voltage. 1. A broadband power limiter circuit having a distributed architecture , the broadband power limiter circuit including:(a) a plurality of limiter segments, each limiter segment comprising a stack of one or more self-activating power limiters, each limiter segment separated from an adjacent limiter segment by an associated intermediate matching inductor, each limiter segment configured to initiate limiting of at least one of power, voltage, or current of a signal applied to such limiter segment only when such power, voltage, or current exceeds a set threshold for such limiter segment;(b) a first terminal coupled to a first end one of the plurality of limiter segments; and(c) a second terminal coupled to a second end one of the plurality of limiter segments;wherein the first terminal, the second terminal, and the combined plurality of limiter segments and associated intermediate matching inductors comprise a signal line.2. The invention of claim 1 , wherein at ...

TRIMMING CIRCUIT AND OPERATING METHOD THEREOF

Disclosed herein is a method for trimming a voltage regulator by a trimming circuit comprising a voltage divider configured to divide a divide reference voltage according to a divider code and to output a first divider output voltage, a comparator configured to receive the first divider output voltage and a compare reference voltage and to output an output voltage of the comparator by comparing the first divider output voltage and the compare reference voltage and a logic unit configured to output the divider code to the voltage divider and to determine a final divider code based on the output voltage of the comparator. 1. An operation method of a trimming circuit for a voltage regulator comprising a comparator and a voltage divider , the voltage divider being inserted between the voltage regulator and the comparator and connected thereto , the method comprising:determining a final divider code for the voltage divider by comparing a first divider output voltage and a compare reference voltage; anddetermining a final regulator code for the voltage regulator by comparing a second divider output voltage and a trimming reference voltage,wherein the first divider output voltage is generated by dividing a divide reference voltage according to a divider code inputted to the voltage divider, and the second divider output is generated by dividing an output voltage of the voltage regulator according to the final divider code.2. The method of claim 1 , wherein the determining the final divider code comprises:determining a first divider code; anddetermining a second divider code by inverting signals applied to the comparator.3. The method of claim 2 , wherein the determining the first divider code comprises:applying the first divider output voltage to a non-inverting input of the comparator and the compare reference voltage to an inverting input of the comparator;adjusting the divider code for the voltage divider until the first divider output voltage exceeds the compare ...

SEMICONDUCTOR DEVICE

A semiconductor device is provided that includes an amplification circuit, a downstream circuit, and a clipping circuit. The amplification circuit includes a sampling capacitor, a feedback capacitor, and an operational amplifier circuit. The sampling capacitor holds air input signal on which sampling is performed, as a signal whose reference is a first reference voltage. The signal that is held in the sampling capacitor is transferred to the feedback capacitor. The operational amplifier circuit amplifies the signal that is held in the sampling capacitor, according to a ratio between values of the sampling capacitor and the feedback capacitor, and outputs the amplified signal, as a signal whose reference is a second reference voltage. The clipping circuit limits a voltage of an output signal of the operational amplifier circuit to a predetermined voltage or below. 1. A semiconductor device , comprising:an amplification circuit configured to perform sampling on an input signal and amplify the input signal;a downstream circuit configured to operate in response to an output signal of the amplification circuit; anda clipping circuit, a sampling capacitor configured to hold the input signal on which the sampling is performed, as a signal whose reference is a first reference voltage,', 'a feedback capacitor to which the signal that is held in the sampling capacitor is transferred, and', 'an operational amplifier circuit configured to amplify the signal that is held in the sampling capacitor, according to a ratio between values of the sampling capacitor and the feedback capacitor, and output the amplified signal, as a signal whose reference is a second reference voltage, and, 'wherein the amplification circuit includes'}the clipping circuit is configured to limit a voltage of an output signal of the operational amplifier circuit to a predetermined voltage or below.2. The semiconductor device according to claim 1 ,wherein the first reference voltage is a voltage that is ...

JITTER CANCELLATION WITH AUTOMATIC PERFORMANCE ADJUSTMENT

Methods, systems, and devices for jitter cancellation with automatic performance adjustment are described. Within a clock distribution system in an electronic device (e.g., a memory device), a jitter cancellation system may be configured to introduce delay between an input clock signal and output clock signal that is directly proportional to the supply voltage for the clock distribution system. In response to supply noise, the delay introduced by the jitter cancellation system may vary directly with respect to the supply voltage fluctuations and thus may offset fluctuations in the delay introduced by other components of the clock distribution system, which may vary inversely with respect to the supply voltage fluctuations. A control component within the jitter cancellation system may execute an algorithm to adjust or regulate the delay introduced by the jitter cancellation system, including its responsiveness to fluctuations in the supply voltage. 1. (canceled)2. An apparatus , comprising:a feedback loop configured to receive a first signal and output a second signal;a first circuit configured to introduce, into the feedback loop, a first delay that is based at least in part on a supply voltage; anda second circuit configured to introduce, into the feedback loop, a second delay that is proportional to the supply voltage.3. The apparatus of claim 2 , further comprising:circuitry configured to determine an amount of jitter between the first signal and the second signal and introduce the first delay, the second delay, or both into the feedback loop.4. The apparatus of claim 3 , wherein the circuitry is configured to adjust a current level of a current source based on the amount of jitter claim 3 , wherein the first delay claim 3 , the second delay claim 3 , or both are introduced into the feedback loop based on the level of the current source.5. The apparatus of claim 3 , wherein:the first circuit is configured to introduce the first delay into the feedback loop based ...

Level shifter

The present disclosure provides a level shifter including: a level shifter section that is driven by a first power source voltage, and that, in accordance with switching of an input signal of a voltage lower than the first power source voltage, switches an output signal that has been level-shifted, from the first power source voltage to a voltage lower than the first power source voltage; and a threshold voltage changing circuit that, in accordance with a switching direction of the input signal, changes a threshold voltage of the input signal for switching the output signal.

Solid-state imaging device, electronic apparatus, and ad converter

The present technology relates to a solid-state imaging device, an electronic apparatus, and an AD converter that are capable of suppressing the occurrence of an error in AD conversion results. The solid-state imaging device includes a pixel section having a plurality of pixels, a comparator for comparing a pixel signal outputted from the pixels with a reference signal, and a counter for counting the time of comparison made by the comparator. The comparator includes a first amplifier for comparing the pixel signal with the reference signal, a second amplifier that has a first transistor and amplifies an output signal of the first amplifier, and a second transistor having the same polarity as the first transistor. A gate of the second transistor is connected to an output end of the first amplifier, and a source and a drain of the second transistor are connected to the same fixed potential as a source of the first transistor. The present technology is applicable, for example, to a CMOS image sensor.

Driver circuit charging charge node

Disclosed is a driver circuit. The driver circuit includes a clamp transistor, a comparison voltage transistor, an amplification transistor, a bias transistor, and a charge circuit. The comparison voltage is configured to provide a comparison voltage. The amplification transistor includes an amplification gate connected to a first node of the clamp transistor, a first amplification node configured to receive the comparison voltage, and a second amplification node connected to a gate of the clamp transistor. The bias transistor is configured to supply a bias voltage. The charge circuit is at least one of configured to drain a current from the first node through the clamp transistor and configured to supply a current to the first node through the clamp transistor.

CRYSTAL OSCILLATOR CIRCUIT AND METHOD THEREOF

A crystal oscillator comprises: an inverter configured to receive a first voltage at a first node and output a second voltage at a second node; a feedback network inserted between the first node and the second node, wherein the feedback network includes a serial connection of a first feedback resistor, a clamp network, and a second feedback resistor; a first optional resistor inserted between the second node and a third node; a second optional resistor inserted between a fourth node and the first node; a crystal inserted between the third node and the fourth node; a first shunt capacitor inserted between the third node and a ground node; and a second shunt capacitor inserted between the fourth node to and the ground node. 1. A crystal oscillator comprising:an inverter configured to receive a first voltage at a first node and output a second voltage at a second node;a feedback network inserted between the first node and the second node, wherein the feedback network includes a serial connection of a first feedback resistor, a clamp network, and a second feedback resistor;a crystal inserted between a third node and a fourth node, wherein the third node is coupled to the second node, and the fourth node is coupled to the first node;a first shunt capacitor inserted between the third node and a ground node; anda second shunt capacitor inserted between the fourth node to and the ground node.2. The crystal oscillator of claim 1 , wherein the crystal oscillator further comprises:a first optional resistor inserted between the second node and the third node; anda second optional resistor inserted between the fourth node and the first node.3. The crystal oscillator of claim 1 , wherein the clamp network comprises a parallel connection of a first diode placed in a forward direction claim 1 , a second diode placed in a reverse direction claim 1 , and a feedback capacitor.4. The crystal oscillator of claim 1 , wherein the inverter comprises a NMOS (n-channel metal oxide ...

COMPARATOR AND OSCILLATOR CIRCUIT USING SAID COMPARATOR

Oscillator circuit uses a comparator, and controls charge-discharge of Miller capacitance between gate and drain of a MOSFET serving as an amplifier of the comparator gain unit and gate capacitance of the MOSFET, and enables comparator output to follow a high-frequency control signal that is input externally. An oscillator circuit uses a comparator CMP having differential and gain units. This oscillator circuit includes: a charge-discharge controller to control charge-discharge of Miller capacitance between gate and drain of a MOSFET and gate capacitance of the MOSFET; and an output controller to control output of the gain unit. Output controller includes: an inverter to connect to an input of the differential unit and receive a control signal input; a logic circuit to receive output of the inverter and output of the gain unit as an input; a transistor; and a capacitor to connect to input and output of the logic circuit. 1. A comparator having a differential unit and a gain unit , comprising:a charge-discharge control unit configured to connect to an output of the differential unit and configured to control charge-discharge of Miller capacitance between the gate and the drain of a MOSFET serving as an amplifier of the gain unit and gate capacitance of the MOSFET; andan output control unit configured to control an output of the gain unit,a signal generated at an external terminal of the comparator being input to one of the inputs of the differential unit,the output control unit including:a first inverter configured to receive a signal generated at the external terminal as an input;a first logic circuit configured to receive the output of the first inverter and the output of the gain unit as an input;a first transistor having a drain configured to connect to the output of the gain unit, a source configured to connect to a reference potential of the comparator, and a gate configured to connect to the output of the first logic circuit; anda first capacitor configured to ...

Vehicle throttle locking circuit and method

A vehicle throttle locking circuit and method are provided. A control unit receives detection voltages from a pedal sensor and, when a clamping actuation signal is ON, digital clamping voltages are gradually reduced according to the detection voltages. AD/A conversion unit converts the digital clamping voltages to analog clamping voltages. A variable voltage clamping unit clamps the detection voltages according to the analog clamping voltages. The gradual reduction of the digital clamping voltages are stopped when the detection voltages are already clamped at an idle condition so that the pedal is effectively locked at the idle condition. As such, the present invention not only provides anti-theft function, but also avoids traffic accident and hazard to the safety of the driver or passers due to the vehicle's sudden loss of power.

CHAMFERING CIRCUIT OF ADJUSTABLE CHAMFERED WAVEFORM AND ADJUST METHOD OF CHAMFERED WAVEFORM

The present invention provides a chamfering circuit of adjustable chamfered waveform and an adjust method of a chamfered waveform. The chamfering circuit of adjustable chamfered waveform according to the present invention comprises a digital power source IC (), a first resistor (R), a second resistor (R) and a triode (Tr); wherein the chamfered waveform can be adjusted by adjusting the triode base voltage (VB) outputted by the digital power source IC () to promote the image quality. In comparison with prior art, welding the resistor is not required to accomplish the adjustment of the chamfered waveform. The operation is simple and the work efficiency is high. 1. A chamfering circuit of adjustable chamfered waveform , comprising: a digital power source IC , a first resistor , a second resistor and a triode; wherein the digital power source IC comprises: a TFT activation voltage output terminal and a triode base voltage output terminal;one end of the first resistor is electrically coupled to the TFT activation voltage output terminal of the digital power source IC, and the other end is electrically coupled to an emitter of the triode;a base of the triode is electrically coupled to the triode base voltage output terminal of the digital power source IC, and the emitter is electrically coupled to one end of the second resistor, and a collector is grounded;one end of the second resistor is electrically coupled to the other end of the first resistor, and the other end is grounded;the TFT activation voltage output terminal outputs a TFT activation voltage, and the triode base voltage output terminal outputs a triode base voltage, and the triode base voltage is an adjustable voltage.2. The chamfering circuit of adjustable chamfered waveform according to claim 1 , wherein a chamfered waveform of the TFT activation voltage is adjusted by adjusting the triode base voltage.3. The chamfering circuit of adjustable chamfered waveform according to claim 2 , wherein in a process of ...

System and Method for Circuit Protection

A method for operating a gate driver circuit includes supplying power to the gate driver circuit from a power supply including a positive power supply voltage and a negative power supply voltage. The method also includes comparing the negative power supply voltage with a first voltage at an output terminal of a transistor, wherein the gate driver circuit is coupled to a gate terminal of the transistor. The method also includes operating the gate driver circuit when the negative power supply voltage is more negative than a trigger voltage, wherein the trigger voltage is a predetermined voltage above the first voltage. The method also includes deactivating at least a portion of the gate driver circuit when the negative power supply voltage is more positive than the trigger voltage. 1. A method for operating a gate driver circuit comprising:supplying power to the gate driver circuit from a power supply comprising a positive power supply voltage and a negative power supply voltage;comparing the negative power supply voltage with a first voltage at an output terminal of a transistor, wherein the gate driver circuit is coupled to a gate terminal of the transistor;operating the gate driver circuit when the negative power supply voltage is more negative than a trigger voltage, wherein the trigger voltage is a predetermined voltage above the first voltage; anddeactivating at least a portion of the gate driver circuit when the negative power supply voltage is more positive than the trigger voltage.2. The method of claim 1 , wherein the trigger voltage is between about 0.1V and about 0.5V above the first voltage.3. The method of claim 1 , wherein the trigger voltage above the first voltage by less than a forward operating voltage of a diode.4. The method of claim 1 , wherein the output terminal of the transistor is an emitter terminal or a source terminal.5. The method of claim 1 , wherein the transistor is a MOSFET.6. The method of claim 1 , wherein comparing comprises: ...

SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

According to an embodiment, a semiconductor integrated circuit includes a circuit block provided between a power source voltage line and a reference voltage line, a circuit block provided between a power source voltage line and a reference voltage line, a clamp unit which is provided between the power source voltage line and the reference voltage line and is conductive when it is detected that an ESD voltage is applied using a first time constant, a trigger circuit which causes a trigger signal to be active when it is detected that an ESD voltage is applied using a second time constant smaller than the first time constant, and a transistor which is provided between a signal line, between the circuit blocks, and the power source voltage line or the reference voltage line. 1. A semiconductor integrated circuit comprising:a first circuit block which is provided between a first power source voltage line and a first reference voltage line;a second circuit block which is provided between a second power source voltage line and a second reference voltage line;a clamp unit which is provided between the first power source voltage line and the second reference voltage line, and is conductive when it is detected that an ESD voltage is applied between the first power source voltage line and the second reference voltage line using a first time constant;a trigger circuit which is provided between the first power source voltage line and the second reference voltage line, and causes a trigger signal to be active when it is detected that an ESD voltage is applied between the first power source voltage line and the second reference voltage line using a second time constant smaller than the first time constant; anda switch which is provided between a signal line between the first and second circuit blocks and one of the first power source voltage line and the second reference voltage line, and is ON when the trigger signal is active.2. The semiconductor integrated circuit according to ...