УТРОИТЕЛЬ ЧАСТОТЫ

Полезная модель относится к радиотехнике и связи и может быть использована в качестве умножителя частоты.Устроитель частоты содержит управляемый фазовращатель, компаратор, перемножитель, интегратор, преобразователь частота-напряжение и переключатель полярности, причем вход утроителя частоты соединен с входом управляемого фазовращателя и входом компаратора, выход которого соединен с первым входом перемножителя, выход которого соединен с входом интегратора, выход которого через переключатель полярности соединен с управляющим входом управляемого фазовращателя, выход которого соединен с выходом утроителя частоты, а выход компаратора соединен с управляющим входом переключателя полярности и через преобразователь частота-напряжение со вторым входом перемножителя.Техническим результатом заявляемой полезной модели является повышение точности утроителя частоты. 2 ил.

Блок задержки импульсов

Предлагаемая полезная модель относится к измерительной технике, а именно к устройствам многоканальной программируемой цифровой задержки пускового импульса. Техническим результатом полезной модели является уменьшение погрешности времени задержки пускового импульса при заданной тактовой частоте в ПЛИС. Технический результат достигается тем, что в блоке задержки импульсов, содержащем канал пускового импульса, генератор, микроконтроллер, канал выходного импульса, ПЛИС, содержащую умножитель частоты, четыре триггеры, первый элемент И, первый счетчик задержки, первый счетчик длительности, регистр кода задержки, при этом генератор соединен с входом умножителя частоты, первый выход которого соединен с тактовым входом четырех триггеров и первых счетчиков задержки и длительности; канал пускового импульса соединен с входом второго триггера, выход которого соединен с входом третьего триггера и с первым входом первого элемента И, второй вход которого соединен с инверсным выходом третьего триггера, а ...

Блок задержки импульсов

Предлагаемая полезная модель относится к измерительной технике, а именно к устройствам многоканальной программируемой цифровой задержки пускового импульса. Техническим результатом полезной модели является уменьшение погрешности времени задержки пускового импульса при заданной тактовой частоте в ПЛИС.Технический результат достигается тем, что блок задержки импульсов, содержащий канал пускового импульса, генератор, ПЛИС, содержащую умножитель частоты, четыре D-триггера, два элемента И, четыре S-триггера, два счетчика задержки, два счетчика длительности, элемент ИЛИ, регистр кода задержки, регистр кода длительности; при этом генератор соединен с входом умножителя частоты, первый и второй выходы которого соединены с тактовыми входами соответственно первого, второго D-триггера, первого, второго S-триггера, первого счетчика задержки, первого счетчика длительности, и третьего, четвертого D-триггера, третьего, четвертого S-триггера, второго счетчика задержки, второго счетчика длительности; входы ...

Anordnung zur programmierbaren Verzoegerung eines Signals mit einem Zaehler

Verfahren und Schaltungsanordnung zur Synchronisierung eines Fernseh-Bildsignalgebers

Verzögerungsschaltung

Verzögerungsschaltung, die ein Eingangssignal verzögert, mit einem Eingangsanschluss (102), zu welchem das Eingangssignal geliefert wird, mehreren Verzögerungspfaden (104) mit jeweils mehreren Verzögerungselementen (110, 112, 114), welche Verzögerungspfade (104) zumindest einen ersten Verzögerungspfad (104a) und einen zweiten Verzögerungspfad (104b) aufweisen und parallel mit dem Eingangsanschluss (102) verbunden sind, und einem ersten Verbindungspfad (106a), der elektrisch einen Ausgang eines Verzögerungselements (112a) des ersten Verzögerungspfades (104a) mit einem Eingang eines Verzögerungselements (112b) des zweiten Verzögerungspfades (104b) verbindet, dadurch gekennzeichnet, dass der erste Verbindungspfad (106a) ein variables Verzögerungselement (108a) enthält, das eine grobe Verzögerungsauflösung (ΔT) hat, und dass die die mehreren Verzögerungselemente (110, 112, 114) aufweisenden Verzögerungspfade (104) eine feine Verzögerungsauflösung (Δt) haben.

Schaltung zur Verzoegerung von impulsfoermigen Signalen

Delay circuit for ring oscillator in which delay routes are connected parallel with input terminal

A variable delay circuit (100), comprising delay routes (104a, 104b), connection routes (106a, 106b), and a NAND circuit (146) having a NAND logic of outputs of the delay routes (104a, 104b), wherein the delay routes (104a, 104b) are connected parallel with an input terminal (102), the connection route (106a) connects the output of a delay element (132) contained in the first delay route (104a) electrically to the input of a delay element (140) contained in the second delay route (104b), the connection route (106b) connects the output of the delay element (140) electrically to the input of the delay element (132), and an additional element is provided to the input of a specified delay element so as to uniform the input load of each delay element, whereby the variable delay circuit (100) stabilizing a power current and generating an accurate delay with small scale of circuit can be realized.

Phaseninterpolator

Phaseninterpolatorvorrichtung, umfassend:eine Vielzahl von Stromquellen,eine Vielzahl von Stromauswahlschaltern, die der Vielzahl von Stromquellen zugeordnet sind, um die Stromquellen wahlweise mit mindestens zwei Summierknoten zu koppeln,eine Phasensignaleingangsstufe, die eingerichtet ist, mindestens zwei Eingangssignale zu empfangen, die unterschiedliche Phasen aufweisen, wobei die Phaseneingangsstufe eingerichtet ist, einen ersten Strom von einem ersten Summierknoten der mindestens zwei Summierknoten basierend auf einem ersten Eingangssignal der mindestens zwei Eingangssignale zu modifizieren, um einen ersten modifizierten Strom zu erzeugen, und einen zweiten Strom von einem zweiten Summierknoten der mindestens zwei Summierknoten basierend auf einem zweiten Eingangssignal der mindestens zwei Eingangssignale zu modifizieren, um einen zweiten modifizierten Strom zu erzeugen,eine Ausgangsstufe, die eingerichtet ist, ein Ausgangssignal basierend auf dem ersten modifizierten Strom und dem ...

Verfahren zur Modulation eines Grundtaktes für digitale Schaltungen und Taktmodulator zur Ausführung des Verfahrens

Bei einem Verfahren zur Modulation eines Grundtaktes für digitale Schaltungen, bei dem die Abstände benachbarter Schaltflanken verändert werden, wobei der Grundtakt über eine wechselnde Anzahl von Verzögerungseinheiten geleitet wird und so die Abstände der benachbarten Schaltflanken verändert werden, ist vorgesehen, daß die Verzögerungszeiten der Verzögerungseinheiten kalibriert werden, daß die Verzögerungseinheiten jeweils mehrere Verzögerungsglieder aufweisen, die einzeln und/oder in Gruppen zu- bzw. weggeschaltet werden. Ein Taktmodulator ist entsprechend aufgebaut und betreibbar.

SPEICHERBLOCKAUSWAHL UNTER VERWENDUNG VON MEHREREN WORTLEITUNGEN ZUR ADRESSIERUNG EINER EINZIGEN SPEICHERZELLENZEILE

CMOS delay circuits with improved accuracy by reduction of supply voltage changes

The capacitive charging current flowing in the driver DR of a CMOS delay circuit can cause a variation in the supply voltages and hence reduce the accuracy of the delay. To counteract this effect, a biassing circuit ADC is coupled to the capacitive node LIN in the path of the signal to be delayed. The biassing circuit restricts the voltage swing at the node LIN and so reduces the amplitude of the charging currents injected into the supply rails. Further, the direct rail-to-rail current in the biassing circuit has a voltage dependency complementary to that of the delay node driver so that the overall direct rail-to-rail current consumption is relatively independent of the node voltage. The biassing circuits may be disabled by switch CUT to permit static current testing. The delay circuit may be used in a semiconductor tester or in an oscilloscope.

Delay device, semiconductor testing device, semiconductor device, and oscilloscope

Pulse delay circuit for pulse signals

A phase shifting circuit for shifting a phase of an input pulse signal comprises a first circuit for delaying the input pulse signal so as to produce a first pulse signal having a first pulse width, a second circuit for delaying the first pulse signal so as to produce a second pulse signal having a second pulse width, a smoothing circuit for smoothing the second pulse signal, and a comparing circuit for comparing an output signal level of the smoothing circuit with a predetermined reference level so as to produce a control signal dependent on a difference between the two compared levels. The control signal is supplied to the first and second circuits to control delay times thereof so that the first and second pulse widths respectively become constant. The second delay circuit produces the second pulse signal as an output pulse signal of the phase shifting circuit having a period essentially identical to that of the input pulse signal but having a phase which is shifted by a predetermined ...

A low power clock phase adjustment circuit for a high-speed data link

The phase of a clock signal which is received as a differential signal is adjusted by changing the propagation delay through a differential to single-ended converter. The propagation delay is varied by altering the currents provided by current sources 312,314 to the two input differential pairs 304 and 310, which respectively comprise large and small transistors. This technique allows lower power consumption than adjustable delays using programmable capacitance (figure 2). The adjustment signals may be provided by a controller 414 (figure 4) which acts on four phase adjustment circuits to maintain their outputs at 90 degree intervals.

SIGNAL GENERATING CIRCUIT

Improvements in or relating to time delay generator circuits

... 1,037,532. Pulse delaying circuits. SPACE TECHNOLOGY LABORATORIES Inc. Feb. 20, 1963 [Feb. 20, 1962], No. 6868/63. Heading H3P. A pulse-delaying circuit comprises an adjustable resonant circuit arranged to have a first natural frequency during a first half-cycle of oscillation and a higher natural frequency during subsequent half-cycles. As shown in Fig. 1, capacitors 38a, 36 are normally charged from a source 20 via resistor 18. When thyratron 12 is fired by a pulse 24, capacitor 38a discharges resonantly via inductor 40a and thyratron 50. At the end of the first half-cycle, thyratron 50 becomes non-conductive, hence the discharge continues at a higher frequency determined by the series combination of the thyratron capacitance 64 and capacitor 38a. The circuit 36, 34 has a long time constant so that the discharge current of capacitor 36 via thyratron 12 provides a bias which allows thyratron 12 to pass the negative half-cycles of the higher frequency oscillatory current. The leading edge ...

Apparatus for synchronizing a remote television signal source

... 961,228. Automatic phase control systems; television. FERNSEH G.m.b.H. July 21, 1961 [July 23, 1960] No. 26492/61. Drawings to Specification. Headings H3A and H4F. At television camera stations remote from a television central control station synchronizing pulses are generated of timing advanced relative to synchronizing pulses received at the cameras from the central station by twice the time of transit of pulses between the two stations so that sync. pulses transmitted back to the centre station, along with video signals, are in phase synchronism with the central station master synchronizing pulses. To this end, line and vertical sync. pulses are derived at the cameras from a composite video and sync. signal transmitted from the central station and the line sync. pulses phase compared with local line sync. pulses generated and passed to a phase detector circuit through a delay network of delay equal to twice the constant time of transmission of signals between the stations. The phase ...

Method and apparatus for synthesising a waveform and method and apparatus for generating a lo signal

Loudspeaker driver systems

The system comprises a modulator 120 configured to receive an input signal and to output a pulse width modulated (PWM) signal representative of the received input signal. A delay element 130, 140 applies delays to the PWM output signal to generate a first delayed signal 154 coupled to a second voice coil 114 and a second delayed signal 156 coupled to a third voice coil 116. An undelayed output signal 152 is coupled to a first voice coil 112. The system can be regarded as a FIR filter that may be used to suppress a carrier frequency of the PWM signal. The FIR filter may receive a configuration signal (fig 7) that causes the filter to adapt to a change in the frequency of the PWM signal.

Control mechanism based on timing information

A system operated on a logic circuit (77) clocked by a clock (7) comprising timing violation detection means (1), timing violation correction means (2), time violation frequency obtaining means (3), thresholding means (4) adapted to check if an average frequency of occurrence of timing violations is outside a range, and controlling means (5) adapted to control at least one of a clock frequency, a processing, a heat generation, a bias voltage, a current, and a temperature (6) in a way to bring the average frequency of occurrence of timing violations into the range if the average frequency of occurrence of timing violations is outside the range.

Testing time delay characteristics of electronic devices

Improvements in pulse generating means utilizing delay timed master to control delay timed slaves

... 1,079,000. Semi-conductor pulse circuits. GENERAL ELECTRIC CO. Dec. 9, 1965 [Dec. 14, 1964], No. 52246/65. Heading H3T. [Also in Division H2] A network for generating a series of pulses comprises a master pulse generator which includes a variable time delay circuit to cause the master pulse at the end of a time interval from a given instant, the time interval being determined by the variable time delay circuit, the network further comprising a slave pulse generator for generating an initial slave pulse upon the occurrence of a master pulse, the slave pulse generator including a fixed time delay circuit which is activated by the occurrence of the initial slave pulse to cause the slave pulse generator to provide a further slave pulse at the end of a time interval determined by the fixed time delay circuit. The occurrence of the master pulse also causes the production, after a fixed time delay, of a pulse in a second slave pulse generator and the occurrence of this latter pulse causes the ...

A clock pulse circuit

A clock network for LSI chips of a data handling network comprises a pulse producing circuit on each LSI chip (12, 14) responsive to the leading edge of a master clock signal to produce local clock signals whose pulse durations are dependent, at least in part, on the manufacturing and environmental conditions of the LSI chip.The pulse producing circuit on each LSI chip consists of a plurality of delay networks (22, 24, 26; 22a, 24a, 26a) and a NOR gate (28; 28a), so arranged that the gate is set to produce the leading edge of the local clock pulse coincident with the leading edge of the master clock pulse, and will produce the trailing edge of the local clock pulse upon a delay dependent, at least in part, upon the manufacturing conditions employed in the fabrication of the chip and the environmental conditions to which the chip is subjected. ...

Circuitry for suppressing spurious electric signals

... 808,037. Pulse circuits. NATIONAL CASH REGISTER CO. Feb. 6, 1957 [Feb. 23, 1956], No. 4042/57. Class 40 (6). Fig. 1 shows a circuit for amplifying shaping and gating the signals sent by the reading-heads associated with the channels on a rotating magnetic drum 100. As the drum 100 revolves the substantially square magnetic saturation pattern 129, Fig. 2, of binary digits 1 and 0 recorded on channel 1 and represented at 138, Fig. 2, induces a waveform 130, Fig. 2, at head 102 in which associated with e + and e - pulses corresponding to the leading and trailing edges of waveform 138 unwanted overshoot is also present. The play-back coil 104 is loaded by resistor 108 so that the oscillatory pulses 131, Fig. 2, are quickly damped out. The signal is amplified in negative feedback amplifier stage 133 and applied directly to cathode follower stage 134 to produce the waveform shown at 140, Fig. 2. This signal is inverted by transformer 110 and clamped by diodes 113, 114, the potentiometer 137 being ...

Improvements with the servo systems in phase.

EXACT SLEEP TIMER WITH A ECONOMICAL AND LITTLE EXACT INTERVAL TIMER

ARRANGEMENT FOR GENERATING SYNKRONISIERSIGNALEN WITH VERY LOW JITTER

Impulse synchronisation mechanism

CIRCUIT ARRANGEMENT FOR GENERATING A PULSE WITH A DELAYED EDGE

... 13,9.78 1 PHD 78027 "Circuit arrangement for generating a pulse with a delayed edge." For delaying the switching edge of a differential (pulse) amplifier the drive current of the current amplifier is delayed by a small capacitance in the common emitter circuit.

PROGRAMMABLE HIGH-SPEED DIGITAL DELAY CIRCUIT

DIGITALLY CONTROLLED PHASE SHIFTER

DIGITALLY CONTROLLED PHASE SHIFTER

A clock is phase shifted by an amount controlled by the value of a control signal by establishing at least several discrete delay times to be imposed on the clock. The control signal value controls selection of the imposed discrete delay time. An analog-to-digital converter of a phase locked loop responds to intelligence representing variable phase bits and the selected phase shifted clock to control the signal value. The selected replica is derived by at least several cascaded substantially equal time delay units. In one embodiment, a multiplexer responds to the clock and the signal value, with is Gray coded, to control connections from one of the delay units to an output terminal. In another embodiment, the number of cascaded delay units interposed between the clock and an output terminal is controlled by the signal value. One use of the phase shifter is in a phase lock loop.

WAVESHAPING TRANSVERSAL FILTER AND METHOD UTILIZING THE SAME FOR DATA TRANSMISSION OVER COAXIAL CABLE

A transversal filter (20) has a plurality of variable delay lines each having multiple voltage controlled delay stages in series, with one of the variable delay lines having a clock input (54), and the other variable delay lines having data signal inputs. A phase comparator (150) is coupled to the output of two non-adjacent stages of the variable delay lines having the clock input. A feed-back circuit (25) is coupled to the comparator and provides voltage signals to the voltage controlled delay stages of all of the variable delay lines, such that adjacent stages in a particular delay line are delayed in time equal fractions of a clock cycle from each other, and so that all delay lines are running on the same clock. A voltage weighing circuit (40) is provided for shaping the voltage outputs of the data signal variable delay lines and the weighing circuit is coupled to the delay line stages by switches (128) which are activated when a data signal is propagated through a delay line stage.

Circuit de suppression de signaux parasites, notamment pour calculatrices électroniques

Dispositif servant à retarder des impulsions.

Schaltungsanordnung mit drei Schaltzuständen auf Grund einer Eingangsinformation mit zwei Schaltzuständen

Impuls-Verformungsschaltung

Monostabiler Multivibrator

Impulssynchronisiervorrichtung

Elektronische Zeitverzögerungseinrichtung

Einrichtung zur Synchronisierung von Impulsgeneratoren

Anpassschaltung

Schwellwertschaltung für den Empfang elektrischer Signale

Generatorschaltung für die Erzeugung eines einstellbar verzögerten Auslösesignals

Mehrstufen-Zeitrelais

Verzögerungsanordnung

Als Sägezahn-Oszillator arbeitender Modulator

Einrichtung zur Regenerierung von Ausgangssignalen einer piezoelektrischen Stimmgabel

Digitale Schaltungsanordnung zur Erzeugung eines in der Phase einem Eingangstaktsignal folgenden Ausgangstaktsignales

Elektronisches Zeitrelais für Wechselstrom

Verzögerungsschaltung und Verwendung derselben als Rückkopplungsnetzwerk in einem Flipflop

Verzögerungsschaltung

Schaltung zum verzerrungsfreien Abschalten einer rechteckförmigen Signalwelle in einem beliebigen Zeitpunkt

Impulsverzögernde Anordnung in einer Datenübertragungsanlage

Diskriminator für binäre, frequenzumgetastete Datensignale

Circuit électrique de minuterie à relais

Statisches Zeitrelais

Relaislose Verzögerungsschaltung mit einem R-C-Glied

Laufzeit-Impulsgenerator

CIRCUIT FOR THE ADAPTATION OF INPUT SIGNALS TO A LOGICAL SIGNAL LEVEL.

Delay circuit, oscillator comprising a [...] delay and phase locked loop.

Time amplifier for amplifying time difference and method therefor

A time amplifier for amplifying time difference and method therefore are provided. The time amplifier comprises two sub-circuits, each sub-circuit comprises: an SR latch, a first phase inverter, a second phase inverter, a third phase inverter and a fourth phase inverter. The SR latch comprises a pair of coupled NAND gates which receive a first input signal and a second input signal and generate a first intermediate signal and a second intermediate signal. The first and second phase inverters respectively receive the first and second intermediate signals and generate a first output signal and a second output signal. The third and fourth phase inverters are coupled between the first output signal and the first intermediate signal and between the second output signal and the second intermediate signal to respectively for a first positive feedback path and a second positive feedback path.

Process and device to produce a train of impulses having an exact relation of phase compared to a periodic tension

Retarding device of impulses

Device of synchronization of generators of impulses

Delay arrangement

Improvements with the electronic devices of temporization

Generator of advanced electric impulses, usable in particular in the apparatuses of telecommunication

Assembly to generate a train of impulses in which the edges of the impulses have a position in time exactly definite

PULSE GENERATOR WITH TIME DELAY

GENERATOR OF DELAYS USING A PROGRAMMABLE RESISTANCE CONTAINING MATERIAL HAS PHASE SHIFT

A CIRCUIT FOR GENERATING A PULSE WIDTH MODULATED SIGNAL

JITTER FREE TRIGGER PULSE GENERATOR

DELAY ELEMENT FOR A AC VOLTAGE LOGIC SYSTEM

DELAY LOCKED LOOP USING AC COUPLING PHASE INTERPOLATOR PERFORMING NOT ONLY FUNCTION OF INTERPOLATING PHASE OF INPUT SIGNAL BUT ALSO FUNCTION OF CONTROLLING PHASE OF OUTPUT SIGNAL AND AN APPARATUS THEREOF

PURPOSE: By being proceed the phase interpolate function of the input signals and duty correction and level shift function the delay locked loop using the AC coupling phase interpolator and this apparatus simplifies the configuration of the delay locked loop. CONSTITUTION: A phase interpolate part(11) is applied the first supply voltage. A phase interpolate part generates an interpolated signal in one or more interpolator node by being proceed the phase interpolate toward the input signal of m. By being connected between each and the first node of the interpolator node and including one or more coupling capacitor coupled AC-the phase interpolate part generates the coupling signal in the first node. According to the output unit(12) is the second supply voltage, the voltage level of the coupling signal is controlled. The phase interpolate part additionally includes the filtering capacitor eliminating the input inverter of m and noise of the coupling signal. COPYRIGHT KIPO 2010 ...

Data processing system, data processing circuit and data processing method

A data processing system, comprising: a PLL configured to receive a reference clock and to generate a common clock; a processing unit configured to output an operation condition data based on one of temperature, voltage, or process information; and at least two data processing circuits, each comprising: a first clock signal generator configured to receive the common clock signal, the first clock signal generator having a first clock latency adjusting circuit configured to adjust clock signal propagation delay based on the operation condition data; and a second clock signal generator configured to receive the common clock signal, the second clock signal generator having a second clock latency adjusting circuit configured to adjust clock signal propagation delay based on the operation condition data.

Oscillator

In a current controlling type oscillator for performing a control of oscillation frequency using a differential amplifying circuit, deterioration of phase noise characteristics and a deadlock in the oscillation frequency control tend to occur because of an inclination and width of a linear region of the output characteristics of the differential amplifying circuit. This invention provides an oscillator having a resistor inserted in each current path of a differential pair of the differential amplifying circuits constituting an oscillation frequency control circuit to reduce the inclination of the linear region of the output currents Ia, Ib of the differential pair. Furthermore, a reference voltage applied to the base of one transistor of the above said differential pair is set at a low value to cause the linear region to shift to the low voltage side so as to prevent a saturation region from happening in the low voltage side. Moreover, when converting a result of the comparison of a phase ...

SIGNAL DELAY DEVICE, SIGNAL DELAY DEVICE CONTROL METHOD

Provided are a signal delay device and a signal delay device control method with which it is possible to easily set a degree of delay which is applied to an input signal. A signal delay device which outputs a delay signal whereby a delay is applied to an input signal comprises: a delay means, further comprising a plurality of display units which are serially connected, wherein each delay unit applies a delay to an inputted signal and outputs same; a selection means for outputting the delay signal, further comprising a plurality of selection units which are serially connected and which receive as input the output of one of the plurality of delay units, wherein each selection unit other than the headmost selection unit receives as input the output of the preceding selection unit and outputs either the output from the delay unit or the output from the previous selection unit, depending on the inputted selection signal; a register unit which retains delay setting data which sets the degree ...

DELAY CIRCUIT AND TEST APPARATUS

A delay circuit for delaying an input signal with a desired delay and outputting the delayed signal. The delay circuit includes a light emitting element for emitting light according to an input signal and outputting a delay signal, a bias current source for supplying in advance a first light emitting element with a bias current smaller than a light emission threshold current of the first light emitting element, a bias current controller for controlling the bias current according to a desired delay time, a modulation current source for supplying the light emitting element with a modulation current for making the light emitting element emit light in accordance with the input signal, and a modulation current controller for controlling the modulation current in accordance with a delay resolution in the delay circuit. The modulation current controller controls the modulation current further according to a variable delay range in the delay circuit.

TIMING SIGNAL DELAY CIRCUIT

A timing signal delay circuit which issues input pulse signals while delaying them by a setpoint value that can be adjusted by every predetermined unit, and which can be utilized as a timing generating source for an LSI (semiconductor integrated circuit) tester. The circuit comprises a plurality of delay devices (Dij) that have weighted delay quantities and are arranged in the form of a matrix, a selector (S) which selects a delay device for each array of matrix, means for connecting selected delay devices in series, and an operation control circuit (M) which controls said selector depending upon the setpoint value of delay time and the error quantities of each of the delay devices. Since a delay quantity is given for every predetermined unit despite the error of each of the delay devices, a correction matrix is connected in series with the above matrix, or the weighting of each of the delay devices is modified.

Pulse generator

Controlled rise time output driver

A control slew rate output driver has a plurality of component drivers that are switched on in turn to provide an edge on the output. A control circuit provides a series of respective control signals component drivers, which are correspondingly switched on in turn. The control circuit takes a signal, preferably a data signal, and supplies it in parallel to a plurality of delay buffers, which delay the data signal by different amounts to produce the control signals for the component drivers. The delay buffers are voltage controlled and the control voltage for each is provided by a respective tap of a voltage divider. The current passes through the voltage divider can be changed to change the control voltages and, hence, the overall rise or fall time provided by the output driver.

Oscillator

In the current-controlled oscillator performing an oscillation frequency control by using a differential amplifier circuit, resistors are inserted to each current path of a differential pair of the differential amplifier circuit, and thereby an inclination of output currents Ia, Ib of a differential pair is small in the linear line region. Further, by setting a reference voltage applied to a base of a transistor of one side of the differential pair lowly, the linear region is shifted to low voltage side, and thereby a saturation region of the low voltage side is not occurred. Moreover, when a comparison result of a phase of an output signal of the current-controlled oscillation circuit and a reference signal is converted to an oscillation frequency control voltage Vtune, by limiting an upper limit voltage of the Vtune by an output of a regulator in stead of a positive voltage power source Vcc of common circuit, the Vtune does not move to a saturation region upper than the linear region.

Accurate timing generator and method therefor

In one embodiment, a reference generator forms a reference signal that may have temperature and process variations. A comparator that has similar variations is used to detect a signal using the reference.

Semiconductor circuit

There is provided a semiconductor circuit including three or more nodes at least including one input node and one output node, plural paths which are connected between the three or more nodes and whose signal propagation directions between the nodes are regulated, a signal propagation time regulator for regulating a signal propagation time of each of the paths, an input unit for inputting a predetermined input signal to the input node, and a detector for detecting a time required for the input signal to propagate through the paths and arrive at the output node.

Glitch free clock enable circuit

A clock enabling circuit that generates an output clock signal such that when the enable output signal changes to a logical false, the output clock signal returns to its steady-state value in a manner that does not produce any glitches, and preserves the duty cycle of the input clock. The circuit comprises a first D flip-flop that is positive-edge triggered, a second D flip-flop that is negative-edge triggered, and a two-input AND gate. The first flip-flop has the D input connected to a constant positive voltage, the positive-edge triggered clock input connected to the input clock signal, the Q output connected to the AND gate, and the Q-complement output connected to the asynchronous reset of the second flip-flop. The second flip-flop has the D input connected to the enable output signal, the negative-edge triggered clock input connected to the input clock signal, the Q output connected to the asynchronous reset of the first flip-flop, and the Q-complement output connected to the AND gate ...

Clock-generating circuit for clock-controlled logic circuits

A clock-generating circuit for logic circuits with clock-controlled decoupling stages includes an interlock circuit which, in an interlocking mode, sets the outputs of the clock-generating circuit and thus, the clock lines, to an interlocking potential, thereby causing the decoupling stages to be placed into a shunt-current-free operating state.

Spectrally selective dithering and color filter mask for increased image sensor blue sensitivity

An improved method of operating a color scanning system of the type that incorporates a monochrome image sensor having at least one photosensitive area that is sequentially exposed to individual colors of a scene and to a dithering of the scene with respect to the image sensor photosensitive area is described along with an improved color filter mask for the at least one photosensitive area. The blue filter mask is formed over a portion the photosensitive area, for example, an L-shaped portion, that covers approximately 75% of the photosensitive area. The method of operation is to first image and dither a red filtered version of the scene onto the photosensitive area to generatr a red image signal. Next a green filtered version of the scene is imaged and dithered onto the photosensitive area to generate a green image signal, and lastly a blue filtered version of the scene is imaged onto the photosensitive area without dithering to generate a blue image signal. The photosensitive area generates ...

Delay circuit

A delay circuit which is capable of maintaining a constant delay time. The circuit includes a plurality of first delay circuits connected in series and each having an inverter for inverting an input voltage signal, and a variable capacitor connected to an output terminal of the inverter.

Variable delay clock circuit

A high-speed clock delay circuit in which an external differential digital clock signal is connected to a pair of differentially connected, current switching transistors. Emitter follower drivers couple the switching transistors to differential delayed clock output terminals. A pair of diodes cross-coupled between the differential output terminals and the switching transistors provide a relatively large Miller Effect capacitance, the charging and discharging of which provides a delay in the switching of the transistor pair, as measured differentially. Changing the charging and discharging current through the emitter follower driver, changes the bias across the diodes and thus changes their effective capacitance.

System, method and apparatus for an open loop calibrated phase wrapping phase modulator for wideband rf outphasing/polar transmitters

A device article and method for an open loop calibrated phase wrapping phase modulator. A tapped delay line may provide a coarse resolution for one or more phases of a signal. A phase multiplexer may receive one or more coarse phases from the tapped delay line and select a coarse phase to send to the digitally controlled delay line. A digitally controlled delay line may provide a fine resolution to the coarse phase from the phase multiplexer.

Fine-grained Clock Skew Tuning in an Integrated Circuit

An apparatus for controlling clock skew in an integrated circuit (IC) includes timing circuitry operative to generate a clock signal for distribution in the IC and at least one buffer circuit operative to receive the clock signal, or a signal indicative of the clock signal, and to generate a delayed version of the clock signal as an output thereof. The buffer circuit includes at least first and second inverter stages and a resistive-capacitive (RC) loading structure. An output of the first inverter stage is connected to an input of the second inverter stage via the RC loading structure. The buffer circuit has a delay associated therewith that is selectively varied as a function of one or more adjustable characteristics of the RC loading structure. Clock skew in the IC is controlled as a function of the delay of the buffer circuit.

Oscillator circuit

An oscillator circuit includes a clock oscillator which outputs a main clock signal having an oscillating frequency switched between a high frequency and a low frequency in response to a frequency selection signal, and a frequency divider circuit which outputs a sub-clock signal having a divided frequency equivalent to a frequency division ratio of the oscillating frequency of the main clock signal, the frequency division ratio being switched in response to the frequency selection signal. The divided frequency of the sub-clock signal is predetermined for each of the high frequency and the low frequency to which the oscillating frequency is switched in response to the frequency selection signal.

Semiconductor integrated circuit

Each of a plurality of inverters includes: a first transistor having one end connected to a first terminal; and a second transistor having one end connected to a second terminal and the other end connected to the other end of the first transistor. The first transistors included in the inverters located at either odd-number orders or even-number orders counted from an input terminal side of an inverter chain circuit become conductive when a pre-charge signal has a first state to pre-charge the other end of the first transistors, and become non-conductive when the pre-charge signal has a second state.

Circuit and method for delaying signal

A delay circuit includes a delay unit configured to delay a reference input signal and generate a reference output signal and a storage unit configured to store a plurality of input signals in response to the reference input signal and output the stored signals in response to the reference output signal.

Apparatus and system of implementation of digital phase interpolator with improved linearity

An apparatus comprising: a first control switch driven by a first bit value; a first weighted switch driven by a first clock signal; a first intermediate node coupled between the first control switch and the second weighted switch; a first precharge transistor coupled to the first intermediate node, wherein the precharge transistor is driven by an inverse of the clock signal; a second control switch driven by an inverse of the bit; a second weighted switch driven by a second clock signal; a second intermediate node coupled between the second control switch and the second weighted switch; a second precharge transistor coupled to the second intermediate node, wherein the second precharge transistor is driven by an inverse of the second clock signal; and a capacitor coupled to the first control switch, the second control switch, the first precharge transistor and the second precharge transistor.

Adjustable capacitance structure

A capacitance structure comprises a plurality of metal oxide silicon (MOS) capacitors. A first end of each MOS capacitor of the plurality of MOS capacitors is coupled together at an effective node. A second end of each MOS capacitor of the plurality of MOS capacitors is configured to receive a respective different signal. Each first end of each MOS capacitor of the plurality of MOS capacitors thereby functions as an input end of a capacitor with a capacitance value determined based on the respective different signal. An effective capacitance value thereby results at the effective node.

Aging degradation diagnosis circuit and aging degradation diagnosis method for semiconductor integrated circuit

Provided is an aging degradation diagnosis circuit, including: a first delay circuit including a gate array for allowing aging degradation to progress, the first delay circuit being configured to delay an input signal and output a first output signal; a second delay circuit including a gate array having the same number of stages as the first delay circuit, the second delay circuit being configured to delay an input signal and output a second output signal; and an arbitrary delay unit, which is capable of varying a delay period in the second delay circuit by a predetermined amount. A delay comparison unit outputs comparison information obtained by relatively comparing delays between the first output signal and the second output signal. An adjustment unit uses the comparison information, to thereby readjust the delay period in the second delay circuit.

Fractional and integer pll architectures

A digital fractional PLL introduces an accumulated phase offset before the digital VCO to achieve the fractional part of the division ratio. To provide this phase offset, the digital accumulator can integrate a fractional component Δn. By forcing Δn to zero, the PLL becomes an integer-N PLL. A de-skew timing configuration can be used to remove any time mismatch between integer and fractional counters of the PLL. A digital PLL can merge the function of frequency generation (DVCO) and that of fractional frequency counting into the same circuit block by reusing various phases of the frequency output to generate a fractional frequency count. A digital integer PLL can include a comparator, wherein the feedback loop of this PLL forces the phase difference between the reference clock and feedback signals to approach zero. By changing the duty cycle of feedback signal, the frequency tracking behavior of the loop can be varied.

Frequency-agile strobe window generation

The disclosed embodiments relate to components of a memory system that support frequency-agile strobe enable window generation during read accesses. In specific embodiments, this memory system contains a memory controller which includes a timing circuit to synchronize a timing-enable signal with a timing signal returned from a read path, wherein the timing signal includes a delay from the read path. In some embodiments, the timing circuit further comprises two calibration loops. The first calibration loop tracks the timing-enable signal with respect to a cycle-dependent delay in the delay, wherein the cycle-dependent delay depends on a frequency of the strobe signal. The second calibration loop tracks the timing-enable signal with respect to a cycle-independent delay in the delay, wherein the cycle-independent delay does not depend on the frequency of the strobe signal. In some embodiments, the first calibration loop and the second calibration loop are cascaded.

Integrated Circuit With an Adaptable Contact Pad Reconfiguring Architecture

An apparatus and method are disclosed for providing test mode contact pad reconfigurations that expose individual internal functional modules or block groups in an integrated circuit for testing and for monitoring. A plurality of switches between each functional module switches between passing internal signals among the blocks and passing in/out signals external to the block when one or more contact pads are strapped to input a pre-determined value. Another set of switches between the functional modules and input/output contact pads switch between functional inputs to and from the functional modules and monitored signals or input/output test signals according to the selected mode of operation.

Polyphase clock generator

A polyphase clock generator for use in clock data recovery (CDR) includes a phase selector and a four-to-eight phase converter further including a plurality of delay paths, switches, and phase interpolators. The switches switch over the delay paths so as to select a group of delay paths suited to a clock frequency which is determined in advance. A plurality of reference clock signals with a predetermined phase difference (e.g. 90°) therebetween is selectively delayed while passing through the selected group of delay paths. The phase interpolators interpolate the delayed reference clock signals, passing through the selected group of delay paths, into the reference clock signals, thus generating a plurality of clock signals. The phase selector selectively combines the clock signals with a mixing ratio according to clock data recovery, thus generating a plurality of recovery clock signals with a precise phase difference (e.g.) 45°) therebetween.

Pulsed level gauge system with controllable delay path through selected number of delay cells

A level gauge system comprising transmission signal generating circuitry for generating a transmission signal; a propagation device connected to the transmission signal generating circuitry and arranged to propagate the transmission signal towards a surface of the product inside the tank, and to return a reflected signal resulting from reflection of the transmission signal at the surface of the product contained in the tank. The level gauge system further comprises reference signal providing circuitry configured to provide a reference signal. At least one of the transmission signal generating circuitry and the reference signal providing circuitry comprises delay circuitry. The delay circuitry comprises a plurality of delay cells, and controllable switching circuitry arranged and configured to allow formation of a delay path comprising a subset of the plurality of delay cells connected in series, to thereby allow control of a signal propagation delay of the delay circuitry.

Pulsed level gauge system with supply voltage controlled delay

A level gauge system comprising transmission signal generating circuitry for generating a transmission signal; a propagation device connected to the transmission signal generating circuitry and arranged to propagate the transmission signal towards a surface of the product inside the tank, and to return a reflected signal resulting from reflection of the transmission signal at the surface of the product contained in the tank. The level gauge system further comprises reference signal providing circuitry configured to provide a reference signal. At least one of the transmission signal generating circuitry and the reference signal providing circuitry comprises delay circuitry. The delay circuitry comprises at least one delay cell exhibiting a propagation delay for pulses passing through the at least one delay cell that varies in dependence of a supply voltage provided to the at least one delay cell, and voltage control circuitry connected to the at least one delay cell.

PHASE INTERPOLAR, RECEPTION CIRCUIT AND INFORMATION PROCESSING APPRATUS

A third periodic signal is synthesized using a first output signal having a phase corresponding to a first periodic signal and a second output signal having a phase corresponding to the second periodic signal. A value of the third periodic signal is detected at a timing of the phase of the delayed first periodic signal. The value of the third periodic signal detected with the delayed first periodic signal is compared with the value of the third periodic signal detected by the first periodic signal delayed by the different delay amount. The delay amount is obtained for the detected third periodic signal being a maximum or a minimum. In a state of the optimum delay amount, an amplitude of the third periodic signal is adjusted so that the detected value of the third periodic signal falls within a predetermined range. 1. A phase interpolator comprising:a first signal generation circuit that generates a first output signal that has a phase corresponding to a phase of a first periodic signal that has been input;a second signal generation circuit to which a second periodic signal having a phase different from that of the first periodic signal is input, the second signal generation circuit generating a second output signal that has a phase corresponding to a phase of the second periodic signal;a third signal generation circuit that generates a third periodic signal by synthesizing the first output signal and the second output signal;a delay circuit that provides a variable delay amount to the first periodic signal;a detection circuit that detects a value of the third periodic signal at a timing corresponding to the phase of the first periodic signal that is delayed by the delay circuit;an optimum delay amount obtaining circuit that compares the value of the third periodic signal detected by the detection circuit according to the first periodic signal that has the delay amount with the value of the third periodic signal detected by the detection circuit according to the ...

INTEGRATED CIRCUIT DEVICE TIMING CALIBRATION

Techniques for performing timing calibration for an integrated circuit (IC) device are described. During operation, a first integrated circuit device transmits a first calibration pattern having differently delayed rising edge transitions with respect to a timing reference. The first integrated circuit device additionally transmits a second calibration pattern having differently delayed falling edge transitions with respect to the timing reference. Next, the first integrated circuit generates a timing offset for transmitting data from the first integrated circuit device. This timing offset is derived from information received from a second integrated circuit device sampling the first calibration pattern and the second calibration pattern. 1. A method of operation of an integrated circuit device , the method comprising:transmitting, from a first integrated circuit device, a first calibration pattern having differently delayed rising edge transitions with respect to a timing reference;transmitting, from the first integrated circuit device, a second calibration pattern having differently delayed falling edge transitions with respect to the timing reference; andgenerating a timing offset for transmitting data from the first integrated circuit device, wherein the timing offset is derived from information received from a second integrated circuit device sampling the differently-delayed rising edge transitions of the first calibration pattern and the differently-delayed falling edge transitions of the second calibration pattern.2. The method of claim 1 , wherein generating the timing offset comprises:determining a first timing location with respect to the timing reference based at least on the sampled differently-delayed rising edge transitions;determining a second timing location with respect to the timing reference based at least on the sampled differently-delayed falling edge transitions;computing a third timing location by averaging the first timing location and the ...

Critical-path circuit for performance monitoring

An integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin is disclosed. The monitor circuit has two shift registers, one of which includes a delay element that applies a delay value to a received signal. The inputs to the two shift registers form a signal input node capable of receiving an input signal. The monitor circuit also has a logic gate having an output and at least two inputs, each input connected to a corresponding one of the outputs of the two shift registers. The output of the logic gate indicates whether the target timing margin is satisfied or not satisfied.

Signal delay circuit and signal delay method

A signal delay circuit comprising: a first delay stage, for delaying a first input signal to generate a first delay signal; and a second delay stage, for cooperating with part of delay units of the first delay stage to delay the first delay signal to generate a second delay signal. The signal delay circuit selectively enables the delay stages of the first delay stage or the second delay stage, wherein the signal delay circuit mixes the first delay signal and the second delay signal to generate a first mixed signal when the first delay stage and the second delay stage are both enabled.

Semiconductor device

A semiconductor device includes a first signal delay block configured to delay a first edge of an input signal with varying delay amounts, maintain a second edge of the input signal, and output at least one first driving signal, a second signal delay block configured to delay the second edge of the input signal with the varying delay amounts, maintain the first edge of the input signal, and output at least one second driving signal, and an output pad driving block configured to drive a data output pad with a first voltage in response to the first driving signal and drive the data output pad with a second voltage in response to the second driving signal.

High-resolution phase interpolators

A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.

High-resolution phase interpolators

A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.

Delaying Data Signals

In one embodiment, multiple (serializer-deserializer) SERDES channels are aligned by selectively slipping one or more of the incoming serial data streams one bit at a time prior to deserialization. Within each SERDES channel, a slip circuit slips the corresponding serial data stream by one bit (i.e., one unit interval (UI)) by extending the high portion of the duty cycle of a corresponding clock signal. The high portion of the clock signal is extended using a 3-to-1 mux that selects a fixed high signal, such as the high power supply rail, as an intermediate mux output signal whenever transitioning between two different applied clock signals that are offset from one another by one UI. In this way, the slip circuit avoids glitches that might otherwise result from switching directly between the two clock signals.

CLOCK GENERATOR FOR GENERATING OUTPUT CLOCK HAVING NON-HARMONIC RELATIONSHIP WITH INPUT CLOCK AND RELATED CLOCK GENERATING METHOD THEREOF

A clock generator has an oscillator block and an output block. The oscillator block provides a second clock of multiple phases, and includes an oscillator and a delay locked loop (DLL). The oscillator is used to provide a first clock. The DLL is used to generate the second clock according to the first clock. The output block is used to receive the second clock and generate a third clock by selecting signals from the multiple phases, wherein the third clock has non-harmonic relationship the first clock. 1. A clock generator , comprising: an oscillator, arranged to provide a first clock; and', 'a delay locked loop (DLL), arranged to generate said second clock according to said first clock; and, 'an oscillator block, arranged to provide a second clock of multiple phases, comprisingan output block, arranged to receive said second clock and generate a third clock by selecting signals from said multiple phases, wherein said third clock has non-harmonic relationship with said first clock.2. The clock generator of claim 1 , wherein said output block comprises:a multiplexer, arranged to generate a multiplexer output by multiplexing said multiple phases according to a control signal; anda controller, arranged to receive said multiplexer output and generate said control signal according to said multiplexer output.3. The clock generator of claim 2 , wherein said multiplexer output is cyclically set by said signals of said multiple phases.4. The clock generator of claim 2 , wherein said controller is arranged to update said control signal when said multiplexer output has a transition from a first logic level to a second logic level.5. The clock generator of claim 2 , wherein said output block further comprises:a toggle circuit, arranged to receive said multiplexer output and generate said third clock according to said multiplexer output, wherein said third clock is toggled when said toggle circuit is triggered by said multiplexer output.6. The clock generator of claim 5 , ...

PARTIAL RESPONSE RECEIVER AND RELATED METHOD

A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit. A second storage circuit stores a sampled bit selected from the sampled signals in response to a second clock signal. A time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal. 1. (canceled)2. An integrated circuit comprising:a two phase partial response equalizer circuit;the two phase partial response equalizer circuit having a first sampler circuit to sample an input signal to generate a first sampled signal in response to a first sampling clock having a first phase, and a second sampler circuit to sample the input signal to generate a second sampled signal in response to a second sampling clock having a second phase;the two phase partial response equalizer circuit having a first feedback path to control partial response selection by the first sampler circuit in dependence on the second sampled signal and a second feedback path to control partial response selection by the second sampler circuit in dependence on the first sampled signal;a latch in the first feedback path, the second feedback path not having a latch; andcircuitry to generate a latch clock for the latch in the first feedback path to be phase offset from each of the first sampling clock and the second sampling clock.3. The integrated circuit of claim 2 , wherein:the ...

SIGNAL PROCESSING APPARATUS

A delay element delays an output signal Dt from an arithmetic circuit and outputs a delayed signal Dd. An XOR element compares the output signal Dt with the delayed signal Dd, and outputs an XORout signal with the signal value “0” when the signals match each other, and outputs an XORout signal with the signal value “1” when the signals do not match each other. In a flip-flop when the signal value of the XORout signal at the rise of a clock of a clock signal CK is “0”, the output signal Dt is output from a flip-flop and when the signal value of the XORout signal at the rise of the clock becomes “1” even once, a fixed value of the signal value “0” continues to be output. 1. A signal processing apparatus comprising:a delaying unit that inputs an output signal output continuously from an arithmetic circuit, delays the output signal input, and outputs the output signal delayed as a delayed signal;a comparing unit that inputs the output signal from the arithmetic circuit and inputs the delayed signal from the delaying unit in parallel with the input of the output signal from the arithmetic circuit, compares signal values between the output signal and the delayed signal input at same timing, and outputs one of a match signal and a mismatch signal as a comparison result signal, the match signal notifying that the compared signal values of the output signal and the delayed signal match each other, and the mismatch signal notifying that the compared signal values of the output signal and the delayed signal mismatch each other;a determining unit that inputs a clock signal and inputs the comparison result signal from the comparing unit in parallel with the input of the clock signal, and determines, every time determination timing comes, whether the comparison result signal input in parallel at the determination timing is a match signal or a mismatch signal, the determination timing being at least one of clock rise timing and clock fall timing; andan output unit that inputs the ...

DYNAMIC CLOCK PHASE CONTROL ARCHITECTURE FOR FREQUENCY SYNTHESIS

Embodiments of a device and circuit implementing a digitally controlled oscillator with reduced analog components. In an example, the digitally controlled oscillator can include a phase accumulator controlled by a stall circuit to selective stall the phase accumulator. In some examples, the digitally controlled oscillator can include a phase select circuit to select multiple phases of a phase select circuit based on the output of the phase accumulator. In some examples, these selected phases can then be used by a phase interpolator to generate a synthetic clock signal. 1. A synthetic frequency generator comprising; to receive a master oscillator signal having a frequency and a period;', 'to receive a plurality of phase-control signals;', 'to receive a plurality of selection signals synchronized with the master oscillator; and', 'to provide first and second multiplexer clock signals having transitions synchronized with transitions of the master oscillator signal using a selection of the plurality of phase control signals, the selection based on the plurality of selection signals;', 'wherein the first and second multiplexer clock signals are configured to include a phase offset, and wherein a period of the phase offset is equal to or greater than one half the period of the master oscillator signal; and, 'a multiplexer configured'}an interpolator configured to receive the first and second multiplexer clock signals and to interpolate an output clock signal using the first and second multiplexer clock signals, wherein the output clock signal includes an average frequency greater than zero.2. The synthetic frequency generator of claim 1 , wherein the phase offset is about 45 degrees.3. The synthetic frequency generator of claim 1 , including a digital control circuit configured to provide the plurality of phase control signals.4. The synthetic frequency generator of claim 3 , wherein the multiplexer is configured to provide a clock signal to drive the digital control ...

Delay circuit and electronic device having the same

An electronic device receives a voltage from a power supply. The electronic device includes a load, a first adjusting module, a switching module, a delay module, and a second adjusting module. The first adjusting module produces a working voltage when the electronic device is powered on. The switching module establishes an electrical connection between the first adjusting module and the load when receiving the working voltage, and cuts off the electrical connection when not receiving the working voltage. The delay module delays outputting the working voltage to the load for a first predetermined time period on power on, and maintains a power supply to the load for a second predetermined time period after power off. Both the first predetermined time period and the second predetermined time period are independently adjustable.

Analog delay lines and adaptive biasing

Examples of analog delay lines and analog delay systems, such as DLLs incorporating analog delay lines are described, as are circuits and methods for adaptive biasing. Embodiments of adaptive biasing are described and may generate a bias signal for an analog delay line during start-up. The bias signal may be based in part on the frequency of operation of the analog delay line.

Feed-forward equalizer architectures

Circuits and methods are provided for efficient feed-forward equalization when sample-and-hold circuitry is employed to generate n time-delayed versions of an input data signal to be equalized. To equalize the input data signal, m data signals are input to m feed-forward equalization (FFE) taps of a current-integrating summer circuit, wherein each of the m data signals corresponds to one of the n time-delayed versions of the input data signal. A capacitance is precharged to a precharge level during a reset period of the current-integrating summer circuit. An output current is generated by each of the m FFE taps during an integration period of the current-integrating summer circuit, wherein the output currents from the m FFE taps collectively charge or discharge the capacitance during the integration period. A gating control signal is applied to an FFE tap during the integration period to disable the FFE tap during a portion of the integration period in which the data signal input to the FFE tap is invalid.

Multi-Point Analog to Single-Line Input for a PLC System

A hardware/PLC logic combination which enables measurement of a plurality of analog voltage points (e.g., multiples of 8 points) on a single high speed PLC input without separate synchronization inputs or outputs. This is accomplished through the use of a multiplexer circuit [clock, binary counter, analog multiplexer, voltage to frequency converter], and a high speed counter function at the PLC. Synchronization between the PLC and circuit is through the detection of a fixed voltage on channel “one” of the circuit, which is set well above the typical range (e.g., 0-10V) of the remaining analog inputs. 1. A multiple channel system for a single input of a controller comprising:a first multiplexer having a plurality of inputs and an output;a binary counter circuit coupled to the first multiplexer; and,a controller having a first input coupled to the output of the first multiplexer, the first input selectively receiving data from the plurality of inputs to the first multiplexer.2. The system of wherein the controller is a PLC.3. The system of further comprising a clock coupled to the binary counter circuit.4. The system of wherein each input of the first plurality of inputs of the first multiplexer is coupled to a device providing an analog voltage signal.5. The system of further comprising a voltage to frequency converter coupled to the multiplexer.6. The system of wherein one of the plurality of inputs of the first multiplexer is coupled to a reference voltage to synchronize the system.7. The system of further comprising a second multiplexer having a plurality of inputs and an output claim 1 , the output of the second multiplexer coupled to the first input of the controller claim 1 , the first input selectively receiving data from the plurality of inputs to the second multiplexer.8. The system of wherein the binary counter is coupled to the second multiplexer.9. The system of wherein each of the plurality of inputs of the second multiplexer is coupled to an analog ...

SAMPLING CLOCK GENERATOR CIRCUIT, AND IMAGE READER AND ELECTRONIC DEVICE INCORPORATING THE SAME

A sampling clock generator circuit includes a reference clock generator, a sampling hold circuit, a sampling clock generator to delay an output clock signal from the reference clock generator by a predetermined delay amount to generate and supply a sampling clock signal to the sampling hold circuit, a phase determining element to compare phases of a drive clock signal for an image reading unit and the sampling clock signal to output a result of the phase comparison, the drive clock signal generated according to the output clock signal of the reference clock generator, and a controller to adjust the delay amount of the sampling clock generator on the basis of the result of the phase comparison so that a phase difference between the drive clock signal and the sampling clock signal becomes zero. 1. A sampling clock generator circuit comprising:a reference clock generator;a sampling hold circuit;a sampling clock generator configured to delay an output clock signal from the reference clock generator by a predetermined delay amount to generate and supply a sampling clock signal to the sampling hold circuit;a phase determining element configured to compare phases of a drive clock signal for an image reading unit and the sampling clock signal to output a result of the phase comparison, the drive clock signal generated according to the output clock signal of the reference clock generator; anda controller configured to adjust the delay amount of the sampling clock generator on the basis of the result of the phase comparison so that a phase difference between the drive clock signal and the sampling clock signal becomes zero.2. A sampling clock generator according to claim 1 , further comprising:a first delay circuit having a plurality of first delay taps to delay the output clock signal input by a tap selection; anda second delay circuit having a plurality of second delay taps having a delay amount smaller than that of the first delay taps to delay the output clock signal ...

MULTI-STAGE PHASE MIXER CIRCUIT

A multi-stage phase mixer circuit includes: a first phase mixer configured to receive first and second input clock signals and output a first intermediate clock signal according to control of a first coarse control signal; a second phase mixer configured to receive the first and second input clock signals and output a second intermediate clock signal according to control of a second coarse control signal; and a third phase mixer configured to receive the first and second intermediate clock signals and output an output clock signal according to control of a fine control signal. 1. A multi-stage phase mixer circuit comprising:a first phase mixer configured to receive first and second input clock signals and output a first intermediate clock signal according to control of a first coarse control signal;a second phase mixer configured to receive the first and second input clock signals and output a second intermediate clock signal according to control of a second coarse control signal; anda third phase mixer configured to receive the first and second intermediate clock signals and output an output clock signal according to control of a fine control signal.2. The multi-stage phase mixer circuit of claim 1 , wherein the multi-stage phase mixer circuit performs a phase mixing operation through two stages by performing a first phase mixing operation using the first and second phase mixers and performing a second phase mixing operation using the third phase mixer.3. The multi-stage phase mixer circuit of claim 1 , wherein the first and second coarse control signals have a difference of 1 least significant bit (LSB).4. The multi-stage phase mixer circuit of claim 1 , wherein the first and second intermediate clock signals have a delay time difference corresponding to 1 LSB of the first and second coarse control signals.5. The multi-stage phase mixer circuit of claim 1 , wherein each of the first claim 1 , second claim 1 , and third phase mixers comprises two or more inverting ...

Phase interpolator for clock data recovery circuit with active wave shaping integrators

A phase interpolator for a CDR circuit produces an output clock having level transitions between the level transitions on two input clocks. The input clocks drive cross-coupled differential amplifiers with an output that can be varied in phase by variable current throttling or steering, according to an input control value. The differential amplifiers produce an output signal with a transition spanning a time between the start of a transition on the leading input clock up to the end of the transition on the lagging input clock. The output clock is linear so long as the transitions on the two input clocks overlap. Active integrators each having an amplifier with a series resistance and capacitive feedback path are coupled to each input to the cross-coupled differential amplifiers, which enhances overlap of the input clock rise times and improves the linearity of the interpolated output signal.

SAMPLE-AND-HOLD CIRCUIT FOR GENERATING A VARIABLE SAMPLE DELAY TIME OF A TRANSFORMER AND METHOD THEREOF

A sample-and-hold circuit for generating a variable sample delay time of a transformer includes a discharge detection unit, a sample delay time generation unit, and a comparator. The discharge detection unit generates a first voltage according to a first turning-on signal and a first reference current. Length of the first turning-on signal is varied with a discharge time of a present period of the transformer. The sample delay time generation unit generates a second voltage according to the first turning-on signal and a second reference current. The comparator generates a sample signal to a control circuit of the transformer according to a first voltage corresponding to a previous period of the transformer and a second voltage corresponding to the present period of the transformer. The first reference current is K times the second reference current, and 0 Подробнее

Integrated circuit having a multiplying injection-locked oscillator

Methods and apparatuses featuring a multiplying injection-locked oscillator are described. Some embodiments include a pulse-generator-and-injector and one or more injection-locked oscillators. The outputs of the pulse-generator-and-injector can be injected into corresponding injection points of an injection-locked oscillator. In embodiments that include multiple injection-locked oscillators, the outputs of each injection-locked oscillator can be injected into the corresponding injection points of the next injection-locked oscillator. Some embodiments reduce deterministic jitter by dynamically modifying the loop length of an injection-locked oscillator, and/or by using a duty cycle corrector, and/or by multiplexing/blending the outputs from multiple delay elements of an injection-locked oscillator.

POWER EFFICIENT MULTIPLEXER

A power efficient multiplexer. In accordance with a first embodiment, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for inverting the one of a plurality of input signals. Both the stacked inverter and the transmission gate provide beneficial reductions in static power consumption in comparison to conventional multiplexer designs. 1. A method comprising:outputting at least one bit and a complement of the at least one bit;selectively passing one of a plurality of input signals by using the at least one bit and the complement; andindependently of the at least one bit and the complement and a state of a clock signal, inverting an input signal from said selectively passing.2. The method of claim 1 , wherein said selectively passing comprises:applying the at least one bit to a first transmission gate and a second transmission gate; andapplying the complement to the first transmission gate and the second transmission gate.3. The method of claim 2 , wherein said selectively passing further comprises:if the at least one bit is a first value, outputting a first input signal from the first transmission gate.4. The method of claim 3 , wherein said selectively passing further comprises:if the at least one bit is a second value, outputting a second input signal from the second transmission gate.5. The method of claim 1 , wherein said inverting comprises:using a stacked inverter to invert the input signal from said selectively passing, wherein the stacked inverter includes a first number of transistors arranged as a low-to-high transition leg and a second number of transistors arranged as a high-to-low transition leg.6. The method of claim 5 , wherein the first number equals the second number.7. The method of claim 5 , wherein the first number is greater than the second number.8. The method of claim 5 , wherein the first number is less than the second number.9. A ...

Semiconductor integrated circuit and signal transmission method thereof

A semiconductor integrated circuit includes a plurality of semiconductor chips stacked in a multi-layer structure; a correction circuit in each semiconductor chip configured to reflect a delay time corresponding to the position of the chip in the stack into an input signal to output to each semiconductor chip; and a plurality of through-chip vias formed vertically through each of the semiconductor chips and configured to transmit the input signal to the semiconductor chip.

INTEGRATED CIRCUIT

An integrated circuit includes a clock control unit configured to selectively output an external clock or a delayed clock acquired by delaying the external clock as an input clock in response to a divided clock generated by dividing the external clock, when a test mode is entered; and an internal circuit operating in response to the input clock. 1. An integrated circuit comprising:a clock control unit configured to transfer a first reference voltage or a second reference voltage as a first selection reference voltage in response to a divided clock which is generated by dividing an external clock when a test mode is entered, and generate an input clock by comparing the first selection reference voltage and the external clock; andan internal circuit configured to operate in response to the input clock.2. The integrated circuit according to claim 1 , wherein the clock control unit comprises:a control signal generating section configured to output the divided clock as a control signal when the test mode is entered;a first reference voltage transferring section configured to transfer the first reference voltage or the second reference voltage as the first selection reference voltage in response to the control signal; anda comparing section configured to compare the first selection reference voltage and the external clock and generate the input clock.3. The integrated circuit according to claim 2 , wherein the control signal generating section outputs the ground voltage as the control signal when the test mode is not entered.4. The integrated circuit according to claim 2 , wherein the first reference voltage transferring section transfers the second reference voltage with a higher level than the first reference voltage as the first selection reference voltage when the test mode is entered.5. The integrated circuit according to claim 1 , further comprising:a voltage control unit configured to generate an internal voltage and supply the internal voltage to the internal ...

Method and circuit for adjusting the frequency of a clock signal

In a general aspect, a method for adjusting an oscillator clock frequency can include applying a first control value to a first oscillator, applying a second control value, different from the first control value, to a second oscillator, measuring a frequency of each of the first and second oscillators, determining, by interpolation, a corrected frequency measurement of the second oscillator depending on a frequency deviation measured between the first and second oscillators when subjected to a third control value, on the third control value, and on the control value applied to the second oscillator, determining by interpolation a new first control value depending on the measured frequency of the first oscillator, on the corrected frequency, on the first and second control values, and on a desired frequency, and applying the new first control value to the first oscillator.

PULSE GENERATOR

A pulse generator comprising: a first signal generating arm comprising a first inductor and a plurality of switching elements, each arranged to draw current through the first inductor; and a controller arranged to activate the plurality of switching elements in a predetermined sequence so as to generate a predetermined pulse waveform at a pulse generator output. The switching elements of the signal generating arm and the inductor together form a pulse synthesizer that takes the signal from the controller and uses it to synthesize an output pulse. Compared with conventional transmitter architectures, the functions of the upconversion mixer, the DAC, and the power amplifier are all performed by a single simplified circuit. This is both area efficient and power efficient. 1. A pulse generator comprising:a first signal generating arm comprising a first inductor and a plurality of switching elements, each arranged to draw current through the first inductor; anda controller arranged to activate the plurality of switching elements in a predetermined sequence so as to generate a predetermined pulse waveform at a pulse generator output.2. A pulse generator as claimed in claim 1 , wherein:the plurality of switching elements in the first signal generating arm are arranged to draw different amounts of current.3. A pulse generator as claimed in claim 2 , wherein the plurality of switching elements are transistors and the current drawing ability of each transistor is defined by sizing of the transistors.4. A pulse generator as claimed in claim 1 , further comprising:a second signal generating arm comprising a second inductor and a plurality of switching elements, each arranged to draw current through the second inductor; andwherein the controller is arranged to activate the plurality of switching elements of the first and second signal generating arms in a predetermined sequence so as to generate a predetermined pulse waveform as a differential signal between a first pulse ...

Phase synchronized lo generation

Aspects of the disclosure provide methods and apparatuses for generating an internal reset signal that is synchronous to a clock signal. In some embodiments, an apparatus includes a clock switch circuit and a plurality of serially coupled D flip-flops (DFFs). The clock switch circuit receiving the clock signal can output the clock signal in an on state and block the clock signal in an off state. The plurality of serially coupled DFFs are coupled to the clock switch circuit and driven by the clock signal. If an external reset signal is enabled, the plurality of serially coupled DFFs can enable the internal reset signal. If the external reset signal is disabled, after a predefined number of clock signal cycles, the plurality of serially coupled DFFs can disable the internal reset signal.

DYNAMIC VOLTAGE-LEVEL CLOCK TUNING

Apparatus and methods are provided for improving yield and frequency performance of integrated circuit processors, such as multiple-core processors. In an example, an apparatus can include a plurality of clock buffers, each clock buffer of the plurality of clock buffers configured to receive a first clock signal and distribute a plurality of second clock signals, a one-time programmable locate critical path mechanism configured provide a plurality of indications to enable or disable a delay of each clock buffer of the plurality of clock buffers, and a power management control circuit configured to over-ride one or more of the plurality of indications in a first non-test mode of operation of the apparatus and to not over-ride the one or more indications in a second non-test mode of operation of the apparatus. 1. An apparatus comprising:a plurality of clock buffers, each clock buffer of the plurality of clock buffers configured to receive a first clock signal and distribute a plurality of second clock signals;a one-time programmable locate critical path mechanism configured provide a plurality of indications to enable or disable a first delay of each clock buffer of the plurality of clock buffers; anda power management control circuit configured to over-ride one or more of the plurality of indications in a first non-test mode of operation of the apparatus and to not over-ride the one or more indications in a second non-test mode of operation of the apparatus.2. The apparatus of claim 1 , wherein the one-time programmable locate critical path mechanism is programmed during a test mode of the apparatus.3. The apparatus of claim 1 , wherein the first non-test mode is defined by a first supply voltage of the apparatus and a first frequency of the first clock signal; andwherein the second non-test mode is defined by a second supply voltage of the apparatus and a second frequency of the first clock signal.4. The apparatus of claim 3 , including a plurality of delay ...

CLOCK SYNTHESIS FOR FREQUENCY SCALING IN PROGRAMMABLE LOGIC DESIGNS

Systems and methods described herein are related to clock signal generation for synchronous electronic circuitry. Power management in electronic devices circuitry may be implemented by scaling the frequency multiple functional modules implemented in the synchronous electronic circuitry. The present disclosure discussed clock generators that may provide frequency scaling of clock signals for functional modules within an electronic device. Moreover, certain clock signal generators may reduce mitigate generation of large currents during frequency scaling by employing circuitry that leads to incremental frequency changes. Circuitry that allows substantially glitchless or reduced-glitch transition between clock rate frequencies are also discussed. 1. A method , comprising:generating, by a first configurable clock signal generator of a configurable clock, a first internal clock signal having a first frequency;generating, by a second configurable clock signal generator of the configurable clock, a second internal clock signal having a second frequency;providing, as an output signal of the configurable clock, the first internal clock signal having the first frequency, the second internal clock signal having the second frequency, or both;in response to determining that the first internal clock signal and the second internal clock signal do not match a target frequency, reconfiguring the first configurable clock signal generator to generate the first internal clock signal having a third frequency, reconfiguring the second configurable clock signal generator to generate the second internal clock signal having a fourth frequency, or both; andproviding, as the output signal of the configurable clock, the first internal clock signal having the third frequency, the second internal clock signal having the fourth frequency, or both.2. The method of claim 1 , wherein a difference between the first frequency and the second frequency comprises an incremental difference.3. The method of ...

DEVICE, METHOD AND SYSTEM FOR PROVIDING A DELAYED CLOCK SIGNAL TO A CIRCUIT FOR LATCHING DATA

Techniques and mechanisms for determining a delay to be applied to a clock signal for synchronizing data communication. In an embodiment, a delay is applied to a first clock signal to generate a second clock signal, which is then communicated to a latch circuit via a clock signal distribution path. The delay is determined based on an evaluation of a first time needed for signal communication via a model of the clock signal distribution path. Such determining is further based on an evaluation of a second time for one cycle of a cyclical signal, where said cycle correspond to that of the first clock signal. In another embodiment, multiple different delays are applied each to a different respective clock signal, where each of said delays is based on both the evaluation of the first time and the evaluation of the second time. 1. An integrated circuit (IC) chip comprising:first circuitry to receive a first clock signal, to generate a second clock signal based on the first clock signal, and to communicate the second clock signal via a first signal path which comprises a clock signal distribution path;{'b': 1', '1, 'second circuitry to generate a signal S, wherein a second signal path of the second circuitry comprises a model of the first signal path, wherein the signal S comprises a first indication of a first delay corresponding to the model; and'}{'b': 1', '2, 'third circuitry to receive the signal S and a signal S comprising a second indication of a second delay based on a cycle of a cyclical signal, the third circuitry further to provide to the first circuitry a control signal based on the first indication and the second indication, wherein the first circuitry is to apply a third delay to the first clock signal based on the control signal, wherein the third delay is based on a sum of a first value and a second value, wherein the first value represents the first delay, and wherein the second value represents a time for a scalar multiple of one cycle of the cyclical ...

CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS

A continuously adaptive timing calibration function for a data interface is disclosed. A first calibration method is performed for a mission data path, typically at power-on, to establish an optimal sample point. Reference data paths are established for a second calibration method that does not disturb normal system operation. Data bit edge transitions are examined at fringe timing points on either side of the optimal sample point. Assuming that a timing change for the edge transitions indicates a drift of the optimal sample point, when a drift amount is determined to be greater than a correction threshold value the optimal sampling point for the mission path is adjusted accordingly. At no point does the continuous calibration function determine that any data bit is invalid since the optimal sampling point is always maintained. Also, at no point does continuous calibration require successive alternating data bit values such as 1-0-1 or 0-1-0. 1. A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation , comprising;receiving a first stream of data bits input to the data interface circuit;initially establishing, using a first calibration method, an optimal sampling point for sampling the data bits input to the data interface circuit;receiving a second stream of data bits input to the data interface circuit during normal system operation; establishing at least one reference data path for sampling transition edges of the second stream of data bits input to the data interface during normal system operation;', 'using the at least one reference data path, sampling a plurality of fringe timing points associated with transition edges of the second stream of data bits input to the data interface circuit;', 'comparing a first fringe timing measurement made during a first performance of the second calibration method, with a second fringe timing measurement made during a second ...

Multi-signal realignment for changing sampling clock

An apparatus may include a circuit configured to receive first and second samples of an underlying data from respective first and second sample periods and which correspond to respective first and second sensors, a phase control value may have first and second values during respective first and second sample periods. The phase control value may be a control value for a sample clock signal. The circuit may also determine a difference in the phase control value between the first value and the second value. The circuit may then digitally interpolate the first and second samples to produce a phase shifted first and second samples where the digital interpolation of at least one of the first and second samples mat be at least in part based on the difference in the phase control value to compensate for a phase misalignment between the first sample and the second sample.

ERROR DETECTION AND COMPENSATION FOR A MULTIPLEXING TRANSMITTER

Various aspects provide for error detection and compensation for a multiplexing transmitter. For example, a system can include an error detector circuit and a duty cycle correction circuit. The error detector circuit is configured to measure duty cycle error for a clock associated with a transmitter to generate error detector output based on a clock pattern for output generated by the transmitter in response to a defined bit pattern. The duty cycle correction circuit is configured to adjust the clock associated with the transmitter based on the error detector output. Additionally or alternatively, the error detector circuit is configured to measure quadrature error between an in-phase clock and a quadrature clock in response to the defined bit pattern. Additionally or alternatively, the system can include a quadrature error correction circuit configured to adjust phase shift between the in-phase clock and the quadrature clock based on quadrature error. 1. A system for reducing error associated with a multiplexing transmitter , comprising:an error detector circuit configured to measure a quadrature error for a clock associated with a transmitter to generate first error detector information based on a first clock pattern for a first output generated by the transmitter in response to a defined bit pattern, and generate second error detector information based on a second clock pattern for a second output generated by the transmitter in response to an inverted version of the defined bit pattern, wherein the error detector circuit is further configured to determine a first average value of the first error detector information and a second average value of the second error detector information, determine a differential average value of the first average value and the second average value based on a comparison of the first average value to the second average value, and determine an error detector output based on the differential average value; anda duty cycle correction ...

HIGH-SPEED INTERFACE APPARATUS AND DESKEW METHOD THEREOF

A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode. 1. A high-speed data transmitter comprising:a first buffer connected to a first channel;a second buffer connected to a second channel; anda third buffer connected to a third channel, toggle the first channel from a first voltage level to a second voltage level different from the first voltage level over a predetermined interval;', 'maintain the second channel at the first or second voltage level during the predetermined interval; and', 'start a skew calibration mode based on the first channel and at least one of the second or third channel., 'wherein the high-speed data transmitter is configured to2. The high-speed data transmitter of claim 1 , wherein the predetermined interval is a period of transmitting a deskew synchronous code.3. The high-speed data transmitter of claim 2 , wherein the deskew synchronous code includes serial data “11111111”.4. The high-speed data transmitter of claim 1 , further configured to transmit normal data in a Mobile Industry Processor Interface (MIPI) standard.5. The high-speed data transmitter of claim 4 , wherein the normal data includes display data or image data.6. The high-speed data transmitter of claim 1 , configured to transmit normal data after the predetermined interval.7. The high-speed data transmitter of claim 1 , further comprising a clock generator configured to generate a clock signal.8. The high-speed data transmitter of claim 1 , wherein at least one of the first to third channels includes differential data lines.9. The ...

APPARATUS AND METHODS FOR COMPENSATION OF SIGNAL PATH DELAY VARIATION

Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation. 1. An electronic system with compensation for signal path delay variation , the electronic system comprising: a timing circuit configured to generate an output signal based on timing of an input reference signal;', 'an output pin configured to receive the output signal from the timing circuit and', 'a delay compensation circuit configured to provide one or more compensation signals to the timing circuit; and, 'an integrated circuit (IC) comprisinga signal path configured to route the output signal from the output pin to a destination node,wherein the one or more compensation signals are operable to digitally compensate the timing circuit for a variation in delay of the signal path.2. The electronic system of claim 1 , wherein the delay compensation circuit comprises a delay model configured to generate an estimate of the variation in delay based on one or more operating conditions.3. The electronic system of claim 2 , wherein the delay model is configured to receive a temperature signal indicating a temperature condition.4. The electronic system of claim 2 , wherein the IC further comprises an interface ...

OPTICAL DRIVING DEVICE AND OPTICAL COMMUNICATION SYSTEM

An optical driving device and an optical communication system are provided which can improve signal quality of laser light that uses a PAM method. A laser driver drives a semiconductor laser by using an N-level (N is an integer of 3 or more) PAM signal. A clock control circuit determines a driving timing of the laser driver. In a case where N=4, for example, the clock control circuit determines a driving timing in association with a transition of the PAM signal from a fourth level to a first level to be earlier than a driving timing in association with a transition in an opposite direction by a first time, assuming that levels are the first level, . . . , and the fourth level in an order from a level at which light intensity is minimum. 1. An optical driving device that drives a direct modulation type semiconductor laser , comprising:a laser driver that drives the semiconductor laser by using an N-level (N is an integer of 3 or more) PAM (Pulse Amplitude Modulation) signal; anda clock control circuit that determines a driving timing of the laser driver,wherein the clock control circuit determines the driving timing in association with a transition from an N-th level to a first level to be earlier than the driving timing in association with a transition from the first level to the N-th level by a first time, assuming that N levels are the first level, a second level, . . . , and the N-th level in an order from a level at which light intensity is minimum.2. The optical driving device according to claim 1 ,wherein the N levels are four levels.3. The optical driving device according to claim 2 ,wherein the first time is “(Tf−Tr)/2”, assuming that a time required for the transition from the N-th level to the first level is “Tf” and a time required for the transition from the first level to the N-th level is “Tr”.4. The optical driving device according to claim 2 ,wherein the clock control circuit determines all the driving timings in association with transitions except ...

PROGRAMMABLE DELAY CIRCUIT INCLUDING HYBRID FIN FIELD EFFECT TRANSISTORS (FINFETS)

Embodiments relate to programmable delay circuit. An aspect includes a first stage comprising a first hybrid fin field effect transistor (finFET) comprising a first gate corresponding to a first control FET, and a second gate corresponding to a first default FET, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins. Another aspect includes a second stage connected in series with the first stage, the second stage comprising a second hybrid finFET comprising a first gate corresponding to a second control FET, and a second gate corresponding to a second default FET, and a second plurality of fins, wherein the first gate and the second gate of the second stage each partially control a second shared fin of the second plurality of fins. 1. A programmable delay circuit , comprising:a first stage comprising a first hybrid fin field effect transistor (finFET), the first hybrid finFET comprising a first gate corresponding to a first control FET, and a second gate corresponding to a first default FET, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins; anda second stage connected in series with the first stage, the second stage comprising a second hybrid finFET, the second hybrid finFET comprising a first gate corresponding to a second control FET, and a second gate corresponding to a second default FET, and a second plurality of fins, wherein the first gate and the second gate of the second stage each partially control a second shared fin of the second plurality of fins,wherein the first default FET and the second default FET each receive a gate voltage from a power supply rail of the programmable delay circuit.2. (canceled)3. The programmable delay circuit of claim 1 , wherein the first default FET and the first control FET are in parallel in the ...

PROGRAMMABLE DELAY CIRCUIT INCLUDING HYBRID FIN FIELD EFFECT TRANSISTORS (FINFETS)

Embodiments relate to programmable delay circuit. An aspect includes a first stage comprising a first hybrid fin field effect transistor (finFET) comprising a first gate corresponding to a first control FET, and a second gate corresponding to a first default FET, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins. Another aspect includes a second stage connected in series with the first stage, the second stage comprising a second hybrid finFET comprising a first gate corresponding to a second control FET, and a second gate corresponding to a second default FET, and a second plurality of fins, wherein the first gate and the second gate of the second stage each partially control a second shared fin of the second plurality of fins. 1. A method for providing a programmable delay circuit , comprising:forming a first stage comprising a first hybrid fin field effect transistor (finFET), the first hybrid finFET comprising a first gate corresponding to a first control FET, and a second gate corresponding to a first default FET, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins; andforming a second stage connected in series with the first stage, the second stage comprising a second hybrid finFET, the second hybrid finFET comprising a first gate corresponding to a second control FET, and a second gate corresponding to a second default FET, and a second plurality of fins, wherein the first gate and the second gate of the second stage each partially control a second shared fin of the second plurality of finsthe first default FET and the second default FET each receive a gate voltage from a power supply rail of the programmable delay circuit.2. (canceled)3. The method of claim 1 , wherein the first default FET and the first control FET are in parallel ...

EXPANSION CONTROL CIRCUIT

An expansion control circuit includes a delay circuit coupled to a first expansion module and a switching circuit coupled to a second expansion module. The switching circuit includes a buffer and a switching module. The buffer is coupled to the first expansion module. The first expansion module outputs a first control signal upon being switched on and outputs a second control signal after a working time. The delay circuit outputs a disconnecting signal upon being switched on. The buffer is switched off upon receiving the disconnect signal. The delay circuit further outputs a connecting signal after a delay time after outputting the disconnecting signal. The buffer is switched on upon receiving the connect signal. The buffer further outputs the second control signal to the switching module upon being switched on. The switching module controls the second expansion module to be switched on v receiving the second control signal. 1. An expansion control circuit comprising:a delay circuit coupable to a first expansion module; and a buffer coupable to the first expansion module, and', 'a switching module configured to couple to a second expansion module;, 'a switching circuit having output a first control signal upon being switched on, and', 'output a second control signal after a preset working time;, 'wherein the first expansion module is configured to enable the buffer to be switched off subsequent to being switched on, and', 'enable the buffer to be switched on subsequent to being switched off;, 'wherein the delay circuit is configured towherein the buffer is configured to output the second control signal to the switching module upon being switched on; andwherein the switching module is configured to control the second expansion module to be switched on upon receiving the second control signal.2. The expansion control circuit of claim 1 , wherein the switching module comprises a first field effect transistor (FET) and a second FET claim 1 , the first FET is switched ...

SEMICONDUCTOR DEVICE AND CONTROL METHOD OF SEMICONDUCTOR DEVICE

While transmission of data to be transmitted and gap data to be transmitted by the same transmission path as that data is controlled so that a frequency of a data signal may become equal to or more than a certain frequency, a data output driver selects and outputs the data or the gap data as the data signal, a valid signal generation circuit outputs a valid signal that indicates whether or not the data is effective, and a reception circuit that is formed in a different die receives the data signal and the valid signal transmitted via the transmission path that includes a through silicon via and acquires the data from the data signal based on the valid signal. 1. A semiconductor device comprising:a holding circuit that holds first data to be transmitted;a data generation circuit that generates second data to be transmitted by the same transmission path as the first data;a control circuit that controls transmission of the first data and the second data so that a frequency of a data signal becomes equal to or more than a certain frequency;an output circuit that selects and outputs the first data held by the holding circuit or the second data generated by the data generation circuit as the data signal in correspondence with control by the control circuit;a valid signal generation circuit that outputs a valid signal that indicates that the data is effective when the output circuit is outputting the first data; anda reception circuit that is formed in a second die different from a first die that includes the holding circuit, the data generation circuit, the control circuit, the output circuit, and the valid signal generation circuit, receives the data signal and the valid signal transmitted from the first die via the transmission path that includes a through silicon via, and acquires the first data from the data signal based on the valid signal.2. The semiconductor device according to claim 1 , comprisingan inversion control circuit that outputs an inversion control ...

CMOS Pulse Shrinking, Stretching or Shrink-and-Stretch Mixing Method and Device Thereof

A CMOS pulse shrinking or stretching device includes a basic element sequence, including odd combination positions and even combination positions, and homogeneous logic elements connected to form the basic element sequence. The device further includes an inhomogeneous logic element serially connected between two of the basic elements at the odd or even combination position for shrinking or stretching a pulse signal. A CMOS pulse shrink-and-stretch mixing device further includes an inhomogeneous logic element set, including an odd-positioned inhomogeneous logic element and an even-positioned inhomogeneous logic element to combine stretching and shrinking functions of the pulse signal by adding a stretched pulse and a shrunk pulse signal together. 1. A CMOS pulse shrinking or stretching method comprising:providing a plurality of odd combination positions and a plurality of even combination positions on a basic element sequence which is formed from a series of basic elements;providing a plurality of homogeneous logic elements and at least one odd-positioned inhomogeneous logic element or at least one even-positioned inhomogeneous logic element for forming a pulse shrinking or stretching device;serially connecting the odd-positioned inhomogeneous logic element at the odd combination position or serially connecting the even-positioned inhomogeneous logic element at the even combination position to form the pulse shrinking and stretching device; andutilizing the odd-positioned inhomogeneous logic element to stretch a pulse signal or utilizing the even-positioned inhomogeneous logic element to shrink the pulse signal.2. The CMOS pulse shrinking or stretching method as defined in claim 1 , wherein the odd-positioned inhomogeneous logic element and the even-positioned inhomogeneous logic element are arranged together to provide a neutralizer or a neutralizing function of pulse shrinking and stretching.3. The CMOS pulse shrinking or stretching method as defined in claim 1 , ...

DELAY CIRCUIT, ELECTRONIC CIRCUIT USING DELAY CIRCUIT AND ULTRASONIC IMAGING DEVICE

A delay circuit and an ultrasonic imaging apparatus with the higher-accuracy delay time, the longer maximum delay time, and the lower power consumption are provided. An input line to which an analog input signal is input, a plurality of analog signal memory devices, an output line, a plurality of sampling switches that control connection/disconnection between the input line and the plurality of analog signal memory devices, a plurality of output switches that control connection/disconnection between the plurality of analog signal memory devices and the output line, and a clock generation part that generates sampling switch control signals for controlling the sampling switches and output switch control signals for controlling the output switches are provided, and phase of the sampling switch control signals may be shifted with respect to phase of the output switch control signals. 1. A delay circuit comprising:an input line to which an analog input signal is input;a plurality of analog signal memory devices;an output line from which an analog output signal is output;a plurality of sampling switches that control connection/disconnection between the input line and the plurality of analog signal memory devices;a plurality of output switches that control connection/disconnection between the plurality of analog signal memory devices and the output line; anda clock generation part that generates sampling switch control signals for respectively controlling the plurality of sampling switches and output switch control signals for respectively controlling the plurality of output switches from a reference clock,the delay circuit delaying signals by controlling the plurality of sampling switches to accumulate the analog input signal in the plurality of analog signal memory devices and controlling the plurality of output switches to output the signals accumulated in the plurality of analog signal memory devices to the output line,wherein phase of the plurality of sampling switch ...

SEMICONDUCTOR APPARATUS AND SYSTEM INCLUDING PLURALITY OF CHANNELS

A semiconductor apparatus includes a direct access section, an interface section, and a through-via region. The direct access section receives first and second groups of input signals through a direct access pad, and generates first and second groups of control signals based on the first and second groups of input signals. The interface section comprises a plurality of channel circuits suitable for receiving a part or all of the first and second groups of control signals in response to a plurality of channel selection signals. The through-via region electrically couples the plurality of channel circuits and a plurality of stack dies to form a plurality of channels, respectively. 1. A semiconductor apparatus comprising:a direct access section suitable for receiving first and second groups of input signals through a direct access pad, and generating first and second groups of control signals based on the first and second groups of input signals;an interface section comprising a plurality of channel circuits suitable for receiving a part or all of the first and second groups of control signals in response to a plurality of channel selection signals; anda through-via region suitable for electrically coupling the plurality of channel circuits and a plurality of stack dies to form a plurality of channels, respectively, and transferring signals from the plurality of channel circuits to the plurality of stack dies respectively corresponding to the plurality of channel circuits.2. The semiconductor apparatus of claim 1 , wherein the direct access section comprises:a receiver suitable for generating the first and second groups of control signals by decoding the first and second groups of input signals; anda channel selection unit suitable for generating the plurality of channel selection signals based on a part of the first and second groups of control signals.3. The semiconductor apparatus of claim 2 , wherein the interface section further comprises:a main buffer unit ...

INTERPOLATOR

An interpolator includes a first delay circuit, a second delay circuit, and a tunable delay circuit. The first delay circuit delays a first input signal for a fixed delay time, so as generate a first output signal. The second delay circuit delays a second input signal for the fixed delay time, so as to generate a second output signal. The tunable delay circuit delays the first input signal for a tunable delay time, so as to generate an output interpolation signal. The tunable delay time is determined according to the first output signal, the second output signal, and the output interpolation signal. 1. An interpolator , comprising:a first delay circuit, delaying a first input signal for a fixed delay time, so as to generate a first output signal;a second delay circuit, delaying a second input signal for the fixed delay time, so as to generate a second output signal; anda tunable delay circuit, delaying the first input signal for a tunable delay time, so as to generate an output interpolation signal, wherein the tunable delay time is determined according to the first output signal, the second output signal, and the output interpolation signal,wherein the first output signal, the second output signal, and the output interpolation signal have the same frequency, and a phase of the first output signal leads a phase of the second output signal, and a phase of the output interpolation signal is substantially between the phase of the first output signal and the phase of the second output signal.2. The interpolator as claimed in claim 1 , wherein the phase of the output interpolation signal is substantially in the middle of the phase of the first output signal and the phase of the second output signal.3. The interpolator as claimed in claim 1 , wherein each of the first delay circuit and the second delay circuit is formed by cascading two fixed inverters.4. The interpolator as claimed in claim 1 , wherein the tunable delay circuit comprises a tunable unit which is formed by ...

A SYSTEM FOR STABILIZING DELAY

The present invention relates to pulse power technology. The system includes an input channel, a pulse edge detector () connected in series with two inputs, a filter (), a variable delay unit (), and a feedback channel from the generator to one of the inputs of the pulse edge detector (). The system comprises a reference delay unit (), and the input channel is connected both to the variable delay unit () and to a reference delay unit () for simultaneous supply of input to said units. Signals to both inputs of the pulse edge detector () are synchronous on average, i.e. tstab.avg=1/τ∫ tstab dt=tref with τ>>τest.oper where: tstab.avg—generator output delay relative to the input signal, averaged over the operation time of the system τ at a given tref; tref—reference unit () output delay relative to the input signal; τest.oper—stabilization system time response to changes in external parameters, with the stabilization delay tstab determined from the condition tstab=tvar+tunstab where: tvar—delay of the variable delay unit (); tunstab—unstable delay of the generator. The stabilization of the delay is independent of the pulse repetition frequency. 1at least one input channel connected in series;a pulse edge detector with two inputs;a filter;a variable delay unit, and a feedback channel of the pulse voltage generator connected to one of the inputs of the pulse edge detector, with a special feature;a reference delay unit wherein the at least one input channel is connected both to the variable delay unit and to the reference delay unit for simultaneous input signal to the variable delay unit and the reference delay unit, whereby the signals to both inputs of the pulse edge detector are synchronous on average, i.e. tstab.avg=1/τ∫ tstab dt=tref with τ>>τest.oper where: tstab.avg is a generator output delay relative to the input signal, averaged over the operation time of the delay stabilization system ti at a given tref; wherein tref is a reference unit output delay relative to ...

Semiconductor devices

A semiconductor device includes a delay time adjustment circuit and an address input circuit. The delay time adjustment circuit adjusts a point in time when charges are supplied to internal nodes according to a voltage level of a back-bias voltage in response to a test mode signal. The delay time adjustment circuit also delays an active signal by a first delay time varying according to amounts of charge of the internal nodes to generate a bank selection signal. The address input circuit is driven by the back-bias voltage. The address input circuit receives an address in response to the bank selection signal to generate an internal address. The address input circuit delays the address by a second delay time varying according to a voltage level of the back-bias voltage.

DC-TO-DC DRIVERS WITH HIGH RESOLUTION DIMMING

One aspect of the invention provides a DC-to-DC driver including: a converter including an output configured to drive a load with an output current; and a feedback controller coupled to the converter. The feedback controller includes: a pulse-width modulator configured to output a first pulse-width modulated signal to the converter; a first switching mechanism coupled to the pulse-width modulator; a compensator having an output coupled to the first switching mechanism, the compensator configured to generate a first duty cycle control signal based on a comparison of the output current and a first reference voltage; and a sampler having an input coupled to the output of the compensator and an output coupled to the switching mechanism, the sampler configured to generate a second duty cycle control signal based on the first duty cycle control signal. 1. A DC-to-DC driver comprising:a converter comprising an output configured to drive a load with an output current; and a pulse-width modulator configured to output a first pulse-width modulated signal to the converter;', 'a first switching mechanism coupled to the pulse-width modulator;', 'a compensator having an output coupled to the first switching mechanism, the compensator configured to generate a first duty cycle control signal based on a comparison of the output current and a first reference voltage; and', 'a sampler having an input coupled to the output of the compensator and an output coupled to the switching mechanism, the sampler configured to generate a second duty cycle control signal based on the first duty cycle control signal;, 'a feedback controller coupled to the converter and comprisingwherein the switching mechanism selectively couples one of the compensator and the sampler with the pulse-width modulator based at least in part on a dimming signal.2. The driver of claim 1 , wherein the converter further comprises a switch network comprising a first operating state and a second operating state and ...

CLOCK SIGNAL CONTROLLER

The present invention provides a clock signal controller structure. The invention allows for the large-skew clock signals to be converted into small-skew clock signals. The technical solution of the present invention may be adopted to synchronize two large-skew clock signals. 1. A clock signal controller , comprising:a first clock combiner comprising a plurality of transistors; anda second clock combiner comprising a plurality of transistors, whereina first clock signal input into the first clock combiner is faster than a second clock signal input into the second clock combiner,a trailing edge of a first single clock signal outputted by the first clock combiner corresponds to a rising edge of the first clock signal, and its rising edge corresponds to the trailing edge of the second clock signal, anda trailing edge of a second single clock signal outputted by the first clock combiner corresponds to the rising edge of the second clock signal, and its rising edge corresponds to the trailing edge of the first clock signal.2. The clock signal controller of claim 1 , wherein the plurality of transistors of the first clock combiner comprises a first transistor claim 1 , a second transistor claim 1 , a third transistor and a fourth transistor.3. The clock signal controller of claim 2 , wherein the first transistor is a P-type transistor claim 2 , a source of the first transistor is connected to a working level claim 2 , a drain of the first transistor is connected to a first connecting point claim 2 , and a gate of the first transistor is connected to a first clock signal input end.4. The clock signal controller of claim 3 , wherein the second transistor is an N-type transistor claim 3 , a source of the second transistor is connected to the first connecting point claim 3 , a drain of the second transistor is connected to a reference level claim 3 , and a gate of the second transistor is connected to the first clock signal input end.5. The clock signal controller of claim 4 ...

Serializer, data transmitting circuit, semiconductor apparatus and system including the same

A serializer may include a pre-buffer stage and a main buffer stage. The pre-buffer stage may be configured to generate a plurality of delayed signals by buffering a plurality of signals in synchronization with a plurality of pre-clock signals, respectively. The main buffer stage may be configured to generate an output signal by buffering the plurality of delayed signals in synchronization with a plurality of main clock signals, respectively. The plurality of pre-clock signals may have phase differences from the plurality of main clock signals, respectively.

SEMICONDUCTOR APPARATUS INCLUDING CLOCK PATHS AND SEMICONDUCTOR SYSTEM INCLUDING THE SEMICONDUCTOR APPARATUS

A semiconductor apparatus includes a first clock path which generates a first output clock signal by delaying a first phase clock signal, and a second clock path which generates a second output clock signal by delaying a second phase clock signal based on a delay compensation signal. The oscillating path generation circuit forms oscillating paths with the first clock path and the second clock path. The delay information generation circuit generates a delay compensation signal based on oscillating signals generated by forming the oscillating paths. 1. A semiconductor apparatus comprising:a first clock path configured to generate a first output clock signal by delaying a first phase clock signal in a normal operation mode and to generate the first output clock signal by delaying a first oscillating signal in a monitoring mode;a second clock path configured to generate a second output clock signal by delaying a second phase clock signal based on a delay compensation signal in the normal operation mode and to generate the second output clock signal by delaying a second oscillating signal in the monitoring mode;an oscillating path generation circuit configured to receive the first output clock signal to generate the first oscillating signal and to feed back the first oscillating signal to the first clock path, and configured to receive the second output clock signal to generate a second oscillating signal and to feed back the second oscillating signal to the second clock path; anda delay information generation circuit configured to generate the delay compensation signal based on the oscillating signal.2. The semiconductor apparatus according to claim 1 , wherein the second phase clock signal has a phase difference corresponding to a unit phase from the first phase clock signal.3. The semiconductor apparatus according to claim 1 , wherein the first clock path comprises:a first oscillating controller configured to receive the first phase clock signal and the first ...

Output circuit

A drive assist circuit includes a pulse generation circuit which outputs a pulse to control an assist operation when an assist signal makes a first transition corresponding to a transition of a gate signal from a high level to a low level. The pulse generation circuit includes a delay circuit provided in one of two inputs of a logic gate. The delay circuit is configured such that a delay is greater when an input makes a transition corresponding to the first transition of the assist signal, as compared to a case where the input makes a transition corresponding to an inverse of the first transition.

CLOCK RECOVERY DEVICE AND SOURCE DRIVER FOR RECOVERING EMBEDDED CLOCK FROM INTERFACE SIGNAL

In generating a mask signal to be used when a clock signal embedded in an interface signal is recovered, the mask signal may be generated by compensating for a processing delay time occurring in a mask signal generation circuit, thereby reducing the inaccuracy of the mask signal due to the processing delay time. 1. A clock recovery device comprising:a mask signal generation unit configured to generate a mask signal in accordance with a first mask reference signal;a mask duplication signal generation unit configured to generate a mask duplication signal in accordance with a second mask reference signal;a clock extraction unit configured to extract an extraction clock from an interface signal with a clock signal embedded therein in a time interval indicated by the mask signal;a first time-delay control unit configured to generate a compensation clock by time-delaying the extraction clock so that a phase difference between the extraction clock and the mask duplication signal becomes smaller; anda second time-delay control unit configured to generate the first mask reference signal, and the second mask reference signal by time-delaying the compensation clock, and to generate the first mask reference signal and the second mask reference signal so that a phase of the first mask reference signal is ahead of a phase of the second mask reference signal.2. The clock recovery device of claim 1 , whereinthe mask signal generation unit generates a rising edge of the mask signal in accordance with the first mask reference signal through a first internal circuit,the mask duplication signal generation unit generates a rising edge of the mask duplication signal in accordance with the second mask reference signal through a second internal circuit, anda processing delay time of the first internal circuit and a processing delay time of the second internal circuit are substantially same.3. The clock recovery device of claim 1 , wherein one period of the interface signal is divided into ...

Device for detecting margin of circuit operating at certain speed

Disclosed is a device for detecting the margin of a circuit operating at an operating speed. The device includes: a signal generating circuit generating an input signal including predetermined data; a first adjustable delay circuit delaying the input signal by a first delay amount and thereby generating a delayed input signal; a circuit under test performing a predetermined operation based on a predetermined operation timing and thereby generating a to-be-tested signal according to the delayed input signal; a second adjustable delay circuit delaying the to-be-tested signal by a second delay amount and thereby generating a delayed to-be-tested signal; a comparison circuit comparing the data included in the delayed to-be-tested signal with the predetermined data based on the predetermined operation timing and thereby generating a comparison result; and a calibration circuit determining whether the circuit under test passes a speed test according to the comparison result. 1. A device for detecting a margin of a circuit operating at a circuit operating speed , the device comprising:a signal generating circuit configured to generate an input signal including predetermined data at a beginning of a detection process;a first adjustable delay circuit coupled to the signal generating circuit, and configured to delay the input signal by a first delay amount to generate a delayed input signal;a circuit under test (CUT) coupled to the first adjustable delay circuit, and configured to perform a predetermined operation after the beginning of the detection process to generate a to-be-tested signal according to the delayed input signal, wherein the predetermined operation is based on a predetermined operation timing;a second adjustable delay circuit coupled to the CUT, and configured to delay the to-be-tested signal by a second delay amount in the detection process to generate a delayed to-be-tested signal;a comparison circuit coupled to the second adjustable delay circuit, and ...

DELAY CONTROL SYSTEM HAVING TOLERANCE FOR PVT VARIATION

A delay control system has a tolerance for process, voltage, and temperature (PVT) variations. The delay control system includes a detection compensation block configured to receive a constant current source, detect a PVT variation, and supply a compensation current; a current summation block configured to receive the compensation current and supply a summation current; a current-to-voltage converter configured to receive the summation current and supply a bias voltage depending on the amount of the summation current; and a delay chain block configured to adjust a delay time in response to the bias voltage. Related methods are also described.

DRIVING SIGNAL CONTROL CIRCUIT AND DRIVING APPARATUS

A driving signal control circuit includes a discharge circuit, a counter circuit, and a control circuit. The discharge circuit is configured to compare a monitored voltage and a reference voltage, and generate a discharge signal. The monitored voltage is proportional to a core voltage. The counter circuit is configured to perform an up/down count operation according to the discharge signal, and generate a count signal. The control circuit is configured to generate a driving signal which has an enable period proportional to the count signal. 1. A driving signal control circuit , comprising:a discharge circuit configured to compare a monitored voltage and a reference voltage, and generate a discharge signal, the monitored voltage being proportional to a core voltage;a counter circuit configured to perform an up/down count operation according to the discharge signal, and generate a count signal; anda control circuit configured to generate a driving signal which has an enable period that is proportional to the count signal.2. The driving signal control circuit according to claim 1 , wherein the counter circuit comprises:a start signal generator configured to generate a clock signal based on a command signal;a flag signal generator configured to generate a flag signal based on the discharge signal; anda counter configured to count the flag signal based on the clock signal, and generate the count signal.3. The driving signal control circuit according to claim 2 ,wherein the counter comprises a plurality of count circuits which perform the up/down count operation,wherein the count circuits are electrically coupled sequentially, andwherein the respective count circuits generate a plurality of count bits comprising the count signal.4. The driving signal control circuit according to claim 3 , wherein the counter circuit further comprises:a counter controller configured to provide a count output signal based on the clock signal and a carry output signal.5. The driving signal ...

POWER CONVERTER WITH PHASE ERROR CORRECTION

A power converter circuit included in a computer system may charge and discharge a switch node coupled to a regulated power supply node via an inductor. The power converter circuit may generate a reference clock signal using a system clock signal and a voltage level of the switch node. The reference clock signal may be used to initiate a charge cycle, whose duration may be based on generated ramp signals. 1. An apparatus , comprising:a voltage regulator circuit that includes a switch node coupled to a regulated power supply node via an inductor, wherein the voltage regulator circuit is configured to source a charge current to the switch node during a charge cycle; and determine a phase difference between a system clock signal and a voltage level of the switch node;', 'generate a reference clock signal using the phase difference;', 'generate a plurality of ramp signals using the voltage level of the switch node;', 'initiate the charge cycle using the reference clock signal; and', 'halt the charge cycle using the plurality of ramp signals., 'a control circuit configured to2. (canceled)3. The apparatus of claim 1 , wherein to generate the reference clock signal claim 1 , the control circuit is further configured claim 1 , based on the phase difference claim 1 , to selectively charge or discharge a capacitor.4. The apparatus of claim 3 , wherein the control circuit is further configured to generate a control current using a voltage level across the capacitor.5. The apparatus of claim 4 , wherein the control circuit is further configured to delay the system clock signal to generate the reference clock signal.6. The apparatus of claim 1 , wherein the control circuit is further configured to halt the charge cycle using a result of a comparison of a voltage level of the switch node and a reference voltage level.7. A method claim 1 , comprising:receiving, by a power converter circuit, a system clock signal, wherein the power converter circuit includes a switch node coupled ...

Digital Timer Delay Line with Sub-Sample Accuracy

The present document relates to a timer which is counter-based and uses an asynchronous circuitry to improve the accuracy between the available clock cycles. In particular, a timer is presented which may comprise a first timer circuit configured to receive a clock signal and a trigger signal, wherein an edge of the trigger signal arrives after a first edge of the clock signal and before a second edge of the clock signal. The first timer circuit may be configured to determine, in a capture phase, a time offset interval for approximating a time interval between the first edge of the clock signal and the edge of the trigger signal.

Semiconductor module, vehicle and elevator

A semiconductor module of an embodiment includes a first switching device, a first gate drive circuit controlling ON/OFF of the first switching device, a second switching device connected with the first switching device in parallel or in series, a second gate drive circuit controlling ON/OFF of the second switching device, and a control circuit controlling timing of transmitting a gate drive signal from the first gate drive circuit and transmitting a gate drive signal from the second gate drive circuit by synchronizing the first gate drive circuit and the second gate drive circuit.

VOLTAGE GENERATING SYSTEM, VOLTAGE GENERATING CIRCUIT AND ASSOCIATED METHOD

A voltage generating system including: a voltage source, a clock generating circuit, and a voltage generating circuit. The voltage source generates a reference voltage. The clock generating circuit generates a first clock signal and a second clock signal according to the reference voltage. The voltage generating circuit including an output circuit and a switch circuit. The output circuit generates a control signal at a control node according to the first clock signal and the reference voltage, generates an output signal at an output node according to the second clock signal and the reference voltage. An absolute value of an amplitude of the output signal is greater than the reference voltage while an absolute value of an amplitude of the control signal is greater than the reference voltage. The switch circuit selectively outputs the output signal to an output terminal according to the control signal. 1. A voltage generating system , comprising:{'sub': 'ref', 'a voltage source, arranged to generate a reference voltage (V);'}{'sub': H', 'L, 'b': 2', '1, 'a clock generating circuit, arranged to generate a first clock signal (CLK) and a second clock signal (CLK) according to the reference voltage, wherein a first amplitude (VDD) of the first clock signal is greater than the reference voltage and a second amplitude (VDD) of the second clock signal; and'} [{'sub': out', 'ctrl, 'an output node (N) and a control node (N);'}, {'sub': 'out', 'an output circuit, coupled to the clock generating circuit, wherein the output circuit is arranged to generate a control signal (CTRL) at the control node according to the first clock signal and the reference voltage, generate an output signal (V) at the output node according to the second clock signal and the reference voltage, and an absolute value of a third amplitude of the output signal is greater than the reference voltage while an absolute value of a fourth amplitude of the control signal is greater than the reference voltage; and ...

SEMICONDUCTOR APPARATUS RELATED TO RECEIVING CLOCK SIGNALS HAVING VARIABLE FREQUENCIES, AND SYSTEM INCLUDING THE SEMICONDUCTOR APPARATUS

A system may include an external apparatus and a semiconductor apparatus. The semiconductor apparatus may be configured to communicate with the external apparatus by receiving a frequency-varying first clock signal provided from the external apparatus. 1. A system comprising:an external apparatus configured to provide a first clock signal and a second clock signal; anda semiconductor apparatus configured to communicate with the external apparatus by receiving the first clock signal and the second clock signal,wherein the first clock signal has a first frequency and a second frequency higher than the first frequency, and the second clock signal has a third frequency lower than the first frequency.2. The system of claim 1 , wherein the second frequency is double the first frequency and the first frequency is double the third frequency.3. The system of claim 1 , wherein the first clock signal is transferred from the external apparatus to the semiconductor apparatus when a synchronized signal is transferred between the external apparatus and the semiconductor apparatus claim 1 , and the synchronized signal is transferred in synchronization with the first clock signal.4. The system of claim 1 , wherein the external apparatus provides the first clock signal including at least one pulse having the first frequency and a pulse having the second frequency.5. The system of claim 1 , wherein the semiconductor apparatus includes:a frequency divider configured to generate at least one internal clock signal by dividing a frequency of the first clock signal; anda phase detector configured to generate a phase detection signal by comparing phases between the at least one internal clock signal and the second clock signal.6. The system of claim 5 , wherein the phase detection signal is feedback to the external apparatus claim 5 , and the external apparatus changes a phase of the first clock signal based on the phase detection signal.7. The system of claim 5 , wherein the semiconductor ...

SYSTEMS AND METHODS FOR OPTICAL DISTANCE MEASUREMENT

Systems and methods for performing optical distance measurement are provided. In one aspect, a system for measuring a distance to an object comprises a light emitter configured to emit an outbound light pulse, and a light sensor configured to receive a returning light pulse reflected from the object and output an analog pulse signal representing the returning light pulse. The system also comprises a field-programmable gate array (FPGA) coupled to the light sensor. The FPGA is configured to convert the analog pulse signal to a plurality of digital signal values, and generate a plurality of time measurements corresponding to the plurality of digital signal values. The system also comprises a controller configured to calculate the distance to the object based on the plurality of digital signal values and the plurality of time measurements. 1. A system for measuring a distance to an object , the system comprising:a light emitter configured to emit an outbound light pulse;a light sensor configured to receive a returning light pulse reflected from the object and output an analog pulse signal representing the returning light pulse; convert the analog pulse signal to a plurality of digital signal values, and', 'generate a plurality of time measurements corresponding to the plurality of digital signal values by sampling each digital signal value, wherein a time resolution of the sampling is shorter than a clock period of the FPGA; and, 'a field-programmable gate array (FPGA) coupled to the light sensor and configured toa controller configured to calculate the distance to the object based on the plurality of digital signal values and the plurality of time measurements.2. The system of claim 1 , wherein the light emitter claim 1 , light sensor claim 1 , FPGA claim 1 , and controller are carried by an unmanned vehicle claim 1 , an autonomous vehicle claim 1 , or a robot.3. The system of claim 1 , wherein the time resolution is at least 5 times shorter than the clock period of ...

Modified Flying Adder Architecture

According to an embodiment, an improved flying adder circuit, comprises a fine clock, a coarse pulse clock, a rising edge triggered output connected to both the fine clock and the coarse pulse clock, a pulse clock connected to the rising edge triggered output, an adder, a 12-bit register situated to receive a signal from the adder and the pulse clock, and a single bit register situated to receive a signal from the pulse clock. 1. A flying adder circuit , comprising:a fine pulse clock;a coarse pulse clock;a rising edge triggered output circuit, connected to both the fine pulse clock and the coarse pulse clock to provide a pulse train;an adder;a register/accumulator situated to receive a signal from said adder and said pulse train; anda single bit register situated to receive a signal from said rising edge triggered output.2. The flying adder circuit of claim 1 , wherein the fine clock has a 256 picosecond period.3. The flying adder circuit of claim 1 , wherein the fine clock has 16 picosecond steps.4. The flying adder circuit of claim 1 , wherein the coarse pulse clock has a period between approximately 3840 picoseconds and 4096 picoseconds.5. The flying adder circuit of claim 1 , wherein the coarse pulse clock has 256 picosecond steps.6. The flying adder circuit of claim 1 , wherein said fine pulse clock outputs a number of fine pulse clock pulse trains selectable by a first multiplexer and wherein the fine pulse clock pulse train selected by said first multiplexer is controlled by middle significant bits from said register/accumulator.7. The flying adder circuit of claim 1 , wherein said coarse pulse clock outputs a number of coarse pulse clock pulse trains selectable by a second multiplexer and wherein the coarse pulse clock pulse train selected by said second multiplexer is controlled by most significant bits from said register/accumulator.8. The improved flying adder circuit of claim 1 , further comprising a delay circuit coupled to said rising edge triggered ...

Clock generator

A clock generator comprises a voltage controlled oscillator including a ring oscillator which has a plurality of differential inverter circuits connected in a ring shape, and a phase controller to control an output of a differential inverter circuit which belongs to a second group, in a first state or a second state, for a predetermined time period. The differential inverter circuit which belongs to the second group is distinct from a differential inverter circuit which belongs to a first group. The differential inverter circuit which belongs to the second group, in the first state, outputs a first logic signal from a first differential output terminal and outputs a second logic signal from a second differential output terminal. Further, the differential inverter circuit which belongs to the second group, in the second state, outputs the second logic signal from the first differential output terminal and outputs the first logic signal from the second differential output terminal.

System and method for clocking integrated circuit

A system and method of clocking an integrated circuit (IC) includes determining operating characteristics of the IC. The IC has multiple domains and each domain receives a respective domain clock signal. A skew value is determined for each of the domain clock signals, where each skew value is associated with a respective domain of the IC. The domain clock signals are generated from a reference clock signal and each domain clock signal is skewed from the reference clock according to the respective skew value.

DELAY CELL, DELAY LOCKED LOOK CIRCUIT, AND PHASE LOCKED LOOP CIRCUIT

A delay cell includes a first transistor and a second transistor, at least one of which has a fully depleted silicon-on-insulator (FD-SOI) structure. A first control voltage is applied to the body of the first transistor and a second control voltage is applied to the body of the second transistors in order to adjust the delay time of the delay cell. DLL and PLL circuits includes this type of delay cell. 1. A delay cell comprising:a first transistor having a first terminal connected to a power supply voltage terminal, a second terminal connected to an output terminal, and a gate terminal connected to an input terminal; anda second transistor having a first terminal connected to a ground terminal, a second terminal connected to the output terminal, and a gate terminal connected to the input terminal,wherein each of the first and second transistors has a fully depleted silicon-on-insulator (FD-SOI) structure, and at least one of a first control voltage is applied to a body of the first transistor and a second control voltage is applied to a body of the second transistors to adjust a delay time of the delay cell.2. The delay cell of claim 1 , wherein the first transistor is a P-type Metal Oxide Semiconductor (PMOS) transistor and the second transistor is an N-type MOS (NMOS) transistor.3. The delay cell of claim 1 , wherein each of the first transistor and second transistor comprises:a body layer;a buried insulation layer on the body layer;a pair of impurity regions disposed on the buried insulation layer to function as source/drain regions;a semiconductor layer disposed between the pair of impurity regions in contact with the buried insulation layer;a gate insulation layer on a top surface of the semiconductor layer opposite to the buried insulation layer; anda gate electrode on the gate insulation layer.4. The delay cell of claim 3 , wherein the body layer of the first transistor is N-type and the pair of impurity regions of the first transistor are P-type claim 3 , ...

PHASE INTERPOLATOR

Apparatus to implement several high performance phase interpolators are disclosed. Some embodiments are directed to a full-wave integrating phase interpolation core comprising two pairs of in-phase and quadrature-phase current DACs arranged in a cascode architecture to drive an integrating capacitor and produce an interpolation voltage waveform. The current DACs are biased, weighted, and controlled by in-phase and quadrature-phase input clocks to yield an interpolation waveform that presents a phase value between the phases of the input clocks. Some embodiments deploying the interpolator core use feedback circuitry and reference voltages to adjust the common mode and amplitude of the interpolation voltage waveform to obtain both optimal performance and operation within the interpolator linear region or output compliance range. Both the single-core and dual-core implementations, as well as other implementations of the interpolator core, exhibit high power supply rejection, highly linear interpolation, a wide frequency range, and low cost duty cycle correction. 118-. (canceled)19. A method for designing a low power phase interpolator that exhibits high power supply rejection , the method comprising: identifying a positive in-phase current source having a positive in-phase input that is operatively coupled to a positive in-phase control module that receives power from a positive power supply terminal, and produces a positive in-phase output;', 'identifying a positive quadrature phase current source having a positive quadrature phase input that is operatively coupled to a positive quadrature phase control module that receives power from the positive power supply terminal, and produces a positive quadrature phase output;', 'identifying a negative in-phase current source having a negative in-phase input that is operatively coupled to a negative in-phase control module that receives power from a negative power supply terminal, and produces a negative in-phase output;', ' ...

Variable Delay Element

A delay circuit includes first and second transistors and a biasing circuit. The first transistor has a control node coupled to an input node of the delay circuit, a first main current node coupled to a first supply voltage, and a second main current node coupled to an output node of the delay circuit. A second transistor has a control node coupled to the input node, a first main current node coupled to a second supply voltage, and a second main current node coupled to the output node. The biasing circuit is configured to generate first and second differential control voltages , to apply the first differential control voltage to a further control node of the first transistor and to apply the second differential control voltage to a further control node of the second transistor. 1. A delay circuit comprising:an input node;an output node;a first transistor of a first conductivity type, the first transistor having a control node coupled to the input node, a first main current node coupled to a first supply voltage node, and a second main current node coupled to the output node;a second transistor of a second conductivity type, the second transistor having a control node coupled to the input node, a first main current node coupled to a second supply voltage node, and a second main current node coupled to the output node; anda biasing circuit having a first differential control voltage output coupled to a further control node of the first transistor and a second differential control voltage output coupled to a further control node of the second transistor.2. The delay circuit of claim 1 , wherein the biasing circuit is configured to adjust a delay of the delay circuit by modifying voltage levels of the first and second differential control voltages.3. The delay circuit of claim 1 , wherein the biasing circuit comprises a differential amplifier.4. The delay circuit of claim 1 , further comprising a control circuit coupled to a control input of the biasing circuit to ...

PRECISION MODULATION TIMER (PMT) INTEGRATED IN A PROGRAMMALBE LOGIC DEVICE

A timer block includes: a digital control block including a mode selector and a register loading a time delay; a counter coupled to the register of the digital control block, wherein the counter loads a counter value corresponding to the time delay based on an operational mode selected by the mode selector and generates a digital output indicating the counter value that is decremented at each clock; and a pulse generator configured to generate a pulse signal based on the counter value of the counter. The timer block is integrated in a programmable logic device (PLD) including a programmable fabric and a signal wrapper that is configured to provide signals between the timer block and the programmable fabric. The operational mode of the timer block is programmably configured using the programmable fabric and the signal wrapper. 1. A timer block comprising:a digital control block including a mode selector and a register loading a time delay;a counter coupled to the register of the digital control block, wherein the counter loads a counter value corresponding to the time delay based on an operational mode selected by the mode selector and generates a digital output indicating the counter value that is decremented at each clock; anda pulse generator configured to generate a pulse signal based on the counter value of the counter,wherein the timer block is integrated in a programmable logic device (PLD) including a programmable fabric and a signal wrapper that is configured to provide signals between the timer block and the programmable fabric, andwherein the operational mode of the timer block is programmably configured using the programmable fabric and the signal wrapper.2. The timer block of claim 1 , wherein the time delay is a programmable time delay or a preset time delay.3. The timer block of claim 2 , wherein the programmable time delay is received from the programmable fabric claim 2 , and the programmable time delay is fed to the one or more registers via the ...

HIGH-SPEED SERIAL DATA RECEIVING APPARATUS

Provided is a high-speed serial data receiving apparatus including: a clock converter configured to convert a serial clock into a parallel clock; a data converter configured to convert a serial data packet into N parallel data packets and outputting the N parallel data packets; a synchronization signal detector configured to receive the N parallel data packets and the parallel clock, and detecting a data start synchronization of the N parallel data packets output from the data converter by comparing the parallel data packets with a synchronization code of N bits set in advance; and an error compensation unit configured to detect and compensate for a skew between parallel clock and data. 1. A high-speed serial data receiving apparatus comprising:a clock converter configured to convert a serial clock into a parallel clock;a data converter configured to convert a serial data packet into N parallel data packets and output the N parallel data packets;a synchronization signal detector configured to receive the N parallel data packets and the parallel clock, and detect data start synchronization of the N parallel data packets output from the data converter by comparing the parallel data packets with a synchronization code of preset N bits; andan error compensation unit configured to detect a clock skew between parallel clocks and compensate for the clock skew.2. The high-speed serial data receiving apparatus of claim 1 , wherein the data converter converts the serial data packet into N parallel data packets by sampling the serial data packet into N flip-flops based on the serial clock.3. The high-speed serial data receiving apparatus of claim 2 , wherein the data converter outputs the N parallel data packets by synchronizing the N parallel data packets by using the parallel clock.4. The high-speed serial data receiving apparatus of claim 1 , wherein the clock converter comprises:a counter configured to receive a selection signal value that is selected between a single data ...

DEMUX CONTROL CIRCUIT

The present application provides a demux control circuit. The demux control circuit includes a driving chip, a logic circuit, and a demux for providing two or three pulse signals to the logic circuit, the logic circuit including a plurality of NOR Gate and a plurality of buffers which can convert two pulse signals into three control signals or convert the three pulse signals into four control signals through the cooperation of the NOR gates and the buffers to achieve outputting a larger number of control signals by a smaller number of pins, thereby reducing the number of pins outputted from the driving chip and reduce production costs. 1. A demux control circuit , comprising:a driving chip; a logic circuit electrically connected to the driving chip, and a demux electrically connected to the logic circuit;the driving chip for providing a first pulse signal and a second pulse signal to the logic circuit;the logic circuit comprising a first two-input NOR gate, a second two-input NOR gate, a third two-input NOR gate, a first in-phase buffer, a second in-phase buffer, and a third in-phase buffer;a first input terminal and a second input terminal of the first two-input NOR gate respectively accessing the first pulse signal and the second pulse signal, an output terminal electrically connected to an input terminal of the first in-phase buffer; a first input terminal of the second two-input NOR gate accessing the first pulse signal; a second input terminal electrically connected to the output terminal of the first two-input NOR gate, an output terminal electrically connected to an input terminal of the second in-phase buffer; a first input terminal of the third two-input NOR gate accessing the second pulse signal, a second input terminal electrically connected to the output terminal of the first two-input NOR gate, an output terminal electrically connected to an input terminal of the third in-phase buffer; andoutput terminals of the first in-phase buffer, the second in- ...

DELAY CONTROL DEVICE AND TUNABLE DELAY DEVICE

A delay control device for controlling a delay circuit includes an oscillator, a counter, and an output control circuit. The oscillator generates an internal clock signal according to an external clock signal. The counter generates an accumulative signal according to the internal clock signal. The counter is selectively reset by the external clock signal. The output control circuit generates a delay indication signal according to the accumulative signal. The delay time of the delay circuit is adjusted according to the delay indication signal. 1. A delay control device for controlling a delay circuit , comprising:an oscillator, generating an internal clock signal according an external clock signal;a counter, generating an accumulative signal according to the internal clock signal, wherein the counter is selectively reset by the external clock signal; andan output control circuit, generating a delay indication signal according to the accumulative signal, wherein a delay time of the delay circuit is adjusted according to the delay indication signal.2. The delay control device as claimed in claim 1 , wherein the oscillator comprises:a NAND gate, wherein the NAND gate has a first input terminal for receiving the external clock signal, a second input terminal coupled to a first node, and an output terminal coupled to a second node;a first inverter, wherein the first inverter has an input terminal coupled to the second node, and an output terminal coupled to a third node; anda second inverter, wherein the second inverter has an input terminal coupled to the third node, and an output terminal coupled to the first node for outputting the internal clock signal.3. The delay control device as claimed in claim 1 , wherein the accumulative signal comprises a first bit claim 1 , a second bit claim 1 , a third bit claim 1 , and a fourth bit.4. The delay control device as claimed in claim 3 , wherein the counter comprises:a first D flip-flop, wherein the first D flip-flop has a ...

CONFIGURABLE RETRY FOR SYSTEM OPERATIONS

The present disclosure relates to configuring parameters of a system. In some examples, a timer duration circuit can be configured to output a timer duration signal defining a time duration for a retry signal based on an impedance of a first circuit coupled at a first node. A logic circuit can be configured to control an output of the retry signal to at least one integrator circuit to control a current to a second node based on one of the timer duration signal and a retry timer signal, and a combination thereof. An output circuit can be configured to output a stop retry signal based on a voltage established by a second circuit at the second node based on its impedance and the current. The stop retry signal can indicate a number of retries that have occurred and can be based on the capacitances of the first and second circuits. 1. A system comprising:a timer duration circuit coupled to a first node and configured to output a timer duration signal, wherein a first circuit is coupled to the first node, and the timer duration signal defines a time duration for a retry signal based on an impedance of the first circuit;a logic circuit configured to control the retry signal that is output to at least one integrator circuit to control a current to a second node based on one of the timer duration signal, a retry timer signal (RTRS), and a combination thereof, wherein a second circuit is coupled to the second node and to provide a voltage at the second node based on an impedance of the second circuit and the current; andan output circuit configured to output a stop retry signal based on the voltage at the second node, wherein the stop retry signal is to indicate a number of retries that have occurred, the number of retries being set based on the impedances of the first and second circuits.2. The system of claim 1 , wherein the first circuit is to provide a voltage at the first node based on the impedance of the first circuit and a current from a current source.3. The system ...

Method and Apparatus for RC/CR Phase Error Calibration of Measurement Receiver

A circuit includes a RC-CR circuit and a second circuit. The RC-CR circuit outputs a first signal at a first output node over a RC path, and a second signal at a second output node over a CR path. The second circuit is coupled to the RC-CR circuit at the first output node over the RC path. The second circuit includes an array of capacitors coupled in parallel and a plurality of switches, and each of the array of capacitors is connected, in series, to a corresponding switch in the plurality of switches. Each of the array of capacitors and its corresponding switch are coupled between the first output node and a ground. The plurality of switches is switched on or off such that the first signal and the second signal have a phase difference that falls within a predetermined phase range. 1. An apparatus comprising:a resistor-capacitor/capacitor-resistor (RC-CR) circuit having an input node, a resistor capacitor (RC) path, and a capacitor resistor (CR) path, the RC-CR circuit configured to generate at least a first output signal and a second output signal by applying a phase-shift to an input signal received over the at an input node of the RC-CR circuit, to output the first output signal over the RC path of the RC-CR circuit, and to output the second output signal over the CR path of the RC-CR circuit,wherein the RC path of the RC-CR circuit includes an array of capacitors coupled in parallel and a plurality of switches, a first terminal of each capacitor in the array of capacitors being coupled to a common node and a second terminal of each capacitor in the array of capacitors being coupled to a ground of the circuit through a corresponding switch in the plurality of switches.2. The apparatus of claim 1 , wherein each capacitor in the array of capacitors has a capacitance that is based on a predetermined weighting factor.3. The apparatus of claim 1 , wherein the RC-CR circuit further comprises:a first resistor having a first terminal coupled to the ground of the circuit ...

CURRENT-STARVING IN TUNABLE-LENGTH DELAY (TLD) CIRCUITS EMPLOYABLE IN ADAPTIVE CLOCK DISTRIBUTION (ACD) SYSTEMS FOR COMPENSATING SUPPLY VOLTAGE DROOPS IN INTEGRATED CIRCUITS (ICs)

Current-starving in tunable-length delay (TLD) circuits in adaptive clock distribution (ACD) systems for compensating voltage droops in clocked integrated circuits (ICs) is disclosed. Voltage droops slow propagation of signals in clocked circuits. However, clock delay circuits in a TLD circuit increase a clock period by increasing a clock delay in response to a voltage droop. In large power distribution networks (PDN), impedance can delay and reduce the magnitude of voltage droops experienced at the TLD circuit. If the voltage droop at the TLD circuit is smaller than at the clocked circuit, then the clock period isn't stretched enough to compensate the slowed clocked circuit. A current-starved TLD circuit starves the clock delay circuits of current in response to a voltage droop indication, which further increases the clock signal delay, and further stretches the clock period to overcome a larger voltage droop in clocked circuits in other areas of the IC.

CONTROL APPARATUS FOR POWER CONVERTER

In a control apparatus for a power converter, a current obtainer obtains a current flowing through an inductor as an inductor current, and an alternating-current voltage obtainer obtains an alternating-current voltage. A drive signal outputting unit generates, based on the alternating-current voltage obtained by the voltage obtainer, a sinusoidal command. The drive signal outputting unit performs peak-current mode control to output a drive signal that controls switching of the drive switch to thereby cause the inductor current to follow the sinusoidal command. A delay unit delays, for one switching cycle of the drive switch, an off-switching timing of the drive switch in accordance with the alternating-current voltage. The drive signal defines the off-switching timing of the switch. 1. A control apparatus applicable to a power converter that includes an inductor and a drive switch , and that converts one of an alternating-current voltage and a direct-current voltage input thereto into the other of the alternating-current voltage and the direct-current voltage , the control apparatus comprising:a current obtainer configured to obtain a current flowing through the inductor as an inductor current;an alternating-current voltage obtainer configured to obtain the alternating-current voltage; generate, based on the alternating-current voltage obtained by the voltage obtainer, a sinusoidal command; and', 'perform peak-current mode control to output a drive signal that controls switching of the drive switch to thereby cause the inductor current to follow the sinusoidal command; and, 'a drive signal outputting unit configured toa delay unit configured to delay, for one switching cycle of the drive switch, an off-switching timing of the drive switch in accordance with the alternating-current voltage, the drive signal defining the off-switching timing of the switch.2. The control apparatus according to claim 1 , wherein:the power converter is configured to convert the ...

Selectable Delay Buffers and Logic Cells for Dynamic Voltage Scaling in Ultra Low Voltage Designs

Provided is a selectable delay buffer for tuning a delay path in a circuit. The selectable delay buffer comprises a first delay segment configured to pass an input signal to an output terminal within a first range of time delays, a second delay segment configured to pass the input signal to the output terminal within a second range of time delays that is different from the first range, and a segment selection switch configured to selectively couple the delay segments to the output terminal based on received selection information that indicates which delay segment to couple to the output terminal. 1. A selectable delay buffer for tuning a delay path in a circuit , comprising:at least two delay segments each configured to pass an input signal to an output terminal within at least two ranges of time delays that are different between each other; anda segment selection switch configured to selectively couple the delay segments to the output terminal based on received selection information that indicates which delay segment to couple to the output terminal.2. The selectable delay buffer of claim 1 , wherein the segment selection switch comprises a multiplexer.3. The selectable delay buffer of claim 1 , further comprising one or more additional delay segments wherein each additional delay segment is configured to pass the input signal to the output terminal within a range of time delays that is different from the other range of time delays and wherein the segment selection switch is configured to selectively couple the additional delay segments to the output terminal based on the received selection information.4. The selectable delay buffer of claim 3 , wherein the selection information comprises two or more selection signals.5. The selectable delay buffer of claim 1 , further comprising a fixed delay section and wherein the first delay segment claim 1 , the second delay segment claim 1 , and the segment selection switch form an adjustable delay section.6. The selectable ...

CONTROL DEVICE, DELAY DIFFERENCE ADJUSTMENT METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM FOR STORING DELAY DIFFERENCE ADJUSTMENT PROGRAM

A control device causes a first transmission system in a MIMO transmission device to transmit a first transmitting-end clock transmission signal (first transmission signal), causes a second transmission system to transmit a second transmission signal, and causes the first transmission system to transmit a third transmission signal. The control device acquires a first phase value and a second phase value. The first phase value is a phase value of the second transmission signal received in the second reception system operating based on a receiving-end clock signal synchronous with a transmitting-end clock signal by the first transmission signal. The second phase value is a phase value of the third transmission signal received in the second reception system in synchronous operation. The control device calculates a first correction value for correcting a first delay amount set value of a delay adjustment processing unit based on the first and second phase values 1. A control device for adjusting a difference in delay between a first transmission system and a second transmission system in a MIMO (multiple-input and multiple-output) transmission device including the first transmission system and the second transmission system operating based on a transmitting-end clock signal and being capable of MIMO communication with a MIMO reception device including a first reception system and a second reception system operating based on a receiving-end clock signal , the control device comprising:hardware including a processor and a memory; anda control unit for implemented at least by the hardware and thatcauses a first transmission radio processing unit in the first transmission system to transmit a first transmitting-end clock transmission signal,causes a second transmission radio processing unit in the second transmission system to transmit a second transmitting-end clock transmission signal,causes the first transmission radio processing mean to transmit a third transmitting-end ...

Data-dependent delay circuits

A method of designing a logic circuit with data-dependent delays is performed using an electronic design automation system. The logic circuit includes logic paths from logic inputs to at least one logic output. The method includes: obtaining an initial circuit design; specifying respective delays for multiple logic paths in the initial circuit design such that at least some of the outputs switch at different times within a clock cycle for different combinations of logic input levels; and forming a second circuit design having the specified respective delays along the respective logic paths by adding delay elements to the initial circuit design based on the specified respective delays.

CONTROL CIRCUIT OF THIN FILM TRANSISTOR

A control circuit of a thin film transistor, comprising: a substrate; a silicon nitride layer disposed on the substrate; a silicon dioxide layer disposed on the silicon nitride layer; a light shielding layer disposed inside the silicon nitride layer, which comprising a first light shielding region and a second light shielding region; at least one N type metal oxide semiconductor disposed on the silicon dioxide layer at a position corresponding to the first light shielding region; at least one P type metal oxide semiconductor disposed on the silicon dioxide layer at a position corresponding to the second light shielding region; each of the N type metal oxide semiconductor and the P type metal oxide semiconductor has a gate electrode layer, a first control signal received by voltage pulses of the gate electrode layer synchronized with a second control signal received by the light shielding layer in voltage variation. 1. A control circuit of a thin film transistor , comprising:a substrate;a silicon nitride layer disposed on the substrate;a silicon dioxide layer disposed on the silicon nitride layer;a light shielding layer disposed inside the silicon nitride layer, the light shielding layer comprising a first light shielding region and a second light shielding region;at least one N type metal oxide semiconductor disposed on the silicon dioxide layer at a position corresponding to the first light shielding region; andat least one P type metal oxide semiconductor disposed on the silicon dioxide layer at a position corresponding to the second light shielding region;wherein each of the N type metal oxide semiconductor and the P type metal oxide semiconductor has a gate electrode layer, a first control signal received by voltage pulses of the gate electrode layer is synchronized with a second control signal received by the light shielding layer in voltage variation.2. The control circuit of the thin film transistor according to claim 1 , wherein the N type metal oxide ...

CLOCK SPURS REDUCTION TECHNIQUE

Aspects of the disclosure provide a circuit having a jittered clock generator. The jittered clock generator is configured to add jitter of a controlled characteristic to a first clock signal of a clock frequency to generate a second clock signal to be used by a transceiver for operating at a radio frequency. The jitter of the controlled characteristic adjusts a clock harmonic at the radio frequency of the transceiver. 1. A circuit comprising:a jittered clock generator configured to add jitter of a controlled characteristic to a first clock signal of a clock frequency to generate a second clock signal to be used by a transceiver for operating at a radio frequency, the jitter of the controlled characteristic adjusting a clock harmonic at the radio frequency of the transceiver.2. The circuit of claim 1 , wherein the jittered clock generator further comprises:a jitter controller configured to generate a control signal as a function of the specific clock harmonic; anda jitter generator configured to add the jitter according to the control signal to the first clock signal to generate the second clock signal.3. The circuit of claim 2 , wherein the jitter generator is configured to add a variable delay to the first clock signal to generate the second clock signal.4. The circuit of claim 2 , wherein the jitter generator comprises a delay chain of a plurality of delay elements to add an additional amount of delay to the first clock signal.5. The circuit of claim 4 , wherein the jitter generator comprises an edge selector configured to vary a selection of one of the delay elements to output the second clock in order to change the variable delay of the second clock signal to the first clock signal.6. The circuit of claim 5 , wherein the jitter controller is configured to generate a sequence of selection codes to control the edge selector to vary the selection of the delay elements.7. The circuit of claim 6 , wherein the jitter controller is configured to generate the sequence ...

PROGRAMMABLE DELAY CIRCUIT

A computing circuit that includes clocked circuitry, a controller, and a clock generator. The clocked circuitry is configured to receive data and to perform data manipulation on the data based on a first clock signal. The controller is configured to control the transmission of the data to the clocked circuitry. The clock generator is configured to receive as inputs a second clock signal and a delay control signal from the controller, and to delay the second clock signal to generate the first clock signal. The clock generator includes a main delay component configured to receive the second clock signal and to output the first clock signal. The clock generator also includes a switchable delay component connected in parallel with the main delay component, where the switchable delay component is configured to receive as an input the delay control signal from the controller. 1. A computing circuit , comprising:clocked circuitry configured to receive data and perform data manipulation on the data based on a first clock signal;a controller configured to control the transmission of the data to the clocked circuitry; anda clock generator configured to receive as inputs a second clock signal and a delay control signal from the controller, and configured to delay the second clock signal to generate the first clock signal, the clock generator comprising:a main delay component configured to receive the second clock signal and output the first clock signal; anda switchable delay component connected in parallel with the main delay component, the switchable delay component configured to receive as an input the delay control signal from the controller.2. The computing circuit of claim 1 , wherein the switchable delay component corresponds to a delay that is less than the main delay component.3. The computing circuit of claim 1 , wherein the switchable delay component corresponds to a delay that is more than the main delay component.4. The computing circuit of claim 1 , wherein the ...

DELAY CIRCUIT AND DIGITAL TO TIME CONVERTER

A delay circuit includes a first inverter in which a delay time of rising is larger than a delay time of falling, and a second inverter which is connected in series with the first inverter and in which a delay time of falling is larger than a delay time of rising. Transistors for each of the first and second inverters are connected in series between a power supply terminal and a ground terminal. 1. A delay circuit comprising:a first inverter in which a delay time of rising is larger than a delay time of falling; anda second inverter which is connected in series with the first inverter, and in which a delay time of falling is larger than a delay time of rising,wherein transistors for each of the first inverter and the second inverter are connected in series between a first power terminal and a second power terminal.2. The delay circuit according to claim 1 , wherein the first power terminal is connected to a power supply and the second power terminal is connected to ground.3. The delay circuit according to claim 2 , wherein an output signal of the first inverter is supplied to the second inverter as an input signal.4. The delay circuit according to claim 1 , wherein the transistors for the first inverter are laid out on a semiconductor substrate in a single line and the transistors for the second inverter are laid out on the semiconductor substrate in a single line.5. The delay circuit according to claim 4 , wherein gate widths of the transistors for the first and second inverters are the same.6. The delay circuit according to claim 1 , wherein a first P-type transistor; and', 'a first N-type transistor which is connected in series with the first P-type transistor, and whose driving force is smaller than a driving force of the first P-type transistor; and, 'the first inverter includes a second P-type transistor; and', 'a second N-type transistor which is connected in series with the second P-type transistor, and whose driving force is larger than a driving force of ...

CLOCK GATING USING A DELAY CIRCUIT

An apparatus includes a latch of a clock gating circuit (CGC). The latch is configured to generate a first signal in response to a clock signal. The apparatus further includes a delay circuit of the CGC. The delay circuit is configured to receive the clock signal and to generate a second signal based on the clock signal and the first signal. The apparatus further includes an output circuit of the CGC. The output circuit is coupled to the delay circuit and to the latch. The output circuit is configured to generate a master clock signal based on the clock signal and the second signal. An edge of the master clock signal is delayed with respect to an edge of the clock signal based on a delay characteristic associated with a slave clock signal. 1. An apparatus comprising:a latch of a clock gating circuit (CGC), the latch configured to generate a first signal in response to a clock signal; anda delay circuit of the CGC, the delay circuit configured to receive the clock signal and to generate a second signal based on the clock signal and the first signal; andan output circuit of the CGC, the output circuit coupled to the delay circuit and to the latch, the output circuit configured to generate a master clock signal based on the clock signal and the second signal, wherein an edge of the master clock signal is delayed with respect to an edge of the clock signal based on a delay characteristic associated with a slave clock signal.2. The apparatus of claim 1 , further comprising a second latch of the CGC claim 1 , wherein the latch and the delay circuit form a first gating sub-circuit claim 1 , and wherein the second latch and the output circuit form a second clock gating sub-circuit.3. The apparatus of claim 1 , wherein the master clock signal has a falling edge that is delayed with respect to a falling edge of the clock signal.4. The apparatus of claim 1 , wherein the delay circuit includes an AND device.5. The apparatus of claim 4 , wherein the AND device has a first input ...

INTERPOLATION APPARATUS FOR ENCODER, CONTROLLING METHOD OF INTERPOLATION APPARATUS FOR ENCODER, NON-TRANSITORY STORAGE MEDIUM STORING CONTROLLING PROGRAM OF INTERPOLATION APPARATUS FOR ENCODER AND ENCODER

An AD converter acquires first and second input values. A first multiplication unit multiplies a first tangent value, which is based on a first boundary angle based on a phase range of a reference value, by the reference value to calculate a first threshold value. A second multiplication unit multiplies a second tangent value, which is based on a second boundary angle based on the phase range, by the reference value to calculate a second threshold. A comparison unit determines whether the comparison value is within a particular phase range specified by the first and the second thresholds. The comparison unit determines magnitude of the comparison value when the comparison value is not within the particular phase range. A phase estimation unit updates the particular phase range to a phase range adjacent to a direction corresponding to the result of determination. 1. An interpolation apparatus for an encoder comprising:an AD converter which converts a first sine wave signal generated in accordance with a change of the position of a measurement object into a digital signal to acquire a first input value, and converts a second sine wave signal which is generated in accordance with the change of the position of the measurement object and which is 90° different in phase from the first sine wave signal into a digital signal to acquire a second input value;a first multiplication unit which uses one of the first input value and the second input value as a reference value and uses the other as a comparison value to multiply a first tangent value by the reference value to calculate a first threshold, the first tangent value being based on a first boundary angle decided on the basis of the phase range of the reference value;a second multiplication unit which multiplies a second tangent value by the reference value to calculate a second threshold, the second tangent value being based on a second boundary angle decided on the basis of the phase range of the reference value;a ...

POWER EFFICIENT MULTIPLEXER

A power efficient multiplexer. In accordance with a first embodiment, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for inverting the one of a plurality of input signals. Both the stacked inverter and the transmission gate provide beneficial reductions in static power consumption in comparison to conventional multiplexer designs. 1. A circuit , comprising:a transmission gate structure including a plurality of input nodes and an output node; and an inverter input node coupled to the output node;', 'a low-to-high transition leg comprising a first number of transistors;', 'a high-to-low transition leg comprising a second number of transistors that is different relative to the first number of transistors; and', 'an inverter output node coupled to the low-to-high transition leg and to the high-to-low transition leg., 'a stacked inverter including2. The circuit of claim 1 , wherein the first number of transistors is greater than the second number of transistors.3. The circuit of claim 1 , wherein the first number of transistors is less than the second number of transistors.4. The circuit of claim 1 , wherein the first number of transistors comprises p-type transistors claim 1 , and wherein each p-type transistor includes a respective gate coupled to the inverter input node.5. The circuit of claim 1 , wherein the second number of transistors comprises n-type transistors claim 1 , and wherein each n-type transistor includes a respective gate coupled to the inverter input node.6. The circuit of claim 1 , wherein the stacked inverter is operable to provide at the inverter output node an inverted version of an input value at a selected one of the plurality of input nodes.7. The circuit of claim 1 , wherein the transmission gate structure further comprises:a first transmission gate coupled between a first input node of the plurality of input nodes and the output ...

BUFFER CONTROL CIRCUIT AND MULTI-CHIP PACKAGE INCLUDING THE SAME

A buffer control circuit includes: an activation control block suitable for generating a buffer activation control signal by detecting a first input of a repeatedly provided chip select signal; and a buffer suitable for buffering the chip select signal in response to the buffer activation control signal after the generation of the buffer activation control signal. 1. A buffer control circuit , comprising:an activation control block suitable for generating a buffer activation control signal by detecting a first input of a repeatedly provided chip select signal; anda buffer suitable for buffering the chip select signal in response to the buffer activation control signal after the generation of the buffer activation control signal.2. The buffer control circuit of claim 1 , wherein the activation control block generates the buffer activation control signal claim 1 , which is enabled a predetermined time after the first input of the chip select signal.3. The buffer control circuit of claim 2 , wherein the activation control block includes:a shift unit suitable for generating a plurality of control signals in response to a clock signal by sequentially shifting the chip select signal;a latch unit suitable for latching the chip select signal and the control signals in response to a last one among the control signals;a clock control unit suitable for generating a plurality of clock signals having different enabling time sections in response to an output signal of the latching unit;an input control signal generation unit suitable for generating a plurality of input control signals by sequentially shifting the chip select signal in response to the plurality of dock signals; andan activation control signal generation unit suitable for generating the buffer activation control signal by detecting rising and falling edges of each of the input control signals.4. The buffer control circuit of claim 3 , wherein the activation control signal generation unit includes a toggle ...