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Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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24-01-2018 дата публикации

Аналого-цифровой преобразователь

Номер: RU0000176659U1
Автор: Мария Сергеевна Жаворонкова, Сергей Николаевич Бондарь
Принадлежит: федеральное государственное бюджетное образовательное учреждение высшего образования "Ставропольский государственный аграрный университет"

Полезная модель относится к измерительной технике, в частности к аналого-цифровым преобразователям, и может быть использована в цифровых системах для измерения и контроля аналоговых величин. Технический результат, который может быть достигнут с помощью предлагаемой полезной модели, сводится к расширению функциональных возможностей, повышению точности или быстродействия или снижению сложности схемы. Расширение функциональных возможностей заключается в обеспечении возможности аналого-цифрового преобразования не только однополярных положительных, но также однополярных отрицательных и двуполярных сигналов. Устройство содержит схему сравнения, цифроаналоговый преобразователь, триггер, генератор импульсов, счетчик, регистр, постоянное запоминающее устройство, блок предсказания, блок определения знака и инвертирования отрицательных напряжений, в состав которого входят аналоговый инвертор, компаратор, два аналоговых ключа. 1 табл., 5 ил. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 176 659 U1 (51) МПК H03M 1/38 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК H03M 1/38 (2006.01); H03M 1/46 (2006.01) (21)(22) Заявка: 2017119127, 31.05.2017 (24) Дата начала отсчета срока действия патента: 24.01.2018 Приоритет(ы): (22) Дата подачи заявки: 31.05.2017 (45) Опубликовано: 24.01.2018 Бюл. № 3 1 7 6 6 5 9 R U (54) АНАЛОГО-ЦИФРОВОЙ ПРЕОБРАЗОВАТЕЛЬ (57) Реферат: Полезная модель относится к измерительной технике, в частности к аналого-цифровым преобразователям, и может быть использована в цифровых системах для измерения и контроля аналоговых величин. Технический результат, который может быть достигнут с помощью предлагаемой полезной модели, сводится к расширению функциональных возможностей, повышению точности или быстродействия или снижению сложности схемы. Расширение функциональных возможностей заключается в обеспечении возможности аналого-цифрового Стр.: 1 (56) Список документов, цитированных в отчете о поиске: RU 2205500 C1, ...

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Номер записи: 1
17-08-2020 дата публикации

Последовательный преобразователь двухполярного напряжения в двоичный код последовательного приближения

Номер: RU0000199113U1
Автор: Сергей Ильич Зиатдинов
Принадлежит: Федеральное государственное автономное образовательное учреждение высшего образования "Санкт-Петербургский государственный университет аэрокосмического приборостроения"

Полезная модель относится к вычислительной технике и может быть использована при цифровой обработке сигналов для преобразования двухполярного напряжения в цифровой двоичный код с увеличенным динамическим диапазоном преобразования. Последовательный преобразователь двухполярного напряжения в двоичный код последовательного приближения обеспечивает преобразование как положительного, так и отрицательного напряжения в двоичный код, а также увеличивает динамический диапазон преобразования в два раза, за счет того, что включает n-разрядный параллельный цифроаналоговый преобразователь, n разрядных триггеров, n двухвходовых дизъюнктора сброса разрядных триггеров, n двухвходовых конъюнкторов, n+1-разрядный сдвигающий регистр, двухвходовой дизъюнктор подачи тактовых импульсов, линию задержки, двухвходовой дизъюнктор окончания преобразования, триггер начала преобразования, генератор тактовых импульсов, двухвходовой конъюнктор подачи тактовых импульсов, двухвходовой логический сумматор по модулю два, знаковый компаратор, компаратор, логический инвертор, второй аналоговый ключ, первый аналоговый ключ, аналоговый сумматор и аналоговый инвертор. Преобразование двухполярного напряжения в двоичный код достигается за счет того, что в составе преобразователя имеется аналоговый инвертор и два аналоговых ключа, позволяющие сравнивать в компараторе положительное преобразуемое напряжение с положительным напряжением с выхода цифроаналогового преобразователя и при отрицательном преобразуемом напряжении - с отрицательным напряжением после инверсии выходного напряжения цифроаналогового преобразователя. 1 ил. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 199 113 U1 (51) МПК H03M 1/38 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК H03M 1/38 (2020.02) (21)(22) Заявка: 2020110478, 12.03.2020 (24) Дата начала отсчета срока действия патента: Дата регистрации: 17.08.2020 Приоритет(ы): (22) Дата подачи заявки: 12.03.2020 (45) Опубликовано: 17.08 ...

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Номер записи: 2
19-04-2012 дата публикации

Analog to digital converter

Номер: US20120092202A1
Автор: John Kikidis, Michael Birbas, Nikolaos Petrellis
Принадлежит: ANALOGIES SA

An analog to digital converter for converting an initial analog signal into a digital signal comprising at least one electronic module with an input, a first output, and a second output, which module generates from an analog input signal: a first output signal, which first output signal in terms of multiples of a predetermined amount of current or voltage, such as 1 uA or 1 mV, is substantially equal to the integer quotient of division of the input signal by a number or comprises a plurality of signals which if combined are substantially equal to the integer quotient of division of the input signal in terms of multiples of a predetermined amount of current or voltage, and a second output signal which in terms of multiples of a predetermined amount of current or voltage, such as 1 uA or 1 mV, is substantially equal to the remainder of the division, the analog to digital converter also comprising a further analog to digital converter for converting the second output signal into a digital signal, wherein the further analog to digital converter is connected the at least one module and the module is configured so that in use when the analog input signal connects through the input the first output signal connects through the first output, and the second output signal connects through the second output into the further analog to digital converter.

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Номер записи: 3
03-05-2012 дата публикации

Hysteresis-Compensating Interpolation Circuits in Optical Encoders

Номер: US20120104236A1
Автор: Chung Min Thor, Gim Eng Chew, Weng Chong Sam
Принадлежит: Avago Technologies ECBU IP Singapore Pte Ltd

Disclosed are various embodiments of circuitry and methods to compensate for variations in hysteresis associated with the comparators of an interpolation circuit in a single track optical encoder. Such variations in hysteresis may be minimized or eliminated by providing appropriately configured resistor ladder circuits to condition the inputs to the comparators, or by programming or trimming resistors in positive feedback loops of the comparators. The single track optical encoder configurations disclosed herein permit very high resolution reflective optical encoders in small packages to be provided. Methods of making and using such optical encoders are also disclosed.

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Номер записи: 4
04-10-2012 дата публикации

Adc calibration

Номер: US20120249351A1
Автор: Cheng Yen Weng, Fang-Shi Jordan Lai, Hsu-Feng Hsueh, Kuo-Ming Wang, Yung-Fu Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An analog-to-digital converter (ADC) including a plurality of comparators connected to the ADC. The ADC further includes a first pair of terminals and a second pair of terminals connected to each of the plurality of comparators. The ADC further includes a first pair of switches coupled to each of the first pair of terminals and a second pair of switches coupled to each of the second pair of terminals, where the first and second pair of switches are configured to alternate a corresponding comparator between normal operation and a calibration configuration. Comparators other than the corresponding comparator are configured for normal operation if the corresponding comparator is configured to be calibrated.

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Номер записи: 5
13-12-2012 дата публикации

Ad converter

Номер: US20120313801A1
Автор: Shinroku Maejima, Yoshinori Tokioka
Принадлежит: Renesas Electronics Corp

To provide a highly accurate and small AD converter. The AD converter converts an analog voltage Vin into a digital code DC of N-bit, and includes memory blocks MB 1 to MB (2 N −1). Each memory block MB (2 n −1) includes (2 n −1) memory cells 1 for an MRAM. After stored data of the memory cell 1 is reset to “0”, an analog current Iin proportional to the analog voltage Vin is shunted to the (2 n −1) bit lines BL of the each memory block MB (2 n −1). Stored data of the memory cells 1 of the memory blocks MB 1 to MB (2 N −1) is read to generate the digital code DC. Accordingly, a ladder resistance is unnecessary.

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Номер записи: 6
10-01-2013 дата публикации

Biological analog-to-digital and digital-to-analog converters

Номер: US20130009799A1
Автор: James J. Collins, Timothy Kuan-Ta Lu
Принадлежит: Boston University, Massachusetts Institute of Technology

Described herein are novel biological converter switches that utilize modular components, such as genetic toggle switches and single invertase memory modules (SIMMs), for converting analog inputs to digital outputs, and digital inputs to analog outputs, in cells and cellular systems. Flexibility in these biological converter switches is provided by combining individual modular components, i.e., SIMMs and genetic toggle switches, together. These biological converter switches can be combined in a variety of network topologies to create circuits that act, for example, as switchboards, and regulate the production of an output product(s) based on the combination and nature of input signals received.

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Номер записи: 7
28-02-2013 дата публикации

Sample and hold circuit and a/d converter

Номер: US20130050002A1
Автор: Hikaru Watanabe
Принадлежит: Toyota Motor Corp

The present invention is related to a sample and hold circuit and an A/D converter, and prevents an output saturation for an input voltage over a power supply voltage range in the sample and hold circuit. A first switch which is turned on when an input voltage is to be sampled; a sampling capacitor configured to sample the input voltage input via the first switch when the first switch is turned on, and sample a predetermined reference voltage when the first switch is turned off; an adding/subtracting part configured to perform an addition or a subtraction between the input voltage sampled by the sampling capacitor and the predetermined reference voltage sampled by the sampling capacitor; and a hold part configured to hold and output a voltage obtained by the addition or the subtraction by the adding/subtracting part are provided.

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Номер записи: 8
02-05-2013 дата публикации

DIGITAL-TO-ANALOG CONVERTER, ANALOG-TO-DIGITAL CONVERTER, AND SEMICONDUCTOR DEVICE

Номер: US20130106636A1
Автор: Amano Kiyotaka, Asayama Go, FUKUSHIMA Noriyuki, Muramatsu Yoshinori, Nitta Yoshikazu
Принадлежит: SONY CORPORATION

A DA conversion device includes the following elements. A higher-bit current source cell portion includes uniformly weighted higher-bit current source cells to generate an identical constant current. A lower-bit current source cell portion includes a lower-bit current source cells that are weighted to generate 1/two-to-the-power-of-certain-numbers constant currents. A constant current source selection controller includes a lower-bit controller having a scaler that uses clocks scaled down to 1/two-to-the-power-of-certain-numbers to select the lower-bit current source cells, and a higher-bit controller having shift registers and using a signal indicating a carry bit or a borrow bit used in the lower-bit controller to sequentially activate shift outputs of the shift registers, and uses the shift outputs to select the higher-bit current source cells. Constant current outputs of the selected current source cells are added and output so that an output current corresponding to the digital input signal is obtained. 1. A digital-to-analog conversion device comprising:a higher-bit current source cell portion including a plurality of higher-bit current source cells that are uniformly weighted to generate an identical constant current;a lower-bit current source cell portion including a plurality of lower-bit current source cells that are weighted to generate constant currents which are 1/two-to-the-power-of-certain-numbers of the constant current generated by the higher-bit current source cells; anda constant current source selection controller operable to select the higher-bit current source cells of the higher-bit current source cell portion and the lower-bit current source cells of the lower-bit current source cell portion in accordance with a data value of a digital input signal,wherein the constant current source selection controller includes a lower-bit controller and a higher-bit controller, and the lower-bit controller includes a scaler that performs a scaling operation ...

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Номер записи: 9
30-05-2013 дата публикации

AD CONVERSION CIRCUIT AND IMAGING APPARATUS

Номер: US20130134296A1
Автор: Hagihara Yoshio
Принадлежит: OLYMPUS CORPORATION

An AD conversion circuit includes a reference signal generation unit, which generates a reference signal, a comparison unit, which ends a comparison process at a timing at which the reference signal has satisfied a predetermined condition with respect to the analog signal, a first path in which a signal is transferred through each of n delay units, a clock signal generation unit, which outputs a lower-order phase signal, a latch unit, which latches the lower-order phase signal, a higher-order count unit including a first counter circuit, which acquires a higher-order count value by performing a count operation using a signal output from any one of the delay units, a calculation unit, which generates a lower-order count signal, and a lower-order count unit, which acquires a lower-order count value by performing the count operation using the lower-order count signal. 1. An analog-to-digital (AD) conversion circuit comprising:a reference signal generation unit configured to generate a reference signal that increases or decreases with the passage of time;a comparison unit configured to compare an analog signal serving as an AD conversion target with the reference signal and end a comparison process at a timing at which the reference signal has satisfied a predetermined condition with respect to the analog signal;a clock signal generation unit configured to have an oscillation circuit formed by n (n is an odd number greater than or equal to 3) delay units and including a first path in which a signal is transferred through each of the n delay units and a second path in which a signal is transferred by bypassing some of the n delay units, and output a lower-order phase signal including a plurality of signals output from the plurality of delay units;a latch unit configured to latch the lower-order phase signal at a timing related to the end of the comparison process;a higher-order count unit including a first counter circuit configured to acquire a higher-order count value ...

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Номер записи: 10
30-05-2013 дата публикации

ANALOG-TO-DIGITAL CONVERTER

Номер: US20130135132A1
Автор: LIU MING-HUANG, OU WEI-YANG
Принадлежит: SITRONIX TECHNOLOGY CORP.

The present invention provides an analog-to-digital converter, which comprises an integration circuit, a threshold signal generating circuit, a main comparison circuit, a sub comparison circuit, a counter, and a decoder. The integration circuit integrates an input signal and produces an integration signal. The threshold signal generating circuit generates a main threshold signal and a plurality of sub threshold signals. The main comparison circuit produces a plurality of main comparison signals according the integration signal and the main threshold signal. The sub comparison circuit produces a plurality of sub comparison signals according to the integration signal and the plurality of sub threshold signals. The counter counts the plurality of main comparison signals and produces a first counting signal. The decoder decodes the plurality of sub comparison signals and produces a second count signal. The first count signal and the second count signal are used for producing a digital signal. 1. An analog-to-digital converter , comprising:an integration circuit, integrating an input signal for producing an integration signal;a threshold signal generating circuit, generating a main threshold signal and a plurality of sub threshold signals;a main comparison circuit, producing a plurality of main comparison signals according to said integration signal and said main threshold signal;a sub comparison circuit, producing a plurality of sub comparison signals according to said integration signal and said plurality of sub threshold signals;a counter, counting said plurality of main comparison signals for producing a first counting signal; anda decoder, decoding said plurality of sub comparison signals for producing a second counting signal;where said first counting signal and said second counting signal are used for producing a digital signal.2. The analog-to-digital converter of claim 1 , and further comprising:a latch, latching said first counting signal and said second ...

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Номер записи: 11
13-06-2013 дата публикации

TIME DETECTION CIRCUIT, AD CONVERTER, AND SOLID STATE IMAGE PICKUP DEVICE

Номер: US20130146751A1
Автор: Hagihara Yoshio
Принадлежит: OLYMPUS CORPORATION

A time detection circuit may include: a delay unit configured to have a plurality of delay units, each of which delays and outputs an input signal, and start an operation at a first timing relating to an input of a first pulse; a latch unit configured to latch logic states of the plurality of delay units; a count unit configured to perform a count operation based on a clock output from one of the plurality of delay units; a count latch unit configured to latch a state of the count unit; and a latch control unit configured to enable the latch unit at a second timing relating to an input of a second pulse and cause the latch unit and the count latch unit to execute a latch at a third timing at which a predetermined time has elapsed from the second timing. 1. A time detection circuit comprising:a delay unit configured to have a plurality of delay units, each of which delays and outputs an input signal, and start an operation at a first timing relating to an input of a first pulse;a latch unit configured to latch logic states of the plurality of delay units;a count unit configured to perform a count operation based on a clock output from one of the plurality of delay units;a count latch unit configured to latch a state of the count unit; anda latch control unit configured to enable the latch unit at a second timing relating to an input of a second pulse and cause the latch unit and the count latch unit to execute a latch at a third timing at which a predetermined time has elapsed from the second timing.2. The time detection circuit according to claim 1 , wherein the delay unit is an annular delay circuit in which the plurality of delay units are connected in an annular shape.3. The time detection circuit according to claim 1 , further comprising:a comparison unit configured to receive an analog signal and a reference signal that increases or decreases with the passage of time and output a comparison signal when the reference signal has satisfied a predetermined ...

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Номер записи: 12
13-06-2013 дата публикации

LASER OPTICAL TOUCH CONTROL MODULE ANALOG-TO-DIGITAL CONVERSION SYSTEM AND METHOD OF THE SAME

Номер: US20130147766A1
Автор: CHEN Guo-Zen, Lin Shun-Cheng, Wen Ming-Hua
Принадлежит: SERAFIM TECHNOLOGIES INC.

A laser optical touch control module includes a light emitting part with a laser light source and a light receiving part with a position sensor. A laser beam is emitted from the laser light source and reflected by a wide angle optical element. Thus a light fan of the reflected light is larger than 90 degrees to form a wide angle linear light beam. The position of a touch control widget is obtained by a sensor of the light receiving part that detects the linear light beam blocked and reflected by the touch control widget. An analog-to-digital conversion system includes a variable reference level generator that calculates to generate a variable reference level according to different variances. Then the sensor output data is converted into a digital signal based on the reference voltage level by a digital comparator and the digital signal is output to a processor. 2. The module as claimed in claim 1 , wherein the light path of the light emitting part and the light path of the light receiving part are arranged horizontally and transversely.3. The module as claimed in claim 1 , wherein the wide angle optical element is a line generator optics.4. The module as claimed in claim 1 , wherein the light emitting part and the light receiving part are mounted in a housing with an opening to form an assembly.5. The module as claimed in claim 1 , wherein a micro lens is disposed on a sensing surface of the position sensor so that the reflected laser beam formed due to the touch control widget in contact with surface of the display is concentrated on the sensing surface.6. A laser optical touch control module disposed on one side of a display for providing optical positioning input function to form an optical touch control display contacted by a touch control widget comprising a light emitting part and a light receiving part; whereina laser beam is emitted from a laser light source of the light emitting part and is reflected by a wide angle optical element so that a light fan of ...

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Номер записи: 13
13-06-2013 дата публикации

Flexible crank angle position sensing

Номер: US20130151194A1
Автор: Doyle Kent Stewart, Wayne Hawken
Принадлежит: Woodward Inc

A flexible crank angle position sensing device and data structure is provided. The device allows a user to enter specific data into a data structure relating to an encoder wheel used to determine the position of the crank shaft. The specific data is stored in the device and can be recalled for use in specific engine implementations. Furthermore, a user can enter data to describe other encoder wheels associated with a cam shaft of an engine. A data structure relating to a cam shaft encoder wheel relates to the data structure relating to the crank shaft encoder wheel such that various positional information, regarding both the cam shaft and crank shaft, can be detected by the device.

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Номер записи: 14
27-06-2013 дата публикации

High-speed successive-approximation-register analog-to-digital converter and method thereof

Номер: US20130162454A1
Автор: Chia-Liang Lin
Принадлежит: Realtek Semiconductor Corp

In one embodiment, a SAR (successive-approximation register) ADC (analog-to-digital converter) comprising: a plurality of capacitors, a switch controlled by a sampling signal for connecting a common node to a ground node when the sampling signal is asserted; a plurality of switching networks controlled by the sampling signal and a plurality of control bits comprising a respective grounding bit and a respective data bit, each of the plurality of switching networks for connecting a bottom plate of a respective capacitor to an analog input signal, a ground node, a first reference voltage, or a second reference voltage depending on the asserted signal or bit; a comparator for detecting a polarity of a voltage at the common node and outputting a binary decision along with a complementary binary decision when a comparing signal is asserted; a logic gate for receiving the binary decision and the complementary binary decision and outputting a ready signal indicating whether a decision is readily made; a timer for receiving the comparing signal and outputting a time out signal; and a SAR logic for receiving the binary decision, the ready signal, and the time out signal and outputting the sampling signal, the comparing signal, the plurality of control bits, and an output data.

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Номер записи: 15
27-06-2013 дата публикации

Methods and Systems for Compressed Sensing Analog to Digital Conversion

Номер: US20130162457A1
Автор: Allstot David, Gangopadhyay Daibashish
Принадлежит: University of Washington through its Center for Communications

Disclosed herein are example methods, systems, and devices for compressed sensing analog to digital conversion. In an example embodiment, a multiplication circuit is configured to multiply an input signal with a measurement signal to produce a multiplied signal, where the measurement signal includes data from a column of a measurement matrix. The measurement matrix may be generated by a linear feedback shift register (LFSR)-based measurement-matrix generator. An integration circuit may be coupled to the multiplication circuit and configured to integrate the multiplied signal for a predefined amount of time to produce an integrated signal. An analog to digital converter (ADC) circuit may be coupled to the integration circuit and configured to (i) sample the integrated signal and (ii) produce an output signal comprising at least one sample of the integrated signal. Among other benefits of the disclosure herein, a column-wise multiplication of the input signal with the measurement signal enables an efficient compressed-sensing analog-to-digital conversion architecture. 1. A circuit comprising:a multiplication circuit configured to multiply an input signal with a measurement signal to produce a multiplied signal, wherein the measurement signal comprises data from a column of a measurement matrix;an integration circuit coupled to the multiplication circuit and configured to integrate the multiplied signal for a predefined amount of time to produce an integrated signal; andan analog to digital converter (ADC) circuit coupled to the integration circuit and configured to (i) sample the integrated signal and (ii) produce an output signal comprising at least one sample of the integrated signal.2. The circuit of claim 1 , wherein the measurement matrix comprises a plurality of entries claim 1 , the circuit further comprising:a measurement-matrix generator coupled to the multiplication circuit and configured to generate a random coefficient for each entry in the measurement ...

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Номер записи: 16
01-08-2013 дата публикации

ANALOG-DIGITAL CONVERTER, ANALOG-DIGITAL CONVERSION METHOD, IMAGE PICKUP DEVICE, METHOD OF DRIVING THE SAME, AND CAMERA

Номер: US20130193306A1
Автор: Nishi Takafumi
Принадлежит:

An analog-digital converter includes: comparators disposed to correspond to analog signals which are converted into digital signals and configured to compare a voltage value of the analog signal, which is converted into the digital signal, with a voltage value of a predetermined reference signal; counters disposed to correspond to the comparators and configured to count a count value at the time point when the comparison process of the corresponding comparator is finished; and a determiner configured to determine a time point when all the comparators finish their comparison processes. 116-. (canceled)17. An analog-digital converter comprising:comparators that compare a voltage value of an analog signal with a reference signal;counters that count a count value at a time point of a comparison process of a corresponding comparator;a voltage value storage that stores as a maximum voltage value a voltage value which is greater by a predetermined voltage than the voltage value of the analog signal having the maximum voltage value among analog signals converted into digital signals at a previous time and stores as a minimum voltage value a voltage value which is smaller by a predetermined voltage than the voltage value of the analog signal having the minimum voltage value among the analog signals converted into the digital signals at the previous time; anda reference signal generator that generates a down-count reference signal having as an initial voltage value the maximum voltage value stored in the voltage value storage or generates an up-count reference signal having as an initial voltage value the minimum voltage value stored in the voltage value storage.18. The analog-digital converter according to claim 17 , further comprising:a determiner configured to determine a time point when all the comparators finish their comparison processes.19. The analog-digital converter according to claim 17 , wherein each comparator compares a voltage value of the analog signal claim ...

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Номер записи: 17
08-08-2013 дата публикации

SIGNAL INTERPOLATION DEVICE AND PARALLEL A/D CONVERTING DEVICE

Номер: US20130201048A1
Автор: Itakura Tetsuro, Matsuno Junya
Принадлежит: KABUSHKI KAISHA TOSHIBA

There is provided a signal interpolation device, including: a first amplifier to generate a first signal representing a difference between an input signal and a first reference voltage; a second amplifier to generate a second signal representing a difference between the input signal and a second reference voltage; a first output amplifier to amplify the first signal to generate a first output signal; a second output amplifier to amplify the second signal to generate a second output signal; a third output amplifier to amplify a sum of a first interpolation signal and the first signal to generate a third output signal, the first interpolation signal representing a voltage generated by dividing a difference between the first reference voltage and the second reference voltage by “2̂n”; and a fourth output amplifier to amplify a difference between the second signal and the first interpolation signal to generate a fourth output signal. 1. A signal interpolation device , comprising:a first amplifier to generate a first signal representing a difference between an input signal and a first reference voltage;a second amplifier to generate a second signal representing a difference between the input signal and a second reference voltage;a first output amplifier to amplify the first signal to generate a first output signal;a second output amplifier to amplify the second signal to generate a second output signal;a third output amplifier to amplify a sum of a first interpolation signal and the first signal to generate a third output signal, the first interpolation signal representing a voltage generated by dividing a difference between the first reference voltage and the second reference voltage by “2̂n” (“n” is an integer of at least two); anda fourth output amplifier to amplify a difference between the second signal and the first interpolation signal to generate a fourth output signal.2. The device according to claim 1 , further comprisinga fifth output amplifier to amplify a sum ...

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Номер записи: 18
22-08-2013 дата публикации

Device, System and Method for Analogue-to-Digital Conversion Using a Current Integrating Circuit

Номер: US20130214947A1
Автор: Craninckx Jan, Yamamoto Takaya
Принадлежит:

A device including a sample and hold circuit for providing a signal related to an input analogue current signal, by sampling the input analogue current signal and integrating it on capacitive means, thereby charging the capacitive means to a charge value. The capacitive means being configurable to dynamically change its effective capacitance value in order to shape a voltage signal present on the capacitive means such that the charge value remains unchanged. The device also including an analogue-to digital conversion (ADC) and control circuit arranged for performing an ADC of the at least one related signal at the output of the sample and hold circuit into an output digital signal, the ADC and control circuit including successive approximation ADC means for considering the value of the voltage signal on the capacitive means and converting the charge value present in the capacitive means into the digital output signal.

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Номер записи: 19
22-08-2013 дата публикации

COMPARATOR, ANALOG-TO-DIGITAL CONVERTOR, SOLID-STATE IMAGING DEVICE, CAMERA SYSTEM, AND ELECTRONIC APPARATUS

Номер: US20130215303A1
Автор: Ueno Yosuke
Принадлежит: SONY CORPORATION

A comparator includes a first amplifier, a second amplifier, and a level holding part. The first amplifier includes differential-pair transistors and outputs a signal of a level corresponding to a comparison result from a first output node. The differential-pair transistors compare a reference voltage with a potential of an input signal. The second amplifier gain up the signal output from the first output node of the first amplifier and outputs the signal from a second output node. The level holding part holds a level of the second output node at a predetermined level. The second amplifier includes a transistor for amplification and a transistor for a current source. The level holding part holds the level of the second output node of the second amplifier such that the transistor for the current source does not fall into a level at which a saturated operation condition is not satisfied. 1. A comparator , comprising: 'the differential-pair transistors serving as a comparison part configured to compare a reference voltage with a potential of an input signal;', 'a first amplifier including differential-pair transistors and configured to output a signal of a level corresponding to a comparison result from a first output node,'}a second amplifier configured to gain up the signal output from the first output node of the first amplifier and output the signal from a second output node; and the second amplifier including', 'a transistor for amplification connected between the second output node and a power supply or a reference potential source and', 'a transistor for a current source connected between the second output node and the reference potential source or the power supply,', 'the level holding part holding the level of the second output node of the second amplifier such that the transistor for the current source of the second amplifier does not fall into a level at which a saturated operation condition is not satisfied., 'a level holding part configured to hold a level ...

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Номер записи: 20
05-09-2013 дата публикации

AD (ANALOG-TO-DIGITAL) CONVERSION CIRCUIT, MICRO-CONTROLLER, AND METHOD OF ADJUSTING SAMPLING TIME

Номер: US20130229295A1
Автор: YAMADA Toshimi
Принадлежит: LAPIS SEMICONDUCTOR CO., LTD.

An AD (analog-to-digital) conversion circuit includes a capacitor array formed of a plurality of capacitors; a sample hold circuit configured to apply an analog input voltage input through an input terminal to the capacitor array so that the analog input voltage is accumulated in the capacitor array until a sampling time set is elapsed; a comparator circuit configured to sequentially retrieve the analog input voltage accumulated in each of the capacitors of the capacitor array, and to compare the analog input voltage with a reference voltage defined in advance to generate a digital signal; and a sampling time adjusting circuit configured to measure a period of time when a voltage on an input side of the sample hold circuit reaches a threshold value defined in advance relative to the reference voltage, and to set a time determined according to the period of time as the sampling time. 1. An AD (analog-to-digital) conversion circuit , comprising:a capacitor array formed of a plurality of capacitors;a sample hold circuit configured to apply an analog input voltage input through an input terminal to the capacitor array so that the analog input voltage is accumulated in the capacitor array until a sampling time set is elapsed;a comparator circuit configured to sequentially retrieve the analog input voltage accumulated in each of the capacitors of the capacitor array, said comparator circuit being configured to compare the analog input voltage with a reference voltage defined in advance to generate a digital signal; anda sampling time adjusting circuit configured to measure a period of time when a voltage on an input side of the sample hold circuit, which increases according to an adjustment voltage input from an external device connected to the input terminal, reaches a threshold value defined in advance relative to the reference voltage, said sampling time adjusting circuit being configured to set a time determined according to the period of time thus measured as the ...

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Номер записи: 21
12-09-2013 дата публикации

Signal sensing circuit

Номер: US20130234875A1
Автор: Po-Chuan Lin
Принадлежит: Egalax Empia Technology Inc

A signal sensing circuit converts a received current input into a voltage output and provides the voltage output to an analog-to-digital converter (ADC) to generate a digital output signal. The voltage output is associated with a circuit having a first reference impedance, and a reference voltage of the ADC is associated with a circuit having a second reference impedance, wherein the circuit having the first reference impedance and the circuit having the second reference impedance are formed by the same material, so that the ratio between the changes in the current input and the changes in the value of the digital output signal is a constant.

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Номер записи: 22
10-10-2013 дата публикации

INTEGRATED CIRCUIT

Номер: US20130265180A1
Автор: Ito Masao, Matsumoto Osamu, MATSUMOTO Takashi, Suzuki Hiroto
Принадлежит:

A successive approximation register A/D converter that obtains an output of N bits interrupts operation at a timing when the operation of the successive approximation register A/D converter is affected on the basis of circuit timing in an integrated circuit. The A/D converter performs a comparison between a sampling signal and a comparison reference voltage by a sampling period in which an analog signal is sampled, a comparison period of N states in which the sampled signal is sequentially compared with a comparison voltage for each bit, and a reserve period of M states following the comparison period. When an operation is temporarily interrupted, the A/D converter performs a comparison operation of a bit, whereas the comparison is not performed in the reserve period. 1. An integrated circuit including a successive approximation register A/D (analog/digital) converter which obtains a comparison result of N bits (N is a number greater than or equal to 1) , the integrated circuit comprising:a conversion operation controller that determines an interruption timing of a comparison operation in the successive approximation register A/D converter on the basis of an operation timing of a predetermined circuit that interferes with an operation of the successive approximation register A/D converter,wherein the successive approximation register A/D converter obtains the comparison result of N bits by a sampling period in which an analog signal is sampled, a comparison period of N states in which the sampled signal is sequentially compared with a comparison voltage for each bit, and a reserve period of M states (M is a number greater than or equal to 1) which follows the comparison period and in which a comparison of M bits can be performed, andan operation is interrupted in accordance with the determined interruption timing and a comparison operation of a bit where the comparison is not performed enough in the comparison period due to the interruption is performed in the ...

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Номер записи: 23
10-10-2013 дата публикации

AUDIO DEVICE SWITCHING WITH REDUCED POP AND CLICK

Номер: US20130265184A1
Автор: Carpentier John L., Macaluso Steven, Stultz Julie Lynn
Принадлежит: Fairchild Semiconductor Corporation

This document discusses, among other things, apparatus and methods including an analog-to-digital controller (ADC) configured to receive an enable signal and to provide an ADC output signal to control logic, wherein the control logic is configured to provide a control voltage to a control input of a switch. In an example, the control voltage includes the ADC output signal when the ADC output signal is below a first threshold or above a second threshold. In certain examples, the control logic is configured to transition the control voltage from the first threshold to the second threshold when the ADC output signal is between the first and second thresholds. 1. An apparatus comprising:an analog-to-digital controller (ADC) configured to receive an enable signal and to provide an ADC output signal including a plurality of voltage steps depending on the value of the enable signal; andcontrol logic configured to receive the ADC output signal and to provide a control voltage to a control input of a switch,wherein the control voltage includes the ADC output signal when the ADC output signal is below a first threshold or above a second threshold, andwherein the control logic is configured to transition the control voltage from the first threshold to the second threshold when the ADC output signal is between the first and second thresholds.2. The apparatus of claim 1 , including the switch including first and second terminals and the control input.3. The apparatus of claim 1 , including:a capacitor coupled between an input of the ADC and ground.4. The apparatus of claim 1 , including:a series resistor-capacitor (RC) circuit coupled to an input of the ADC.5. The apparatus of claim 1 , wherein the switch includes an audio switch configured to switch an audio signal between the first and second terminals.6. The apparatus of claim 1 , wherein the switch includes a transistor including a gate claim 1 , a source claim 1 , and a drain claim 1 ,wherein the control input includes the ...

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Номер записи: 24
17-10-2013 дата публикации

SINGLE SLOPE AD CONVERTER CIRCUIT PROVIDED WITH COMPARTOR FOR COMPARING RAMP VOLTAGE WITH ANALOG INPUT VOLTAGE

Номер: US20130271308A1
Автор: HIROSE Tetsuya, OSAKI Yuji
Принадлежит: Semiconductor Technology Academic Research Center

A single slope AD converter circuit includes a comparator that compares a ramp voltage varying with a predetermined slope as time elapses with an analog input voltage, a counter that counts a predetermined clock in parallel with the comparing process of the comparator, and a controller that outputs a clock count value corresponding to elapsed time when the ramp voltage is smaller than the analog input voltage, as an AD converted first digital value. The comparator compares the ramp voltage with a predetermined first reference voltage, the counter counts the clock in parallel with the comparing process, and the controller outputs the clock count value corresponding to the elapsed time as an AD converted second digital value. 1. A single slope AD converter circuit , comprising:a comparator configured to compare a ramp voltage varying with a predetermined slope as time elapses with an analog input voltage;a counter configured to count a predetermined clock in parallel with the comparing process of the comparator, anda controller configured to output a clock count value corresponding to elapsed time when the ramp voltage is smaller than the analog input voltage, as an AD converted first digital value, wherein(A) the comparator compares the ramp voltage with a predetermined first reference voltage, the counter counts the clock in parallel with the comparing process, and the controller outputs the clock count value corresponding to the elapsed time as an AD converted second digital value,(B) the comparator compares the ramp voltage with a predetermined second reference voltage different from the first reference voltage, the counter counts the clock in parallel with the comparing process, and the controller outputs the clock count value corresponding to the elapsed time as an AD converted third digital value, and(C) the controller divides one of a difference between the first and second digital values, and a difference between the first and third digital values, by a ...

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Номер записи: 25
07-11-2013 дата публикации

SOLID-STATE IMAGING DEVICE, IMAGING DEVICE, ELECTRONIC EQUIPMENT, A/D CONVERTER AND A/D CONVERSION METHOD

Номер: US20130293754A1
Автор: IWASA Hiroshi, Kikuchi Masaru, Wakabayashi Hayato, Yamagata Yuuki
Принадлежит:

In a reference signal comparison AD conversion scheme, a reference signal SLP_ADC and each of P and D phases of a pixel signal voltage Vare compared. A count clock CKcnt is counted based on the comparison result. The counting result data is converted into signal data Dsig, i.e., the difference between the P and D phases, which is also subjected to CDS. At this time, the n-bit AD conversion is performed on each of the P and D phases of the pixel signal voltage V, followed by summation for digital integration. This prevents any possible detrimental effects that may be caused by summation in the analog domain. Although the signal data becomes W times greater, noise will likely become √W times greater. This alleviates the problem of random noise resulting from AD conversion such as quantizing noise and circuit noise that do not exist in the analog domain, thus reducing the noise. 1. An electronic apparatus , comprising:an imaging lens; 'an analog to digital (A/D) conversion unit, the A/D conversion unit', 'a solid-state imaging device, wherein the solid-state imaging device receives light guided by the imaging lens onto the solid-state imaging device, the solid-state imaging device including a reference signal generation section that generates a reference signal whose level changes gradually;', 'a comparison section the compares the reference signal and a target analog signal; and', 'a counter section that performs a counting based on a count clock and a result of the comparison of the reference signal and the target analog signal, the A/D conversion unit obtaining digital data of the target analog signal based on output data of the counter section,', 'a drive control section that controls the reference signal generation section and the A/D conversion unit to perform a digital integration that repeats an n-bit A/D conversion on the target analog signal W times, where W is a positive integer equal to or greater than 2,', 'the solid-state imaging device further comprising ...

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Номер записи: 26
14-11-2013 дата публикации

A/D CONVERSION CIRCUIT AND SOLID-STATE IMAGING DEVICE

Номер: US20130299676A1
Автор: Tanaka Takanori
Принадлежит: OLYMPUS CORPORATION

An A/D conversion circuit and a solid-state imaging device are able to reduce current consumption, and two input terminals of a NAND element included in a latch circuit receive a corresponding one of a plurality of clock signals and an enable signal. The enable signal is not input to the NAND element before an end timing of A/D conversion, and is input to the NAND element at the end timing of the A/D conversion and at a timing at which latching is performed. The latch circuit latches no clock signal when the enable signal is not input. 1. An A/D conversion circuit comprising:a reference signal generation portion that generates a reference signal that increases or decreases with lapse of time from a predetermined start timing;a comparison portion that compares an analog signal with the reference signal, and outputs a comparison signal at an end timing at which the reference signal satisfies a predetermined condition with respect to the analog signal;a phase shift portion that outputs a plurality of clock signals having different phases from one another in response to a time change from the start timing;a latch portion including a plurality of latch units, each of the plurality of latch units latching a corresponding one of the plurality of clock signals after a predetermined time lapses from an end timing based on the comparison signal; andan operation portion that generates a digital signal according to a signal held in the latch portion,wherein each of the plurality of latch units includes a logic element having a first input terminal and a second input terminal,wherein the first input terminal receives the corresponding one of the plurality of clock signals,wherein the second input terminal does not receive an enable signal before the end timing based on the comparison signal and receives the enable signal at the end timing based on the comparison signal and at a timing at which the latch portion performs latching, andwherein each of the plurality of latch units ...

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Номер записи: 27
14-11-2013 дата публикации

SOLID-STATE IMAGING DEVICE AND CAMERA SYSTEM

Номер: US20130300907A1
Автор: Tanaka Kenichi
Принадлежит:

A solid-state imaging device and a camera system are provided. The solid-state imaging device capable of performing an intermittent operation includes a pixel unit and a pixel signal readout unit for reading out a pixel signal from the pixel unit in units of a plurality of pixels for each column. The pixel signal readout circuit includes a plurality of comparators and a plurality of counters whose operations are controlled by outputs of the comparators. Each of the comparators includes an initializing switch for determining an operating point for each column at a start of row operation, and is configured so that an initialization signal to be applied to the initializing switch is controlled independently in parallel only a basic unit of the initialization signal used for a horizontal intermittent operation, and the initializing switch is held in an off-state at a start of non-operating row. 16-. (canceled)7. An image data processing circuit comprising:a plurality of analog-to-digital converters, each respectively configured to convert an analog signal to a digital signal, each of the plurality of analog-to-digital converters including;a comparator unit configured to compare the analog signal with a reference voltage to output a determination signal;a storing unit configured to store a digital signal corresponding to the analog signal based on the determination signal;wherein an initializing switch sets an initial operating point before analog-to-digital conversion operation is initiated, and an intermittent operation includes at least one non-operating analog-to-digital converter,a first group of the initializing switches corresponding to operating analog-to-digital converters is in an ON state; anda second group of the initializing switches corresponding to non-operating analog-to-digital converters is periodically in an OFF-state, and further wherein the second group of initializing switches are selectively turned off during an image data thinning mode.8. An ...

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Номер записи: 28
05-12-2013 дата публикации

AD CONVERTER CIRCUIT AND AD CONVERSION METHOD

Номер: US20130321189A1
Автор: Chen Yanfei, Ide Tatsuya, YOSHIOKA Masato
Принадлежит:

A low-power and high-speed ADC includes: a successive approximation converter circuit configured to sequentially compare and coarsely convert the analog input signal voltage into a digital signal with a number of higher-order bits, and also to output a residual voltage; a fixed-quantity change time measurement converter circuit configured to finely convert the residual voltage into a digital signal with a number n of lower-order bits by changing the residual voltage at a fixed rate of change and by measuring the time until a predetermined value is reached; and an encoder circuit configured to generate a digital signal with the predetermined number of bits by combining the digital signal with the number of higher-order bits output from the successive approximation converter circuit and the digital signal with the number of lower-order bits output from the fixed-quantity change time measurement converter circuit. 1. An analog-to-digital converter circuit configured to convert an analog input signal voltage into a digital signal with a predetermined number of bits , comprising:a successive approximation converter circuit configured to sequentially compare and coarsely convert the analog input signal voltage into a digital signal with a number of higher-order bits, and also to output a residual voltage between the analog input signal voltage and an analog signal voltage corresponding to the digital signal with the number of higher-order bits;a fixed-quantity change time measurement converter circuit configured to finely convert the residual voltage into a digital signal with a number n of lower-order bits by changing the residual voltage at a fixed rate of change and by measuring the time until a predetermined value is reached; andan encoder circuit configured to generate a digital signal with the predetermined number of bits by combining the digital signal with the number of higher-order bits output from the successive approximation converter circuit and the digital ...

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Номер записи: 29
05-12-2013 дата публикации

ANALOGUE-TO-DIGITAL CONVERTER

Номер: US20130321190A1
Автор: Lesso John Paul, Pennock John Laurence
Принадлежит: Wolfson Microelectronics pIc

An apparatus and method for regulating analogue-to-digital converters. First and second input signals are received at controlled oscillator circuitry which generates respective first and second pulse streams with pulse rates based on the relevant input signal. Difference circuitry determines the difference in number of pulses of the first and second pulse streams and outputs a first digital signal. Circuitry also determines a signal independent value based on the number of pulses of the first and/or second pulse streams. In one embodiment this value is the sum or average of the number of pulses of the first and second pulse streams. This value can be used to calibrate for any variation in transfer characteristic of the oscillator circuitry. In one embodiment this value is compared to a reference value and a regulation signal passed to control circuitry to regulate the operation of the oscillation circuitry. 1. An analogue-to-digital converter for receiving a differential analogue input signal comprising first and second input analogue signals , wherein said first and second analogue input signals exhibit equal and opposite modulations about a reference signal level , the converter comprising;controlled oscillator circuitry for generating first and second pulse streams with pulse rates dependent on the first and second input signals respectively; 'regulation circuitry for generating a regulation signal for modulating the operating conditions of the analogue-to-digital', 'difference circuitry, responsive to a clock signal, for generating a first digital signal based on the difference in number of pulses of the first and second pulse streams; and'}wherein the regulation circuitry is configured to generate a first value based on the number of pulses of the first and/or second pulse streams; andsaid the regulation signal is based on the first value.2. An analogue-to-digital converter as claimed inwherein the regulation circuitry is configured to generating said ...

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Номер записи: 30
26-12-2013 дата публикации

COUNTER, COUNTING METHOD, AD CONVERTER, SOLID-STATE IMAGING DEVICE, AND ELECTRONIC DEVICE

Номер: US20130343506A1
Автор: Hisamatsu Yasuaki
Принадлежит: SONY CORPORATION

A counter configured to perform counting at both edges of an input clock to output an additional value or a subtraction value for a previous count value and a next count value includes a first latch circuit that latches the input clock, a second latch circuit that latches an output from the first latch circuit, a holding section that holds data of the 0th bit of a count value, and a correction section that performs count correction on data of the first and subsequent bits of the count value on the basis of an output of the second latch circuit. 1. A counter configured to perform counting at both edges of an input clock to output an additional value or a subtraction value for a previous count value and a next count value , comprising:a first latch circuit that latches the input clock;a second latch circuit that latches an output from the first latch circuit;a holding section that holds data of the 0th bit of a count value; anda correction section that performs count correction on data of the first and subsequent bits of the count value on the basis of an output of the second latch circuit and an output of the holding section.2. The counter according to claim 1 ,wherein, when it is determined on the basis of clock latch data of the next count value which is the output of the second latch circuit and data of the 0th bit of the previous count value which is the output of the holding section that count correction is to be performed on the data of the first and subsequent bits of the count value, the correction section performs count correction on the data of the first and subsequent bits of the count value by giving a pulse to an input clock in a state where the first latch circuit is put into a through state.3. The counter according to claim 1 , further comprising:a generation section that generates data of the 0th bit of the next count value on the basis of clock latch data of the next count value which is an output of the second latch circuit and data of the 0th bit ...

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Номер записи: 31
16-01-2014 дата публикации

Mixed mode analog to digital converter and method of operating the same

Номер: US20140015702A1
Автор: Jaewon Nam
Принадлежит: Electronics and Telecommunications Research Institute ETRI

An analog to digital converter in accordance with the inventive concept may include a reference voltage generation circuit outputting first and second reference voltages; a decompression part decompressing amplitude of an analog input signal and the first and second reference voltages; a flash ADC converting the decompressed analog input signal into a first digital signal with reference to the decompressed first and second reference voltages; and a successive approximation ADC converting the analog input signal into a second digital signal according to a successive approximation operation with reference to the first digital signal and the first and second reference voltages.

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Номер записи: 32
23-01-2014 дата публикации

METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTOR (ADC) ARCHITECTURE

Номер: US20140022105A1
Автор: Chan Kok Lim, Chen Xuefeng, Fogleman Eric, Ye Sheng
Принадлежит: MaxLinear, Inc.

A system for processing signals may be configured to detect occurrence of particular errors, comprising meta-stability events, during digital conversion to analog signals, and to handle any detected meta-stability event, such as by adjusting at least a portion of a corresponding digital output based on detection of the meta-stability event. The adjusting of the digital output may comprise setting at least the portion of the digital output, such as to one of a plurality of predefined digital values or patterns. The system may comprise a code generator for generating and/or outputting the predefined digital values or patterns. The system may comprise a selector for adaptively selecting, for portions of the digital output, between output of normal processing path and between predefined values or patterns. 1. A method , comprising:detecting in a signal processing component meta-stability events; andwhen a meta-stability event is detected, handling the meta-stability event, wherein the handling comprises adjusting at least a portion of an output of the signal processing component based on detection of the meta-stability event.2. The method of claim 1 , comprising setting at least the portion of the output of the signal processing component claim 1 , when adjusting it based on detection of the meta-stability event claim 1 , to a predefined value.3. The method of claim 2 , comprising selecting the predefined value based on based on processing outcome in the signal processing component prior to or when the meta-stability event is detected.4. The method of claim 1 , wherein at least the portion of the output comprises a sequence of bits.5. The method of claim 4 , wherein sequence of bits correspond to remaining bits in a N-bit output claim 4 , starting with bit corresponding to occurrence of the meta-stability event.6. The method of claim 5 , wherein the value of N is determined claim 5 , when the signal processing component comprises an analog-to-digital convertor (ADC) ...

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Номер записи: 33
06-02-2014 дата публикации

Successive-Approximation-Register Analog-to-Digital Converter and Method Thereof

Номер: US20140035767A1
Автор: Lin Chia-Liang
Принадлежит: Realtek Semiconductor Corp.

A main ADC (analog-to-digital converter) for converting an analog input signal into a digital data, and an auxiliary ADC for converting the same analog input signal into an auxiliary digital data, wherein: the main ADC is a successive-approximation-register (SAR) ADC of a first resolution with a first conversion speed; the auxiliary ADC is of a second resolution with a second conversion speed; the second resolution is lower than the first resolution but the second conversion speed is higher than the first conversion speed; and the main ADC generates the digital data by undergoing a process of successive approximation comprising a plurality of steps including a fast-track step that is based on a value of the auxiliary digital data. 1. An analog-to-digital conversion apparatus , comprising:a first ADC (analog-to-digital converter) having a first resolution and a first conversion speed, for converting an analog input signal into a first digital signal, based in part on a value of a second digital signal; anda second ADC of a second resolution and a second conversion speed, for converting the analog input signal into the second digital signal;wherein the second resolution is lower than the first resolution and the second conversion speed is higher than the first conversion speed.2. The apparatus of claim 1 , wherein the first ADC comprises:a bootstrapped controller, for updating a digital code according to a decision signal and the second digital signal and generating the first digital signal based on a final value of the digital code at an end of the first process.3. The apparatus of claim 2 , wherein the first ADC comprises:a S/H (sample-and-hold) circuit configured to sample the analog input signal into a first voltage;a DAC (digital-to-analog converter) for converting a digital code into a second voltage;a summing circuit configured to generate a third voltage having a magnitude equal to a difference between the first voltage and the second voltage; anda comparator ...

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Номер записи: 34
20-02-2014 дата публикации

Analogue to Digital Converter

Номер: US20140049416A1
Автор: KALLIOINEN Sami Seppo Antero, Kaltiokallio Kim, Nentwig Markus, Seppinen Pauli Mikael
Принадлежит: RENESAS MOBILE CORPORATION

Measures are provided for performing direct radio-frequency to digital conversion. A radio-frequency input signal is compared with a plurality of reference voltages to generate a plurality of comparison signals, each comparison signal corresponding to one of the plurality of reference voltages. One or more of the plurality of generated comparison signals are first filtered to generate a first filtered signal. One or more of the plurality of generated comparison signals are second filtered to generate a second filtered signal. A digital output signal is generated at least on the basis of the first filtered signal and the second filtered signal. 1. A method of performing direct radio-frequency to digital data component conversion , the method comprising:comparing a radio-frequency input signal with a plurality of reference voltages to generate a plurality of comparison signals, each comparison signal corresponding to one of the plurality of reference voltages;first filtering one or more of the plurality of generated comparison signals to generate a first filtered signal;second filtering one or more of the plurality of generated comparison signals to generate a second filtered signal; andgenerating a digital output signal at least on the basis of the first filtered signal and the second filtered signal, wherein the first filtering and the second filtering act to isolate a data component of the radio-frequency input signal.2. A method according to claim 1 , wherein the first filtering is performed on a first subset of the plurality of generated comparison signals and the second filtering is performed on a second claim 1 , different claim 1 , subset of the plurality of generated comparison signals.3. A method according to claim 1 , wherein each comparison signal in the plurality of generated comparison signals corresponds to a different one of the plurality of reference voltages.4. A method according to claim 1 , comprising sampling the plurality of comparison signals at ...

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Номер записи: 35
06-03-2014 дата публикации

AD CONVERSION CIRCUIT AND SOLID-STATE IMAGE PICKUP DEVICE

Номер: US20140061437A1
Автор: YAMAZAKI Susumu
Принадлежит: OLYMPUS CORPORATION

An AD conversion circuit includes: a comparison unit that receives an analog signal and a reference signal, compares voltages of the signals, and outputs a first comparison signal; a signal generation unit that outputs a second comparison signal for switching a logic state, and outputs a third comparison signal that is a result of a logic operation on the first comparison signal and the second comparison signal; a control unit that outputs an enable signal; a clock generation unit that outputs first to nclock signals having different phases; a latch unit that includes first to nlatch units, each of the first to nlatch units including an input terminal, a first control terminal, a second control terminal, and an output terminal, and latches a logic state of the one of the first to nclock signals; and a count unit that performs a count operation. 1. An analog-to-digital (AD) conversion circuit comprising:a comparison unit configured to receive an analog signal and a reference signal that increases or decreases with passage of time, the comparison unit being configured to compare voltages of the analog signal and the reference signal, the comparison unit being configured to output a first comparison signal at a first timing at which the voltages of the analog signal and the reference signal have a predetermined relationship;a signal generation unit configured to output a second comparison signal for switching a logic state at a second timing at which a predetermined time has elapsed from the first timing, the signal generation unit being configured to output a third comparison signal that is a result of a logic operation on the first comparison signal and the second comparison signal;a control unit configured to output an enable signal at least between a timing relating to a comparison start of the comparison unit and the second timing;{'sup': 'th', 'a clock generation unit configured to output first to n(n is a natural number equal to or greater than 2) clock signals ...

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Номер записи: 36
20-03-2014 дата публикации

Ad conversion circuit and solid-state imaging apparatus

Номер: US20140077065A1
Автор: Yoshio Hagihara
Принадлежит: Olympus Corp

An AD conversion circuit and a solid-state imaging apparatus reduce the occurrence of errors in encoding a lower phase signal while securing a degree of freedom of selection of a count clock. A detection circuit performs an operation of detecting logic states of m (m is a natural number of 2 or more) lower phase signals in a signal group that a plurality of lower phase signals latched by the latch unit is arranged, while selecting the m lower phase signals in a predetermined order so that the order thereof becomes the same as the order of the signal group and outputs a state detection signal at the time of detecting that the logic states of the m lower phase signals are in a predetermined logic state in the detection operation. The predetermined order is defined depending on a predetermined signal and an encoding method.

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Номер записи: 37
20-03-2014 дата публикации

Ad converting circuit, photoelectric converting apparatus, image pickup system, and driving method for ad converting circuit

Номер: US20140078362A1
Автор: Daisuke Yoshida
Принадлежит: Canon Inc

An apparatus for acquiring an i-bit digital code by a first stage AD conversion and a j-bit digital code by a second stage AD conversion includes a comparing unit which compares a reference signal and an analog signal in the first stage AD conversion; and an amplifying unit for outputting an amplified residual signal acquired by amplifying a difference between the analog signal and an analog signal corresponding to the i-bit digital code. The comparing unit compares the amplified residual signal and the reference signal in the second stage AD conversion.

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Номер записи: 38
27-03-2014 дата публикации

Successive approximation register analog-to-digital converter

Номер: US20140085122A1
Автор: Jong-Kee Kwon, Tae Moon Roh, Young-Deuk Jeon
Принадлежит: Electronics and Telecommunications Research Institute ETRI

A successive approximation register analog-to-digital converter is provided which includes first and second capacitor arrays configured to generate first and second level voltages, respectively; a comparator configured to compare the first and second level voltages to output a comparison signal; SAR logic configured to generate a digital signal in response to the comparison signal; and a variable common mode selector configured to compare a first analog input voltage and a common mode voltage and to supply one of the first analog input voltage and the common mode voltage to top plates of the first and second capacitor arrays according to a comparison result.

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Номер записи: 39
10-04-2014 дата публикации

AD CONVERSION CIRCUIT AND SOLID-STATE IMAGE PICKUP DEVICE

Номер: US20140098271A1
Автор: Hagihara Yoshio
Принадлежит: OLYMPUS CORPORATION

An AD conversion circuit may include: a reference signal generation unit generating a reference signal increasing or decreasing with passage of time; a comparison unit including a first comparison circuit and a second comparison circuit comparing an analog signal to be subjected to an AD conversion with the reference signal; a clock generation unit including a delay circuit in which a plurality of delay units are connected to one another, and outputting a first lower phase signal and a second lower phase signal based on clock signals output from each of the plurality of delay units; a latch unit including a first latch circuit latching a logical state of the first lower phase signal and a second latch circuit latching a logical state of the second lower phase signal; and a counting unit performing counting based on the second lower phase signal output from the clock generation unit. 1. An AD conversion circuit comprising:a reference signal generation unit configured to generate a reference signal increasing or decreasing with passage of time;a comparison unit that includes a first comparison circuit and a second comparison circuit, each of which compares an analog signal to be subjected to an AD conversion with the reference signal;a clock generation unit that includes a delay circuit in which a plurality of delay units are connected to one another, the clock generation unit outputting a first lower phase signal and a second lower phase signal based on clock signals that are output from each of the plurality of delay units;a latch unit that includes a first latch circuit and a second latch circuit, the first latch circuit being configured to latch a logical state of the first lower phase signal that is output from the clock generation unit, the second latch circuit being configured to latch a logical state of the second lower phase signal that is output from the clock generation unit; anda counting unit configured to perform counting based on the second lower phase ...

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Номер записи: 40
01-01-2015 дата публикации

Imaging Device Comprising a Circuit for Analog-Digital Conversion by Means of the Injection of a Quantity of Charges that Varies as a Function of the Number of Previous Injections

Номер: US20150001379A1
Автор: Moro Jean-Luc
Принадлежит:

In the field of imaging devices comprising a detector generating electric charges in response to incident photon radiation, and an analog-to-digital conversion circuit forming means for reading the quantity of electric charges generated, an analog-to-digital conversion circuit comprises: a comparator which can switch depending on the comparison between a potential on an integration node and a predetermined threshold potential, a counter incrementing with each switch of the comparator, a counter-charge injection circuit injecting a quantity Qc of counter-charges on the integration node with each switch of the comparator, and control means which determine the quantity Qc of counter-charges injected. The analog-to-digital conversion circuit is characterized in that the control means determine the quantity Qc of counter-charges injected as a function of a value of the counter. 1. An analog-to-digital conversion circuit for an imaging device comprising a detector generating electric charges in response to incident photon radiation , the electric charges leading to a variation of an integration potential on an integration node , the analog-to-digital conversion circuit comprising:a comparator which can switch depending on the comparison between the integration potential and a predetermined threshold potential,a counter connected to an output of the comparator and incrementing with each switch of the comparator,a counter-charge injection circuit injecting a quantity Qc of counter-charges at the integration node with each switch of the comparator, andmeans for controlling the counter-charge injection circuit which determine the quantity Qc of counter-charges injected,wherein the control means determine the quantity Qc of counter-charges injected as a function of a value of the counter.2. The circuit as claimed in claim 1 , wherein the control means are configured to make the quantity Qc vary each time the value of the counter reaches one or more predetermined threshold ...

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Номер записи: 41
07-01-2021 дата публикации

Digital Interface Circuit for Analog-to-Digital Converter

Номер: US20210004339A1
Автор: ATAL Sandip, Nandlinger Rolf, TRIVEDI Nirav Prashantkumar
Принадлежит:

A digital interface circuit includes a queue block configured to be coupled between an analog-to-digital converter (ADC) and a Direct Memory Access (DMA) controller of a processor, where the queue block comprises a command buffer and is configured to: receive a first command from the DMA controller; store the first command in the command buffer; modify the first command in accordance with first control bits of the first command to generate a modified first command; and send the modified first command to the ADC. 1. An analog-to-digital conversion system comprising:an analog-to-digital converter (ADC);a multiplexer, wherein the multiplexer has a plurality of input channels that are configured to be coupled to a plurality of analog input signals, wherein an output terminal of the multiplexer is coupled to an input terminal of the ADC; and receive a sequence of commands from the processor, wherein each command of the sequence of commands comprises a channel number that indicates an input channel of the multiplexer, and comprises control bits for the input channel indicated by the channel number;', 'store the sequence of commands in a command buffer of the digital interface circuit; and', 'modify each command of the sequence of commands in accordance with the control bits., 'a digital interface circuit configured to be coupled between the ADC and a processor, wherein the digital interface circuit is configured to2. The analog-to-digital conversion system of claim 1 , wherein the digital interface circuit is further configured to send a modified sequence of commands to the ADC for a first time claim 1 , wherein the ADC converts the analogy input signals at input channels indicated by the channel numbers contained in the modified sequence of commands into digital values.3. The analog-to-digital conversion system of claim 2 , wherein the digital interface circuit is further configured to claim 2 , after sending the modified sequence of commands to the ADC for a first time ...

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Номер записи: 42
05-01-2017 дата публикации

INTEGRATOR, AD CONVERTER, AND RADIATION DETECTION DEVICE

Номер: US20170005667A1
Автор: Funaki Hideyuki, Furuta Masanori, Itakura Tetsuro, KAWATA Go, KIMURA Shunsuke, SHIRAHAMA Hirokatsu
Принадлежит: KABUSHIKI KAISHA TOSHIBA

An integrator according to an embodiment includes first and second nodes, first to fifth switches, first and second main integration capacitors, and a first subsidiary integration capacitor. The first (second, third, fourth, fifth) switch has one end connected to a first (third, first, fourth, first) node and the other end connected to a third (second, fourth, second, fifth) node. The first main integration capacitor has one end connected to the third node and the other end connected to a standard voltage line. The second main integration capacitor has one end connected to the fourth node and the other end connected to the standard voltage line. The first subsidiary integration capacitor that has one end connected to the fifth node and the other end connected to the standard voltage line. 1. An integrator comprising:a first node that receives a signal current;a second node that outputs a voltage;a first switch that has one end connected to the first node and the other end connected to a third node;a second switch that has one end connected to the third node and the other end connected to the second node;a first main integration capacitor that has one end connected to the third node and the other end connected to a standard voltage line;a third switch that has one end connected to the first node and the other end connected to a fourth node;a fourth switch that has one end connected to the fourth node and the other end connected to the second node;a second main integration capacitor that has one end connected to the fourth node and the other end connected to the standard voltage line;a fifth switch that has one end connected to the first node and the other end connected to a fifth node; anda first subsidiary integration capacitor that has one end connected to the fifth node and the other end connected to the standard voltage line.2. The integrator according to claim 1 , further comprising:a sixth switch that has one end connected to the first node and the other end ...

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Номер записи: 43
07-01-2016 дата публикации

Adjustable and buffered reference for adc resolution and accuracy enhancements

Номер: US20160006449A1
Автор: Peter Spevak
Принадлежит: TEXAS INSTRUMENTS DEUTSCHLAND GMBH

An analog to digital converter (ADC) core; a reference voltage generator coupled to an input of the ADC core; a bandgap reference coupled to the reference voltage generator; and a window comparator configured to control a selected reference voltage range generated by the reference voltage generator and received by the ADC core.

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Номер записи: 44
07-01-2016 дата публикации

METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTOR (ADC) ARCHITECTURE

Номер: US20160006450A1
Автор: Chan Kok Lim, Chen Xuefeng, Fogleman Eric, Ye Sheng
Принадлежит:

Methods and systems are provided for controlling signal processing outputs. In signal processing circuitry, searching through a plurality of quantization levels for a quantization level that matches an analog input, and when the search fails within a particular amount of time, adjusting at least a portion of an output of the signal processing circuitry. The adjusting comprises setting the at least portion of the output to a predefined value. Setting the output, or portions thereof, may comprise selecting between output of a normal processing path and output of a code generation path configured for handling search failures. Timing information may be generated for use in controlling generating of the output of the signal processing circuitry. The timing information may be used in measuring per-cycle operation time during the search through the plurality of quantization levels. 120-. (canceled)21. A method , comprising: searching through a plurality of quantization levels for a quantization level that matches an analog input; and', 'when said search for said matching quantization level fails within a particular amount of time, adjusting at least a portion of an output of said signal processing circuitry., 'in signal processing circuitry22. The method of claim 21 , wherein adjusting at least a portion of an output of said signal processing circuitry comprises setting at least said portion of said output of said signal processing circuitry to a predefined value.23. The method of claim 22 , comprising selecting said predefined value based on an outcome of processing in said signal processing circuitry prior to or when said search for said matching quantization level fails.24. The method of claim 21 , comprising selecting claim 21 , for adjusting at least a portion of an output of said signal processing circuitry claim 21 , between an output of a normal processing path and an output of a code generation path configured for handling search failures.25. The method of claim ...

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Номер записи: 45
04-01-2018 дата публикации

PHOTOELECTRIC CONVERSION APPARATUS AND IMAGE CAPTURING SYSTEM

Номер: US20180006659A1
Автор: Hashimoto Seiji, Ise Makoto, Yoshida Daisuke
Принадлежит:

In a first sensitivity level, an AD converter performs AD conversion selectively using, in accordance with the level of the analog signal, any one of a first reference signal and a second reference signal that have mutually different slopes, and in a second sensitivity level that is different from the first sensitivity level, the AD converter performs AD conversion only using a third reference signal. 1. A photoelectric conversion apparatus comprising:a plurality of pixels;a plurality of analog signal output units each configured to output an analog signal in accordance with a signal which is produced by and is output from a corresponding one of the plurality of pixels; anda plurality of analog-to-digital (AD) converters provided to correspond to the plurality of analog signal output units and configured to perform AD conversion by comparing a ramp signal with the analog signal output from the analog signal output units, whereinthe photoelectric conversion apparatus has a first operation mode where the imaging sensitivity level is a first sensitivity level and a second mode where the imaging sensitivity level is a second sensitivity level different from the first sensitivity level,in the first operation mode, each of the plurality of AD converters uses a third ramp signal having a third slope to perform the AD conversion for the analog signal having a third signal level lower than a second threshold value, and uses a fourth ramp signal having a fourth slope different from the third slope to perform the AD conversion for the analog signal having a fourth signal level higher than the second threshold valuein the second operation mode, each of the plurality of AD converters uses a third ramp signal having a third slope to perform the AD conversion for the analog signal having a third signal level lower than a second threshold value, and uses a fourth ramp signal having a fourth slope different from the third slope to perform the AD conversion for the analog signal ...

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Номер записи: 46
02-01-2020 дата публикации

SPECTRALLY EFFICIENT DIGITAL LOGIC (SEDL) ANALOG TO DIGITAL CONVERTER (ADC)

Номер: US20200007141A1
Автор: Murphy Robert J.
Принадлежит:

Spectrally-efficient digital logic (SEDL) techniques implement spectrally-efficient pulses (e.g., Gaussian-shaped pulses) in lieu of conventional square waveforms to improve electromagnetic, radio frequency, and other unwanted emissions. The SEDL techniques can be used for analog-to-digital converters (ADC) and digital-to-analog converters (DAC). An ADC circuit comprises a plurality of comparators configured to receive an analog input signal and compare the analog input signal to a predetermined reference signal, an encoder, and a spectrally-efficient circuit. A DAC circuit includes an integrator circuit, a clocked comparator circuit, a pulse generator, and a combiner circuit. The clocked comparator circuit receives the logic state of each SEDL pulse. The pulse generator receives the logic state and generates a scaled SEDL pulse for each input SEDL pulse. A combiner circuit combines the outputs from the pulse generator and determines analog value corresponding to the input values. 1. An analog-to-digital converter (ADC) comprising:a plurality of comparators, wherein each comparator is configured to receive an analog input signal and to compare the analog input signal to a predetermined reference signal to identify a value of the input signal, and in response to the analog input signal being greater than the reference signal the comparator provides an output having a first value, and in response to the analog input signal being less than the reference signal the comparator provides an output having a second different value;an encoder configured to receive the output signal from each comparator and in response thereto to provide at least one of a plurality of bits at an output as a digital value depending upon one of the plurality of values input to the encoder; anda spectrally-efficient-based sequential circuit configured to assess a state of the digital value and to provide an output pulse having a sequentially-efficient shaped pulse.2. The ADC of claim 1 , wherein ...

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Номер записи: 47
02-01-2020 дата публикации

SPECTRALLY EFFICIENT DIGITAL LOGIC (SEDL) DIGITAL TO ANALOG CONVERTER (DAC)

Номер: US20200007142A1
Автор: Murphy Robert J.
Принадлежит:

Spectrally-efficient digital logic (SEDL) techniques implement spectrally-efficient pulses (e.g., Gaussian-shaped pulses) in lieu of conventional square waveforms to improve electromagnetic, radio frequency, and other unwanted emissions. The SEDL techniques can be used for analog-to-digital converters (ADC) and digital-to-analog converters (DAC). An ADC circuit comprises a plurality of comparators configured to receive an analog input signal and compare the analog input signal to a predetermined reference signal, an encoder, and a spectrally-efficient circuit. A DAC circuit includes an integrator circuit, a clocked comparator circuit, a pulse generator, and a combiner circuit. The clocked comparator circuit receives the logic state of each SEDL pulse. The pulse generator receives the logic state and generates a scaled SEDL pulse for each input SEDL pulse. A combiner circuit combines the outputs from the pulse generator and determines analog value corresponding to the input values. 1. A digital-to-analog converter (DAC) circuit comprising:an integrator circuit having an input configured to receive an input signal provided from a plurality of spectrally-efficient shaped digital logic (SEDL) pulses, with each SEDL pulse representing one or more bits of the input signal and wherein the integrator circuit is configured to determine a logic state represented by each of the plurality of SEDL pulses;a clocked comparator circuit coupled to the integrator circuit and configured to receive the logic state of each SEDL pulse and in response thereto, to provide a clocked comparator circuit signal at an output thereof;a pulse generator having a first input coupled to an output of the integrator circuit and a second input coupled to an output of the clocked comparator circuit, wherein, in response to receiving a logic state and a clocked comparator circuit signal, the pulse generator generates a scaled SEDL pulse for each input signal SEDL pulse;a combiner circuit coupled to the ...

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Номер записи: 48
27-01-2022 дата публикации

TIME DOMAIN RATIOMETRIC READOUT INTERFACES FOR ANALOG MIXED-SIGNAL IN MEMORY COMPUTE CROSSBAR NETWORKS

Номер: US20220027130A1
Автор: KASHMIRI Sayyed Mahdi, MESSNER Jonas, PAPAGEORGIOU Efthymios, WOJCIECHOWSKI Kenneth
Принадлежит:

A circuit configured to compute matrix multiply-and-add calculations that includes a digital-to-time converter configured to receive a digital input and output a signal proportional to the digital input and modulated in time-domain associated with a reference time, a memory including a crossbar network, wherein the memory is configured to receive the time modulated signal from the digital-to-time converter and output a weighted signal scaled in response to network weights of the crossbar network and the time modulated input signal, and an output interface in communication with the crossbar network and configured to receive its weighted output signal and output a digital value proportional to at least the reference time using a time-to-digital converter. 1. A circuit configured to compute matrix multiply-and-add calculations , comprising:a digital-to-time converter configured to receive a digital input and output a signal proportional to the digital input and modulated in time-domain associated with a reference time;a memory including a crossbar network, wherein the memory is configured to receive the time modulated signal from the digital-to-time converter and output a weighted signal scaled in response to network weights of the crossbar network and the time modulated signal; andan output interface in communication with the crossbar network and configured to receive its weighted output signal and output a digital value proportional to at least the reference time using a time-to-digital converter.2. The circuit of claim 1 , wherein the circuit includes a reference clock associated with the digital-to-time converter and the time-to-digital converter.3. The circuit of claim 1 , wherein the network weights include one or more electrical elements configured to scale the signal proportional to the digital input and modulated in time domain.4. The circuit of claim 1 , wherein the circuit includes an integrator for accumulation of the weighted signal scaled in response to ...

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Номер записи: 49
14-01-2021 дата публикации

Optical position-measuring device

Номер: US20210010807A1
Автор: Christoph Lingk, Daniel Frese, Wolfgang Holzapfel
Принадлежит: Dr Johannes Heidenhain GmbH

In an optical position-measuring device for acquiring the rotational angle between two objects that are rotationally moveable relative to each other, a grating measuring standard rotating about an axis of rotation is arranged as a reflection grating. Position information both about an azimuthal rotary movement about the axis of rotation and about a radial displacement of the grating measuring standard is able to be obtained. At least one detection unit is used for scanning the rotating grating measuring standard in order to determine the azimuthal rotational angle as well as a radial displacement of the grating measuring standard. The neutral pivot points of the scanning of the grating measuring standard for the determination of the rotational angle and the displacement are situated in the same plane, with this plane being situated in parallel with the grating measuring standard. The neutral pivot point denotes the particular location about which the grating measuring standard or the detection unit is able to be tilted without a position offset.

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Номер записи: 50
12-01-2017 дата публикации

ANALOG-TO-DIGITAL CONVERTERS FOR SUCCESSIVE APPROXIMATION INCORPORATING DELTA SIGMA ANALOG-TO-DIGITAL CONVERTERS AND HYBRID DIGITAL-TO-ANALOG CONVERTERS WITH CHARGE-SHARING AND CHARGE REDISTRIBUTION

Номер: US20170012633A1
Автор: Bosi Alessandro, Ghittori Nicola, Nani Claudio, Venca Alessandro
Принадлежит:

An A/D converter including a sample and hold circuit, first and second A/D converters and a combination circuit. The sample and hold circuit samples an analog input signal to generate bits. The first A/D converter generate a first digital signal based on the analog input signal and includes charge-sharing and charge-redistribution D/A converters that convert respectively a most-significant-bit and a first least significant bit. The first digital signal is generated based on outputs of the charge-sharing and charge redistribution D/A converters. The second A/D converter generates a second digital signal based on an output of the first A/D converter and includes a delta sigma D/A converter, which converts a second least significant bit. The second digital signal is generated based on an output of the delta sigma D/A converter. The second A/D converter is a fine conversion A/D converter relative to the first A/D converter. 1. An analog-to-digital converter comprising:a sample and hold circuit configured to sample an analog input signal to generate a plurality of bits; a charge-sharing digital-to-analog converter configured to convert a first most-significant-bit of the plurality of bits, and', 'a charge redistribution digital-to-analog converter configured to convert a first least significant bit of the plurality of bits,', 'wherein the first digital signal is generated based on an output of the charge-sharing digital-to-analog converter and an output of the charge redistribution digital-to-analog converter;, 'a first analog-to-digital converter configured to generate a first digital signal based on the analog input signal, comprising'}a second analog-to-digital converter configured to generate a second digital signal based on an output of the first analog-to-digital converter, wherein the second analog-to-digital converter comprises a delta sigma digital-to-analog converter, wherein the delta sigma digital-to-analog converter is configured to convert a second least ...

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Номер записи: 51
12-01-2017 дата публикации

BACKGROUND ESTIMATION OF COMPARATOR OFFSET OF AN ANALOG-TO-DIGITAL CONVERTER

Номер: US20170012634A1
Автор: ALI Ahmed Mohamed Abdelatty, BHORASKAR Paritosh, DINC Huseyin, MORGAN Andrew Stacy
Принадлежит: ANALOG DEVICES, INC.

A pipeline analog-to-digital converter (ADC) converts an analog input signal over several stages, where a stage generates a residue for the subsequent stage to digitize. The residue is generated by coarsely quantizing the analog input signal to generate a digital code, which is used to reconstruct the analog input signal, and the residue is the difference between the analog input signal and the reconstructed version of the analog input signal. The coarse quantization can have errors which are attributed to comparator offsets and bandwidth mismatch. To estimate the comparator offsets while being insensitive to bandwidth mismatch, peak and trough detectors are used to track maximum and minimum values of the residue or the output of the ADC over time, and an expected value estimating the comparator offset can be computed based on the maximum and minimum values. The expected value advantageously “averages” out the bandwidth mismatch contribution to the offset. 1. A method for estimating comparator offset of a sub-analog-to-digital converter (sub-ADC) of an analog to digital converter (ADC) , the method comprising:determining data samples of (1) a residue signal generated based on a difference between an input signal to the sub-ADC and a reconstructed version of the input signal or (2) an input signal to the sub-ADC, wherein data samples corresponds to two neighboring codes which are associated with a comparison made by a comparator of the sub-ADC;tracking, over time, state information of the neighboring codes based on the data samples; anddetermining an expected value, which estimates an offset of the comparator, based on the state information.2. The method of claim 1 , further comprising:calibrating or correcting for the offset based on the expected value.3. The method of claim 1 , wherein the sub-ADC is a flash ADC or quantizer of any stage of a pipeline analog-to-digital converter.4. The method of claim 1 , wherein:the state information comprises (1) maximum values ...

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Номер записи: 52
12-01-2017 дата публикации

METHOD AND A DEVICE FOR ANALOG-TO-DIGITAL CONVERSION OF SIGNALS, CORRESPONDING APPARATUS

Номер: US20170012635A1
Автор: Faravelli Roberto, Poli Salvatore, Quartiroli Matteo, Tripoli Giovanni Carlo
Принадлежит:

One or more first signals and one or more second signals, wherein the second signal(s) are slowly varying or low frequency signals in comparison with the first signals and are converted from analog to digital by sampling the first signals and the second signals to produce samples thereof for analog-to-digital conversion, subjecting the samples of the first signals to conversion to digital at a certain conversion rate, subjecting the samples of the second signal to conversion to digital by segments so that these segments are subjected to conversion to digital along with the samples of the first signals at the respective conversion rate, and reconstructing digital converted samples of the second signal from the segments subjected to conversion to digital. 1. A method , comprising:sampling a first signal at a sampling rate to generate analog samples of the first signal;sampling a second signal at the sampling rate to generate analog samples of the second signal, the second signal being a low frequency signal relative to the first signal;performing conversion of the analog samples of the first signal to digital values at a conversion rate; andperforming time-segmented conversion on the analog samples of the second signal at the conversion rate to sequentially generate bits of a digital value representing the second signal.2. The method of claim 1 , wherein performing time-segmented conversion on the analog samples of the second signal at the conversion rate to sequentially generate bits of a digital value representing the second signal comprises generating N-bit segments of the digital value representing the second signal each period defined by the conversion rate along with converting the analog samples of the first signal to digital values.3. The method of claim 2 , wherein generating the N-bit segments of the second signal comprises generating the N-bit segments from the most significant bit of the digital value representing the second signal to the least significant ...

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Номер записи: 53
12-01-2017 дата публикации

SUCCESSIVE APPROXIMATION SIGMA DELTA ANALOG-TO-DIGITAL CONVERTERS

Номер: US20170012637A1
Автор: Bosi Alessandro, Ghittori Nicola, Nani Claudio, Venca Alessandro
Принадлежит:

An A/D converter including first and second A/D converters and a recombination module. The first A/D converter receives an analog input signal, converts the analog input signal to a first digital signal, and includes a successive approximation module, which performs a successive approximation to generate the first digital signal. The second A/D converter converts an analog output of the first A/D converter to a second digital signal. The analog output of the first A/D converter is generated based on the analog input signal. The second A/D converter is a fine conversion A/D converter relative to the first A/D converter. The second A/D converter performs the delta-sigma conversion process and includes a decimation filter that suppresses noise which reduces amplification and power consumption requirements of the first A/D converter and performs a delta-sigma decimation process to generate the second digital signal based on the analog output of the first A/D converter. 1. An analog-to-digital converter comprising:a first analog-to-digital converter configured to receive an analog input signal and convert the analog input signal to a first digital signal, the first analog-to-digital converter comprising a successive approximation module, wherein the successive approximation module is configured to perform a successive approximation to generate the first digital signal; suppress noise which reduces amplification and power consumption requirements of the first analog-to-digital converter, and', 'perform a delta-sigma decimation process to generate the second digital signal based on the analog output of the first analog-to-digital converter; and, 'a second analog-to-digital converter configured to convert an analog output of the first-analog-to-digital converter to a second digital signal, wherein the analog output of the first analog-to-digital converter is generated based on the analog input signal, wherein the second analog-to-digital converter is a fine conversion ...

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Номер записи: 54
15-01-2015 дата публикации

SEMICONDUCTOR INTEGRATED CIRCUIT

Номер: US20150015229A1
Автор: Teh Chen kong
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A feedback loop, which feedbacks information of an output voltage or a load current, is provided. The feedback loop has a first mode, which digitalizes and feedbacks the information of the current voltage or the load current, and a second mode, which feedbacks the information as an analog value. 1. A semiconductor integrated circuit which feedbacks information of at least one of an output voltage and a load current and controls the output voltage comprising:a first mode which digitalizes and feedbacks the information of at least one of the output voltage and the load current;and a second mode which feedbacks the information of at least one of the output voltage and the load current as an analog value.2. The semiconductor integrated circuit according to claim 1 , wherein a feedback loop feedbacking the information of the output voltage is provided in the semiconductor integrated circuit claim 1 , and the feedback loop includes an AD converter which digitalizes the information of the output voltage claim 1 , anddigitalization by the AD converter is performed in the first mode, and an operation of the AD converter is stopped in the second mode.3. The semiconductor integrated circuit according to claim 2 , wherein the AD converter is a successive approximation register AD converter.4. The semiconductor integrated circuit according to claim 2 , wherein the AD converter is a parallel type AD converter.5. The semiconductor integrated circuit according to claim 4 , wherein the AD converter includes a plurality of comparison circuits which compares a predetermined reference voltage and a feedback voltage of the output voltage and is connected in parallel claim 4 , and at least one of the comparison circuits includes:first and second MOS transistors which compare the reference voltage and the feedback voltage and constitute a differential pair; anda third MOS transistor which supplies a current to the first and second transistors,wherein conduction of the third MOS transistor ...

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Номер записи: 55
14-01-2016 дата публикации

CURRENT COUNTING ANALOG-TO-DIGITAL CONVERTER FOR LOAD CURRENT SENSING INCLUDING DYNAMICALLY BIASED COMPARATOR

Номер: US20160013804A1
Автор: Peluso Vincenzo F
Принадлежит:

In one embodiment, a circuit comprises first and second capacitors configured to receive a sense current in first and second modes, respectively. A comparator is coupled to the first capacitor to compare a voltage of the first capacitor to a reference voltage and generate a count signal in response to the voltage of the first capacitor reaching the reference voltage in the first mode. The comparator is coupled to the second capacitor to compare a voltage of the second capacitor to the reference voltage and generate the count signal in response to the voltage of the second capacitor reaching the reference voltage in the second mode. A reset circuit discharges the first capacitor in the second mode and the second capacitor in the first mode in response to the count signal. A counter increments a count of a number of occurrences of the count signal. 1. A circuit comprising:a first capacitor configured to receive a sense current in a first mode;a second capacitor configured to receive a sense current in a second mode;a comparator coupled to the first capacitor to compare a voltage of the first capacitor to a reference voltage and generate a count signal in response to the voltage of the first capacitor reaching the reference voltage in the first mode and coupled to the second capacitor to compare a voltage of the second capacitor to the reference voltage and generate the count signal in response to the voltage of the second capacitor reaching the reference voltage in the second mode;a reset circuit to discharge the first capacitor in the second mode and to discharge the second capacitor in the first mode in response to the count signal; anda counter incrementing a count of a number of occurrences of the count signal.2. The circuit of further comprising a switch circuit to couple the first capacitor to the comparator in the first mode and couple the second capacitor to the comparator in the second mode.3. The circuit of wherein the reset circuit comprises a first switch ...

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Номер записи: 56
11-01-2018 дата публикации

ANALOG-TO-DIGITAL CONVERSION DEVICE

Номер: US20180013443A1
Автор: Chao Chieh-Yuan, KANG Wen-Juh, Wang Ting-Hao
Принадлежит:

An analog-to-digital conversion device is provided that includes a front SAR ADC and a plurality of rear SAR ADCs. The front SAR ADC is configured to convert an analog input signal into a group of higher bits of a digital output signal in response to different time periods. Each of the rear SAR ADCs is electrically coupled to the front SAR ADC and is configured to receive the analog input signal and the corresponding group of higher bits in response to the different time periods. The rear SAR ADCs convert the analog input signal into a group of lower bits of the digital output signal corresponding to the time period of the group of higher bits. 1. An analog-to-digital conversion device comprising:a clock circuit configured to generate p multi-phase clocks;a front successive-approximation analog-to-digital converter (SAR ADC) electrically coupled to the clock circuit, and configured to convert an analog input signal into p groups of higher bits of a digital output signal in response to different time periods according to the p multi-phase clocks; anda plurality of rear SAR ADCs each electrically coupled to the clock circuit and the front SAR ADC, and configured to receive the analog input signal and one of p groups of higher bits corresponding to each other in response to the different time periods according to the p multi-phase clocks, wherein the number of the plurality of rear SAR ADCs equals the number of phases of the p multi-phase clocks, so that the plurality of rear SAR ADCs convert the analog input signal into p groups of lower bits of the digital output signal corresponding to the time period of the p groups of higher bits; anda combining circuit electrically coupled to the clock circuit, the front SAR ADC and the rear SAR ADCs, and configured to receive the p multi-phase clocks and combine the p groups of higher bits and the p groups of lower bits that correspond to the same time period according to the p multi-phase clocks, so as to generate the digital ...

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Номер записи: 57
10-01-2019 дата публикации

Analog-digital converter

Номер: US20190013820A1
Автор: Kenichi Ohhata
Принадлежит: Kagoshima University NUC

AD conversion is performed by using a combination of a parallel AD converter that includes a plurality of comparators to compare an input potential of an analog input signal sampled by a track and hold circuit and reference potentials different from one another and determines a value of a predetermined number of bits on the higher-order side of a digital signal and a single-slope AD converter that reduces the input potential of the analog input signal sampled by the track and hold circuit at a constant speed, converts a time taken until the reduced input potential becomes equal to a reference potential corresponding to the value determined by the parallel AD converter to a digital value, and determines a remaining value on the lower-order side of the digital signal, and thereby the number of bits of the single-slope AD converter can be reduced and high-speed AD conversion is enabled with a small area and low power consumption.

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Номер записи: 58
09-01-2020 дата публикации

ANALOG-TO-DIGITAL CONVERTER USING CHARGE PACKETS

Номер: US20200014297A1
Автор: Geraedts Paul F. J., Louwsma Simon M.
Принадлежит:

The present invention relates to a converting device for converting an analog voltage into a digital number and to an imaging system comprising the same. The invention further relates to a method for converting an analog voltage into a digital number. 1. A method for converting an analog voltage into a digital number , comprising:a) setting a voltage over a main capacitive element in dependence of the analog voltage; I) injecting or removing an amount of charge into or from the main capacitive element, respectively, to thereby change the voltage over the main capacitive element; and', 'II) comparing the voltage over the main capacitive element to a reference voltage, and, based on said comparison, either returning to sub-step I) to further change the voltage over the main capacitive element or ending the currently performed charge pumping step and proceeding with a next charge pumping step, if any; and, 'b) consecutively performing one or more charge pumping steps, each charge pumping step comprising performing at least sub-step II of the loop comprising the sub-steps ofc) calculating the digital number representing the analog voltage based on the net charge that has been injected into or removed from the main capacitive element as a result of having performed said one or more charge pumping steps.2. The method according to claim 1 , wherein each charge pumping step is associated with a respective amount of charge and/or respective reference voltage.3. The method according to claim 2 , wherein an amount of charge that is associated with one charge pumping step among two charge pumping steps that are to be performed consecutively is positive claim 2 , and wherein an amount of charge that is associated with the other charge pumping step among said two consecutive charge pumping steps is negative.4. The method according to claim 1 , wherein the reference voltage for each charge pumping step is identical claim 1 , preferably equal to zero.5. The method according to ...

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Номер записи: 59
09-01-2020 дата публикации

FRONT-END RECEIVING CIRCUIT AND METHOD FOR THE SAME

Номер: US20200014394A1
Автор: Huang Shih-Hsiung, LEI Liang-Huan, Lin Jian-Ru
Принадлежит:

A front-end receiving circuit includes a first input terminal receiving a first signal, a second input terminal receiving a second signal, a comparator, a first sampling switch, a first sampling shifting circuit and a control circuit. The first sampling switch is coupled between the first input terminal and the first comparator input terminal. The first sample shifting circuit includes a first capacitor, a first reference voltage source, and a second reference voltage source. In a sampling mode, the control circuit is configured to control the first sampling switch and the second sampling switch to be turned on, and control the first shifting switch to be turned off. In a shifting mode, the control circuit is configured to control the first sampling switch and the second sampling to be turned off, and control the first shifting switch to be turned on. 1. A front-end receiving circuit connected to a back-end circuit , comprising:a first input terminal configured to receive a first signal;a second input terminal configured to receive a second signal;a comparator having a first comparator input terminal and a second comparator input terminal respectively connected to the first input terminal and the second input terminal;a first sampling switch connected between the first input terminal and the first comparator input terminal; a first capacitor having one end connected between the first sampling switch and the first comparator input terminal;', 'a first reference voltage source connected to another end of the first capacitor through a second sampling switch; and', 'a second reference voltage source connected to the another end of the first capacitor through a first shifting switch; and, 'a first sampling shifting circuit, which includesa control circuit, configured to be electrically and respectively coupled to the first sampling switch, the second sampling switch and a control end of the first shifting switch, to control the first sampling switch, the second sampling ...

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Номер записи: 60
09-01-2020 дата публикации

Decision Feedback Equalizer

Номер: US20200014565A1
Автор: Brian S. Leibowitz, Jaeha Kim
Принадлежит: RAMBUS INC

A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE, then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.

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Номер записи: 61
09-01-2020 дата публикации

SOLID-STATE IMAGING DEVICE, AND CAMERA SYSTEM USING SAME

Номер: US20200014873A1
Автор: ABE YUTAKA, FUJINAKA Hiroshi, HIGASHI Yosuke, NISHIMURA Kazuko, Sumitani Norihiko
Принадлежит: Panasonic Intellectual Property Management Co., Ltd.

A solid-state imaging device includes a first A/D converter circuit and a second A/D converter circuit per column. The first A/D converter circuit performs a first A/D conversion that (i) refines, using a first comparator, a range including a potential of an analog signal through a binary search, and (ii) generates, based on a result of the binary search, a first digital signal being a high-order portion of the digital signal. The second A/D converter circuit performs a second A/D conversion that generates a second digital signal being a low-order portion that is a remainder of the digital signal by measuring a time required for an output of the second comparator to be inverted, the second comparator comparing a quantitative relationship between the analog signal refined and a ramp signal. 1. A solid-state imaging device , comprising:a plurality of pixel cells arranged in an X-direction and a Y-direction, the plurality of pixels cells each including a photoelectric converter that converts an optical signal to an electrical signal;a plurality of vertical signal lines arranged in the X-direction that are connected to the plurality of pixel cells and transmit the electrical signal as an analog signal; anda plurality of analog-to-digital (A/D) converters arranged in the X-direction that are respectively connected to the plurality of vertical signal lines and convert the analog signal to a digital signal, wherein a first A/D converter circuit having a first comparator; and', 'a second A/D converter circuit having a second comparator,, 'the plurality of A/D converters each includethe first A/D converter circuit performs a first A/D conversion that (i) refines, using the first comparator, a range including a potential of the analog signal through a binary search, and (ii) generates, based on a result of the binary search, a first digital signal being a high-order portion of the digital signal, andthe second A/D converter circuit performs a second A/D conversion that ...

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Номер записи: 62
17-04-2014 дата публикации

DSP RECEIVER WITH HIGH SPEED LOW BER ADC

Номер: US20140104086A1
Автор: AHMADI Mahmoud Reza, Maarefi Hassan, Momtaz Afshin, NAZEMI Ali, ZHANG BO, Zhang Heng
Принадлежит: BROADCOM CORPORATION

Methods and apparatuses are described for a DSP receiver with an analog-to-digital converter (ADC) having high speed, low BER performance with low power and area requirements. Speed is increased for multi-path ADC configurations by resolving a conventional bottleneck. ADC performance is improved by integrating calibration and error detection and correction, such as distributed offset calibration and redundant comparators. Power and area requirements are dramatically reduced by using low BER rectification to nearly halve the number of comparators in a conventional high speed, low BER flash ADC. 1. A device comprising: [ 'a first comparator generating the first bit, where the first comparator is configured to receive an analog signal at a first time; and', 'a first path determining a first bit in the plurality of bits, the first path comprising, a rectifier, where the rectifier is configured to receive the analog signal at a second time after the first time; and', 'a plurality of comparators coupled to an output of the rectifier, the plurality of comparators generating the second bit., 'a second path determining a second bit in the plurality of bits, the second path comprising], 'a multi-path, rectifying analog-to-digital converter (ADC) converting an analog signal into a plurality of bits, the ADC comprising2. The device of claim 1 , the second path further comprising:a signal hold circuit operating in parallel with the first comparator in the first path, wherein the rectifier is coupled to an output of the signal hold circuit.3. The device of claim 2 , wherein the hold circuit comprises one of a delay circuit claim 2 , a sample-and-hold (SH) circuit and a track-and-hold (TH) circuit.4. The device of claim 3 , wherein the SH circuit comprises a multi-stage SH circuit and the TH circuit comprises a multi-stage TH circuit and wherein an input to the second path is coupled between stages in the multi-stage SH circuit or TH circuit.5. The device of claim 1 , wherein the ...

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Номер записи: 63
03-02-2022 дата публикации

WINDOW BASED SUPPLY VOLTAGE CONDITIONING CIRCUIT FOR NOISE FILTERING

Номер: US20220038059A1
Автор: C Sahiti Priya
Принадлежит:

A supply voltage conditioning circuit comprises a differential amplifier, a comparator, a sample and hold (S/H) circuit, and a delay circuit. The differential amplifier receives an input supply voltage and a reference voltage, and outputs a difference signal. The comparator receives the difference signal and a value representative of a noise margin, and outputs a control signal indicative of whether the difference signal is greater than the value representative of the noise margin. The S/H circuit samples the input supply voltage in response to the control signal indicating the difference signal is greater than the noise margin, and outputs a substantially noise free supply voltage. This allows the output supply voltage to track underlying changes in the input supply voltage but filter out noise in the input supply voltage. The delay circuit receives and delays the output supply voltage to generate the reference voltage. 1. A supply voltage conditioning circuit , comprising:a differential amplifier having a first input coupled to an input voltage node, and the differential amplifier having a second differential amplifier input;a comparator having a first input coupled to an output of the differential amplifier, and the comparator having a second comparator input;a sample and hold (S/H) circuit having a first input coupled to an output of the comparator, and the S/H circuit having a second S/H input coupled to the input voltage node; anda delay circuit having an input coupled to an output of the S/H circuit, the delay circuit having an output coupled to the second differential amplifier input.2. The supply voltage conditioning circuit of claim 1 , wherein the second comparator input is configured to receive a value representative of a noise margin for an input voltage on the input voltage node.3. The supply voltage conditioning circuit of claim 2 , wherein the value representative of the noise margin for the input voltage is based on characteristics of a voltage ...

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Номер записи: 64
03-02-2022 дата публикации

FAST BANDWIDTH SPECTRUM ANALYSIS

Номер: US20220038107A1
Автор: Aquino Anthony, Dekoker Michael, Hyman Daniel, Norris Jeffrey
Принадлежит:

An apparatus includes a processor, a Phase-Locked Loop Waveform Generator (PLLWG), a Voltage Controlled Oscillator (VCO), a demodulator, signal conditioning circuitry, and an Analog-to-Digital Converter (ADC). The processor generates control command signals, receives a digital data input signal, and performs spectrum analysis on the digital data input signal. The PLLWG is coupled to the processor, receives the control command signals, and generates a charge pump output signal based on the control command signals. The VCO is coupled to the PLLWG, receives a tuning signal based on the charge pump output signal, and outputs a VCO output signal based on the tuning signal. The demodulator receives an incoming modulated signal and the VCO output signal, and outputs an analog output signal based on the incoming modulated signal and the VCO output signal. The ADC converts the analog output signal into the digital data input signal. 120-. (canceled)21. An apparatus , comprising:a processor to generate control command signals, receive a digital data input signal, and analyze the digital data input signal;a Phase-Locked Loop Waveform Generator (PLLWG), coupled to the processor, to receive the control command signals and generate a charge pump output signal based on the control command signals;a Voltage Controlled Oscillator (VCO), coupled to the PLLWG, to receive a tuning signal based on the charge pump output signal and output a VCO output signal based on the tuning signal;a demodulator to receive an incoming modulated signal and the VCO output signal, and output an in-phase analog data signal and a quadrature analog data signal based on the incoming modulated signal and the VCO output signal;an image reject circuit to receive the in-phase analog data signal and the quadrature analog data signal and sum the in-phase analog data signal and the quadrature analog data signal into the analog output signal; andan Analog-to-Digital Converter (ADC) to convert the analog output ...

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Номер записи: 65
22-01-2015 дата публикации

Device for converting analogue signals into digital signals

Номер: US20150022388A1
Автор: Daniel Dzahini, Fatah-Ellah Rarbi, Laurent Gallin-Martel
Принадлежит: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE CNRS

Method and device for converting analogue signals, of a plurality of pathways, into digital signals. A common circuit ( 2, 3 ) generates first analogue signals corresponding to high-order bits of digital signals For each pathway, a first means compares the first analogue signals with the signal to be converted. A first means ( 18 ) stores high-order bits corresponding to the value of a first analogue signal close to the signal to be converted. A means ( 9 ) stores the deviation between the analogue signal to be converted and said first detected value. A generator means ( 11, 12 ) generates a predetermined number of second analogue signals. A second means compares by successive approximations said second analogue signals with said deviation. A means ( 20 ) stores said low-order bits corresponding to the results arising from said second means of comparison. A means ( 22 ) assembles said high-order bits and said low-order bits.

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Номер записи: 66
16-01-2020 дата публикации

COMPARATOR DIAGNOSTIC SYSTEMS AND METHODS

Номер: US20200021280A1
Автор: Miller Daniel James
Принадлежит: MAXIM INTEGRATED PRODUCTS, INC.

An analog front-end circuit for self-calibrating a comparator, the circuit comprising a comparator in a comparator measurement path; a preamplifier coupled to the comparator by a set of switches; and an amplifier coupled to the preamplifier, the preamplifier receiving a reference signal as a first input and a user-definable reference as a second input, the user-definable reference generating a user-definable value chosen to create a known condition at an output of the preamplifier, the preamplifier determines a residual value that represents a measurement error in a signal path comprising the comparator and is used to adjust the user-definable reference value to calibrate the signal path such that threshold boundaries for the comparator can be adjusted to tighten a comparator specification. 1. An analog front-end circuit for self-calibrating a comparator , the circuit comprising:a comparator in a comparator measurement path;a preamplifier coupled to the comparator by a set of switches; andan amplifier coupled to the preamplifier, the preamplifier receiving a reference signal as a first input and a user-definable reference as a second input, the user-definable reference generating a user-definable value chosen to create a known condition at an output of the preamplifier, the preamplifier determines a residual value that represents a measurement error in a signal path comprising the comparator and is used to adjust the user-definable reference value to calibrate the signal path such that threshold boundaries for the comparator can be adjusted to tighten a comparator specification.2. The circuit according to claim 1 , further comprising one or more switches configured to decouple the preamplifier from the comparator to perform a calibration operation.3. The circuit according to claim 1 , wherein the reference signal and an ADC are decoupled from the preamplifier in regular operation.4. The circuit according to claim 1 , further comprising a programmable data register ...

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Номер записи: 67
21-01-2021 дата публикации

DIFFERENTIAL SOURCE FOLLOWER WITH CURRENT STEERING DEVICES

Номер: US20210021277A1
Автор: Cohen Ariel, Krupnik Yoel, SHIFMAN Yizhak Ethanan
Принадлежит: Intel Corporation

Describe is a buffer which comprises: a differential source follower coupled to a first input and a second input; first and second current steering devices coupled to the differential source follower; and a current source coupled to the first and second current steering devices. The buffer provides high supply noise rejection ratio (PSRR) together with high bandwidth. 1. (canceled)2. An apparatus comprising:an analog front-end;a track and hold circuitry coupled to an output of the analog front-end; and a differential source follower coupled to a first input and a second input, wherein the first input is separate from the second input;', 'first and second current steering devices coupled to the differential source follower; and', 'a current source coupled to the first and second current steering devices., 'a buffer coupled to an output of the track and hold circuitry, the buffer comprising3. The apparatus of claim 2 , wherein the analog front-end comprises a matching network having an impedance that matches an impedance of a transmission media to be coupled to the analog front-end.4. The apparatus of claim 3 , wherein the analog front-end comprises a continuous time linear equalizer coupled to the matching network and the buffer.5. The apparatus of claim 2 , wherein the buffer comprising:a first capacitor coupled to the first current steering device and the differential source follower; anda second capacitor coupled to the second current steering device and the differential source follower.6. The apparatus of comprising a bias generator to generate bias for the differential source follower.7. The apparatus of claim 4 , wherein the buffer comprising:a third capacitor coupled to the first input and the second current steering device; anda fourth capacitor coupled to second input and the second current steering device, wherein the fourth capacitor is coupled to a first output, and wherein the third capacitor is coupled to a second output.8. The apparatus of claim 2 , ...

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Номер записи: 68
10-02-2022 дата публикации

HALL SENSOR-BASED DATA ACQUISITION SYSTEM

Номер: US20220043077A1
Автор: Bhattacharya Anindya, Drakshapalli Prashanth, Lee Seung Bae, Melanson John L.
Принадлежит:

A data acquisition system (DAS) for acquiring data from a Hall effect sensor includes one or more state variables, a multiplexer that periodically rotates a signal from the Hall effect sensor, and a controller that resets the one or more state variables in synchronization with rotation of the signal. The state variables may be digital states in a digital memory or voltages of capacitors the controller forces to a reset voltage. The state variables may be included in a noise-shaping SAR ADC, a delta-sigma ADC, a digital filter, an integrator, an analog filter, a VCO, an incremental ADC or an auxiliary ADC-assisted incremental ADC, or an auxiliary ADC of the DAS. 1. A data acquisition system (DAS) for acquiring data from a Hall effect sensor , comprising:one or more state variables;a multiplexer that periodically rotates a signal from the Hall effect sensor; anda controller that resets the one or more state variables in synchronization with rotation of the signal.2. The DAS of claim 1 , wherein the one or more state variables comprises one or more voltages of one or more capacitors.3. The DAS of claim 2 , wherein to reset the one or more state variables claim 2 , the controller forces the one or more voltages of the one or more capacitors to a reset voltage.4. The DAS of claim 3 , wherein the reset voltage is from a list of voltages comprising:a ground voltage;a common mode voltage;a random voltage;a dithered voltage;a predetermined direct current voltage;an alternating current sinusoidal voltage notched out by subsequent filtering; anda voltage that is uncorrelated to a sampled voltage of the rotated signal.5. The DAS of claim 2 , wherein at least one of the one or more capacitors are included in an interface to the Hall effect sensor.6. The DAS of claim 1 , wherein the one or more state variables comprises at least one digital state in a digital memory claim 1 , and wherein to reset the at least one digital state claim 1 , the controller resets the digital state in ...

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Номер записи: 69
26-01-2017 дата публикации

SEMICONDUCTOR DEVICE PERFORMING COMMON MODE VOLTAGE COMPENSATION USING ANALOG-TO-DIGITAL CONVERTER

Номер: US20170026051A1
Автор: CHO Thomas Byung-Hak, LEE Jong-Woo
Принадлежит:

A semiconductor device is provided that includes a first chip that generates a single signal by connecting a first signal line and a second signal line, to which differential signals are respectively provided, and outputs the single signal to a third signal line. The first chip is driven by a first power supply voltage. The semiconductor device also includes a second chip comprising an analog-to-digital converter (ADC) that receives the single signal through the third signal line, compares the single signal with a reference voltage, and outputs a digital signal based on the comparison. The semiconductor device also includes a controller that monitors the digital signal and adjusts the reference voltage to be approximately equivalent to the first power supply voltage. 1. A semiconductor device comprising:a first chip that generates a single signal by connecting a first signal line and a second signal line, to which differential signals are respectively provided, and outputs the single signal to a third signal line, the first chip being driven by a first power supply voltage;a second chip comprising an analog-to-digital converter (ADC) that receives the single signal through the third signal line, compares the single signal with a reference voltage, and outputs a digital signal based on the comparison; anda controller that monitors the digital signal and adjusts the reference voltage to be approximately equivalent to the first power supply voltage.2. The semiconductor device of claim 1 , wherein the second chip further comprises a variable current source claim 1 , the reference voltage is proportional to an amount of current output from the variable current source claim 1 , and the controller adjusts the amount of current output from the variable current source based on monitoring of the digital signal.3. The semiconductor device of claim 1 , wherein the second chip further comprises a voltage divider that comprises a variable resistor claim 1 , the reference voltage ...

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Номер записи: 70
29-01-2015 дата публикации

IMAGE SENSOR AND METHOD OF CONTROLLING THE SAME

Номер: US20150029372A1
Автор: HAM Seogheon, Lee Hyeokjong, Seo Jinho
Принадлежит:

Provided is an image sensor including a sensor array including a plurality of pixels arranged in rows and columns. The image sensor may include a ramp signal generator which may generate a ramp signal. The intensity of the ramp signal may increase or decrease in response to a ramp enable signal. The image sensor may include an analog-digital converter electrically connected to one of the columns of the pixels. The analog-digital converter may be configured to compare an output signal from the one of the columns of the pixels with the ramp signal, thereby generating time information. The analog-digital converter may be configured to convert the time information to digital information in response to a counter enable signal. An activation of the counter enable signal may be delayed by a predetermined time delay, compared with that of the ramp enable signal.

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Номер записи: 71
28-01-2021 дата публикации

Mixed-Domain Circuit with Differential Domain-Converters

Номер: US20210026309A1
Автор: Elkholy Ahmed
Принадлежит:

A mixed-domain circuit has a differential pair of Digital-to-Time Converters (DTCs), one receiving a reference clock and the other receiving a feedback clock. A Time-to-Digital Converter (TDC) compares outputs from the differential pair of DTCs and generates a digital error value that controls a digital loop filter that controls a Digitally-Controlled Oscillator (DCO) that generates an output clock. A Multi-Modulus Divider (MMD) generates the feedback clock. An accumulated modulation from a delta-sigma modulator is compared to the digital error value by a Least-Mean Square (LMS) correlator to adjust supply voltage or current sources in the pair of DTCs to compensate for errors. A capacitor in each DTC has a charging time adjusted by the accumulated modulation. The DTC can be reduced to a Time-to-Voltage Converter (TVC) and the analog voltages on the capacitors input to an Analog-to-Digital Converter (ADC) to generate the digital error value. 1. A mixed-domain circuit comprising:a first converter having a first input in a first domain, for generating a first output in a second domain;a second converter having a second input in the first domain, for generating a second output in the second domain;wherein the first domain is selected from the group consisting of a time domain, and a digital domain;wherein the second domain is selected from the group consisting of a time domain, a digital domain, and a voltage domain;wherein the first converter is matched to the second converter, wherein a signal injected to both the first input and to the second input adjusts the first output and adjusts the second output by a substantially same amount when a same adjustment signal is applied to both the first converter and to the second converter;wherein the second domain and the first domain are different domains;a differential converter that receives the first output from the first converter, and that receives the second output from the second converter, for generating an error ...

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Номер записи: 72
10-02-2022 дата публикации

RESISTIVE SENSOR BASED DATA ACQUISITION SYSTEM USING LOW DISTORTION ANALOG FRONT-END AND DIGITAL GAIN ERROR CORRECTION

Номер: US20220045689A1
Автор: Bhattacharya Anindya, Drakshapalli Prashanth, Lee Seung Bae, Melanson John L.
Принадлежит:

A data acquisition system (DAS) for processing an input signal from a resistive sensor (e.g., Hall effect sensor) includes a sensor signal path that digitizes the input signal. An input impedance of the sensor signal path attenuates the input signal. A gain error corrector applies a gain error correction factor in a digital domain of the DAS to the digitized input signal to compensate for a loading effect to the resistive sensor. The sensor signal path includes an inverting amplifier that provides low distortion for the input signal and an ADC (e.g., delta-sigma, SAR, pipelined, auxiliary) that digitizes the input signal. A sensor characterization path digitizes the sensor resistance which the gain error corrector uses, along with the inverting amplifier input impedance, to calculate the gain error correction factor. 1. A data acquisition system (DAS) for processing an input signal from a resistive sensor , comprising:a sensor signal path that digitizes the input signal;wherein an input impedance of the sensor signal path attenuates the input signal;a gain error corrector that applies a gain error correction factor in a digital domain of the DAS to the digitized input signal to compensate for a loading effect to the resistive sensor;a sensor characterization path that characterizes a resistance of the sensor; andwherein the gain error corrector uses the characterized resistance of the sensor to determine the gain error correction factor.2. The DAS of claim 1 , wherein the sensor signal path comprises:an analog front-end circuit that comprises an inverting amplifier that provides low distortion for the input signal.3. The DAS of claim 1 , wherein the sensor signal path comprises an analog-to-digital converter (ADC).4. The DAS of claim 3 , wherein the ADC is one of the following: a delta-sigma analog-to-digital converter (ADC) claim 3 , a successive approximation register (SAR) ADC claim 3 , a pipelined ADC claim 3 , or an auxiliary ADC for digitizing the input signal ...

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Номер записи: 73
24-01-2019 дата публикации

INBUILT THRESHOLD COMPARATOR

Номер: US20190028113A1
Автор: Soundararajan Rishi
Принадлежит:

A comparator includes a first input stage coupled to a first signal input and a first reference input, wherein the first input stage is coupled between a first node and a second node. A second input stage is coupled to a second signal input and a second reference input, wherein the second input stage is coupled between a third node and the second node. An output stage generates at least one output signal in response to the first and second input signals. First switching circuitry is coupled between the first node and the output stage. The first switching circuitry is for coupling the first node to a fourth node in response to a reset signal. Second switching circuitry is coupled between the third node and the output stage. The second switching circuitry is for coupling the third node to a fifth node in response to the reset signal. 1. A comparator comprising:a first input stage coupled to a first signal input and a first reference input, the first input stage coupled between a first node and a second node;wherein the first input stage comprises:a first transistor coupled between the first node and the second node, the gate of the first transistor being coupled to the first signal input; anda first plurality of capacitors coupled to the first node and a first plurality of switches, the first plurality of switches coupled to the first reference input wherein the first plurality of switches is controlled by a processor;a second input stage coupled to a second signal input and a second reference input, the second input stage coupled between a third node and the second node;wherein the second input stage comprises:a second transistor coupled between the third node and the second node, the gate of the second transistor being coupled to the second signal input; anda second plurality of capacitors coupled to the third node and a second plurality of switches, the second plurality of switches coupled to the second reference input wherein the second plurality of switches is ...

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Номер записи: 74
28-01-2021 дата публикации

SMART ELECTRONIC SWITCH

Номер: US20210028615A1
Автор: Faricelli Marco, Illing Robert, Mayer Alexander
Принадлежит:

A circuit may include an electronic switch that has a load current path coupled between an output node and a supply node and that is configured to connect or disconnect the output node and the supply node in accordance with a drive signal. Further, the circuit includes a monitoring circuit that is configured to receive a current sense signal, which represents the load current passing through the load current path, and that is further configured to determine a protection signal based on the current sense signal, a state of the monitoring circuit, and at least one wire parameter. The wire parameter characterizes a wire that is—during operation—connected to the output node, and the protection signal is indicative of whether to disconnect the output node from supply node. Further, the circuit includes a protection circuit connected to the monitoring circuit. 1. A circuit comprising:an electronic switch having a load current path coupled between an output node and a supply node and configured to connect or disconnect the output node and the supply node in accordance with a drive signal;a monitoring circuit configured to receive a current sense signal representing the load current passing through the load current path and to determine a protection signal based on the current sense signal, a state of the monitoring circuit, and at least one wire parameter that characterizes a wire operably connected to the output node, the protection signal being indicative of whether to disconnect the output node from the supply node; anda protection circuit connected to the monitoring circuit and configured to store the state of the monitoring circuit in one or more registers included in the protection circuit,wherein the protection circuit is configured to receive a logic supply potential at an input node, and includes a supply circuit configured to provide a temporary supply for the protection circuit when a supply potential received at an input node deviates from an internal supply ...

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Номер записи: 75
01-05-2014 дата публикации

SUCCESSIVE APPROXIMATION A/D CONVERTER

Номер: US20140118175A1
Автор: Nakanishi Junya
Принадлежит: ASAHI KASEI MICRODEVICES CORPORATION

The successive approximation A/D converter includes: switch groups to each of which is connected to the other end of each corresponding capacitor of capacitors to to selectively switch a capacitor to be applied to a successive comparison in response to a switch group control signal Ct a comparator for making a successive comparison of a comparison voltage VSN based on a holding voltage on each corresponding capacitor, selected through the switch groups from among the capacitors, with a predetermined reference voltage VC in synchronization with a timing control signal CLK to obtain a judgment output according to the comparison result; and a voltage application part for applying a predetermined voltage to the comparison voltage based on a form-of-voltage application control signal Ct for a predetermined period when a predetermined time has elapsed after the successive comparison. 1. A successive approximation A/D converter comprising:a capacitor array having a plurality of capacitors;a plurality of switch groups connected to the capacitor array;a comparator connected to the capacitor array to make a successive comparison in response to a timing control signal to obtain a judging output signal; anda first controller for generating a control signal to control the plurality of switch groups according to the judging output signal from the comparator,wherein when the comparator cannot obtain the judging output signal at a time of comparison timing by the timing control signal, the judging output signal is obtained after a lapse of a predetermined time after the time of the comparison timing.2. The successive approximation A/D converter according to claim 1 , wherein a successive comparison of a holding voltage on each corresponding capacitor of the plurality of capacitors in the capacitor array with a predetermined reference voltage is made to obtain a digital output signal corresponding to an input analog signal.3. The successive approximation A/D converter according to ...

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Номер записи: 76
01-05-2014 дата публикации

METHODS AND APPARATUS FOR A SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER

Номер: US20140118176A1
Автор: Kolla Yeshwant Nagaraj, Price Burt L., Shah Dhaval R.
Принадлежит: QUALCOMM INCORPORATED

Methods and apparatus for a successive approximation register analog to digital converter are provided. In an example, provided is a method for digitally representing an analog input signal. A bit of the digital output signal is generated by altering a test voltage by an amount comparable to a weight afforded to the bit, comparing the altered test voltage with the analog input signal to create a comparison output, switching a two-to-one multiplexer to select the comparison output instead of a preceding shift-successive approximation register block output, storing the comparison output in a flip-flop, inhibiting clocking of the flip-flop, and outputting the comparison output from the flip-flop as the bit of the digital output signal. 1. A successive approximation register (SAR) including a flip-flop configured to perform functions of a shift register and a flip-flop.2. The SAR of claim 1 , wherein at least a part of the SAR is integrated on a semiconductor die.3. The SAR of claim 1 , further comprising at least one of a processor claim 1 , integrated circuit claim 1 , base station claim 1 , and a mobile device claim 1 , with which the flip-flop is integrated.4. The SAR. of claim 1 , further comprising one of a NAND latch configured to inhibit clocking of the flip-flop and a NOR latch configured to inhibit clocking of the flip-flop.5. The SAR of claim 1 , further comprising an RC delay and a two-input OR gate configured to inhibit clocking of the flip-flop.6. The SAR of claim 1 , further comprising a serial read out circuit configure to read a state of the flip-flop.7. The SAR. of claim 1 , further comprising a parallel read out circuit configured to read a state of the flip-flop.8. An analog to digital converter (ADC) claim 1 , comprising:a successive approximation register (SAR) including a flip-flop configured to perform functions of a shift register and a flip-flop.9. The ADC of claim 8 , wherein at least a part of the ADC is integrated on a semiconductor die.10. ...

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Номер записи: 77
02-02-2017 дата публикации

SYMMETRICAL CAPACITOR ARRAYS SUCCESIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTER (ADC)

Номер: US20170033800A1
Автор: Ng Kian Ann, Xu Yong Ping, Yuan Chao
Принадлежит:

Analog-to-digital converter (ADC) circuitry includes a first binary-weighted capacitor array having a total capacitance of 2C. The value of n represents number of bits of a digital signal that represents an analog signal. The ADC circuitry also includes a second binary-weighted capacitor array having a total capacitance of 2C. In addition to that, the ADC circuitry further includes a comparator circuit having first and second terminals. The first terminal is coupled to the first binary-weighted capacitor array, and the second terminal is coupled to the second binary weighted capacitor array. The switching circuit within the second binary-weighted capacitor array may be configurable to couple a largest capacitance capacitor within the second binary-weighted capacitor array from remaining capacitors within the second binary weighted capacitor array. 1. Analog-to-digital converter (ADC) circuitry , comprising:{'sup': 'n-2', 'first and second binary-weighted capacitor arrays, wherein each first and second binary-weighted capacitor array is having a total capacitance of 2C, wherein n represents a number of bits of a digital signal representing an analog signal;'}a comparator circuit having first and second terminals, wherein the first terminal is coupled to the first binary-weighted capacitor array, and the second terminal is coupled to the second binary weighted capacitor array; anda switching circuit within the second binary-weighted capacitor array is configurable to couple a largest capacitance capacitor within the second binary-weighted capacitor array from remaining capacitors within the second binary weighted capacitor array.2. The ADC circuitry of claim 1 , wherein the first binary-weighted capacitor array includes a plurality of capacitors arranged parallel to each other claim 1 , wherein capacitances for the capacitors are based on a sequence that follows 2 claim 1 , where a value of the m decreases from m=n to m=3.3. The ADC circuitry of claim 2 , wherein the ...

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Номер записи: 78
17-02-2022 дата публикации

Flash analog to digital converter

Номер: US20220052705A1
Автор: Chien-Ming Wu, Shih-Hsiung Huang
Принадлежит: Realtek Semiconductor Corp

A flash analog to digital converter includes a voltage generator circuit, an encoder circuit, and first and second double differential amplifier circuits. The voltage generator circuit generates reference voltages according to first and second voltages. The encoder circuit generates a digital signal corresponding to an input signal according to first signals. The first double differential amplifier circuit compares the input signal with a first reference voltage in the reference voltages, to generate a corresponding one of the first signals. The second double differential amplifier circuit compares the input signal with a second reference voltage in the reference voltages, to generate a corresponding one of the first signals. A difference between the first voltage and the first reference voltage is less than that between the first voltage and the second reference voltage, and the first and the second double differential amplifier circuits have different circuit architectures.

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Номер записи: 79
31-01-2019 дата публикации

RADIO FREQUENCY FLASH ADC CIRCUITS

Номер: US20190036539A1
Автор: CHANA Jatinder, LYE William Michael, ZORTEA Anthony Eugene
Принадлежит:

A system and method for sampling an RF signal are described. The system comprises a plurality of capacitors, a plurality of resistors, and a sampling circuit. A first port of each capacitor of the plurality of capacitors is coupled to the RF signal. A first port of each resistor of the plurality of resistors is coupled to one of a plurality of reference levels. A second port of each resistor of the plurality of resistors is coupled to a second port of a corresponding capacitor of the plurality of capacitors. The sampling circuit produces a plurality of digital outputs by sampling the second port of each resistor of the plurality of resistors. 120-. (canceled)21. A system comprising:a plurality of preamplifiers, wherein a first input of each of the plurality of preamplifiers is operably coupled to a radio frequency (RF) input, and wherein a second input of each of the plurality of preamplifiers is operably coupled to a reference level of a plurality of reference levels; anda sampling circuit operably coupled to an output of each of the plurality of preamplifiers, wherein the sampling circuit is operable to produce a plurality of digital outputs.22. The system of claim 21 , wherein the system comprises a converter operable to convert the plurality of digital outputs to a binary output.23. The system of claim 21 , wherein the system comprises a series of resistors between a first reference input and a second reference input claim 21 , each reference level of the plurality of reference levels being produced along the series of resistors.24. The system of claim 23 , wherein the system comprises a first switch for selecting the first reference input and a second switch for selecting the second reference input.25. The system of claim 21 , wherein the sampling circuit comprises a plurality of comparators claim 21 , wherein the output of each of the plurality of preamplifiers is operably coupled to an input of a comparator of the plurality of comparators.26. The system of ...

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Номер записи: 80
31-01-2019 дата публикации

PHOTOELECTRIC CONVERSION APPARATUS AND IMAGE CAPTURING SYSTEM

Номер: US20190036540A1
Автор: Hashimoto Seiji, Ise Makoto, Yoshida Daisuke
Принадлежит:

In a first sensitivity level, an AD converter performs AD conversion selectively using, in accordance with the level of the analog signal, any one of a first reference signal and a second reference signal that have mutually different slopes, and in a second sensitivity level that is different from the first sensitivity level, the AD converter performs AD conversion only using a third reference signal. 1. (canceled)2. A photoelectric conversion apparatus in which a sensitivity level is settable , the photoelectric conversion apparatus comprising:a ramp signal supply unit configured to supply a ramp signal; andan analog-to-digital (AD) converter into which an analog signal based on light incident on a pixel and the ramp signal are input, and configured to perform analog-to-digital (AD) conversion on the analog signal by comparing the analog signal and the ramp signal,wherein in the AD conversion in a first sensitivity level, the ramp signal supply unit outputs a first number of ramp signals having different slopes to the AD converter, andwherein in the AD conversion in a second sensitivity level different from the first sensitivity level, the ramp signal supply unit outputs a second number, smaller than the first number, of ramp signals having different slopes or only one ramp signal to the AD converter.3. The photoelectric conversion apparatus according to claim 2 , wherein the second sensitivity level is higher than the first sensitivity level.4. The photoelectric conversion apparatus according to claim 3 , wherein a ramp signal to be used for the AD conversion in the second sensitivity level includes a ramp signal having a smallest slope among the first number of ramp signals.5. The photoelectric conversion apparatus according to claim 3 , wherein a ramp signal to be used for the AD conversion in the second sensitivity level includes a ramp signal having a smaller slope than a slope of any of the first number of ramp signals.6. The photoelectric conversion ...

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Номер записи: 81
30-01-2020 дата публикации

SOLID-STATE IMAGING DEVICE, AND CAMERA SYSTEM USING SAME

Номер: US20200036931A1
Автор: ABE YUTAKA, FUJINAKA Hiroshi, Higuchi Masahiro, ICHIRYU Dai, NISHIMURA Kazuko
Принадлежит:

A solid-state imaging device includes an A/D converter per column. The A/D converter performs a first A/D conversion that (i) refines, using a first comparator, a range including a potential of an analog signal to a range of a potential corresponding to a difference between a first potential and a second potential through a binary search, and further (ii) generates, based on a result of the binary search, a first digital signal being a high-order portion of a digital signal. The A/D converter also performs a second A/D conversion that generates, based on a ramp signal and the result of the binary search, a second digital signal being a low-order portion of a remainder of the digital signal, by measuring a time necessary for an output of a second comparator to be inverted. 1. A solid-state imaging device , comprising:a plurality of pixel cells arranged in an X-direction and a Y-direction, the plurality of pixels cells each including a photoelectric converter that converts an optical signal to an electrical signal;a plurality of vertical signal lines arranged in the X-direction that are connected to the plurality of pixel cells and transmit the electrical signal as an analog signal; anda plurality of analog-to-digital (A/D) converters arranged in the X-direction that are respectively connected to the plurality of vertical signal lines and convert the analog signal to a digital signal, wherein include a first comparator and a second comparator;', 'perform a first A/D conversion that (i) refines, using the first comparator, a range including a potential of the analog signal to a range of a potential corresponding to a difference between a first potential and a second potential through a binary search, and further (ii) generates, based on a result of the binary search, a first digital signal being a high-order portion of the digital signal; and', 'perform a second A/D conversion that generates, based on a ramp signal and the result of the binary search, a second digital ...

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Номер записи: 82
12-02-2015 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20150042500A1
Автор: FUJIWARA Masaki, MATSUMOTO Takashi, MORIMOTO Yasuo
Принадлежит: RENESAS ELECTRONICS CORPORATION

To provide a semiconductor device capable of accurately controlling the cycle of an internal clock signal. This semiconductor device, by using signal that is output from a sequence register of an asynchronous successive approximation type ADC when N times of comparison are completed, detects whether or not the signal and its delay signal are output when the period transitions from a comparison period to a sampling period, and generates, on the basis of the detection result, a delay control signal for controlling the cycle of an internal clock signal by controlling the delay times of the delay circuits. 1. A semiconductor device comprising an asynchronous successive approximation type A/D converter that samples an external analog signal in a sampling period , generates an internal clock signal in a comparison period , performs first to n-th comparisons in synchronization with first to n-th leading edges (where n is an integer equal to or greater than 2) of the internal clock signal , and converts the external analog signal to a multi-bit digital signal on the basis of a comparison result ,wherein the asynchronous successive approximation type A/D converter includes a sequence register that outputs first to n-th signals indicating that the first to n-th comparisons have been performed, respectively,the semiconductor device further comprising a control circuit that detects whether or not the n-th signal is output when a period transitions from the comparison period to the sampling period, and that controls a cycle of the internal clock signal on the basis of a detection result.2. The semiconductor device according to claim 1 , further comprising a delay circuit that delays the n-th signal and generates an (n+1)th signal claim 1 ,wherein the control circuit detects whether or not the n-th and (n+1)th signals are output, respectively, when a period transitions from the comparison period to the sampling period, and controls a cycle of the internal clock signal on the ...

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Номер записи: 83
11-02-2016 дата публикации

DOUBLE DATA RATE COUNTER, AND ANALOG-TO-DIGITAL CONVERTER AND CMOS IMAGE SENSOR USING THE SAME

Номер: US20160043725A1
Автор: HWANG Won-Seok, LEE Sung-Jin
Принадлежит:

A Double Data Rate (DDR) counter includes an input clock control portion suitable for generating a first clock corresponding to a state of a input clock based on a counter enable signal, and an LSB control portion suitable for holding a least significant bit based on the counter enable signal and successively performing a counting operation on the first clock in multiple sections. 1. A Double Data Rate DDR counter , comprising:an input clock control portion suitable for generating a first clock corresponding to a state of a input clock based on a counter enable signal; anda Least Significant Bit (LSB) control portion suitable for holding an LSB based on the counter enable signal and successively performing a counting operation on the first clock in multiple sections.2. The DDR counter of claim 1 , wherein the input clock control portion detects the state of a neighboring clock of the input clock based on a first edge of the counter enable signal and inverts or non-inverts the input clock based on a detected state of the neighboring clock.3. The DDR counter of claim 1 , wherein the input clock control portion includes:a counting section determination block suitable for receiving the input clock and the counter enable signal and determining a counting section;a clock sampling block suitable for sampling the state of the input clock based on the counter enable signal; anda first inversion/non-inversion block suitable for inverting or non-inverting an output of the counting section determination block based on a clock sampling result obtained from the clock sampling block and outputting the first clock to the LSB control portion.4. The DDR counter of claim 3 , wherein the input clock control portion further includes:a third inversion/non-inversion block suitable for inverting or non-inverting a cross-correlation double sampling output based on a control signal and outputting the counter enable signal.5. The DDR counter of claim 3 , wherein the counting section ...

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Номер записи: 84
09-02-2017 дата публикации

Successive approximation method with a nonlinear characteristic

Номер: US20170041015A1
Автор: Alexander Kahl, Daniel Lopez-Diaz, Steffen Tratmann, Thomas Niederfriniger
Принадлежит: Lantiq Beteiligungs GmbH and Co KG

A circuit comprises a successive approximation analog-to-digital converter that comprises a feedback path and is operated for example in accordance with the successive approximation method. The feedback path is configured to translate a digital signal in accordance with a prescribed function and to furthermore convert the translated digital signal into an analog feedback signal. For example, the prescribed function can be an exponential function. As such, it can be possible to convert an input signal into an output signal by means of a nonlinear characteristic.

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Номер записи: 85
09-02-2017 дата публикации

SUCCESSIVE COMPARISON A/D CONVERSION CIRCUIT

Номер: US20170041016A1
Автор: Harada Yasunari
Принадлежит: OLYMPUS CORPORATION

A successive comparison A/D conversion circuit includes: an comparison circuit including a differential amplification circuit which includes a pair of differential input terminals, amplifies a pair of first differential signals input into the pair of differential input terminals, and outputs a pair of second differential signals, and a latch circuit which compares voltages of the second differential signals output from the differential amplification circuit, retains an comparison result, and outputs the retained comparison result; a digital circuit which generates a digital signal corresponding to the first differential signal, based on the comparison result; an arithmetic circuit which generates a reference signal based on the digital signal, generates the first differential signal by subtracting the reference signal from a third differential signal or adding the reference signal to the third differential signal, and outputs the generated first differential signal to the pair of differential input terminals; and a control circuit. 1. A successive comparison A/D conversion circuit , comprising:an comparison circuit including a differential amplification circuit which includes a pair of differential input terminals, amplifies a pair of first differential signals input into the pair of differential input terminals, and outputs a pair of second differential signals, and a latch circuit which compares voltages of the second differential signals output from the differential amplification circuit, retains an comparison result, and outputs the retained comparison result;a digital circuit which generates a digital signal corresponding to the first differential signal, based on the comparison result;an arithmetic circuit which generates a reference signal based on the digital signal, generates the first differential signal by subtracting the reference signal from a third differential signal, or by adding the reference signal to the third differential signal, and outputs the ...

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Номер записи: 86
24-02-2022 дата публикации

Ratiometric analog-to-digital conversion circuit

Номер: US20220060194A1
Автор: Jang Hyun Yoon
Принадлежит: Silicon Works Co Ltd

A ratiometric analog-to-digital conversion circuit includes a first voltage range operation circuit configured to use a first power supply voltage of a first voltage range, and output an analog signal corresponding to an external input signal; and a second voltage range operation circuit configured to use a second power supply voltage of a second voltage range, generate a digital value by analog-to-digital converting the analog signal, feed back the digital value for analog-to-digital conversion, and output a digital signal corresponding to the digital value and proportional to the input signal.

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Номер записи: 87
19-02-2015 дата публикации

Signal converter and method for operating a signal converter

Номер: US20150048958A1
Автор: Clemens Kain, Heimo Hartlieb, Michael Hausmann
Принадлежит: INFINEON TECHNOLOGIES AG

In accordance with an embodiment, a method for operating a signal converter includes converting an analog input signal to a digital output signal, comprising by comparing the analog input signal to an analog comparison signal, and detecting whether the analog input signal exceeds a predetermined maximum or minimum threshold by comparing the analog input signal to an analog threshold signal. The analog comparison signal and the analog threshold signal are generated by a same digital-to-analog converter.

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Номер записи: 88
18-02-2016 дата публикации

Multi-zone data converters

Номер: US20160049948A1
Автор: Curtis Ling
Принадлежит: Maxlinear Inc

Aspects of a method and system for data converters having a transfer function with multiple operating zones. In some embodiments, an operating zone of the multiple operating zones is characterized by more stringent performance criteria than the other operating zones. Thus, such data converters may receive an input signal and generate an output signal from the input signal per the transfer function and the more stringent performance criteria in the appropriate operating zone.

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Номер записи: 89
08-05-2014 дата публикации

Quadrature signal decoding using a driver

Номер: US20140125503A1
Автор: MunishKumar MANGAL, Ranajay MALLIK
Принадлежит: STMicroelectronics International NV

A system and method for decoding quadrature signals includes a quadrature signal generator, a quadrature signal decoder, a key matrix and a driver. The quadrature signal generator generates quadrature signals on rotation. The quadrature signal decoder is configured to convert the quadrature signals into non-overlapping signals. The key matrix is configured to receive the non-overlapping signals. The driver is configured to scan the key matrix to decode the non-overlapping signals to generate an event update corresponding to a direction of rotation of the quadrature signal generator.

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Номер записи: 90
16-02-2017 дата публикации

Reference Voltage Generator for an Analog-Digital Converter and Method for Analog-Digital Conversion

Номер: US20170047940A1
Автор: Cardoso Paulo António Ribeiro, de Figueiredo Pedro Miguel Ferreira
Принадлежит:

Analog-digital converter configured for conversion of an input voltage, represented by a pair of input potentials, into a binary code using successive approximation. The analog-digital converter comprises a reference voltage generator (RVG) supplying a first pair of reference potentials and a second pair of reference potentials. The analog-digital converter further comprises a switched capacitor array (SCA) configured to receive the first and the second pair of reference potentials as well as a control unit (CTRL) coupled to the switched capacitor array (SCA) and configured to switch capacitors of the switched capacitor array (SCA) either to the first pair of reference potentials or to the second pair of reference potentials depending on a progress of the conversion. 1. Reference voltage generator (RVG) for supplying a first pair of reference potentials at a first terminal pair and a second pair of reference potentials at a second terminal pair to a switched capacitor array (SCA) of an analog-digital converter working with successive approximation , wherein{'b': 1', '2, 'the reference voltage generator (RVG) comprises a first input (I) and a second input (I) to be coupled to an external voltage supply (EVS); and'}{'b': 1', '2, 'a first charge reservoir (RESa) with a first and a second terminal coupled between the first terminal pair, the first terminal coupled to the first input (I) via a first switch and the second terminal coupled to the second input (I) via a second switch; and'}{'b': 1', '2, 'the second terminal pair is coupled to the first input (I) and the second input (I).'}2. Reference voltage generator (RVG) according to claim 1 , further comprising:{'b': 1', '1, 'a first charge pump (CP) coupled to the first terminal of the first charge reservoir (RESa) via a first pump switch (PS); and'}{'b': 2', '2, 'a second charge pump (CP) coupled to the second terminal of the first charge reservoir (RESa) via a second pump switch (PS).'}31212. Reference voltage ...

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Номер записи: 91
16-02-2017 дата публикации

Analog-to-Digital Converter

Номер: US20170047941A1
Автор: Zhang Zhenyong
Принадлежит:

A system includes an analog-to-digital converter receiving a plurality of input signals. One particular input signal has a particular analog value and the analog-to-digital converter uses a fixed reference to convert the particular analog value to a particular digital value. The analog-to-digital converter uses the particular analog value as a reference for converting the analog values of the remaining input signals. 1. A system , comprising:an analog-to-digital converter receiving a plurality of analog input signalsthe analog-to-digital converter using a fixed reference to convert a first analog input signal from the plurality of analog input signals to a first digital value; andthe analog-to-digital converter using the first digital value for a reference for converting the plurality of analog input signals, except the first analog input signal, to digital values.2. The system of where the first digital value is an output of the system.3. The system of claim 1 , wherein the first analog input signal has a maximum value when compared to the plurality of analog input signals during a measurement time interval.4. The system of claim 1 , where the analog-to-digital converter is a successive-approximation analog-to-digital converter.5. The system of claim 1 , where the analog-to-digital converter is a floating-point analog-to-digital converter.6. The system of claim 1 , where the analog-to-digital converter is a floating-point successive-approximation analog-to-digital converter. CROSS-REFERENCE TO RELATED APPLICATION(S)This continuation application claims priority to U.S. patent application Ser. No. 14/065,129, filed Oct. 28, 2013, which application is hereby incorporated by reference in its entirety.In electronic systems there is a common need to convert analog signals into a form suitable for use by a processor or controller. An analog-to-digital converter (A/D or ADC) is a circuit that converts an analog signal into one or more digital numbers representing the ...

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Номер записи: 92
03-03-2022 дата публикации

BAYESIAN NETWORK IN MEMORY

Номер: US20220067491A1
Автор: Gong Jing, Parab Ameya, Vengertsev Dmitry, Watson Stewart R.
Принадлежит:

Apparatuses and methods can be related to implementing a Bayesian neural network in a memory. A Bayesian neural network can be implemented utilizing a resistive memory array. The memory array can comprise programmable memory cells that can be programed and used to store weights of the Bayesian neural network and perform operations consistent with the Bayesian neural network.

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Номер записи: 93
25-02-2016 дата публикации

SEMICONDUCTOR DEVICE, ANALOG-TO-DIGITAL CONVERSION METHOD, ONBOARD SYSTEM, AND MEASUREMENT METHOD

Номер: US20160053705A1
Автор: Goto Masashi
Принадлежит:

There is provided a semiconductor device including: an integrator that repeats integrating a first reference voltage after integrating an analog signal; a comparator that compares an output of the integrator and a second reference voltage; a counter circuit that counts a first integration time determined to integrate the analog signal, and a second integration time until the output of the integrator reaches the second reference voltage from start of integration of the first reference voltage; a calculation circuit that calculates a digital value of the analog signal based on the first and the second integration times; a control circuit that performs control so that the analog signal is input to the integrator while the counter circuit counts the first integration time; and an integration time update circuit that updates the first integration time counted by the counter circuit based on the second integration time counted thereby. 1. A semiconductor device comprising:an integrator that repeats integrating a first reference voltage after integrating an analog signal;a comparator that compares an output of the integrator and a second reference voltage;a counter circuit that counts a first integration time determined to integrate the analog signal, and a second integration time until the output of the integrator reaches the second reference voltage from start of integration of the first reference voltage;a calculation circuit that calculates a digital value of the analog signal based on the first and the second integration times;a control circuit that performs control so that the analog signal is input to the integrator while the counter circuit counts the first integration time; andan integration time update circuit that updates the first integration time counted by the counter circuit based on the second integration time counted by the counter circuit.2. The semiconductor device according to claim 1 , whereinthe control circuit controls an input to the integrator so ...

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Номер записи: 94
03-03-2022 дата публикации

ANALOG-TO-DIGITAL CONVERTING DEVICE AND CONTROL SYSTEM

Номер: US20220069832A1
Автор: ENDO Hiroshi
Принадлежит: DENSO WAVE INCORPORATED

An analog-to-digital converting device includes: a main analog-to-digital converter configured to convert an analog signal output from a sensor to a digital signal; and a monitoring unit configured to monitor the digital signal converted by the main analog-to-digital converter. The main analog-to-digital converter is provided by a special purpose IC arranged separately from a microcomputer for controlling the main analog-to-digital converter. The monitoring unit includes multiple sub analog-to-digital converters each of which having a conversion accuracy lower than that of the main analog-to-digital converter and converting the analog signal output from the sensor to a digital signal. The monitoring unit sets a predetermined threshold based on conversion values of the digital signals converted by the multiple sub analog-to-digital converters, and compares a conversion value of the digital signal converted by the main analog-to-digital converter with the predetermined threshold. 1. An analog-to-digital converting device applied to a control system that controls an industrial equipment as a control target , the analog-to-digital converting device comprising:a main analog-to-digital converter configured to convert an analog signal, which is output from a sensor and input to the analog-to-digital converting device, to a digital signal; anda monitoring unit configured to monitor the digital signal converted by the main analog-to-digital converter,whereinthe main analog-to-digital converter is provided by an analog-to-digital conversion purpose integrated circuit arranged separately from a microcomputer that controls the main analog-to-digital converter, and a plurality of sub analog-to-digital converters each of which having a conversion accuracy lower than a conversion accuracy of the main analog-to-digital converter and converting the analog signal, which is output from the sensor and input to the analog-to-digital converting device, to a digital signal;', 'a setting ...

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Номер записи: 95
25-02-2016 дата публикации

Enhanced resolution successive-approximation register analog-to-digital converter and method

Номер: US20160056831A1
Автор: Joonsung Park, Krishnaswamy Nagaraj, Mikel Ash
Принадлежит: Texas Instruments Inc

An enhanced resolution successive-approximation register (SAR) analog-to-digital converter (ADC) is provided that includes a digital-to-analog converter (DAC), a comparator and enhanced resolution SAR control logic. The DAC includes analog circuitry that is configured to convert an M-bit digital input to an analog output. The comparator includes a plurality of coupling capacitors. The enhanced resolution SAR control logic is configured to generate an M-bit approximation of an input voltage and to store a residue voltage in at least one of the coupling capacitors. The residue voltage represents a difference between the input voltage and the M-bit approximation of the input voltage. The enhanced resolution SAR control logic is further configured to generate an N-bit approximation of the input voltage based on the stored residue voltage, where N>M.

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Номер записи: 96
22-02-2018 дата публикации

LOW POWER BUFFER WITH DYNAMIC GAIN CONTROL

Номер: US20180054191A1
Автор: GORECKI James Lawrence, TAN Han-Yuan
Принадлежит:

The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers. 1. A communication system for communication over a receiver channel comprising:a plurality of buffer circuits in the receiver channel, at least some of the plurality of buffer circuits electrically connected to a gain control signal; and a DC signal generator that generates a bias current to set amplitudes of a pair of differential DC biasing signals;', 'a replica buffer having inputs that are electrically connected to the pair of differential DC biasing signals, the replica buffer to serve as a proxy for the plurality of buffer circuits in the receiver channel, and the replica buffer having at least one pair of differential DC output signals; and', 'a double difference amplifier that is electrically connected to the at least one pair of differential DC output signals and to the pair of differential DC biasing signals to produce the gain control signal that is electrically connected to at least some of the plurality of buffer circuits in the receiver channel., 'a DC gain control signal generation circuit comprising2. The communication system of claim 1 ...

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Номер записи: 97
22-02-2018 дата публикации

MULTIPLE SAMPLING STAGE RECEIVER AND RELATED METHODS

Номер: US20180054210A1
Автор: Ali Tamer, Awad Ramy
Принадлежит:

A line receiver including an analog-to-digital converter is described. The line receiver may include an input stage, a first sampling stage, an integration stage, and a second sampling stage. The input stage may be configured to receive an input voltage representative of a signal transmitted by a transmitter, and to convert the input voltage to a current. The input stage may include a trans-conductance stage. The current may be sampled using the first sampling stage. The sampled current may be converted to a voltage using the integration stage. The integration stage may include a trans-impedance stage. The voltage obtained using the integration stage may be sampled using the second sampling stage. 1. A line receiver comprising:an input stage configured to receive an input signal and to generate an intermediate signal;a first sampling stage coupled to the input stage and configured to sample the intermediate signal at a first rate;an integration stage coupled to the first sampling stage and configured to integrate the sampled intermediate signal; anda second sampling stage coupled to the integrator stage and configured to sample the integrated sampled intermediate signal at a second rate,wherein the first sampling stage comprises a plurality of switches configured to sample the intermediate signal at different times and wherein the integration stage comprises a plurality of integrators, each of the plurality of integrators being coupled to a respective switch of the plurality of switches.2. The line receiver of claim 1 , wherein the integration stage comprises an amplifier and a capacitor coupled between an input terminal and an output terminal of the amplifier.3. The line receiver of claim 2 , wherein the input terminal of the amplifier is clamped to a fixed potential.4. The line receiver of claim 2 , wherein the amplifier has a gain that is greater than 1.5. The line receiver of claim 2 , wherein the amplifier has a gain that is greater than or equal to 100.6. The ...

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Номер записи: 98
22-02-2018 дата публикации

SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER (ADC) WITH DYNAMIC SEARCH ALGORITHM

Номер: US20180054211A1
Автор: Ling Curtis, Pullela Raja
Принадлежит:

Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logic modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage. 1. A method of an analog-to-digital converter , comprising:generating a digital reference code;converting the digital reference code to an analog reference voltage;comparing an analog input voltage to the analog reference voltage to obtain a comparison output;updating the digital reference code based on the comparison output; andafter repeating the converting, comparing, and updating up to a predetermined number of times, outputting the digital reference code as a digital output code representative of the analog input voltage, a first bit accuracy when the analog input voltage falls within a first voltage range, and', 'a second bit accuracy different than the first bit accuracy when the analog input voltage falls within a second voltage range., 'wherein the predetermined number of times results in the digital output code representing the analog input voltage to at least2. The method of claim 1 , wherein the predetermined number of times further results in the digital output code representing the analog voltage to at least a third bit accuracy different than the first and second bit accuracies when the analog input voltage falls within a third voltage range.3. The method of claim 1 , wherein:the first bit accuracy corresponds to a 1-LSB (least significant bit) accuracy; andthe second bit accuracy corresponds to a 2-LSB accuracy.4. The method of ...

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Номер записи: 99
15-05-2014 дата публикации

COMPARATOR AND A/D CONVERTER

Номер: US20140132437A1
Автор: Danjo Takumi
Принадлежит: FUJITSU LIMITED

A comparator includes: a differential amplifier of which operational state is switched in response to a clock-signal, and which outputs a first intermediate-output corresponding to a first input-signal and a second intermediate-output corresponding to a second input-signal; a differential latch circuit of which operational state is switched in response to the clock-signal, and a state of which is changed depending on the first intermediate-output and the second intermediate-output; a first adjuster configured to adjust a threshold of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output; and a second adjuster configured to adjust a threshold variation of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output. 1. A comparator , comprising:a differential amplifier of which operational state is switched in response to a clock signal, and which outputs a first intermediate output corresponding to a first input signal and a second intermediate output corresponding to a second input signal;a differential latch circuit of which operational state is switched in response to the clock signal, and a state of which is changed depending on the first intermediate output and the second intermediate output;a first adjuster configured to adjust a threshold of the differential latch circuit with respect to a change of a state of the first intermediate output and a change of a state of the second intermediate output; anda second adjuster configured to adjust a threshold variation of the differential latch circuit with respect to a change of a state of the first intermediate output and a change of a state of the second intermediate output.2. The comparator according to claim 1 , wherein: a latch circuit which includes a first line including a first PMOS transistor and a first NMOS ...

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Номер записи: 100