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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 1128. Отображено 100.
23-08-2012 дата публикации

Soft-decision non-binary ldpc coding for ultra-long-haul optical transoceanic transmissions

Номер: US20120216093A1
Автор: Fatih Yaman, Ivan B. Djordjevic, Lei Xu, Shaoliang Zhang, Ting Wang
Принадлежит: NEC Laboratories America Inc

Methods and systems for soft-decision non-binary low-density parity-check (LDPC) coding for ultra-long-haul optical transoceanic transmissions are provided. A receiver includes one or more maximum a posteriori (MAP) equalizers configured to decode one or more symbols of an encoded input stream to provide one or more symbol log-likelihood ratios (LLRs). One or more LLR estimators are configured to estimate the log-likelihood ratios of the one or more symbol LLRs to provide one or more bit LLRs. One or more non-binary LDPC decoders are configured to decode the input stream using the one or more bit LLRs to recover an original input stream.

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Номер записи: 1
20-09-2012 дата публикации

Method for controlling a basic parity node of a non-binary ldpc code decoder, and corresponding basic parity node processor

Номер: US20120240002A1
Автор: Emmanuel Boutillon, Laura Conde-Canencia
Принадлежит: UNIVERSITE DE BRETAGNE SUD

A method for controlling an elementary parity node of a decoder for decoding non-binary LDPC codes or a code decoder using at least one non-binary parity constraint, and to the corresponding elementary parity node. The elementary parity node receives first and second input lists (U 1 ,U 2 ) having n m elements sorted in ascending or descending order, n m being greater than 1, and gives an output list (U out ) of n m , elements sorted in said ascending or descending order, n m , being greater than 1, each element of the output list (U out ) being the result of a computing operation φ between an element of the first input list (U 1 ) and an element of the second input list (U 2 ). A limited number of candidates is selected for each element of the output list to be generated so as to reduce the number of operations to be carried out in the elementary parity node.

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Номер записи: 2
11-10-2012 дата публикации

Four-dimensional non-binary ldpc-coded modulation schemes for ultra high-speed optical fiber communication

Номер: US20120260142A1
Автор: Ivan B. Djordjevic, Lei Xu, Murat Arabaci, Ting Wang
Принадлежит: NEC Laboratories America Inc

Systems and methods are disclosed for communicating signals, by receiving a K-symbol-long input block from a 2 m -ary source channel; encoding the input block into a 2 m -ary non-binary low-density parity-check (LDPC) codeword of length N; and mapping each 2 m -ary symbol to a point in a signal constellation comprised of 2 m points, wherein a non-binary LDPC code is used as the component code for forward error correction in a coded modulation scheme capable of achieving optical fiber communication at rates beyond 100 Gb/s.

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Номер записи: 3
22-11-2012 дата публикации

Memory controller, semiconductor memory apparatus and decoding method

Номер: US20120297273A1
Автор: Atsushi Takayama, Kenji Sakaue, Tatsuyuki Ishikawa, Yoshihisa Kondo
Принадлежит: Toshiba Corp

A memory controller including a buffer configured to perform decoding frame-unit data decoded by an LDPC decoder through partial parallel processing based on a check matrix made up of a block of a unit matrix and a plurality of blocks in which each row of the unit matrix is sequentially shifted and store threshold decision information of the data read from a memory section, an LLR conversion section configured to convert the threshold decision information to an LLR, an LMEM configured to store probability information β calculated during iteration processing that repeatedly performs column processing and row processing based on the LLR in an iteration unit equal to or smaller than a size of the block, and a CPU core configured to transfer the probability information β stored in the LMEM to the buffer every time the iteration processing in the iteration unit is completed.

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Номер записи: 4
27-12-2012 дата публикации

Systems and Methods for Non-Binary Decoding

Номер: US20120331370A1
Автор: Changyou Xu, Chung-Li Wang, Shaohua Yang, Wu Chang, YANG Han, Zongwang Li
Принадлежит: LSI Corp

Various embodiments of the present invention provide systems and methods for data processing. A data processing circuit is disclosed that includes: a data detector circuit, a first symbol constrained arrangement circuit, and a second symbol constrained arrangement circuit. The data detector circuit is operable to apply a data detection algorithm to a combination of a first input data set and a decoded data set to yield a detected output that includes a number of non-binary symbols. The first symbol constrained arrangement circuit is operable to receive the detected output and to re-arrange the detected output in accordance with a first arrangement algorithm to yield a re-arranged output. The bits for at least one non-binary symbol from the detected output are maintained together in the re-arranged output. The second symbol constrained arrangement circuit is operable to receive a second input data set and to re-arrange the second data input in accordance with a second arrangement algorithm to yield the decoded data set. The bits for at least one non-binary symbol from the second input data set are maintained together in the decoded data set output.

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Номер записи: 5
18-04-2013 дата публикации

LDPC Decoder With Targeted Symbol Flipping

Номер: US20130097475A1
Автор: Chung-Li Wang, Shaohua Yang, Zongwang Li
Принадлежит: LSI Corp

Various embodiments of the present invention provide systems and methods for decoding data in a non-binary LDPC decoder with targeted symbol flipping. For example, a non-binary low density parity check data decoder is disclosed that comprises a variable node processor operable to update variable node symbol values according to a plurality of elements in a non-binary Galois Field, a check node processor connected to the variable node processor and operable to perform parity check calculations, and a controller operable to perform symbol flipping and to control decoding iterations in the variable node processor and the check node processor.

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Номер записи: 6
30-05-2013 дата публикации

Variable Sector Size LDPC Decoder

Номер: US20130139022A1
Автор: Lei Chen, Shaohua Yang, YANG Han, Zongwang Li
Принадлежит: LSI Corp

Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for decoding variably sized blocks of data in an LDPC decoder. For example, in one embodiment an apparatus includes a low density parity check decoder operable to perform decoding of a plurality of circulant sub-matrices from an H matrix, and a controller connected to the low density parity check decoder, operable to omit any of the plurality of circulant sub-matrices from the decoding if they do not contain user data.

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Номер записи: 7
13-06-2013 дата публикации

Systems and Methods for Combined Binary and Non-Binary Data Processing

Номер: US20130148232A1
Автор: Changyou Xu, Chung-Li Wang, Lei Chen, Shaohua Yang, YANG Han, Zongwang Li
Принадлежит: LSI Corp

Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a combination data decoder circuit. The combination data decoder circuit includes: a non-binary data decoder circuit and a binary data decoder circuit.

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Номер записи: 8
04-07-2013 дата публикации

Non-binary qc-ldpc code decoding device and associated method

Номер: US20130173981A1
Автор: Chen-Yap Leong, Chung-Jay Yang, Kuo-Hsuan Liao, Yeong-Luh Ueng
Принадлежит: National Tsing Hua University NTHU

A non-binary quasi-cyclic (QC) low-density parity-check (LDPC) code decoding device comprises a first barrel-shifter, a routing network and a second barrel-shifter. The first barrel-shifter uses a constraint h′v′+h″v″=hv to shift q−1 elements of an input by j 0 positions to produce first temporary elements. The routing network connects to the first barrel-shifter, permutes the first temporary elements to produce second temporary elements if v′ of the constraint is not zero and designates the first temporary elements as the second temporary elements if v′ of the constraint is zero. The second barrel-shifter connects to the routing network and uses the constraint h′v′+h″v″=hv to shift q−1 elements of the second temporary elements by i 0 positions. A non-binary QC-LDPC decoding method is also disclosed.

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Номер записи: 9
01-08-2013 дата публикации

Symbol Flipping Data Processor

Номер: US20130198580A1
Автор: Haitao Xia, Johnson Yen, Lei Chen, Ming Jin
Принадлежит: LSI Corp

Various embodiments of the present invention provide systems and methods for a symbol flipping data processor. For example, a symbol flipping data processor is disclosed that includes a data decoder in the symbol flipping data processor operable to perform error checking calculations, and a data detector in the symbol flipping data processor operable to perform symbol flipping in the data detector based at least in part on the error checking calculations, wherein the output of the data processor is generated at least in part based on the symbol flipping in the data detector.

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Номер записи: 10
15-08-2013 дата публикации

Reduced complexity non-binary ldpc decoding algorithm

Номер: US20130212451A1
Автор: Majid NEMATI ANARAKI, Richard D. Barndt, Xinde Hu
Принадлежит: Stec Inc

A custom decoding algorithm is introduced, in connection with a corresponding decoding structure, to resolve many complexity and large memory requirements of known decoders. A system. A variable node forms a confidence vector of four components, one component for each state of a memory cell, and passes the current primary component (e.g., the largest) to one or more check nodes. The check nodes calculate a temporary component and corresponding index based on all components received from the variable nodes, which they pass back to the respective variable nodes. The variable node updates the confidence vector based on the temporary nodes received from respective check nodes, and determines the correct state for corresponding memory cell based on which component in the confidence vector is currently the primary component.

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Номер записи: 11
26-09-2013 дата публикации

Parallel encoding for non-binary linear block code

Номер: US20130254639A1
Автор: Hai-Jo Tarn, Kalyana Krishnan
Принадлежит: Xilinx Inc

An encoder module includes P/L parity shift registers that are sequentially coupled, wherein an input of a first parity shift register of the parity shift registers is coupled to the input of the encoder module, an output of the last parity shift register of the parity shift registers is coupled to the output of the encoder module, each of the parity shift registers being configured to store L parity digits. The encoder module also includes a feedback circuit comprising P/L parity generation modules, wherein each of the parity generation modules is coupled to an output of a corresponding one of the parity shift registers by a switch and also coupled to the input of the first parity shift register, wherein each of the parity generation modules is configured to generate L parity digits for transmission to the input of the first parity shift register when its corresponding switch is closed.

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Номер записи: 12
31-10-2013 дата публикации

Method and System For Error Correction in Flash Memory

Номер: US20130290813A1
Автор: Aditya Ramamoorthy, Pantas Sutardja, Zining Wu
Принадлежит: MARVELL WORLD TRADE LTD

A controller is described for a multi-level, solid state, non-volatile memory array having memory cells. The memory cells are configured to store data using a first number of digital levels. The controller is configured to encode multiple data bits to generate multiple encoded data bits, convert the multiple encoded data bits into multiple data symbols, and send the multiple data symbols for storage in a memory cell of the multi-level, solid state, non-volatile memory array. The controller is further configured to generate an output signal, using a second number of digital levels, based on data associated with the multiple data symbols stored in the memory cell. The second number of digital levels is greater than the first number of digital levels used to store the multiple data symbols in the memory cell. The controller is further configured to output multiple output data symbols based on the output signal.

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Номер записи: 13
21-11-2013 дата публикации

Systems and methods for non-binary ldpc encoding

Номер: US20130311845A1
Автор: Fan Zhang, Shaohua Yang, Zongwang Li
Принадлежит: LSI Corp

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data encoding.

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Номер записи: 14
19-12-2013 дата публикации

Updating variable nodes associated with an iterative decoder

Номер: US20130339817A1
Автор: Zion S. Kwok
Принадлежит: Individual

Embodiments of the present disclosure describe device, methods, computer-readable media and system configurations for data decoding and/or error correction. In various embodiments, an iterative decoder may compute, from sign bits of log likelihood ratios associated with x bits of a plurality of bits of encoded data, a first combination of the x bits having a higher associated log density ratio than any other combination of the x bits. In various embodiments, the iterative decoder may further be configured to compute m combinations of the x bits having m highest associated log density ratios, based on reductions in log density ratios associated with one or more sub-combinations of the x bits and the computed first combination of the x bits. In various embodiments, a variable node associated with the iterative decoder may be updated with the m combinations of the x bits. Other embodiments may be described and/or claimed.

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Номер записи: 15
26-12-2013 дата публикации

Processing elementary check nodes of an iterative ed transmitter appar

Номер: US20130346833A1
Автор: Zion S. Kwok
Принадлежит: Intel Corp

Embodiments of the present disclosure describe devices, apparatus, methods, computer-readable media and system configurations for processing elementary check nodes associated with an iterative decoder in a manner that conserves computing resources. In various embodiments, first and second sets of m tuples may be received, e.g., as input for the elementary check node. Each tuple may include a symbol and a probability that the symbol is correct, and the first and second sets of m tuples may be sorted by their respective probabilities. In various embodiments, less than all combinations of the first and second sets of m tuples may be computed for consideration as output of the elementary check node, and some computed combinations may be eliminated from consideration as output. In various embodiments, the elementary check node may output a set of m output tuples with the highest probabilities. Other embodiments may be described and/or claimed.

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Номер записи: 16
02-01-2014 дата публикации

Systems and Methods for Enhanced Bit Correlation Usage

Номер: US20140006894A1
Автор: Fan Zhang
Принадлежит: LSI Corp

The present invention is related to systems and methods for applying a data decode algorithm to different rotations or modifications of a decoder input as part of data processing.

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Номер записи: 17
01-01-2015 дата публикации

METHOD FOR TRANSMITTING NON BINARY ERROR CORRECTING CODE WORDS WITH CCSK MODULATION, AND CORRESPONDING SIGNAL AND DEVICE

Номер: US20150003499A1
Автор: Abassi Oussama, Boutillon Emmanuel, Conde-Canencia Laura
Принадлежит:

The invention concerns a method for transmitting symbols of non binary error correcting code words via a transmission channel. The method comprises a first modulation associating each code word symbol of p bits with a sequence of at leas 2p chips from 2p possible sequences a second modulation to modulate the phase or amplitude of a carrier signal with the sequences associated with the code words, and a step of transmitting the modulated carrier signal via said transmission channel. According to the invention the first modulation is a spread spectrum modulation of the cyclic code shift keying type using a basic pseudo-random sequence of at least 2p chips, the possible 2p sequences being obtained by a circular shift of the basic pseudo-random sequence and a cyclic prefix is inserted into each symbol to be transmitted. 14-. (canceled)5. A method for transmitting symbols of non-binary error-correcting code words via a transmission channel , each code word symbol comprising p bits , said method comprising{'sup': p', 'p, 'a first modulation step associating each p-bit code word symbol with sequence of at least 2chips from 2possible sequences,'}a second modulation step to modulate the phase or amplitude of at least one carrier signal with the sequences associated with the code words, anda transmission step for transmitting the modulated carrier signal via said transmission channel,{'sup': p', 'p, 'wherein the first modulation step is a spread spectrum modulation of the cyclic code-shift keying type using a basic pseudo-random sequence of at least 2chips, the 2possible sequences being obtained by a circular shift of the basic pseudo-random sequence, and wherein the method further comprises, after said second modulation step, a step of inserting a cyclic prefix into each symbol to be transmitted.'}6. A device for transmitting symbols of non-binary error-correcting code words via a transmission channel , each code word symbol comprising p bits , said device , comprising{'sup ...

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Номер записи: 18
02-01-2020 дата публикации

Storage drive error-correcting code-assisted scrubbing for dynamic random-access memory retention time handling

Номер: US20200004624A1
Автор: Shu Li
Принадлежит: Alibaba Group Holding Ltd

encoding, at the storage device, the data with a second encoding to generate a second parity portion; aligning, by the storage device, the data, the first parity portion, and the second parity portion according to a predefined alignment scheme, the aligning generating aligned data; and writing, by the storage device, the aligned data to the memory device.

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Номер записи: 19
13-01-2022 дата публикации

TWO-LEVEL ERROR CORRECTING CODE WITH SHARING OF CHECK-BITS

Номер: US20220014213A1
Автор: LU Shih-Lien Linus
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A memory device includes: a memory device configured to store data bits to be written to the memory device; and a memory controller. The memory controller includes: a first level error correction code (ECC) circuit coupled to the memory device, wherein the first level ECC circuit is configured to generate a first plurality of first level check bits corresponding to the data bits based on a first error detection scheme; and a second level ECC circuit coupled to the memory device, wherein the second level ECC circuit is configured to generate a second plurality of second level check bits corresponding to both the data bits and the first plurality of first level check bits based on a first error correction scheme. 1. A method of operating a memory controller coupled to a memory device , comprising:generating a first plurality of first level check bits corresponding to data bits to be written to the memory device based on a first error detection scheme; andgenerating a second plurality of second level check bits corresponding to both the data bits and the first plurality of first level check bits based on a first error correction scheme.21. The method of , further comprising:storing the data bits in the memory device.32. The method of , further comprising:storing the first plurality of first level check bits and the second plurality of second level check bits in the memory device.43. The method of , further comprising:reading the stored data bits;reading the first plurality of first level check bits; andcalculating a first plurality of syndromes based on the stored data bits and the first plurality of first level check bits.54. The method of , further comprising:if any of the first plurality of syndromes is not equal to zero, correcting the stored data bits based on the stored data bits, the first plurality of first level check bits, and the second plurality of second level check bits by using the first error correction scheme.61. The method of , further comprising: ...

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Номер записи: 20
04-01-2018 дата публикации

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 4/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

Номер: US20180006663A1
Автор: HUR Nam-Ho, KIM Heung-Mook, KWON Sun-Hyoung, PARK Sung-Ik
Принадлежит:

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). 2. The LDPC encoding method of claim 1 , wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 17280 claim 1 , a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 1800 claim 1 , and a second parity part corresponding to an identity matrix included in the PCM and having a length of 45720.3. The LDPC encoding method of claim 2 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part claim 2 , that is claim 2 , 17280 claim 2 , by a circulant permutation matrix (CPM) size corresponding to the PCM claim 2 , that is claim 2 , 360 claim 2 , and a value obtained by dividing a length of the first parity part claim 2 , that is claim 2 , 1800 claim 2 , by the CPM size.4. The LDPC encoding method of claim 3 , wherein the accumulation is performed at parity bit addresses that are updated using the sequence.5. The LDPC encoding method of claim 4 , wherein the accumulation is performed while the rows of the sequence are being repeatedly changed by the CPM size of the PCM. This application is a continuation of U.S. patent application Ser. No. 14/496,654, filed on Sep. 25, 2014, which claims the benefit of Korean Patent Application Nos. 10-2014-0106180 and 10-2014-0120014, filed Aug. 14, 2014 and Sep. 11, 2014, respectively, which are hereby incorporated by reference herein in their entirety.The present ...

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Номер записи: 21
03-01-2019 дата публикации

DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD

Номер: US20190007061A1
Автор: Shinohara Yuji, Yamamoto Makiko
Принадлежит: SATURN LICENSING LLC

A data processing apparatus and a data processing method which enable provision of an LDPC code that achieves good error-rate performance. An LDPC encoding unit performs encoding using an LDPC code having a code length of 64800 bits and a code rate of 24/30, 25/30, 26/30, 27/30, 28/30, or 29/30. The LDPC code includes information bits and parity bits, and a parity check matrix H is composed of an information matrix portion corresponding to the information bits of the LDPC code, and a parity matrix portion corresponding to the parity bits. The information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table that shows positions of elements of 1 in the information matrix portion in units of 360 columns. The present technology apparatus and method may be applied to LDPC encoding and LDPC decoding. 1an encoding unit configured to encode information bits into an LDPC (Low Density Parity Check) code having a code length of 64800 bits and a code rate of 24/30 on the basis of a parity check matrix of the LDPC code, whereinthe LDPC code includes information bits and parity bits,the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,the information matrix portion is represented by a parity check matrix initial value table, andthe parity check matrix initial value table is a table showing positions of elements of 1 in the information matrix portion in units of 360 columns, including{'b': 1504', '2103', '2621', '2840', '3869', '4594', '5246', '6314', '7327', '7364', '10425', '11934', '12898', '12954}{'b': 27', '1903', '3923', '4513', '7812', '8098', '8428', '9789', '10519', '11345', '12032', '12157', '12573', '12930}{'b': 17', '191', '660', '2451', '2475', '2976', '3398', '3616', '5769', '6724', '8641', '10046', '11552', '12842}{'b': 13', '1366', '4993', '6468', '7689', '8563', '9131', '10012', '10914', '11574', '11837', ' ...

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Номер записи: 22
12-01-2017 дата публикации

METHOD FOR DECODING NON-BINARY CODES AND CORRESPONDING DECODING APPARATUS

Номер: US20170012642A1
Автор: Declercq David, Garcia Herrero Francisco Miguel, Li Erbao, Valls Coquillat Javier
Принадлежит:

An extension to the enhanced serial generalized bit-flipping decoding algorithm (ES-GBFDA) of non-binary LDPC codes by introducing soft information in the check node operation. The application not only considers the most reliable symbol in the syndrome computation, but also takes at least the second most reliable symbol of each incoming message into account. An extended information set is available for the parity-check node update and this allows introducing the concept of weak and strong votes performed by the check node unit. Each variable node can receive two kinds of votes, whose amplitudes can be tuned to the reliability of the syndrome that produces the vote. 1. A method for decoding a non-binary low density parity-check (NB-LDPC) code defined in a finite field of size q , which is a symbol flipping decoding method using multiple votes performed by the check node unit and transferred to the variable node unit ,{'sub': n', 'm', 't, 'claim-text': [{'sub': n', 'm', 'n', 'n', 'c, 'sup': 1(j)', 'th', 'p(j), 'each variable node V, connected to a check node C, is configured for determining (A1.1, A1.2) a most reliable symbol Qand at least one symbol which is at least a pmost reliable symbol Q, with p≧2 for obtaining a vector of dmost reliable symbols;'}, {'sub': 'm', 'claim-text': [{'sub': n', 'n', 'c, 'sup': 0(j)', '(j), '(A3.1) a first symbol to be voted R=Rbased on the vector of dmost reliable symbols passed by the variable nodes connected to him in the bipartite graph;'}, {'sub': n', 'c', 'c', 'n', 'c', 'c', 'n, 'sup': i(j)', 'th', 'p(j)', '1(j), '(A3.2) a list of i=1, . . . , L second symbols to be voted Rbased on a list of L+1 test vectors defined as a combination of dsymbols with a restriction according to which at most η of these dsymbols are a pmost reliable symbol Qwith p≧2, and at least d−η of these dsymbols are a most reliable symbol Q.'}], 'each check node Cis configured for determining], 'the code can be displayed in a bipartite graph comprising at ...

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Номер записи: 23
12-01-2017 дата публикации

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 2/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

Номер: US20170012645A1
Автор: HUR Nam-Ho, KIM Heung-Mook, KWON Sun-Hyoung, PARK Sung-Ik
Принадлежит:

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). 2. The LDPC encoding method of claim 1 , wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 8640 claim 1 , a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 1800 claim 1 , and a second parity part corresponding to an identity matrix included in the PCM and having a length of 54360.3. The LDPC encoding method of claim 2 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part claim 2 , that is claim 2 , 8640 claim 2 , by a circulant permutation matrix (CPM) size corresponding to the PCM claim 2 , that is claim 2 , 360 claim 2 , and a value obtained by dividing a length of the first parity part claim 2 , that is claim 2 , 1800 claim 2 , by the CPM size.4. The LDPC encoding method of claim 3 , wherein the accumulation is performed at parity bit addresses that are updated using the sequence.5. The LDPC encoding method of claim 4 , wherein the accumulation is performed while the rows of the sequence are being repeatedly changed by the CPM size of the PCM. This application is a continuation of U.S. patent application Ser. No. 14/496,457, filed on Sep. 25, 2014, which claims the benefit of Korean Patent Application Nos. 10-2014-0106178 and 10-2014-0120012, filed Aug. 14, 2014 and Sep. 11, 2014, respectively, which are hereby incorporated by reference herein in their entirety.1. Technical FieldThe ...

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Номер записи: 24
14-01-2016 дата публикации

PARITY CHECK MATRIX GENERATING METHOD, ENCODING APPARATUS, ENCODING METHOD, DECODING APPARATUS AND DECODING METHOD USING THE SAME

Номер: US20160013809A1
Автор: Jeong Hong-Sil, MYUNG Se-Ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A method of low density parity check (LDPC) encoding includes: receiving a plurality of information word bits; LDPC encoding the information word bits using a parity check matrix in which a sum of elements in same positions in a plurality of groups constituting the parity check matrix is less than 2; and generating LDPC codeword bits comprising the information word bits and parity bits as a result of the LDPC encoding, wherein each of the plurality of groups constituting comprises a same number of columns. 1. A method of low density parity check (LDPC) encoding , the method comprising:receiving a plurality of information word bits;LDPC encoding the information word bits using a parity check matrix in which a sum of elements in same positions in a plurality of groups constituting the parity check matrix is less than 2; andgenerating LDPC codeword bits comprising the information word bits and parity bits as a result of the LDPC encoding,wherein each of the plurality of groups constituting comprises a same number of columns.2. The method of claim 1 , wherein a number of the plurality of groups is an integer multiple of a number of bits constituting a modulation symbol to be generated from the LDPC codeword bits.3. The method of claim 2 , wherein bits among the LDPC codeword bits corresponding to different parity check equations constitute the modulation symbol claim 2 , andwherein each of the parity check equations is formed of bits corresponding to columns where 1 exists in a row in the parity check matrix.4. The method of claim 3 , wherein the bits constituting the modulation symbol are separated by a same predetermined interval in the LDPC codeword bits.5. The method of claim 1 , further comprising generating the parity check matrix by:performing row permutation and column permutation on a preset parity check matrix;dividing the parity check matrix, on which the row permutation and the column permutation are performed, into the plurality of groups according to a ...

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Номер записи: 25
11-01-2018 дата публикации

METHOD AND SYSTEM FOR LDPC DECODING

Номер: US20180013446A1
Автор: Gulak Glenn, Milicevic Mario
Принадлежит:

A Low-Density Parity-Check (LDPC) decoder and a method for LDPC decoding are provided. The LDPC decoder receives a soft-decision input codeword block in which the probability of a bit being a “0” or a “1” is represented as a log-likelihood ratio (LLR). During LDPC decoding, a sequence of hardware logic units iteratively updates the soft-decision input codeword block until a valid codeword is found or a maximum number of decoding iterations is reached. Each hardware logic unit comprises a check node (CN) update logic unit and a variable node (VN) update logic unit. The CN update logic units are coupled via a closed CN path, and the VN update logic units are coupled via a closed VN path. Aspects of this LDPC decoder alleviate the global routing and energy efficiency challenges of traditional LDPC decoders, to enable multi-rate, multi-Gb/s decoding without compromising error correction performance in next-generation systems and future CMOS technology nodes. 1. A method for Low-Density Parity-Check (LDPC) decoding , the method comprising:receiving a soft-decision input codeword block, wherein the probability of a bit being a “0” or a “1” is represented in the soft-decision input codeword block as a log-likelihood ratio (LLR); anditeratively updating the soft-decision input codeword block, by a sequence of hardware logic units, until a valid codeword is found or a maximum number of decoding iterations is reached, wherein each decoding iteration comprises a check node (CN) phase followed by a variable node (VN) phase, generating a CN-to-VN message,', 'generating an intermediate LLR and a VN-to-CN message according to the CN-to-VN message, and', 'storing the VN-to-CN message in a memory for use during the CN phase in a next iteration,, 'wherein each hardware logic unit of the sequence of hardware logic units operates in series during the CN phase, therebywherein each hardware logic unit of the sequence of hardware logic units operates in series during the VN phase, thereby ...

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Номер записи: 26
14-01-2021 дата публикации

TECHNIQUES TO IMPROVE ERROR CORRECTION USING AN XOR REBUILD SCHEME OF MULTIPLE CODEWORDS AND PREVENT MISCORRECTION FROM READ REFERENCE VOLTAGE SHIFTS

Номер: US20210013903A1
Автор: Kwok Zion S., MOTWANI RAVI H., VANAPARTHY Santhosh K.
Принадлежит:

Examples include techniques to improve error correction using an exclusive OR (XOR) rebuild scheme that includes two uncorrectable codewords. Examples include generation of soft XOR codewords using bits of correctable codewords to rebuild a codeword read from a memory that has uncorrectable errors and adjust bit reliability information to generate a new codeword having correctable errors. Examples also include techniques to prevent mis-correction due to read reference voltage shifts using non-linear transformations. 1. An apparatus comprising: receive address information for error correction code (ECC) codewords, the address information indicating addresses where the ECC codewords are to be written to a memory by a controller of a memory device;', 'apply an exclusive OR (XOR) or exclusive NOR (XNOR) operation to address information that is not stored in the memory or apply a non-linear transformation function to the addresses where the ECC codewords are to be written;', 'provide the address information to an ECC encoder of the controller for the ECC encoder to calculate ECC parity for respective ECC codewords, wherein the ECC encoder is to generate an additional ECC codeword to be written to memory, data for the additional ECC codeword is a bitwise XOR or XNOR of the ECC codewords to be written to the memory in an XOR stripe;', 'receive address information associated with reading the ECC codewords from the memory;', 'provide the address information to an ECC decoder of the controller for the ECC decoder to decode the ECC codewords read from the memory; and', 'check whether or not the address information obtained from decoded ECC codewords matches expected address information for the decoded ECC codewords., 'circuitry to2. The apparatus of claim 1 , the circuitry to implement the non-linear transformation further comprises the circuitry to:input the address information to the non-linear transformation function to output transformed address information bits;provide ...

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Номер записи: 27
15-01-2015 дата публикации

ERROR CORRECTING DECODING APPARATUS FOR DECODING LOW-DENSITY PARITY-CHECK CODES

Номер: US20150019931A1
Автор: MAEHATA Takashi
Принадлежит: Sumitomo Electric Industries, Ltd.

A decoder applies decode processing to N input data in parallel to generate K decode data. An S/P converter outputs N input data applied in series to decoder through first lines L-L dividedly over several times. A P/S converter receives through second lines R-R the K decode data from decoder dividedly over several times to output in series the K decoded data to an external source. 19-. (canceled)10. An error correcting decoding apparatus for performing decoding in units of code length N , comprising:a first storage unit for storing N input data constituting a code with a code length N;a decoder; andB1 first lines connecting the first storage unit with the decoder, where B1 is a natural number of at least 2 and less than the code length N, wherein: 'the decoder decodes the N input data constituting a code with a code length N, which are provided from the first storage unit, in parallel.', 'the first storage unit provides the stored N input data constituting a code with a code length N to the decoder through the B1 first lines dividedly over several times, a parallel number of input data provided in each time is up to B 1,'}11. The error correcting decoding apparatus according to claim 10 , wherein:the first storage unit includes B1 dual port memories, each having one input and one output,the B1 dual port memories store the N input data constituting a code with a code length N, andthe B1 dual port memories and the B1 first lines are connected in a one-to-one correspondence.12. The error correcting decoding apparatus according to claim 10 , wherein:the first storage unit includes B1 dual port memories, each having one input and one output,each dual port memory stores in duplication the N input data constituting a code with a code length N,the B1 dual port memories and the B1 first lines are connected in a one-to-one correspondence, andeach dual port memory outputs data among the N input data constituting a code with a code length N, differing from each other.13. The ...

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Номер записи: 28
18-01-2018 дата публикации

JOINT DE-DUPLICATION-ERASURE CODED DISTRIBUTED STORAGE

Номер: US20180018235A1
Автор: Arslan Suayb S., Goker Turguy, Wideman Roderick B.
Принадлежит:

Methods and apparatus deduplicate and erasure code a message in a data storage system. One example apparatus includes a first chunking circuit that generates a set of data chunks from a message, an outer precoding circuit that generates a set of precoded data chunks and a set of parity symbols from the set of data chunks, a second chunking circuit that generates a set of chunked parity symbols from the set of parity symbols, a deduplication circuit that generates a set of deduplicated data chunks by deduplicating the set of precoded chunks or the set of chunked parity symbols, an unequal error protection (UEP) circuit that generates an encoded message from the set of deduplicated data chunks, and a storage circuit that controls the data storage system to store the set of deduplicated data chunks, the set of parity symbols, or the encoded message. 1. A non-transitory computer-readable storage device storing computer executable instructions that when executed by a computer control the computer to perform a method for deduplicating and erasure coding a message , the method comprising:accessing the message,generating a set of message chunks by chunking the message using a first chunking approach;generating a set of outer-precoded parity symbols and a set of outer-precoded data symbols from the set of message chunks using an outer precode;storing the set of outer-precoded parity symbols in a data storage system;generating a set of unique data symbols by deduplicating the set of outer-precoded data symbols based, at least in part, on a chunk identification (ID) table, where the chunk ID table stores a unique chunk ID associated with a unique data symbol stored in the data storage system, a chunk size associated with the unique data symbol, or a chunk reference count associated with the unique chunk ID, where the chunk ID table is stored in a data storage device with a faster access time than the data storage system;storing a copy of the set of unique data symbols in the ...

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Номер записи: 29
03-02-2022 дата публикации

OFFSET VALUE DETERMINATION IN A CHECK NODE PROCESSING UNIT FOR MESSAGE-PASSING DECODING OF NON-BINARY CODES

Номер: US20220038116A1
Автор: Boutillon Emmanuel, HARB Hassan, MARCHAND Cédric
Принадлежит: UNIVERSITE DE BRETAGNE SUD

Embodiments of the invention provide an elementary check node processing unit () implemented in a check node processing unit of a non-binary error correcting code decoder, the elementary check node processing unit () being linked to a variable node processing unit () and being configured to receive a first message and a second message, each message comprising at least two components. The elementary check node processing unit () comprises a calculation unit () which determines two or more auxiliary components from the components comprised in the first message and from the components comprised in the second message, an auxiliary component comprising an auxiliary reliability metrics. The calculation unit () also determines, in association with each of the two or more auxiliary components, decoding performance values. The elementary check node processing unit () also comprises a selection unit () which selects, among the two or more auxiliary components, the auxiliary component that is associated with the optimal decoding performance values and determines an offset value from the auxiliary reliability metrics comprised in the selected auxiliary component. The elementary check node processing unit () then transmits the offset value and a selected set of auxiliary components among the two or more auxiliary components to the variable node processing unit (). 2. The elementary check node processing unit of claim 1 , wherein said decoding performance values comprise a bit error rate evaluated for a given signal-to-noise ratio.3. The elementary check node processing unit of claim 1 , wherein said first message comprises a first predefined number of components and said second message comprises a second predefined number of components claim 1 , each component of the first message and of the second message comprising a symbol and a reliability metrics associated with said symbol claim 1 , the calculation unit being configured to determine each auxiliary component among said ...

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Номер записи: 30
26-01-2017 дата публикации

METHOD AND APPARATUS FOR A VOLUME MANAGEMENT SYSTEM IN A NON-VOLATILE MEMORY DEVICE

Номер: US20170024277A1
Автор: Wong Wanmo
Принадлежит: MICRON TECHNOLOGY, INC.

Embodiments for partitioning a non-volatile memory device is described. In one embodiment a memory system includes a first addressable range of memory blocks for storing different types of data. The memory system is partitioned to include a second addressable range of memory blocks capable of storing data indicating attributes of the first addressable range of memory blocks. The second addressable range of memory blocks may also be periodically updated such that the capacities of the first addressable range of memory blocks may be dynamically adjusted depending on application needs and changes to the non-volatile memory device over time In some embodiments, one partition of a memory device may be configured for high reliability data storage while a second partition is configured for normal reliability storage. 1. A system comprising:a memory array of multi-level memory cells;a first addressable range of memory blocks of the memory array, the first addressable range of memory blocks configured as single level memory cells, and further configured to store read data, the first addressable range comprising a first error correcting code (“ECC”) to correct errors in the read data;a second addressable range of memory blocks of the memory array, the second addressable range of memory blocks configured to store user data, the second addressable range comprising a second ECC to correct errors in the user data; and store first device information regarding the first addressable range and second device information regarding the second addressable range, wherein a partition size of the first addressable range and the second addressable range are included the first and second device information; and', 'track an update to the first device information and the second device information according to a block map including partition information regarding the first addressable range and the second addressable range, and, 'a third addressable range of memory blocks of the memory array, ...

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Номер записи: 31
25-01-2018 дата публикации

Ldpc decoder, semiconductor memory system and operating method thereof

Номер: US20180026658A1
Автор: In-Cheol Park, Jaehwan Jung
Принадлежит: Korea Advanced Institute of Science and Technology KAIST, SK hynix Inc

An operation method of a LPC decoder includes: initializing variable nodes of a Tanner graph representing a parity check matrix; performing a check node update to check nodes of the Tanner graph based on variable node values of the variable nodes; performing a variable node update when there are USC nodes among the updated check nodes as a result of the check node update; and repeating the performing of the check node update and the variable node update when there are USC nodes as the result of the check node update, wherein the performing of the variable node update includes: selecting among the variable nodes a predetermined number of variable nodes having a USC value greater than a threshold; and flipping the variable node values of the selected variable nodes, and wherein the USC value is a number of the USC nodes linked to one of the variable nodes.

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Номер записи: 32
10-02-2022 дата публикации

TRANSMITTER AND PARITY PERMUTATION METHOD THEREOF

Номер: US20220045695A1
Автор: Jeong Hong-Sil, KIM Kyung-Joong, MYUNG Se-Ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a parity permutator configured to perform parity permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups including the interleaved parity bits; and a puncturer configured to select some of the parity bits in the group-wise interleaved bit groups, and puncture the selected parity bits, wherein the parity permutator group-wise interleaves the bit groups such that some of the bit groups are positioned at predetermined positions, respectively, and a remainder of the bit groups are positioned without an order within the group-wise interleaved bit groups so that the puncturer selects parity bits included in the some of the bit groups positioned at the predetermined positions sequentially and selects parity bits included in the remainder of the bit groups without an order. 2. The receiving method of claim 1 , wherein the transmitting apparatus encodes 6480 information bits according to the code rate of 6/15 to generate 9720 parity bits.3. The receiving apparatus of claim 1 , wherein the plurality of groups comprise 45 groups including 0to 44groups.5. The transmitting method of claim 4 , wherein the encoding comprises encoding 6480 information bits based on the code rate of 6/15 to generate 9720 parity bits. This application is a continuation of U.S. application Ser. No. 16/390,393, filed on Apr. 22, 2019, which is a continuation of U.S. application Ser. No. 15/058,318, filed on Mar. 2, 2016, which claims priority from Korean Patent Application No. 10-2015-0137185, filed on Sep. 27, 2015, and U.S. Provisional Application No. 62/127,056, filed on Mar. 2, 2015, the disclosures of which are incorporated herein in by reference in their entireties.Apparatuses and methods consistent with the exemplary embodiments of the inventive concept relate to a transmitter and a parity permutation ...

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Номер записи: 33
24-01-2019 дата публикации

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

Номер: US20190028122A1
Автор: IKEGAYA Ryoji, Shinohara Yuji, Yamamoto Makiko
Принадлежит: SATURN LICENSING LLC

The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 64800 bits and an encoding rate r is 7/15, 9/15, 11/15, or 13/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code. 1. A method for generating a digital television broadcast signal , and for decreasing a signal-to-noise power ratio of the generated digital television broadcast signal , the method comprising:receiving data to be transmitted in a digital television broadcast signal; wherein the LDPC code word includes information bits and parity bits, the parity bits being processed by the receiving device to recover information bits corrupted by transmission path errors,', 'the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,', 'the information matrix portion is represented by a parity check matrix initial value table, and', 'the parity check matrix initial value table, having each row indicating positions of elements ‘1’ in corresponding 360 columns of the information matrix portion as a subset of information bits used in calculating the parity bits in the LDPC encoding, is as follows, 'performing low density parity check (LDPC) encoding in an LDPC encoding circuitry, on input bits of the received data according to a parity check matrix of an LDPC code having a code length N of 64800 bits and an encoding rate r of 9/15 to generate an LDPC code word, the LDPC code enabling error correction processing to correct errors generated in a transmission path of ...

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Номер записи: 34
28-01-2021 дата публикации

Memory Controller and Method for Decoding Memory Devices with Early Hard-Decode Exit

Номер: US20210028795A1
Автор: Graumann Peter John Waldemar
Принадлежит: Microchip Technology Inc.

A method and apparatus for decoding are disclosed. The method includes receiving a first Forward Error Correction (FEC) block of read values, starting a hard-decode process in which a number of check node failures is identified and, during the hard-decode process comparing the identified number of check node failures to a decode threshold. When the identified number of check node failures is not greater than the decode threshold the hard-decode process is continued. When the identified number of check node failures is greater than the decode threshold, the method includes: stopping the hard-decode process prior to completion of the hard-decode process; generating output indicating that additional reads are required; receiving one or more additional FEC blocks of read values, mapping the first FEC block of read values and the additional FEC blocks of read values into soft-input values; and performing a soft-decode process on the soft-input values. 1. A method for decoding comprising:receiving a first Forward Error Correction (FEC) block of read values at a hard-input decode circuit, each bit of the first FEC block of read values representative of a corresponding bit of a stored FEC block;starting a hard-decode process by the hard-input decode circuit, the hard-decode process including variable node processing and check node processing on the first FEC block of read values to identify a number of check node failures;during the hard-decode process, comparing the identified number of check node failures to a decode threshold;when the identified number of check node failures is not greater than the decode threshold, continuing the hard-decode process by the hard-input decode circuit; stopping the hard-decode process prior to completion of the hard-decode process;', 'generating output indicating that additional reads are required;', 'receiving at a mapper the first FEC block of read values and one or more additional FEC blocks of read values, each bit of each of the one ...

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Номер записи: 35
04-02-2016 дата публикации

Method and apparatus for transmitting/receiving data in wireless communication system supporting non-binary channel code

Номер: US20160036609A1
Автор: Chi-Woo Lim, Min SAGONG, Seok-Ki Ahn, Sung-Nam Hong, Woo-Myoung PARK
Принадлежит: SAMSUNG ELECTRONICS CO LTD

The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-Generation (4G) communication system such as a Long Term Evolution (LTE). A method for transmitting data in a transmitting apparatus in a wireless communication system supporting a non-binary channel code is provided. The method includes generating at least one modulation symbol by modulating at least one code symbol based on a predetermined modulation scheme; and transmitting the at least one modulation symbol to a receiving apparatus, wherein the generating of the at least one modulation symbol comprises generating the at least one modulation symbol from the at least one code symbol to thereby reduce a number of complex modulation symbols generated from a plurality of code symbols.

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Номер записи: 36
01-02-2018 дата публикации

NON-BINARY ENCODING FOR NON-VOLATILE MEMORY

Номер: US20180034479A1
Автор: Galbraith Richard Leo, Goode Jonas Andrew, Ravindran Niranjay
Принадлежит:

A data storage system and method are provided for storing data in non-volatile memory devices. Binary data is received for storage in a non-volatile memory device. The binary data is converted into non-binary data comprising base-X values, where X is an integer greater than two. The non-binary data is encoded to generate a codeword and the codeword is written to a wordline of the non-volatile memory device. 1. A method , comprising:receiving binary data for storage in a non-volatile memory device;converting the binary data into non-binary data;encoding the non-binary data to generate a codeword; andwriting the codeword to a wordline of the non-volatile memory device.2. The method of claim 1 , wherein converting the binary data into non-binary data comprises converting base-two values of the binary data into base-X values claim 1 , where X is an integer greater than two.3. The method of claim 2 , wherein X is a non-power-of-two integer.4. The method of claim 2 , wherein writing the codeword in the wordline of the non-volatile memory device comprises programming memory cells of the wordline to respective program levels selected from X available program levels based on values of the non-binary data.5. The method of claim 1 , wherein encoding the non-binary data comprises generating a non-binary low-density parity-check (LDPC) code claim 1 , andwherein the generated codeword comprises the non-binary data and the non-binary LDPC code.6. The method of claim 1 , further comprising:reading the codeword from the wordline of the non-volatile memory device;decoding the codeword to retrieve the non-binary data; andconverting the non-binary data back into the binary data.7. A data storage system claim 1 , comprising:a plurality of non-volatile memory devices; and receive first binary data for storage in the data storage system;', 'convert base-two values of the first binary data into first non-binary data comprising base-X values, where X is an integer greater than two;', ' ...

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Номер записи: 37
01-02-2018 дата публикации

METHOD FOR PROCESSING DATA BLOCK IN LDPC ENCODER

Номер: US20180034585A1
Автор: Ahn Joonkui, Kim Bonghoe, Kim Byounghoon, NOH Kwangseok
Принадлежит: LG ELECTRONICS INC.

A method for communication device processing a data block in a low-density parity-check (LDPC) encoder includes the steps of, if a size of a payload is equal to or greater than a prescribed size, performing code block segmentation, and performing encoding in a unit of a code block on code blocks according to the code block segmentation. In this case, the code block segmentation may be performed by a payload size supported by a parity check matrix (H) corresponding to a coding rate of the LDPC encoder. 1. A method for a communication device processing a data block in a low-density parity-check (LDPC) encoder , the method comprising:if a size of a payload is equal to or greater than a prescribed size, performing code block segmentation; andperforming encoding in a unit of a code block on code blocks according to the code block segmentation,wherein the code block segmentation is performed by a payload size supported by a parity check matrix (H) corresponding to a coding rate of the LDPC encoder.2. The method of claim 1 , wherein the code block segmentation is performed to minimize a number of the code block.3. The method of claim 1 , wherein the code block segmentation is performed using one of a plurality of payload sizes supported by the parity check matrix (H).4. The method of claim 1 , further comprising:if a size of an encoded bit according to the encoding is not a size defined by the parity check matrix (H) corresponding to a coding rate of the LDPC encoder, performing rate matching or shortening.5. The method of claim 4 , wherein the rate matching comprises puncturing or repetition.6. The method of claim 1 , further comprising:attaching a CRC (cyclic redundancy check) to a code block after the code block segmentation is performed.7. The method of claim 1 , wherein the payload is segmented into different payload sizes supported by the parity check matrix (H) corresponding to a coding rate of the LDPC encoder.8. A communication device for processing a data block ...

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Номер записи: 38
17-02-2022 дата публикации

METHODS AND DEVICES FOR RATE ADAPTIVE FORWARD ERROR CORRECTION USING A FLEXIBLE IRREGULAR ERROR CORRECTING CODE

Номер: US20220052712A1
Автор: PAN Chunpo
Принадлежит:

Methods and devices for performing rate adaptive forward error correction using a flexible irregular error-correcting code, such as a staircase code. Each codeword of the ECC uses one of two or more different encodings, each encoding having a different number of parity bits. By adjusting the proportions of codewords of each encoding included in a data block, the FEC overhead can be finely adjusted, achieving flexible levels of FEC overhead in response to increased or decreased noise or perturbations in a communication channel. Three types of flexible irregular zipper codes are described: general zipper codes, staircase codes, and oFEC codes. 1. A method comprising:receiving, at a forward error correction (FEC) encoder of a transmitter, a digital data signal comprising a plurality of data bits; the FEC enabled data signal comprising a sequence of data blocks alternating between row-wise data blocks and column-wise data blocks;', a data bit sequence comprising one or more of the data bits; and', 'a parity bit sequence comprising one or more parity bits, each parity bit sequence being based on its respective data bit sequence and a corresponding row of a prior column-wise data block;, 'each row-wise data block comprising a plurality of rows, the plurality of rows defining a plurality of columns, each row comprising, a data bit sequence comprising one or more of the data bits; and', 'a parity bit sequence comprising one or more parity bits, each parity bit sequence being based on its respective data bit sequence and a corresponding column of a prior row-wise data block;, 'each column-wise data block comprising a plurality of columns, the plurality of columns defining a plurality of rows, each column comprising, 'each data block including at least one parity bit sequence of a first encoding and at least parity bit sequence of a second encoding;', 'each parity bit sequence of the first encoding having a first predetermined number of parity bits;', 'each parity bit ...

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Номер записи: 39
31-01-2019 дата публикации

PERMUTATION NETWORK DESIGNING METHOD, AND PERMUTATION CIRCUIT OF QC-LDPC DECODER

Номер: US20190036548A1
Автор: Hsiao Yu-Hua, Yen Heng-Lin
Принадлежит: Shenzhen EpoStar Electronics Limited CO.

A permutation network designing method and a permutation circuit using the same are provided. The method includes: identifying a predetermined check matrix of the QC-LDPC decoder, wherein the check matrix comprises M×N sub-matrices, wherein each of the sub-matrices is a Z×Z matrix, wherein Z is a default dimension value of each of the sub-matrices; constructing a permutation network of a permutation circuit according to the default dimension value and a saving parameter, wherein the permutation network comprises a plurality of permutation layers arranged sequentially, and each of the permutation layers has the same amount of nodes, wherein the amount of the permutation layers and the amount of the nodes of each of the permutation layers are set according to the default dimension value and a saving parameter; and disposing a plurality of selectors on the nodes of the permutation network of the permutation circuit. 1. A permutation network designing method for a permutation circuit of a quasi-cyclic low-density parity check (QC-LDPC) decoder corresponding to a rewritable non-volatile memory module , comprising:identifying a size of a physical page of the rewritable non-volatile memory module as a page size, wherein the physical page is configured to store a plurality of codewords;obtaining a length of each of the codewords as a codeword length according to the amount of the codewords and the page size;identifying a predetermined check matrix of the QC-LDPC decoder, wherein the check matrix comprises M×N sub-matrices, wherein each of the sub-matrices is a Z×Z matrix, wherein Z is a default dimension value of each of the sub-matrices, and the default dimension value is a quotient obtained by dividing the codeword length with N;calculating a first value according to the default dimension value, and calculating a second value according to the first value and a saving parameter, wherein the second value is a difference value obtained by subtracting the first value with the ...

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Номер записи: 40
12-02-2015 дата публикации

APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS

Номер: US20150043672A1
Автор: HONG Sungryong, Hwang Jaeho, KIM Byounggill, KIM Jaehyung, KIM Woochan, Ko Woosuk
Принадлежит:

A method and an apparatus for transmitting broadcast signals thereof are disclosed. The method for transmitting broadcast signals includes encoding data of PLPs (Physical Layer Pips); building at least one signal frame by mapping the encoded data of the PLPs; and modulating data in the built signal frame by OFDM (Orthogonal Frequency Division Multiplexing) method and transmitting the broadcast signals having the modulated data. 1. A method of providing an emergency alert via broadcast signal transmission , the method including:encoding data of PLPs (Physical Layer Pips), wherein the encoding data of the PLPs further includes,encoding the data of the PLPs with LDPC (Low Density Parity Check) codes,bit interleaving the LDPC encoded data in the PLPs,mapping the bit interleaved data onto constellations,MIMO (Multi Input Multi Output) encoding the mapped data, andtime interleaving the MIMO encoded data;building at least one signal frame by mapping the encoded data of the PLPs; andmodulating data in the built signal frame by OFDM (Orthogonal Frequency Division Multiplexing) method and transmitting the broadcast signals having the modulated data,wherein the signal frame includes a preamble generated by using an EAS (Emergency Alert System) sequence, wherein the EAS sequence provides signaling about the emergency.2. The method of claim 1 , wherein the preamble provides a first signaling information to indicate when a receiver in a stand-by mode wakes up.3. The method of claim 2 , wherein the EAS sequence of the preamble includes the first signaling information.4. The method of claim 1 , wherein the preamble further includes a second signaling information indicating whether EAS data is provided in the current signal frame claim 1 , andwherein the EAS data includes information about the emergency.5. The method of claim 4 , wherein the signal frame further includes physical layer signaling data having signaling information for the data of the PLPs claim 4 ,wherein the physical ...

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Номер записи: 41
11-02-2016 дата публикации

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

Номер: US20160043737A1
Автор: Shinohara Yuji, Yamamoto Makiko
Принадлежит: SONY CORPORATION

A data processing device including an encoding unit configured to encode an information bit into an LDPC code with a code length of 64800 bits and an encoding rate of 2/30, based on a parity check matrix of an LDPC (Low Density Parity Check) code. The LDPC code includes an information bit and a parity bit. The parity check matrix includes an information matrix part corresponding to the information bit and a parity matrix part corresponding to the parity bit. The information matrix part is shown by a parity check matrix initial value table. The parity check matrix initial value table is a table showing positions of elements of 1 of the information matrix part every 360 columns. 1. A data processing device comprising:an encoding unit configured to encode an information bit into an LDPC code with a code length of 64800 bits and an encoding rate of 2/30, based on a parity check matrix of an LDPC (Low Density Parity Check) code, whereinthe LDPC code includes an information bit and a parity bit,the parity check matrix includes an information matrix part corresponding to the information bit and a parity matrix part corresponding to the parity bit,the information matrix part is shown by a parity check matrix initial value table, andthe parity check matrix initial value table is a table showing positions of elements of 1 of the information matrix part every 360 columns and is expressed as follows30 251 2458 3467 9897 12052 12191 15073 15949 16328 16972 17704 20672 22200 22276 25349 26106 28258 29737 30518 30951 32440 43031 46622 47113 52077 52609 52750 54295 55384 56954 57155 57853 599426985 7975 8681 10628 10866 13223 14882 18449 19570 24418 24538 24556 25926 26162 26947 28181 30049 33678 35497 37980 41276 43443 44124 48684 50382 51223 53635 57661 58040 59128 59300 59614 60200 603291896 5169 7347 10895 14434 14583 15125 15279 17169 18374 20805 25203 29509 30267 30925 33774 34653 34827 35707 36868 38136 38926 42690 43464 44624 46562 50291 50321 51544 56470 56532 58199 58398 ...

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Номер записи: 42
12-02-2015 дата публикации

DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD

Номер: US20150046765A1
Автор: Shinohara Yuji, Yamamoto Makiko
Принадлежит: SONY CORPORATION

A data processing apparatus and a data processing method which enable provision of an LDPC code that achieves good error-rate performance. An LDPC encoding unit performs encoding using an LDPC code having a code length of 64800 bits and a code rate of 24/30, 25/30, 26/30, 27/30, 28/30, or 29/30. The LDPC code includes information bits and parity bits, and a parity check matrix H is composed of an information matrix portion corresponding to the information bits of the LDPC code, and a parity matrix portion corresponding to the parity bits. The information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table that shows positions of elements of 1 in the information matrix portion in units of 360 columns. The apparatus and method may be applied to LDPC encoding and LDPC decoding. 142-. (canceled)43. A data processing apparatus comprising:an encoding unit configured to encode information bits into an LDPC (Low Density Parity Check) code having a code length of 64800 bits and a code rate of 26/30 on the basis of a parity check matrix of the LDPC code, whereinthe LDPC code includes information bits and parity bits,the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,the information matrix portion is represented by a parity check matrix initial value table, andthe parity check matrix initial value table is a table showing positions of elements of 1 in the information matrix portion in units of 360 columns, including142 2307 2598 2650 4028 4434 5781 5881 6016 6323 6681 6698 81252932 4928 5248 5256 5983 6773 6828 7789 8426 8494 8534 8539 8583899 3295 3833 5399 6820 7400 7753 7890 8109 8451 8529 8564 860221 3060 4720 5429 5636 5927 6966 8110 8170 8247 8355 8365 861620 1745 2838 3799 4380 4418 4646 5059 7343 8161 8302 8456 86319 6274 6725 6792 7195 7333 8027 8186 8209 8273 8442 8548 8632494 1365 2405 3799 5188 5291 7644 ...

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Номер записи: 43
12-02-2015 дата публикации

DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD

Номер: US20150046766A1
Автор: Shinohara Yuji, Yamamoto Makiko
Принадлежит:

A data processing apparatus and a data processing method which enable provision of an LDPC code that achieves good error-rate performance. An LDPC encoding unit performs encoding using an LDPC code having a code length of 64800 bits and a code rate of 18/30, 19/30, 20/30, 21/30, 22/30, or 23/30. The LDPC code includes information bits and parity bits, and a parity check matrix H is composed of an information matrix portion corresponding to the information bits of the LDPC code, and a parity matrix portion corresponding to the parity bits. The information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table that shows positions of elements of 1 in the information matrix portion in units of 360 columns. The apparatus and method may be applied to LDPC encoding and LDPC decoding. 1. A data processing apparatus comprising:an encoding unit configured to encode information bits into an LDPC (Low Density Parity Check) code having a code length of 64800 bits and a code rate of 18/30 on the basis of a parity check matrix of the LDPC code, whereinthe LDPC code includes information bits and parity bits,the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,the information matrix portion is represented by a parity check matrix initial value table, andthe parity check matrix initial value table is a table showing positions of elements of 1 in the information matrix portion in units of 360 columns, including113 1557 3316 5680 6241 10407 13404 13947 14040 14353 15522 15698 16079 17363 19374 19543 20530 22833 24339271 1361 6236 7006 7307 7333 12768 15441 15568 17923 18341 20321 21502 22023 23938 25351 25590 25876 2591073 605 872 4008 6279 7653 10346 10799 12482 12935 13604 15909 16526 19782 20506 22804 23629 24859 256001445 1690 4304 4851 8919 9176 9252 13783 16076 16675 17274 18806 18882 20819 21958 22451 23869 23999 241771290 ...

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Номер записи: 44
01-05-2014 дата публикации

Hardware Architecture and Implementation of Low Power Layered Multi-Level LDPC Decoder

Номер: US20140122979A1
Автор: Chung-Li Wang, Johnson Yen, Lei Chen, Zongwang Li
Принадлежит: LSI Corp

A layered LDPC decoder sorts and selects a subset of message entries for processing based on entry size. MIN1 and MIN2 values for each message entry in the subset are truncated, and either the truncated values or non-truncated values are combined with a symbol vector based on whether the subset of message entries includes a variable node associated with the layer being processed.

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Номер записи: 45
18-02-2016 дата публикации

METHOD AND APPARATUS OF LDPC ENCODER IN 10GBASE-T SYSTEM

Номер: US20160049962A1
Автор: Hou Jilei, Huang Yin, Li Jian, Xu Changlong, Xue Ylsheng
Принадлежит:

A method of data encoding is disclosed. A communications device receives a set of information bits to be encoded into a codeword (c), which includes the set of information bits and a set of parity bits. A first bit value is assigned to a first parity bit in the set of parity bits. The remaining parity bits are then encoded based, at least in part, on the first bit value assigned to the first parity bit. The device may encode the remaining parity bits using the set of information bits and a parity check matrix (H) for a low density parity check (LDPC) code. The device may also generate a new parity check matrix (H) based on linearly independent rows of the parity check matrix H, and iteratively evaluate each of the remaining parity bits based on the equation: Hc=0. The device may then determine whether the encoded codeword c is a valid codeword given the LDPC code, and change one or more bit values of the codeword if c is not a valid codeword. 1. A method of data encoding comprising:receiving a set of information bits to be encoded into a codeword (c), wherein the codeword includes the set of information bits and a set of parity bits;assigning a first bit value to a first parity bit in the set of parity bits; and 'determining whether the codeword is a valid codeword for a given LDPC code; and', 'encoding remaining parity bits in the set of parity bits based, at least in part, on the first bit value assigned to the first parity bit, wherein encoding the remaining parity bits compriseschanging one or more bit values of the codeword if the codeword is not a valid codeword.2. The method of claim 1 , wherein the remaining parity bits are encoded using the set of information bits and a parity check matrix (H) for a low density parity check (LDPC) code.3. The method of claim 2 , further comprising:{'sub': '0', 'generating a new parity check matrix (H) using linearly independent rows of the parity check matrix.'}4. The method of claim 3 , wherein encoding the remaining ...

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Номер записи: 46
16-02-2017 дата публикации

DATA SENDING METHOD AND APPARATUS

Номер: US20170047945A1
Автор: Chen Zhouhui, Lin Wei, MA Zheng
Принадлежит: Huawei Technologies Co., Ltd.

The present invention discloses a data sending method and apparatus, which resolves a problem that performance of a high coding rate LDPC code obtained in an existing puncturing manner based on a variable node degree distribution is relatively poor. The method includes: encoding, by using an LDPC code check matrix, an information bit that needs to be sent, to obtain a codeword sequence; determining a puncturing priority of each parity bit in the codeword sequence according to row destruction and/or cycle destruction, on the LDPC code check matrix, of a variable node corresponding to each parity bit; puncturing the codeword sequence according to the puncturing priority of each parity bit in the codeword sequence; and generating a bit sequence according to the punctured codeword sequence, and sending the bit sequence. In this way, performance of an obtained high coding rate LDPC code is improved. 1. A data sending method , wherein the method comprises:encoding, by using a low density parity check (LDPC) code check matrix, an information bit that needs to be sent, to obtain a codeword sequence, wherein the codeword sequence comprises the information bit and parity bits;determining a puncturing priority of each parity bit in the codeword sequence according to at least one of row destruction and cycle destruction, on the LDPC code check matrix, of a variable node corresponding to each parity bit;puncturing the codeword sequence according to the puncturing priority of each parity bit in the codeword sequence; andgenerating a bit sequence according to the punctured codeword sequence, and sending the bit sequence, whereinthe row destruction is used to measure impact of the variable node in the LDPC code check matrix on correct decoding of variable nodes adjacent to the variable node, wherein the adjacent variable nodes are variable nodes that are adjacent to the variable node and that are of variable nodes connected to check nodes connected to the variable node; and the ...

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Номер записи: 47
15-02-2018 дата публикации

MEMORY CONTROLLER, SEMICONDUCTOR MEMORY SYSTEM AND OPERATING METHOD THEREOF

Номер: US20180048329A1
Автор: HA Jeong-Seok, KIM Dae-Sung, Lee Sang-Ha
Принадлежит:

An operation method of a memory controller includes: reading a second data from memory cells when a hard decision error correction decoding operation based on a first data read from the memory cells fails; calculating a LLR of each bit-data included in the first data by using the first and second data; and performing a soft decision error correction decoding operation based on the LLR, wherein the memory cells include a first and second memory cell, wherein the first data includes first-bit-data read from the first and second memory cell, wherein the second data includes second-bit-data read from the first and second memory cell, wherein the LLR is a LLR of the first-bit-data read from the first memory cell calculated based on the first bit and a second bit read from the first memory cell and a first bit and a second bit read from the second memory cell. 1. An operation method of a memory controller , the operation method comprising:reading a second data from memory cells when a hard decision error correction decoding operation based on a first data read from the memory cells fails;calculating a Log Likelihood Ratio (LLR) of each bit-data included in the first data by using the first data and the second data; andperforming a soft decision error correction decoding operation based on the LLR,wherein the memory cells include a first memory cell and a second memory cell adjacent to the first memory cell,wherein the first data includes first-bit-data read from the first memory cell and the second memory cell,wherein the second data includes second-bit-data read from the first memory cell and the second memory cell, andwherein the LLR is a LLR of the first-hit-data read from the first memory cell calculated based on the first bit and a second bit read from the first memory cell and a first bit and a second bit read from the second memory cell.2. The operation method of claim 1 ,wherein each of the memory cells stores n-bit-data,wherein each of the first-bit-data ...

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Номер записи: 48
03-03-2022 дата публикации

FORWARD ERROR CORRECTION USING NON-BINARY LOW DENSITY PARITY CHECK CODES

Номер: US20220069844A1
Автор: Abrams Stuart, Hadani Ronny, Namboodiri Vamadevan
Принадлежит:

Methods, systems and devices for forward error correction in orthogonal time frequency space (OTFS) communication systems using non-binary low-density parity-check (NB-LDPC) codes are described. One exemplary method for forward error correction includes receiving data, encoding the data via a non-binary low density parity check (NB-LDPC) code, wherein the NB-LDPC code is characterized by a matrix with binary and non-binary entries, modulating the encoded data to generate a signal, and transmitting the signal. Another exemplary method for forward error correction includes receiving a signal, demodulating the received signal to produce data, decoding the data via a NB-LDPC code, wherein the NB-LDPC code is characterized by a matrix with binary and non-binary entries, and providing the decoded data to a data sink. 1. An apparatus for forward error correction , comprising:a processor-implemented encoder configured to encode information bits via a non-binary low density parity check (NB-LDPC) code, wherein the NB-LDPC code is formulated as a matrix with binary and non-binary entries;a modulator configured to modulate, using an orthogonal time frequency space (OTFS) modulation scheme, the encoded information bits to generate a signal; anda transmitter configured to transmit the signal over a channel,wherein a parity matrix H for the NB-LDPC code is based on a binary H matrix, and 'add offsets to entries in a first column and entries in a first row of the binary H matrix such that the first column and the first row contain only identity elements.', 'wherein the binary H matrix is based on a computer search algorithm configured to2. The apparatus of claim 1 , wherein the computer search algorithm is configured to terminate upon a determination that no N-cycles are present in a Tanner graph representation of the binary H matrix claim 1 , and wherein N=4 or N=6.3. The apparatus of claim 1 , wherein the parity check matrix H is represented a H=[H claim 1 , H] claim 1 , where ...

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Номер записи: 49
14-02-2019 дата публикации

Low Density Parity Check Decoder

Номер: US20190052288A1
Автор: Choi Gwan S., GUNNAM Kiran Kumar
Принадлежит: The Texas A&M University System

A method and system for decoding low density parity check (“LDPC”) codes. A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes decoding circuitry configured to process blocks of an LDPC matrix. The decoding circuitry includes a control unit that controls processing by the decoding circuitry. The control unit is configured to cause the decoding circuitry to process blocks of a layer of the LDPC matrix out of order. 1. A low density parity check (LDPC) code decoder , comprising: 'a control unit that controls processing by the decoding circuitry, the control unit configured to cause the decoding circuitry to process blocks of a layer of the LDPC matrix out of order,', 'decoding circuitry configured to process blocks of an LDPC matrix, the decoding circuitry comprising an R new update substep that provides an R new message, wherein the R new message is produced for a block of a different layer of the matrix from a layer containing a block currently being processed;', 'an R old update substep that provides an R old message, wherein the R old message is produced for a layer of the matrix currently being processed;', 'a P message substep that generates updated P messages;', 'a Q message substep that computes variable node messages (Q messages); and', 'a check node partial state processing substep that updates partial state of the layer based on Q messages computed for the block., 'wherein the control unit is configured to cause the decoding circuitry to process each block of the LDPC matrix in processing substeps comprising2. The LDPC code decoder of claim 1 , wherein the decoding circuitry is configured to generate a Q message by combining an R message with a P message.3. The LDPC code decoder of claim 1 , wherein the decoding circuitry further comprises a permuter configured to permute a P message.4. The LDPC code decoder of claim 3 , wherein the permuter is configured to permute the P message by a difference of ...

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Номер записи: 50
26-02-2015 дата публикации

MULTI-LEVEL MEMORY CONTROLLER WITH PROBABILITY-DISTRIBUTION-BASED ENCODING

Номер: US20150058702A1
Автор: Ramamoorthy Aditya, Sutardja Pantas, Wu Zining
Принадлежит:

A memory controller includes an encoder, a modulator, and a demodulator. A nonvolatile memory includes memory cells, each programmable to one of three or more levels. According to first encoded data, the modulator programs a first subset of the memory cells to a first of the levels and a second subset of the memory cells to a second of the levels. Measurable values of the first subset are characterized by a first probability density function having a first width. Measurable values of the second subset are characterized by a second probability density function having a second width. The first width is greater than the second width. The encoder generates the first encoded data based on input data such that the first subset is smaller than the second subset. The demodulator is configured to output second encoded data in response to measurable values of the memory cells. 1. A memory controller for a nonvolatile memory including a plurality of memory cells , each of the plurality of memory cells being configured to be programmed to one of a plurality of levels , the plurality of levels being greater than two , the memory controller comprising:an encoder configured to receive input data and generate first encoded data based on the input data; a first subset of the plurality of memory cells is programmed to a first level of the plurality of levels,', 'a second subset of the plurality of memory cells is programmed to a second level of the plurality of levels,', 'measurable values of the first subset of the plurality of memory cells are characterized by a first probability density function having a first width,', 'measurable values of the second subset of the plurality of memory cells are characterized by a second probability density function having a second width,', 'the first width of the first probability density function is greater than the second width of the second probability density function, and', 'the encoder is configured to generate the first encoded data such ...

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Номер записи: 51
25-02-2021 дата публикации

METHOD AND APPARATUS FOR LOW DENSITY PARITY CHECK CHANNEL CODING IN WIRELESS COMMUNICATION SYSTEM

Номер: US20210058095A1
Автор: JIN Jie, Mazurenko Ivan Leonidovich, PETIUSHKO Aleksandr Aleksandrovich, ZHANG Chaolong
Принадлежит: Huawei Technologies CO.,Ltd.

Embodiments of this application disclose provides a low density parity check (LDPC) channel encoding method for use in a wireless communications system. A communication device encodes an input bit sequence by using a LDPC matrix, to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. Embodiments of the application provide eight particular designs of the base matrix. The encoding method provided in the embodiments of the application can be used in various communications systems including the fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths. 2. The method according to claim 1 , further comprising:determining, by the communication apparatus, the lifting factor Z; anddetermining, by the communication apparatus, the base matrix according to a set index of the lifting factor Z.3. The method according to claim 1 , wherein lifting factor Z is one of 5 claim 1 , 10 claim 1 , 20 claim 1 , 40 claim 1 , 80 claim 1 , 160 claim 1 , or 320.4. The method according to claim 1 , wherein the base matrix comprises m rows and n columns claim 1 , where m and n are positive integers claim 1 , and n=m+10.5. The method according to claim 4 , wherein 7≤m≤42 claim 4 , and 17≤n≤52.6. The method according to claim 1 , wherein the matrix H is determined according to a transformed matrix of the base matrix claim 1 , and wherein the transformed matrix is obtained by performing one or more of row transformation or column transformation on the base matrix.7. The method according to claim 1 , further comprising:receiving a signal, the signal comprising information that is based on low density parity check (LDPC) encoding; andperforming demodulating, deinterleaving, and rate de-matching on the signal to obtain the input sequence.9. The apparatus according to claim 8 , wherein the at least one processor is further configured to: ...

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Номер записи: 52
13-02-2020 дата публикации

ERROR CORRECTION CIRCUIT AND OPERATING METHOD THEREOF

Номер: US20200052716A1
Автор: KANG Soon Young, Kim Dae Sung
Принадлежит:

Provided herein may be an error correction circuit. An error correction circuit for performing error correction decoding based on an iterative decoding scheme using a NB-LDPC code may include a symbol configuration circuit for configuring an initial symbol to be assigned as a variable node value to a variable node, a reliability value initialization circuit for initializing first reliability values of candidate symbols corresponding to the variable node based on the initial symbol assigned to the variable node, and a symbol correction circuit updating the first reliability values of the candidate symbols based on communications received from a check node coupled to the variable node, the candidate symbols having updated first reliability values, respectively, and adjusting the variable node value to one of the candidate symbols based on a comparison with the updated first reliability value of one of the candidate symbols with a first threshold value. 1. An error correction circuit for performing error correction decoding based on an iterative decoding scheme using a Non-Binary Low Density Parity Check (NB-LDPC) code , comprising:a symbol configuration circuit configured to configure an initial symbol to be assigned as a variable node value to a variable node;a reliability value initialization circuit configured to initialize first reliability values of candidate symbols corresponding to the variable node based on the initial symbol assigned to the variable node; anda symbol correction circuit configured to update the first reliability values of the candidate symbols based on communications received from a check node coupled to the variable node, the candidate symbols having updated first reliability values, respectively, and configured to adjust the variable node value to one of the candidate symbols based on a comparison with the updated first reliability value of one of the candidate symbols with a first threshold value.2. The error correction circuit according to ...

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Номер записи: 53
13-02-2020 дата публикации

METHOD AND APPARATUS FOR LOW DENSITY PARITY CHECK CHANNEL CODING IN WIRELESS COMMUNICATION SYSTEM

Номер: US20200052720A1
Автор: JIN Jie, Mazurenko Ivan Leonidovich, PETIUSHKO Aleksandr Aleksandrovich, ZHANG Chaolong
Принадлежит: Huawei Technologies CO.,Ltd.

Embodiments of this application disclose provides a low density parity check (LDPC) channel encoding method for use in a wireless communications system. A communication device encodes an input bit sequence by using a LDPC matrix, to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. Embodiments of the application provide eight particular designs of the base matrix. The encoding method provided in the embodiments of the application can be used in various communications systems including the fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths. 2. The method according to claim 1 , wherein N is equal to 50×Z.3. The method according to claim 1 , wherein the input sequence c is represented as c={c claim 1 , c claim 1 , c claim 1 , . . . claim 1 , c} claim 1 , and the encoded sequence d is represented as d={d claim 1 , d claim 1 , d claim 1 , . . . claim 1 , d} claim 1 , wherein in encoding the input sequence c using the matrix H claim 1 , an element c(k=0 claim 1 , 1 claim 1 , 2 claim 1 , . . . claim 1 , K−1) in the input sequence c and an element do (n=0 claim 1 , 1 claim 1 , 2 claim 1 , . . . claim 1 , N−1) in the encoded sequence d satisfy:for k=2Z to K−1,{'sub': k', 'k−2z', 'k, 'if cis not a filling bit, d=c; and'}{'sub': k', 'k', 'k−2Z, 'if cis a filling bit, c=0, and dis a filling bit.'}5. The method according to claim 4 , wherein the parity sequence w has N+2Z−K bits and the parity sequence w is represented as w={w claim 4 , w claim 4 , w claim 4 , . . . claim 4 , w}.6. The method according to claim 5 , wherein in encoding the input sequence c using the matrix H claim 5 , an element in the parity sequence w and an element in the encoded sequence d satisfy:for k=K to N+2Z−1,{'sub': k−2z', 'k−K, 'd=w.'}7. The method according to claim 1 , wherein Z is a minimum value that satisfies K×Z≥K claim 1 ...

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Номер записи: 54
20-02-2020 дата публикации

Error correction device, operating method thereof and electronic device including the same

Номер: US20200059244A1
Автор: Dae Sung Kim
Принадлежит: SK hynix Inc

An error correction device includes a bit reliability value determination circuit configured to determine bit reliability values respectively corresponding to hard decision bits, based on soft decision bit sets respectively corresponding to the hard decision bits; and a decoder including a variable node configured to receive and store the hard decision bits and the bit reliability values, and perform a decoding operation for the hard decision bits by restoring reliability values from the bit reliability values, wherein the reliability values respectively correspond to elements except a decision symbol configured by the hard decision bits, in a Galois field (GF) defined in the variable node.

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Номер записи: 55
05-03-2015 дата публикации

POWER CONTROL METHOD AND APPARATUS

Номер: US20150067380A1
Автор: Wang Huaping, ZHAN Peng
Принадлежит:

The application provides a power control method and apparatus. The power control method includes: obtaining, by a transmit end of a link, bit error rate information of a receive end of the link; and if the bit error rate information does not meet a predetermined condition, adjusting a transmit power class value of the transmit end. According to the power control method and apparatus of the application, the transmit power class value of the transmit end of the link can be dynamically adjusted according to a change of a system or an external environment, thereby improving interference immunity of the link and ensuring stability and reliability of data transmission. 1. A power control method , comprising:obtaining bit error rate information of a receive end of a link; andadjusting a transmit power class value of a transmit end of the link if the bit error rate information does not meet a predetermined condition.2. The power control method according to claim 1 , wherein after the adjusting the transmit power class value of the transmit end of the link claim 1 , the method further comprises:obtaining a signal-to-noise ratio of the transmit end and a signal-to-noise ratio of the receive end;if the signal-to-noise ratio of the transmit end and the signal-to-noise ratio of the receive end remain unchanged or increase compared with those before the transmit power class value of the transmit end is adjusted, determining that power control is successful; andif the signal-to-noise ratio of the transmit end or the signal-to-noise ratio of the receive end decreases compared with that before the transmit power class value of the transmit end is adjusted, reversely adjusting the transmit power class value of the transmit end.3. The power control method according to claim 2 , wherein the transmit end receives the bit error rate information and the signal-to-noise ratio that are based on channel encoding and sent by the receive end.4. The power control method according to claim 3 , ...

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Номер записи: 56
04-03-2021 дата публикации

Low density parity check decoder

Номер: US20210067175A1
Автор: Gwan S. CHOI, Kiran Kumar Gunnam
Принадлежит: TEXAS A&M UNIVERSITY SYSTEM

A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an R message from a previous iteration with a P message to produce a Q message. The P sum adder array adds the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message.

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Номер записи: 57
10-03-2016 дата публикации

Data processing apparatus and data processing method

Номер: US20160072523A1
Автор: Lachlan Michael, Makiko Yamamoto, Nabil Sven Loghin Muhammad, Yuichi Hirayama, Yuji Shinohara
Принадлежит: Sony Corp

The present technology relates to a data processing apparatus and a data processing method that are able to secure good communication quality in data transmission using an LDPC code. One symbol is mapped to one of 16 signal points prescribed in 16APSK, with code bits of four bits of an LDPC code having a code length of 16200 bits and a code rate of 7/15 as one symbol. 16 signal points prescribed in 16APSK are four signal points on an inner circle and 12 signal points on an outer circle, and a radius ratio of the inner circle and the outer circle is 5.25. The present technology may be applied to, for example, a case of performing data transmission using an LDPC code.

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Номер записи: 58
08-03-2018 дата публикации

TRANSMISSION APPARATUS, TRANSMISSION METHOD, RECEPTION APPARATUS, and RECEPTION METHOD

Номер: US20180069569A1
Автор: KOBAYASHI Kiyotaka, MURAKAMI Yutaka, YAP Choo Eng
Принадлежит:

In a multi-antenna communication system using LDPC codes, a simple method is used to effectively improve the received quality by performing a retransmittal of less data without restricting applicable LDPC codes. In a case of a non-retransmittal, a multi-antenna transmitting apparatus transmits, from two antennas, LDPC encoded data formed by LDPC encoding blocks. In a case of a retransmittal, the multi-antenna transmitting apparatus uses a transmission method, in which the diversity gain is higher than in the previous transmission, to transmit only a part of the LDPC encoded data as previously transmitted. For example, the only the part of the LDPC encoded data to be re-transmitted is transmitted from the single antenna. 1. A transmission apparatus comprising:a Low Density Parity Check (LDPC) encoder that generates an encoded data sequence using a parity check matrix including a plurality of columns that are different in column weight, the encoded data sequence being decoded by a reception apparatus; anda transmitter that transmits the encoded data sequence and then transmits a duplicate of a part of the encoded data sequence, wherein:a column weight of the parity check matrix corresponding to the duplicate of the part of the encoded data sequence is greater than a column weight of the parity check matrix corresponding to data that is not repeatedly transmitted among data to be repeatedly transmitted in the encoded data sequence.2. The transmission apparatus according to claim 1 , wherein:the transmitter repeatedly transmits the duplicate of the part of the encoded data sequence a plurality of times.3. A transmission method comprising:generating an encoded data sequence using a parity check matrix including a plurality of columns that are different in column weight, the encoded data sequence being decoded by a reception apparatus; andtransmitting the encoded data sequence and then transmitting a duplicate of a part of the encoded data sequence, wherein:a column ...

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Номер записи: 59
08-03-2018 дата публикации

METHODS AND DEVICES FOR GENERATING OPTIMIZED CODED MODULATIONS

Номер: US20180069570A1
Автор: ABDMOULEH Ahmed, Boutillon Emmanuel
Принадлежит: UNIVERSITE DE BRETAGNE SUD

Embodiments of the invention provide a device for determining a coded modulation scheme, said coded modulation scheme being defined by at least one non-binary error correcting code containing at least one non-binary parity-check equation, a modulation scheme, and a modulation mapping, wherein the device comprises: 1. A device for determining a coded modulation scheme , said coded modulation scheme being defined by at least one non-binary error correcting code containing at least one non-binary parity-check equation , a modulation scheme , and a modulation mapping , wherein said device comprises:a calculation unit configured to determine one or more candidate modulation mappings and one or more candidate parity-check equations defining said at least one non-binary error correcting code, each set of a candidate modulation mapping and at least one candidate parity-check equation providing codeword vectors and being associated with one or more metrics, each metric being defined by a number of distinct pairs of codeword vectors having an Euclidean distance of a defined value; anda selection unit configured to select one candidate modulation mapping and at least one candidate parity-check equation according to an optimization criterion applied to said one or more metrics.2. The device of claim 1 , wherein the one or more candidate parity-check equations are represented by one or more coefficients claim 1 , the error correcting code being defined by a set of values claim 1 , the calculation unit being configured to determine the one or more candidate parity-check equations by determining a value of at least one coefficient representing the one or more candidate parity-check equations from said set of values.3. The device of claim 1 , wherein the calculation unit is configured to determine said one or more candidate modulation mappings from a predefined set of modulation mappings.4. The device of claim 1 , wherein the optimization criterion comprises the minimization of at ...

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Номер записи: 60
28-02-2019 дата публикации

BIT-FLIPPING DECODER FOR G-LDPC CODES WITH SYNDROME-DECODING FOR COMPONENT CODES

Номер: US20190068219A1
Автор: Bhatia Aman, CAI Yu, Kumar Naveen, LU Xuanxuan, XIONG Chenrong, Zhang Fan
Принадлежит:

Techniques are described for performing a bit-flipping decoding scheme on a G-LDPC codeword. In an example, a decoding system uses two syndrome tables. The first syndrome table identifies a predefined syndrome for a component codeword that protects a bit of the G-LDPC codeword. This predefined syndrome is identified based on a location of the bit and is used to update a current syndrome of the component codeword. The second syndrome table identifies one or more bit error locations for the component codeword. The bit error locations are identified from the second syndrome table based on the current syndrome of the component codeword, as updated. In an example, the error locations are used to update a reliability of the bit if its location corresponds to one of the error locations. A bit flipping decision is made for the bit based on its reliability. 1. A generalized low density-parity check (G-LDPC) decoding method , comprising:receiving, by a decoding system, a G-LDPC codeword that comprises a plurality of component codewords; and identifying a component codeword that protects a bit of the G-LDPC codeword;', 'updating a current syndrome of the component codeword based on a predefined syndrome from a first syndrome table, wherein the predefined syndrome is determined from the first syndrome table based on a location of the bit in at least one of the component codeword or the G-LDPC codeword; and', 'performing a bit-flipping operation on the bit in the component codeword based on an error location from a second syndrome table, wherein the error location is determined from the second syndrome table based on the current syndrome of the component codeword, and wherein the bit-flipping operation is performed based on a determination that the error location corresponds to the location of the bit., 'decoding, by the decoding system, the G-LDPC codeword by at least2. The method of claim 1 , further comprising:initializing, by the decoding system, a decision bit of the G-LDPC ...

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Номер записи: 61
09-03-2017 дата публикации

MEMORY SYSTEM INCLUDING ERROR CORRECTOR AND OPERATING METHOD THEREOF

Номер: US20170070240A1
Автор: KIM Nack Hyun
Принадлежит:

A memory system includes a controller and a semiconductor memory device. The semiconductor memory device stores a data set having main data bits and parity bits and provide soft decision bit streams corresponding to the data set in response to control signals of the controller. The controller includes a soft decision decoder for identifying data set by decoding the soft decision bit streams according to a first decoding method, a deinterleaver for deinterleaving the identified data set, a hard decision decoder for decoding the deinterleaved data set according to a second decoding method based on parity bits included in the deinterleaved data set, and outputting a failed data set if the decoding according to the second decoding method has failed, and an interleaver for interleaving the failed data set. The interleaved data set is fed back to the soft decision decoder. 1. A memory system comprising:a controller; anda semiconductor memory device configured to store a data set having main data bits and parity bits and provide soft decision bit streams corresponding to the data set in response to control signals of the controller, a soft decision decoder configured to identify the data set by decoding the soft decision bit streams according to a first decoding method;', 'a deinterleaver configured to deinterleave the identified data set;', 'a hard decision decoder configured to decode the deinterleaved data set according to a second decoding method based on the parity bits included in the deinterleaved data set, and output a failed data set if the decoding according to the second decoding method has failed; and', 'an interleaver configured to interleave the failed data set,', 'wherein the interleaved data set is fed back to the soft decision decoder., 'wherein the controller includes2. The memory system of claim 1 , wherein the soft decision decoder re-decodes the soft decision bit streams based on the interleaved data set.3. The memory system of claim 1 , wherein the ...

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Номер записи: 62
27-02-2020 дата публикации

ERROR CORRECTION DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME

Номер: US20200067538A1
Автор: JO Myung Jin, KANG Soon Young, Kim Dae Sung, SUNG Wan Je
Принадлежит:

An error correction device includes: a plurality of variable node units each configured to: receive a hard decision bit and a channel reliability value having a first bit-precision; and perform an iteration of a decoding operation on the hard decision bit based on the channel reliability value; a plurality of check node units each configured to: receive one or more reference reliability values having a second bit-precision from one or more variable node units coupled thereto among the plurality of variable node units during the iteration; and transmit, based on the one or more reference reliability values, one or more check reliability values having the second bit-precision to the one or more variable node units coupled thereto, wherein, during the iteration, each of the plurality of variable node units further: receives one or more first check reliability values from one or more check node units coupled thereto among the plurality of check node units; and updates the hard decision bit with reference to the channel reliability value and the one or more first check reliability values by upsizing the first bit-precision of the channel reliability value and the second bit-precision of the one or more first check reliability values. 1. An error correction device comprising:a plurality of variable node units each configured to:receive a hard decision bit and a channel reliability value having a first bit-precision; andperform an iteration of a decoding operation on the hard decision bit based on the channel reliability value;a plurality of check node units each configured to:receive one or more reference reliability values having a second bit-precision from one or more variable node units coupled thereto among the plurality of variable node units during the iteration; andtransmit, based on the one or more reference reliability values, one or more check reliability values having the second bit-precision to the one or more variable node units coupled thereto,wherein, ...

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Номер записи: 63
07-03-2019 дата публикации

PERMUTATION NETWORK DESIGNING METHOD, AND PERMUTATION CIRCUIT OF QC-LDPC DECODER

Номер: US20190074850A1
Автор: Hsiao Yu-Hua
Принадлежит: Shenzhen EpoStar Electronics Limited CO.

A permutation network designing method and a permutation circuit using the same are provided. The method includes: identifying a predetermined check matrix of the QC-LDPC decoder, wherein the check matrix comprises M×N sub-matrices, wherein each of the sub-matrices is a Z×Z matrix, wherein Z is a default dimension value of each of the sub-matrices; constructing a second permutation network of a permutation circuit by removing a target first permutation layer from a first permutation layer according to a shift type of the check matrix, wherein the amount of a plurality of second permutation layers and the amount of the second nodes of each of the second permutation layers are set according to the default dimension value; and disposing a plurality of selectors on the second nodes of the constructed second permutation network of the permutation circuit. 1. A permutation network designing method for a permutation circuit of a quasi-cyclic low-density parity check (QC-LDPC) decoder corresponding to a rewritable non-volatile memory module , comprising:identifying a size of a physical page of the rewritable non-volatile memory module as a page size, wherein the physical page is configured to store a plurality of codewords;obtaining a length of each of the codewords as a codeword length according to the amount of the codewords and the page size;identifying a predetermined check matrix of the QC-LDPC decoder, wherein the check matrix comprises M×N sub-matrices, wherein each of the sub-matrices is a Z×Z matrix, wherein Z is a default dimension value of each of the sub-matrices, and the default dimension value is a quotient obtained by dividing the codeword length with N;calculating a first value according to the default dimension value, and identifying a first permutation network according to the first value, the default dimension value, and a shift type of the check matrix, wherein the first permutation network comprises a plurality of first permutation layers arranged ...

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Номер записи: 64
17-03-2016 дата публикации

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

Номер: US20160079998A1
Автор: Hirayama Yuichi, Michael Lachlan, MUHAMMAD Nabil Sven Loghin, Shinohara Yuji, Yamamoto Makiko
Принадлежит: SONY CORPORATION

A code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 7/15 is interchanged with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK. In the interchanging, when 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a (#i+1)-th bit from a most significant bit of the 3 bits of code bits is set to a bit b#i, a (#i+1)-th bit from a most significant bit of 3 bits of symbol bits of the one symbol is set to a bit y#i, and a bit b, a bit b, and a bit b are interchanged with a bit y, a bit y, and a bit y 140-. (canceled)41: A data processing device comprising:an encoding unit configured to perform LDPC encoding based on a parity check matrix of an LDPC code in which a code length is 16200 bits and an encoding rate is 7/15; andan interchanging unit configured to interchange a code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 7/15 with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK,wherein, when 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a (#i+1)-th bit from a most significant bit of the 3 bits of code bits is set to a bit b#i, a (#i+1)-th bit from a most significant bit of 3 bits of symbol bits of the one symbol is set to a bit y#i, and the interchanging unit interchanges{'b': 0', '1, 'a bit b with a bit y,'}{'b': 1', '0, 'a bit b with a bit y, and'}{'b': 2', '2, 'a bit b with a bit y,'}wherein the LDPC code includes an information bit and a parity bit,wherein the parity check matrix includes an information matrix part corresponding to the information bit and a parity matrix part corresponding to the parity bit,wherein the information matrix part is shown by a parity check matrix initial value table, ...

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Номер записи: 65
17-03-2016 дата публикации

MULTIPLE SIZE AND RATE FORWARD ERROR CORRECTION (FEC) CODE COMBINATION WITH MINIMUM SHORTENING AND MAXIMUM COMBINED CODE RATE

Номер: US20160080001A1
Автор: Prodan Richard Stephen
Принадлежит: BROADCOM CORPORATION

A communication device is configured to encode information bits using one or more forward error correction (FEC) codes and/or error correction codes (ECCs) to generate different codewords (e.g., codeword groups having different lengths, based on different code rates, etc.). The device generates a combined codeword using different sized codewords (e.g., long, medium, and short) by filling fills long codewords completely if possible, then filling medium codewords completely if possible with the remaining message bits (if any), and filling short codewords completely if possible plus another additional short codeword with the remaining message bits (if any). If the total number of short (or medium and short) codeword parity bits is greater than or equal to the number of medium (or long) codeword parity bits, then the device increments the number of medium (or long) codewords by one and setting the number of short (or medium and short) codewords to zero. 1. A communication device comprising:a communication interface; and encode first information using a first code having a first code rate to generate first codewords having a first size;', 'shorten the first codewords to generate first shortened codewords having a first shortened size;', 'encode second information using a second code having a second code rate to generate second codewords having a second size that is less than the first size;', 'shorten the second codewords to generate second shortened codewords having a second shortened size;', 'encode third information using a third code having a third code rate to generate third codewords having a third size that is less than the second size;', 'shorten the third codewords to generate third shortened codewords having a third shortened size;', 'generate an orthogonal frequency division multiple access (OFDMA) frame that includes a combined codeword having a predetermined size;', 'generate the combined codeword using a first subset of the first codewords when the ...

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Номер записи: 66
15-03-2018 дата публикации

ELEMENTARY CHECK NODE PROCESSING FOR SYNDROME COMPUTATION FOR NON-BINARY LDPC CODES DECODING

Номер: US20180076830A1
Автор: Boutillon Emmanuel, MARCHAND Cédric
Принадлежит: UNIVERSITE DE BRETAGNE SUD

Embodiments of the invention provide a check node processing unit implemented in a decoder for decoding a signal, the check node processing unit being configured to receive at least three input messages and to generate at least one output message, wherein the check node processing unit comprises: 1. A check node processing unit implemented in a decoder for decoding a signal , the check node processing unit being configured to receive at least three input messages and to generate at least one output message , wherein the check node processing unit comprises:a syndrome calculator configured to determine a set of syndromes from said at least three input messages using at least two elementary check node processors, each syndrome comprising a symbol, a reliability metric associated with said symbol, and a binary vector;a decorrelation unit configured to determine, in association with at least an output message, a set of candidate components from said set of syndromes, each candidate component comprising a symbol and a reliability metric associated with said symbol, said set of candidate components comprising one or more pairs of components comprising a same symbol; anda selection unit configured to determine at least an output message by selecting components comprising distinct symbols from the set of candidate components associated with said at least an output message.2344. The check node processing unit of claim 1 , wherein at least one elementary check node processor is configured to determine an intermediary message from a first message and a second message claim 1 , said first message and second message being derived from said at least three input messages claim 1 , said intermediary message comprising one or more components and an intermediary binary vector associated with each component claim 1 , each component comprising a symbol and a reliability metric associated with said symbol claim 1 , said one or more components being sorted into a given order of the ...

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Номер записи: 67
18-03-2021 дата публикации

MEMORY SYSTEM AND OPERATING METHOD THEREOF

Номер: US20210083690A1
Автор: CHUNG Hoiju, JANG Mun Seon, KIM Tae Kyun
Принадлежит:

A memory system includes a memory controller including: a memory core configured to store data and an error correction code corresponding to the data; a syndrome generator configured to generate a first syndrome by substituting the data and the error correction code, read from the memory core, into a first check matrix, and generate a second syndrome by substituting the data and the error correction code, read from the memory core, into a second check matrix; and an error correction unit configured to correct an error of the read data and error correction code by using the first syndrome and the second syndrome, wherein constituents having values of ‘1’ in the first check matrix have values of ‘1’ also in the second check matrix. 1. A memory comprising:a memory core configured to store data and an error correction code corresponding to the data;a syndrome generator configured to generate a first syndrome by substituting the data and the error correction code, read from the memory core, into a first check matrix, and generate a second syndrome by substituting the data and the error correction code, read from the memory core, into a second check matrix; andan error correction unit configured to correct an error of the read data and error correction code by using the first syndrome and the second syndrome,wherein constituents having values of ‘1’ in the first check matrix have values of ‘1’ also in the second check matrix.2. The memory according to claim 1 , wherein the syndrome generatorgenerates the first syndrome by substituting the first check matrix into the data and the error correction code read from the memory core, andgenerates a pre-syndrome by substituting the data and the error correction code, read from the memory core, into [the second check matrix]-[the first check matrix], and generates the second syndrome by adding the pre-syndrome and the first syndrome.3. The memory according to claim 1 , wherein the error correction code is a Reed-Solomon type code. ...

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Номер записи: 68
22-03-2018 дата публикации

APPARATUSES AND METHODS FOR GENERATING PROBABILISTIC INFORMATION WITH CURRENT INTEGRATION SENSING

Номер: US20180081753A1
Автор: Helm Mark A., Kaynak Mustafa N., Khayat Patrick R., Parthasarathy Sivagnanam, Yip Aaron S.
Принадлежит: MICRON TECHNOLOGY, INC.

Methods and apparatuses for generating probabilistic information for error correction using current integration are disclosed. An example method comprises sensing a first plurality of memory cells based on a first sense threshold, responsive to sensing the first plurality of cells, associating a first set of probabilistic information with the first plurality of memory cells, sensing a second plurality of memory cells based on a second sense threshold, responsive to sensing the second plurality of memory cells, associating a second set of probabilistic information with the second plurality of memory cells, and performing an error correction operation on the first and second pluralities of memory cells based, at least in part, on the first and second values. 1. A method comprising:sensing a first plurality of memory cells based on a first sense threshold;responsive to sensing the first plurality of cells, identifying a portion of the first plurality of memory cells as having a voltage stored thereon within a first range of voltages;sensing a second plurality of memory cells based on a second sense threshold;responsive to sensing the second plurality of memory cells, identifying a portion of the second plurality of memory cells as having a voltage stored thereon within a second range of voltages; andperforming an error correction operation on the first and second pluralities of memory cells based, at least in part, on the identified first and second ranges of voltages.2. The method of claim 1 , further comprising:determining a number of memory cells in the portion of the second plurality of memory cells;determining whether the number of memory cells in the portion of the second plurality of memory cells exceeds a threshold;responsive to the number of memory cell in the portion of the second plurality of memory cells exceeding the threshold, sensing a third plurality of memory cells based on a third sense threshold; andidentifying a portion of the third plurality of ...

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Номер записи: 69
31-03-2022 дата публикации

Data storage device channel encoding current data using redundancy bits generated over preceding data

Номер: US20220103188A1
Автор: Iouri Oboukhov, Niranjay RAVINDRAN, Richard L. Galbraith
Принадлежит: Western Digital Technologies Inc

A data storage device is disclosed comprising a non-volatile storage medium (NVSM). A first block of data is channel encoded into first channel data based on a channel code constraint, and the first channel data is error correction encoded to generate first redundancy bits. A second block of data is channel encoded into second channel data based on the channel code constraint and the first redundancy bits, and the first channel data and the second channel data are error correction encode to generate second redundancy bits. A third block of data is channel encoded into third channel data based on the channel code constraint and the second redundancy bits. The first, second and third channel data and the first and second redundancy bits are stored in the NVSM.

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Номер записи: 70
31-03-2022 дата публикации

TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF

Номер: US20220103190A1
Автор: Jeong Hong-Sil, KIM Kyung-Joong, LOBETE Daniel Ansorregui, MOUHOUCHE Belkacem, MYUNG Se-Ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding of input bits based on a parity check matrix including information word bits and parity bits, the LDPC codeword including a plurality of bit groups each including a plurality of bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the interleaver is further configured to interleave the LDPC codeword such that a bit included in a predetermined bit group from among the plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol. 2. The receiving method of claim 1 , wherein each of the plurality of groups comprises 360 values.3. The receiving method of claim 1 , wherein π(j) is determined based on at least one of the code length claim 1 , a modulation method for the signal claim 1 , and the code rate.5. The transmitting method of claim 4 , wherein each of the plurality of bit groups comprises 360 bits. This is a Continuation of U.S. application Ser. No. 16/443,321 filed Jun. 17, 2019, which is a Continuation of U.S. application Ser. No. 15/783,162 filed Oct. 13, 2017, which issued as U.S. Pat. No. 10,367,533, which is a Continuation of U.S. application Ser. No. 14/716,132 filed May 19, 2015, which issued as U.S. Pat. No. 9,800,269 on Oct. 24, 2017, and which claims priority from U.S. Provisional Application No. 62/001,155 filed on May 21, 2014 and Korean Patent Application No. 10-2015-0000697 filed on Jan. 5, 2015, the disclosures of which are incorporated herein by reference in their entirety.Apparatuses and methods consistent with exemplary embodiments relate to a transmitting apparatus which processes and transmits data, and an interleaving method thereof.In the 21st century information-oriented society, broadcasting communication services are ...

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Номер записи: 71
25-03-2021 дата публикации

METHOD AND APPARATUS FOR GENERATING AN LDPC CODE WITH A REQUIRED ERROR FLOOR

Номер: US20210091793A1
Автор: KUO Shiuan-Hao
Принадлежит:

A method for generating an LDPC (low-density parity check) code with a required error floor, comprising: using a parity generation circuit to generate an LDPC code; using a detection circuit to detect the LDPC code according to a plurality of trapping set cores in a database and to generate at least one piece of trapping-set-core information; using a verification circuit to perform an important sampling simulation according to the LDPC code and each trapping-set-core information separately to obtain an estimated error floor for each trapping-set-core information; using the verification circuit to separately compare each of the estimated error floors with an expected error floor; and when all of the estimated error floors are lower than or equal to the expected error floor, using the verification circuit to output the LDPC code. 1. A method for generating an LDPC (low-density parity check) code with a required error floor , comprising:using a parity generation circuit to generate an LDPC code;using a detection circuit to detect the LDPC code according to a plurality of trapping set cores in a database and to generate at least one piece of trapping-set-core information for the LDPC code, wherein each trapping-set-core information comprises one of the trapping set cores, and an appearance number and an appearance position of it in the LDPC code, and wherein the trapping set core comprised in each trapping-set-core information are different from each other;using a verification circuit to perform an important sampling simulation according to the LDPC code and each trapping-set-core information separately to obtain an estimated error floor for each trapping-set-core information;using the verification circuit to separately compare each of the estimated error floors with an expected error floor; andwhen all of the estimated error floors are lower than or equal to the expected error floor, using the verification circuit to output the LDPC code.2. The method as claimed in ...

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Номер записи: 72
25-03-2021 дата публикации

METHOD AND APPARATUS FOR CHANNEL ENCODING/DECODING IN A COMMUNICATION OR BROADCASTING SYSTEM

Номер: US20210091884A1
Автор: AHN Seok-Ki, JANG Min, Jeong Hong-Sil, Kim Jae-Yoel, KIM Kyung-Joong, MYUNG Seho
Принадлежит:

A channel encoding method in a communication or broadcasting system is provided. The channel encoding method includes reading a first sequence corresponding to a parity check matrix, converting the first sequence to a second sequence by applying a certain rule to a block size corresponding to a parity check matrix and the first sequence, and encoding information bits based on the second sequence. The block size has at least two different integer values. 1. A method for encoding in a communication or broadcasting system supporting a low density parity check (LDPC) code , the method comprising:identifying a base matrix consisting of 0 and 1;identifying a predetermined number based on the base matrix;identifying a block size Z based on the predetermined number;identifying, from among a plurality of sets of block sizes, a set of block sizes associated with the block size Z;identifying an exponent matrix including at least one integer value based on the identified set of block sizes;obtaining a parity check matrix based on the base matrix, the block size Z, and the exponent matrix; andencoding information bits based on the parity-check matrix,wherein the parity-check matrix includes a submatrix consisting of Z×Z zero matrices and Z×Z circular permutation matrices.2. The method of claim 1 ,wherein a multiplication of the predetermined number and the block size Z is larger than or equal to a size of the information bits.3. The method of claim 1 , wherein the identifying of the block size comprises:identifying a size of the information bits to encode; andidentifying the block size based on the size of the information bits.4. The method of claim 1 , wherein the set of block sizes is associated with block sizes determined among {(A+i) claim 1 , 2(A+i) claim 1 , 2(A+i) claim 1 , . . . claim 1 , 2(A+i)} claim 1 , where i=0 claim 1 , 1 claim 1 , 2 claim 1 , . . . claim 1 , A−1 claim 1 , and A and S are positive integers.5. The method of claim 4 , wherein A is 8 and S is 4.6. The ...

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Номер записи: 73
31-03-2016 дата публикации

Non-binary low density parity check (NB-LDPC) codes for communication systems

Номер: US20160094246A1
Автор: Shen Ba-Zhong, Vasista Srinivasan Ranganathan Sudarsan
Принадлежит: BROADCOM CORPORATION

A communication device (alternatively, device) includes a processor configured to support communications with other communication device(s) and to generate and process signals for such communications. In some examples, the device includes a communication interface and a processor, among other possible circuitries, components, elements, etc. to support communications with other communication device(s) and to generate and process signals for such communications. The device receives a non-binary low density parity check (NB-LDPC) coded signal. The device then decodes the NB-LDPC coded signal using a NB-LDPC matrix to generate estimates of information bits encoded therein. The NB-LDPC matrix is characterized by a base proto-matrix having elements that represent sub-matrices, and the elements are selected from a finite Galois field that includes symbols. In another example, the device encodes other information bits using a generator matrix to generate another NB-LDPC coded signal and then transmits this other NB-LDPC coded signal. 1. A communication device comprising: receive a non-binary low density parity check (NB-LDPC) coded signal; and', 'decode the NB-LDPC coded signal using a NB-LDPC matrix to generate estimates of information bits encoded therein, wherein the NB-LDPC matrix is characterized by a base proto-matrix having a plurality of elements that represent a plurality of sub-matrices, wherein the plurality of elements are selected from a finite Galois field that includes 2-bit symbols, wherein a plurality of edges specify connectivity between a plurality of check nodes and a plurality of variable nodes based on the NB-LDPC matrix, and wherein each edge of a subset of edges of the plurality of edges corresponding to a sub-matrix of the plurality of sub-matrices that is based on a non-zero-valued 2-bit symbol has a common weight., 'a processor configured to2. The communication device of claim 1 , wherein:a zero-valued 2-bit symbol within the base proto-matrix ...

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Номер записи: 74
21-03-2019 дата публикации

MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY

Номер: US20190089377A1
Автор: KUMANO Yuta, Sakamaki Yoshiyuki, Uchikawa Hironori
Принадлежит: Toshiba Memory Corporation

According to one embodiment, a memory system comprises an encoder that encodes by a graph code and a data holding unit that holds data to be used in encoding. A check matrix of the graph code includes first to sixth submatrices, and the encoder produces a first vector obtained by multiplying an information word and the first submatrix, produces a second vector obtained by multiplying the information word and the third submatrix, produces a third vector obtained by multiplying the first vector and the fifth submatrix inverted in sign, produces a fourth vector obtained by adding the third vector and the second vector, produces a first parity obtained by multiplying the fourth vector and the data, produces a fifth vector obtained by multiplying the first parity and the second submatrix inverted in sign, and produces a second parity obtained by adding the fifth vector and the first vector. 1. A memory system which can be connected to a host , comprising:a nonvolatile memory;an encoder that encodes at least a part of user data received from the host as an information word by a graph code;an encode data holding unit that holds for-encoding data to be used when the encoder encodes the information word; anda memory interface that writes a code word subjected to the encoding into the nonvolatile memory,wherein a check matrix of the graph code includes first to sixth submatrices,wherein the encoder:produces a first vector obtained by multiplying the information word and the first submatrix,produces a second vector obtained by multiplying the information word and the third submatrix,produces a third vector obtained by multiplying the first vector and the fifth submatrix inverted in sign,produces a fourth vector obtained by adding the third vector and the second vector,produces a first parity obtained by multiplying the fourth vector and the for-encoding data,produces a fifth vector obtained by multiplying the first parity and the second submatrix inverted in sign, andproduces ...

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Номер записи: 75
21-03-2019 дата публикации

DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD

Номер: US20190089378A1
Автор: Hirayama Yuichi, Michael Lachlan, MUHAMMAD Nabil Sven Loghin, Shinohara Yuji, Yamamoto Makiko
Принадлежит: SONY CORPORATION

The present technology relates to a data processing apparatus and a data processing method that are able to secure good communication quality in data transmission using an LDPC code. One symbol is mapped to one of 16 signal points prescribed in 16APSK, with code bits of four bits of an LDPC code having a code length of 16200 bits and a code rate of 7/15 as one symbol. 16 signal points prescribed in 16APSK are four signal points on an inner circle and 12 signal points on an outer circle, and a radius ratio of the inner circle and the outer circle is 5.25. The present technology may be applied to, for example, a case of performing data transmission using an LDPC code. 1a mapping unit that maps a symbol to any one of 16 signal points prescribed in 16APSK, with code bits of four bits of an LDPC code having a code length of 16200 bits and a code rate of 7/15 as one symbol,wherein the 16 signal points prescribed in 16APSK are four signal points on an inner circle and 12 signal points on an outer circle, andwherein a radius ratio of the inner circle and the outer circle is 5.25.. A data processing apparatus comprising: This application is a continuation of U.S. application Ser. No. 14/782,713, filed Oct. 6, 2015, which is a National Stage of PCT/JP2014/061154, filed Apr. 21, 2014, and claims the benefit of priority under 35 U.S.C. § 119 of Japanese Patent Application No.2013-096994, filed May 2, 2013. The entire contents of each application is incorporated herein by reference.The present invention relates to a data processing apparatus and a data processing method, and in particular, relates to a data processing apparatus and a data processing method which are able to secure good communication quality in data transmission using, for example, an LDPC code.A low density parity check (LDPC) code has a high error correction ability, and has been widely adopted in a transmission scheme including satellite digital broadcasting such as, for example, digital video broadcasting ( ...

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Номер записи: 76
30-03-2017 дата публикации

TECHNIQUES FOR ADAPTIVE LDPC DECODING

Номер: US20170093428A1
Автор: Prabhakar Abhiram, Wang Chung-Li, Yen Johnson
Принадлежит:

Techniques are described for an adaptive low density parity check (LDPC) decoder. The techniques include receiving a first set of values corresponding to a first low density parity check codeword and noise, performing a first plurality of iterations of an iterative decoding algorithm using a first set of decoding parameters to decode the received first set of values, comparing a metric with a first threshold, and upon determining that the metric is larger than the threshold: selecting a second set of decoding parameters for the iterative LDPC decoder and performing a second plurality of iterations of the iterative LDPC decoding algorithm using the second set of decoding parameters to decode the received first set of values and generate a first set of decoded bits. 1. A method for adaptive decoding , comprising:receiving a first set of values corresponding to a first low density parity check (LDPC) codeword and noise;performing a first plurality of iterations of an iterative decoding algorithm using a first set of decoding parameters to decode the received first set of values;comparing a metric with a first threshold; and selecting a second set of decoding parameters for the iterative LDPC decoder; and', 'performing a second plurality of iterations of the iterative LDPC decoding algorithm using the second set of decoding parameters to decode the received first set of values and generate a first set of decoded bits., 'upon determining that the metric is larger than the first threshold2. The method of claim 1 , wherein the second set of decoding parameters comprises one or more scaling factors and one or more initial log likelihood ratio (LLR) values.3. The method of claim 1 , wherein at least one of the scaling factors in the second set of decoding parameters is different from a corresponding scaling factor in the first set of decoding parameters.4. The method of claim 1 , wherein at least one of the initial log likelihood ratio (LLR) values is in the second set of ...

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Номер записи: 77
30-03-2017 дата публикации

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 3/15 AND QUADRATURE PHASE SHIFT KEYING, AND BIT INTERLEAVING METHOD USING SAME

Номер: US20170093437A1
Автор: HUR Nam-Ho, KIM Heung-Mook, KWON Sun-Hyoung, LEE Jae-Young, PARK Sung-Ik
Принадлежит:

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation. 1. A bit interleaving method , comprising:storing a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15;generating an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword; andstoring the interleaved codeword corresponding to a modulator for quadrature phase shift keying (QPSK) modulation.2. The bit interleaving method of claim 1 , wherein the parallel factor is 360 claim 1 , and the bit group includes 360 bits.4. The bit interleaving method of claim 1 , wherein the interleaving is performed using the following equation using permutation order:{'br': None, 'sub': j', 'π(j)', 'group, 'Y=X0≦j≦N'}{'sub': π(j)', 'j, 'where Xis the π(j) th bit group, Yis an interleaved j-th bit group, and π(j) is a permutation order for bit group-based interleaving.'}5. The bit interleaving method of claim 4 , wherein the permutation order corresponds to an interleaving sequence represented by the following interleaving sequence{'br': None, '={75 170 132 174 7 111 30 4 49 133 50 160 92 106 27 126 116 178 41 166 88 84 80 153 103 51 58 107 167 39 108 24 145 96 74 65 8 40 76 140 44 68 125 119 82 53 152 102 38 28 86 162 171 61 93 147 117 32 150 26 59 3 148 173 141 130 154 97 33 172 115 118 127 6 16 0 143 9 100 67 98 110 2 169 47 83 164 155 ...

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Номер записи: 78
09-04-2015 дата публикации

Low density parity check encoder having length of 64800 and code rate of 7/15, and low density parity check encoding method using the same

Номер: US20150100844A1
Автор: Heung-Mook Kim, Nam-Ho Hur, Sun-Hyoung Kwon, Sung-Ik Park
Принадлежит: Electronics and Telecommunications Research Institute ETRI

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 7/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

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Номер записи: 79
09-04-2015 дата публикации

Transmitting apparatus and signal processing method thereof

Номер: US20150100845A1
Автор: Hong-Sil Jeong, Kyung-Joong Kim, Se-Ho Myung
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver is formed of a plurality of columns each including a plurality of rows and includes a block interleaver configured to divide each of the plurality of columns into a first part and a second part and interleave the LDPC codeword, the number of rows constituting each column divided into the first part is determined differently depending upon the modulation method, wherein the number of rows constituting each column divided into the second part is determined depending upon the number of rows constituting each column divided into the first part.

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Номер записи: 80
07-04-2016 дата публикации

Reception apparatus and reception method

Номер: US20160099725A1
Автор: Choo Eng Yap, Kiyotaka Kobayashi, Yutaka Murakami
Принадлежит: Panasonic Intellectual Property Corp of America

In a multi-antenna communication system using LDPC codes, a simple method is used to effectively improve the received quality by performing a retransmittal of less data without restricting applicable LDPC codes. In a case of a non-retransmittal, a multi-antenna transmitting apparatus transmits, from two antennas, LDPC encoded data formed by LDPC encoding blocks. In a case of a retransmittal, the multi-antenna transmitting apparatus uses a transmission method, in which the diversity gain is higher than in the previous transmission, to transmit only a part of the LDPC encoded data as previously transmitted. For example, the only the part of the LDPC encoded data to be re-transmitted is transmitted from the single antenna.

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Номер записи: 81
07-04-2016 дата публикации

ENCODING IN UPLINK MULTI-USER MIMO AND OFDMA TRANSMISSIONS

Номер: US20160099796A1
Автор: Ding Gang, Kim Youhan, Tian Bin, Vermani Sameer, Yang Lin
Принадлежит:

A method, an apparatus, and a computer-readable medium for wireless communication are provided. In one aspect, the apparatus is configured to determine a number of data symbols for transmitting a data payload. The apparatus is configured to determine a number of payload bits for transmitting the data payload based on the determined number of data symbols. The apparatus is configured to transmit a data frame. The data frame includes a signal field and data symbols encoded based on the data payload, the determined number of data symbols, and the determined number of payload bits, in which the data symbols are encoded using LDPC encoding or BCC encoding. 1. A method of wireless communication for a station , comprising:determining a number of data symbols for transmitting a data payload;determining a number of payload bits for transmitting the data payload based on the determined number of data symbols; andtransmitting a data frame, wherein the data frame comprises a signal field and data symbols encoded based on the data payload, the determined number of data symbols, and the determined number of payload bits, wherein the data symbols are encoded using low density polarity check (LDPC) encoding or binary convolution code (BCC) encoding.2. The method of claim 1 , wherein the signal field comprises at least one of a padding bit claim 1 , a packet length claim 1 , a space-time block code bit claim 1 , or a modulation and coding scheme value.3. The method of claim 1 , further comprising encoding the data payload using LDPC encoding or BCC encoding for uplink multi-user multiple-input-multiple-output (MU-MIMO) transmission or uplink orthogonal frequency-division multiple access (OFDMA) transmission to an access point.4. The method of claim 1 , further comprising receiving a trigger message claim 1 , wherein the trigger message includes a mandatory time duration for the data frame.5. The method of claim 4 , wherein the station is associated with a space-time block code value ...

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Номер записи: 82
28-03-2019 дата публикации

MIN-SUM DECODING FOR LDPC CODES

Номер: US20190097656A1
Автор: Bhatia Aman, Kumar Naveen, Prabhakar Abhiram, XIONG Chenrong, Zhang Fan
Принадлежит:

Techniques are described for performing a check node update (CNU) as part of iterative decoding of a low density-parity check (LDPC) code. The CNU uses a min-sum decoding approach that monitors whether two values received in messages from two variable nodes connected to a check nodes are equal and are the minimum value among the values received by the check nodes from other variable nodes connected thereto. Upon detecting such an event, the minimum value is adjusted by reducing it by an adjustment value to generate an adjusted minimum value. This adjusted minimum value approximates the minimum value that a sum-product algorithm (SPA) decoding approach would have generated. The adjusted minimum value is included in a response message sent from the check node to a variable node. The bit corresponding to that variable node is decoded based on this adjusted minimum value. 1. A low density-parity check (LDPC) method involving a min-sum based decoding approach and implemented on an LDPC decoder , the LDPC method comprising:receiving, by a check node of the LDPC decoder from a first variable node of the LDPC decoder, a first value indicating a reliability of a bit value for a first bit of an LDPC codeword, the first variable node corresponding to the first bit and connected to the check node;determining, by the check node, that the first value is equal to a minimum value stored by the check node for a second variable node of the LDPC decoder, the second variable node corresponding to a second bit of the LDPC codeword and connected to the check node;generating, by the check node in response to determining that the first value is equal to the minimum value, an adjusted minimum value by at least updating the minimum value according to an adjustment value; andsending, by the check node to a third variable node of the LDPC decoder, the adjusted minimum value, the third variable node corresponding to a third bit of the LDPC codeword and connected to the check node,wherein the ...

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Номер записи: 83
28-03-2019 дата публикации

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 2/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

Номер: US20190097658A1
Автор: HUR Nam-Ho, KIM Heung-Mook, KWON Sun-Hyoung, PARK Sung-Ik
Принадлежит:

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to . The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). 1. A low density parity check (LDPC) decoder , comprising:a receiving unit configured to receive a signal corresponding to an LDPC codeword having a length of 64800 and a code rate of 2/15, the LDPC codeword encoded using a sequence corresponding to a parity check matrix (PCM); anda decoding unit configured to perform decoding the received signal, the decoding corresponding to the parity check matrix.3. The LDPC decoder of claim 2 , wherein the LDPC codeword comprises a systematic part corresponding to information bits and having a length of 8640 claim 2 , a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 1800 claim 2 , and a second parity part corresponding to an identity matrix included in the PCM and having a length of 54360.4. The LDPC decoder of claim 3 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part claim 3 , that is claim 3 , 8640 claim 3 , by a circulant permutation matrix (CPM) size corresponding to the PCM claim 3 , that is claim 3 , 360 claim 3 , and a value obtained by dividing a length of the first parity part claim 3 , that is claim 3 , 1800 claim 3 , by the CPM size.5. The LDPC decoder of claim 2 , wherein the LDPC codeword is generated by performing accumulation with respect to a memory and the accumulation is performed at parity bit addresses that are updated using the sequence.6. The LDPC decoder of claim 5 , wherein the ...

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Номер записи: 84
16-04-2015 дата публикации

Multiple component codes based generalized low-density parity-check codes for high-speed optical transport

Номер: US20150106680A1
Автор: Ivan B. Djordjevic, Ting Wang
Принадлежит: NEC Laboratories America Inc

Systems and methods for data transport, including encoding streams of input data using generalized low-density parity check (GLDPC) encoders, the one or more GLDPC encoders being configured to generate GLDPC coded data streams using a plurality of component local codes to improve error correction strength, employ single-parity checks and two or more local block codes during generation of the GLDPC codes, and enable continuous tuning of code rate using the generated GLDPC codes. Signals may be generated using mappers, the mappers configured to assign bits of signals to signal constellations and to associate the bits of the signals with signal constellation points. The signal may be modulated using an I/Q or 4-D modulator composed of one polarization beam splitter, two I/Q modulators, and one polarization beam combiner. The modulated signals are multiplexed using a mode-multiplexer, transmitted over a transmission medium, and the signals are received and decoded using GLDPC decoders.

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Номер записи: 85
13-04-2017 дата публикации

EFFICIENT LDPC ENCODER FOR IRREGULAR CODE

Номер: US20170104499A1
Автор: Bhatia Aman, Yen Johnson, Yuan Wei-Hao, Zeng Lingqi
Принадлежит:

A first memory location stores circulant contents of portions A, C, E, and B of a parity check matrix H. A second memory location stores circulant column counts of the portions A, C, E, and B. A third memory location stores a dense matrix equal to (ETB+D), where T is an identity matrix and D and T are also portions of the parity check matrix H. First and second parity information is generated in response to receiving information data. Generating the first and second parity information includes accessing the circular content of the portions A, C, E, and B of a parity check matrix H and accessing the circulant column counts of the portions A, C, E, and B. 1. A memory system comprising:an array of memory locations; and a first encoder memory location storing circulant contents of A, C, E, and B, where A, C, E, and B are portions of a parity check matrix H;', 'a second encoder memory location storing circulant column counts of A, C, E, and B; and', {'sup': −1', '−1', 't, 'a third encoder memory location storing a dense matrix, where the dense matrix is equal to (ETB+D), where T is an identity matrix and D and T are also portions of the parity check matrix H, wherein the encoder is configured to receive information data, u, and configured to, 'generate a first product by multiplying the information data by (E*A+C), wherein generating the first product includes accessing the first and second encoder memory location;', {'sub': '1', 'sup': 't', 'generate first parity information Pby multiplying the dense matrix by the first product; and'}, {'sub': 2', '1, 'sup': t', 't', 't, 'generate second parity information P, where the second parity information equals (A*u+B*P).'}], 'an encoder, the encoder comprising2. The memory system of claim 1 , wherein multiplying the information data by (E*A+C) further includes:determining a start of the circulant content of E by accessing a circulant pointer that points to a first address of the first encoder memory location that marks the start ...

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Номер записи: 86
26-03-2020 дата публикации

Data processing apparatus and data processing method

Номер: US20200099396A1
Автор: Makiko Yamamoto, Yuji Shinohara
Принадлежит: SATURN LICENSING LLC

The present technology relates to a data processing apparatus and a data processing method which enable provision of an LDPC code that achieves good error-rate performance. An LDPC encoding unit performs encoding using an LDPC code having a code length of 64800 bits and a code rate of 18/30, 19/30, 20/30, 21/30, 22/30, or 23/30. The LDPC code includes information bits and parity bits, and a parity check matrix H is composed of an information matrix portion corresponding to the information bits of the LDPC code, and a parity matrix portion corresponding to the parity bits. The information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table that shows positions of elements of 1 in the information matrix portion in units of 360 columns. The present technology may be applied to LDPC encoding and LDPC decoding.

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Номер записи: 87
09-06-2022 дата публикации

Load Balanced Decoder Systems And Methods

Номер: US20220182076A1
Автор: Ashjaee Spanta, Lin Jiun-Yee, Lui Gee Hang
Принадлежит: Intel Corporation

A decoding circuit system includes a load balancing scheduler circuit, a full range decoder circuit, and an auxiliary decoder circuit. The load balancing scheduler circuit provides codewords that each have a lifting factor greater than a predefined value to the full range decoder circuit. The full range decoder circuit decodes the codewords that each have a lifting factor greater than the predefined value to generate first decoded output data. The load balancing scheduler circuit provides codewords that each have a lifting factor less than the predefined value to the auxiliary decoder circuit. The auxiliary decoder circuit decodes the codewords that each have a lifting factor less than the predefined value to generate second decoded output data. 1. A decoding circuit system comprising:a load balancing scheduler circuit;a full range decoder circuit, wherein the load balancing scheduler circuit provides codewords that each have a lifting factor greater than a predefined value to the full range decoder circuit, and wherein the full range decoder circuit decodes the codewords that each have a lifting factor greater than the predefined value to generate first decoded output data; anda first auxiliary decoder circuit, wherein the load balancing scheduler circuit provides codewords that each have a lifting factor less than the predefined value to the first auxiliary decoder circuit, and wherein the first auxiliary decoder circuit decodes the codewords that each have a lifting factor less than the predefined value to generate second decoded output data.2. The decoding circuit system of claim 1 , wherein the predefined value equals a point in a curve for a probability distribution of the lifting factors of the codewords at which an area under the curve up to the predefined value is equal to an area under the curve from the predefined value up to a maximum value of the curve.3. The decoding circuit system of further comprising:a second auxiliary decoder circuit, wherein the ...

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Номер записи: 88
13-05-2021 дата публикации

SIMPLIFIED CHECK NODE PROCESSING IN NON-BINARY LDPC DECODER

Номер: US20210143838A1
Автор: Boutillon Emmanuel, MARCHAND Cédric
Принадлежит: UNIVERSITE DE BRETAGNE SUD

Embodiments of the invention provide a decoder comprising at least one check node processing unit configured to receive at least three variable node messages from one or more variable node processing units and to determine one or more check node messages, wherein the at least one check node processing unit comprises at least two blocks of sub-check nodes, each block of sub-check node being configured to: 1. A decoder comprising at least one check node processing unit configured to receive at least three variable node messages from one or more variable node processing units and to determine one or more check node messages , wherein the at least one check node processing unit comprises at least two blocks of sub-check nodes , each block of sub-check node being configured to:determine a set of sub-check node syndromes from at least one variable node message among said at least three variable node messages; anddetermine at least one check node message from at least one syndrome.2. The decoder of claim 1 , wherein it further comprises at least one message presorting unit configured to determine permuted variable node messages by applying one or more permutations to the at least three variable node messages claim 1 , each block of sub-check node being configured to determine said set of sub-check node syndromes from at least one permuted variable node message of said permuted variable node messages.3. The decoder of claim 1 , further comprising a block division unit configured to perform a division of at least one check node processing unit into at least two blocks of sub-check nodes using a set of block division parameters.4. The decoder of claim 1 , wherein at least one check node processing unit comprises at least two blocks of sub-check nodes claim 1 , at least one block of sub-check node implementing a syndrome sub-check node architecture and at least one block of sub-check node implementing a forward-backward architecture.5. The decoder of claim 3 , wherein the set ...

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Номер записи: 89
16-04-2020 дата публикации

Transformation of Binary Data to Non-Binary Data For Storage in Non-Volatile Memory

Номер: US20200115555A1
Автор: Jonas Andrew Goode, Niranjay RAVINDRAN, Richard Leo Galbraith
Принадлежит: Western Digital Technologies Inc

A data storage system and method are provided for storing data in non-volatile memory devices. Binary data is received for storage in a non-volatile memory device. The binary data is converted into non-binary data comprising base-X values, where X is an integer greater than two. The non-binary data is encoded to generate a codeword and the codeword is written to a wordline of the non-volatile memory device.

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Номер записи: 90
25-08-2022 дата публикации

TRANSMISSION METHOD AND RECEPTION METHOD

Номер: US20220271774A1
Автор: KOBAYASHI Kiyotaka, MURAKAMI Yutaka, YAP Choo Eng
Принадлежит:

In a multi-antenna communication system using LDPC codes, a simple method is used to effectively improve the received quality by performing a retransmittal of less data without restricting applicable LDPC codes. In a case of a non-retransmittal, a multi-antenna transmitting apparatus () transmits, from two antennas (A,B), LDPC encoded data formed by LDPC encoding blocks (A,B). In a case of a retransmittal, the multi-antenna transmitting apparatus () uses a transmission method, in which the diversity gain is higher than in the previous transmission, to transmit only a part of the LDPC encoded data as previously transmitted. For example, the only the part of the LDPC encoded data to be re-transmitted is transmitted from the single antenna (A). 1. A transmission apparatus comprising:an encoding circuit configured to encode data according to a parity check matrix of Low Density Parity Check coding to generate an encoded data sequence such that the encoded data sequence includes a first bit and a second bit, the parity check matrix having a first column and a second column to generate the first bit and the second bit, respectively; anda transmitting circuit configured to transmit an orthogonal frequency divisional multiplexing (OFDM) signal including the encoded data sequence and configured to retransmit an OFDM signal including the first bit without retransmitting the second bit, whereina first number of 1 bits in the first column is greater than a second number of 1 bits in the second column.2. A reception apparatus comprising: an orthogonal frequency divisional multiplexing (OFDM) signal including an encoded data sequence; and', 'an OFDM singal including a first retransmitted bit which is identical to a first bit included in the encoded data sequence, a second bit in the encoded data sequence having not been retransmitted; and, 'a receiving circuit configured to receivea decoding circuit configured to decode the encoded data sequence according to a parity check matrix ...

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Номер записи: 91
25-08-2022 дата публикации

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

Номер: US20220271775A1
Автор: IKEGAYA Ryoji, Shinohara Yuji, Yamamoto Makiko
Принадлежит:

The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes. 1. A receiver for receiving digital television signals , the receiver comprising:an input circuitry configured to receive encoded data, each 4 bits of which mapped to any one of 16 signal points of a modulation method; andprocessing circuitry configured toprocess the encoded data to produce a group-wise interleaved low density parity check (LDPC) codeword;process the group-wise interleaved LDPC codeword in a unit of a bit group of 360 bits to produce an LDPC codeword of an LDPC code; wherein an (i+1)-th bit group from a head of the LDPC codeword of the LDPC code is indicated by a bit group i, the LDPC codeword of the LDPC code has a sequence of bit groups 0 to 179, and the group-wise interleaved LDPC codeword has a following sequence of bit groups,0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 148, 152, 156, 160, 164, 168, 172, 176, 1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69, 73, 77, 81, 85, 89, 93, 97, 101, 105, 109, 113, 117, 121, 125, 129, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62, 66, 70, 74, 78, 82, 86, 90, 94, 98, 102, 106, 110, 114, 118, 122, 126, 130, 134, 138, 142, 146, 150, 154, 158, 162, 166, 170, 174, 178, 3, 7, 11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51, 55, 59, 63, 67, 71, 75, 79, 83, 87, 91, 95, 99, 103, 107, 111, 115, 119, 123, 127, 131, 135, 139, 143, 147, 151, 155, 159, 163, 167, 171, 175, 179,decode the LDPC codeword of the LDPC code to produce decoded data; andprocess the decoded data for presentation;wherein the LDPC code has a length N of of 64800 bits and a coding rate r of 13/15 and corresponds to a parity check matrix initial value table including the following, ...

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Номер записи: 92
11-05-2017 дата публикации

Non-Binary Low Density Parity Check Code Column Rotation

Номер: US20170132077A1
Автор: Shaohua Yang, Xuebin Wu, YANG Han
Принадлежит: Avago Technologies General IP Singapore Pte Ltd

An apparatus for processing data includes a storage medium operable to store encoded data, and a read channel circuit with a low density parity check encoder operable to encode data to generate the encoded data, and a low density parity check decoder operable to decode the encoded data retrieved from the storage medium. The read channel circuit is operable to perform a column rotation on the encoded data prior to storage and after retrieval before decoding.

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Номер записи: 93
10-05-2018 дата публикации

METHOD FOR CONTROLLING A CHECK NODE OF A NB-LDPC DECODER AND CORRESPONDING CHECK NODE

Номер: US20180131395A1
Автор: Boutillon Emmanuel, LEHNIGK-EMDEN Timo, SCHLÄFER Philipp
Принадлежит:

Some embodiments are directed to a method for controlling a check node of a NB-LDPC decoder. The check node receives dinput lists Uand delivers and delivers doutput lists V, with iϵ[1 . . . d]. Each input list and output list includes nelements and each element of the input or output lists includes a reliability value associated to a symbol of a Galois Field GF(q) with q>n. The input elements and output elements are sorted according to the reliability values in the lists. The method is a syndrome-based method. The syndromes are sums of delements of input lists U. The method includes a step of syndrome calculation, a step of decorrelation and a step for generating the output list. 1. A method for controlling a check node of a decoder for decoding non-binary LDPC codes , the check node receiving dc input lists Ui of nm elements (Ui[j]) and delivering dc output lists Vi of n′m elements (Vi[j]) , with “iϵ[1 . . . ” “d”_“c” “]” , with dc>2 , each element of the input or output lists , called respectively input element and output , comprising a reliability value (LLR(Ui[j]) , LLR(Vi[j])) associated to a symbol (GF(Ui[j]) , GF(Vi[j])) of a Galois Field GF(q) with q>nm and q>n′m , the input elements and output elements being substantially sorted according to the reliability values respectively in the input list and output list , the method comprising:adding dc input elements of input lists Ui in order to generate a plurality of sums called syndromes, each of the input elements belonging to a distinctive input list among the dc input lists Ui and each syndrome comprising a reliability value which is the sum of the reliability values of the input elements and a symbol of the Galois field which is the sum of the symbols of the input elements in the Galois field,applying, for each output list Vi, a decorrelation to the syndromes by subtracting the input element of the input list Ui from the syndromes in order to generate decorrelated syndromes, andselecting, for each output ...

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Номер записи: 94
11-05-2017 дата публикации

DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT

Номер: US20170134049A1
Автор: CHANG HUNG-CHI, Hsiao Yu-Hua, Yen Heng-Lin
Принадлежит:

A decoding method, a memory storage device and a memory control circuit unit are provided. The method includes: determining an offset threshold value and a corresponding check matrix; receiving response data from a rewritable non-volatile memory module and performing an iterative decoding process. The check matrix includes at least one sub-matrix group, each sub-matrix of the sub-matrix group has a default dimension, and the offset threshold value is less than a default dimension value corresponding to the default dimension In the iterative decoding process, several default groups in a data set are shifted, so as to obtain first shift groups, while an offset of each first shift group with respect to a corresponding group among the default groups is not over the default threshold value. Therefore, decoding reference data used in the iterative decoding process may be generated more efficiently. 1. A decoding method for a rewritable non-volatile memory module , comprising:determining an offset threshold value and a check matrix corresponding to the offset threshold value, wherein the check matrix comprises at least one sub-matrix group, each sub-matrix of the at least one sub-matrix group has a default dimension, the offset threshold value is less than a default dimension value corresponding to the default dimension, and the at least one sub-matrix group comprises a first sub-matrix group;transmitting a read command sequence, wherein the read command sequence instructs to read a physical unit of the rewritable non-volatile memory module;receiving response data corresponding to the read command sequence; andperforming an iterative decoding process on the response data, generating a data set corresponding to the response data, wherein the data set comprises a plurality of default groups;', 'shifting the default groups according to a plurality of sub-matrices belonging to the first sub-matrix group to obtain a plurality of first shift groups, wherein an offset of each ...

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Номер записи: 95
11-05-2017 дата публикации

Channel coding framework for 802.11ay and larger block-length ldpc codes for 11ay with 2-step lifting matrices and in-place property

Номер: US20170134050A1
Автор: Eran Pisek, RAKESH Taori, Shadi Abu-Surra, Thomas Henige
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Methods and apparatuses for coding a codeword. An apparatus for decoding the codeword includes a memory configured to receive the codeword encoded based on a low-density parity check (LDPC) code H-matrix and a two-step lifting matrix and processing circuitry configured to decode the received codeword. An apparatus for encoding the codeword includes memory configured to store information bits to be encoded into the codeword and processing circuitry configured to encode the codeword based on based on a LDPC code H-matrix and a two-step lifting matrix. A code length of the LDPC code H-matrix lifted by the two-step lifting matrix is an integer multiple of 672 bits. The LDPC code block H-matrix may be an IEEE 802.11ad standard LDPC coding matrix. The two-step lifting matrix can be one of a plurality of two-step lifting matrices to generate a family of LDPC codes.

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Номер записи: 96
03-06-2021 дата публикации

DYNAMIC SELF-CORRECTION OF MESSAGE RELIABILITY IN LDPC CODES

Номер: US20210165712A1
Автор: Kwok Zion S., Mitra Debarnab, MOTWANI RAVI H.
Принадлежит: Intel Corporation

An embodiment of an electronic apparatus comprises one or more substrates, and logic coupled to the one or more substrates, the logic to detect unreliable messages between check nodes and variable nodes in association with an error correction operation, determine respective degrees of unreliability for the unreliable messages, and reduce an influence of the unreliable messages on the error correction operation, as compared to an influence of reliable messages between the check nodes and the variables nodes, based on the determined respective degrees of unreliability. Other embodiments are disclosed and claimed. 1. An electronic apparatus , comprising:one or more substrates; and detect unreliable messages between check nodes and variable nodes in association with an error correction operation,', 'determine respective degrees of unreliability for the unreliable messages, and', 'reduce an influence of the unreliable messages on the error correction operation, as compared to an influence of reliable messages between the check nodes and the variables nodes, based on the determined respective degrees of unreliability., 'logic coupled to the one or more substrates, the logic to2. The apparatus of claim 1 , wherein the logic is further to:increase a reliability factor of reliable messages sent from the check nodes to the variables nodes and keep unreliable messages sent from the check nodes to the variables nodes unchanged to reduce the influence of the unreliable messages sent from the check nodes to the variable nodes.3. The apparatus of claim 1 , wherein the logic is further to:reduce a reliability factor of unreliable messages sent from the variable nodes to the check nodes and keep the reliable messages sent from the variable nodes to the check nodes unchanged to reduce the influence of unreliable messages sent from the variable nodes to the check nodes.4. The apparatus of claim 1 , wherein the logic is further to:calculate a message to be sent from a check node to a ...

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Номер записи: 97
23-04-2020 дата публикации

Simplified, presorted, syndrome-based, extended min-sum (ems) decoding of non-binary ldpc codes

Номер: US20200127683A1
Автор: Cédric MARCHAND, Emmanuel Boutillon
Принадлежит: UNIVERSITE DE BRETAGNE SUD

Embodiments of the invention provide a check node processing unit ( 25 ) configured to determine at least one check node message to decode a signal encoded using a NB-LDPC code, the check node processing unit comprising: a data link to one or more message presorting units ( 24 ) configured to determine permuted variable node messages by applying one or more permutations to at least three variable node messages generated by one or more variable node processing units ( 23 ); a syndrome calculation unit ( 26 ) configured to determine a set of syndromes from the at least three permuted variable node messages, a syndrome comprising binary values; a decorrelation and permutation unit ( 27 ) configured, for each check node message of a given index, to: Determine a permuted index by applying to said given index the inverse of the one or more permutations; Select at least one valid syndrome in the set of syndromes, a valid syndrome comprising a binary value associated with said permuted index equal to a given value; Determine, at least one candidate check node component from said at least one valid syndrome; a selection unit ( 28 ) configured to determine at least one check node message from said at least one candidate check node component.

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Номер записи: 98
03-06-2021 дата публикации

VARIABLE NODE PROCESSING METHODS AND DEVICES FOR MESSAGE-PASSING DECODING OF NON-BINARY CODES

Номер: US20210167799A1
Автор: Boutillon Emmanuel, HARB Hassan, MARCHAND Cédric
Принадлежит: UNIVERSITE DE BRETAGNE SUD

Embodiments of the invention provide a variable node processing unit () for a non-binary error correcting code decoder, the variable node processing unit () being configured to receive one check node message and intrinsic reliability metrics, and to generate one variable node message from auxiliary components derived from said one check node message and intrinsic reliability metrics, the intrinsic reliability metrics being derived from a received signal, an auxiliary component comprising an auxiliary symbol and an auxiliary reliability metrics associated with said auxiliary symbol, wherein the variable node processing unit () comprises: 1. A variable node processing unit for a non-binary error correcting code decoder , the variable node processing unit being configured to receive one check node message and intrinsic reliability metrics , and to generate one variable node message from auxiliary components derived from said one check node message and intrinsic reliability metrics , the intrinsic reliability metrics being derived from a received signal , an auxiliary component comprising an auxiliary symbol and an auxiliary reliability metrics associated with said auxiliary symbol , wherein the variable node processing unit comprises:a sorting and redundancy elimination unit configured to process iteratively the auxiliary components and to determine components of the variable node message by iteratively sorting the auxiliary components according to a given order of the auxiliary reliability metrics and keeping a predefined number of auxiliary components comprising the auxiliary symbols that are the most reliable and all different from one another.2. The variable node processing unit of claim 1 , wherein the variable node processing unit comprises a calculation unit configured to determine a first auxiliary message from the check node message and the intrinsic reliability metrics and a second auxiliary message from the intrinsic reliability metrics associated with a ...

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Номер записи: 99
17-05-2018 дата публикации

SCHEDULING METHOD OF A PARITY CHECK MATRIX AND AN LDPC DECODER FOR PERFORMING SCHEDULING OF A PARITY CHECK MATRIX

Номер: US20180138924A1
Автор: CHOI YOUNGMIN, KIM Min Hyuk
Принадлежит: Electronics and Telecommunications Research Institute

Provided is a method of scheduling a parity check matrix, the method performed by a low-density parity-check (LDPC) decoder, the method including checking at least one non-zero elemental variable node in the parity check matrix, identifying a first index of a row of the parity check matrix in the at least one non-zero elemental variable node, extracting a column in which the at least one non-zero elemental variable node is positionable from the parity check matrix using the first index, and mapping the at least one non-zero elemental variable node to the extracted column based on an arrangement, and identifying a second index of the column of the parity check matrix through the mapped at least one non-zero elemental variable node. 1. A method of scheduling a parity check matrix , the method performed by a low-density parity-check (LDPC) decoder , the method comprising:checking at least one non-zero elemental variable node in the parity check matrix;identifying a first index of a row of the parity check matrix in the at least one non-zero elemental variable node;extracting a column in which the at least one non-zero elemental variable node is positionable from the parity check matrix using the first index, and mapping the at least one non-zero elemental variable node to the extracted column based on an arrangement; andidentifying a second index of the column of the parity check matrix through the mapped at least one non-zero elemental variable node.2. The method of claim 1 , further comprising:simultaneously performing a check node update (CNU) and a variable node update (VNU) using the first index and the second index.3. The method of claim 2 , wherein the second index indicates a column of the parity check matrix used along with a row corresponding to the first index to simultaneously perform the CNU and the VNU.4. The method of claim 1 , wherein the first index is identified by grouping the at least one non-zero elemental variable node of the parity check matrix ...

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Номер записи: 100