ПРИЕМНОЕ УСТРОЙСТВО, СПОСОБ ПРИЕМА, ПРОГРАММА И ПРИЕМНАЯ СИСТЕМА

Изобретение относится к приемному устройству, способу приема, носителю записи и приемной системе для выполнения процесса временного деперемежения, пригодного для приемников, совместимых с DVB-T.2. Техническим результатом является обеспечение возможности одновременного приема данных и сигналов управления одним и тем же устройством. Приемное устройство, соответствующее стандарту Т.2 цифрового телевещания, известному как DVB-T2, выполненное с возможностью выполнения декодирования кодов низкой плотности с контролем четкости (НПКЧ) для магистралей физического уровня (МФУ) (PLC), обозначающих потоки данных, и уровня 1 (L1), представляющего параметры передачи физического уровня. Приемное устройство включает в себя устройство декодирования НПКЧ, выполненное с возможностью того, что, когда сигнал кодированных НПКЧ данных и сигнал управления кодированной НПКЧ передачей передаются мультиплексированными, упомянутое устройство декодирования НПКЧ может декодировать как сигнал данных, так и сигнал управления ...

УСТРОЙСТВО ОБРАБОТКИ ДАННЫХ И СПОСОБ ОБРАБОТКИ ДАННЫХ

... 1. Устройство обработки данных, содержащее:блок кодирования, который кодирует информационный бит в LDPC-код, имеющий длину кода 16200 битов и кодовую скорость 12/15, на основании матрицы контроля четности кода разреженного контроля четности (LDPC),где LDPC-код включает в себя информационный бит и бит четности,где матрица контроля четности включает в себя информационную часть матрицы, соответствующую информационному биту, и часть матрицы четности, соответствующую биту четности,где информационная часть матрицы представлена таблицей начальных значений матрицы контроля четности игде таблица начальных значений матрицы контроля четности представляет собой таблицу, представляющую позиции элементов 1 в информационной части матрицы с интервалом 360 столбцов, и представляет собой2. Устройство обработки данных по п. 1,в котором, если строка исходной таблицы матрицы контроля четности представлена i и длина битов четности LDPC-кода представлена М,(2+360×(i-1))-й столбец матрицы контроля четности представляет ...

DVB-T2 OFDM interleaver with large symbol sequential write/PR read/PR write/sequential read mode and small symbol sequential write/PR read mode

In DVB-T symbols are interleaved on to OFDM sub-carriers. The existing interleavers write a first symbol to memory sequentially 132 and read it out according to a pseudo-random (PR) pattern 134. The next symbol is immediately written to these PR locations 120 and then read sequentially 126, and so on. The former operation (sequential write/PR read) produces better separation of initially adjacent symbols (Fig. 6). DVB-T2 uses OFDM transmission in 1/2/4/8/16/32k sub-carrier modes and allows switching between these modes. The invention switches interleaving schemes between the DVB-T one above and one where alternate symbols are assigned their own memory area to perform sequential write/PR read (Fig. 10), depending upon whether the number of carriers is less than half the number of memory locations. Thereby maximising symbol separation. The PR pattern is produced by feeding the output of an LFSR through a permutation matrix. The symbol/sub-carrier relationship ...

Interleaving or de-interleaving of data of variable rate

Data processing apparatus and method

DEVICE AND PROCEDURE FOR THE DATA PROCESSING

DEVICE AND PROCEDURE FOR THE DATA PROCESSING

DEVICE AND PROCEDURE FOR THE DATA PROCESSING

Data processing device and data processing method

Data process device, data process method, coding device, coding method

APPROACHES FOR ACHIEVING IMPROVED CAPACITY PLANS FOR A SATELLITE COMMUNICATIONS SYSTEM VIA INTERLEAVED BEAMS FROM MULTIPLE SATELLITES

A method is provided for interleaving frequency reuse plans of multiple satellites to form an aggregate frequency reuse cell plan. A first plurality of spot beams is generated by a first satellite for a first frequency reuse plan based on radio frequency (RF) spectrum bands. A second plurality of spot beams is generated by a second satellite for a second frequency reuse plan based on the RF spectrum bands. The first and second plurality of spot beams are interleaved to generate an aggregate frequency reuse cell plan. According to the aggregate frequency reuse plan, each of a first plurality of cells is covered by a combination of at least two of the plurality of spot beams of the first satellite, and each of a first plurality of cells is covered by a combination of at least two of the plurality of spot beams of the second satellite.

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 4/15 AND QUADRATURE PHASE SHIFT KEYING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.

TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

TIME INTERLEAVER, TIME DEINTERLEAVER, TIME INTERLEAVING METHOD, AND TIME DEINTERLEAVING METHOD

A convolution interleaver, which is included in a time interleaver and performs a convolution interleaving, comprises: a first switch for switching the connection destination of the input of the convolution interleaver to an end of any one of a plurality of branches; FIFO memories disposed in some of the plurality of branches except one branch in such a manner that the number of FIFO memories is different among said some of the plurality of branches; and a second switch for switching the connection destination of the output of the convolution interleaver to the other end of said any one of the plurality of branches. When a plurality of cells, the number of which is equal to the number of code words per frame, have passed, the first and second switches switch said connection destinations in such a manner that the branching of the destinations is performed by repeating the plurality of branches in turn.

TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

DATA-PROCESSING DEVICE AND DATA PROCESSING METHOD

This technology pertains to a data-processing device and a data processing method that make it possible to ensure good communication quality when using an LDPC code to transmit data. In group-wise interleaving, an LDPC code having a code length (N) of 16,200 bits and a code rate (r) of 10/15 or 12/15 is interleaved on a per-bit-group basis, each bit group being 360 bits long. In group-wise deinterleaving, the interleaved LDPC code is restored to the original ordering thereof. This technology can be applied, for example, to data transmission or the like using an LDPC code.

TRANSMITTING APPARATUS, RECEIVING APPARATUS, AND SIGNAL PROCESSING METHOD THEREOF

A transmitting apparatus, a receiving apparatus and methods of controlling these apparatuses are provided. The transmitting apparatus includes: a baseband packet generator configured to, based on an input stream including a first type stream and a second type stream, generate a baseband packet including a header and payload data corresponding to the first type stream; a frame generator configured to generate a frame including the baseband packet; a signal processor configured to perform signal-processing on the generated frame; and a transmitter configured to transmit the signal-processed frame, wherein the header includes a type of the payload data in the baseband packet and the number of the first type stream packets in the baseband packet.

METHOD AND APPARATUS FOR ENCODING AND DECODING LOW DENSITY PARITY CHECK

An encoding apparatus is provided. The encoding includes a low density parity check (LDPC) encoder which performs LDPC encoding on input bits based on a parity-check matrix to generate an LDPC codeword formed of 64,800 bits, in which the parity-check matrix includes an information word sub-matrix and a parity sub-matrix, the information word sub-matrix is formed of a group of a plurality of column blocks each including 360 columns, and the parity-check matrix and the information word sub-matrix are defined by various tables which represent positions of value one (1) present in every 360-th column.

MODULATOR AND MODULATION METHOD USING NON-UNIFORM 16-SYMBOL SIGNAL CONSTELLATION FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING 4/15 CODE RATE

A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 4/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.

MODULATOR AND MODULATION METHOD USING NON-UNIFORM 16-SYMBOL SIGNAL CONSTELLATION FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING 2/15 CODE RATE

A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 2/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 16200 AND CODE RATE OF_3/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

... ²²A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC ²encoding method are disclosed. The LDPC encoder includes first memory, second ²memory, and a processor. The first memory stores an LDPC codeword having a ²length of 16200 and a code rate of 3/15. The second memory is initialized to ²0. The ²processor generates the LDPC codeword corresponding to information bits by ²performing accumulation with respect to the second memory using a sequence ²corresponding to a parity check matrix (PCM).² ...

SIGNALLING CODING AND MODULATION METHOD AND DEMODULATION AND DECODING METHOD AND DEVICE

Provided are a signalling coding and modulation method and a demodulation and decoding method and device, characterized in that the method comprises the steps of: extending based on signalling according to an extension pattern table to obtain an extended codeword, and conducting predetermined coding on the extended codeword to obtain a coded codeword; conducting check bit replacement on a check bit portion in the coded codeword and then splicing same into an information bit portion of the coded codeword, to obtain a replaced coded codeword; according to the length of the signalling, punching the replaced coded codeword according to a predetermined punching rule to obtain a punched coded codeword; and conducting bit rotation on a tuple sequence obtained by conducting predetermined processing based on the punched coded codeword, and then mapping same into a signalling symbol according to a predetermined mapping rule.

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 4/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

MODULE PARALLEL BITS INTERLEAVING

УСТРОЙСТВО И СПОСОБ ОБРАБОТКИ ДАННЫХ

Устройство обработки данных отображает входные символы, предназначенные для передачи, в заданное количество сигналов поднесущей ортогонально мультиплексированного с частотным разделением (ОМЧР) символа. Процессор обработки данных включает в себя запоминающее устройство перемежителя, которое считывает заданное количество символов данных для отображения на сигналы поднесущей ОМЧР. Запоминающее устройство перемежителя считывает символы данных на поднесущие ОМЧР для выполнения отображения, причем считывание из запоминающего устройства выполняют в другом порядке, чем считывание в запоминающее устройство, порядок определяют из набора адресов, в результате чего символы данных перемежают на сигналы поднесущей. Набор адресов генерируют из генератора адреса, который содержит линейный сдвиговый регистр с обратной связью и схему перестановок. Линейный сдвиговый регистр с обратной связью имеет десять каскадов регистра с полиномом генератора для линейного сдвигового регистра с обратной связью и код перестановки ...

MODULE PARALLEL BITS INTERLEAVING

УСТРОЙСТВО И СПОСОБ ОБРАБОТКИ ДАННЫХ

Настоящее изобретение касается устройства обработки данных и способа обработки данных, которые могут улучшить устойчивость к появлению ошибок в данных. В демультиплексоре 25 заменяют в соответствии с правилом сопоставления битов LDPC-кода и битов символов, которые представляют символы, mb битов из битов кода и используют биты кода после замены как биты b символов. Согласно правилу сопоставления, когда группы, в которые сгруппированы биты кода и биты символа в зависимости от вероятности появления ошибок, используют как группы битов кода и группы битов символа соответственно, определяют комбинацию любой группы битов кода и любой группы битов символа, которой должна быть сопоставлена группа битов кода, и количества битов кода и битов символа.

MODULE PARALLEL BITS INTERLEAVING

УСТРОЙСТВО И СПОСОБ ОБРАБОТКИ ДАННЫХ

Устройство обработки данных отображает входные символы, предназначенные для передачи, в заданное количество сигналов поднесущей ортогонально мультиплексированного с частотным разделением (ОМЧР) символа. Процессор обработки данных включает в себя запоминающее устройство перемежителя, которое считывает заданное количество символов данных для отображения на сигналы поднесущей ОМЧР. Запоминающее устройство перемежителя считывает символы данных на поднесущие ОМЧР для выполнения отображения, причем считывание из запоминающего устройства выполняют в другом порядке, чем считывание в запоминающее устройство, порядок определяют из набора адресов, в результате чего символы данных перемежают на сигналы поднесущей. Набор адресов генерируют из генератора адреса, который содержит линейный сдвиговый регистр с обратной связью и схему перестановок. Линейный сдвиговый регистр с обратной связью имеет десять каскадов регистра с полиномом генератора для линейного сдвигового регистра с обратной связью R'i [9] ...

УСТРОЙСТВО И СПОСОБ ОБРАБОТКИ ДАННЫХ

Устройство обработки данных отображает входные символы, предназначенные для передачи, в заданное количество сигналов поднесущей ортогонального мультиплексированного с частотным разделением (ОМЧР) символа. Процессор обработки данных включает в себя запоминающее устройство перемежителя, который считывает заданное количество символов данных для отображения на сигналы поднесущей ОМЧР. Запоминающее устройство перемежителя считывает символы данных на поднесущие ОМЧР для выполнения отображения, причем считывание с запоминающего устройства выполняют в ином порядке, чем занесение в запоминающее устройство, порядок определяют по набору адресов, в результате чего символы данных перемежают на сигналы поднесущей. Набор адресов генерируют с генератора адреса, содержащего линейный регистр сдвига с обратной связью и схему перестановок.

УСТРОЙСТВО И СПОСОБ ОБРАБОТКИ ДАННЫХ

Устройство обработки данных выполнено с возможностью отображения символов входных данных, предназначенных для передачи, в заданное количество сигналов поднесущих ортогональных мультиплексированных с частотным разделением ОМЧР символов. Заданное количество сигналов поднесущих определяют в соответствии с одним из многих режимов работы, и входные символы данных разделяют на первые наборы входных символов данных и вторые наборы входных символов данных. Устройство обработки данных содержит перемежитель, выполненный с возможностью обработки нечетного перемежения, при котором выполняют перемежение первых наборов входных символов данных на сигналах поднесущей первых символов ОМЧР, и обработки четного перемежения, при котором осуществляют перемежение вторых наборов входных символов данных на сигналах поднесущих вторых символов ОМЧР, так что когда символы входных данных из первого набора считывают из ячеек в запоминающем устройстве перемежителя, символы входных данных со второго набора могут быть ...

УСТРОЙСТВО И СПОСОБ ОБРАБОТКИ ДАННЫХ, А ТАКЖЕ УСТРОЙСТВО И СПОСОБ КОДИРОВАНИЯ

Изобретение относится к устройству обработки данных и к способу обработки данных, а также к устройству кодирования и способу кодирования, которые позволяют улучшить устойчивость к ошибкам. В коде LDPC, который предписан в соответствии с DVB-S.2 и имеет длину кода 64800 и скорость кодирования 2/3, mb кодовых битов заменяют и кодовые биты после замены становятся битами символов, состоящими из b символов. Когда m равно 8 и b равно 2, в случае, когда i+1-й бит от старшего значащего бита 8×2 кодовых битов и 8×2 битов символов двух последовательных символов представлены как bi и yi, соответственно, замена состоит в назначении b0 для y15, b1 для у7, b2 для y1, b3 для у5, b4 для у6, b3 для y13, b6 для у11, b7 для у9, b8 для у8, b9 для y14, b10 для y12, b11 для у3, b12 для у0, b13 для у10, b14 для у4 и b15 для у2. Настоящее изобретение можно применять, например, в системе передачи данных для передачи кода LDPC и т.д.

MODULE PARALLEL BITS INTERLEAVING

УСТРОЙСТВО И СПОСОБ ОБРАБОТКИ ДАННЫХ

Устройство обработки данных отображает входные символы, предназначенные для передачи, в заданное количество сигналов поднесущей ортогонального мультиплексированного с частотным разделением (ОМЧР) символа. Процессор обработки данных включает в себя запоминающее устройство перемежителя, которое считывает заданное количество символов данных для отображения на сигналы поднесущей ОМЧР. Запоминающее устройство перемежителя считывает символы данных на поднесущие ОМЧР для выполнения отображения, причем считывание из запоминающего устройства выполняют в другом порядке, чем считывание в запоминающее устройство, порядок определяют из набора адресов, в результате чего символы данных перемежают на сигналы поднесущей. Набор адресов генерируют из генератора адреса, который содержит линейный сдвиговый регистр с обратной связью и схему перестановок. Полином генератора для линейного сдвигового регистра с обратной связью предусмотрен с порядком перестановок, который был установлен путем анализа на основе ...

УСТРОЙСТВО И СПОСОБ ОБРАБОТКИ ДАННЫХ

Устройство обработки данных отображает входные символы, предназначенные для передачи, в заданное количество сигналов поднесущей ортогонально мультиплексированного с частотным разделением (ОМЧР) символа. Процессор обработки данных включает в себя запоминающее устройство перемежителя, которое считывает заданное количество символов данных для отображения на сигналы поднесущей ОМЧР. Запоминающее устройство перемежителя считывает символы данных на поднесущие ОМЧР для выполнения отображения, причем считывание из запоминающего устройства выполняют в другом порядке, чем считывание в запоминающее устройство, порядок определяют из набора адресов, в результате чего символы данных перемежают на сигналы поднесущей. Набор адресов генерируют из генератора адреса, который содержит линейный сдвиговый регистр с обратной связью и схему перестановок. Линейный сдвиговый регистр с обратной связью имеет двенадцать каскадов регистра с полиномом генератора для линейного сдвигового регистра с обратной связью и код ...

비트 인터리버

... 수신 성능의 향상을 도모하기 위한 본 발명의 비트 인터리브 방법은 의사 순회 저밀도 패리티체크 부호화 방식으로 생성된 부호어의 비트를 재배열하는 비트 인터리브 방법으로, 각 순회블록의 비트의 콘스테레이션 어 중의 위치를 결정하는 순회블록 퍼뮤테이션 규칙에 따라서 부호어의 순회블록을 재배열하는 순회블록 퍼뮤테이션 처리와, 순회블록의 재배열 후의 부호어의 비트를 재배열하는 비트 퍼뮤테이션 처리를 포함한다.

DATA PROCESSING APPARATUS AND METHOD

Time and cell de-interleaving circuit and method of performing time and cell de-interleaving

Data processing apparatus and method for interleaving and deinterleaving data

A data processing apparatus is arranged to map input data symbols to be communicated onto a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed OFDM symbols. The predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the input data symbols are divided into first sets of input data symbols and second sets of input data symbols.

Transmitting apparatus and signal processing method thereof

A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method.

TRANSMITTER APPARATUS AND SIGNAL PROCESSING METHOD THEREOF

A transmitter apparatus and a receiver apparatus are provided. The transmitter apparatus includes: an encoder configured to generate a low density parity check (LDPC) by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol. The modulator maps a bit included in a predetermined group from among a plurality of groups constituting the LDPC codeword onto a predetermined bit in the modulation symbol. 2. The receiving method of claim 1 , wherein each of the plurality of groups comprises 360 values.3. The receiving method of claim 1 , further comprises:deinterleaving one or more values from among the values of the deinterleaved plurality of groups, andwherein the decoding is performed by decoding the values of the deinterleaved plurality of groups comprising the deinterleaved one or more values.5. The transmitting method of claim 4 , wherein each of the plurality of bit groups comprises 360 bits. This is a Continuation of U.S. application Ser. No. 16/424,481 filed May 29, 2019, which is a Continuation of U.S. application Ser. No. 15/264,057 filed Sep. 13, 2016, now U.S. Pat. No. 10,367,606 issued on Jul. 30, 2019, which is a Continuation of U.S. application Ser. No. 14/324,436 filed Jul. 7, 2014, now U.S. Pat. No. 9,484,957 issued on Nov. 1, 2016, which claims the benefit under 35 U.S.C. § 119 from U.S. Provisional Application 61/843,114 filed on Jul. 5, 2013, U.S. Provisional Application 61/864,758 filed on Aug. 12, 2013, and U.S. Provisional Application 61/897,480 filed on Oct. 30, 2013, in the United States Patent and Trademark Office, and Korean Patent Application 10-2013-0125664 filed on Oct. 21, 2013, Korean Patent Application 10-2014-0026298 filed on Mar. 5, 2014, and Korean Patent Application 10-2014-0083647 filed on Jul. 4, 2014, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their ...

Data processing apparatus and method

A data processing apparatus maps symbols received from a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed (OFDM) symbols into an output symbol stream. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has ten register stages with a generator polynomial for the linear feedback shift register of R [9] = R -1 [0]⊕ R -1 [3], and the permutation code forms, with an additional bit, an eleven bit ...

Transparent component interleaving for rotated constellations

The present invention relates to communication systems that employ rotated constellations and provides a transmitter in which a component interleaver is paired with a matching deinterleaver upstream of the constellation rotation, as well as corresponding receivers and methods. According to this configuration, component separation can be performed while preserving the cell order.

LDPC coded modulation in combination with 256QAM and OFDM

Information bits are encoded according to an outer BCH code (111) and an inner low density parity check code (115) with code rate 7/15 and a codeword length of 16200. The resulting codeword bits are bit-interleaved (120) and the interleaved bits are demultiplexed (130) into 8 sequences of bits. The 8 sequences of bits are permuted (130) according to a predetermined permutation rule: v0 = b2, v1 = b6, v2 = b0, v3 = b1, v4 = b4, v5 = b5, v6 = b3, v7 = b7, and mapped onto symbols of a 256 QAM constellation (140). A transmission frame is built from these symbols (1030) and an OFDM generator (1040) processes the frame and outputs a transmission signal.

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

The present invention relates to a data processing device and a data processing method capable of improving the resistance to error of data. An LDPC encoder 115 performs encoding using an LDPC code having a code length of 4320 bits and a coded rate of one of four types including 1/2, 7/12, 2/3, 3/4. A parity check matrix H of the LDPC code is configured by arranging elements of 1's of an information matrix, which are determined based on a parity check matrix initial value table of the parity check matrix H representing positions of elements of 1's of the information matrix corresponding to an information length according to the code length and the coded rate for every 72 columns, in a column direction at a period of 72 columns. The parity check matrix initial value table, for example, is used for digital broadcasting for mobile terminals. The present invention can be applied in a case where LDPC encoding is performed.

УСТРОЙСТВО И СПОСОБ ДЛЯ ПЕРЕДАЧИ И ПРИЕМА ДАННЫХ В СИСТЕМЕ СВЯЗИ/ШИРОКОВЕЩАНИЯ

Изобретение относится к технике связи и предназначено для передачи и приема в системах связи/радиовещания. Технический результат - повышение надежности связи и широковещания за счет эффективного восстановления искаженной информации. Для этого в устройстве и способе для осуществления сокращения и прореживания в случае осуществления кодирования и декодирования предусмотрено использование матрицы проверки четности в системе связи/широковещания. В способе эксплуатации передающей стороны определяется количество битов, подлежащих заполнению нулями. Определяется количество групп битов, где все биты подлежат заполнению нулями. Все биты в группах битов с 0-й по (-1)-ю, указанных шаблоном сокращения, заполняются нулями. Информационные биты отображаются в позиции незаполненных битов в информационных битах Бозе-Чаудхури-Хоквенгема (BCH). Информационные биты BCH кодируются по BCH для генерации информационных битов LDPC. Информационные биты LDPC кодируются с LDPC для генерации кодового слова с заполнением ...

УСТРОЙСТВО ОБРАБОТКИ ДАННЫХ И СПОСОБ ОБРАБОТКИ ДАННЫХ

Изобретение относится к обработке данных. Технический результат состоит в упрощении обработки данных управления, имеющих улучшенное отношение пиковой мощности к средней мощности (PAPR). Для этого в передающем устройстве модуль 21 дополнения дополняет данные управления, необходимые для демодуляции, нулями в качестве фиктивных данных, а модуль 101 скремблирования осуществляет скремблирование этих данных управления, дополненных фиктивными данными (дополненные данные управления). Модуль 121 замещения осуществляет замещение скремблированных фиктивных данных в составе скремблированных дополненных фиктивными данными данных управления, а модуль 22 кодирования в коде Бозе-Чоудхури-Хоквенгема (BCH-коде) и модуль 23 кодирования в коде с низкой плотностью проверки на четность (LDPC-коде) осуществляют кодирование в BCH-коде и кодирование в LDPC-коде в качестве кодирования в коде с коррекцией ошибок применительно к замещенным данным, полученным в результате замещения. Модуль сокращения 21 осуществляет ...

УСТРОЙСТВО ОБРАБОТКИ ДАННЫХ И СПОСОБ ОБРАБОТКИ ДАННЫХ

Изобретение относится к технике связи и предназначено для обработки данных. Технический результат – обеспечение хорошего качества связи при передаче данных с использованием LDPC-кода. Для этого в устройстве передачи при перестановке с целью сопоставления бита LDPC-кода, для которого длина кода равна 16200 битам и скорость кодирования равна 7/15, с битом символа, соответствующим любой из 8 сигнальных точек, определенных 8-позиционной PSK, когда 3 бита кода, которые сохранены в трех блоках памяти емкостью 16200/3 битов и которые побитно считаны из блоков памяти, сопоставляют одному символу, бит b, бит bи бит bпереставляют соответственно с битами y, yи y. Возвращают к исходной позицию переставленного бита кода, полученного из данных, переданных из устройства передачи. 4 н.п. ф-лы, 79 ил.

СПОСОБ И УСТРОЙСТВО ДЛЯ ПРИЕМА ДАННЫХ

Изобретение касается способа и устройства для приема данных. Терминал, принимающий данные, выполняет следующую обработку каждого принятого блока файла: декодирование с прямой коррекцией ошибок для Tb декодируемых последовательностей битов блока файла с получением, соответственно, Tb декодированных последовательностей битов информации с длиной К; при этом i-тая декодируемая последовательность битов образована из i-тых битов каждого нестертого информационного сегмента файла и контрольного сегмента файла блока файла в последовательности, соответствующей последовательности информационных сегментов файла и контрольных сегментов файла; объединение К декодированных информационных сегментов файла блока файла последовательно, чтобы генерировать исходные данные файла блока файла; при этом m-ный декодированный информационный сегмент файла образован из m-ных битов Tb декодированных последовательностей битов информации в последовательности, соответствующей последовательности упомянутых последовательностей ...

СПОСОБ И УСТРОЙСТВО ДЛЯ ПРИЕМА ДАННЫХ

... 1. Способ приема данных, включающий обработку каждого принятого блока файла в терминале, принимающем данные, следующим образом: ! А: выполнение декодирования с прямой коррекцией ошибок для Тb декодируемых последовательностей битов блока файла с получением соответственно Тb декодированных последовательностей битов информации с длиной К, ! при этом i-я декодируемая последовательность битов образована из i-х битов каждого нестертого информационного сегмента файла и контрольного сегмента файла блока файла последовательно согласно последовательности информационных сегментов файла и контрольных сегментов файла; ! В: объединение К декодированных информационных сегментов файла блока файла последовательно, чтобы генерировать исходные данные файла для блока файла; ! при этом m-й декодированный информационный сегмент файла образован из m-х битов Тb декодированных последовательностей битов информации в последовательности, соответствующей последовательности упомянутых последовательностей битов информации ...

УСТРОЙСТВО И СПОСОБ ДЛЯ ГЕНЕРИРОВАНИЯ МАТРИЦЫ ПРОВЕРКИ ЧЕТНОСТИ В СИСТЕМЕ СВЯЗИ С ИСПОЛЬЗОВАНИЕМ ЛИНЕЙНЫХ БЛОЧНЫХ КОДОВ И УСТРОЙСТВО ПЕРЕДАЧИ/ПРИЕМА И СПОСОБ ДЛЯ ИСПОЛЬЗОВАНИЯ ЭТОГО

... 1. Способ для кодирования канала в системе связи с использованием кода проверки четности низкой плотности (LDPC), содержащий этапы:извлечения матрицы проверки четности LDPD кода; ивыполнение кодирования LDPC с использованием извлеченной матрицы проверки четности,при этом кодовая скорость 1/5, длина кодового слова 4320, и матрица проверки четности формируется, как определяется в следующей таблице:.2. Способ по п.1, в котором матрица проверки четности имеет множество групп столбцов, обеспечиваемых, посредством группирования столбцов, соответствующих информационному слову, при этом каждая группа столбцов имеет 72 столбца, ипри этом каждая строка в таблице включает в себя информацию последовательности, показывающую положения строк, где '1' располагается в соответствующей группе столбцов матрицы проверки четности.3. Способ по п.1, в котором кодовая скорость обозначает отношение длины информационного слова к длине кодового слова, соответственно, соответствуя матрице проверки четности.4. Способ ...

ПРИЕМНОЕ УСТРОЙСТВО, СПОСОБ ПРИЕМА, ПРОГРАММА И ПРИЕМНАЯ СИСТЕМА

... 1. Приемное устройство, содержащее: ! устройство декодирования НПКЧ, выполненное с возможностью того, что, когда сигнал кодированных НПКЧ данных, где код НПКЧ представляет собой код низкой плотности с контролем четности, и сигнал управления кодированной НПКЧ передачей передаются мультиплексированными, упомянутое устройство декодирования НПКЧ может декодировать как сигнал данных, так и сигнал управления передачей; ! устройство хранения, выполненное с возможностью расположения перед упомянутым устройством декодирования НПКЧ и для хранения по меньшей мере упомянутого сигнала управления передачей при приеме упомянутого сигнала данных и упомянутого сигнала управления передачей; и ! управляющее устройство, выполненное с возможностью управления упомянутым устройством декодирования НПКЧ для декодирования упомянутого сигнала данных в то время как упомянутый сигнал управления передачей накапливается в упомянутом устройстве хранения, и для прерывания текущего декодирования, чтобы управлять упомянутым ...

УСТРОЙСТВО ОБРАБОТКИ ДАННЫХ И СПОСОБ ОБРАБОТКИ ДАННЫХ

... 1. Устройство обработки данных, содержащее:модуль кодирования, выполненный с возможностью кодирования LDPC, имеющего длину кода 16200 битов, и скорость кодирования равную 8/15, на основе матрицы проверки на четность кода LDPC; имодуль взаимной замены, выполненный с возможностью осуществления взаимной замены знаковых битов кода LDPC, кодируемого модулем кодирования, на символьные биты для символа, соответствующего любой из 16 сигнальных точек, определенных 16QAM, при этомкод LDPC, кодируемый модулем кодирования, включает в себя информационные биты и биты четности, аматрица проверки на четность включает в себя область информационной матрицы, соответствующую информационным битам и область матрицы четности, соответствующую битам четности, причемобласть информационной матрицы представлена таблицей исходного значения матрицы проверки на четность, атаблица исходного значения матрицы проверки на четность представляет собой таблицу, представляющую положения элементов 1 на участке информационной ...

УСТРОЙСТВО ОБРАБОТКИ ДАННЫХ И СПОСОБ ОБРАБОТКИ ДАННЫХ

... 1. Устройство обработки данных, содержащее:средство перестановки, выполненное с возможностью перестановки кодовых бит в количестве mb бит в соответствии с правилом назначения, используемым для назначения кодовых бит кода с низкой плотностью проверки на четность (LDPC) символьным битам, представляющим символ и с возможностью установки кодовых бит после перестановки, в качестве символьных бит, когда кодовые биты кода LDPC, имеющего длину кода, равную N бит, записаны в направлении столбцов средства хранения, выполненного с возможностью хранения кодовых бит в направлении строк и в направлении столбцов, при этом m бит из кодовых бит кода LDPC, считываемых в направлении строк, устанавливают в качестве одного символа, а величине b присваивают заданное целое положительное значение, при этом средство хранения выполнено с возможностью хранения mb бит в направлении строк и хранения N/(mb) бит в направлении столбцов, кодовые биты кода LDPC записывают в направлении столбцов средства хранения и затем ...

data processing apparatus and method

Address generation polynomial and permutation matrix for DVB-T2 16k OFDM sub-carrier mode (de)interleaver

The standards for DVB-T/H specify (de)interleaving symbols to/from OFDM subcarriers. It further specifies an interleaving address generator that comprises a linear feedback shift register and a permutation matrix operating on the shift register bits. The DVB-T/H specifications include 3 modes with approximately 2, 4 and 8 thousand sub-carriers, and interleaver address generators for these are known. A proposed DVB-T2 specification includes three new modes with 1, 16 and 32 thousand sub-carriers. The invention specifies a polynomial to be implemented in the LFSR and a permutation matrix for the 16k mode. R(i)[12] = R(i-1)[0] xor R(i-1)[1] xor R(i-1)[4] xor R(i-1)[5] xor R(i-1)[9] xor R(i-1)[11] 0:9/ 1:7 / 2:6 / 3:10 / 4:12 / 5:5 / 6:1 / 7:11 / 8:0 / 9:2 / 10:3 / 11:4 / 12:8 Simulations have shown that the proposed system provides good separation of adjacent symbols and hence good noise immunity.

Data processing apparatus and method

Data processing apparatus and method

Data processing apparatus and method

DATA PROCESSING APPARATUS AND METHOD A data processing apparatus maps input symbols to be communicated onto a 5 predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order 10 than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. A generator polynomial for the linear feedback shift register of R[131=R [0])R,[I])R_,1 [2]DR,'[12] is provided with a permutation 15 order which has been established by simulation analysis to ...

Data processing device, data processing method, coding device and coding method

Data processing device and data processing method

The present invention relates to a data processing device and a data processing method that can improve the robustness of data against errors. An LDPC encoder (115) performs encoding with one of LDPC codes having a code length of 4320 bits and one of four encoding rates of 1/2, 7/12, 2/3, or 3/4. The parity-check matrix (H) for each LDPC code has a structure in which elements with the value 1 in the information matrix of the parity-check matrix (H) are arranged in cycles of 72 columns in the column direction, the information matrix being determined by a parity-check-matrix initial-value table that indicates the positions of the elements with the value 1 in the information matrix in cycles of 72 columns, the information matrix corresponding to the information length which is a function of the code length and the encoding rate. The parity-check-matrix initial-value table is, for example, designed for digital broadcasting for mobile terminals. The present invention is applicable to LDPC encoding ...

Data processing device and data processing method

The present invention relates to a data processing device and a data processing method that can improve the robustness of data against errors. An LDPC encoder (115) performs encoding with one of LDPC codes having a code length of 4320 bits and one of four encoding rates of 1/2, 7/12, 2/3, or 3/4. The parity-check matrix (H) for each LDPC code has a structure in which elements with the value 1 in the information matrix of the parity-check matrix (H) are arranged in cycles of 72 columns in the column direction, the information matrix being determined by a parity-check-matrix initial-value table that indicates the positions of the elements with the value 1 in the information matrix in cycles of 72 columns, the information matrix corresponding to the information length which is a function of the code length and the encoding rate. The parity-check-matrix initial-value table is, for example, designed for digital broadcasting for mobile terminals. The present invention is applicable to LDPC encoding ...

Parallel bit interleaver

This bit interleave method performs bit permutation on QC LDPC code words consisting of N cyclic blocks of Q bits, and partitions said processed code words into multiple constellation words consisting of M bits. The code words are partitioned into F×N/M folding sections, and each constellation word is associated with one of the F×N/M folding sections. The bit permutation processing is performed such that the constellation words consist of F bits from each of M/F different cyclic blocks in the associated folding section.

MODULATOR AND MODULATION METHOD USING NON-UNIFORM 16-SYMBOL SIGNAL CONSTELLATION FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING 4/15 CODE RATE

... ²A modulator and a modulation method using a non-uniform 16-symbol signal ²constellation are disclosed. The modulator includes a memory and a processor. ²The ²memory receives a codeword corresponding to a low-density parity check (LDPC) ²code ²having a code rate of 4/15. The processor maps the codeword to 16 symbols of ²the non-uniform ²16-symbol signal constellation on a 4-bit basis.² ...

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

The present invention relates to a data processing device and a data processing method capable of improving data error resilience. In a case where LDPC codes having a code length of 4320 bits are mapped to sixteen signal points, a demultiplexer performs replacement assigning b0 to y0, b1 to y4, b2 to y1, b3 to y6, b4 to y2, b5 to y5, b6 to y3 and b7 to y7 for LDPC codes with a code rate of 1/2, and assigning b0 to y0, b1 to y4, b2 to y5, b3 to y2, b4 to y1, b5 to y6, b6 to y3 and b7 to y7 for LDPC codes with code rates of 7/12, 2/3 and 3/4, where (#i+1)-th bits from the most significant bits of 4×2-bit sign bits and of 4×2-bit symbol bits of two successive symbols are represented by bits b#i and y#i, respectively. The present invention can be applied, for example, to a transmission system transmitting LDPC codes.

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

This technology pertains to a data-processing device and a data processing method that make it possible to ensure good communication quality when using an LDPC code to transmit data. In group-wise interleaving, an LDPC code having a code length (N) of 16,200 bits and a code rate (r) of 10/15 or 12/15 is interleaved on a per-bit-group basis, each bit group being 360 bits long. In group-wise deinterleaving, the interleaved LDPC code is restored to the original ordering thereof. This technology can be applied, for example, to data transmission or the like using an LDPC code.

MODULATOR AND MODULATION METHOD USING NON-UNIFORM 16-SYMBOL SIGNAL CONSTELLATION FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING 2/15 CODE RATE

A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 2/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.

MODULE PARALLEL BITS INTERLEAVING

УСТРОЙСТВО И СПОСОБ ОБРАБОТКИ ДАННЫХ

Устройство обработки данных отображает входные символы, предназначенные для передачи, в заданное количество сигналов поднесущей ортогонально мультиплексированного с частотным разделением (ОМЧР) символа. Процессор обработки данных включает в себя запоминающее устройство перемежителя, которое считывает заданное количество символов данных для отображения на сигналы поднесущей ОМЧР. Запоминающее устройство перемежителя считывает символы данных на поднесущие ОМЧР для выполнения отображения, причем считывание из запоминающего устройства выполняют в другом порядке, чем считывание в запоминающее устройство, порядок определяют из набора адресов, в результате чего символы данных перемежают на сигналы поднесущей. Набор адресов генерируют из генератора адреса, который содержит линейный сдвиговый регистр с обратной связью и схему перестановок. Линейный сдвиговый регистр с обратной связью имеет двенадцать каскадов регистра с полиномом генератора для линейного сдвигового регистра с обратной связью R'i ...

УСТРОЙСТВО И СПОСОБ ОБРАБОТКИ ДАННЫХ

Настоящее изобретение относится к устройству обработки данных и к устройству обработки данных, которое позволяет улучшить устойчивость к ошибкам кодовых битов кода LDPC, таких как пакетные ошибки или уничтожение битов. Блок 21 кодирования LDPC выполняет кодирование LDPC в соответствии с матрицей проверки на четность, в котором матрица проверки на четность, которая представляет собой часть, соответствующую битам четности кода LDPC (с малой плотностью проверок на четность), имеет лестничную структуру и выводит код LDPC. Перемежитель 23 четности осуществляет перемежение четности, состоящее в перемежении битов четности кода LDPC, выводимого из блока 21 кодирования LDPC, в положения других битов четности. Настоящее изобретение можно применять, например, к устройству передачи, которое передает код LDPC.

УСТРОЙСТВО И СПОСОБ ОБРАБОТКИ ДАННЫХ, А ТАКЖЕ КОДИРУЮЩЕЕ УСТРОЙСТВО И СПОСОБ КОДИРОВАНИЯ

Изобретение относится к устройству обработки данных и к способу обработки данных, а также к кодирующему устройству и способу кодирования, которые могут улучшить устойчивость к ошибкам. В коде LDPC, который предписан стандартом DVB-S.2 и имеет длину кода 64.800 и скорость кодирования 2/3, mb кодовых разрядов заменяются, и кодовые разряды после этой замены становятся символьными разрядами b символов. Если m равно 8, a b равно 2, когда (i+1)-й бит из наиболее значимого бита из 8 х 2 кодовых разрядов и 8 х 2 символьных разрядов двух следующих друг за другом символов представлены через bi и уi, соответственно, осуществляется замена назначения b0 биту у15, бита b1 биту у7, бита b2 биту y1, бита b3 биту у5, бита b4 биту у6, бита b5 биту у13, бита b6 биту у11, бита b7 биту у9, бита b8 биту у8, бита b9 биту у14, бита b10 биту y12, бита b11 биту у3, бита b12 биту у0, бита b13 биту у10, бита b14 биту у4 и бита b15 биту у2. Настоящее изобретение может применяться, например, в передающей системе для ...

УСТРОЙСТВО И СПОСОБ ОБРАБОТКИ ДАННЫХ

Устройство обработки данных отображает входные символы, предназначенные для передачи, в заданное количество сигналов поднесущей ортогонального мультиплексированного с частотным разделением (ОМЧР) символа. Процессор обработки данных включает в себя запоминающее устройство перемежителя, которое считывает заданное количество символов данных для отображения на сигналы поднесущей ОМЧР. Запоминающее устройство перемежителя считывает символы данных на поднесущие ОМЧР для выполнения отображения, причем считывание из запоминающего устройства выполняют в другом порядке, чем считывание в запоминающее устройство, порядок определяют из набора адресов, в результате чего символы данных перемежают на сигналы поднесущей. Набор адресов генерируют из генератора адреса, который содержит линейный сдвиговый регистр с обратной связью и схему перестановок. Полином генератора для линейного сдвигового регистра с обратной связью предусмотрен с порядком перестановок, который был установлен путем анализа на основе ...

MODULE PARALLEL BITS INTERLEAVING

УСТРОЙСТВО И СПОСОБ ОБРАБОТКИ ДАННЫХ

Устройство обработки данных отображает входные символы, предназначенные для передачи, в заданное количество сигналов поднесущей ортогонально мультиплексированного с частотным разделением (ОМЧР) символа. Процессор обработки данных включает запоминающее устройство перемежителя, которое считывает заданное количество символов данных для отображения на сигналы поднесущей ОМЧР. Запоминающее устройство перемежителя считывает символы данных на поднесущие ОМЧР для выполнения отображения, причем считывание с запоминающего устройства выполняют в другом порядке, чем занесение в запоминающее устройство, и этот порядок определяют по набору адресов, вследствие чего символы данных перемежают по сигналам поднесущей. Набор адресов генерируют с помощью генератора адресов, который содержит линейный регистр сдвига с обратной связью и схему перестановок. Линейный регистр сдвига с обратной связью имеет двенадцать каскадов регистра с полиномом генератора для линейного регистра сдвига с обратной связью , и код ...

Data processing device, data processing method, coding device and coding method

The present invention is related to a data processing device, a data processing method, a coding device and a coding method that can be configured to improve a tolerance to an error. A code bit of mb bits in an LDPC code having a code length of 64,800 bits and a code rate of 2/3 as prescribed in the DVB-S.2 is replaced and a code bit after the replacement is a symbol bit with b symbols. When m is8 and b is 2, and code bits with 8x2 bits and (i+1)th bit from the most significant bit of the 8x2 symbol bits of successive two symbols are expressed by bi and yi, respectively, the following replacement for each allocation is carried out: b0 with y15, b1 with y7, b2 with y1, b3 with y5, b4 with y6, b5 with y13, b6 with y11, b7 with y9, b8 with y8, b9 with y14, b10 with y12, b11 with y3, b12 with y0, b13 with y10, b14 with y4, and b15 with y2. The present invention can be applied to a transmission system to transmit the LDPC code, for instance.

For cascade-connected coding system advanced iterative decoding and channel estimation system and method

Transmitter device and signal processing method thereof

DATA RECEPTION USING LOW DENSITY PARITY CHECK CODING AND CONSTELLATION MAPPING

APPARATUS AND A METHOD FOR PROCESSING DATA, MAPPING INPUT SYMBOLS ON SUBCARRIER SIGNALS OF OFDM SYMBOLS AND IMPROVING DATA COMMUNICATION

PURPOSE: An apparatus and a method for processing data are provided to improve interleaving of the data symbol for 8k operation mode of an OFDM modulation system like DVB(Digital Video Broadcast) standard by changing a permutation code from one OFDM symbol to other OFDM symbol. CONSTITUTION: A data processing unit maps input data symbols on the preset number of subcarrier signals on an OFDM(Orthogonal Frequency Division Multiplexed) symbol. A data processing unit includes an interleaver memory reading into the preset number of data symbols for mapping the OFDM subcarrier signals. An interleaver memory reads out the data symbols from the memory to the output symbol stream for performing the mapping so that the data symbol is deinterleaved from the OFDM subcarrier signals. An address generator(102) with a linear feedback shift register and a permutation circuit(210) generates an address set. The linear feedback shift register includes 12 register stages(200) and an xor-gate(202) connected ...

BROADCASTING SIGNAL TRANSMITTER/RECEIVER AND BROADCASTING SIGNAL TRANSMISSION/RECEPTION METHOD

Disclosed is a broadcasting signal receiver. A broadcasting signal receiver, according to one embodiment of the present invention, comprises: an OFDM demodulator, which OFDM demodulates PLP data and signaling information that are included in a broadcasting signal; a MISO decoder, which MISO decodes MISO-type PLP data, which is included in the PLP data, and the signaling information; a frame de-mapper, which parses a frame by cell de-mapping the PLP data and the signaling information; and a BICM decoder, which bit de-interleaves and FEC decodes the PLP data and the signaling information, wherein the BICM decoder further includes a MIMO decoder, which MIMO decodes MIMO-type PLP data included in the PLP data, and the frame de-mapper further extracts the signaling information about the next frame, which is included in the frame, from a data symbol section of the frame.

FLEXIBLE CHANNEL DECODER.

A configurable Turbo-LDPC decoder comprising: - A set of P>1 Soft-Input-Soft-Output decoding units (DP0 - DPP-1; DPi) for iteratively decoding both Turbo- and LDPC-encoded input data, each of said decoding units having first (I1i) and second (I2i) input ports and first (O1i) and second (O2i) output ports for intermediate data; First and second memories (M1, M2) for storing said intermediate data, each of said first and second memories comprising P independently readable and writable memory blocks having respective input and output ports; and A configurable switching network (SN) for connecting the first input and output ports of said decoding units to the output and input ports of said first memory, and the second input and output ports of said decoding units to the output and input ports of said second memory.

RECEIVER FOR RECEIVING DATA IN A BROADCAST SYSTEM

A receiver for receiving data in a broadcast system comprises a broadcast receiver that receives via said broadcast system a receiver input data stream comprising a plurality of channel symbols represented by constellation points in a constellation diagram, a demodulator that demodulates said channel symbols into codewords, and a decoder that decodes said codewords into output data words. A redundancy calculator determines a required amount of redundancy data required for correct demodulation and decoding by use of the originally received channel symbol and additional redundancy data. A broadband request unit requests, if demodulation of a channel symbol and/or decoding of a codeword is erroneous or likely to fail, a required amount of redundancy data via a broadband system, that is received by a broadband receiver via said broadband system. Said demodulator and/or said decoder is configured to use said redundancy data for demodulation and decoding, respectively.

Transmitting apparatus and signal processing method thereof

A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method.

DATA-PROCESSING DEVICE AND DATA-PROCESSING METHOD

The present technology relates to a data-processing device and a data-processing method, which are capable of improving tolerance for an error of data. When an LDPC code having a code length of 16200 bits is mapped to 16 signal points, a demultiplexer performs exchanging such that when a (#i + 1)-th bit from a most significant bit of code bits of 4 × 2 bits and a (#i + 1)-th bit from a most significant bit of symbol bits of 4 × 2 bits of 2 consecutive symbols are represented by a bit b#i and a bit y#i, respectively, for LDPC codes having coding rates of 1/5, 4/15, and 1/3, b0 is allocated to y4, b1 is allocated to y3, b2 is allocated to y2, b3 is allocated to y1, b4 is allocated to y6, b5 is allocated to y5, b6 is allocated to y7, and b7 is allocated to y0. For example, the present invention can be applied to a transmission system that transmits an LDPC code or the like.

Apparatus for transmitting and receiving a signal and method of transmitting and receiving a signal

RECEIVING APPARATUS, RECEIVING METHOD AND PROGRAM, AND RECEIVING SYSTEM

PROBLEM TO BE SOLVED: To prevent a sudden change in power consumption. SOLUTION: An LDPC (low density parity check) decoding section 11 receives an LDPC code and decodes the received code. A control section 81 calculates a free time in which decoding is not executed from output of a result of decoding to reception of a new LDPC code, on the basis of a reception interval of the LDPC code and an output timing of the result of decoding. The control section 81 controls the velocity of LDPC decoding by controlling the frequency of an operation clock of the LDPC decoding section 11 on the basis of the free time. The device is applicable to a receiving apparatus for receiving an LDPC code, for example. COPYRIGHT: (C)2011,JPO&INPIT ...

УСТРОЙСТВО ОБРАБОТКИ ДАННЫХ И СПОСОБ ОБРАБОТКИ ДАННЫХ

... 1. Устройство обработки данных, содержащее:средство дополнения для дополнения данных управления фиктивными данными, при этом указанные данные управления необходимы для демодуляции;средство скремблирования для скремблирования дополненных данных управления, при этом дополненные данные управления представляют собой данные управления, после дополнения;средство замещения для генерирования замещенных данных посредством замещения скремблированных фиктивных данных в составе скремблированных дополненных фиктивными данными данных управления; исредство кодирования в коде с коррекцией ошибок для кодирования замещенных данных в коде с коррекцией ошибок.2. Устройство обработки данных, содержащее:средство скремблирования для скремблирования данных управления, необходимых для демодуляции;средство дополнения для дополнения скремблированных данных управления фиктивными данными; исредство кодирования в коде с коррекцией ошибок для кодирования дополненных скремблированных данных, формируемых посредством дополнения ...

УСТРОЙСТВО И СПОСОБ ДЛЯ ПЕРЕДАЧИ И ПРИЕМА ДАННЫХ В СИСТЕМЕ СВЯЗИ/ШИРОКОВЕЩАНИЯ

... 1. Способ действия передающей стороны в системе связи/широковещания, причем способ содержит этапы, на которых:кодируют информационные биты контроля четности низкой плотности (LDPC) для генерации кодового слова;определяют количествобитов, подлежащих прореживанию, в битах четности кодового слова;определяют количествогрупп битов четности, где все биты подлежат прореживанию;если количествогрупп битов четности, где все биты подлежат прореживанию, больше или равно количествугрупп битов четности, включенных во вторую часть четности,прореживают все биты четности, включенные в группу битов второй четности;прореживают все биты в группах битов четности с 0-й по-ю первой части четности, указанных первым шаблоном прореживания; иесли количествогрупп битов четности, где все биты подлежат прореживанию меньше количествагрупп битов четности, включенных во вторую часть четности,прореживают все биты в группах битов четности с 0-й по-ю второй части четности, указанных вторым шаблоном прореживания,причем первый ...

Address generation polynomial and permutation matrix for DVB-T2 1k OFDM sub-carrier mode (de)interleaver

The standards for DVB-T/H specify (de)interleaving symbols to/from OFDM subcarriers. It further specifies an interleaving address generator that comprises a linear feedback shift register and a permutation matrix operating on the shift register bits. The DVB-T/H specifications include 3 modes with approximately 2, 4 and 8 thousand sub-carriers, and interleaver address generators for these are known. A proposed DVB-T2 specification includes three new modes with 1, 16 and 32 thousand sub-carriers. The invention specifies a polynomial to be implemented in the LFSR and a permutation matrix for the 1k mode. R(i)[8] = R(i-1)[0] xor R(i-1)[4] 0:8 / 1:7 / 2:6 / 3:5 / 4:0 / 5:1 / 6:2 / 7:3 / 8:4 Simulations have shown that the proposed system provides good separation of adjacent symbols and hence good noise immunity.

Symbol to sub-carrier interleaver for DVB-T2 using odd interleaving

DVB-T and DVB-H interleave symbols to sub-carriers using a pseudo random sequence generated using an LFSR (linear feedback shift register) 200 whose bits are fed through a permutation matrix 210 to generate the read address for a partitioned interleaver memory. The invention provides improved separation between symbols by using an odd interleaving process only (fig 9) for successive sets of data symbols, when the number of data symbols which can be carried per OFDM symbol is less than half the maximum that can be carried. Data symbols to be transmitted are sequentially written into the memory and read out using generated address. Applying a cyclic offset to the address that changes from symbol to symbol reduces the likelihood that successive data bits which are close in order are mapped onto the same sub-carrier of an OFDM symbol.

Method and apparatus for memory access in an interleaver

An interleaver or deinterleaver comprises a memory having M logical memory units arranged in groups of N memory units such that accesses to memory units within a group are faster after a first access to a memory in that group using first access. An address generator is arranged to write consecutive data items â received via an input data stream â a number n of memory units apart that is less than the size of groups N of memory units so that two or more data items are written within groups. The generator then reads consecutive memory units to form an output data stream. The memory may comprise dynamic RAM, and the interleaver may operate by means of the DVB-T2 standard. The arrangement provides fast interleaving without increasing memory size.

Data processing apparatus and method

Data processing apparatus and method

DEVICE AND PROCEDURE FOR THE DATA PROCESSING

DEVICE FOR SENDING AND RECEIVING A SIGNAL AND A PROCEDURE FOR SENDING AND RECEIVING A SIGNAL

Techniques To Control Power Consumption In An Iterative Decoder By Control Of Node Configurations

A method for controlling power consumption of an iterative decoder based on one or more criteria is described. The method may include progressively enabling and disabling nodes of the iterative decoder to perform iterative decoding on a demodulated signal to provide a decoded signal with minimal variation of a supply voltage.

Readdressing decoder for quasi-cyclic low-density parity-check and method thereof

A readdressing decoder for QC-LDPC decoding including a memory, a controller and parallel processors is provided. The memory stores a QC-LDPC matrix including sub-matrices respectively addressed with a corresponding address. The controller readdresses each of the sub-matrices into divided matrices and defines each of the divided matrices into a first address group and a second address group. The controller further respectively transmits the divided matrices of the first address group and the second address group to the parallel processors to perform correction algorithm.

Apparatus and method for transmitting and receiving data in communication system

An apparatus and a method for transmitting and receiving a signal in a communication system are provided. The method includes checking a type of the signal to be transmitted; determining a number of puncture bits according to the type of the signal; and puncturing an encoded signal to be transmitted according to the number of puncture bits.

Data processing device and data processing method

A data processing device and a data processing method that can readily process control data having its PAPR improved. In a transmission device, a padder pads control data necessary for demodulation with zeros as dummy data, and a scrambler scrambles the padded control data (post-padding control data). A replacement unit replaces scrambled dummy data in the scrambled post-padding control data with the dummy data, and a BCH encoder and an LDPC encoder perform BCH encoding and LDPC encoding as error correction encoding on the replacement data obtained through the replacement. A shortening unit performs shortening by deleting the dummy data contained in the LDPC code and puncturing the parity bits of the LDPC code. The device can be applied in cases where control data is subjected to error correction encoding and is then transmitted, for example.

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 3/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping. 1. A BICM device , comprising:an error-correction coder configured to output a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15;a bit interleaver configured to generate an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword; anda modulator configured to perform 64-symbol mapping after generating the interleaved codeword, {'br': None, 'i': Y', '=X', 'j≦N, 'sub': j', 'π(j)', 'group, '0≦'}, 'wherein the interleaving is performed using the following equation using permutation order{'sub': j', 'j, 'where Xis the j-th bit group, Yis an interleaved j-th bit group, and π(j) is a permutation order for bit group-based interleaving.'}2. The BICM device of claim 1 , wherein the permutation order corresponds to an interleaving sequence represented by the following{'br': None, 'interleaving sequence={74 72 104 62 122 35 130 0 95 150 139 151 133 109 31 59 18 148 9 105 57 132 102 100 115 101 7 21 141 30 8 1 93 92 163 108 52 159 24 89 117 88 178 113 98 179 144 156 54 164 12 63 39 22 25 137 13 41 44 80 87 111 145 23 85 166 83 55 154 20 84 58 26 126 170 103 11 33 172 155 116 169 142 70 161 47 3 162 77 19 28 97 124 6 168 107 60 76 143 121 42 157 65 43 173 56 171 90 131 119 94 5 68 138 149 73 67 53 61 4 86 99 75 36 15 48 177 167 174 51 176 81 120 158 123 34 49 ...

TRANSMITTING APPARATUS AND MAPPING METHOD THEREOF

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme. 2. The method as claimed in claim 1 , wherein the interleaving comprises:splitting the codeword into a plurality of bit groups; andinterleaving the plurality of bit group.3. The method as claimed in claim 1 , wherein the mapping comprises:demultiplexing the bits of the interleaved codeword into parallel streams to generate cells; andmapping the cells onto the constellation points. This application is a Continuation of application Ser. No. 14/716,222 filed May 19, 2015, the disclosure of which is incorporated herein by reference in its entirety.Apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to transmitting and receiving date using broadcasting, more particularly, to the design of non-uniform constellations used in a Bit Interleaved Coded Modulation (BICM) mapping bits at an output of an encoder and interleaver to complex constellations.The current broadcasting systems consistent with the Digital Video Broadcasting Second Generation Terrestrial (DVB-T2) use a Bit Interleaved and Coded Modulation (BICM) chain in order to encode bits to be transmitted. The BICM chain includes a channel encoder like a Low Density Parity Check (LDPC) encoder followed by a Bit Interleaver and a Quadrature Amplitude Modulation (QAM) mapper. The role of the QAM mapper is to map different bits output from the channel encoder and interleaved using the Bit Interleaver to QAM cells. Each cell represents a complex number having real and imaginary part. The QAM mapper groups M bits into one cell. Each cell is ...

TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol. 2. The receiving apparatus of claim 1 , wherein each of the plurality of groups comprises 360 values.3. The receiving apparatus of claim 1 , wherein π(j) is determined based on at least one of the code length claim 1 , a modulation method and the code rate. This is a continuation of U.S. patent application Ser. No. 15/435,042, filed Feb. 16, 2017, which is a continuation of U.S. patent application Ser. No. 15/130,204, filed on Apr. 15, 2016, issued as U.S. Pat. No. 9,692,454 on Jun. 27, 2017, which is a continuation of U.S. patent application Ser. No. 14/625,862, filed Feb. 19, 2015, issued as U.S. Pat. No. 9,602,137 on Mar. 21, 2017, which claims priority from U.S. Provisional Application No. 61/941,676 filed on Feb. 19, 2014, U.S. Provisional Application No. 62/001,170 filed on May 21, 2014, and Korean Patent Application No. 10-2015-0000671 filed on Jan. 5, 2015. The entire disclosures of the prior applications are considered part of the disclosure of this continuation application, and are hereby incorporated by reference.Apparatuses and methods consistent with exemplary embodiments relate to a transmitting apparatus and an interleaving method thereof, and more particularly, to a transmitting apparatus which processes data and transmits the data, and an interleaving method thereof.In the 21st century information-oriented society, broadcasting communication services are moving into the era of digitalization, ...

RECEIVER FOR RECEIVING DATA IN A BROADCAST SYSTEM

A receiver for receiving data in a broadcast system comprises a broadcast receiver that receives via said broadcast system a receiver input data stream comprising a plurality of channel symbols represented by constellation points in a constellation diagram, a demodulator that demodulates said channel symbols into codewords, and a decoder that decodes said codewords into output data words. A redundancy calculator determines a required amount of redundancy data required for correct demodulation and decoding by use of the originally received channel symbol and additional redundancy data. A broadband request unit requests, if demodulation of a channel symbol and/or decoding of a codeword is erroneous or likely to fail, a required amount of redundancy data via a broadband system, that is received by a broadband receiver via said broadband system. Said demodulator and/or said decoder is configured to use said redundancy data for demodulation and decoding, respectively. 1. (canceled)2. A receiver comprising circuitry configured to:receive, via broadcast receiver circuitry, in a broadcast signal forward error correction (FEC) encoded data representing a content item for a non-real-time event;perform decoding of the content item and determine whether additional data is required to complete the decoding of the content item; send a request to a server for redundancy data corresponds to specifically requested bit positions in the received broadcast signal,', 'receive the requested redundancy data via broadband receiver circuitry, and', 'complete the decoding of the content item based on the received redundancy data; and, 'in response to a determination result that additional data is required to complete the decoding of the content item based on the received FEC encoded data,'}process the content item as the non-real time event.3. The receiver as claimed in wherein the content item is a data service item.4. The receiver as claimed in claim 3 , wherein the data service item is ...

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 2/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). 2. The LDPC encoding method of claim 1 , wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 8640 claim 1 , a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 1800 claim 1 , and a second parity part corresponding to an identity matrix included in the PCM and having a length of 54360.3. The LDPC encoding method of claim 2 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part claim 2 , that is claim 2 , 8640 claim 2 , by a circulant permutation matrix (CPM) size corresponding to the PCM claim 2 , that is claim 2 , 360 claim 2 , and a value obtained by dividing a length of the first parity part claim 2 , that is claim 2 , 1800 claim 2 , by the CPM size.4. The LDPC encoding method of claim 3 , wherein the accumulation is performed at parity bit addresses that are updated using the sequence.5. The LDPC encoding method of claim 4 , wherein the accumulation is performed while the rows of the sequence are being repeatedly changed by the CPM size of the PCM. This application is a continuation of U.S. patent application Ser. No. 14/496,457, filed on Sep. 25, 2014, which claims the benefit of Korean Patent Application Nos. 10-2014-0106178 and 10-2014-0120012, filed Aug. 14, 2014 and Sep. 11, 2014, respectively, which are hereby incorporated by reference herein in their entirety.1. Technical FieldThe ...

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 16200 AND CODE RATE OF 3/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). 2. The LDPC encoding method of claim 1 , wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 3240 claim 1 , a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 1080 claim 1 , and a second parity part corresponding to an identity matrix included in the PCM and having a length of 11880.3. The LDPC encoding method of claim 2 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part claim 2 , that is claim 2 , 3240 claim 2 , by a circulant permutation matrix (CPM) size corresponding to the PCM claim 2 , that is claim 2 , 360 claim 2 , and a value obtained by dividing a length of the first parity part claim 2 , that is claim 2 , 1080 claim 2 , by the CPM size.4. The LDPC encoding method of claim 3 , wherein the accumulation is performed at parity bit addresses that are updated using the sequence.5. The LDPC encoding method of claim 4 , wherein the accumulation is performed while the rows of the sequence are being repeatedly changed by the CPM size of the PCM. This application is a continuation of and claims priority of U.S. application Ser. No. 14/496,356 filed Sep. 25, 2014, which claims the benefit of Korean Patent Application Nos. 10-2014-0106174 and 10-2014-0120009, filed Aug. 14, 2014 and Sep. 11, 2014, respectively, which are hereby incorporated by reference herein in their entirety.1. ...

PARALLEL BIT INTERLEAVER

A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each imade up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section. 1. A transmitting method for transmitting a codeword generated based on a quasi-cyclic low-density parity check coding scheme , the transmitting method comprising:a cyclic block permutation step of applying a cyclic block permutation process to a codeword made up of N cyclic blocks each consisting of Q bits, to reorder the cyclic blocks in accordance with a cyclic block permutation rule defining a reordering of the cyclic blocks;a bit permutation step of applying a bit permutation process to the codeword after the cyclic block permutation process, to reorder the bits of the codeword in accordance with a bit permutation rule defining a reordering of the bits;a dividing step of dividing the codeword after the bit permutation process into a plurality of constellation words, each of the constellation words being made up of M bits,a modulating step of mapping each constellation word to a modulated signal, anda transmitting step of transmitting a transmitting signal generated from the constellation words, whereinN is a multiple of M,the bit permutation rule defines the reordering of the bits of the codeword after the cyclic block permutation process, the reordering of the bit permutation rule being equivalent to a column-row permutation process including a writing process and a reading process, the bits of the N cyclic blocks being written into a matrix row-by-row during the writing process, the written bits being ...

TRANSMITTING APPARATUS AND MAPPING METHOD THEREOF

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme. This application is a Continuation of application Ser. No. 15/705,749 filed Sep. 15, 2017, which is a Continuation of application Ser. No. 14/716,222 filed May 19, 2015, and issued as U.S. Pat. No. 9,800,365, on Oct. 24, 2017, the disclosures of which are incorporated herein by reference in their entirety.Apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to transmitting and receiving date using broadcasting, more particularly, to the design of non-uniform constellations used in a Bit Interleaved Coded Modulation (BICM) mapping bits at an output of an encoder and interleaver to complex constellations.The current broadcasting systems consistent with the Digital Video Broadcasting Second Generation Terrestrial (DVB-T2) use a Bit Interleaved and Coded Modulation (BICM) chain in order to encode bits to be transmitted. The BICM chain includes a channel encoder like a Low Density Parity Check (LDPC) encoder followed by a Bit Interleaver and a Quadrature Amplitude Modulation (QAM) mapper. The role of the QAM mapper is to map different bits output from the channel encoder and interleaved using the Bit Interleaver to QAM cells. Each cell represents a complex number having real and imaginary part. The QAM mapper groups M bits into one cell. Each cell is translated into a complex number. M, which is the number of bits per cell, is equal to 2 for QPSK, 4 for 16QAM, 6 for 64QAM, and 8 for 256. It is possible to use a higher QAM size in order to increase a throughput. For example: 1K QAM is a ...

Apparatus for transmitting and receiving a signal and method of transmitting and receiving a signal

According to one embodiment, a transmitter for transmitting at least one broadcast signal having PLP (Physical Layer Pipe) data includes: a BCH (Bose-Chadhuri-Hocquenghem) encoder configured to BCH encode the PLP data; an LDPC (Low Density Parity Check) encoder configured to LDPC encode the BCH encoded PLP data and output FECFrames (Forward Error Correction Frames); a mapper configured to map data in the FECFrames onto constellations by QAM (Quadrature Amplitude Modulation) schemes; a time-interleaver configured to time-interleave the mapped data; a frame builder configured to build a signal frame including preamble symbols and data symbols; and an OFDM (Orthogonal Frequency Division Multiplexing) modulator configured to modulate data in the signal frame by an OFDM scheme. The PLP data are processed by an LDPC scheme for a long or a short LDPC FECframe. The preamble symbols include signaling information for the time-interleaved PLP data. The data symbols include the time-interleaved PLP data.

TRANSMITTING APPARATUS AND SIGNAL PROCESSING METHOD THEREOF

A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method. 1. An interleaving method of a transmitting apparatus , the method comprising:splitting bits into a plurality of bit groups;interleaving the plurality of bit groups;interleaving the interleaved plurality of bit groups using a plurality of containers to provide an interleaved codeword, each of the plurality of containers comprising a first part and a second part;demultiplexing bits of the interleaved codeword to generate cells;mapping the cells onto constellation points, andtransmitting a signal which is based on the constellation points,wherein a number of bits to be written in the first part is determined based on a number of the plurality of containers and a number of bits of each of the plurality of bit groups, andwherein a number of bits to be written in the second part is determined based on the number of the plurality of containers and the number of the bits of each of the plurality of bit groups.2. The method as claimed in claim 1 , wherein the each of the plurality of bit groups comprises 360 bits.3. The method as claimed in claim 1 , wherein the number of the plurality of containers is equal to a modulation order for the mapping.4. A transmitting apparatus comprising:a group interleaver configured to split bits into a plurality of bit groups and interleave the plurality of bit groups;a block ...

APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING DATA IN COMMUNICATION SYSTEM

An apparatus and a method for transmitting and receiving a signal in a communication system are provided. The method includes checking a type of the signal to be transmitted; determining a number of puncture bits according to the type of the signal; and puncturing an encoded signal to be transmitted according to the number of puncture bits. 1. A method for operating a receive device , the method comprising:receiving, from a transmit device, by a transceiver, a signal generated based on remaining bits of parity bits after puncturing, wherein the parity bits are generated by adding at least one shortened bit to bits comprising information bits to generate input bits for an encoding, if a number of the information bits is less than a number of the input bits for the encoding, and applying the encoding to the input bits;determining, by a hardware processor, a number of puncture bits for the parity bits;generating, by the hardware processor, an output signal by adding at least one bit corresponding to the number of the puncture bits to the signal; anddecoding, by the hardware processor, the output signal,wherein the number of puncture bits is determined by adjusting a number of temporary puncture bits based on a modulation order of the signal,wherein the number of temporary puncture bits is determined by using a first parameter and a second parameter,wherein the first parameter and the second parameter are determined based on a type of the signal, the type of the signal corresponding to a protection level of the signal,wherein the first parameter is related to a ratio of a number of bits to be punctured to a number of bits to be shortened, and is multiplied by a number of the at least one shortened bit to generate a multiplication result, andwherein the second parameter is related to an integer that is added to the multiplication result to determine the number of temporary puncture bits.2. The method of claim 1 , wherein the type of the signal indicates whether the ...

PARALLEL BIT INTERLEAVER

A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process. 1. A bit interleaving method for interleaving bits of a codeword generated based on a low-density parity check coding scheme , a parity-check matrix of the low-density parity check coding scheme having a quasi-cyclic structure , the bit interleaving method comprising:a bit permutation step of applying a bit permutation process to a codeword made up of N bit groups each consisting of Q bits, to reorder the bits of the codeword in accordance with a bit permutation rule defining a reordering of the bits;a dividing step of dividing the codeword after the bit permutation process into a plurality of constellation words, each of the constellation words being made up of M bits; anda mapping step of mapping the plurality of constellation words to a plurality of constellation symbols, whereinN is not a multiple of M,the bit permutation rule includes a first rule and a second rule, the first rule being applied to N′=N−X bit groups, the second rule being applied to X bit groups, where X is a remainder of N divided by M,the reordering of the first rule is equivalent to a column-row permutation process including a writing process and a reading process, the bits of the N′ bit groups being written into a matrix row-by-row during the writing process, the written bits being read out from the matrix column-by-column during the reading process, the ...

TRANSMITTER, RECEIVER, AND SIGNAL PROCESSING METHOD THEREOF

A transmitter and receiver of a broadcasting signal and a method of processing the broadcasting signal are provided. The transmitter includes: a segmenter configured to segment an L signaling of a frame into a plurality of segmented L signalings such that each of the segmented L signalings has bits a number of which is equal to or smaller than a predetermined number; and an encoder configured to perform a Bose, Chaudhuri, Hocquenghem (BCH) and a low density parity check (LDPC) encoding, or the LDPC encoding without the BCH encoding, with respect to the segmented L signalings. 1. A signal generation and transmitting apparatus comprising:a segmenter configured to segment input bits into a plurality of segmented blocks according to a segmentation value, if a size of the input bits is greater than the segmentation value;a zero padder configured to fill a bit space of a predetermined size with bits and one or more zero padding bits, if a size of the bits is less than the predetermined size, the bits comprising bits of each of the plurality of segmented blocks;an encoder configured to encode bits included in the bit space to generate parity bits based on a code;a puncturer configured to puncture one or more parity bits from among the generated parity bits;a zero remover configured to remove the one or more zero padding bits from the encoded bits included in the bit space;a mapper configured to map remaining encoded bits after removing and remaining parity bits after the puncturing onto constellation points; anda transmitter configured to transmit a signal which is generated based on the constellation points,wherein the segmentation value is based on the code, a zero padding parameter and a puncturing parameter.2. The signal generation and transmitting as claimed in claim 1 , further comprising:an encoder configured to encode the plurality of segmented blocks based on a first code to generate a codeword respectively, the codeword comprising bits of a segmented block and ...

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

In a transmitting device, in interchanging to interchange a code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 7/15 with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK, when 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a bit b, a bit b, and a bit b are interchanged with a bit y, a bit y, and a bit y, respectively. A position of the interchange code hit obtained from data transmitted from the transmitting device is returned to an original position. The present technology is applicable to a case of transmitting data using an LDPC code, for example. 130-. (canceled)31. A data processing device comprising:a reverse interchanging unit configured to perform reverse interchange processing for returning a position of an interchanged code bit obtained from data transmitted from a transmitting device to an original position; and an encoding unit configured to perform LDPC encoding based on a parity check matrix of an LDPC code in which a code length is 16200 bits and an encoding rate is 7/15, and', 'an interchanging unit configured to interchange a code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 7/15 with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK,, 'a decoding unit configured to decode an LDPC code obtained by the reverse interchange processing, the transmitting device including'}wherein, when 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a (#i+1)-th bit from a most significant bit of the 3 bits of code bits is set to a bit b#i, a (#i+1)-th bit from a most significant bit of 3 bits of symbol bits of the one symbol is set to a bit y#i, and the interchanging unit interchanges{'b': 0', ' ...

PARALLEL BIT INTERLEAVER

A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process. 1. A bit interleaving method for interleaving bits of a codeword generated based on a quasi-cyclic low-density parity check coding scheme , including a repeat-accumulate quasi-cyclic low-density parity check coding scheme , the bit interleaving method comprising:a bit permutation step of applying a bit permutation process to a codeword made up of N cyclic blocks each consisting of Q bits, to reorder the bits of the codeword in accordance with a bit permutation rule defining a reordering of the bits; anda dividing step of dividing the codeword after the bit permutation process into a plurality of constellation words, each of the constellation words being made up of M bits, whereinN is not a multiple of M,the bit permutation rule includes a first rule and a second rule, the first rule being applied to N′=N−X cyclic blocks, the second rule being applied to X cyclic blocks, the first rule and the second rule differing from each other, where X is a remainder of N divided by M, andthe reordering of the first rule is equivalent to a column-row permutation process including a writing process and a reading process, the bits of the N′ cyclic blocks being written into a matrix row-by-row during the writing process, the written bits being read out from the matrix column-by-column during the reading process, the matrix having M rows, the Q bits ...

LOW DENSITY PARITY CHECK CODE FOR TERRESTRIAL CLOUD BROADCAST

Provided is an LDPC (Low Density Parity Check) code for terrestrial cloud broadcast. A method of encoding input information based on an LDPC (Low Density Parity Check) includes receiving information and encoding the input information with an LDPC codeword using a parity check matrix, wherein the parity check matrix may have a structure obtained by combining a first parity check matrix for an LDPC code having a higher code rate than a reference value with a second parity check matrix for an LDPC code having a lower code rate than the reference value. 1. A method of decoding an LDPC (Low Density Parity Check) code by an LDPC decoder , the method comprising:receiving an LDPC codeword; anddecoding the LDPC codeword corresponding to a parity check matrix, wherein the parity check matrix includes a dual diagonal matrix and an identity matrix.2. The method of claim 1 , wherein the LDPC codeword includes a systematic part corresponding to input information claim 1 , a first parity part corresponding to the dual diagonal matrix claim 1 , and a second parity part corresponding to the identity matrix.3. The method of claim 2 , wherein the LDPC codeword is generated by performing:obtaining the first parity part using accumulation corresponding to the dual diagonal matrix based on the input information; andobtaining the second parity part using the identity matrix based on the calculated first parity part.4. The method of claim 3 , wherein the LDPC codeword is generated by further performingpuncturing the LDPC codeword corresponding to predetermined locations of at least one of the first parity part and the second parity part for a target code rate.5. The method of claim 4 , wherein the puncturing corresponds to the identity matrix in the parity check matrix.6. An LDPC (Low Density Parity Check) decoder comprising:a receiving unit configured to receive an LDPC codeword; anda decoding unit configured to decode the LDPC codeword corresponding to a parity check matrix, wherein the ...

APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING DATA IN COMMUNICATION SYSTEM

An apparatus and a method for transmitting and receiving a signal in a communication system are provided. The method includes checking a type of the signal to be transmitted; determining a number of puncture bits according to the type of the signal; and puncturing an encoded signal to be transmitted according to the number of puncture bits. 1. A method for operating a transmit device , the method comprising:generating, by a hardware processor, parity bits by adding at least one shortened bit to bits comprising information bits to generate input bits for an encoding if a number of the information bits is less than a number of the input bits for the encoding, and applying the encoding to the input bits;identifying, by the hardware processor, a type of a signal to be transmitted to a receive device, the type of the signal corresponding to a protection level of the signal;determining, by the hardware processor, a first parameter and a second parameter based on the type of the signal;determining, by the hardware processor, a number of temporary puncture bits using the first parameter and the second parameter;determining, by the hardware processor, a number of puncture bits by adjusting the number of temporary puncture bits based on a modulation order of the signal;puncturing, by the hardware processor, at least one bit among the parity bits according to the number of the puncture bits;generating the signal based on remaining bits of the parity bits after the puncturing, andtransmitting, by a transceiver, to the receive device, the signal,wherein the first parameter is a ratio of a number of bits to be punctured to a number of bits to be shortened, and is multiplied by a number of the at least one shortened bit to generate a multiplication result, andwherein the second parameter is an integer that is added to the multiplication result to determine the number of temporary puncture bits.2. The method of claim 1 , wherein the type of the signal indicates whether the signal ...

Transmitting apparatus and mapping method thereof

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme.

TRANSMITTING APPARATUS AND MAPPING METHOD THEREOF

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme. 2. The apparatus as claimed in claim 1 , wherein the constellation points in one quadrant of the constellation claim 1 , and constellation points in remaining quadrants are obtained by indicating each constellation point a which is defined as a* claim 1 , −a* claim 1 , and −a claim 1 , respectively claim 1 , * indicating complex conjugation.4. The method as claimed in claim 3 , wherein the constellation points in one quadrant of the constellation claim 3 , and constellation points in remaining quadrants are obtained by indicating each constellation point a which is defined as a* claim 3 , −a* claim 3 , and −a claim 3 , respectively claim 3 , * indicating complex conjugation. This is a continuation of U.S. application Ser. No. 15/496,647 filed Apr. 25, 2017, which is a continuation of U.S. application Ser. No. 14/715,674 filed May 19, 2015, the disclosure of which is incorporated herein by reference in its entirety.Apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to transmitting and receiving date using broadcasting, more particularly, to the design of non-uniform constellations used in a Bit Interleaved Coded Modulation (BICM) mapping bits at an output of an encoder and interleaver to complex constellations.The current broadcasting systems consistent with the Digital Video Broadcasting Second Generation Terrestrial (DVB-T2) use a Bit Interleaved and Coded Modulation (BICM) chain in order to encode bits to be transmitted. The BICM chain includes a channel encoder like a Low Density Parity ...

TRANSMITTING APPARATUS AND MAPPING METHOD THEREOF

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme. 2. The receiving apparatus as claimed in claim 1 , wherein the decoder is configured to decode the deinterleaved values based on the LDPC code having a code rate of 4/15.3. The receiving apparatus as claimed in claim 1 , wherein the constellation points in the table comprise constellation points in one quadrant claim 1 , andwherein constellation points in remaining quadrants are obtained by indicating each constellation point a of the constellation points in the table as a*, −a*, and −a, respectively, * indicating complex conjugation. This is a Continuation of U.S. application Ser. No. 15/412,991 filed Jan. 23, 2017, which is a Continuation of U.S. application Ser. No. 14/715,780 filed May 19, 2015 in the United States Patent and Trademark Office, the disclosure of which is incorporated herein by reference in its entirety.Apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to transmitting and receiving date using broadcasting, more particularly, to the design of non-uniform constellations used in a Bit Interleaved Coded Modulation (BICM) mapping bits at an output of an encoder and interleaver to complex constellations.The current broadcasting systems consistent with the Digital Video Broadcasting Second Generation Terrestrial (DVB-T2) use a Bit Interleaved and Coded Modulation (BICM) chain in order to encode bits to be transmitted. The BICM chain includes a channel encoder like a Low Density Parity Check (LDPC) encoder followed by a Bit Interleaver and a Quadrature Amplitude Modulation (QAM) ...

Transmitting apparatus and signal processing method thereof

A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method.

Approaches for achieving improved capacity plans for a satellite communications system via interleaved beams from multiple satellites

A method is provided for interleaving frequency reuse plans of multiple satellites to form an aggregate frequency reuse cell plan. A first plurality of spot beams is generated by a first satellite for a first frequency reuse plan based on radio frequency (RF) spectrum bands. A second plurality of spot beams is generated by a second satellite for a second frequency reuse plan based on the RF spectrum bands. The first and second plurality of spot beams are interleaved to generate an aggregate frequency reuse cell plan. According to the aggregate frequency reuse plan, each of a first plurality of cells is covered by a combination of at least two of the plurality of spot beams of the first satellite, and each of a first plurality of cells is covered by a combination of at least two of the plurality of spot beams of the second satellite.

LOW DENSITY PARITY CHECK CODE FOR TERRESTRIAL CLOUD BROADCAST

Provided is an LDPC (Low Density Parity Check) code for terrestrial cloud broadcast. A method of encoding input information based on an LDPC (Low Density Parity Check) includes receiving information and encoding the input information with an LDPC codeword using a parity check matrix, wherein the parity check matrix may have a structure obtained by combining a first parity check matrix for an LDPC code having a higher code rate than a reference value with a second parity check matrix for an LDPC code having a lower code rate than the reference value. 1. A method of encoding input information based on an LDPC (Low Density Parity Check) , the method comprising:receiving information; andencoding the input information to an LDPC codeword using a parity check matrix,wherein the parity check matrix includes a dual diagonal matrix, and an identity matrix.2. The method of claim 1 , wherein the encoded LDPC codeword includes a systematic part corresponding to the input information claim 1 , a first parity part corresponding to the dual diagonal matrix claim 1 , and a second parity part corresponding to the identity matrix.3. The method of claim 2 , wherein said encoding comprises:calculating the first parity part using accumulation corresponding to the dual diagonal matrix based on the input information; andcalculating the second parity part using the identity matrix based on the calculated first parity part.4. The method of claim 3 , further comprisingperforming puncturing the LDPC codeword corresponding to predetermined locations of at least one of the first parity part and the second parity part for a target code rate.5. The method of claim 4 , wherein the puncturing corresponds to the identity matrix in the parity check matrix.6. An LDPC encoder comprising:an input unit receiving information; andan encoding unit encoding the input information to an LDPC codeword using a parity check matrix,wherein the parity check matrix includes a dual diagonal matrix, and an identity ...

LOW DENSITY PARITY CHECK CODE FOR TERRESTRIAL CLOUD BROADCAST

Provided is an LDPC (Low Density Parity Check) code for terrestrial cloud broadcast. A method of encoding input information based on an LDPC (Low Density Parity Check) includes receiving information and encoding the input information with an LDPC codeword using a parity check matrix, wherein the parity check matrix may have a structure obtained by combining a first parity check matrix for an LDPC code having a higher code rate than a reference value with a second parity check matrix for an LDPC code having a lower code rate than the reference value. 1. A method of decoding an LDPC code by an LDPC (Low Density Parity Check) decoder , the method comprising:receiving an LDPC codeword encoded by a parity check matrix; and a first matrix,', 'a dual diagonal matrix which has the same number of rows and columns as the number of rows of the first matrix,', 'a zero matrix which has the same number of rows as the number of columns of the dual diagonal matrix,', 'a second matrix which has the same number of rows as the number of the columns of the zero matrix, and', 'an identity matrix which has the same number of rows and columns as the number of the columns of the zero matrix,', 'wherein a last column of the first matrix is adjacent to a first column of the dual diagonal matrix in the parity check matrix, a last row of the first matrix and a last row of the dual diagonal matrix are adjacent to a first row of the second matrix in the parity check matrix, and wherein an element matrix of the dual diagonal matrix constituting a dual diagonal line is continuous to an element matrix that constitutes a diagonal line of the identity matrix., 'decoding the received LDPC codeword using the parity check matrix, wherein the parity check matrix includes'}2. The method of claim 1 , the identity matrix is adjacent to the second matrix and the zero matrix.3. The method of claim 2 , wherein the encoded LDPC codeword includes a systematic part corresponding to the input information claim 2 , ...

SYSTEMS AND METHODS FOR ADVANCED ITERATIVE DECODING AND CHANNEL ESTIMATION OF CONCATENATED CODING SYSTEMS

Systems and methods for decoding block and concatenated codes are provided. These include advanced iterative decoding techniques based on belief propagation algorithms, with particular advantages when applied to codes having higher density parity check matrices such as iterative soft-input soft-output and list decoding of convolutional codes, Reed-Solomon codes and BCH codes. Improvements are also provided for performing channel state information estimation including the use of optimum filter lengths based on channel selectivity and adaptive decision-directed channel estimation. These improvements enhance the performance of various communication systems and consumer electronics. Particular improvements are also provided for decoding HD radio signals, satellite radio signals, digital audio broadcasting (DAB) signals, digital audio broadcasting plus (DAB+) signals, digital video broadcasting-handheld (DVB-H) signals, digital video broadcasting-terrestrial (DVB-T) signals, world space system signals, terrestrial-digital multimedia broadcasting (T-DMB) signals, and China mobile multimedia broadcasting (CMMB) signals. These and other improvements enhance the decoding of different digital signals. 1. A method for iteratively decoding a digital signal , the signal being an Orthogonal Frequency-Division Multiplexed (OFDM) signal comprising OFDM reference subcarriers , OFDM data subcarriers , and OFDM symbol intervals , the method comprising:a. performing OFDM demodulation and subcarrier de-mapping of the digital signal into system control and data sequence symbols to obtain received distorted modulated symbols;b. performing initial channel state information estimation based on the received distorted modulated symbols, wherein said received distorted modulated symbols are carried by a plurality of OFDM data subcarriers and a plurality of OFDM reference subcarriers in at least one OFDM symbol interval;c. performing phase correction of the received distorted modulated symbols ...

TRANSMITTER, RECEIVER, AND SIGNAL PROCESSING METHOD THEREOF

A transmitter and receiver of a broadcasting signal and a method of processing the broadcasting signal are provided. The transmitter includes: a segmenter configured to segment an L1 signaling of a frame into a plurality of segmented L1 signalings such that each of the segmented L1 signalings has bits a number of which is equal to or smaller than a predetermined number; and an encoder configured to perform a Bose, Chaudhuri, Hocquenghem (BCH) and a low density parity check (LDPC) encoding, or the LDPC encoding without the BCH encoding, with respect to the segmented L1 signalings. 1. A transmitter comprising:a segmenter configured to segment an L1 signaling of a frame into a plurality of segmented L1 signalings such that each of the segmented L1 signalings has bits a number of which is equal to or smaller than a predetermined number; andan encoder configured to perform a Bose, Chaudhuri, Hocquenghem (BCH) encoding and a low density parity check (LDPC) encoding, or the LDPC encoding without the BCH encoding, with respect to the segmented L1 signalings.2. The transmitter as claimed in claim 1 , wherein the predetermined number is smaller than at least one of a length of an information word of the BCH encoding and a length of an information word of the LDPC encoding.3. The transmitter as claimed in claim 1 , wherein the predetermined number is calculated based on t a predetermined transmission code rate claim 1 , a number of parity bits generated by the BCH encoding claim 1 , and a number of parity bits generated by the LDPC encoding.5. The transmitter as claimed in claim 1 , wherein the encoder is configured to add at least one padding bit to a segmented L1 signaling among the segmented L1 signalings so that all of the at least one padding bit has a same value.6. A signal processing method of a transmitter comprising:segmenting an L1 signaling of a frame into a plurality of segmented L1 signalings such that each of the segmented L1 signalings has bits a number of which ...

TRANSMITTING APPARATUS AND SIGNAL PROCESSING METHOD THEREOF

A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method. 1. An interleaving method comprising:interleaving a codeword; andmapping bits of the interleaved codeword onto constellation points,wherein the interleaving comprises:splitting the codeword into a plurality of bit groups;interleaving the plurality of bit groups; andinterleaving the interleaved plurality of bit groups using a plurality of columns, each of the plurality of columns comprising a first part and a second part,wherein some bit groups of the interleaved plurality of bit groups are interleaved in the first part, and at least one remaining bit group is interleaved in the second part, andwherein bits of the some bit groups and bits of the at least one remaining bit group are written in a column direction and are read out in a row direction.2. The method as claimed in claim 1 , wherein each of the plurality of bit groups comprises 360 bits.3. The method as claimed in claim 1 , wherein the interleaving further comprises interleaving the parity bits claim 1 , andwherein the splitting comprises splitting an codeword comprising the interleaved parity bits into a plurality of bit groups. This is a Continuation Application of U.S. application Ser. No. 14/527,953 filed Oct. 30, 2014, which claims the benefit under 35 U.S.C. § 119 from U.S. Provisional Application No. 61/897,460 field on Oct. 30, 2013, in the ...

SYSTEMS AND METHODS FOR ADVANCED ITERATIVE DECODING AND CHANNEL ESTIMATION OF CONCATENATED CODING SYSTEMS

Systems and methods for decoding block and concatenated codes are provided. These include advanced iterative decoding techniques based on belief propagation algorithms, with particular advantages when applied to codes having higher density parity check matrices such as iterative soft-input soft-output and list decoding of convolutional codes, Reed-Solomon codes and BCH codes. Improvements are also provided for performing channel state information estimation including the use of optimum filter lengths based on channel selectivity and adaptive decision-directed channel estimation. These improvements enhance the performance of various communication systems and consumer electronics. Particular improvements are also provided for decoding HD radio signals, satellite radio signals, digital audio broadcasting (DAB) signals, digital audio broadcasting plus (DAB+) signals, digital video broadcasting-handheld (DVB-H) signals, digital video broadcasting-terrestrial (DVB-T) signals, world space system signals, terrestrial-digital multimedia broadcasting (T-DMB) signals, and China mobile multimedia broadcasting (CMMB) signals. These and other improvements enhance the decoding of different digital signals. 1. A method for generating check-to-variable messages during an iteration in decoding of codes represented by a parity check matrix , the method comprising the following steps for at least one variable node:a. calculating a check-to-variable message Mcv(i,j) from check node i to variable node j;{'sub': 1', '2, 'b. identifying two smallest absolute values, Minand Min, in a set of variable-to-check messages Mvc(i, k), where k≠j, excluding the message from variable j to check node i, Mvc(i,j);'}{'sub': 1', '2, 'c. calculating a scaling factor α=1−β·Min/Min, where β is a non-negative number such that 0≤β≤1; and'}d. scaling the check-to-variable message Mcv(i,j) as Mcv(i,j)=α·Mcv(i,j).2. The method of wherein the check-to-variable message Mcv(i claim 1 ,j) from check node i to ...

SIGNALLING CODING AND MODULATION METHOD AND DEMODULATION AND DECODING METHOD AND DEVICE

Provided are a signaling coding and modulation method and a demodulation and decoding method and device, characterized in that the method comprises the steps of: extending signaling which has been subjected to first predetermined processing according to an extension pattern table to obtain an extended codeword, and conducting predetermined coding on the extended codeword to obtain a encoded codeword; conducting parity bit permutation on a parity bit portion in the encoded codeword and then splicing the permutated parity bits to the end of information bits in the encoded codeword, to obtain a permutated encoded codeword; according to the length of the signaling, punching the permutated encoded codeword according to a predetermined punching rule to obtain a punched encoded codeword; and conducting second predetermined processing on the punched encoded codeword to obtain a tuple sequence, which is used for mapping, and then mapping the tuple sequence, which is used for mapping, into a signaling symbol according to a predetermined mapping rule. 1. A signalling coding and modulation method , characterized in that the method comprises the steps of:extending signaling which has been subjected to first predetermined processing according to an extension pattern table to obtain an extended codeword, and conducting predetermined coding on the extended codeword to obtain a encoded codeword;conducting parity bit permutation on parity bits in the encoded codeword and then splicing the permutated parity bits to the end of information bits in the encoded codeword, to obtain a permutated encoded codeword;according to the length of the signalling, punching the permutated encoded codeword according to a predetermined punching rule to obtain a punched encoded codeword; andconducting second predetermined processing on the punched encoded codeword to obtain a tuple sequence, which is used for mapping, and then mapping the obtained tuple sequence into a signalling symbol according to a ...

Broadcast signal frame generating apparatus and broadcast signal frame generating method using bootstrap and preamble

An apparatus and method for broadcast signal frame using a bootstrap and a preamble are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a time interleaver configured to generate a time-interleaved signal by performing interleaving on a BICM output signal; and a frame builder configured to generate a broadcast signal frame including a bootstrap and a preamble using the time-interleaved signal.

PARALLEL BIT INTERLEAVER

A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process. 1. A transmission method comprising:generating a codeword according to a low density parity check coding scheme such that the codeword includes N bit groups each consisting of Q bits, a parity check matrix of the low density parity check coding scheme having a quasi-cyclic structure;reordering bits in the codeword;dividing the codeword into constellation words each consisting of M bits after the bits in the codeword are reordered; andgenerating a transmission signal based on the constellation words,wherein a first part of the N bit groups is constituted by K bit groups and bits of the K bit groups are written into an M by Q matrix row-by-row and the written bits of the K bit groups are read from the M by Q matrix column-by-column in order to reorder the bits in the codeword, andwherein a second part of the N bit groups is constituted by L bit groups, and bits of the L bit groups are mapped onto the constellation words in a state where bits in the L bit groups are not reordered.2. A transmission device comprising:generating circuitry configured to generate a codeword according to a low density parity check coding scheme such that the codeword includes N bit groups each consisting of Q bits, a parity check matrix of the low density parity check coding scheme having a quasi-cyclic structure;reordering circuitry connected to the ...

MODULATOR AND MODULATION METHOD USING NON-UNIFORM 16-SYMBOL SIGNAL CONSTELLATION FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING 2/15 CODE RATE

A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 2/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis. 116. A modulation method using a non-uniform -symbol signal constellation , comprising:receiving a codeword having a code rate of 2/15;mapping the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis; andadjusting at least one of amplitude and phase of a carrier in accordance with the mapping.2. The modulation method of claim 1 , wherein the 16 symbols have non-uniform distances therebetween claim 1 , and comprise a first group of four symbols of a 1st quadrant claim 1 , a second group of four symbols symmetric to the four symbols of the first group with respect to an imaginary axis claim 1 , a third group of four symbols symmetric to the four symbols of the first group with respect to an origin claim 1 , and a fourth group of four symbols symmetric to the four symbols of the first group with respect to a real axis.3. The modulation method of claim 1 , wherein a vector corresponding to four symbols w claim 1 , w claim 1 , w claim 1 , and wof a first group is w claim 1 , a vector corresponding to four symbols w claim 1 , w claim 1 , wand wof a second group is −conj(w) (conj(w) is a function that outputs conjugate complex numbers of all elements of w) claim 1 , a vector corresponding to four symbols w claim 1 , w claim 1 , wand wof a third group is −w claim 1 , and a vector corresponding to four symbols w claim 1 , w claim 1 , wand wof a fourth group is conj(w).4. The modulation method of claim 3 , wherein amplitudes of real and imaginary components of two of the four symbols of the first group are symmetric.5. The modulation method of claim 4 , wherein the ...

MODULATOR AND MODULATION METHOD USING NON-UNIFORM 16-SYMBOL SIGNAL CONSTELLATION FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING 4/15 CODE RATE

A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 4/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.

Transmitting apparatus and signal processing method thereof

A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver is formed of a plurality of columns each including a plurality of rows and includes a block interleaver configured to divide each of the plurality of columns into a first part and a second part and interleave the LDPC codeword, the number of rows constituting each column divided into the first part is determined differently depending upon the modulation method, wherein the number of rows constituting each column divided into the second part is determined depending upon the number of rows constituting each column divided into the first part.

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 2/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to . The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). 1. A low density parity check (LDPC) decoder , comprising:a receiving unit configured to receive a signal corresponding to an LDPC codeword having a length of 64800 and a code rate of 2/15, the LDPC codeword encoded using a sequence corresponding to a parity check matrix (PCM); anda decoding unit configured to perform decoding the received signal, the decoding corresponding to the parity check matrix.3. The LDPC decoder of claim 2 , wherein the LDPC codeword comprises a systematic part corresponding to information bits and having a length of 8640 claim 2 , a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 1800 claim 2 , and a second parity part corresponding to an identity matrix included in the PCM and having a length of 54360.4. The LDPC decoder of claim 3 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part claim 3 , that is claim 3 , 8640 claim 3 , by a circulant permutation matrix (CPM) size corresponding to the PCM claim 3 , that is claim 3 , 360 claim 3 , and a value obtained by dividing a length of the first parity part claim 3 , that is claim 3 , 1800 claim 3 , by the CPM size.5. The LDPC decoder of claim 2 , wherein the LDPC codeword is generated by performing accumulation with respect to a memory and the accumulation is performed at parity bit addresses that are updated using the sequence.6. The LDPC decoder of claim 5 , wherein the ...

PARALLEL BIT INTERLEAVER

A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each imade up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section. 1. A transmitting method for transmitting a codeword generated based on a quasi-cyclic low-density parity check coding scheme , including a repeat-accumulate quasi-cyclic low-density parity check coding scheme , the transmitting method comprising:a cyclic block permutation step of applying a cyclic block permutation process to a codeword made up of N cyclic blocks each consisting of Q bits, to reorder the cyclic blocks in accordance with a cyclic block permutation rule defining a reordering of the cyclic blocks;a bit permutation step of applying a bit permutation process to the codeword after the cyclic block permutation process, to reorder the bits of the codeword in accordance with a bit permutation rule defining a reordering of the bits;a dividing step of dividing the codeword after the bit permutation process into a plurality of constellation words, each of the constellation words being made up of M bits, anda transmitting step of transmitting a transmitting signal generated from the constellation words, whereinN is a multiple of M,the bit permutation rule defines the reordering of the bits of the codeword after the cyclic block permutation process, the reordering of the bit permutation rule is equivalent to a column-row permutation process including a writing process and a reading process, the bits of the N cyclic blocks being written into a matrix row-by-row during the writing process, the written bits ...

TRANSMITTING APPARATUS AND MAPPING METHOD THEREOF

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme. 2. The method as claimed in claim 1 , wherein the represented constellation points comprise constellation points in one quadrant claim 1 , andwherein constellation points in remaining quadrants are obtained by indicating each constellation point a among the constellation points in the one quadrant as a*, −a*, and −a, respectively, * indicating complex conjugation. This is a continuation of U.S. patent application Ser. No. 14/714,508, filed May 18, 2015. The entire disclosures of the prior applications are considered part of the disclosure of the accompanying continuation application, and are hereby incorporated by reference.Apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to transmitting and receiving date using broadcasting, more particularly, to the design of non-uniform constellations used in a Bit Interleaved Coded Modulation (BICM) mapping bits at an output of an encoder and interleaver to complex constellations.The current broadcasting systems consistent with the Digital Video Broadcasting Second Generation Terrestrial (DVB-T2) use a Bit Interleaved and Coded Modulation (BICM) chain in order to encode bits to be transmitted. The BICM chain includes a channel encoder like a Low Density Parity Check (LDPC) encoder followed by a Bit Interleaver and a Quadrature Amplitude Modulation (QAM) mapper. The role of the QAM mapper is to map different bits output from the channel encoder and interleaved using the Bit Interleaver to QAM cells. Each cell represents a complex number having real and ...

TRANSMITTING APPARATUS AND MAPPING METHOD THEREOF

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme. 2. The transmitting method as claimed in claim 1 , wherein the listed constellation points comprise constellation points in one quadrant claim 1 , andwherein constellation points in remaining quadrants are obtained by indicating each constellation point a which is defined in the table as a*, −a*, and −a, respectively, * indicating complex conjugation.4. The receiving method as claimed in claim 3 , wherein the listed constellation points comprise constellation points in one quadrant claim 3 , andwherein constellation points in remaining quadrants are obtained by indicating each constellation point a which is defined in the list as a*, −a*, and −a, respectively, * indicating complex conjugation. This is a continuation of U.S. application Ser. No. 16/923,322 filed Jul. 8, 2020, which is a continuation of U.S. application Ser. No. 16/244,713, filed Jan. 10, 2019, which is a continuation of U.S. application Ser. No. 15/881,076, filed Jan. 26, 2018, which is a continuation of U.S. application Ser. No. 14/714,624 filed May 18, 2015, the disclosure of which is incorporated herein by reference in its entirety.Apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to transmitting and receiving date using broadcasting, more particularly, to the design of non-uniform constellations used in a Bit Interleaved Coded Modulation (BICM) mapping bits at an output of an encoder and interleaver to complex constellations.The current broadcasting systems consistent with the Digital Video Broadcasting Second Generation ...

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 2/15 AND 16-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping. 1. A BICM reception device , comprising:a demodulator configured to perform demodulation corresponding to 16-symbol mapping;a bit deinterleaver configured to perform group-unit deinterleaving on a interleaved codeword, the interleaved codeword generated after the demodulation; anda decoder configured to restore information bits by LDPC-decoding a deinterleaved codeword generated based on the group-unit deinterleaving, the deinterleaved codeword corresponding to a LDPC codeword having a length of 64800 and a code rate of 2/15,wherein the group-unit deinterleaving is performed on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword.2. The BICM reception device of claim 1 , wherein the group-unit deinterleaving corresponds to interleaving performed by using permutation order claim 1 , and {'br': None, 'interleaving sequence={5 58 29 154 125 34 0 169 80 59 13 42 77 167 32 87 24 92 124 143 114 120 166 138 64 136 149 57 18 101 119 35 33 113 75 108 104 3 27 39 172 159 129 62 146 142 19 147 111 70 74 79 10 132 1 161 155 90 15 133 47 112 84 28 160 117 150 49 7 81 44 63 118 4 158 148 82 69 36 162 86 71 22 26 61 40 126 170 177 23 91 68 56 110 21 93 107 85 20 128 109 66 83 12 179 141 97 78 157 72 130 99 165 45 11 152 168 14 16 2 137 140 121 173 50 55 94 144 73 51 98 174 178 17 100 9 122 54 38 156 131 127 164 102 116 176 30 37 139 95 43 135 53 89 106 ...

TRANSMITTING APPARATUS AND SIGNAL PROCESSING METHOD THEREOF

A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method. 1. A receiving apparatus comprising:a receiver configured to receive a signal from a transmitting apparatus;a demodulator configured to demodulate the signal to generate values;a deinterleaver configured to deinterleave the values; anda decoder configured to decode bits using the deinterleaved values,wherein the decoder is configured to decode bits based on a low density parity check (LDPC) code,wherein the deinterleaver is configured to deinterleave the values using a plurality of rows, split the deinterleaved values into a plurality of groups and deinterleave the plurality of groups,wherein each of the plurality of rows comprises a first part and a second part,wherein a number of values to be written in the first part is determined based on a number of the plurality of rows and a number of values of each of the plurality of groups, andwherein a number of values to be written in the second part is determined based on the number of the plurality of rows and the number of the values of each of the plurality of groups.2. The receiving apparatus as claimed in claim 1 , wherein each of the plurality of groups comprises 360 values.3. The receiving apparatus as claimed in claim 1 , wherein the number of the plurality of rows is equal to a modulation order for the demodulating. This application is a Continuation ...

TRANSMITTING APPARATUS AND SIGNAL PROCESSING METHOD THEREOF

A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method. 1. An interleaving method of a transmitting apparatus , the method comprising:encoding input bits to generate parity bits;splitting a codeword comprising the input bits and the parity bits into a plurality of bit groups;interleaving the plurality of bit groups;interleaving the interleaved plurality of bit groups using a plurality of containers to provide an interleaved codeword, each of the plurality of containers comprising a first part and a second part;mapping the interleaved codeword onto constellation points, andtransmitting at least one of the constellation points,wherein a number of bits to be written in the first part is determined based on a number of the plurality of containers and a number of bits of each of the plurality of bit groups, andwherein a number of bits to be written in the second part is determined based on the number of the plurality of containers and the number of the bits of each of the plurality of bit groups.2. The method as claimed in claim 1 , wherein each of the plurality of bit groups comprises 360 bits.3. The method as claimed in claim 1 , further comprising:interleaving the parity bits,wherein the splitting splits a codeword comprising the input bits and the interleaved parity bits into the plurality of bit groups.4. The method as claimed in claim 1 , wherein some bit ...

Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 4/15 and 64-symbol mapping, and bit interleaving method using same

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 4/15 and quadrature phase shift keying, and bit interleaving method using same

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 2/15 AND 16-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping. 1. A bit interleaving method , comprising:storing a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15;generating an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword; andstoring the interleaved codeword corresponding to a modulator for 16-symbol mapping.2. The bit interleaving method of claim 1 , wherein the 16-symbol mapping is a Non-Uniform Constellation (NUC) symbol mapping which corresponds to 16 constellations.3. The bit interleaving method of claim 2 , wherein the parallel factor is 360 claim 2 , and the bit group includes 360 bits.6. The bit interleaving method of claim 5 , wherein the permutation order corresponds to an interleaving sequence represented by the following{'br': None, 'interleaving sequence={5 58 29 154 125 34 0 169 80 59 13 42 77 167 32 87 24 92 124 143 114 120 166 138 64 136 149 57 18 101 119 35 33 113 75 108 104 3 27 39 172 159 129 62 146 142 19 147 111 70 74 79 10 132 1 161 155 90 15 133 47 112 84 28 160 117 150 49 7 81 44 63 118 4 158 148 82 69 36 162 86 71 22 26 61 40 126 170 177 23 91 68 56 110 21 93 107 85 20 128 109 66 83 12 179 141 97 78 157 72 130 99 165 45 11 152 168 14 16 2 137 140 121 173 50 55 94 144 73 51 98 174 178 17 100 9 122 54 38 156 131 127 164 102 116 176 30 37 139 95 43 135 53 89 106 171 76 175 ...

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 7/15 AND QUADRATURE PHASE SHIFT KEYING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation. 1. A bit interleaving method , comprising:storing a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15;generating an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword; andstoring the interleaved codeword corresponding to a modulator for quadrature phase shift keying (QPSK) modulation.2. The bit interleaving method of claim 1 , wherein the parallel factor is 360 claim 1 , and the bit group includes 360 bits.3. The bit interleaving method of claim 2 , wherein the LDPC codeword is represented by (uu claim 2 , . . . claim 2 ,u) (where Nis 64800) claim 2 , and is divided into 180 bit groups each including 360 bits claim 2 , as in the following equation:{'br': None, 'i': X', '={u', '×j≦k', 'j+', '≦k Подробнее

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 3/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping. 1. A bit interleaving method , comprising:storing a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15;generating an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword; andoutputting the interleaved codeword for 64-symbol mapping.2. The bit interleaving method of claim 1 , wherein the 64-symbol mapping is a Non-Uniform Constellation (NUC) symbol mapping which corresponds to 64 constellations.3. The bit interleaving method of claim 2 , wherein the parallel factor is 360 claim 2 , and the bit group includes 360 bits.6. The bit interleaving method of claim 5 , wherein the permutation order corresponds to an interleaving sequence represented by the following{'br': None, 'interleaving sequence={74 72 104 62 122 35 130 0 95 150 139 151 133 109 31 59 18 148 9 105 57 132 102 100 115 101 7 21 141 30 8 1 93 92 163 108 52 159 24 89 117 88 178 113 98 179 144 156 54 164 12 63 39 22 25 137 13 41 44 80 87 111 145 23 85 166 83 55 154 20 84 58 26 126 170 103 11 33 172 155 116 169 142 70 161 47 3 162 77 19 28 97 124 6 168 107 60 76 143 121 42 157 65 43 173 56 171 90 131 119 94 5 68 138 149 73 67 53 61 4 86 99 75 36 15 48 177 167 174 51 176 81 120 158 123 34 49 128 10 134 147 96 160 50 146 16 38 78 91 152 46 127 27 175 135 79 125 82 2 129 153 14 40 32 114 106 ...

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 2/15 AND 256-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping. 1. A bit interleaving method , comprising:storing a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15;generating an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword; andstoring the interleaved codeword corresponding to a modulator for 256-symbol mapping.2. The bit interleaving method of claim 1 , wherein the 256-symbol mapping is a Non-Uniform Constellation (NUC) symbol mapping which corresponds to 256 constellations.3. The bit interleaving method of claim 2 , wherein the parallel factor is 360 claim 2 , and the bit group includes 360 bits.5. The bit interleaving method of claim 1 , wherein the interleaving is performed using the following equation using permutation order:{'br': None, 'i': Y', '=X', '≦j≦N, 'sub': j', 'π(j)', 'group, '0'}{'sub': π(j)', 'j, 'where Xis the π(j) th bit group, Yis an interleaved j-th bit group, and π(j) is a permutation order for bit group-based interleaving.'} This application is a continuation of and claims priority to U.S. application Ser. No. 14/639,646 filed Mar. 5, 2015, which claims the benefit of Korean Patent Application No. 10-2015-0023409, filed Feb. 16, 2015, which are hereby incorporated by reference herein in their entirety.1. Technical FieldThe present disclosure relates generally to an ...

TRANSMITTER, RECEIVER, AND SIGNAL PROCESSING METHOD THEREOF

A transmitter and receiver of a broadcasting signal and a method of processing the broadcasting signal are provided. The transmitter includes: a segmenter configured to segment an L1 signaling of a frame into a plurality of segmented L1 signalings such that each of the segmented L1 signalings has bits a number of which is equal to or smaller than a predetermined number; and an encoder configured to perform a Bose, Chaudhuri, Hocquenghem (BCH) and a low density parity check (LDPC) encoding, or the LDPC encoding without the BCH encoding, with respect to the segmented L1 signalings. 1. A transmitter comprising:a segmenter configured to segment input bits based on a predetermined value;a zero padder configured to pad zero bits;a Low-Density Parity Check (LDPC) encoder configured to encode LDPC information bits comprising the segmented input bits and the padded zero bits to generate parity bits;a puncturer configured to puncture one or more bits of the parity bits; anda zero bits remover configured to remove the zero bits,wherein the predetermined value is determined based on an LDPC code of the LDPC encoder and a ratio of a number of parity bits to be punctured and a number of zero bits to be padded.2. The transmitter as claimed in claim 1 , further comprising:a Bose, Chaudhuri, Hocquenghem (BCH) encoder configured to encode the segmented input bits to generate BCH encoded bits,wherein the LDPC information bits comprise the BCH encoded bits and the padded zero bits.3. The transmitter as claimed in claim 2 , wherein the predetermined number is smaller than at least one of a number of BCH information bit for the BCH encoder and a number of the LDPC information bits for the LDPC encoder.4. The transmitter as claimed in claim 2 , wherein the predetermined number is calculated based on a predetermined transmission code rate claim 2 , a number of parity bits generated by the BCH encoder and a number of parity bits generated by the LDPC encoder.6. A signal processing method of ...

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 4/15 AND 16-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping. 1. A bit-interleaved coded modulation (BICM) reception device , comprising:a demodulator configured to perform demodulation corresponding to 16-symbol mapping;a bit deinterleaver configured to perform group-unit deinterleaving on interleaved values, the interleaved values generated after the demodulation; anda decoder configured to restore information bits by LDPC-decoding deinterleaved values generated based on the group-unit deinterleaving, the deinterleaved values corresponding to a LDPC codeword having a length of 16200 and a code rate of 4/15,wherein the group-unit deinterleaving is performed on a group basis, the size of the group corresponding to a parallel factor of the LDPC codeword,wherein the LDPC codeword is encoded using a sequence corresponding to a parity check matrix (PCM) and comprises a systematic part corresponding to information bits and having a length of 4320, a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 1080, and a second parity part corresponding to an identity matrix included in the PCM and having a length of 10800.2. The BICM reception device of claim 1 , wherein the group-unit deinterleaving corresponds to a reverse process of interleaving performed by using a permutation order claim 1 , and {'br': None, 'interleaving sequence={34 3 19 35 25 2 17 36 26 38 0 40 27 10 7 43 21 28 15 6 1 37 18 30 32 33 29 ...

TRANSMITTING APPARATUS AND SIGNAL PROCESSING METHOD THEREOF

A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method. 1. A receiving method comprising:receiving a signal from a transmitting apparatus;demodulating the signal to generate values;deinterleaving the values using a plurality of columns; anddecoding the deinterleaved values based on a low density parity check (LDPC) code,wherein each of the plurality of columns comprises a first part and a second part,wherein some values of the values are deinterleaved in the first part and at least one remaining value is deinterleaved in the second part, andwherein the some values and the at least one remaining value are written in a row direction and are read out in a column direction.2. The method as claimed in claim 1 , further comprising:splitting the deinterleaved values into a plurality of groups; anddeinterleaving the deinterleaved plurality of groups.3. The method as claimed in claim 2 , wherein each of the plurality of groups comprises 360 values.4. A transmitting method comprising:encoding input bits based on a low density parity check (LDPC) code to generate a codeword;splitting the codeword into a plurality of bit groups;interleaving the plurality of bit groups;interleaving bits of the interleaved plurality of bit groups using a plurality of columns, each of the plurality of columns comprising a first part and a second part; andmapping the interleaved bits to ...

TRANSMITTING APPARATUS AND MAPPING METHOD THEREOF

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme. 2. The apparatus as claimed in claim 1 , wherein the encoder encodes the input bits according to a code rate of 4/15.3. The apparatus as claimed in claim 1 , wherein the constellation points as defined in the table comprises constellation points in one quadrant claim 1 , andwherein constellation points in remaining quadrants are obtained by indicating each constellation point a which is defined in the table as a*, −a*, and −a, respectively, * indicating complex conjugation. This application is a Continuation of U.S. application Ser. No. 14/715,780 filed May 19, 2015 in the United States Patent and Trademark Office, the disclosure of which is incorporated herein by reference in its entirety.1. FieldApparatuses and methods consistent with exemplary embodiments of the inventive concept relate to transmitting and receiving date using broadcasting, more particularly, to the design of non-uniform constellations used in a Bit Interleaved Coded Modulation (BICM) mapping bits at an output of an encoder and interleaver to complex constellations.2. Description of the Related ArtThe current broadcasting systems consistent with the Digital Video Broadcasting Second Generation Terrestrial (DVB-T2) use a Bit Interleaved and Coded Modulation (BICM) chain in order to encode bits to be transmitted. The BICM chain includes a channel encoder like a Low Density Parity Check (LDPC) encoder followed by a Bit Interleaver and a Quadrature Amplitude Modulation (QAM) mapper. The role of the QAM mapper is to map different bits output from the channel encoder ...

Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 2/15 and 256-symbol mapping, and bit interleaving method using same

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol. 2. The receiving method of claim 1 , wherein each of the plurality of groups comprises 360 values.3. The receiving method of claim 1 , further comprising:deinterleaving one or more values from among the values of the deinterleaved plurality of groups, andwherein the decoding comprises decoding the values of the deinterleaved plurality of groups comprising the deinterleaved one or more values.5. The transmitting method of claim 4 , wherein each of the plurality of bit groups comprises 360 values. This is a continuation application of U.S. application Ser. No. 16/510,405, filed on Jul. 12, 2019, which is a continuation of U.S. application Ser. No. 14/625,795 filed Feb. 19, 2015, now U.S. Pat. No. 10,425,110, issued on Sep. 24, 2019, which claims priority from U.S. Provisional Application No. 61/941,708 filed on Feb. 19, 2014 and Korean Patent Application No. 10-2015-0024183 filed on Feb. 17, 2015, the disclosures of which are incorporated herein by reference in their entirety.Apparatuses and methods consistent with exemplary embodiments relate to a transmitting apparatus and an interleaving method thereof, and more particularly, to a transmitting apparatus which processes and transmits data, and an interleaving method thereof.In the 21st century information-oriented society, broadcasting communication services are moving into the era of digitalization, multi-channel, wideband, and high quality. In particular, as ...

Transmitter, receiver, and signal processing method thereof

A transmitter and receiver of a broadcasting signal and a method of processing the broadcasting signal are provided. The transmitter includes: a segmenter configured to segment an L1 signaling of a frame into a plurality of segmented L1 signalings such that each of the segmented L1 signalings has bits a number of which is equal to or smaller than a predetermined number; and an encoder configured to perform a Bose, Chaudhuri, Hocquenghem (BCH) and a low density parity check (LDPC) encoding, or the LDPC encoding without the BCH encoding, with respect to the segmented L1 signalings.

Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 4/15 and 16-symbol mapping, and bit interleaving method using same

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.

TRANSMITTING APPARATUS AND MAPPING METHOD THEREOF

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme. 2. The receiving apparatus as claimed in claim 1 , wherein the listed constellation points comprises constellation points in one quadrant claim 1 , andwherein constellation points in remaining quadrants are obtained by indicating each constellation point a which is defined in the list as a*, -a*, and -a, respectively, * indicating complex conjugation.4. The receiving method as claimed in claim 3 , wherein the listed constellation points comprises constellation points in one quadrant claim 3 , andwherein constellation points in remaining quadrants are obtained by indicating each constellation point a which is defined in the list as a*, -a*, and -a, respectively, * indicating complex conjugation. This application is a continuation of U.S. application Ser. No. 15/881,076, filed Jan. 26, 2018, which is a continuation of U.S. application Ser. No. 14/714,624 filed May 18, 2015, the disclosure of which is incorporated herein by reference in its entirety.Apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to transmitting and receiving date using broadcasting, more particularly, to the design of non-uniform constellations used in a Bit Interleaved Coded Modulation (BICM) mapping bits at an output of an encoder and interleaver to complex constellations.The current broadcasting systems consistent with the Digital Video Broadcasting Second Generation Terrestrial (DVB-T2) use a Bit Interleaved and Coded Modulation (BICM) chain in order to encode bits to be transmitted. The BICM chain includes a channel ...

TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol. 1. A data processing apparatus , comprising:an interleaver configured to split a codeword comprising information bits and parity bits into a plurality of bit groups and interleave the plurality of bit groups to provide an interleaved codeword;a demultiplexer configured to demultiplex the interleaved codeword to generate data cells; anda mapper configured to map the data cells onto constellation points for quadrature phase shift keying modulation,wherein the parity bits are generated based on the information bits and a forward error correction code according to a code rate of 5/15 and a code length of 16200, and {'br': None, 'i': Y', '=X', 'j Подробнее

LOW DENSITY PARITY CHECK CODE FOR TERRESTRIAL CLOUD BROADCAST

Provided is an LDPC (Low Density Parity Check) code for terrestrial cloud broadcast. A method of encoding input information based on an LDPC (Low Density Parity Check) includes receiving information and encoding the input information with an LDPC codeword using a parity check matrix, wherein the parity check matrix may have a structure obtained by combining a first parity check matrix for an LDPC code having a higher code rate than a reference value with a second parity check matrix for an LDPC code having a lower code rate than the reference value. 1. A method of decoding an LDPC (Low Density Parity Check) code by an LDPC decoder , the method comprising;receiving a signal corresponding to an LDPC codeword; andperforming decoding for the signal, the LDPC codeword corresponding to a parity check matrix, wherein the parity check matrix includes a dual diagonal matrix and an identity matrix.2. The method of claim 1 , wherein the dual diagonal matrix corresponds to dual diagonal lines and the identity matrix corresponds to a diagonal line.3. The method of claim 2 , wherein an element of the dual diagonal lines is located at the neighboring location of an element of the diagonal line.4. The method of claim 1 , wherein the LDPC codeword includes a systematic part corresponding to input information claim 1 , a first parity part corresponding to the dual diagonal matrix claim 1 , and a second parity part corresponding to the identity matrix.5. The method of claim 4 , wherein the LDPC codeword is generated by performing:obtaining the first parity part using accumulation corresponding to the dual diagonal matrix based on the input information; andobtaining the second parity part using the identity matrix based on the calculated first parity part.6. The method of claim 5 , wherein the LDPC codeword is generated by further performingpuncturing the LDPC codeword corresponding to predetermined locations of at least one of the first parity part and the second parity part for a ...

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 4/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping. 1. A bit-interleaved coded modulation (BICM) reception device , comprising:a demodulator configured to perform demodulation corresponding to 64-symbol mapping;a bit deinterleaver configured to perform group-unit deinterleaving on interleaved values, the interleaved values generated after the demodulation; anda decoder configured to restore information bits by LDPC-decoding deinterleaved values generated based on the group-unit deinterleaving, the deinterleaved values corresponding to a LDPC codeword having a length of 64800 and a code rate of 4/15,wherein the group-unit deinterleaving is performed on a group basis, the size of the group corresponding to a parallel factor of the LDPC codeword.2. The BICM reception device of claim 1 , wherein the group-unit deinterleaving corresponds to interleaving performed by using permutation order claim 1 , and {'br': None, 'interleaving sequence={141 80 47 89 44 7 46 11 175 173 99 2 155 52 86 128 174 33 170 31 35 162 64 95 92 4 16 49 137 104 29 9 60 167 50 23 43 176 121 71 132 103 144 39 12 90 114 131 106 76 118 66 24 58 122 150 57 149 93 53 14 73 165 82 126 97 59 133 154 153 72 36 5 96 120 134 101 61 115 0 28 42 18 145 156 85 146 6 161 10 22 138 127 151 87 54 20 139 140 152 13 91 111 25 123 77 78 69 3 177 41 81 19 107 45 148 70 160 51 21 116 48 157 17 125 142 83 110 37 98 179 129 168 172 1 40 166 159 147 56 100 63 26 169 135 15 75 84 163 79 143 113 ...

TRANSMITTING APPARATUS AND MAPPING METHOD THEREOF

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme. 21. The method as claimed in claim s , wherein the listed constellation points comprises constellation points in one quadrant , andwherein constellation points in remaining quadrants are obtained by indicating each constellation point a which is defined in the list as a*, −a*, and −a, respectively, * indicating complex conjugation. This application is a continuation of U.S. application Ser. No. 14/714,624 filed May 18, 2015, the disclosure of which is incorporated herein by reference in its entirety.Apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to transmitting and receiving date using broadcasting, more particularly, to the design of non-uniform constellations used in a Bit Interleaved Coded Modulation (BICM) mapping bits at an output of an encoder and interleaver to complex constellations.The current broadcasting systems consistent with the Digital Video Broadcasting Second Generation Terrestrial (DVB-T2) use a Bit Interleaved and Coded Modulation (BICM) chain in order to encode bits to be transmitted. The BICM chain includes a channel encoder like a Low Density Parity Check (LDPC) encoder followed by a Bit Interleaver and a Quadrature Amplitude Modulation (QAM) mapper. The role of the QAM mapper is to map different bits output from the channel encoder and interleaved using the Bit Interleaver to QAM cells. Each cell represents a complex number having real and imaginary part. The QAM mapper groups M bits into one cell. Each cell is translated into a complex number. M, which is the ...

PARALLEL BIT INTERLEAVER

A bit interleaving method involves applying a bit permutation process to bits of a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N′/M folding sections (N′ being a subset of N selected cyclic blocks and being a multiple of M/F), each of the constellation words being associated with one of the F×N′/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word. 1. A bit interleaving method for interleaving bits of a codeword generated based on a quasi-cyclic low-density parity check coding scheme including a repeat-accumulate quasi-cyclic low-density parity check coding scheme , the bit interleaving method comprising:a bit permutation step of applying a bit permutation process to the codeword made up of N cyclic blocks each consisting of Q bits, to reorder the bits of the codeword in accordance with a bit permutation rule defining a reordering of the bits; anda dividing step of dividing the codeword after the bit permutation process into a plurality of constellation words, each of the constellation words being made up of M bits, whereinN is not a multiple of M,the bit permutation rule is a rule for applying column-row permutation that is equivalent to writing the Q bits in each of N′=N−X cyclic blocks of the N cyclic blocks in a row direction to a row among M rows of a matrix and reading in a column direction, where X is a remainder of N divided by M, andX cyclic blocks include a cyclic block in a parity section of the codeword.2. A bit interleaver for interleaving bits of a codeword generated based on a quasi-cyclic low-density parity check coding scheme including a repeat-accumulate quasi-cyclic low-density parity check coding ...

SIGNALLING CODING AND MODULATION METHOD AND DEMODULATION AND DECODING METHOD AND DEVICE

Provided are a signaling coding and modulation method and a demodulation and decoding method and device, characterized in that the method comprises the steps of: extending signaling which has been subjected to first predetermined processing according to an extension pattern table to obtain an extended codeword, and conducting predetermined coding on the extended codeword to obtain a encoded codeword; conducting parity bit permutation on a parity bit portion in the encoded codeword and then splicing the permutated parity bits to the end of information bits in the encoded codeword, to obtain a permutated encoded codeword; according to the length of the signaling, punching the permutated encoded codeword according to a predetermined punching rule to obtain a punched encoded codeword; and conducting second predetermined processing on the punched encoded codeword to obtain a tuple sequence, which is used for mapping, and then mapping the tuple sequence. 1. A signalling coding and modulation device , characterized in that the device comprises:a memory; and extend signalling which has been subjected to first predetermined processing, and conduct predetermined coding to obtain an encoded codeword;', 'conduct parity bit permutation on parity bits in the encoded codeword and then add the permutated parity bits to the end of information bits in the encoded codeword, to obtain a permutated encoded codeword;', 'puncture the permutated encoded codeword to obtain a punctured encoded codeword; and', 'conduct second predetermined processing on the punctured encoded codeword to obtain a tuple sequence, which is used for mapping, and then map the obtained tuple sequence into a signalling symbol., 'a processor, coupled with the memory and configured to2. The signalling coding and modulation device of claim 1 , characterized in that the processor is further configured to:conduct scrambling and BCH coding on the signalling, and extend an obtained BCH codeword to obtain an extended BCH ...

IMPROVED ERROR CONTROL CODING AN DECODING FOR SERIAL CONCATENATED CODES

A broadcast TV signal is a DVB-T2 based system. The DVB-T2 transmitter offsets the BCH codeword with respect to the LDPC codeword, such that, e.g., the first half of the BCH codeword is contained in one LDPC codeword and the second half of the BCH codeword is contained in the next LDPC codeword. 1. Apparatus for use in a transmitter , the apparatus comprising:a Bose-Chaudhuri-Hocquenghem multiple error correction binary block (BCH) coder for BCH coding an input data stream to provide BCH codewords;a delay element for offsetting each BCH codeword with respect to a boundary of a low density parity check (LDPC) codeword; andan LDPC coder for LDPC coding the offset BCH codewords for providing LDPC codewords such that a portion of one BCH codeword is conveyed in one LDPC codeword and the remaining portion of the BCH codeword is conveyed by the next LDPC codeword.2. The apparatus of claim 1 , wherein the transmitter transmits a DVB-T2 signal.3. The apparatus of claim 1 , wherein the transmitter transmits data formatted in super frames and further comprising:a processor for modifying signaling information conveyed by the LDPC codewords to indicate a value for a super frame index.4. The apparatus of claim 3 , wherein the signaling information is an L1 pre-signaling table.5. A method for use in a transmitter claim 3 , the method comprising:coding an input data stream to provide coded output data by using a combination of Bose-Chaudhuri-Hocquenghem multiple error correction binary block (BCH) coding and low density parity check (LDPC) coding such that a portion of one BCH codeword is conveyed in one LDPC codeword and the remaining portion of the BCH codeword is conveyed by the next LDPC codeword; andtransmitting the coded output data.6. The method of claim 5 , wherein the transmitter is a DVB-T2 transmitter.7. The method of claim 5 , wherein the coded output data is formatted for transmission in super frames and wherein the coded output data conveys signaling information to ...

TRANSMITTING APPARATUS AND MAPPING METHOD THEREOF

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme. 2. The transmitting apparatus as claimed in claim 1 , wherein the interleaver is configured to split the codeword into a plurality of bit groups and interleave the plurality of bit groups to provide the interleaved codeword.3. The transmitting apparatus as claimed in claim 1 , wherein the constellation mapper is configured to demultiplex the bits of the interleaved codeword into parallel streams to generate cells and map the cells onto the constellation points. This application is a Continuation of application Ser. No. 16/105,417 filed Aug. 20, 2018, which is a Continuation of application Ser. No. 15/705,749 filed Sep. 15, 2017, and issued as U.S. Pat. No. 10,057,005, on Aug. 21, 2018, which is a Continuation of application Ser. No. 14/716,222 filed May 19, 2015, and issued as U.S. Pat. No. 9,800,365, on Oct. 24, 2017, the disclosures of which are incorporated herein by reference in their entireties.Apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to transmitting and receiving date using broadcasting, more particularly, to the design of non-uniform constellations used in a Bit Interleaved Coded Modulation (BICM) mapping bits at an output of an encoder and interleaver to complex constellations.The current broadcasting systems consistent with the Digital Video Broadcasting Second Generation Terrestrial (DVB-T2) use a Bit Interleaved and Coded Modulation (BICM) chain in order to encode bits to be transmitted. The BICM chain includes a channel encoder like a Low Density Parity Check (LDPC) ...

Parallel bit interleaver

A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process.

TRANSMISSION METHOD, RECEPTION METHOD, TRANSMITTER, AND RECEIVER

A codeword is divided into N/(B×D) sections, a bit permutation is applied to (B×D)×Q bits of each of the sections, each Q groups of bits of each of the sections are mapped to a real-valued symbol, each Q D-dimensional vector having D real-valued symbols in Q×D real-valued symbols of each of the sections is multiplied by an orthogonal matrix with D rows and D columns, only two bits of the same quasi-cyclic block are encoded in a constellation block consisting of two D-dimensional vectors, and the two bits are mapped to the same dimension of the two D-dimensional vectors one bit by one bit. 1. A transmission method for transmitting , in a communication system employing D-dimensional rotated constellations , a codeword generated based on a quasi-cyclic low-density parity-check coding scheme including a repeat-accumulate quasi-cyclic low-density parity-check coding scheme , real-valued symbols each being obtained by encoding B bits , the codeword consisting of N quasi-cyclic blocks , the quasi-cyclic blocks each consisting of Q bits , the transmission method comprising the steps of:dividing the codeword into N/(B×D) sections each consisting of M=B×D quasi-cyclic blocks, applying a bit permutation to M×Q=(B×D)×Q bits of each of the sections, and grouping the permuted (B×D)×Q bits of each of the sections into Q groups of bits each consisting of M=(B×D) bits, the bit permutation being adapted such that the Q bits of each of the quasi-cyclic blocks are mapped to Q different groups of bits;mapping B bits of each of the groups of bits to a real-valued symbol;transforming a D-dimensional vector having D real-valued symbols generated from the groups of bits as elements into a D-dimensional rotated constellation having D transformed real-valued symbols as elements by multiplying the D-dimensional vector by an orthogonal matrix with D columns and D rows, the orthogonal matrix being a matrix for spreading values of elements in each dimension of the D-dimensional vector over at ...

MODULATOR AND MODULATION METHOD USING NON-UNIFORM 16-SYMBOL SIGNAL CONSTELLATION FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING 4/15 CODE RATE

A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 4/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis. 1. A BICM reception device , comprising:a demodulator configured to perform demodulation corresponding to 16-symbol mapping using 16 symbols of a non-uniform 16-symbol signal constellation;a bit deinterleaver configured to perform group-unit deinterleaving on interleaved values, the interleaved values generated after the demodulation; anda decoder configured to restore information bits by LDPC-decoding deinterleaved values generated based on the group-unit deinterleaving, the deinterleaved values corresponding to a LDPC codeword having a code rate of 4/15,wherein the group-unit deinterleaving is performed on a group basis, the size of the group corresponding to a parallel factor of the LDPC codeword.2. The BICM reception device of claim 1 , wherein the 16 symbols have non-uniform distances therebetween claim 1 , and comprise a first group of four symbols of a 1st quadrant claim 1 , a second group of four symbols symmetric to the four symbols of the first group with respect to an imaginary axis claim 1 , a third group of four symbols symmetric to the four symbols of the first group with respect to an origin claim 1 , and a fourth group of four symbols symmetric to the four symbols of the first group with respect to a real axis.3. The BICM reception device of claim 2 , wherein a vector corresponding to four symbols w claim 2 , w claim 2 , w claim 2 , and wof a first group is w claim 2 , a vector corresponding to four symbols w claim 2 , w claim 2 , wand wof a second group is −conj(w) (conj(w) is a function that outputs conjugate complex numbers of all elements of w) claim 2 , a vector ...

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 7/15 AND QUADRATURE PHASE SHIFT KEYING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation. 1. A bit interleaver , comprising:a first memory configured to store a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15;a processor configured to generate an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword; anda second memory configured to provide the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.2. The bit interleaver of claim 1 , wherein the parallel factor is 360 claim 1 , and the bit group includes 360 bits.5. The bit interleaver of claim 4 , wherein the permutation order corresponds to an interleaving sequence represented by the following equation:{'br': None, 'interleaving sequence={152 172 113 167 100 163 159 144 114 47 161 125 99 89 179 123 149 177 1 132 37 26 16 57 166 81 133 112 33 151 117 83 52 178 85 124 143 28 59 130 31 157 170 44 61 102 155 111 153 55 54 176 17 68 169 20 104 38 147 7 174 6 90 15 56 120 13 34 48 122 110 154 76 64 75 84 162 77 103 156 128 150 87 27 42 3 23 96 171 145 91 24 78 5 69 175 8 29 106 137 131 43 93 160 108 164 12 140 71 63 141 109 129 82 80 173 105 9 66 65 92 32 41 72 74 4 36 94 67 158 10 88 142 45 126 2 86 118 73 79 121 148 95 70 51 53 21 115 135 25 168 11 136 18 138 134 119 146 0 97 22 165 40 19 60 46 14 49 139 58 101 39 116 ...

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 4/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping. 1. A bit interleaver , comprising:a first memory configured to store a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15;a processor configured to generate an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword; anda second memory configured to provide the interleaved codeword to a modulator for 64-symbol mapping.2. The bit interleaver of claim 1 , wherein the 64-symbol mapping is a Non-Uniform Constellation (NUC) symbol mapping which corresponds to 64 constellations.3. The bit interleaver of claim 2 , wherein the parallel factor is 360 claim 2 , and the bit group includes 360 bits.6. The bit interleaver of claim 5 , wherein the permutation order corresponds to an interleaving sequence represented by the following equation:{'br': None, 'interleaving sequence={141 80 47 89 44 7 46 11 175 173 99 2 155 52 86 128 174 33 170 31 35 162 64 95 92 4 16 49 137 104 29 9 60 167 50 23 43 176 121 71 132 103 144 39 12 90 114 131 106 76 118 66 24 58 122 150 57 149 93 53 14 73 165 82 126 97 59 133 154 153 72 36 5 96 120 134 101 61 115 0 28 42 18 145 156 85 146 6 161 10 22 138 127 151 87 54 20 139 140 152 13 91 111 25 123 77 78 69 3 177 41 81 19 107 45 148 70 160 51 21 116 48 157 17 125 142 83 110 37 98 179 129 168 172 1 40 166 159 147 56 100 63 26 169 135 15 ...

APPARATUS FOR TRANSMITTING AND RECEIVING A SIGNAL AND METHOD OF TRANSMITTING AND RECEIVING A SIGNAL

The present invention relates to a method of transmitting and receiving signals and a corresponding apparatus. One aspect of the present invention relates to a method of extracting PLP from data slices. 116-. (canceled)17. A transmitter for transmitting at least one broadcast signal having Physical Layer Pipe (PLP) data , the transmitter comprising:a Bose-Chadhuri-Hocquenghem (BCH) encoder to BCH encode the PLP data;a Low Density Parity Check (LDPC) encoder to LDPC encode the BCH encoded PLP data and output Forward Error Correction Frames (FECFrames);a bit interleaver to bit interleave data in the FECFrames;a mapper to map the bit interleaved data in the FECFrames onto constellations;an outer encoder to outer encode signaling information;a zero-padding module to insert zeros into the outer encoded signaling information;an inner encoder to inner encode the zero-inserted signaling information;a parity puncturing module to puncture parity bits of the inner encoded signaling information;a zero-removing module to remove the inserted zeros from the signaling information on which the parity puncturing is performed;a time-interleaver to perform time-interleaving the mapped data based on a skip operation, wherein the time-interleaver writes the mapped data into an interleaving block and reads out the written data from the interleaving block excluding cells which are skipped according to the skip operation, wherein the time-interleaving is performed by calculating positions for cells having the mapped data and the cells to be skipped based on a row index and a column index;a frame builder to build a signal frame including preamble symbols and data symbols, wherein the preamble symbols include the zero-removed signaling information for the time interleaved data and the data symbols include the time interleaved data; anda modulator to modulate data in the signal frame by an Orthogonal Frequency Division Multiplexing (OFDM) scheme, wherein the signaling information includes ...

TRANSMISSION DEVICE, TRANSMISSION METHOD, RECEPTION DEVICE, AND RECEPTION METHOD

An FEC coder in a transmission device according to an exemplary embodiment of the present disclosure performs BCH coding and LDPC coding based on whether a code length of the LDPC coding is a 16 k mode or a 64 k mode. A mapper performs mapping in an I-Q coordinate to perform conversion into an FEC block, and outputs pieces of mapping data (cells). The mapper defines different non-uniform mapping patterns with respect to different code lengths even an identical coding rate is used by the FEC coder. This configuration improves a shaping gain for different error correction code lengths in a transmission technology in which modulation of the non-uniform mapping pattern is used. 112-. (canceled)13. A transmission method for transmitting data , comprising:performing forward error correction (FEC) coding on the data to generate an FEC frame;interleaving bits included in the FEC frame to output a bit-interleaved FEC frame;performing first mapping based on the bit-interleaved FEC frame to output first cells;generating Layer-1 signaling information including a transmission parameter;performing forward error correction (FEC) coding on the Layer-1 signaling information to output a Layer-1 FEC frame;performing second mapping based on the Layer-1 FEC frame to output second cells;generating a transmission signal based on the first cells and the second cells, whereincoding rates are provided for the FEC coding and the coding rates include a first coding rate and a second coding rate higher than the first coding rate,non-uniform constellation maps are associated with the coding rates,a first non-uniform constellation map is used when the first mapping is performed, the first non-uniform constellation map being associated with the first coding rate, anda second non-uniform constellation map is used when the second mapping is performed, the second non-uniform constellation map being associated with the second coding rate.14. The transmission method according to claim 13 , further ...

RECEIVING APPARATUS AND DE-INTERLEAVING METHOD THEREOF

A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol. 2. The broadcast signal receiving apparatus of claim 1 , wherein each of the plurality of groups comprises 360 values.3. The broadcast signal receiving apparatus of claim 1 , wherein π(j) is determined based on at least one of the code length claim 1 , a modulation method and the code rate.5. The broadcast signal transmitting apparatus of claim 4 , wherein each of the plurality of bit groups comprises 360 bits. This is a continuation of U.S. patent application Ser. No. 16/505,226, filed on Jul. 8, 2019, which is a continuation of U.S. patent application Ser. No. 16/042,628, filed on Jul. 23, 2018, issued as U.S. Pat. No. 10,382,063 on Aug. 13, 2019, which is a continuation of U.S. patent application Ser. No. 15/435,042, filed on Feb. 16, 2017, issued as U.S. Pat. No. 10,033,409 on Jul. 24, 2018, which is a continuation of U.S. patent application Ser. No. 15/130,204, filed on Apr. 15, 2016, issued as U.S. Pat. No. 9,692,454 on Jun. 27, 2017, which is a continuation of U.S. patent application Ser. no. 14/625,862, filed on Feb. 19, 2015, issued as U.S. Pat. No. 9,602,137 on Mar. 21, 2017, which claims priority from U.S. Provisional Application 61/941,676 filed on Feb. 19, 2014, U.S. Provisional Application 62/001,170 filed on May 21, 2014, and Korean Patent Application 10-2015-0000671 filed on Jan. 5, 2015. The entire disclosures of the prior applications are considered part of the ...

MODULATOR AND MODULATION METHOD USING NON-UNIFORM 16-SYMBOL SIGNAL CONSTELLATION FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING 2/15 CODE RATE

A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 2/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis. 1. A modulator using a non-uniform 16-symbol signal constellation , comprising:a memory configured to receive a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 2/15; anda processor configured to map the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.2. The modulator of claim 1 , wherein the 16 symbols have non-uniform distances therebetween claim 1 , and comprise a first group of four symbols of a 1st quadrant claim 1 , a second group of four symbols symmetric to the four symbols of the first group with respect to an imaginary axis claim 1 , a third group of four symbols symmetric to the four symbols of the first group with respect to an origin claim 1 , and a fourth group of four symbols symmetric to the four symbols of the first group with respect to a real axis.3. The modulator of claim 2 , wherein a vector corresponding to the four symbols w claim 2 , w claim 2 , w claim 2 , and wof the first group is w claim 2 , a vector corresponding to the four symbols w claim 2 , w claim 2 , wand wof the second group is -conj(w) (conj(w) is a function that outputs conjugate complex numbers of all elements of w) claim 2 , a vector corresponding to the four symbols w claim 2 , w claim 2 , wand wof the third group is -w claim 2 , and a vector corresponding to the four symbols w claim 2 , w claim 2 , wand wof the fourth group is conj(w).4. The modulator of claim 3 , wherein amplitudes of real and imaginary components of two of the four symbols of the first group are symmetric.52. The modulator of claim 4 , wherein the four ...

MODULATOR AND MODULATION METHOD USING NON-UNIFORM 16-SYMBOL SIGNAL CONSTELLATION FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING 7/15 CODE RATE

A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 7/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis. 1. A modulator using a non-uniform 16-symbol signal constellation , comprising:a memory configured to receive a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 7/15; anda processor configured to map the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.2. The modulator of claim 1 , wherein the 16 symbols have non-uniform distances therebetween claim 1 , and comprise a first group of four symbols of a 1st quadrant claim 1 , a second group of four symbols symmetric to the four symbols of the first group with respect to an imaginary axis claim 1 , a third group of four symbols symmetric to the four symbols of the first group with respect to an origin claim 1 , and a fourth group of four symbols symmetric to the four symbols of the first group with respect to a real axis.3. The modulator of claim 2 , wherein a vector corresponding to the four symbols w claim 2 , w claim 2 , w claim 2 , and wof the first group is w claim 2 , a vector corresponding to the four symbols w claim 2 , w claim 2 , wand wof the second group is −conj(w) (conj(w) is a function that outputs conjugate complex numbers of all elements of w) claim 2 , a vector corresponding to the four symbols w claim 2 , w claim 2 , wand wof the third group is −w claim 2 , and a vector corresponding to the four symbols w claim 2 , w claim 2 , wand wof the fourth group is conj(w).4. The modulator of claim 3 , wherein amplitudes of real and imaginary components of two of the four symbols of the first group are symmetric.5. The modulator of claim 4 , wherein the four ...

MODULATOR AND MODULATION METHOD USING NON-UNIFORM 16-SYMBOL SIGNAL CONSTELLATION FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING 3/15 CODE RATE

A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 3/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis. 1. A modulator using a non-uniform 16-symbol signal constellation , comprising:a memory configured to receive a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 3/15; anda processor configured to map the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.2. The modulator of claim 1 , wherein the 16 symbols have non-uniform distances therebetween claim 1 , and comprise a first group of four symbols of a 1st quadrant claim 1 , a second group of four symbols symmetric to the four symbols of the first group with respect to an imaginary axis claim 1 , a third group of four symbols symmetric to the four symbols of the first group with respect to an origin claim 1 , and a fourth group of four symbols symmetric to the four symbols of the first group with respect to a real axis.3. The modulator of claim 2 , wherein a vector corresponding to the four symbols w claim 2 , w claim 2 , w claim 2 , and wof the first group is w claim 2 , a vector corresponding to the four symbols w claim 2 , w claim 2 , wand wof the second group is −conj(w) (conj(w) is a function that outputs conjugate complex numbers of all elements of w) claim 2 , a vector corresponding to the four symbols w claim 2 , w claim 2 , wand wof the third group is −w claim 2 , and a vector corresponding to the four symbols w claim 2 , w claim 2 , wand wof the fourth group is conj(w).4. The modulator of claim 3 , wherein amplitudes of real and imaginary components of two of the four symbols of the first group are symmetric.5. The modulator of claim 4 , wherein the four ...

MODULATOR AND MODULATION METHOD USING NON-UNIFORM 16-SYMBOL SIGNAL CONSTELLATION FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING 4/15 CODE RATE

A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 4/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis. 1. A modulator using a non-uniform 16-symbol signal constellation , comprising:a memory configured to receive a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 4/15; anda processor configured to map the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.2. The modulator of claim 1 , wherein the 16 symbols have non-uniform distances therebetween claim 1 , and comprise a first group of four symbols of a 1st quadrant claim 1 , a second group of four symbols symmetric to the four symbols of the first group with respect to an imaginary axis claim 1 , a third group of four symbols symmetric to the four symbols of the first group with respect to an origin claim 1 , and a fourth group of four symbols symmetric to the four symbols of the first group with respect to a real axis.3. The modulator of claim 2 , wherein a vector corresponding to the four symbols w claim 2 , w claim 2 , w claim 2 , and wof the first group is w claim 2 , a vector corresponding to the four symbols w claim 2 , w claim 2 , wand wof the second group is conj(w) (conj(w) is a function that outputs conjugate complex numbers of all elements of w) claim 2 , a vector corresponding to the four symbols w claim 2 , w claim 2 , wand wof the third group is -w claim 2 , and a vector corresponding to the four symbols w claim 2 , w claim 2 , wand wof the fourth group is conj(w).4. The modulator of claim 3 , wherein amplitudes of real and imaginary components of two of the four symbols of the first group are symmetric.5. The modulator of claim 4 , wherein the four ...

Transmitter apparatus and interleaving method thereof

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

Receiver for receiving data in a broadcast system using redundancy data

A receiver for receiving data in a broadcast system includes a broadcast receiver that receives, via the broadcast system, a receiver input data stream including plural channel symbols represented by constellation points in a constellation diagram. A demodulator demodulates the channel symbols into codewords and a decoder decodes the codewords into output data words. A broadband receiver obtains redundancy data via a broadband system, the redundancy data for a channel symbol including one or more least robust bits of the channel symbol or a constellation subset identifier indicating a subset of constellation points including the constellation point representing the channel symbol. The demodulator and/or the decoder is configured to use the redundancy data to demodulate the respective channel symbol and to decode the respective codeword, respectively.

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

The present technology relates to a data processing device and a data processing method that make it possible to ensure good communication quality in a data transmission using LDPC codes. In group-wise interleave, an LDPC code whose code length is 16200 bits and code rate is 10/15, 11/15, 12/15, or 13/15 is interleaved in a 360-bit group unit. In group-wise deinterleave, a sequence of the LDPC code after group-wise interleave obtained from data transmitted from a transmitting device to the original sequence. The present technology can be applied, for example, to data transmission or the like using the LDPC codes. 1. A data processing device , comprising:a group-wise interleave unit of performing group-wise interleave of interleaving in a 360-bit group unit an LDPC code whose code length is 16200 bits and code rate is 10/15, 11/15, 12/15 or 13/15,the (i+1)th bit group from the beginning of the LDPC code of the 16200 bits being as a bit group i, and in the group-wise interleave, a sequence of bit group 0 to 44 of the 16200 bits of the LDPC code being interleaved into the following sequence of the bit group:15, 25, 9, 27, 5, 38, 13, 10, 19, 16, 28, 1, 36, 0, 11, 17, 32, 35, 7, 26, 14, 21, 6, 4, 23, 22, 3, 18, 20, 24, 30, 12, 37, 2, 40, 8, 33, 29, 31, 34, 41, 42, 43, 44, 39.2. The data processing device according to claim 1 , further comprising:a mapping unit of mapping the LDPC code onto any of 1024 signal points defined by a modulation scheme in a 10 bits unit.3. The data processing device claim 1 , according to claim 1 , further comprising:an encoder, which performs LDPC encoding based on a parity check matrix of an LDPC code whose code length is 16200 bits and code rate is 10/15,the LDPC code including information bits and parity bits,the parity check matrix including an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits,the information matrix part being represented by a parity check matrix initial ...

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

The present technology relates to a data processing device and a data processing method that make it possible to ensure good communication quality in a data transmission using LDPC codes. In group-wise interleave, an LDPC code whose code length is 64800 bits and code rate is 10/15, 11/15, 12/15, or 13/15 is interleaved in a 360-bit group unit. In group-wise deinterleave, a sequence of the LDPC code after group-wise interleave obtained from data transmitted from a transmitting device to the original sequence. The present technology can be applied, for example, to data transmission or the like using the LDPC codes. 1. A data processing device , comprising:a group-wise interleave unit of performing group-wise interleave of interleaving in a 360-bit group unit an LDPC code, whose code length is 64800 bits and code rate is 10/15, 11/15, 12/13 or 13/15,{'b': 0', '179, 'the (i+1)th bit group from the beginning of the LDPC code of the 64800 bits being as a bit group i, and in the group-wise interleave, a sequence of bit group to of the 64800 bits of the LDPC code being interleaved into the following sequence of the bit group90, 64, 100, 166, 105, 61, 29, 56, 66, 40, 52, 21, 23, 69, 31, 34, 10, 136, 94, 4, 123, 39, 72, 29, 106, 16, 14, 134, 152, 142, 164, 37 67, 17, 48, 99 135, 54, 2 0, 146, 115, 20, 76, 111, 83, 145, 177, 156, 174, 28, 25, 139, 33, 128, 1, 179, 45, 153, 38, 62, 110, 151, 32, 70, 101, 143, 77,130, 50, 84, 127, 103, 109, 5, 63, 92, 124, 87, 160, 108, 26, 60, 98, 172, 102, 88, 170, 6, 13, 171, 97, 95, 91, 81, 137, 119 148, 86, 35, 30, 140, 65, 82, 49, 46, 133, 71, 42, 43, 175, 141, 55, 93, 79, 107, 173, 78, 176, 96, 73, 57, 36, 44, 154, 19, 11, 165, 58, 18, 53, 126, 138, 117, 51, 113, 114, 162, 178, 3, 150, 8, 22, 131, 157, 118, 116, 85, 41, 27, 80, 12, 112, 144, 68, 167, 59, 75, 122, 132, 149, 24, 120, 47, 104, 147, 121, 74, 155, 125, 15, 7, 89, 161, 163, 9, 159, 168, 169, 158.2. The data processing device according to claim 1 , further comprisinga mapping ...

TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol. 2. The transmitting apparatus of claim 1 , wherein each of the plurality of bit groups comprises 360 bits.3. The transmitting apparatus of claim 1 , wherein the interleaver comprises:a parity interleaver configured to interleave the parity bits;a group-wise interleaver configured to interleave the plurality of bit groups constituting the parity interleaved LDPC codeword; anda block interleaver configured to interleave the group-wise interleaved LDPC codeword.4. The transmitting apparatus of claim 1 , wherein π(j) is determined based on at least one of a length of the LDPC codeword claim 1 , a modulation method and a code rate.5. The transmitting apparatus of claim 3 , wherein the block interleaver is configured to interleave the group-wise interleaved LDPC codeword by writing bits constituting the plurality of bit groups in a plurality of columns of the block interleaver in a column wise claim 3 , and reading each row of the plurality of columns in which the bits constituting the plurality of bit groups written in a row wise.6. The transmitting apparatus of claim 5 , wherein claim 5 , each column of the block interleaver is composed a first part and a second part claim 5 , the block interleaver is configured to write bits constituting at least some bit groups among the plurality of bits groups in the first part serially claim 5 , and write bits constituting the bit groups remaining of the plurality of bit groups ...

TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol. 2. The transmitting apparatus of claim 1 , wherein each of the plurality of bit groups comprises 360 bits.3. The transmitting apparatus of claim 1 , wherein the interleaver comprises:a parity interleaver configured to interleave the parity bits;a group-wise interleaver configured to interleave the plurality of bit groups constituting the parity interleaved LDPC codeword; anda block interleaver configured to interleave the group-wise interleaved LDPC codeword.4. The transmitting apparatus of claim 1 , wherein π(j) is determined based on at least one of a length of the LDPC codeword claim 1 , a modulation method and a code rate.5. The transmitting apparatus of claim 3 , wherein the block interleaver is configured to interleave the group-wise interleaved LDPC codeword by writing bits constituting the plurality of bit groups in a plurality of columns of the block interleaver in a column wise claim 3 , and reading each row of the plurality of columns in which the bits constituting the plurality of bit groups written in a row wise.6. The transmitting apparatus of claim 5 , wherein claim 5 , each column of the block interleaver is composed a first part and a second part claim 5 , the block interleaver is configured to write bits constituting at least some bit groups among the plurality of bits groups in the first part serially claim 5 , and write bits constituting the bit groups remaining of the plurality of bit groups ...

PARALLEL BIT INTERLEAVER

A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process. 1. A bit interleaving method for interleaving bits of a codeword generated based on a low-density parity check coding scheme , a parity-check matrix of the low-density parity check coding scheme having a quasi-cyclic structure , the bit interleaving method comprising:a bit permutation step of applying a bit permutation process to a codeword made up of N bit groups each consisting of Q bits, to reorder the bits of the codeword in accordance with a bit permutation rule defining a reordering of the bits; anda dividing step of dividing the codeword after the bit permutation process into a plurality of constellation words, each of the constellation words being made up of M bits, whereinN is not a multiple of M,the bit permutation rule includes a first rule and a second rule, the first rule being applied to N′=N−X bit groups, the second rule being applied to X bit groups, where X is a remainder of N divided by M,the reordering of the first rule is equivalent to a column-row permutation process including a writing process and a reading process, the bits of the N′ bit groups being written into a matrix row-by-row during the writing process, the written bits being read out from the matrix column-by-column during the reading process, the matrix having M rows, the Q bits included in one bit group being written into a same row sequentially, the ...

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 3/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping. 1. A bit-interleaved coded modulation (BICM) reception device , comprising:a demodulator configured to perform demodulation corresponding to 64-symbol mapping;a bit deinterleaver configured to perform group-unit deinterleaving on interleaved values, the interleaved values generated after the demodulation; anda decoder configured to restore information bits by LDPC-decoding deinterleaved values generated based on the group-unit deinterleaving, the deinterleaved values corresponding to a LDPC codeword having a length of 64800 and a code rate of 3/15,wherein the group-unit deinterleaving is performed on a group basis, the size of the group corresponding to a parallel factor of the LDPC codeword.2. The BICM reception device of claim 1 , wherein the group-unit deinterleaving corresponds to interleaving performed by using permutation order claim 1 , and {'br': None, 'interleaving sequence={74 72 104 62 122 35 130 0 95 150 139 151 133 109 31 59 18 148 9 105 57 132 102 100 115 101 7 21 141 30 8 1 93 92 163 108 52 159 24 89 117 88 178 113 98 179 144 156 54 164 12 63 39 22 25 137 13 41 44 80 87 111 145 23 85 166 83 55 154 20 84 58 26 126 170 103 11 33 172 155 116 169 142 70 161 47 3 162 77 19 28 97 124 6 168 107 60 76 143 121 42 157 65 43 173 56 171 90 131 119 94 5 68 138 149 73 67 53 61 4 86 99 75 36 15 48 177 167 174 51 176 81 120 158 123 34 49 128 10 134 147 96 160 50 146 16 38 78 91 152 46 ...

APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING DATA IN COMMUNICATION SYSTEM

Apparatuses for transmitting and receiving a signal in a communication system are provided. An apparatus of a receive device includes a receiver configured to receive, from a transmit device, a signal comprising remaining bits of parity bits after puncturing, wherein the parity bits are obtained by adding at least one shortened bit to information bits to obtain input bits for an encoding, if a number of the information bits is less than a number of the input bits for the encoding; and a hardware processor configured to determine a number of puncture bits for the parity bits, generate an output signal by adding at least one value corresponding to the number of the puncture bits to the signal, and decode the output signal. 1. An apparatus of a receive device , the apparatus comprising:a receiver configured to receive, from a transmit device, a signal comprising remaining bits of parity bits after puncturing, wherein the parity bits are obtained by adding at least one shortened bit to information bits to obtain input bits for an encoding, if a number of the information bits is less than a number of the input bits for the encoding; and determine a number of puncture bits for the parity bits,', 'generate an output signal by adding at least one value corresponding to the number of the puncture bits to the signal, and', 'decode the output signal,, 'a hardware processor configured towherein the number of puncture bits is determined by adjusting a number of temporary puncture bits based on a modulation order of the signal,wherein the temporary puncture bits is determined by using a first parameter and a second parameter,wherein the first parameter and the second parameter are determined based on a type of the signal, the type of the signal corresponding to a protection level of the signal,wherein the first parameter is related to a ratio of a number of bits to be punctured to a number of bits to be shortened, and is multiplied by a number of the at least one bit shortened to ...

BIT INTERLEAVER AND BIT DE-INTERLEAVER

A method for bit interleaving is provided. A method includes mapping a set of bits ≡{a: k=0, 1, 2, . . . N−1} to an array ={B: i=0, 1, 2, . . . , M−1; j=0, 1, 2, . . . , N−1} such that bit amaps to B, wherein mod denotes the modulo operator, └ ┘ denotes the floor operator, and M and N are constants, performing at least one of—a first permutation operation comprising permuting two or more bits within each of one or more first groups of bits, wherein each first group of bits is defined by ={B: i=0, 1, 2, . . . , M−1; p∈{0, 1, 2, . . . , N−1}} and—a second permutation operation comprising permuting two or more bits within each of one or more second groups of bits, wherein each second group of bits is defined by ={B: j=0, 1, 2, . . . , N−1; q∈ {0, 1, 2, . . . , M−1}} and de-mapping bits from to obtain an interleaved set of bits ≡{b: k=0, 1, 2, N−1} such that bit B,is de-mapped to bit b. 1. A method for bit interleaving , the method comprising:{'u': [{'@style': 'single', 'a'}, {'@style': 'double', 'B'}], 'sub': k', 'post', 'i,j', 'k', 'k mod M, └k/M┘, 'mapping a set of bits ≡{a: k=0, 1, 2, . . . N−1} to an array ={B: i=0, 1, 2, . . . , M−1; j=0, 1, 2, . . . , N−1} such that bit amaps to B, wherein mod denotes the modulo operator, └ ┘ denotes the floor operator, and M and N are constants;'} [{'u': {'@style': 'single', 'G'}, 'sup': '(1)', 'sub': p', 'i,p, 'a first permutation operation comprising permuting two or more bits within each of one or more first groups of bits, wherein each first group of bits is defined by ={B=i=0, 1, 2, . . . , M−1; p∈ {0, 1, 2, . . . , N−1}}; and'}, {'u': {'@style': 'single', 'G'}, 'sup': '(2)', 'sub': q', 'q,j, 'a second permutation operation comprising permuting two or more bits within each of one or more second groups of bits, wherein each second group of bits is defined by ={B: j=0, 1, 2, . . . , N−1; q∈ {0, 1, 2, . . . , M−1} }; and'}], 'performing at least one of{'u': [{'@style': 'double', 'B'}, {'@style': 'single', 'b'}], 'sub': k', ' ...

Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 2/15 and 256-symbol mapping, and bit interleaving method using same

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

TRANSMITTING APPARATUS AND SIGNAL PROCESSING METHOD THEREOF

A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method. 1. A receiving apparatus comprising:a receiver configured to receive a signal from a transmitting apparatus;a demodulator configured to demodulate the signal to generate values;a deinterleaver configured to deinterleave the values using a plurality of columns; anda decoder configured to decode the deinterleaved values based on a low density parity check (LDPC) code,wherein each of the plurality of columns comprises a first part and a second part,wherein some values of the values are deinterleaved in the first part and at least one remaining value is deinterleaved in the second part, andwherein the some values and the at least one remaining value are written in a row direction and are read out in a column direction.2. The apparatus as claimed in claim 1 , wherein the deinterleaver is configured to split the deinterleaved values into a plurality of values and deinterleave the deinterleaved plurality of values.3. The apparatus as claimed in claim 2 , wherein each of the plurality of groups comprises 360 values.4. A receiving method comprising:receiving a signal from a transmitting apparatus;demodulating the signal to generate values;deinterleaving the values using a plurality of columns; anddecoding the deinterleaved values based on a low density parity check (LDPC) code,wherein each of the plurality of ...

APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS

The present invention provides a method of transmitting broadcast signals. The method includes, encoding, by an encoder, PLP (Physical Layer Pipe) data; time interleaving, by a time interleaver, the encoded PLP data; frame mapping, by a framer, the time interleaved PLP data onto at least one signal frames; frequency interleaving, by a frequency interleaver, data in the at least one signal frames; and waveform modulating, by a waveform module, the frequency interleaved data in the at least one signal frame and transmitting, by the waveform module, broadcast signals having the modulated data, wherein the frequency interleaving is conducted according to an interleaving mode, wherein the interleaving mode is determined based on a FFT (Fast Fourier Transform) size. 128-. (canceled)29. A frequency de-interleaver used in a broadcast signal receiver , the frequency de-interleaver comprising: a signal frame including a number of OFDM (Orthogonal Frequency Division Multiplexing) symbols,', 'the number of OFDM symbols is an even number,', 'the number of OFDM symbols include a symbol carrying physical layer signalling data and one or more symbols carrying PLP data,', 'the deinterleaving sequence of which addresses are within a range of a number of cells in an OFDM symbol is generated based on a toggle bit and a symbol offset sequence,', 'the symbol offset sequence is generated for every OFDM symbol pair including two consecutive OFDM symbols,', 'the symbol offset sequence is reset on the symbol carrying physical layer signalling data that is followed by the one or more symbols carrying the PLP data; and, 'a memory index generator configured to generate a de-interleaving sequence that is used to de-interleave data in one or more signal frames, whereina memory.30. The frequency de-interleaver of claim 29 ,wherein the frequency de-interleaver operates on an OFDM symbol, the frequency de-interleaver is configured to write a first OFDM symbol of an OFDM symbol pair on the memory and ...

Apparatus for transmitting broadcast signal, apparatus for receiving broadcast signal, and method therefor

A transmitting device is disclosed. The transmitting device includes a controller that groups a plurality of transmitters into a plurality of groups including three or more groups and a plurality of code units that generate different output streams based on a data stream with respect to the plurality of groups. The controller delivers the output streams to the plurality of groups.

PARALLEL BIT INTERLEAVER

A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each made up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section. 1. A transmitting method comprising:generating a codeword according to a low-density parity check coding scheme such that the codeword includes N bit groups each consisting of Q bits, a parity-check matrix of the low-density parity check coding scheme having a quasi-cyclic structure;reordering the N bit groups;reordering bits of the codeword after the N bit groups are reordered;dividing the codeword into constellation words, the constellation words each consisting of M bits after the bits of the codeword are reordered;generating a transmission signal based on the constellation words after the codeword is divided; andtransmitting the transmission signal through an antenna, whereinN is a multiple of M, andthe bits of the codeword are written into an M by Q matrix row-by-row and the written bits of the codeword are read from the M by Q matrix column-by-column in order to reorder the bits of the codeword.2. The transmission method according to claim 1 , wherein the bits of the codeword are written into the M by Q matrix from a topmost row and the written bits of the codeword are read from the M by Q matrix from a leftmost column.3. The transmission method according to claim 1 , wherein the N bit groups are reordered according to a reordering table.4. A transmitter comprising:generating circuitry generating a codeword according to a low-density parity check coding scheme such that the codeword includes N bit groups ...

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD FOR IMPROVING RESISTANCE TO ERROR OF DATA

A data processing device and a data processing method capable of improving resistance to error of data. An LDPC encoder encodes by an LDPC code whose code length is 16200 bits and code rate is 4/15, 7/15, or 8/15. A parity check matrix of the LDPC code is composed by arrangement of an element of an information matrix determined by a parity check matrix initial value table indicating a position of the element of the information matrix corresponding to an information length corresponding to the code length and the code rate for each 360 columns of the parity check matrix with a period of 360 columns in a column direction. The parity check matrix initial value table is for digital broadcasting for a mobile terminal, for example. This technology may be applied to a case in which LDPC encoding and LDPC decoding are performed. 4. The data processing device according to claim 1 , further comprising:a parity interleaver, which interleaves only the parity bit of the LDPC code.5. The data processing device according to claim 1 , further comprising:a column twist interleaver, which performs column twist interleave by recording a code bit of the LDPC code while shifting in a column direction.6. The data processing device according to claim 1 , whereina 2+360×(i−1)-th column of the parity check matrix is a column obtained by cyclic shift of a 1+360×(i−1)-th column indicated by the parity check matrix initial value table downward by q=M/360 (i represents the number of rows of the parity check matrix initial table and M represents a parity length).7. The data processing device according to claim 6 , whereinq is set to 33.8. The data processing device according to claim 1 , whereinas for a 1+360×(i−1)-th column of the parity check matrix,an i-th row of the parity check matrix initial value table indicates a row number of an element 1 of the 1+360×(i−1)-th column of the parity check matrix,as for each column from a 2+360×(i−1)-th column to a 360×i-th column other than the 1+360×(i−1 ...

PARITY INTERLEAVING APPARATUS FOR ENCODING VARIABLE-LENGTH SIGNALING INFORMATION AND PARITY INTERLEAVING METHOD USING SAME

A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit. 1. A method of transmitting signaling information , comprising:segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups;generating a parity bit string for parity puncturing by group-wise interleaving the groups using an order of group-wise interleaving;generating parity punctured parity bits by performing the parity puncturing using the parity bit string;performing quadrature phase shift keying (QPSK) modulation for generating a transmission signal by using an input signal corresponding to the parity punctured parity bits; andtransmitting the transmission signal over a physical channel to a reception device.2. The method of claim 1 , wherein the LDPC codeword includes zero-padded variable length signaling information as information bits.3. The method of claim 1 , wherein the parity bits correspond to 12960 bits claim 1 , the groups correspond to 36 groups each of which is composed of 360 bits.4. The method of claim 2 , wherein the LDPC codeword includes an LDPC information bit string generated by filling all bits of at least one of information bit groups selected by using a shortening pattern order with 0.5. The method of claim 3 , wherein the order of group-wise interleaving corresponds to a sequence of 36 numbers which indicate the order of the 36 groups.6. The method of claim 5 , wherein the order of group-wise interleaving ...

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 2/15 AND 16-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping. 1. A broadcast signal reception method , comprising:performing, by a demodulator, demodulation corresponding to 16-symbol mapping;performing, by a deinterleaver, group-unit deinterleaving on interleaved values, the interleaved values generated after the demodulation; andrestoring, by a decoder, information bits by LDPC-decoding deinterleaved values generated based on the group-unit deinterleaving, the deinterleaved values corresponding to a LDPC codeword having a length of 64800 and a code rate of 2/15,wherein the group-unit deinterleaving is performed on a group basis, the size of the group corresponding to a parallel factor of the LDPC codeword.2. The broadcast signal reception method of claim 1 , wherein the group-unit deinterleaving corresponds to a reverse process of a interleaving performed by using permutation order claim 1 , and {'br': None, 'interleaving sequence={5 58 29 154 125 34 0 169 80 59 13 42 77 167 32 87 24 92 124 143 114 120 166 138 64 136 149 57 18 101 119 35 33 113 75 108 104 3 27 39 172 159 129 62 146 142 19 147 111 70 74 79 10 132 1 161 155 90 15 133 47 112 84 28 160 117 150 49 7 81 44 63 118 4 158 148 82 69 36 162 86 71 22 26 61 40 126 170 177 23 91 68 56 110 21 93 107 85 20 128 109 66 83 12 179 141 97 78 157 72 130 99 165 45 11 152 168 14 16 2 137 140 121 173 50 55 94 144 73 51 98 174 178 17 100 9 122 54 38 156 131 127 164 102 116 176 30 37 139 95 43 135 53 89 ...

Transmitting apparatus and mapping method thereof

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme.