КОММУТАЦИОННАЯ СИСТЕМА ДЛЯ ВЫПОЛНЕНИЯ АСИНХРОННОГО РЕЖИМА ПЕРЕДАЧИ И СПОСОБ КОММУТАЦИИ ЯЧЕЕК В НЕЙ

Изобретение относится к коммутационной системе для выполнения асинхронного режима передачи и способу коммутации ячеек в ней. Технический результат заключается в обеспечении коммутации асинхронного режима передачи при комплексном представлении данных. Система включает в себя входной буфер, входную коммутационную схему, выполняющую функцию выборки и суммирования, коммутационную схему копирования, выполняющую функцию выборки и суммирования, коммутационную схему обратной связи, принимающую отправленные обратно ячейки и сохраняющую их до следующего цикла ячеек, таблицу маршрутизации для запоминания данных для преобразования и замены данных для маршрутизации ячеек, контроллер маршрутизации и обратной связи, маршрутизирующий-управляющий входными ячейками и отправленными обратно ячейками согласно таблице маршрутизации, коммутационные схемы маршрутизации, разделитель ячеек, разделяющий ячейки, маршрутизированные-выведенные в число маршрутизирующих схем, и передающий их к коммутационным схемам маршрутизации ...

СПОСОБ ДЛЯ СИНХРОНИЗАЦИИ ПЕРЕДАЧИ ДАННЫХ С ПОСТОЯННОЙ ЦИФРОВОЙ СКОРОСТЬЮ В СЕТЯХ С АСИНХРОННЫМ РЕЖИМОМ ПЕРЕДАЧИ И УСТРОЙСТВО ДЛЯ ВЫПОЛНЕНИЯ СПОСОБА

SWITCHING EQUIPMENT AND MEDIATION PROCEDURE

BUFFERSYSTEM WITH OVERLOAD REGULATION WITH CONNECTINGWISE TRAFFIC ADMINISTRATION

PROCEDURE AND DEVICE FOR STORING PACKAGES WITH A BORDER INDICATOR

AT SWITCHING CENTER

OPTICAL CROSSPOINT SWITCH.

PROCEDURE AND SWITCHING CONFIGURATION FOR THE SWITCHING OF MESSAGE PACKAGES.

MODULAR EXPANDABLE DIGITAL SINGLE-STEP OUPLE NET IN AT (ASYNCHRONUS TRANSFER MODE) TECHNOLOGY FOR A FAST PACKAGE-OBTAINED INFORMATION TRANSFER.

AT TRANSMISSION SYSTEM FOR THE STATISTIC MULTIPLEX FORMATION OF CELLS

ASYNCHRONOUS TIME MULTIPLEX NETWORK.

MEDIATION PROCEDURE AND - DEVICE FOR A SATELLITE COMMUNICATION SYSTEM

NETWORK FUNCTION MODULE FOR A CABLE MODEM CONCLUSION SYSTEM

PROCEDURE AND DEVICE FOR THE TRAFFIC FLOW PRICE INCREASE AROUND THE SERVICE QUALITY IN A COMMUNICATIONS NETWORK WORK FOR FULFILLING

DEVICE FOR AT OF CONNECTING PERMISSION CONTROL OF DBR CONNECTIONS

PRIORITY SELECTION MEANS FOR DATA TRANSMISSION DEVICE

VIRTUAL MULTIPLE TRANSMISSION CIRCUIT SWITCHING USING CELL RECYCLING

PROCEDURE FOR THE ADMINISTRATION OF THE SOUND SIGNAL CODING AND - RENDITION IN AN ASYNCHRONOUS TRANSMISSION SYSTEM

PROCEDURE AND SYSTEM FOR SENDING AND/OR RECEIVING FROM INFORMATION BETWEEN NETWORK ELEMENTS

PROCEDURE FOR the OPTIMIZED ONE �BERTRAGEN BY AT CELLS �BER CONNECTING SECTIONS

Link buffer sharing method and apparatus

Serial control and data interconnect system using a crossbar switch and a multipoint topology

Linked-list structures for multiple levels of control in an atm switch

Expandable data width sam for a multiport ram

An asynchronous transfer mode switch

ATM switching network

Terabit per second ATM packet switch having out-of-band control with multicasting

Method and equipment for prioritizing traffic in an atm network

Communication links for transmission of data in fixed size packets

PACKET SWITCHING NETWORK

PACKET SWITCHING NETWORK A packet switching network that accommodates the appearance of multiple occurrences of packets addressed to the same destination are accommodated. The network includes a recirculating delay block within the switch, and an expander that includes a modest number of multiple appearances of the same address, followed by memories that accept the packets delivered at those multiple appearances, store the packets, and output the stored packets to the user, one at a time, in accordance with a set priority scheme.

ARBITRATION METHOD AND APPARATUS FOR A NON-BLOCKING SWITCH

A switching method and apparatus operates as a work conserving network device. An arbiter using an arbitration algorithm controls a switch fabric interconnecting input ports and output ports. To switch cells, a virtual output queue of an input port is selected that corresponds to an output port with a lowest occupancy rating and a request is sent to this output port. In a greedy version of the algorithm, input ports may send requests to the lowest occupied output port for which they have a cell. In a non-greedy version, requests may only be sent if that input port has a cell for the lowest occupied output port in the entire network device. An output port that receives one or more requests from input ports uses an input port selection algorithm to select an input port from which to receive a packet. After as many input and output ports are matched as is possible in a phase, the packets for those matched ports are transferred across the switch. The switch fabric operates with a speedup of ...

DYNAMIC JITTER BUFFERING FOR VOICE-OVER-IP AND OTHER PACKET-BASED COMMUNICATION SYSTEMS

A variable-size jitter buffer is used to store information associated with a voice signal, facsimile signal or other received signal in a receiver of a packet- based communication system. The receiver determines an appropriate adjustment time for making an adjustment to the size of the buffer based at least in part on a result of a signal detection operation performed on the received signal. For example, in the case of a received voice signal, the determined adjustment time may be a time at which a state machine associated with a speech detector is in a "no speech" state. If the actual buffer size at the determined adjustment time is not within a designated range of a target computed at least in part based on one or more jitter measurements, the buffer size is adjusted at the determined adjustment time, e.g., by an amount representative of the difference between the actual buffer size and the target. The invention provides low-delay and low-complexity jitter buffering particularly well ...

SYSTEM AND METHOD FOR SWITCHING PACKETS IN A NETWORK

A switching node for transferring packets, each including a destination address, in a network includes a plurality of input port modules, a plurality of output port modules and a switching fabric, including a packet meta-data processor and a packet switch. Each input port module is connected to a communication link for receiving packets thereover, and each output port module is connected to a communication link for transmitting packets thereover. Each input port module, upon receiving a packet, buffers the packet and generates a meta-data packet therefore identifying the output port module that is to transmit the packet and packet identifier information, and provides it to the packet meta-data processor. The packet meta-data processor receives the meta-data packets generated by all of the input port modules and operational status information from all of the output port modules and for each output port module, processes the meta-data packets received from all of the input port modules in ...

METHOD AND APPARATUS FOR SYNCHRONIZING DEVICES IN ATM BASED BASE STATION SUBSYSTEMS USING SPECIAL VIRTUAL CHANNEL CONNECTIONS

... ▓▓▓A method and apparatus for synchronizing devices in ATM based base station ▓subsystems using special ATM virtual channel connections is disclosed. The ▓invention provides a high, constant bit rate connection to the BTSs via the ▓ATM cloud that is primarily for synchronization. The method in accordance with ▓the invention includes establishing a high, constant bit rate virtual channel ▓connection to each of the plurality of remote devices from the transmitting ▓device and broadcasting data cells to the plurality of remote devices for ▓processing by the plurality of remote devices to deduce a clock frequency for ▓synchronization thereto. The remote devices comprise base transceiver stations ▓(BTS). The transmitting device (1210) is an interworking function device, ▓which may be a transcoder. The method enables clock synchronization by ▓providing a synchronous residual timestamp, through analysis to deduce the ▓arrival time of the data cells, and by determining an available capacity of ...

APPARATUS AND METHOD FOR CONNECTING INTER-SRM HIGHWAYS

A method for connecting inter-SRM highways, is used in a MSSR formed by arraying a plurality of rows pursuant to a broadband ISDN system. This method inserts a connection module between SRMs in each SRM row, has a plurality of horizontal highways connect an SRM on the input side with an SRM on the output side in each SRM row, provides a plurality of vertical highways crossing the plurality of horizontal highways and has a plurality of switches, provided at respective crossing points between horizontal highways and vertical highways, arbitrarily switch the connection of the horizontal highways to the vertical highway.

SELF-ROUTING MULTIPATH NETWORK FOR SWITCHING ASYNCHRONOUS TIME-DIVISION MULTIPLEX CELLS

Réseau de commutation à auto-acheminement et trajets multiples pour la commutation de cellules à multiplexage temporel asynchrone comprenant des ports d'entrée (pi1,pi64...), des ports de sortie (po1,po64...), des commutateurs (TSi1, TSi16...) arrangés en plusieurs étages de commutateurs interconnectés, chaque commutateur ayant des entrées et des sorties et étant agencé pour transférer une cellule reçue sur l'une de ses entrées, sur une ou plusieurs de ses sorties, en fonction de données d'acheminement associées à ladite cellule. Chaque commutateur élémentaire d'un étage au moins du réseau possède au moins trois sorties, arrangées en groupes de sorties d'une ou plusieurs sorties déterminées. En fonction de données d'acheminement associées à une cellule reçue sur l'une quelconque de ses entrées, le commutateur (TSi1, TSi16... ) est agencé pour identifier un ensemble d'un ou plusieurs desdits groupes de sorties et pour transférer ladite cellule reçue, sur une sortie de chaque groupe de sorties ...

Cell Switching System Node Resequencing Device

Data Queueing Apparatus and ATM Cell Switch Based on Shifting and Searching

ATM SWITCH AND CONTROL METHOD THEREOF

SERVING CONSTANT BIT RATE TRAFFIC IN A BROADBAND DATA SWITCH

This invention relates to a method and apparatus for transmitting constant and variable bit rate traffic in a broadband ISDN switch. Data from constant bit rate sources such as television cameras is entered into a group of queues. Each member of the group for queuing data of a different band of bit rates. Data is transmitted from these queues with highest priority from the queue storing data of the highest band of bit rates. If the longest enqueued entity of data in one of the other queues has been enqueued for more than a prespecified period, its priority is increased. Analytic studies have shown that use of three queues for constant bit rate traffic and a fourth queue for variable bit rate traffic allows a high occupancy in the output channels to be maintained with a negligible number of data entities excessively delayed.

METHOD AND APPARATUS FOR PERFORMING PRIORITY CONTROL FOR CELLS IN OUTPUT BUFFER TYPE ATM SWITCH

There is provided a method of performing priority control for cells in an output buffer type ATM switch including a switching unit, having a plurality of input ports and a plurality of output ports, for switching/outputting the cells input from the input ports to the output ports, and a plurality of output buffer units, connected to the output ports of the switching unit, for temporarily storing the cells output from the output ports to perform output control of the cells. A loss quality class and a delay quality class are added to each cell. A plurality of logical queues for temporarily storing the cells are vertically set in a buffer memory in accordance with the delay quality classes and routing information. The input cells are selectively written in the logical queues on the basis of the delay quality classes and the routing information added to the cells. A transition process is performed for all the logical queues to change the delay quality class of each of the logical queues into ...

CROSS-POINT TYPE SWITCH USING COMMON MEMORIES

LOW DELAY OR LOW LOSS SWITCH FOR ATM

... 2084303 9219060 PCTABS00017 An ATM switching arrangement is disclosed in which two types of cells are distinguished. A first type of cells is marked as low loss and a second type of cells is marked as low delay. In the switching arrangement a cell buffer (9) is subdivided into a first memory area (LL) for the low loss cells and a second area (LD) for the low delay cells. In the case of the cell buffer (9) being completely filled, low loss cells get read-in priority over low delay cells. In reading out from the cell buffer low delay cells take priority over low loss cells, unless the low delay area is empty. It is also possible to set a threshold value for the content of the low loss area; when the content of the low loss area exceeds the threshold value, outputting of the low loss cells can then be started.

MICRO-FRAME MULTIPLEX TRANSMITTER

A multiplex transmitter for loading micro-frames smaller than a standard ATM cell on the standard ATM cell in a multiplexing state. Input micro-frames are sequentially introduced to a distributing circuit (504) through an interface (503). The circuit (504) distributes the micro-frames by using input distribution information. The distribution information follows service conditions set for each connection or each micro-frame. A buffer is selected for a fetching circuit (506) in accordance with prefixed buffer selecting logic. A cell discarding and monitoring circuit (508) discards such microframes that exceed allowable cell discarding time of t2-1 to t2-m. A multiplex processing circuit (507) delivers a cell or vacant cell to a cell output circuit (511) in accordance with the cell output timing of the circuit (511).

A FAULT TOLERANT SWITCHING SYSTEM FOR SATELLITE AND TERRESTRIAL SWITCHES

An apparatus for routing a plurality of cells. The apparatus includes a plurality of inputs, wherein the plurality of cells are received at the inputs. Each of the cells contains routing information. The apparatus also includes a plurality of outputs, wherein the outputs are associated with a plurality of destinations such that each output corresponds to a destination within the plurality of destinations. The apparatus employs a routing means for routing the cells received by the inputs through the apparatus to the outputs using the routing information contained in the cells. The routing means includes a number of single path switching matrixes in which each single path switching matrix has a plurality of stages. A portion of these stages are dilated such that two or more cells may be routed to the same destination.

NETWORK NODE FOR SHARING A COMMON BUFFER AMONG MULTIPLE CONNECTIONS WHILE ENSURING MINIMUM BANDWIDTH FOR EACH CONNECTION

A network node includes a single buffer connected to a transmission medium. Detection circuitry receives an incoming packet and detects the virtual connection of the received packet. Control circuitry calculates a value of delivery instant for the received packet according to a minimum bandwidth assigned to the detected virtual connection so that vacancy of the transmission medium is reduced to a minimum if the received packet were delivered from the buffer onto the transmission medium at the instant of the calculated value. The calculated value is compared with a decision threshold assigned to the detected virtual connection. The received packet is stored into the buffer if the calculated value is smaller than the decision threshold or discarded if the calculated value is greater than the decision threshold.

METHOD AND APPARATUS FOR TRACKING BUFFER AVAILABILITY

The invention is a method and apparatus for transmitting frames from a plurality of node ports (N_ports) to their associated fabric ports (F_ports) for forwarding to other interconnected F_ports on a Fibre Channel switch in which the transmitted frames are stored in a plurality of receive buffers (432, 434, 436, 438) at the associated F_port prior to forwarding to an interconnected F_port, and a receive credit counter(480), a smart credit counter (482) and a transmit credit counter (142) are employed for tracking the availability of the receive buffers.

Communication Data Receiver

ATM ARCHITECTURE AND SWITCHING ELEMENT

An ATM switching system architecture of a switch fabric type (20) is built of a plurality of ATM switch element circuits (40) and routing table circuits (30) for each physical connection to/from the switch fabric (20). A shared pool of memory (100) is employed to eliminate the need to provide memory at every crosspoint. Each routing table (30) maintains a marked interrupt linked list for storing information about which ones of its virtual channels are experiencing congestion. This linked list is available to a processor in an external workstation to alert the processor when a congestion condition exists in one of the virtual channels. The switch element circuit (40) typically has up to eight 4-bit-wide nibble inputs (10-17) and eight 4-bit-wide nibble outputs (O0-07) and is capable of connecting cells received at any of its inputs (1017) to any of its outputs (00-07), based on the information in a routing tag uniquely associated with each cell.

FRAME-RELAY FRAME TRANSMISSION CIRCUIT

The frame-relay frame transmission circuit of the present invention for reassembling a frame-relay frame into an Asynchronous Transfer Mode (ATM) cell comprises: a processor for determining a shift size for each connection, the shi ft size by which the frame is to be shifted from the top address of a frame buffer; a frame receiver for receiving the frame through the connection; a memory for storing the receive d frame in a frame buffer from an address shifted from the top of a frame buffer by the shift size; and a segmentation and reassembling device for reassembling the frame into the A TM cell.

HIGH SPEED PACKET SCHEDULING METHOD AND APPARATUS

A packet scheduler is disclosed which provides a high degree of fairness in scheduling packets associated with different sessions. The scheduler also minimizes packet delay for packet transmission from a plurality of sessions which may have different requirements and may operate at different transfer rates. When a packet is received by the scheduler, the packet is assigned its own packet virtual start time based on whether the session has any pending packets and the values of the virtual finish time of the previous packet in the session and the packets arrival time. The scheduler then determines a virtual finish time of the packet by determining the transfer time required for the packet based upon its length and rate and by adding the transfer time to the packet virtual start time of the packet. The packet with the smallest virtual finish time is then scheduled for transfer. By selecting packets for transmission in the above described manner, the available bandwidth may be shared in pro-rata ...

CENTRALIZED QUEUING FOR ATM NODE

An ATM switching node has a queuing resource (230) connected to an ATM switch core (30). The queuing resource provides centralized queuing for ATM cells destined for routing through the ATM switch core to plural output links. The ATM switch core routes an ATM cell destined for any output link requiring queuing to the centralilzed queuing resource. ATM cells for output links not requiring queuing are not directed to the queuing resource. The queuing resource has a link multiplexer (280) for each output link which is handled by the queuing resource. Each link multiplexer has both a first stage (304) and a second stage (302). The second stage comprises plural queues (312) for storing ATM packets and a second stage multiplexer (314) for selecting the ATM packets stored in the plural queues of the second stage for transmission to the first stage. The first stage comprises plural queues (320) for storing ATM cells and a first stage multiplexer (330) for selection of ATM cells including ATM cells ...

SWITCHING NETWORK HAS MULTIPLE WAYS AND HAS AUTOACHEMINEMENT FOR THE COMMUTATION OF CELLS HAS ASYNCHRONOUS TEMPORAL MULTIPLEXING.

AN INTERCONNECT APPARATUS AND A DATA COMMUNICATION METHOD

THE LOW-DELAY OR LOW-LOSS SWITCH FOR ASYNCHRONOUS TRANSFER MODE

Combined header parameter table for ATM node

Within an ATM node, a cell handling unit (CHU) receives incoming ATM cells from an ATM switch and provides outgoing ATM cells back to the ATM switch. The cell handling unit consults a combined or consolidated table to obtain ATM parameters (e.g., VCI) for use in headers of outgoing ATM cells. The combined table can be utilized both for ATM cells with AAL2 protocol and ATM cells of a second type AAL protocol. The second type AAL protocol is preferably AAL2 prime, which requires that AAL2 packets carried in the ATM cell payload be whole packets and that the ATM payload not have an AAL2-type start field. The combined table is structured to have plural intervals, including a first interval for AAL2 protocol connections and plural other intervals for the second type AAL protocol connections. Each row for the AAL2 protocol interval associates (1) a unique incoming VCI value; (2) an output link value; (3) an outging VCI value; and (4) an offset value. The offset value points to the one of the ...

DSL transmit traffic shaper structure and procedure

A method and apparatus for transmitting network traffic includes selecting a major node in a major ring, where the major node corresponds to a first transmission opportunity encoded in the major ring. The major node specifies a minor node in a minor ring representing a virtual port. The method and apparatus also includes transmitting network traffic to a virtual connection that uses the virtual port. Alternatively, transmitting network traffic involves processing a schedule that includes a sequence of transmission opportunities encoded in a schedule ring and satisfying a minimum data rate for a scheduled virtual connection by processing a corresponding first minimum number of transmission opportunities from the schedule, each such transmission opportunity allocated by a schedule node to the scheduled virtual connection, where the schedule node is included in the schedule ring.

HIERARCHICAL OUTPUT-QUEUED PACKET-BUFFERING SYSTEM AND METHOD

L'invention se rapporte à un système et à un procédé de mise en mémoire tampon qui permet à des dispositifs de communication intégrant une architecture à maillage total de parvenir à des niveaux d'agrégation de largeurs de bande normalement associés à des architectures à maillage partiel. Cette invention met en oeuvre une structure de mémoire hiérarchique comportant de premiers et de seconds tampons de paquets pour la mise en mémoire tampon des paquets entre les ports d'entrée et de sortie du dispositif de communication. Les paquets reçus sont organisés par port de sortie et niveau de priorité dans le premier tampon de paquets qui fonctionne à la vitesse réseau maximale du dispositif de communication. Ces paquets sont ensuite canalisés, avec une priorité et des affectations de ports de sortie correspondantes et à une vitesse inférieure à la vitesse réseau, vers les seconds tampons de paquets qui présentent des profondeurs de tampons excédant celui du premier tampon de paquets. Le système ...

ASYNCHRONOUS TRANSFER MODE SWITCH

A switching device for switching ATM cells from a plurality of network input links to a plurality of network output links comprises a plurality of ports containing line interfaces and input and output buffers, a hardware switch controller, a microprocessor, and memory for storing routing tables and system software. All these elements are interconnected via a processor bus, and additionally, the ports are interconnected by a separate switching bus. The switch controller employs hash-based routing table indexing to route cells from selected input ports to appropriate output ports according to the cells' header information. Switch requests generated by incoming cells are arbitrated using a token bus allocation scheme. The majority of cells are switched almost entirely in hardware, but the microprocessor can assume control of the switching architecture to resolve exception conditions and to perform special processing on selected virtual circuits. Two output buffers perport are provided; one ...

PRIORITIZED-BUFFER MANAGEMENT FOR FIXED SIZE PACKETS IN MULTIMEDIA APPLICATIONS

Tampon à priorité pour la couche de contrôle d'accès au support (MAC), destiné à des applications multimédia, en particulier en réseau sans fil à mode de transfert asynchrone (MTA) dans lequel une réservation, fondée sur l'accès multiple à répartition temporelle (AMRT), est exécutée sur la base de trames de données de commande (CDF). Ledit tampon est constitué par un système mémoire adressable divisé en pages séquentielles d'égales dimensions pour stocker des paquets de données respectifs ou des cellules MTA ayant le même nombre d'octets. Le système mémoire comprend un registre d'étiquettes pour stocker les étiquettes associées aux pages respectives, chaque étiquette indiquant l'état plein ou vide de la page associée; un registre miroir pour stocker les mises à jour sans conflit provenant du registre d'étiquettes; et un registre de pages pour stocker des pointeurs vers la page libre ou inoccupée la plus basse. Les adresses tampon séquentielles des emplacements de mémoire dans le système ...

CELL-BASED CLOCK RECOVERY DEVICE

A clock recovery unit provides a clock recovery function in the receiving entity of a system to implement adaptation of constant bit-rate (CBR) services over an asynchronous transfer mode (ATM) or ATM-like network. Incoming cells are periodically sampled for buffer fill level Li. The maximum fill level of undelayed cells Lxj is extracted from successive series of a predetermined whole number M of buffer-fill samples Li. A frequency adjustment logic unit provides at its output a bit stream at a given clock frequency fj. The frequency adjustment logic unit makes incremental adjustments to the clock frequency fj tending to cause the steady state mean of the fill level Lxj, or its derivative, to move toward zero.

A FAULT TOLERANT SWITCHING SYSTEM FOR SATELLITE AND TERRESTRIAL NETWORKS

A switch that has a plurality of inputs in which cells are received at these inputs. Each cell received at the inputs of the switch contain routing information. A routing means is employed to route the cells received at the inputs of the switch to outputs using routing information in which a number of the cells are misrouted by the routing means during the process of routing the cells to the outputs. Bus means is employed to route a cell to the destination in which the bus means is connected to the routing means. The bus means routes misrouted cells that are misrouted from the destination by some selected amount.

METHOD AND APPARATUS FOR EMULATING A CIRCUIT CONNECTION IN A CELL BASED COMMUNICATIONS NETWORK

The invention comprises a method and apparatus for emulating a circuit connection in a cell based communications network (10). A virtual connection is sent from a source connected to the network (10) to a node (12) in the network (10) wherein the virtual connection comprises a series of data cells comprising a header portion and a data portion. The virtual connection is transported across at least one communications link (14) connecting the first node (12) to a second node (12) in the network (10). A first queue is dedicated to the virtual connection at each node (12) in the network (10) through which signal passes. The queue comprises a first amount of buffer space, is dedicated for the duration of the circuit connection and, dedicated only to that virtual connection. A first amount of link bandwidth is allocated to the virtual connection on each communication link (14) across which the virtual connection passes. The amount of link bandwidth is allocated for the duration of the circuit ...

DEVICE FOR OPTIMAL PROCESSING OF INFORMATION IN A PACKET-ORIENTED TRANSMISSION

The invention relates to a device for optimal processing of information in a packet-oriented transmission. According to the prior art, a plurality of FIFO registers are usually used to process job queues. One problem associated with this is that the use of a plurality of FIFO registers incurs significant costs. The invention avoids this problem by combining the plurality of FIFO registers in one FIFO register.

SCHEDULER IMPLEMENTING WEIGHTED FAIR QUEUING BY A WEIGHT LIMITED FIRST IN-FIRST OUT METHODOLOGY

L'invention concerne des procédés et un appareil d'ordonnancement qui font appel à une méthode PEPS à poids limité (WLF), afin de fournir une mise en file d'attente pondérée par connexion tout en maximisant la préservation de l'ordre d'arrivée des cellules, réduisant ainsi les variations additionnelles du retard des cellules (CDV) ajoutées au cours de l'ordonnancement. La présente invention permet de réduire les CDV additionnelles d'une connexion jusqu'à ce que cette dernière ait dépassé sa juste part d'exploitation des ressources.

Switch fabric with memory management unit for improved flow control

A method for controlling a flow of packet data in a memory management unit of a network switch fabric is disclosed. A first portion of a data packet is received at a port on an ingress bus ring of the network switch fabric. A class of service for the data packet is determined based on the first portion and the portion is stored in a packer RAM of the port based on the class of service. Subsequent portions of the data packet are stored in the packer RAM. Once the predetermined number of portions have been received, the predetermined number of portions is sent to a packet pool RAM. A reference pointer to a first predetermined number of portions is sent to a transaction queue once an end of packet is detected and an egress scheduler detects a presence of a ready packet in the transaction queue and notifies an unpacker of the ready packet. The unpacker puts the ready packet into a FIFO and the ready packet is sent to an ingress/egress module.

Connection admission control based on bandwidth and buffer usage

A connection admission control (CAC) technique for a telecommunications node approximates probability of loss using a log moment generating function and its two partial derivatives of workload on a queue over a time interval. The approximation uses four state variables, which depend on the log moment generating function and its two partial derivatives. The four state variables are: (1) Linear term in approximation to log loss ratio at a working point; (2) the argument of logarithmic term in approximation to log loss ratio at the working point; (3) a buffer limit used at the working point; and (4) a multiplier of imaginary traffic used at the working point. Advantageously, these state variables vary linearly with the traffic, so a new connection can simply add its contributions to them. The connection admission control (CAC) uses the state variables to produce the following three parameters: (1) an approximation q=z−log(c) to the logarithm of the probability of loss; (2) a buffer size limit ...

Method and apparatus for performing priority control for cells in output buffer type ATM switch

There is provided a method of performing priority control for cells in an output buffer type ATM switch including a switching unit, having a plurality of input ports and a plurality of output ports, for switching/outputting the cells input from the input ports to the output ports in accordance with routing information, and a plurality of output buffer units having output buffer memories, connected to the output ports of the switching unit, for temporarily storing the cells output from the output ports to perform output control of the cells. A loss quality class, a delay quality class and the routing information are added to each of the cells. A plurality of logical queues for temporarily storing the cells are virtually set in an input buffer memory in accordance with the delay quality classes and the routing information. The input cells are selectively written in the logical queues on the basis of the loss quality classes and the routing information added to the cells. A transition process ...

ATM cell forwarding and label swapping method and apparatus

The techniques required to switch an ATM cell between an input adapter and an output adapter are enhanced by performing two look-up operations. The first look-up operation is performed in the input adapter which receives the cell to be switched. The first look-up operation retrieve the address of the target output port and a connection control block. The second look-up operation is performed in the target output adapter and makes use of the results of the input adapter search to retrieve the information need to complete the transfer of the cell to the target output port.

Device and method for cell processing in cell relay nodes

A cell processor and a method for a cell processor (CP) utilize Cell Transit Queues to partition cell processing of cells from a Cell Interconnect in a cell relay network, thereby facilitating cost-efficient cell transmission from a cell interconnect to a node output.

System and method for multi-frame received queuing with sorting in an asynchronous transfer mode (ATM) system

An ATM information system processes information at the frame level using a processor including a device driver; a system memory and an adapter for sorting data cells into partially completed frames stored in the system memory using control information provided by the device driver. A controller in the adapter determines when an end of frame indication is received in a cell and updates a pointer in system memory for a completed frame list to a recently completed frame. The device driver processes frames in a completed frame list according a priority of the list. The device driver processing is independent of the sorting and storing of completed frames received in the system memory which improves the performance of the driver and the ability to handle delay sensitive traffic.

Packet input thresholding for resource distribution in a network switch

A system and method for input thresholding packets in a network switch. A network switch may include multiple input ports, multiple output ports, and a shared random access memory coupled to the input ports and output ports by data transport logic. Packets entering the network switch may be assigned to one of a plurality of threshold groups and to one of a plurality of flows within the threshold group. In one embodiment, each threshold group may be divided into a plurality of levels of operation. As resources are allocated or freed by the threshold group, the threshold group may dynamically move up or down in the levels of operation. Within each level, one or more different values may be used as level boundaries and resource limits for flows within the threshold group. In one embodiment, programmable registers may be used to store these values.

Method and system for guaranteeing quality of service in large capacity input output buffered cell switch based on minimum bandwidth guarantees and weighted fair share of unused bandwidth

Data cells of plural classes are transferred from input ports to output ports through a switch by storing the cells at each input port in class-specific virtual output queues (VOQ) within sets of VOQs associated with output ports, and providing credits to VOQs according to class-associated guaranteed bandwidths. When a cell is received at a VOQ having credits, a high-priority request for transfer is generated. If a cell is received at a VOQ that does not have any available credits, a low-priority request for transfer is generated. In response to requests, grants are issued to VOQ sets without regard to class, high-priority requests being favored over low-priority requests. When a grant is received for a particular VOQ set, an arbitrator selects a VOQ from the set, giving priority to VOQs having credits over VOQs without credits, and a cell from the selected VOQ is transferred. Requests generated from all input ports are forwarded to a central scheduler associated with a switch fabric slice ...

Hardware self-sorting scheduling queue

The scheduling queue of the present invention is configured as a systolic array utilizing self-sorting scheduling cells to sort information packets based upon previously assigned priorities, while at the same time yielding a small constant latency independent of the length of the queue. The scheduling queue of the present invention is effective in supporting various Quality of Service (QoS) policies and algorithms, including both Differentiated Services (DiffServ) and Integrated Services (IntServ) having an arbitrary number of flows.

High performance fault tolerant switching system for multimedia satellite and terrestrial communications networks

A switch that has a plurality of inputs in which cells are received at these inputs. Each cell received at the inputs of the switch contain routing information. A routing means is employed to route the cells received at the inputs of the switch to outputs using routing information in which a number of the cells are misrouted by the routing means during the process of routing the cells to the outputs. Bus means is employed to route a cell to the destination in which the bus means is connected to the routing means. The bus means routes misrouted cells that are misrouted from the destination by some selected amount.

Distributed type switching system

A switching system for integratedly switching voice, data, image information and the like. The switching system comprises a plurality of front-end modules each adapted to perform a switching processing in association with a subscriber line or a trunk line, and a single or a plurality of central modules for interconnecting the plurality of front-end modules in star-type fashion and switching information prevailing between the front-end modules, in unit of block accommodating the information and a header added thereto to contain connection control information and in accordance with the contents of the header. The front-end modules are connected to the central module via inter-module highways each having frames occurring at a predetermined period and time slots contained in each frame to carry blocks.

Pass/drop apparatus and method for network switching node

A switching node for transferring packets, each including a destination address, in a network includes a plurality of input port modules, a plurality of output port modules and a switching fabric, including a packet meta-data processor and a packet switch. Each input port module is connected to a communication link for receiving packets thereover, and each output port module is connected to a communication link for transmitting packets thereover. Each input port module, upon receiving a packet, buffers the packet and generates a meta-data packet therefor identifying the output port module that is to transmit the packet and packet identifier information, and provides it to the packet meta-data processor. The packet meta-data processor receives the meta-data packets generated by all of the input port modules and operational status information from all of the output port modules and for each output port module, processes the meta-data packets received from all of the input port modules in ...

ATM cell switching system

An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting ...

Method and apparatus for scheduling cells in an input-queued switch

A high-bandwidth input-queued switch includes a set of input queues, a rotating priority iterative matching desynchronizing scheduler, and a crossbar switch. Each input queue includes at least one stored cell with an output device designation signal and a data signal. Each output device designation signal is processed by the rotating priority iterative matching desynchronizing scheduler so that the data signal associated with the output device designation signal is routed through the crossbar switch to an output device specified by the output device designation signal. The rotating priority iterative matching desynchronizing scheduler includes a set of grant scheduler units, each of which receives a set of device designation signals and generates an input device grant signal on the basis of a grant scheduler priority designation signal. The scheduler also includes a set of accept scheduling units, each of which receives a set of input device grant signals from the grant scheduling units ...

Method and apparatus for providing programmable memory functions for bi-directional traffic in a switch platform

A method and apparatus for providing programmable memory functions for bi-directional cell traffic in a switch platform are provided, wherein a parameterized bi-directional FIFO unit controls cell traffic in a switch platform using a first and a second unidirectional FIFO buffer. The first and second unidirectional FIFO buffers each comprise asynchronous read and write ports. A cell size and a word size of the first and second unidirectional FIFO buffers are programmable. The bi-directional FIFO unit is coupled to write at least one cell from and read at least one cell to at least one asynchronous transfer mode (ATM) interface, at least one frame relay interface, at least one voice interface, and at least one data interface. As such, the first unidirectional FIFO buffer is coupled to write at least one cell from, and the second unidirectional FIFO buffer is coupled to read at least one cell to an ATM interface, a frame relay interface, a voice interface, and a data interface. The first ...

Data transmission with constant data rate

A method for forming data received from a data source into frames for transmission over a data link according to a protocol in which data is carried as data frames and in which once transmission of the data frame begun the entirety of the data frame must be transmitted at no less than a pre-set data rate, the method comprising: including in a frame traffic data formed from data received for transmission from the data source, and if insufficient data received for transmission from the data source is available to transmit the frame at the pre-set data rate, including in the frame padding data, the padding data being of a predetermined format distinguishable from the traffic data.

Input buffering and queue status-based output control for a digital traffic switch

A digital traffic switch having DIBOC buffer control has a queue status-based control strategy to limit status traffic on the switch and status buffer requirements. Status messages are transmitted from inputs to outputs when the content status of a logical output queue has changed from "empty" to "not empty", or vice versa, rather than on a "per cell" request basis. Status messages are transmitted from outputs to inputs when the clearance status of a logical output queue has changed from "not clear to release" to "clear to release", or vice versa, rather than on a "per cell" grant basis. The status of each logical output queue is monitored at outputs by retaining and updating a single status bit which has a particular binary value when the logical output queue's status is "empty" and the opposite binary value when the logical output queue's status is "not empty". The status of each logical output queue is monitored at inputs by retaining and updating a single status bit which has a particular ...

Packet transfer method and device

A packet transfer device that can be easily realized even when a number of input ports is large. Each input buffer temporarily stores entered packets class by class, and outputs packets of a selected class specified by the control unit, while the control unit determines the selected class of packets to be outputted from the input buffers according to a packet storage state in the packet storage units of the input buffers as a whole for each class. Each input buffer can temporarily store entered packets while selecting packets to be outputted at a next phase, and the control unit can specify packets to be selected in the input buffers according to an output state of packets previously selected in the input buffers as a whole. Packets stored in the buffer can be managed in terms of a plurality of groups, and each packet entered at the buffer can be distributed into a plurality of groups so that packets are distributed fairly among flows. The packets belonging to one of a plurality of groups ...

Communiction control device and method for an ATM system applicable to an ABR mode

Digital communications switching fabric

A type of switching fabric for exchanging variable-size frames of digital information between frame processors coupled directly or indirectly to one or more digital communication lines. It comprises one or more multi-line serial communication controllers (MSCCs), and a backplane providing a full mesh of serial point-to-point bi-directional links between each MSCC, and, in a loopback, from each MSCC back to itself. The MSCCs collectively manage the transfer of variable-size frames between the frame processors. To transfer digital information from a source line to a destination line, a frame processor coupled to the ingress line drives the switching fabric by signaling its MSCC that there is information. The ingress MSCC then switches the digital information through the backplane to the MSCC serving the frame processor coupled to the egress line. The switching fabric uses a clocking scheme that makes possible high throughput rates.

Apparatus for testing ATM channels

Interrupt modulator for receiving bursty high speed network traffic

Buffer device suitable for asynchronous transfer mode communication

A buffer device capable of dealing with multiple priority levels in which the efficiency of the memory capacity utilization can be improved such that the priority levels can be handled at the higher efficiency with smaller memory capacities, and which is adaptable to a high speed buffer implementation. The device includes a data register array (10) containing empty data registers and imaginary FIFO queues, and an administrative register array (11) comprised of a two port RAM (11a,11b) for storing pointer chains specifying the imaginary FIFO queues. The input of data is accompanied by the modification of the pointer chain to extend it, whereas the output of data is accompanied by the modification of the pointer chain to shorten it, so that the imaginary FIFO queues are administered in flexible manner in order to achieve efficient memory capacity utilization. The procedure for controlling the imaginary FIFO queues can be executed in parallel because of the independency of read and write operations ...

METHOD AND SYSTEM FOR SCHEDULING INFORMATION USING CALENDARS

A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. The priorities in the preferred embodiment include a low latency service, a minimum bandwidth, a weighted fair queueing and a system for preventing a user from continuing to exceed his service levels over an extended period. The present invention includes a plurality of calendars with different service rates to allow a user to select the service rate which he desires. If a customer has chosen a high bandwidth for service, the customer will be included in a calendar which is serviced more often than if the customer has chosen a lower bandwidth.

CIRCUIT AND METHOD FOR SERVICE CLOCK RECOVERY

A circuit and method for synchronizing a service clock at a destination node with a service clock at a source node for circuit emulation service over a packet network. The method includes receiving data packets from a source node at at least one port of the destination node. At the destination node, the method removes from the data packets residual time stamp (RTS) values that were created at the source node based on at least the service clock at the source node. RTS values are stored in memory at the destination node. The method determines a majority count and a minority count of RTS values over a period of time from the RTS values stored in memory. The method further uses the majority and minority counts to set the frequency of a service clock at the destination node for use in receiving data packets.

Method of operating a packet reassembly buffer

Described herein is a method for reassembling variable length packets from fixed length cells. When a variable length packet, for example, an Internet Protocol (IP) packet, is transmitted between routers over a link which transmits data as fixed length cells, for example, an asynchronous transfer mode (ATM) link, the packet must be segmented into compatible fixed length cells. The receiving router must reassemble the original packet from the cells as they arrive. A packet buffer free pool (300) is provided which is maintained as a linked list, known as a 'free list', and which comprises a plurality of buffer elements (302, 304, 306, 308, 310, 312, 314, 316, 318, 320, 322, 324, 326, 328, 330, 332, 334, 336, 338, 340). When a first cell for a given packet arrives, a buffer element (302) is taken from the head of the free list and allocated to that packet. The packet data from the first and subsequent cells is copied into the allocated buffer element and each time the buffer element is moved ...

Adaptive digital clock recovery

Adaptive clock recovery enables the clock of a CBR service to be recovered, this service being emulated from an ATM transmitter, is provided at an ATM receiver. The fill level of a first buffer receiving a stream of cells is used to provide coarse control of the rate of output of a stream of cells from the first buffer. The fill level of a further, fine, buffer receiving said stream of cells from the first buffer is monitored for determining a clock frequency, corresponding to the service clock frequency, for outputting cells from the fine buffer. The first buffer fill level control provides low pass cell jitter filtering by selectively supplying a first or a second clock frequency for outputting cells from the first buffer. The fine filter fill level control employs a phase locked loop responsive to the current fill level to set a clock frequency for reading out said fine buffer at the service clock frequency. ...

Optical switch matrix

Asynchronous time division multiplex communication system

Packet switching network

ATMスイッチにおける輻輳を制御するためにしきい値を変更するための装置および方法

ATMスイッチにおいて、キューしきい値はスイッチ輻輳に依存して動的に変化する。すべてのキューが1つ以上のクラスに組織化される。各クラスのためのしきい値はクラスのすべてのキューにおけるセルの数に逆比例して依存する。 ...

CELL ABORT AVOIDANCE SYSTEM AND METHOD IN BUFFER

PROBLEM TO BE SOLVED: To prevent cells remaining in a QoS buffer from being aborted to the utmost in advance in the case that traffic of a specific QoS class in an ATM exchange is increased. SOLUTION: The ATM exchange is provided with a storage cell number monitor section that monitors congestion in a plurality of QoS buffers of buffer sections 3, 5, a software data section 813 that stores cell read priority (WRR value) added to each QoS buffer, and a software control section 812 that dynamically changes the WRR value on the occurrence of a QoS buffer (occurrence of cell abort or buffer congestion warning) to increase the WRR value of the QoS buffer where cell abort takes place, and reads cells from the QoS buffer in time division according to the weight of the WRR value in a share round form. Moreover, the ATM exchange restores the WRR value to an initial value when the congestion of the QoS buffer is stopped. COPYRIGHT: (C)2001,JPO ...

Verfahren zur Verwaltung eines gemeinsamen Speichers in Netzknoten

Context-switched multi-stream pipelined reorder engine

A pipelined reorder engine reorders data items received over a network on a per-source basis. Context memories correspond to each of the possible sources. The pipeline includes a plurality of pipeline stages that together simultaneously operate on the data items. The context memories are operatively coupled to the pipeline stages and store information relating to a state of reordering for each of the sources. The pipeline stages read from and update the context memories based on the source of the data item being processed.

Apparatus & method

A method of controlling data packet congestion in a data packet network comprises determining a reference flow condition that results in data packet congestion at a node of a data packet network, and identifying a data packet flow having a flow condition substantially equal to the reference flow condition. For such an identified data packet flow the following actions are taken causing a data packet to be dropped from the identified data packet flow, allowing a predetermined number of data packets from the identified data packet flow to proceed, and dropping data packets from the identified data packet flow subsequent to the predetermined number of data packets, until the packets that were not dropped have been delivered to the egress ports of the network.

ACCESS NODE FOR DATA CENTERS

A highly-programmable access node is described that can be configured and optimized to perform input and output (I/O) tasks, such as storage and retrieval of data to and from storage devices (such as solid state drives), networking, data processing, and the like. For example, the access node may be configured to execute a large number of data I/O processing tasks relative to a number of instructions that are processed. The access node may be highly programmable such that the access node may expose hardware primitives for selecting and programmatically configuring data processing operations. As one example, the access node may be used to provide high-speed connectivity and I/O operations between and on behalf of computing devices and storage components of a network, such as for providing interconnectivity between those devices and a switch fabric of a data center. 1. An access node integrated circuit comprising:a networking unit configured to control input and output of data between a network and the access node integrated circuit;one or more host units configured to at least one of control input and output of the data between the access node integrated circuit and one or more application processors or control storage of the data with one or more storage devices;a plurality of processing clusters, each of the processing clusters including two or more programmable processing cores configured to perform processing tasks on the data;a data network fabric interconnecting the plurality of processing clusters, the one or more host units, and the networking unit, wherein the data network fabric is configured to carry the data between the networking unit, the one or more host units, and the plurality of processing clusters; andat least one control network fabric interconnecting the plurality of processing clusters, the one or more host units, and the networking unit, wherein the at least one control network fabric is configured to carry control messages identifying the ...

SYSTEMS AND METHODS FOR DYNAMIC POWER USAGE AND DATA TRANSFER RATE MANAGEMENT IN A SENSOR NETWORK

Described are systems, methods, and computer readable medium for dynamic power usage and data transfer rate management in a sensor network including synchronous and asynchronous links. Exemplary embodiments provide a lightweight communication protocol enabling dynamic management of data buffer size in a sensor network and corresponding control of power usage and data transfer rates in the sensor network. 1. A system for dynamic power usage and data transfer rate management in a sensor network including synchronous links and asynchronous links , the system comprising:a root node that includes a microcontroller or microprocessor device, the root node configured to generate and send a data read request command;a link node that maintains one or more data buffers, the link node in wired communication with the root node and configured to receive the data read request command from the root node and route the data read request command to a destination sensor among a plurality of sensors; andthe plurality of sensors, each of the plurality of sensors in wired communication with the link node, the destination sensor among the plurality of sensors configured to sense data and store the data in at least one of the one or more data buffers maintained by the link node based on the data read request command,wherein the root node is configured to dynamically increase or decrease a size of the one or more data buffers maintained by the link node to manage power usage and data transfer rates in the sensor network.2. The system of claim 1 , wherein the data read request command from the root node is accompanied by metadata identifying the destination sensor and the link node is further configured to route the data read request command to the destination sensor based on the metadata included with the data read request command claim 1 , the link node not processing the data read request command.3. The system of claim 1 , wherein the destination sensor is configured to generate and send a ...

BUS CONVERTER

A device for coupling a fieldbus to a local bus for connection to at least one data bus subscriber, the device comprising a first unit that is connectable to the fieldbus and is adapted for sending and receiving data via the fieldbus; a second unit that is connectable to the local bus and is adapted for sending and receiving data via the local bus in at least one data packet; a data management unit that is connected to the first unit and the second unit, wherein the data management unit is adapted for transferring first symbols from data received via said first unit to said second unit in a sequence-dependent manner; and wherein the second unit is adapted to send at least one data packet including the first symbols on the local bus. In addition, a corresponding method for transferring data is described. 1. A device for coupling a fieldbus to a local bus for connecting to at least one data bus subscriber , the local bus being a ring bus , the device comprising:a first unit connectable to the fieldbus and adapted to send and receive data via the fieldbus;a second unit connectable to the local bus and adapted to send and receive data via the local bus in at least one data packet;a data management unit connected to the first unit and the second unit, the data management unit being adapted to transfer first symbols from data received via the first unit to the second unit in a sequence-dependent manner; and the second unit being adapted to send at least one data packet including the first symbols on the local bus.2. The device according to claim 1 , wherein the data management unit is adapted to prepend and/or append additional symbols to the first symbols.3. The device according to claim 1 , wherein the data management unit is adapted to temporarily store the first symbols.4. The device according to claim 1 , wherein the second unit is adapted to generate the at least one data packet comprising the first symbols and to send the at least one data packet on the local bus.5 ...

TECHNOLOGIES FOR JITTER-ADAPTIVE LOW-LATENCY, LOW POWER DATA STREAMING BETWEEN DEVICE COMPONENTS

Technologies for low-latency data streaming include a computing device having a processor that includes a producer and a consumer. The producer generates a data item, and in a local buffer producer mode adds the data item to a local buffer, and in a remote buffer producer mode adds the data item to a remote buffer. When the local buffer is full, the producer switches to the remote buffer producer mode, and when the remote buffer is below a predetermined low threshold, the producer switches to the local buffer producer mode. The consumer reads the data item from the local buffer while operating in a local buffer consumer mode and reads the data item from the remote buffer while operating in a remote buffer consumer mode. When the local buffer is above a predetermined high threshold, the consumer may switch to a catch-up operating mode. Other embodiments are described and claimed. 1. A computing device for data streaming between components , the computing device comprising:a consumer component to determine whether a data item produced by a producer component of the computing device is available in a local buffer or a remote buffer during operation in a local buffer mode or during operation in a remote buffer mode, wherein the local buffer and the remote buffer are accessible to the consumer component and the producer component;a local buffer consumer logic to (i) determine whether the local buffer is empty in response to a determination that the data item is available during operation in the local buffer mode, and (ii) switch to the remote buffer mode in response to a determination that the local buffer is empty; anda remote buffer consumer logic to (i) determine whether the remote buffer is empty in response to a determination that the data item is available during operation in the remote buffer mode, and (ii) switch to the local buffer mode in response to a determination that the remote buffer is empty;wherein the consumer component is further to (i) read the data ...

Enhanced acknowledgement handling in communication packet transfer

Described herein are methods, systems, and software for handling packet buffering between end users and content servers, such as content delivery nodes. In one example, a method of operating a content server includes generating first and second data packets for first and second content requests. Once generated, the method provides storing the first packets in a packet buffer and transferring the first packets to a first user device. Upon transfer, the first packets are deleted from the packet buffer and replaced with the second packets.

COMMUNICATION APPARATUS, COMMUNICATION METHOD, AND RECORDING MEDIUM

In order to achieve a communication apparatus capable of efficiently transmitting data, the present invention is provided with a plurality of buffers configured to cause a communication packet to wait therein, and an intra-buffer packet switching means for moving a predetermined communication packet among packets waiting in the plurality of buffers from a first buffer in which the predetermined communication packet waits to a second buffer among the plurality of buffers. 1. A communication apparatus comprising:a plurality of buffers configured to cause a communication packet to wait therein; andan intra-buffer packet switch configured to move a predetermined communication packet among packets waiting in the plurality of buffers from a first buffer in which the predetermined communication packet waits to a second buffer among the plurality of buffers.2. The communication apparatus according to claim 1 , further comprising:a destination distributor configured to distribute a communication packet to the plurality of buffers and send the communication packet; anda plurality of rate controllers configured to send the communication packet sent from the plurality of buffers at a predetermined rate.3. The communication apparatus according to claim 1 , further comprisinga packet sending start commanding unit configured to instruct stop of sending the predetermined communication packet from the second buffer when the movement starts, and instruct sending of the predetermined communication packet from the second buffer when sending of all communication packets of a kind identical to a kind of the predetermined communication packet from the first buffer is detected.4. The communication apparatus according to claim 1 , further comprising:a timer which indicates, when a timer value greater than a rate of the predetermined communication packet is set and the communication packet is sent from the buffer, a display value to be decreased from the timer value with a lapse of time; ...

COMBINED INPUT AND OUTPUT QUEUE FOR PACKET FORWARDING IN NETWORK DEVICES

An apparatus for switching network traffic includes an ingress packet forwarding engine and an egress packet forwarding engine. The ingress packet forwarding engine is configured to determine, in response to receiving a network packet, an egress packet forwarding engine for outputting the network packet and enqueue the network packet in a virtual output queue. The egress packet forwarding engine is configured to output, in response to a first scheduling event and to the ingress packet forwarding engine, information indicating the network packet in the virtual output queue and that the network packet is to be enqueued at an output queue for an output port of the egress packet forwarding engine. The ingress packet forwarding engine is further configured to dequeue, in response to receiving the information, the network packet from the virtual output queue and enqueue the network packet to the output queue. 1. An apparatus for switching network traffic , the apparatus comprising: determine, in response to receiving a network packet, an egress packet forwarding engine for outputting the network packet; and', 'enqueue the network packet in a virtual output queue for output to the egress packet forwarding engine;, 'an ingress packet forwarding engine implemented in circuitry and configured tothe egress packet forwarding engine implemented in processing circuitry and configured to, in response to a first scheduling event, output, to the ingress packet forwarding engine, information indicating the network packet in the virtual output queue and that the network packet is to be enqueued at an output queue for an output port of the egress packet forwarding engine; dequeue the network packet from the virtual output queue; and', 'enqueue the network packet to the output queue; and, 'wherein the ingress packet forwarding engine is further configured to, in response to receiving the information dequeue the network packet from the output queue; and', 'output the network packet at ...

SCHEDULING GRANULARITY BASED ON APPLICATION TYPE

The present disclosure generally discloses a scheduling granularity capability. The scheduling granularity capability is configured to improve scheduling granularity in a wireless communication system supporting transport of application flows via radio bearers. The scheduling granularity capability may be configured to support improved scheduling granularity by controlling scheduling at various levels of granularity, such as at the bearer level (e.g., for scheduling bearers with respect to each other), at the application flow level (e.g., for scheduling the application flow of a bearer when the bearer includes a single application flow, for scheduling application flows of a bearer with respect to each other when the bearer includes multiple application flows, or the like), or the like, as well as various combinations thereof. The scheduling granularity capability may be configured to support improved scheduling granularity by identifying application types of application flows supported by the bearers and controlling scheduling, at various layers of granularity, based on the application types of the application flows supported by the bearers. 1. An apparatus , comprising: separate, for a bearer including a set of application flows, packets of the respective application flows into a respective set of per-flow queues associated with the respective application flows of the bearer;', 'identify, based on the per-flow queues associated with the respective application flows of the bearer, respective application types of the respective application flows of the bearer;', 'adapt scheduling of one of the application flows of the bearer based on one or more of the respective application types of one or more of the respective application flows of the bearer; and', 'adapt scheduling of the bearer based on one or more of the respective application types of one or more of the respective application flows of the bearer., 'a processor and a memory communicatively connected to the ...

ADAPTIVE JITTER BUFFER

The present disclosure relates to an adaptive jitter buffer for buffering audio data received via a network. The adaptive jitter buffer comprises an adaptive audio sample buffer, which comprises an adaptive resampler that receives a number of audio samples of the audio data and that outputs a first number of audio samples, which are resampled from the received number of audio samples according to a resampling factor, an audio sample buffer that buffers audio samples, wherein the outputted first number of audio samples are written to the audio sample buffer during an input access event and a second number of audio samples are read from the audio sample buffer during an output access event, and an audio sample buffer fill quantity controller that controls a fill quantity of the audio sample buffer based on controlling the resampling factor of the adaptive resampler. 1. An adaptive jitter buffer for buffering audio data received via a packet-switched network , comprising:an adaptive resampler that receives a number of audio samples of the audio data and that outputs a first number of audio samples, which are resampled from the received number of audio samples according to a resampling factor,an audio sample buffer that buffers audio samples, wherein the outputted first number of audio samples are written to the audio sample buffer during an input access event and a second number of audio samples are read from the audio sample buffer during an output access event, andan audio sample buffer fill quantity controller that controls a fill quantity of the audio sample buffer, wherein the audio sample buffer fill quantity controller controls the fill quantity of the audio sample buffer based on controlling the resampling factor of the adaptive resampler.2. The adaptive jitter buffer according to claim 1 , wherein the audio sample buffer fill quantity controller comprises:an audio sample buffer fill quantity estimator that estimates an average instantaneous fill quantity of ...

METHOD AND APPARATUS FOR ORDER ENTRY IN AN ELECTRONIC TRADING SYSTEM

Orders received by an electronic trading system are processed in batches based on the instrument to which an order relates. An incoming order is assigned to a queue of a queue set that makes up the batch according to a random process. Where orders are received from related trading parties they are assigned to the same queue set according to their time of receipt. The batch has a random duration within defined minimum and maximum durations and at the end of the batch, the orders held in the queues are transferred to a matching thread of the trading system sequentially with one order being removed from each queue and a number of passes of the queues completed until orders have been removed. 1. A computerized method for submission of orders to an electronic trading system for matching , comprising the steps of:receiving at a server, from parties trading on the electronic trading system, electronic order messages for trading an instrument;initiating a message batch having a defined duration;storing the received electronic order messages in a storage device of the server, the orders being stored in said storage device in an order in which they were received at the electronic trading system;after expiry of the defined duration of the batch, submitting the stored order messages to a matching engine of the electronic trading system in an order unrelated to the order in which they are stored in the storage device.2. A method according to claim 1 , comprising claim 1 , on receipt of an order message claim 1 , determining the origin of the order message claim 1 , determining whether another order message from the same origin is stored in the storage device for the batch and claim 1 , if another such message is stored claim 1 , queuing the message behind the earlier stored message claim 1 , whereby on expiry of the batch duration claim 1 , the earlier stored message from the same origin is sent for matching ahead of the later received message from the same origin.3. A method ...

Access node for data centers

An access node that can be configured and optimized to perform input and output (I/O) tasks, such as storage and retrieval of data to and from network devices (such as solid state drives), networking, data processing, and the like. For example, the access node may be configured to receive data to be processed, wherein the access node includes a plurality of processing cores, a data network fabric, and a control network fabric; receive, over the control network fabric, a work unit message indicating a processing task to be performed a processing core; and process the work unit message, wherein processing the work unit message includes retrieving data associated with the work unit message over the data network fabric.

TECHNOLOGIES FOR JITTER-ADAPTIVE LOW-LATENCY, LOW POWER DATA STREAMING BETWEEN DEVICE COMPONENTS

Technologies for low-latency data streaming include a computing device having a processor that includes a producer and a consumer. The producer generates a data item, and in a local buffer producer mode adds the data item to a local buffer, and in a remote buffer producer mode adds the data item to a remote buffer. When the local buffer is full, the producer switches to the remote buffer producer mode, and when the remote buffer is below a predetermined low threshold, the producer switches to the local buffer producer mode. The consumer reads the data item from the local buffer while operating in a local buffer consumer mode and reads the data item from the remote buffer while operating in a remote buffer consumer mode. When the local buffer is above a predetermined high threshold, the consumer may switch to a catch-up operating mode. Other embodiments are described and claimed. 1. A computing device for data streaming between components , the computing device comprising:a producer component to generate a data item during operation in a local buffer mode or during operation in a remote buffer mode;a local buffer producer logic to (i) determine whether a local buffer is full in response to generation of the data item during operation in the local buffer mode, and (ii) switch to the remote buffer mode in response to a determination that the local buffer is full; anda remote buffer producer logic to (i) determine whether a remote buffer is below a low threshold in response to generation of the data item during operation in the remote buffer mode, and (ii) switch to the local buffer mode in response to a determination that the remote buffer is below the low threshold;wherein the producer component is further to (i) add the data item to the local buffer during operation in the local buffer mode, wherein the local buffer is accessible by the producer component and a consumer component of the computing device, and (ii) add the data item to the remote buffer during ...

USING E-MAIL MESSAGE CHARACTERISTICS FOR PRIORITIZATION

Message prioritization may be provided. First, a message may be received and a priority level may be calculated for the message. If the message is not rejected for having a priority lower than a predetermined threshold, the message may be placed in a first priority queue. Next, the message may be de-queued from the first priority queue based upon the calculated priority level for the message. Distribution group recipients corresponding to the message may then be expanded and the priority level for the message may be re-calculated based upon the expanded distribution group recipients. Next, the message may be placed in a second priority queue. The message may then be de-queued from the second priority queue based upon the re-calculated priority level for the message and delivered. 1. A method for providing prioritization , the method comprising:receiving a message;calculating a priority level for the message;rejecting the message when the priority level is lower than a predetermined threshold;placing the message in a first priority queue;de-queuing the message from the first priority queue based upon the calculated priority level for the message;expanding distribution group recipients corresponding to the message;re-calculating the priority level for the message based upon the expanded distribution group recipients;placing the message in a second priority queue;de-queuing the message from the second priority queue based upon the re-calculated priority level for the message; anddelivering the message.2. The method of claim 1 , wherein receiving the message comprises receiving the message from an e-mail client.3. The method of claim 1 , wherein receiving the message comprises receiving the message from a message server.4. The method of claim 1 , wherein calculating the priority level for the message comprises calculating the priority level based upon direct characteristics of the message.5. The method of claim 1 , wherein calculating the priority level for the message ...

Transmitting data

A method comprises: initialising a value of an input transfer size parameter; initialising a value of a transfer data segment parameter; requesting data from a data source, the requesting using the value of the input transfer size parameter to indicate an amount of data requested; storing data received from the data source in a cache; using the value of the transfer data segment parameter to form a data segment from data stored in the cache; transmitting the data segment using multiple logical connections of a transfer path, each logical connection carrying a different part of the data segment; when it is confirmed that the data segment has been transmitted over the transfer path, deleting the data segment from the cache; measuring performance of transmission of data over the path using different values of the transfer data segment parameter and identifying a first optimum value of the transfer data segment parameter; whilst transmitting using the first optimum value of the transfer data segment parameter, measuring performance of transmission of data over the path using different values of the input transfer size parameter and identifying a first optimum value of the input transfer size parameter; whilst transmitting using the first optimum value of the input transfer size parameter, measuring performance of transmission of data over the path using different values of the transfer data segment parameter and identifying a second optimum value of the transfer data segment parameter; and requesting data from the data source using the first optimised value of the input transfer size parameter to indicate an amount of data requested and using the value of the second optimum value of the transfer data segment parameter to form data segments from data stored in the cache for transmission over the path.

PRIORITIZATION FOR A SET OF DATA SIGNALS BASED ON SKEW REQUIREMENTS

Examples herein disclose an identification of a set of skew requirements corresponding to a set of data signals. Based on the set of skew requirements, the examples prioritize an order of transmission for the set of data signals. The example queue the set of data signals in accordance with the prioritized order. 1. A method executable by an integrated circuit , the method comprising:identifying a set of skew requirements corresponding to a set of data signals;based on the set of skew requirements, prioritizing an order of transmission for the set of data signals; andqueueing the set of data signals in accordance with the prioritized order,wherein a data signal corresponding to a lower skew requirement is a higher ordered priority than a skew-tolerant data signal.2. (canceled)3. The method of claim 1 , comprising:transmitting the set of data signals in a serial manner based on the prioritized order.4. The method of claim 1 , comprising:modifying a bit in the set of data signals corresponding to the set of skew requirements; andsetting a parity bit in the set of data signals prior to transmission.5. The method of claim 1 , comprising:receiving a different set of data signals;identifying the set of skew requirements corresponding to the different set of data signals, wherein the set of skew requirements includes a lower skew requirement; andqueuing the different set of data signals in a higher priority than previously queued skew-tolerant signals.6. The method of claim 1 , wherein identifying the set of skew requirements corresponding to the set of data signals comprises:classifying each data signal in the set of data signals according to the set of skew requirements.7. A system comprising: prioritize an order to a set of data signals based on a set of skew requirements corresponding to the set of data signals such that a lower skew data signal in the set of data signals is higher in priority than a skew-tolerant data signal;', 'queue the set of data signals in ...

DATA PROCESSING METHOD AND DEVICE

Embodiments of the present disclosure provide a data processing method and a device. The method includes: determining, by a controller, a data packet filtering rule and a data forwarding path; sending, by the controller, the data packet filtering rule and configuration information carrying the data forwarding path to a first node, where the filtering rule is used to match configuration information corresponding to a data packet of the first node, the configuration information includes routing information corresponding to each node in the data forwarding path, routing information includes a queue identifier which is used to identify a transmission queue to which the data packet belongs; forwarding, by the first node and a remaining node, the data packet. 1. A data processing method , comprising:determining, by a controller, a data forwarding path used for data packet transmission between user equipment and a core network; the filtering rule is used to match configuration information corresponding to a data packet of the first node,', 'the configuration information comprises routing information corresponding to each node in the data forwarding path,', 'routing information corresponding to any node in the data forwarding path comprises a queue identifier allocated by the controller to the data packet, and', 'the queue identifier is used to identify a transmission queue to which the data packet belongs., 'sending, by the controller, a data packet filtering rule and configuration information carrying the data forwarding path to a first node in the data forwarding path, wherein2. The method according to claim 1 , wherein when the data forwarding path is used for the first time to forward the data packet or the data forwarding path changes claim 1 , the routing information corresponding to the any node in the data forwarding path further comprises:an identifier of a node next to the any node and scheduling information of the transmission queue on the any node.3. The method ...

SYSTEM AND METHOD FOR AVOIDING DISEQC CONFLICTS

Method for avoiding DiSEqC conflicts in a receiver connected to a coaxial cable wherein the receiver utilizes the Unicable communication, the method being characterized in that it comprises the steps of: obtaining a list of an identified group of receivers, the group being organized according to an identified order; using a second communication channel () to communicate with at least one other receiver from said identified group; receiving a token over the second communication channel (); transmitting a DiSEqC command over the Unicable bus only when said token has been received; after executing said DiSEqC command (), transmitting said token, over the second communication channel (), to the next receiver identified by said order. 1. Method for avoiding DiSEqC (Digital Satellite Equipment Control) conflicts in a receiver connected to a coaxial cable wherein the receiver utilizes the Unicable communication , the method being characterized in that it comprises the steps of:obtaining a list of an identified group of receivers, the group being organized according to an identified order;{'b': '102', 'using a second communication channel () to communicate with at least one other receiver from said identified group;'}{'b': '102', 'receiving a token over the second communication channel ();'}transmitting a DiSEqC command over the Unicable bus only when said token has been received;{'b': 405', '102, 'after executing said DiSEqC command (), transmitting said token, over the second communication channel (), to the next receiver identified by said order.'}2313. The method according to claim 1 , characterized in that the receiver operates an application () configured to request a channel change for a tuner device wherein said request has an associated priority.3. The method according to claim 2 , characterized in that channel change requests for tuners used for live television have a higher priority than requests for tuners used for recording or other background data collecting ...

ASYNCHRONOUS FEEDBACK TRAINING

Systems, apparatuses, and methods for implementing asynchronous feedback training sequences are described. A transmitter transmits a training sequence indication to a receiver via a communication channel including a plurality of data lines. The training sequence indication includes a bit sequence to indicate the beginning of a training sequence. The indication includes a transition from a zero to a one at the midpoint of a supercycle of ‘N’ clock cycles in length, followed by a predetermined number of ones. The training sequence indication is then followed by a test pattern. The beginning of the test pattern occurs at the end of a supercycle. The receiver determines if there are any errors in the received test pattern, and then sends feedback to the transmitter that indicates whether any errors were detected. Responsive to receiving the feedback, the transmitter alters delay settings for one or more of the data lines. 1. A system comprising:a transmitter; anda receiver coupled to the transmitter via a communication channel including one or more data lanes;wherein the transmitter is configured to transmit a training sequence indication followed by a test pattern on a first lane of the channel; and receive the training sequence indication and the test pattern; and', 'convey an error indication to the transmitter via the first lane that indicates whether any errors were detected in the test pattern., 'wherein the receiver is configured to2. The system as recited in claim 1 , wherein responsive to receiving the error indication claim 1 , the transmitter is configured to change a delay setting for the first lane if the error indication indicates an error was detected.3. The system as recited in claim 1 , wherein the receiver is configured to capture the test pattern responsive to detecting the training sequence indication.4. The system as recited in claim 3 , wherein:the transmitter is configured to transmit the training sequence indication as a plurality of bits during ...

Traffic manager for network switch port

A traffic manager for a network switch input or output port stores incoming cells in a cell memory and later sends each cell out of its cell memory toward one of a set of forwarding resources such as, for example, another switch port or an output bus. Data in each cell references the particular forwarding resource to receive the cell. Each cell is assigned to one of several flow queues such that all cells assigned to the same flow queue are to be sent to the same forwarding resource. The traffic manager maintains a separate virtual output queue (VOQ) associated with each forwarding resource and periodically loads a flow queue (FQ) number identifying each flow queue into the VOQ associated with the forwarding resource that is to receive the cells assigned to that FQ. The traffic manager also periodically shifts an FQ ID out of each non-empty VOQ and forwards the longest-stored cell assigned to that FQ from the cell memory toward its intended forwarding resource. The traffic manager separately determines the rates at which it loads FQ IDs into VOQs and the rates at which it shifts FQ IDs out of each non-empty VOQ. Thus the traffic manager is able to separately control the rate at which cells of each flow queue are forwarded and the rate at which each forwarding resource receives cells.

ATM switch

An ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input cell and switches cells to an output port in an ascending order of the time information. In addition, the ATM switch includes a cell distribution part in the basic switch of the first stage. The cell distribution part determines a routes of a cell to be transferred such that loads of routes within the ATM switch are balanced. The ATM switch further includes an adding part which adds arriving time information to an arriving cell as the time information.

Ａｔｍスイッチ用の分散形バッファリング・システム

(57)【要約】 （修正有） 【課題】 より高い性能のために分散されたバッファリ ングを有し、より大きな設計のモジュール化を可能とす るＡＴＭスイッチを提供する。 【解決手段】 ＡＴＭスイッチは、各々が入力、出力チ ャネルに接続した複数の入力、出力ポート２３，２４ と、その間に接続したスイッチ・ブロック２５と、バッ クプレッシャ信号回路とを有する。入力ポートは、入力 ポートが伝送できるよりも早く入力チャネルから到達し たセルを保持する入力バッファ２１を有し、出力ポート は、出力ポートが伝達できるよりも早くスイッチ・ブロ ックからセルが到達したときにセルを保持する出力バッ ファ２２を有する。バックプレッシャ信号回路は、混雑 している出力バッファから信号を送り、入力ポートのバ ッファに伝送を停止させ、出力バッファに予定されるセ ルを入力ポート・バッファに記憶する。

Cell rearrangement buffer

본 발명은 비동기전송모드 교환기의 셀 처리장치에 관한 것으로, 스위칭 망을 통해 수신되는 셀의 헤더에 포함된 지연 값에 따른 실제지연과 초기화에 의해 결정된 최대지연 및 기반주소를 이용하여 셀 저장 주소를 생성하며, 기반주소를 초기 값으로 설정한 후 셀 타임 클럭에 의해 순환하여 결정하고, 셀 저장 주소와 기반주소를 셀 타임 클럭에 의해 번갈아 출력함으로서 셀 저장 주소에 의해 메모리 할당 맵과 셀버퍼 메모리에 유효 셀 정보와 셀이 입력되도록 하며, 기반주소에 의해 출력되도록 하는 셀 재배열 버퍼를 구현하였다. The present invention relates to a cell processing apparatus of an asynchronous transmission mode switch, wherein a cell storage address is obtained by using a real delay according to a delay value included in a header of a cell received through a switching network and a maximum delay and base address determined by initialization. After the base address is set to the initial value, it is cyclically determined by the cell time clock, and the cell storage address and the base address are alternately output by the cell time clock to output the memory allocation map and the cell buffer memory. A cell reordering buffer is implemented that allows valid cell information and cells to be inputted and outputted by the base address.

An atm switch queuing system

본 발명은 임계시간 동안의 지연을 방지하기 위하여 버스티 트래픽의 셀손실을 최소화한 교환 큐잉 시스템을 갖는 ATM 교환망을 제공하기 위한 것이다. 교환망은 복수개의 입력포트와, 복수개의 출력포트와, 입력포트에서 출력포트로 셀을 전송하기 위한 교환구조부와, 각 출력포트의 각 출력버퍼와 각 입력포트의 각 입력버퍼간의 연결을 수행하는 백프레서 제어부를 구비한다. 각 입력포트는 입력포트의 전송보다 더 빨리 셀이 상기 입력채널로부터 입력되면 셀을 저장하는 입력버퍼를 구비하며, 복수개의 우선순위 레벨로 입력버퍼로부터 셀을 전송한다. 또한 각 출력포트는 셀이 출력포트의 전송보다 더 빨리 셀이 상기 입력포트로부터 입력되면 셀을 저장하는 출력버퍼를 구비하며, 복수개의 우선순위 레벨로 출력버퍼로부터 셀을 전송한다. 이러한 방법으로 셀 우선순위 레벨보다는 기본적인 연결 상태에서 셀을 전송할 수 있으며, 종래의 다른 유저들보다 폭주유발 데이터의 송신을 피할 수 있게 되는 것이다. The present invention is to provide an ATM switching network having an exchange queuing system in which cell loss of bursty traffic is minimized in order to prevent delay during a critical time. The exchange network includes a plurality of input ports, a plurality of output ports, an exchange structure for transferring cells from the input port to the output port, and a back-up structure for connecting between each output buffer of each output port and each input buffer of each input port. And a presser control unit. Each input port has an input buffer for storing cells when a cell is input from the input channel earlier than an input port, and transmits cells from the input buffer at a plurality of priority levels. Each output port also has an output buffer for storing cells when a cell is input from the input port earlier than a transmission of an output port, and transmits cells from the output buffer at a plurality of priority levels. In this way, the cell can be transmitted in a basic connection state rather than the cell priority level, and transmission of congestion-inducing data can be avoided more than the conventional users.

Atm switch address generating circuit

본 발명은 서비스 클래스마다 논리적으로 셀 버퍼를 분할하여 관리하는 것으로, 1개의 LSI에서 복수에 서비스 클래스를 서포트하는 것이 가능한 ATM 스위치의 어드레스 생성 회로를 제공하는 것을 과제로 한다. SUMMARY OF THE INVENTION An object of the present invention is to logically divide and manage a cell buffer for each service class, and to provide an address generation circuit of an ATM switch capable of supporting a plurality of service classes in one LSI. 본 발명은 ATM(비동기 전송 모드) 교환 시스템에서의 공유 버퍼형의 ATM 스위치의 어드레스 생성 회로에 있어서, 공유 버퍼에 격납되어 있는 셀의 출력 포트를 나타내는 수신측 정보, 어드레스, 서비스 클래스 나타내는 클래스 정보가 격납되어 이루어진 어드레스 생서 유닛(5)을 복수 구비하고, 공유 버퍼에 대한 셀의 입출력시에는 셀의 클래스 정보와 일치하는 클래스 정보가 격납되어 있는 어드레스 생성 유닛(5)의 수신측 정보 및 어드레스가 선택되어 사용되도록 구성된다. In the address generation circuit of a shared buffer type ATM switch in an ATM (Asynchronous Transfer Mode) switching system, the receiver side information indicating the output port of a cell stored in the shared buffer, the address, and the class information indicating the service class are provided. The receiving side information and the address of the address generation unit 5 which are provided with a plurality of address generator units 5 which are stored, and which class information matching the class information of a cell are stored at the time of input / output of a cell with respect to a shared buffer are selected. It is configured to be used.

パケット通信方法

(57)【要約】 【課題】 共有バッファメモリを有するマルチポートノ ードが、サービスコミットメントのグレードを維持しな がら、確立されたＶＣに高いパケットバッファリング容 量を提供する。 【解決手段】 ポートを通じて確立されたＶＣに対して 判定された有効メモリ要求量に基づいて、それぞれのポ ートに対して、共有バッファメモリの仮配分を行う。次 に、予約されたバッファ量を考慮して、パケットをバッ ファリングするために現在使用されていないほぼ全部の 利用可能なバッファメモリに基づいて、目的の出力ポー トを通じて運搬するために、確立されているＶＣの入力 パケットを受け付けるかどうかを評価する。予約バッフ ァ量は、入力パケットの受付により、そのポートに対す る仮配分メモリが過負荷あるいは負荷不足になるかに基 づく（および、オプションとして、入力パケットの優先 レベルに基づく）。

The method and system of a kind of shared audio frequency and/or video

本发明公开了一种共享音频和/或视频的方法，其特征在于，该方法包括：第一终端根据第二终端的播放请求，将来自音视频提供模块的音频和/或视频写入缓存空间，并将所述缓存空间中存储的音频和/或视频发送给所述第二终端。本发明还相应地公开了一种共享音频和/或视频的系统。通过本发明，移动终端的视频会议可以实时的在数字家庭网络终端上体现出来，从而可以使得不支持视频会议的数字终端也可以看到视频内容，并且，一个正在开着视频会议的手机终端回到家里，可以很方便的把图像切换到电视终端上，而不用再拿着手机，从而提高用户体验。

Asynchronous feedback training

Subscriber atm mux for interface to isdn

several input buffers(1) temporarily storing input cells from several input lines, a cell recognition circuit(2) classifying the input cell data according to the QOS of each. Some criteria of the QOS include the connection setting data and header data. The cells are stored in a buffer circuit(3) according to the QOS grade. A ring order data circuit(4) outputs a cell out of the network. A ring order data controller(5) facilitates transfer of data between the cell recognition circuit and from the QOS grade buffer circuit to control the transmission of cell data from the ring order data circuit. A connection state control circuit(6) connects a user interface(7) and a signal processing circuit(8) to the network.

Apparatus for the con of hardware component of concentrated b-nt system

A apparatus for controlling the hardware of the broadband network terminal(B-NT) system where controls the hardware executing situation of the physical layer, the ATM Layer and the inner communication processor; communicates with the system controller where controls the transaction of the protocol and calling.

Atm switch

(57)【要約】 【課題】 ディジタル通信ネットワークのＡＴＭスイッ チが、多くの異なる適用と目的のために広範囲のクラス のスケジューリングアルゴリズムを実行することが出来 る。 【解決手段】 待ち合わせシステムは、優先順位により 構成されたＡＴＭスイッチを有するタグ方式の主待ち行 列７０と、伝送がまだスケジューリングされないＡＴＭ セルを有し、かつ、仮想チャネルにより構成されている 副待ち行列７４とを備える。待ち合わせ決定モジュール ７２は、入信するＡＴＭセルがどの待ち行列に配置され るべきかを決定する。再待ち合わせ決定モジュール７８ は、個々の仮想チャネルをブロック化しない事象が起こ ると動作する。 【効果】 ブロック化及び非ブロック化されたチャネル の流れを制御することができる。

Address generating circuit of ATM switch

본 발명은 서비스 클래스마다 논리적으로 셀 버퍼를 분할하여 관리하는 것으로, 1개의 LSI에서 복수에 서비스 클래스를서포트하는 것이 가능한 ATM 스위치의 어드레스 생성 회로를 제공하는 것을 과제로 한다. 본 발명은 ATM(비동기 전송 모드) 교환 시스템에서의 공유 버퍼형의 ATM 스위치의 어드레스 생성 회로에 있어서, 공유 버퍼에 격납되어 있는 셀의 출력 포트를 나타내는 수신측 정보, 어드레스, 서비스 클래스 나타내는 클래스 정보가 격납되어이루어진 어드레스 생서 유닛(5)을 복수 구비하고, 공유 버퍼에 대한 셀의 입출력시에는 셀의 클래스 정보와 일치하는 클래스 정보가 격납되어 있는 어드레스 생성 유닛(5)의 수신측 정보 및 어드레스가 선택되어 사용되도록 구성된다.

Device for controlling hardware of centralized broadband network termination system (B-NT)

중앙처리장치(26) 및 그 주변장치를 포함하는 장치에 있어서, 이중 포트램(30); VME버스 제어수단(31); 인터럽트 제어수단(32); 신호/OAM셀 수신수단(39); 경보상태 처리수단(38); 보드착탈 감시수단(37); 상태인식 레지스터수단(33); 상태제어 레지스터수단(34); 및 공통버스 제어수단(36)을 구비하는 것을 특징으로 하는, 집중형 광대역 망 종단(B-NT)시스템의 하드웨어를 제어하기 위한 장치.

Method and apparatus for providing work-conserving properties in a non-blocking switch with limited speedup independent of switch size

A switching method and apparatus operates as a work conserving network device. An arbiter using an arbitration algorithm controls a switch fabric interconnecting input ports and output ports. To switch cells, a virtual output queue of an input port is selected that corresponds to an output port with a lowest occupancy rating and a request is sent to this output port. In a greedy version of the algorithm, input ports may send requests to the lowest occupied output port for which they have a cell. In a non-greedy version, requests may only be sent if that input port has a cell for the lowest occupied output port in the entire network device. An output port that receives one or more requests from input ports uses an input port selection algorithm to select an input port from which to receive a packet. After as many input and output ports are matched as is possible in a phase, the packets for those matched ports are transferred across the switch. The switch fabric operates with a speedup of only twice that of the input port data rates and is still work conserving.

Device and method of processing of elements of data on mode of asynchronous transmission in system of commutation of mode of asynchronous transmission

FIELD: radio engineering. SUBSTANCE: invention can be used in subscriber's switchboard in system of commutation of mode of asynchronous transmission. System of commutation of mode asynchronous transmission has unit of commutation of elements of data having at least one port of switch for sending of asynchronous transmission of elements of data and subscriber's switchboard having collection of subscriber ports. Device processing elements of data used in system of commutation of mode of asynchronous transmission has conversion storage to store controlling information to determine necessity of copying of element of data from port of switch and controller to copy element of data from port of switch and to send copied elements of data to subscriber ports in agreement with controlling information stored in conversion storage. If element of data is element for transmission from one point to another one then system of commutation of mode of asynchronous transmission transforms heading included in element of data in correspondence with controlling information and sends element of data with transformed heading to one subscriber port as minimum. But if element of data is element for transmission from one point to collection of points then system of commutation of mode of asynchronous transmission selects subscriber ports on basis of transformed heading and sends element of data which heading is allotted to selected subscriber ports. EFFECT: provision for sending asynchronous transmission of elements of data copied from one signal source to subscriber ports without interruption of usage of copied elements of data, processing of elements of data when one element of data is sent to one subscriber port on condition that routing information based on transformation with usage of heading is not provided. 13 cl, 7 dwg, 2 tbl УСОУСТС ПЧ ГЭ РОССИЙСКОЕ АГЕНТСТВО ПО ПАТЕНТАМ И ТОВАРНЫМ ЗНАКАМ (19) (51) МПК ВИ” 2134 024‘ 13) Сл Н 041 12/56 12) ОПИСАНИЕ ИЗОБРЕТЕНИЯ К ПАТЕНТУ ...

Path designation switch for digital signal two-way transmission

(57)【要約】 （修正有） 【課題】 ＡＴＭスイッチおよびシステムにとくに応用 できる経路指定スイッチを改良する。 【解決手段】 入力ポートおよび出力ポートに選択的に 接続できるバッファ回路と、入出力ポート間の選択的接 続を決定する制御回路３９，４０，４１を有し、制御回 路は、制御ビットを持つデジタル信号のデータセルを各 々含むビットフレームを備えるメッセージプロトコルを 動作させ、かつ、各入力セルの制御ビットから（ｉ）ど の１つの出力ポートまたは複数の出力ポートをそのセル のために使用するかの経路識別子と、（ｉｉ）選択され た出力ポートにおいてどの待ち行列が求められるか、 （ｉｉｉ）ビットフレーム源における輻輳を指示する任 意の流れ制御指示を行う。

Cell switch

내용 없음. No content.

Dynamic reservation wireless access scheme using common queue in ATM network

본 발명은 무선 ATM망에서 무선구간에서의 각 단말의 분산 시스템으로 인한 서비스의 불균등성(Unfairness)을 해결하고 무선 서비스의 질을 향상시키기 위한 공통큐를 이용한 동적예약 무선 액세스 방법에 관한 것으로, 기지국에서 이동국으로부터 전달되는 버퍼길이 파라미터를 이용한 하나의 공통큐를 도입하여 동적 예약을 수행하는 방법이다. 본 발명은, NQ와 대응하여 토큰을 저장하는 별도의 공통큐(CQ)를 구성하고, 패킷의 MVCI(MVC Identifier)를 실은 토큰을 상기 하나의 공통큐(CQ)에 저장하고, 프레임 시작에서 상기 공통큐(CQ)에 저장된 토큰이 서비스되어 해당 토큰의 MVCI를 지닌 상기 NQ의 패킷 정보를 RQ로 전달하도록 함으로써, 상기 공통큐(CQ)를 이용하여 상향링크의 동적 할당을 수행한다. The present invention relates to a dynamic reservation wireless access method using a common queue for solving the unfairness of services due to the distributed system of each terminal in the wireless section in the wireless ATM network and improving the quality of the wireless service. A dynamic reservation is performed by introducing a common queue using a buffer length parameter transmitted from a mobile station. The present invention configures a separate common queue (CQ) for storing tokens corresponding to NQ, stores a token carrying MVCI (MVC Identifier) of a packet in the one common queue (CQ), and starts the frame at the beginning of the frame. The token stored in the common queue (CQ) is serviced to transmit packet information of the NQ having the MVCI of the corresponding token to the RQ, thereby performing uplink dynamic allocation using the common queue (CQ). 본 발명에서는 기존의 동적예약시에 사용되는 하나의 파라미터만 이용하며, 복잡한 알고리즘의 적용없이 단순한 하나의 큐만 사용함으로써 기지국에서 이로 인한 제어 부하나 자원 소모는 거의 없으며, 동종 혹은 이종의 트래픽을 가진 각 MVC에 대해 무선 구간의 분산 환경으로 인해 발생될 수 있는 불평등성을 해결함으로써 무선 ATM의 트래픽 제어 개념을 유선 ATM과 유사한 환경으로 취급할 수 있게 되는 부가적인 효과도 가진다. In the present invention, only one parameter used in the existing dynamic reservation is used, and by using only a single queue without applying a complicated algorithm, there is almost no control load or resource consumption caused by the base station. By solving the inequality that may be caused by the distributed environment of the wireless section for MVC, there is an additional effect that the traffic control concept of the wireless ATM can be treated as an ...

apparatus for receiving of asynchronous data having automatic receive mode

본 발명은 큰 비동기 데이터의 수신에서 여러 개의 패킷 데이터로 나누어 연속해서 수신되는 각각의 패킷데이터를 재구성하는 일을 하드웨어적으로 자동화하기 위한 것으로서, 비동기 패킷 데이터 및 등시성(isochronous) 데이터를 출력하는 링크 코어부와, 상기 링크 코어부에서 수행된 컨피규레이션 정보를 저장하는 메모리와, 상기 링크 코어부에서 연속해서 출력되는 비동기 패킷 데이터를 기 설정된 블록 크기만큼 수신하고 결합하여 비동기 블록 패킷 데이터를 생성하는 자동 수신부와, 상기 자동 수신부에서 출력된 비동기 블록 패킷 데이터를 저장하는 버퍼부와, 상기 버퍼부에서 저장된 비동기 패킷 데이터를 읽어 호스트로 전달하거나 호스트로부터의 제어에 따라 상기 저장된 컨피규레이션 정보를 참조하여 비동기 블록 데이터를 전송하는 호스트 인터페이스부를 포함하여 구성되어, 연속되는 각 패킷 데이터의 수신을 각각 처리하지 않고 한 블록으로 데이터를 결합한 후에 처리함으로써 호스트 프로세서의 부담을 덜어 줄 수 있다.

Broadcast control apparatus of shared buffer type atm switch

본 발명은 공유 버퍼형 ATM 단위 스위치에서의 방송 제어 장치에 관한 것으로, 다중화기와 컨트롤 로직을 이용하여 방송 주기일때 출력해야 할 방송셀이 없는 단자에서는 일반셀을 출력하는 방송제어 장치를 제공하기 위하여, 전체 방송 경로 정보를 저장하는 방송 경로 저장 수단(21); 방송 경로 정보를 출력 주기가 될때까지 저장하는 방송 경로 버퍼링 수단(24); 방송셀의 주소를 출력하는 방송 주소 버퍼링 수단(26); 주소를 입력받아 제어신호에 따라 다중화하는 제2다중화 수단(23); 주소를 입력받아 상기 방송 경로 버퍼링 수단(24)의 제어 신호에 따라 다중화하는 제1다중화 수단(25); 및 상기 제2다중화 수단(23)에 제어 신호를 출력하는 제어 수단(22)을 구비하여 방송 주기에도 방송 출력이 없는 단자에 대해서는 주소 버퍼(4)에 저장된 일반셀을 출력할 수 있도록 함으로써 전체 스위치의 수율을 향상시키는 효과가 있다. The present invention relates to a broadcast control device in a shared buffer type ATM unit switch. In order to provide a broadcast control device for outputting a general cell at a terminal having no broadcast cell to be output during a broadcast period using a multiplexer and control logic, Broadcast path storage means (21) for storing full broadcast path information; Broadcast path buffering means (24) for storing broadcast path information until an output period is reached; Broadcast address buffering means (26) for outputting an address of a broadcast cell; Second multiplexing means (23) for receiving an address and multiplexing according to a control signal; First multiplexing means (25) for receiving an address and multiplexing according to a control signal of the broadcast path buffering means (24); And a control means 22 for outputting a control signal to the second multiplexing means 23 so as to output a general cell stored in the address buffer 4 for a terminal having no broadcast output even in a broadcast period. It is effective to improve the yield.

Cell-discarding method

(57)【要約】 【課題】 ＡＴＭＮＩＣがリアルタイムに動作してい る間に、再編成バッファにオーバーフローが発生する場 合に受取ったＡＴＭセルを取り捨ててＱＯＳを向上させ るるＡＴＭセル取捨て方法を提供する。 【解決手段】 複数のエントリよりなる、フリーバッ ファリングをセットアップし、リアルタイムサービスを 要するセルが入力されると、フリーバッファリング内に 存在するヘッドポインタの値とテールポイントの値とを 比較して、一致しないと、テールポインタが指すバッフ ァに受け取ったセルを格納し、そうでないと、ヘッドポ インタの値を１だけ増加させ、最初に受け取ったセルは 取り捨て、最後に受け取ったセルはテールポインタが指 すバッファに格納し、テールポインタの値を１だけ増加 させる。

Atm cell processor

(57)【要約】 【課題】ＡＴＭセル処理装置に適用する、大容量セルバ ッファを構成する。 【解決手段】ＡＴＭセル処理装置のフレーム組立部のフ レーム組立バッファにＤＲＡＭを使用する。ＤＲＡＭア クセスのアクセス速度の異方性を吸収するため、常時に ＤＲＡＭアクセスのランダムアクセスモードを使用し、 この場合のアクセス速度の低下を補うために、ＤＲＡＭ をアレー状に配置し、セルを分割して各ＤＲＡＭにそれ ぞれ順番に書き込み、読み出しを行う。ＤＲＡＭを用い て高速で大容量のセルバッファを構成することが出来 る。本セルバッファはＦＩＦＯなどにも適用できる。

Atm traffic control apparatus and method

에이티엠 트래픽을 제어하는 장치가, 다수개의 트래픽 소스들에 의해 발생되는 트래픽을 저장하여 출력하는 출력버퍼와, 트래픽 소스에 대응되는 수로 구비되고 각각이 뉴런 네트워크로서 설정 타임슬롯 구간 동안 수신된 셀들의 수를 적응적으로 학습하여 미래의 일정 타임슬롯 동안 도달할 셀들의 수를 예측한 미래의 예측 트래픽 값들을 발생하는 트래픽 예측기들과, 트래픽 예측기들에서 출력되는 각 예측 트래픽 값들을 합산한 값과 상기 출력버퍼의 유효 크기 및 설정 타임슬롯 동안 전송될 셀 수를 입력하여 출력버퍼의 호 폭주 발생 유무를 결정하며 호 폭주 결정시 미래의 설정 타임슬롯 구간동안 처리할 수 없는 셀들의 수를 출력하는 결정기와, 익스퍼트 시스템으로써 상기 각 트래픽 소스들의 서비스 레이트, 형태, 피크비트 레이트, 예측 트래픽 값 들과, 상기 호폭주 상태에서 처리할 수 없는 셀 수를 입력하여 각 트래픽 소스들의 최적의 전송속도를 계산하여 상기 출력버퍼의 폭주를 제어하는 트래픽 제어기로 구성된다.

Method and system for sharing audio and/or video data

本发明公开了一种共享音频和/或视频的方法，其特征在于，该方法包括：第一终端根据第二终端的播放请求，将来自音视频提供模块的音频和/或视频写入缓存空间，并将所述缓存空间中存储的音频和/或视频发送给所述第二终端。本发明还相应地公开了一种共享音频和/或视频的系统。通过本发明，移动终端的视频会议可以实时的在数字家庭网络终端上体现出来，从而可以使得不支持视频会议的数字终端也可以看到视频内容，并且，一个正在开着视频会议的手机终端回到家里，可以很方便的把图像切换到电视终端上，而不用再拿着手机，从而提高用户体验。

Method of discarding atm cells in an atm nic

본 발명은 ATM 망접속기(NIC:Network Interface Card)에서 실시간 연결시 재조립 버퍼에 오버플로우(overflow)가 발생될 경우에 수신된 ATM 셀(Cell)을 폐기(discard)하는 방법에 관한 것이다. The present invention relates to a method of discarding a received ATM cell when an overflow occurs in the reassembly buffer during a real time connection in an ATM network interface card (NIC). 이러한 본 발명은 호스트시스템에서 운용되는 응용프로그램의 요구에 따라 ATM 망접속기 드라이버가 ATM 망접속기를 제어하여 데이터를 ATM 통신방식으로 전송하고, ATM 망접속기가 수신된 ATM 셀들을 프리버퍼 링의 엔트리가 가리키는 재조립 버퍼에 저장하여 패킷을 재조립하는 ATM 망접속기에 있어서, 헤드 포인터와 테일 포인터에 의해 저장될 셀들의 버퍼를 지시하는 엔트리들로 구성된 실시간 연결을 위한 프리버퍼 링을 설정하는 단계(100); 실시간 연결에 해당하는 패킷들의 셀이 수신되면 실시간 연결을 관리하기 위한 프리버퍼 링의 헤드 포인터와 테일 포인터를 비교하는 단계(101,102); 헤드 포인터와 테일 포인터가 일치하지 않으면 수신된 셀을 테일 포인터가 가리키는 버퍼에 저장하는 단계(104); 헤드 포인터와 테일 포인터가 일치하면 헤드 포인터 값을 1증가시켜 가장 오래된 셀을 폐기한 후, 수신된 셀을 테일 포인터가 가리키는 버퍼에 저장하는 단계(103,104); 및 테일 포인터값을 1증가시키는 단계(105)로 구성된다. According to the present invention, the ATM network connector driver controls the ATM network connector in accordance with the request of an application program operating in the host system, and transmits data in an ATM communication method. In an ATM network accessor for reassembling a packet by storing in a reassembly buffer that is indicated, setting up a prebuffer ring for a real-time connection consisting of entries indicating a buffer of cells to be stored by a head pointer and a tail pointer (100). ); Comparing (101, 102) a head pointer and a tail pointer of a prebuffer ring for managing a real-time connection when a cell of packets corresponding to the real-time connection is received; If the head pointer and tail pointer do not match, storing the received cell in a buffer pointed to by the tail pointer (104); If the head pointer and tail pointer coincide, increasing the head pointer value by 1 to discard the oldest cell, and then storing the received cells in a buffer indicated by the tail pointer (103, 104); And incrementing the tail pointer value by one (105).

Low delay or low loss switch for ATM

Test method for ATM multiplex transmission equipment

A marine multi-band network selection system

According to the present invention, a maritime multi-band network selection system in a maritime multi-band network system in which a plurality of ship stations and a plurality of ground stations perform maritime wireless communication comprises: a network selection server which implements a function for each module of network selection middleware, selects a required network among heterogeneous networks by using a network selection algorithm, and switches to the required network; a user interface which controls the network selection server in a plurality of transmission modes based on a transmission network ID, and monitors a state of real-time communication and a state of data buffered during network switching; and a network input/output interface which includes modems of the heterogeneous networks, sets link connections of the heterogeneous networks, and is embedded to construct interface input/output ports with the network selection server.

Asynchronous Transfer Mode Cell Multiplexing and Demultiplexing Devices

본 발명은 비동기식전송모드방식의 교환기에 있어서 비동기식전송모드 스위치의 한 입출력포트와 다수의 프로세서간의 정합이 가능하도록 비동기식전송모드 셀을 멀티플렉싱 및 디멀티플렉싱하는 장치를 제공하기 위한 것으로, 본 장치는 전송되는 ATM셀을 멀티플렉싱 및 디멀티플렉싱하는 장치에 구비되는 프로세서와 정합이 가능한 포트수와 동일한 수의 프로세서 링크 정합부, 송신용 버퍼, 수신용 버퍼, 해당 장치의 유지보수 및 초기화 등의 전기능을 제어하는 프로세서, 프로세서로부터 출력되는 ATM셀을 임시적으로 저장하는 송신용 버퍼, 프로세서로 인가할 ATM셀을 임시적으로 저장하는 수신용 버퍼, ATM스위치로부터 프로세서측으로 ATM셀을 전송할 때 이용될 수신용 버퍼에 대한 정보를 저장하는 메모리, 송신용 버퍼의 저장상태를 감시하여 ATM셀을 저장한 송신용 버퍼로부터 해당되는 ATM셀을 읽어 ATM스위치의 해당 입출력포트로 전송하고, ATM스위치의 입출력포트로부터 전송되는 ATM셀에 실려있는 VPI정보를 이용하여 메모리로부터 독출된 수신용 버퍼에 대한 정보를 참조하여 전송되는 ATM셀을 해당되는 수신용 버퍼로 전송하는 스위치 링크 정합부로 구성된다. 따라서 ATM 스위치의 입출력포트에 대한 프로세서의 점유도를 최소화하여 ATM스위치의 활용도를 향상시킬 수 있다. The present invention provides an apparatus for multiplexing and demultiplexing an asynchronous transfer mode cell to enable matching between an input / output port and a plurality of processors of an asynchronous transfer mode switch in an asynchronous transfer mode switch. It controls all functions such as processor link matching unit, transmitting buffer, receiving buffer, maintenance and initialization of the same device as the number of ports that can be matched with the processor included in the device for multiplexing and demultiplexing the ATM cell. Information on the processor, a transmission buffer that temporarily stores the ATM cells output from the processor, a reception buffer that temporarily stores the ATM cells to be applied to the processor, and a reception buffer to be used when transmitting the ATM cells from the ATM switch to the processor. Memory to monitor the status of the transmission buffer Reads the corresponding ATM cell from the transmission buffer that stores the cell and transmits it to the corresponding I / O port of the ATM switch, and reads from the memory using the VPI information contained in the ATM cell transmitted from the I / O port of the ATM switch. The switch link matching unit transmits the transmitted ATM cell to the corresponding receiving buffer with reference to the information. ...

Manufacture of electrode catalyst layer for fuel cell

(57)【要約】 【課題】 共通バッファを仮想的に個別バッファとして 使用できるように共通バッファの記憶制御を行なうこと により、バッファの容量を増大させることなく、又、バ ッファに対する読み出し制御を複雑化することなく、最 低帯域保証を実現できるようにする。 【解決手段】 複数の方路からの受信データを一時的に 記憶する各方路に共通な共通バッファ１の記憶制御を行 なうバッファ制御装置２において、受信データの方路を 識別する方路識別部３と、少なくとも受信データの共通 バッファ１内の記憶位置についての情報を上記方路別に 記憶する記憶部４と、方路識別部３での方路識別結果と 記憶部４の上記記憶位置についての情報とに基づいて受 信データを仮想的に共通バッファ１に方路別に記憶させ るための制御を行なう制御部５とをそなえるように構成 する。

Atm cell buffering method

본 발명은 입력 셀 버퍼링을 DPRAM(Dual Port RAM)을 이용하여 셀의 라이트 포인트를 임의로 지정한다. 온전하지 않은 셀이 입력될 경우 다음 셀의 라이트 포인트를 다시 처음으로 가져감으로써 불필요한 셀을 소거한다. 또한 동일하게 번들된 포트간의 셀 도착 지연 차이를 보상할 수 있도록 하는데 이는 번들된 포트들중 하나의 포트를 기준으로 하여 기준 포트로 입력되는 셀 도착시간으로부터 지정된 시간내에 도착된 셀들을 동일한 도착 시간을 갖는 셀로 간주한다. The present invention arbitrarily designates a write point of a cell by using dual port RAM (DPRAM) for input cell buffering. When an incomplete cell is input, unnecessary cells are erased by bringing the write point of the next cell to the beginning again. In addition, it is possible to compensate for the difference in cell arrival delay between identically bundled ports. It is considered to have a cell. ATM스위치, 입력 셀 버퍼링, 공유 버퍼형, DPRAM ATM Switch, Input Cell Buffering, Shared Buffer Type, DPRAM

Data output buffer control apparatus in atm switch

본 발명은 비동기식 전송모드 교환기의 데이타출력버퍼 제어장치에 관한 것으로, 데이타 출력버퍼에 임계치를 복수개 두어 버퍼에서 대기중인 셀의 양에 따라 입력가능한 저우선순위 셀의 수를 유동적으로 조절해 줌으로써 시간적으로 불확실한 변동을 가지는 트래픽에 대해 고우선순위 셀이 돌발적으로 폐기되는 확률을 현저히 감소시키며, 또한 사용자의 서비스 등급 요구조건을 만족시켜 주기 위해 필요한 데이터 버퍼의 크기를 작게 할 수 있어서 망자원을 경제적으로 이용할 수 있는 장점이 있다. The present invention relates to a data output buffer control apparatus of an asynchronous transfer mode switch, wherein a plurality of thresholds are placed in the data output buffer, and the number of subpriority cells that can be inputted in accordance with the amount of cells waiting in the buffer is controlled in time. It can significantly reduce the probability of accidentally discarding high priority cells for fluctuating traffic, and can reduce the size of the data buffer needed to meet the user's service class requirements. There is an advantage.

Temporary information storage system

FIELD: computer technology. SUBSTANCE: system includes buffer storage for recording data block, data inputs and outputs structurized in data blocks at constant or varying length, set of waiting lines connected data blocks recorded in buffer storage, as well as waiting line control logic. Waiting line control logic of data blocks and output selection includes waiting line which is assigned to each output; each output waiting line is connected with input of data block depending on indexing of output data in data block and buffer memory for identification of cell in buffer memory; each waiting line is connected with data outputs by means of output selection device; one data output which requests transmitted data block is connected with selection device of data block and with output selection device by means of line connected with output waiting line. EFFECT: possibility of balancing information transmission at different outputs and ensuring random selection. 17 cl, 10 dwg су гс ПЧ ГЭ РОССИЙСКОЕ АГЕНТСТВО ПО ПАТЕНТАМ И ТОВАРНЫМ ЗНАКАМ ЗВО“” 2138 845 ' (51) МПК 13) С1 С 06Е 9/00, Н ОДЕ 5/22 12) ОПИСАНИЕ ИЗОБРЕТЕНИЯ К ПАТЕНТУ РОССИЙСКОЙ ФЕДЕРАЦИИ (21), (22) Заявка: 5001555/09, 30.08.1991 (24) Дата начала действия патента: 30.08.1991 (30) Приоритет: 31.08.90 (30) Приоритет: 31.08.1990 ЕК 9010877 (46) Дата публикации: 27.09.1999 (56) Ссылки: ЕК 2623954 АЛ, 02.06.89. ЗЦ 537386 А, 30.11.76. 5Ц 980159 А, 07.12.82. (98) Адрес для переписки: 103735, Москва, ул.Ильинка 5/2, Союзпатент, пат.пов.Емельянову Е.И. (71) Заявитель: Алькатель Н.В. (МГ) (72) Изобретатель: Мишель Энрион (ЕК) (73) Патентообладатель: Алькатель Н.В. (МГ) (54) СИСТЕМА ВРЕМЕННОГО ЗАПОМИНАНИЯ ИНФОРМАЦИИ (57) Реферат: Изобретение относится к вычислительной технике. Его использование для временного запоминания информации позволяет создать систему, способную уравновешивать передачу информации на различных выходах и одновременно обеспечивать их случайный выбор. Система содержит буферную память для записи блока ...

A circuit for controlling the state of sscop sublayer

A state control circuit for SSCOP is provided, whichd includes a state storing unit(10) for storing transmission control state of SSCOP; a state variable storing unit(18) for storing certain state variables; a state control processing unit(12) for reading state from the state storing unit(10) according to input signal from SSCF(50) to output several control signal, for writing exchanged state to the state storing unit(10) and for outputting several signals which control certain operation of SSCOP layer; a timer(14) for detecting non-response state; a CPU(16) for initializing entire circuit of SSCOP.

An input queuing system for connecting to the inputs of a space division switching matrix.

Apparatus and method for allocating time slot using fifo(first in first out) memory

본 발명은 다수개의 선입선출 메모리를 이용한 타임슬롯 할당장치 및 방법에 대한 것으로서, 입력되는 ATM 셀을 분석하여 해당하는 타임슬롯의 유형을 판단하고 ATM 셀을 출력하는 ATM 셀 분석부와, 타임슬롯 할당정보를 저장하는 타임슬롯 할당 테이블, 각각 하나의 타임슬롯 유형에 해당하는 ATM 셀들을 저장하기 위한 다수개의 선입선출 메모리들로 구성되며 ATM 셀 분석부로부터 출력된 ATM 셀을 다수개의 선입선출 메모리들 중 해당하는 타임슬롯 유형의 선입선출 메모리에 저장하는 선입선출 메모리부 및 타임슬롯 할당정보를 참조하여 다수개의 선입선출 메모리들 중 현재 전송되는 타임슬롯에 해당하는 타임슬롯 유형의 선입선출 메모리로부터 읽어낸 ATM 셀을 프레임화하여 출력하는 상향 프레이머를 포함한다. 이로써 본 발명은, 무작위로 들어오는 입력 셀들에 대해 별다른 지연 요소없이 상향 프레임을 지속적으로 전송할 수 있으며 셀들이 저장되는 메모리상의 주소를 처리하는데 발생되는 시간지연의 문제를 해결할 수 있다. [색인어] TDMA, 타임슬롯 할당

ATM switch

Dynamic queue length thresholds in a shared memory atm switch

공유 메모리 ATM 교환기에 있어서 상이한 출력 큐들 사이에 메모리를 할당하기 위한 동적 임계 시스템 및 방법이 기재되어 있다. 임의 시점에 임의의 개별 큐에 대해 최대한 허용가능한 길이는 교환기 내의 사용되지 않은 버퍼링 함수이다. 동적 임계 시스템 및 방법은 소량의 버퍼 공간을 의도적으로 마련하여, 이것을 현재 활성 상태인 소정의 출력 큐에 할당하는 것이 아니라, 현재 활성 상태인 출력 포트들 사이의 나머지 버퍼 공간을 균등하게 공유하게 한다. 동적 임계 시스템 및 방법은 모든 출력 큐에 대한 버퍼 공간에 대한 액세스를 보증하고, 임의의 단일 출력 큐를, 다른 것을 희생시켜 메모리를 독점하는 것으로부터 보호함으로써 공평성 및 교환기 효율을 개선한다. 동적 임계 시스템 및 방법은 불확실하거나 변화하는 부하 상태에 적용된다. 동적 임계 시스템에서 발생하는 패킷 손실은 ATM 시스템에 필요한 소수의 큐에 집중되는 경향이 있는데, 그 이유는 상위 프로토콜층에 방해되는 메시지가 거의 발생하지 않으므로, 메시지를 재송신할 필요가 거의 없기 때문이다. 또한, 동적 임계 시스템 및 방법은 다중 공간 우선 순위를 갖는 트래픽을 처리하기 위해 연장될 수 있다. A dynamic threshold system and method for allocating memory between different output queues in a shared memory ATM switch is described. The maximum allowable length for any individual queue at any point in time is the unused buffering function in the exchange. Dynamic threshold systems and methods intentionally prepare a small amount of buffer space, so that the remaining buffer space is evenly shared between the currently active output ports, rather than allocating it to a given output queue that is currently active. Dynamic threshold systems and methods improve fairness and exchange efficiency by ensuring access to buffer space for all output queues and protecting any single output queue from monopolizing memory at the expense of others. Dynamic threshold systems and methods apply to uncertain or changing load conditions. Packet loss in a dynamic critical system tends to be concentrated in the few queues required by an ATM system, since there are few messages that interfere with the higher protocol layer, so there is little need to retransmit the message. In addition, dynamic threshold systems and methods may be extended to handle traffic with multiple spatial priorities.

Architecture for integrated services packet-switched networks

Transfer rate controller and operation method

(57)【要約】 【課題】 レートの精度を維持しかつセルが送信される レートを動的に調整する柔軟性を提供できるＡＴＭセル の送信の調整方法を実現する。 【解決手段】 転送レートコントローラ１０はデータの 発信者が通信リンクによっていつデータが転送されるか を決定できるようにする。レートの精度を維持しかつセ ルが転送されるレートを動的に調整するための柔軟性を 提供するＡＴＭセルの転送の調整方法が述べられてい る。前の転送の年代順配列、セルの喪失の優先度、レー トパラメータの設定、トラフィックタイプ、および優先 度にしたがって、スケジューラ１２がお互いに対する仮 想接続の相対的な順序付けまたは配置を決定しかつスケ ジューリングする。ファインダ１４はデータ転送のため の仮想接続を選択する。したがって、転送レートコント ローラ１０は転送されるデータトラフィックの種別にし たがって仮想接続に対し個々の転送レートを提供する。

Millimeter-wave communications for peripheral devices

무선 디바이스는 유선-링크 프로토콜을 이용하는 전자 디바이스를, 예를 들어 무선 사설망(WPAN)에 커플링한다. 무선 디바이스는 전자 디바이스에 커플링하도록 구성되는 유선 인터페이스, 유선 인터페이스에 커플링되는 유선 트랜시버, 상기 전자 디바이스에 커플링되는 유선 링크의 종단으로서 기능하도록 구성되는 상기 적어도 하나의 유선 트랜시버, 및 유선 트랜시버에 커플링되고 WPAN 내의 무선 링크의 종단으로서 기능하도록 구성되는 무선 송신기 또는 트랜시버를 포함한다. 무선 디바이스는 복수의 비유사한 유선 디바이스들을 무선 링크를 통해 함께 커플링하도록 구성될 수 있다.

Method of supporting unknown addresses in an interface for data transmission in an asynchronous transfer mode

Apparatus for receiving/sending ipc message in atm switching system and method thereof

본 프로세서간 통신메세지 송수신처리장치 및 방법은 ATM셀의 형태로 프로세서간 데이터를 송수신하는 스위칭시스템에 있어서 IPC메세지를 송수신할 수 있도록 구현된 것으로서, 본 장치는 해당 프로세서와 양방향 억세스 방식으로 메세지를 송수신하기 위한 송수신용 버퍼; 통신메세지 송수신처리장치의 전기능을 제어하는 중앙처리장치; 타 프로세서로부터 메세지 수신시 비동기 전송모드(ATM)셀의 조립을 수행하는 SARA-R; 타 프로세서로 메세지 송신시 비동기 전송모드 셀을 모아 패킷형태로 분할하는 SARA-S; 중앙처리장치에 의해 제어되어 상기 조립된 패킷 또는 분할된 패킷메세지가 저장되는 패킷메모리; 셀조립에 필요한 정보 또는 셀을 분할하는데 필요한 정보가 저장되는 콘트롤 메모리; 메세지 송수신시 패킷포인터를 저장하는 주기억장치를 포함하도록 구성된다. The present invention provides an apparatus and a method for transmitting and receiving communication messages between processors, which are implemented to transmit and receive IPC messages in a switching system that transmits and receives data between processors in the form of an ATM cell. A buffer for transmitting and receiving; A central processing unit controlling all functions of the communication message transmitting and receiving apparatus; SARA-R for assembling an Asynchronous Cell (ATM) cell when receiving a message from another processor; SARA-S that collects asynchronous transmission mode cells and divides them into packets when sending a message to another processor; A packet memory controlled by a central processing unit to store the assembled packet or the divided packet message; A control memory for storing information necessary for cell assembly or information necessary for dividing a cell; And a main memory device for storing a packet pointer when transmitting and receiving a message.

Apparatus for Interface between Devices of different Data Bus

본 발명은 UTOPIA(Universal Test and Operation Physical Interface for ATM) 2에서 서로 다른 데이터 버스를 가지는 디바이스들의 정합에 관한 것으로 특히, UTOPIA 2의 마스터 기능 및 슬레이브 기능을 함께 수행하는 정합 제어부를 통해 ATM 계층과 물리계층 사이의 정합 기능을 분리함으로써, 데이터 버스의 차이로 인해 발생되는 데이터 송수신 성능의 저하를 방지할 수 있는 서로 다른 데이터 버스를 가지는 디바이스들의 정합 장치에 관한 것이다. The present invention relates to the matching of devices having different data buses in UTOPIA (Universal Test and Operation Physical Interface for ATM) 2, and more particularly, to the ATM layer and physical through a matching controller that performs the master and slave functions of UTOPIA 2 together. By separating the matching function between layers, the present invention relates to a matching device of devices having different data buses, which can prevent degradation of data transmission / reception performance caused by data bus differences. 종래 UTOPIA 2 정합 장치는 ATM 계층과 물리계층 사이에서 신호 및 데이터를 수동적으로 전달하는 슬레이브로 동작하기 때문에 폴링을 통해 선택된 하나의 어드레스만 처리할 수 있으므로 유효한 셀을 가지고 있는 어드레스는 자기 순서가 올 때까지 기다려야 하고, 이로 인해 데이터 송수신 성능이 저하되는 문제점이 있었다. Conventional UTOPIA 2 matching devices operate as slaves to passively transfer signals and data between the ATM layer and the physical layer, so that only one address selected through polling can be processed. It has to wait until this, there was a problem that the data transmission and reception performance is deteriorated. 본 발명은 UTOPIA 2 정합 장치에서 물리계층에 대한 정합 기능과 ATM 계층에 대한 정합 기능을 분리함으로써, 하나의 어드레스를 처리하는 동안이라도 유효한 셀을 가지고 있는 다른 어드레스를 처리할 수 있게 되어 데이터 버스 차이로 인한 데이터 송수신 성능 저하를 방지할 수 있는 효과가 있다. The present invention separates the matching function for the physical layer and the matching function for the ATM layer in the UTOPIA 2 matching device, thereby processing another address having a valid cell even while processing one address. There is an effect that can prevent the degradation of data transmission and reception due to.

Data communication device and data communication method

Method and device for controlling memory

메모리에 기록된 디지탈 정보다 다수의 대응한 비트 위치 형태의 이러한 정보가 하나 또는 여러 기능을 제어하도록 이용되기 전에 판독할 수 있게 보정되는 것에 있어서, 이러한 기능의 제어유닛에 의해 활성화 된다. The digital information recorded in the memory is activated by the control unit of this function in that such information in the form of a plurality of corresponding bit positions is corrected to be read before being used to control one or several functions. 제1세트의 비트를 표시하는 저장된 디지탈 정보에 대응하는 메모리 내에서 선택된 어드레스 위치 또는 위치들이 이 기능 및 제어합 역활을 하는 제어세트의 비트를 제어하고/또는 초기화하는데 필요하고 제 2 세트의 비트는 제 1 세트의 비트에 대응하는 현재 세트의 비트와 판독을 위해 현재 선택된 어드레스 위치에 대응하는 제3세트의 비트를 고려하여 산술된다. 메모리로 부터의 디지털 정보의 추종 판독이 수행될때 새로운 제어합이 제 5 세트의 비트를 형성하기 위해 판독을 위해 현재 선택된 어드레스 위치에 대응하는 제 4 세트의 비트와 제 1 세트의 비트에 해당하는 현재 판독된 비트 위치를 고려하여 같은 방식으로 산출된다. 비교가 수행될때 판독 디지탈 정보가 보정으로 얻어지고 일치가 제 2 세트 비트와 제 5 세트 비트 사이에서 발견된다. The selected address location or locations in memory corresponding to the stored digital information indicative of the first set of bits are needed to control and / or initialize the bits of the control set that serve this function and control sum and the second set of bits It is arithmetic considering the bits of the current set corresponding to the first set of bits and the third set of bits corresponding to the address position currently selected for reading. When a follow-up read of digital information from the memory is performed, a new control sum is present to correspond to the fourth set of bits and the first set of bits corresponding to the address location currently selected for reading to form a fifth set of bits. It is calculated in the same manner taking into account the read bit position. When the comparison is performed, read digital information is obtained with correction and a match is found between the second set bit and the fifth set bit.

Asynchronous Transfer Mode Communication Network, System Processing Performance and Memory Usage Enhancement Method

본 발명의 ATM 통신 네트워크는 디바이스 드라이버 및 인터페이스에서 어댑터에 결합된 메모리를 갖는 시스템 프로세서를 포함한다. 메모리내에 저장된 프레임은 어댑터내에 상주하는 전송 준비 큐를 사용하여 네트워크로 전송되며 전송 제어 레지스터에 의해 정의된다. 기술자 및 포인터에 의해 프레임은 디바이스 드라이버에 의해 유지되는 수신 준비 리스트에 서로 연결된다. 전송 프레임 완료 리스트는 전송 제어 레지스터를 사용하여 시스템 메모리내에 설정된다.프레임 전송이 완료된 때를 표시하는 어댑터에 의해 인터럽트가 발생된다. 동시에,셀은 네트워크로부터 수신되고,디바이스 드라이버에 의해 설정되는 프리 버퍼 리스트에 따라 시스템 메모리내에 저장된다. 디바이스 드라이버에 의해 포인터는 수신 프리 버퍼 리스트의 최종 엔트리로 유지된다.어댑터는 수신 프리 버퍼 리스트로부터 사용될 다음 버퍼로 포인터를 유지한다.어댑터내의 수신 제어 레지스터를 통해 어댑터에 대해 표시되는 위치를 갖는 시스템 메모리내의 디바이스 드라이버에 의해 수신 준비 리스트가 설정된다.수신 데이터 셀은 프리 버퍼 리스트로부터 버퍼내의 프레임으로 재어셈블된다. 수신된 프레임의 완료시, 프레임은 적절한 수신 준비 리스트에 추가된다. 하나 이상의 완료된 프레임이 네트 워크로의 전송을 위한 수신 준비 리스트상에 상주하는 경우 어댑터에 의해 프로세서로 인터럽트가 발생된다.

Communication control device

(APPARATUS FOR RECEIVING / SENDING IPC MESSAGE IN THE SWITCHING SYSTEM USING ATM AND METHOD)

본 프로세서간 통신메세지 송수신처리장치 및 방법은 ATM 셀의 형태로 프로세서간 데이터를 송수신하는 스위칭시스템에 있어서, IPC메세지를 송수신할 수 있도록 구현된 것으로서, 본 장치는 해당 프로세서와 양방향 억세스 방식으로 메시지를 송수신하기 위한 송수신용 버퍼; 통신 메시지 송수신처리장치의 전기능을 제어하는 중앙처리장치; 타 프로세서로부터 메시지 수신시 비동기 전송모드(ATM)셀의 조립을 수행하는 SARA-R; 타 프로세서로 메시지 송신시 비동기 전송모드 셀을 모아 패킷형태로 분할하는 SARA-S;중앙처리장치에 의해 제어되어 상기 조립된 패킷 또는 분할된 패킷메세지가 저장되는 패킷메모리; 셀조립에 필요한 정보 또는 셀을 분할하는데 필요한 정보가 저장되는 콘트롤 메모리; 메시지 송수신기 패킷포인터를 저장하는 주기억장치를 포함하도록 구성된다.

Dynamic rate control schedule for atm network

(57)【要約】 （修正有） 【課題】 種々のサービスクラスのキューに対して、臨 機応変に帯域幅を割り当てることができるスケジューラ を提供する。 【解決手段】 内部スイッチキューについての各トラヒ ックストリームが、スイッチ内の輻輳情報に基づいて計 算された最低保証レートと動的成分からなるレートによ ってレートシェーピングされる。高利用率を達成する一 方、動的レート制御ＤＲＣは各ストリームに対して最低 のスループットを保証し、公平に未使用帯域幅を分配す る。加重フェアシェアリングスケジューラと同様に、未 使用帯域幅が最低スループット保証に比例して共有され る必要がない場合には、ＤＲＣは未使用帯域幅分配を臨 機応変に行う。更に、観測されたＱｏＳに基づいて一群 の加重を動的に更新してＤＲＣ内部に効果的な閉ループ ＱｏＳ制御を確立する。またマルチステージスイッチ内 のボトルネック部における内部輻輳を制御する。

Packet communication system and time slot allocation control method used therefor

A matching device between an ATM exchange and a DS1E transmission device

본 발명은 비동기 전송모드인 ATM(Asynchronous Transfer Mode, 이하ATM)교환기를 정합하기위한 정합장치에 관한 것으로, 특히, ATM 교환기로부터 인가되는 ATM 셀을 DS1E 프레임에 실어 전송함과 동시에 DS1E 프레임에 실려 인가되는 셀을 추출하여 ATM 교환기측으로 출력하도록 하는 ATM 교환기와 DS1E 전송장치간의 접합장치에 관한 것이다. 종래에는 ATM 교환기로 부터 출력되는 ATM 셀을 다른 교환국으로 전송하기 위해서는 소정의 전송장치를 사용해야 한다. 그런데 종래에는 교환망내에서의 신호를 전송하기 위한 용도로서 DS1E(유럽식) 전송장치를 사용하고 있는바, ATM 교환기를 정합하여 주기위한 정합장치가 개발되어 있지않아 ATM 교환기를 DS1E 전송장치에 접속 할 수 없게 되는 문제점이 있었다. 본 발명은 스위치와 전송선로 사이의 정합기능을 가진 장치로서 단일 셀을 다수의 전성선로로 동시에 보낼 수 있는 멀티캐스팅 기능을 보유하고 있으며 ATM 교환기와 기존의 DS1E 전송 장치 사이의 프로토콜 변환을 효과적으로 수행하므로, DS1E 전송 장치를 ATM 교환기에 수용할 수 있게 되며, 데이타 전송경로상에서의 프로세서 개입을 최소화 하였으므로 셀 처리를 효과적으로 할 수 있게 된다.

A fixed length picket switching apparatus using multiplacer demultiplexer

There is provided a switching device of fixed length packet using a multiplexor and a demultiplexor. The switching device has a output buffer typed structure and includes a plurality of input port driving units(IPDU:31), a plurality of switch input demultiplexor units(SIDU: 31), a plurality of switch output multiplexor units(SOMU: 33), a plurality of output port driving units(OPDU: 34), a plurality of switch module control unit(SMCU: 36), a switch change-over control unit(SCCU: 37), a processor interface control unit(PICU: 38), and a reset control unit(RSCU:39). The switching device protects itself from temporary overflow of output terminal to enhance the overall performance.

Apparatus and Method for Subscriber Board Traffic Control in ATM System

본 발명은 ATM 시스템의 가입자 보드 트래픽 제어에 관한 것이다. 종래 ATM 시스템의 가입자 보드에서는 프레이머에 장애가 발생하여 장애가 발생한 프레이머에 연결된 물리계층 FIFO에서 ATM 셀이 출력되지 못하고 있는 경우 외부 FIFO에서 해당 물리계층 FIFO로 출력되는 셀이 막히게 되어 연이어 입력되는 정상적인 물리계층 FIFO로 가는 ATM 셀들도 막히게 되는 문제점이 있었다. The present invention relates to subscriber board traffic control in an ATM system. In the subscriber board of the conventional ATM system, if an ATM cell is not output from the physical layer FIFO connected to the failed framer due to a failure of the framer, the cells output from the external FIFO to the corresponding physical layer FIFO are blocked so that the normal physical layer FIFO is successively input. There was a problem that even ATM cells going to be blocked. 본 발명에서는 ATM 시스템의 가입자 보드에서 망동기 블록의 전송 기준 클럭을 카운트하여 프레이머의 장애 여부를 판별하게 함으로써, 장애가 발생한 프레이머에 연결된 물리계층 FIFO로 출력되는 ATM 셀을 외부 FIFO에서 폐기하게 하고, 또한 이를 통해 정상적인 물리계층 FIFO로 출력되는 ATM 셀의 트래픽을 원활하게 처리하게 한다. In the present invention, by determining the failure of the framer by counting the transmission reference clock of the network synchronizer block in the subscriber board of the ATM system, the ATM cell outputted to the physical layer FIFO connected to the failed framer is discarded from the external FIFO. This smoothly handles the traffic of ATM cells output to normal physical layer FIFOs.

Apparatus for processing a cell in a digital signal process of telecommunication system

본 발명은 통신 시스템의 디지털신호처리부에서 셀 처리 장치에 관한 것이다. 선입선출 메모리로부터 디지털 신호 처리기로 전송되는 셀을 송신과 수신이 겹치지 않도록 시간 딜레이를 주는 버퍼와, 상기 디지털신호처리기로부터의 신호와 상기 선입선출 메모리로부터의 신호를 입력받아 우선 순위를 결정하여 우선 순위에 따라 셀 전송을 하도록 하고, 상기 디지털신호처리기로부터 송신인 경우 시작 셀을 발생시켜 상기 선입선출 메모리로 출력하며, 상기 디지털신호처리기로 수신인 경우 시작 셀을 검색하는 아비트레이톨로 이루어짐을 특징으로 한다. 따라서 본 발명은 디지털신호처리기에서 셀 경계를 확인하는 것과 AAL2인지 확인하는 것과 Invalid 셀인지 확인하는데 걸리는 시간을 아비트레이톨을 사용하여 없앴을 있어 디지털신호처리기를 효율적으로 사용할 수 있으며, 디지털신호처리부에서 매 셀마다 요청 및 시작 셀을 인가하는 일에 토글신호를 이용함으로써 시간 딜레이가 생기지 않는 이점이 있다. 에이티엠(Asynchronous Transfer Mode: ATM), 디지털신호처리(Digital Signal Processor) The present invention relates to a cell processing apparatus in a digital signal processing section of a communication system. A buffer for giving a time delay so as to prevent transmission and reception from overlapping with cells transmitted from the first-in first-out memory to a digital signal processor; a signal from the digital signal processor and a signal from the first- And outputting the generated start cell to the first-in-first-out memory when the received signal is a transmission signal from the digital signal processor, and searching for a start cell in the case of the received signal by the digital signal processor . Therefore, the present invention eliminates the time required to confirm cell boundary, AAL2, and Invalid cell using a digital signal processor, so that a digital signal processor can be efficiently used and a digital signal processor There is an advantage that a time delay is not generated by using a toggle signal for applying a request and a start cell to each cell. Asynchronous Transfer Mode (ATM), digital signal processing (Digital Signal Processor)

Buffer device with arbitration function, insertion data arbitration method, and data insertion device with arbitration function

Terabit class packet exchange apparatus and method

물리적으로 실현가능한 1 Tbps 혹은 그 이상의 ATM 패킷교환기(10A)로서, 다수의 입력인터페이스가 단일 단계의 교환구조(14A)로 접속되고, 이 교환구조는 다수의 출력모듈(16 0 -16 m )으로 접속되는 구조를 가지고 있는 일반적인 성장가능한 패킷교환기 구조가 기술된다. 이 ATM 패킷교환기는 다른 성장가능한 패킷교환기에 비해 아웃밴드제어기(20)에 의해 제어되는 단일단계의 교환구조(14A 혹은 14B)를 포함하고 있으며, 비슷한 용량의 전기적인 크로스바 교환기나 그 동형에 비해 상대적으로 회로구성이 현저히 간단하다. 이 ATM 패킷교환기 구조는 매우 유연하여 동일한 교환구조와 아웃밴드제어기의 구조를 사용하여 가변장 패킷이나, 회선교환접속, 폴트 톨러런트 용장 회로를 제공하는데 까지 확장될 수 있다.

Method to estimate the current datapacket rate of a virtual connection, a feedback mechanism using said method and device, switching node and destination node realizing said method

A method is described to estimate the current datapacket rate CCR i called herein current cell rate, of a connection out of a plurality of connections which are carrying datapackets via a multiplexed transmission channel in a communication network. The method includes the steps of storing in a buffer (B) incoming datapackets of the connections, determining the total number of datapackets BC TO in the buffer (B), determining the number of datapackets of the connection BC i in the buffer (B), measuring an aggregate input datapacket rate C IN of the buffer and estimating the current datapacket rate CCR i via the formulae: ##EQU1##

ATM Switch

An ATM switch includes a plurality of stages in which each stage has basic switches and the stages are interconnected. The ATM switch includes M×N basic switches per each stage and a part for interconnecting between the stages. The M×N basic switches are divided into N groups. The part connects an output port of each basic switch at a front stage to M input ports of the basic switches at a back stage. At the output port, a wavelength-multiplexing part is used, and, at the input port, a wavelength-demultiplexing part is used. Further, a wavelength-switching part for switching optical signals of M wavelength-multiplexed optical signals arriving from the M wavelength-multiplexing part and outputting the switched wavelength-multiplexed optical signals to the M wavelength-demultiplexing part is used.

Method for fair dynamic scheduling of available bandwidth rate (ABR) service under asynchronous transfer mode (ATM)

A method for dynamic scheduling of data transmission for a large number of data channels under the available bit rate (ABR) service protocols of asynchronous transfer mode (ATM) uses a schedule table and ready queue. In this method, at each time slot, data channels referenced in the current entry of the schedule table is removed from the schedule table and appended to the ready queue. At each available transmission time slot, an ATM cell is transmitted from the data channel referenced in the record at the head of the ready queue. The data channel is then rescheduled for in the schedule table for the next transmission. The present invention also accommodates data transmission rates related to fractional time slot intervals.

Packet switching system

In a packet switch, a switch request allocation plan is generated by reducin g the number of queue requests VOQ relating to each of one or both sets of por ts I1~.IN, O1~.ON, by a value such that the number of requests relating to each member of the set or sets of ports is no greater than the number of requests (frame value F) that can be handled by the switch (10). This reduction may b e individually done for each queue. Alternatively all queues relating to a giv en port, or to any port, may have their length reduced by a single value determined by the size of the longest queue. A further stage may then apply other allocation rules to allocate requests remaining unallocated by the previous stage.

Cell buffer management device.

Input queuing system designed in particular to be connected to the inputs of a spatial type switching matrix without blocking.

Memory at interconnection points, in particular for the communication of telecommunication terminals operating at different frequencies.

System and method for providing gaps at ingress to a network element

The invention provides a system and method of controlling timing of release of traffic for a communication switch. The traffic originates from at least one source, is directed to a common ingress point of the switch and is directed to a common egress point in the switch. The egress point has a maximum egress transmission rate. The traffic has at least one datastream. Each datastream has a requested transmission rate. The method comprises, for each datastream, establishing a maximum cell release rate such that a sum of each of the maximum cell release rate does not exceed the maximum egress transmission rate and utilizing the maximum cell release rate to govern release of local traffic in the datastream from the ingress point.

Switching system

본 발명은 한 세트의 M개의 입력 포트에서 한 세트의 M개의 출력 포트 중 임의의 포트로 셀을 루팅(routing)하는 스위칭 시스템(switching system)에 관한 것으로, 기존의 기술로 복잡한 네트워크, 멀티미디어 어플리캐이션 및 고속 통신에 있어서 시스템의 속도를 증가시키기 위해, 한 세트의 M개 수신기, 한 세트의 M개 입력 루터 및 한 세트의 M개 ASA 레지스터를 갖는 저장부, 한 세트의 M개 출력 루터, 한 세트의 M개 드라이버 및 한 세트의 M개 ARA 레지스터를 갖는 검색부, 입력 처리 제어부 및 출력 처리 제어부를 갖는 제어부, 셀이 출력 포트로 전송되는 횟수를 등록하는 수단 등을 포함하는 스위칭 시스템이 제공된다. 이러한 스위칭 시스템에 의해, 고속화가 실현된다. The present invention relates to a switching system for routing cells from a set of M input ports to any one of a set of M output ports and is known in the art as a complex network, A set of M output routers, a set of M input routers, and a set of M ASA registers, a set of M output routers, a set of M output routers, There is provided a switching system including a search unit having M drivers of a set and a set of M ARA registers, a control unit having an input process control unit and an output process control unit, means for registering the number of times the cell is transmitted to the output port, and the like . By this switching system, high-speed operation is realized.

METHOD FOR MANAGING THE DECODING AND RESTORATION OF A SOUND SIGNAL IN AN ASYNCHRONOUS TRANSMISSION SYSTEM

Terabit per second packet switch

A physically realizable one terabit or more ATM packet switch 10 A that has a large number of input interfaces connected to a single stage switching fabric 14A which is in turn connected to a number of output modules 160-16 m, accordingto the generic growable packet switch architecture. This ATM packet switch 10 A is different from other growable packet switches in that it has a single stage switch fabric (14A or 14B) controlled by an out-of-band controller 20, yet it has significantly reduced complexity with respect to comparably sized electronic crossbar switches or their isomorphs. This ATM packet switch architecture is so flexible, it can be extended to provide variable length packets, circuit switched connections and fault tolerant redundant circuits using the same switch fabric and out-of-band controller architectures.

Method for managing a list of packets in an output port of a packet switch

Ce procéde permet de tenir compte des niveaux de prioritésil con siste à stocker dans une file de traitement, dans leur ordre d'arrivée pour réémission dans le port de sortie, les identificateurs des paquets à réémettre et à effectuer, en remontant pas à pas la file de traitement, une succession de comparaisons deux à deux des identificateurs présents dans la file de traitement, en s'aidant d'un banc de registres de travail (RD) et en maintenant dans le banc de registre de travail (RD) l'identificateur considéré en fin de chaque comparaison comme le plus ancien dans le niveaux de priorité le plus élevé, ces opérations s'effectuant dans une mémoire de liste d'attente (224) gérée au moyen de quatre pointeurs: un pointeur de lecture PL, un pointeur d'écriture PE, un pointeur auxiliaire de lecture PAL et un pointeur auxiliaire d'ecriture PAE.

A buffer management method for mon-real time traffic in atm switching systems

1. 청구범위에 기재된 발명이 속하는 기술분야 1. TECHNICAL FIELD OF THE INVENTION 본 발명은 비동기전송모드 교환기에서 비실시간 트래픽 서비스를 위한 버퍼 관리 방법에 관한 것임. The present invention relates to a buffer management method for a non-real-time traffic service in an asynchronous transfer mode switch. 2. 발명이 해결하려고 하는 기술적 과제 2. The technical problem to be solved by the invention 본 발명은 교환기의 트래픽 상태에 따라 동적으로 버퍼를 운용하는 비동기전송모드 교환기에서의 버퍼 관리 방법을 제공하는데 그 목적이 있음. It is an object of the present invention to provide a buffer management method in an asynchronous transfer mode exchange that operates a buffer dynamically according to a traffic state of an exchange. 3. 발명의 해결 방법의 요지 3. Summary of the Solution of the Invention 본 발명은, 셀의 서비스를 확인하여 버퍼 저장 셀 수의 임계치 초과 여부를 판단하는 제 1 단계; 하나의 개별연결버퍼 저장 셀 수가 개별연결버퍼 임계치 미만이거나, 모든 개별연결버퍼 저장 셀 수가 선패킷 폐기 임계치와 개별 연결 버퍼 임계치의 합 미만이면 셀을 수락하는 제 2 단계; 모든 개별연결버퍼 저장 셀 수가 부분패킷 폐기 임계치를 초과하면 셀을 폐기하는 제 3 단계; 및 모든 개별연결버퍼 저장 셀 수가 부분패킷폐기 임계치 미만이면 선패킷 폐기를 수행하는 제 4 단계를 포함함. The present invention includes a first step of determining whether a cell exceeds a threshold value by checking a service of a cell; A second step of accepting the cell if the number of one individual connected buffer storage cells is less than the individual connected buffer threshold or if the number of all individual connected buffer storage cells is less than the sum of the prepacket discard threshold and the individual connected buffer threshold; A third step of discarding the cell if the number of all individual buffered storage cells exceeds the partial packet discard threshold; And a fourth step of performing prepacket discard if the number of all individually connected buffer storage cells is below the partial packet discard threshold. 4. 발명의 중요한 용도 4. Important uses of the invention 본 발명은 비동기전송모드 교환기에서의 버퍼 관리에 이용됨. The present invention is used for buffer management in an asynchronous transfer mode exchange.

SELF - ROUTING MULTI - PATH SWITCHING NETWORK FOR SWITCHING ASYNCHRONOUS MULTIPLEXED TIME CELLS.

METHOD FOR MANAGING A LIST OF PACKETS WAITING FOR RE-EMISSION IN AN OUTPUT PORT OF A PACKET SWITCH

The invention concerns a method for taking into account priority levels which consists in storing in a processing queue, in their arrival sequence for retransmission in the output port, packet identifiers to be retransmitted and in carrying out, by backtracking step by step through the processing queue, a series of pairing comparisons of the identifiers present in the processing queue, using a bank of working registers (RD) and maintaining in the bank of working registers (RD) the identifier concerned at the end of each comparison as the earliest in the highest priority level, said operations being carried out in a queue memory (224) managed by means of four pointers: a read pointer (PL), a write pointer (PE), an auxiliary read pointer (PAL) and an auxiliary write pointer (PAE).

METHOD AND SYSTEM FOR SMOOTHING AND CONTROLLING ASYNCHRONOUS TIME COMMUNICATION RATES.

ASYNCHRONOUS CELL TRANSFER MODE SWITCH OF MULTIPLE INPUT CHANNELS WITH MULTIPLE OUTPUT CHANNELS

Concentrator-based growable packet switch

An mxn (m > n) output Packet Switch Unit is implemented by using an nxn Packet Switch Module and an m:n Concentrator. The arriving packet cells are supplied from the m Concentrator inputs to the n Concentrator outputs in a "first-in first-out" (FIFO) sequence. The Concentrator provides for buffering of arriving packet cells on the m Concentrator inputs in excess of available packet cell positions in the n Concentrator outputs until they can be supplied to a Concentrator output in the FIFO sequence. In turn, packet cells from the n Concentrator outputs are supplied to n inputs of the Packet Switch Module which supplies them to appropriate output destinations associated with the n outputs of the Packet Switch Module. A plurality of the Concentrator-Based output Packet Switch Units is readily employed to implement any "larger" Packet Switch architecture.

High bit rate cell switching element in cmos technology

The switching element allows building up of ATM exchanges capable of processing cell flows at bit rates higher than 700 Mbit/s. It uses an architecture with output queues, implemented through a unique shared memory, suitably controlled in order to obtain spatial cell switching towards the outputs. ATM cells are converted into a highly parallel format by a structure named rotation memory, where through the cells are then transferred into the master memory. The rotation memory is used also for the inverse operations of format restoration towards the output. The element control circuit is entrusted with the generation of writing and reading addresses of the master memory, in order to carry out the switching proper.

Apparatus and method for multiplexing cells in asynchronous transmission mode

1. 청구범위에 기재된 발명이 속한 기술분야 1. TECHNICAL FIELD OF THE INVENTION 다중화 장치 Multiplexing device 2. 발명이 해결하려고 하는 기술적 과제 2. The technical problem to be solved by the invention 입력버퍼를 구비하는 다중화장치에서 입력버퍼에 저장된 셀의 수에 따른 우선순위를 검사하여 다중화한다. In the multiplexing apparatus having an input buffer, the multiplexing apparatus checks the priority according to the number of cells stored in the input buffer and multiplexes the same. 3. 발명의 해결 방법의 요지 3. Summary of the Solution of the Invention 입력포트들에 각각 연결되어 수신되는 셀들을 저장하는 버퍼들을 구비하며, 비동기 전송모드의 셀을 다중화하는 경우 먼저 각 버퍼들에 입력되는 셀 수를 카운트하며 각 버퍼의 셀 카운트 값을 비교하여 최대값을 검사한다. 이후 최대값을 갖는 버퍼를 선택하며 선택된 버퍼의 저장 셀을 다중화하여 출력한다. Buffers are provided to store received cells connected to the input ports, respectively. In case of multiplexing cells in asynchronous transmission mode, the number of cells input to each buffer is counted first. Check it. After that, the buffer having the maximum value is selected and the storage cells of the selected buffer are multiplexed and output. 4. 발명의 중요한 용도 4. Important uses of the invention 셀을 저장하는 버퍼의 우선순위를 분석하여 셀을 다중화하므로서, 버퍼의 오버플로우를 방지할 수 있다. By multiplying the cells by analyzing the priority of the buffer storing the cells, the overflow of the buffer can be prevented.

Virtual interconnection memory, in particular for the communication of telecommunications terminals operating at different frequencies.