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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 4522. Отображено 100.
12-01-2012 дата публикации

Nicam decoder with output resampler

Номер: US20120008724A1
Автор: Matthew F. Easley, Matthew S. Barnhill, Roger R. Darr
Принадлежит: THAT Corp

A NICAM audio signal re-sampler may include a non-linear interpolator configured to interpolate in a non-linear manner between sequential digital samples that are based on a stream of demodulated NICAM audio samples. A phase differential calculator may be included that compares phase information at different resolutions.

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Номер записи: 1
16-02-2012 дата публикации

QAM and GMSK Modulation Methods

Номер: US20120039410A1
Автор: Kamilo Feher
Принадлежит: Individual

Filtering and modulating a first bit rate signal into a Gaussian filtered Gaussian Minimum Shift Keyed (GMSK) modulated signal and a second bit rate signal into a Quadrature Amplitude Modulated (QAM) signal. A method for nonlinearly and linearly amplifying GMSK and QAM signals. A diversity receiver and demodulator method for receiving and demodulating transmitted modulated signals. Processing, transmit baseband filtering and modulating signals for providing cross-correlated in-phase and quadrature-phase Gaussian filtered Gaussian Minimum Shift Keying (GMSK) and other cross-correlated modulated signals and spread spectrum Quadrature Phase Shift Keying (QPSK) modulated signals. Transmit processing and filtering for providing time division multiplexed (TDM) Gaussian filtered baseband signal and Orthogonal Frequency Division Multiplexed (OFDM) in-phase and quadrature-phase baseband modulated signal to a cellular network and to separate wireless network. Diversity receiver and demodulator method with multiple antennas for providing demodulated cross-correlated in-phase and quadrature-phase filtered signals.

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Номер записи: 2
05-04-2012 дата публикации

Signal extender system and signal extender thereof

Номер: US20120082249A1
Автор: Chao-Hsuan Hsueh
Принадлежит: Aten International Co Ltd

A signal extender system including a first electronic apparatus, a second electronic apparatus, and a signal extender. The signal extender system includes a transmission module, a receiving module, and pairs of differential transmission lines. The receiving module includes a timing memory unit. The transmission module receives a digital image differential signal including differential data signals, a differential timing signal, and a two-way differential signal. A first pair of differential transmission lines, a second pair of differential transmission lines, and a third pair of differential transmission lines of the pairs of differential transmission lines transmit the differential data signals respectively. A fourth pair of differential transmission lines alternately transmits the two-way differential signal and a part of differential timing signal. The timing memory unit memories and continually replicates the part of differential timing signal to recover the differential timing signal and output it to the second electronic apparatus.

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Номер записи: 3
14-06-2012 дата публикации

Device and method for compensating a signal propagation delay

Номер: US20120146694A1
Автор: Anton Korniienko, Eric Colinet
Принадлежит: Commissariat a lEnergie Atomique et aux Energies Alternatives CEA

A device for compensating a delay τ suffered by a first periodic signal ref(t) during propagation between a first and second end of a first transmission connection, comprising at least: first means able to generate a second signal ref(t+τ) corresponding to the first signal ref(t) the phase of which is advanced by a time equal to the delay τ, second means able to generate, from a third signal ref(t−τ) obtained at the second end of the first transmission connection and corresponding to the first signal ref(t) the phase of which is delayed by the delay τ, and from the second signal ref(t+τ), a fourth signal in phase with the first signal ref(t).

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Номер записи: 4
09-08-2012 дата публикации

Memory System with Calibrated Data Communication

Номер: US20120204054A1
Автор: Benedict Chung-Kwong Lau, Bruno W. Garlepp, Donald C. Stark, Jared Levan Zerbe, Jun Kim, Kevin S. Donnelly, Leung Yu, Mark A. Horowitz, Roxanne Vu, Stefanos Sidiropoulos, Tsyr-Chyang Ho
Принадлежит: RAMBUS INC

An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

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Номер записи: 5
27-09-2012 дата публикации

Signal receiving circuit, memory controller, processor, computer, and phase control method

Номер: US20120242385A1
Автор: Noriyuki Tokuhiro
Принадлежит: Fujitsu Ltd

A signal receiving circuit includes a phase detection unit and a delay control unit. The phase detection unit detects a phase difference between a received signal and a clock signal. The delay control unit receives the phase difference, delays a phase of the received signal in a range not exceeding a delay amount determined by using a predetermined phase difference as a unit, and changes, when the phase difference exceeds the predetermined phase difference, a delay amount of the received signal by using the predetermined phase difference as a unit.

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Номер записи: 6
25-10-2012 дата публикации

Sampling clock selection module of serial data stream

Номер: US20120269308A1
Автор: Chin-Chieh Chao, Hui Wen Miao, Ko-Yang Tso, Ren-Feng Huang
Принадлежит: Raydium Semiconductor Corp

A sampling clock selection module for a serial data stream is disclosed. The sampling clock selection module includes a multi-phase generation circuit, a sampling circuit, a comparison unit and a logic operation unit. The multi-phase generation circuit generates a plurality of non-overlapping clock phases derived from a reference clock signal. The phase selection circuit selects a sampling clock phase under a calibration mode. The sampling circuit performs sampling on the serial data stream a plurality of times to generate a plurality of sampled values in response to the sampling clock phase. The comparison unit compares the sampled values with the serial data stream so as to update a plurality of flag signals. The logic operation unit performs a logic operation on the flag signals so as to select a sampling clock phase under a normal operation mode from the clock phases.

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Номер записи: 7
20-12-2012 дата публикации

Transmitting device, receiving device and transmitting/receiving system

Номер: US20120321002A1
Автор: Hironobu Akita
Принадлежит: THine Electronics Inc

A transmitting device 10 A has a transmission data generating part 11 and an output buffer part 12 A. The transmission data generating part 11 transmits a data 1 and a clock 1, which are to be transmitted to a receiving device, and outputs them to the output buffer part 12 A. The output buffer part 12 A includes a data transmitting part 13 and a clock transmitting part 14 A. The clock transmitting part 14 A generates and transmits a clock intermittently phase-shifted. The data transmitting part 13 transmits the data in sync with the clock transmitted from the clock transmitting part 14 A.

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Номер записи: 8
21-02-2013 дата публикации

Low power edge and data sampling

Номер: US20130044845A1
Автор: Jared L. Zerbe
Принадлежит: Individual

An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit.

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Номер записи: 9
02-05-2013 дата публикации

METHOD FOR TRANSMITTING AN ESMC MESSAGE THROUGH A SONET/SDH DOMAIN

Номер: US20130107897A1
Автор: Bui Dinh Thai, Le Pallec Michel
Принадлежит:

The embodiments of the present invention describe a method for transmitting an Ethernet Synchronization Messaging Channel “ESMC” message between a first and a second Synchronous Ethernet “SyncE” domain, said first and second domains being interconnected by a third, Synchronous Optical Networking/Synchronous Digital Hierarchy “SONET/SDH” domain, in which at least one part of said Ethernet Synchronization Messaging Channel “ESMC” message is encapsulated when entering said third domain and unencapsulated when exiting said third domain, so as to create a network tunnel through the Synchronous Optical Networking/Synchronous Digital Hierarchy “SONET/SDH” domain. 1. A method for transmitting an Ethernet Synchronization Messaging Channel “ESMC” message between a first and a second Synchronous Ethernet “SyncE” domain , said first and second domains being interconnected by a third , Synchronous Optical Networking or Synchronous Digital Hierarchy “SONET/SDH” domain , comprising the steps of:encapsulating at least one part of said ESMC message when entering said third domain; andunencapsulating said at least one part of said ESMC message when exiting said third domain, so as to create a network tunnel through the third SONET/SDH domain.2. A method for transmitting an Ethernet Synchronization Messaging Channel “ESMC” message according to wherein said message comprises at least one Type Length Value “TLV” field different from the Quality Level “QL-TLV” field.3. A method for transmitting an Ethernet Synchronization Messaging Channel “ESMC” message according to claim 1 , wherein the steps of encapsulating and unencapsulating the messages are done within the Synchronous Ethernet-Synchronous Optical Networking/Synchronous Digital Hierarchy “SyncE-SONET/SDH” hybrid nodes located at the interface of the various domains.4. A method for transmitting an Ethernet Synchronization Messaging Channel “ESMC” message according to wherein a SyncE-SONET/SDH hybrid node receivesfirstly, at least ...

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Номер записи: 10
30-05-2013 дата публикации

Semiconductor device, a parallel interface system and methods thereof

Номер: US20130135956A1
Автор: Beom-Sig Cho, Seong-Jin Jang, Seung-Jun Bae
Принадлежит: Individual

A memory device includes a clock receiving block, a data transceiver block, a phase detection block, and a phase information transmitter. The clock receiving block is configured to receive a clock signal from a memory controller through a clock signal line and generate a data sampling clock signal and an edge sampling clock signal. The data transceiver block is configured to receive a data signal from the memory controller through a data signal line. The phase detection block is configured to generate phase information in response to the data sampling clock signal, the edge sampling clock signal and the data signal. The phase information transmitter is configured to transmit the phase information to the memory controller through a phase information signal line that is separate from the data signal line.

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Номер записи: 11
27-06-2013 дата публикации

Method and Apparatus for a Metal Detection System

Номер: US20130163650A1
Автор: Sherwood Spencer, Whittingham John Andrew, Woodland Peter Robert
Принадлежит: GOLDWING DESIGN & CONSTRUCTION PTY LTD

The present application relates to the field of metal detectors, which may find military, industrial and civilian application. In one form, the present application relates to a method and apparatus for a metal detection system in which a first component is synchronized with a second component. The metal detection system is adapted for use in diminishing interference between two or more metal detectors operating in close proximity. In one form, the metal detection system is adapted for use in a ground loop metal detection system that allows for the detection of metal or metallic objects at greater depths than currently available with standard pulse induction or induction type metal detecting equipment. 118.-. (canceled)19. A metal detection system comprising:at least one metal detector;a communication interface;synchronising means for synchronising at least one first metal detector system component with at least one second metal detector system component.20. A metal detection system as claimed in further comprising:synchronising pulse signal means for generating a synchronising pulse signal;transmission means for transmitting the synchronising pulse signal over the communication interface;receiving means for receiving the synchronising pulse signal at the first metal detector system component;resetting means for resetting the timing sequence of at least one of a transmit timing signal and a receive timing signal of the first metal detector system component in accordance with the synchronising pulse signal.21. A metal detection system as claimed in further comprising a remote communication device adapted to invoke the synchronising pulse signal means to generate the synchronising pulse signal and the transmission means to transmit the synchronising pulse signal over the communication interface.22. A metal detection system as claimed in wherein the remote communication device comprises a GPS satellite.23. A metal detection system as claimed in wherein the synchronising ...

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Номер записи: 12
25-07-2013 дата публикации

Dual mode clock/data recovery circuit

Номер: US20130191679A1
Автор: Behnam Amelifard, Jingcheng Zhuang, Nam V. Dang, Tirdad Sowlati, Xiaohua Kong, Zhi Zhu
Принадлежит: Qualcomm Inc

A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.

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Номер записи: 13
22-08-2013 дата публикации

TRANSMISSION APPARATUS, TRANSMISSION METHOD, PROGRAM, AND COMMUNICATION SYSTEM

Номер: US20130215910A1
Автор: Inomata Naoki
Принадлежит: SONY CORPORATION

A transmission apparatus transmits a timestamp in increments of 10seconds in accordance with a standard. The transmission apparatus includes a first counter counting a clock value based on a reference clock of α×10Hz to output values in increments of 10at intervals of α for α consecutive times, a second counter counting the clock value based on the reference clock so as to output α values 0 through α−1 repeatedly, a table in which the α values output from the second counter are associated individually with evenly dispersed values each smaller than the 10, a conversion portion converting the output from the second counter to values each smaller than the 10by referring to the table, and an addition portion adding up the output from the first counter and the output from the conversion portion so as to generate the timestamp in increments of the 10seconds. 1. A transmission apparatus for transmitting a timestamp in increments of 10seconds in accordance with a standard , the transmission apparatus comprising:{'sup': X', 'Y-X, 'a first counter configured to count a clock value based on a reference clock of α×10Hz so as to output values in increments of 10at intervals of α for α consecutive times;'}a second counter configured to count the clock value based on the reference clock so as to output α values 0 through α−1 repeatedly;{'sup': 'Y-X', 'a table in which the α values output from the second counter are associated individually with evenly dispersed values each smaller than the 10;'}{'sup': 'Y-X', 'a conversion portion configured to convert the output from the second counter to values each smaller than the 10by referring to the table, and'}{'sup': '−Y', 'an addition portion configured to add up the output from the first counter and the output from the conversion portion so as to generate the timestamp in increments of the 10seconds.'}2. The transmission apparatus according to claim 1 , whereinthe standard is IEEE 1588 PTP, and{'sup': −Y', '−9, 'the increments of 10are ...

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Номер записи: 14
22-08-2013 дата публикации

Multi-interface compatible bus over a common physical connection

Номер: US20130215911A1
Автор: David P. Chengson, Jaya Bandyopadhyay
Принадлежит: Juniper Networks Inc

A multi-interface bus allows for different bus standards to be implemented over the same set of physical bus lines. More particularly, in one implementation, the system includes a first circuit board, a second circuit board, and a bus connecting the first and second circuit boards. The second circuit board is configured to communicate with the first circuit board using either a synchronous or an asynchronous bus protocol determined based on a bus protocol used by the first circuit board.

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Номер записи: 15
29-08-2013 дата публикации

Information processing apparatus, control method therefor, and recording medium

Номер: US20130222614A1
Автор: Toshiyuki Takagi
Принадлежит: Canon Inc

An information processing apparatus capable of communicating with a first external device storing first time information and a second external device storing second time information, the information processing apparatus, includes a storage unit configured to store third time information, a reception unit configured to receive the first time information, a time adjustment unit configured to regularly adjust the third time information based on the first time information, an operation unit configured to receive a synchronization instruction from a user, a time synchronization unit configured to communicate with the second external device and synchronize the second time information and the third time information if the synchronization instruction is received by the operation unit, and a notification unit configured to notify the user that the third time information can be adjusted by the time adjustment unit in a case of the synchronization instruction being received by the operation unit.

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Номер записи: 16
19-09-2013 дата публикации

MEMORY CONTROLLER WITH FLEXIBLE DATA ALIGNMENT TO CLOCK

Номер: US20130243137A1
Автор: PYEON Hong Beom
Принадлежит: MOSAID TECHNOLOGIES INCORPORATED

A system includes a memory controller and a plurality of memory devices that are connected in-series to the memory controller. The system operation is synchronous with clock that is provided in a fashion of source synchronous clock structure. The source synchronous clock structure includes a PLL (Phase-Locked Loop) that reshapes an incoming clock and a reshaped clock is provided. The PLL provides a shifted clock in phase of 90°. The phase-shifted clock and data are transmitted from the first device to the second device. Clock phase shift provides a center-edge clock with data to be transmitted. The devices are assigned with unique IDs. The least significant bit of the ID number of the last device is used for determination of clock alignment: edge- or center-aligned clock with data produced by the memory controller. 1. An apparatus for communicating with a plurality of devices connected in-series that employs source synchronous clocking , the apparatus comprising:an information detector for detecting number information relating to the number of devices connected in-series; anda clock producer for producing a clock signal in response to the detected number information, the produced clock signal being used for synchronizing communication between the apparatus and the devices.2. The apparatus of wherein the information detector comprises:an identifier detector for detecting a device identifier (ID) associated with one of the series-connected devices and providing the detected device ID as the detected number information to the clock producer.3. The apparatus of wherein the identifier detector comprises:a bit information detector for detecting information on one of bits included in the device ID.4. The apparatus of wherein the bit information detector comprises:a bit number determiner for determining whether a least significant bit (LSB) of the device ID is “1” or “0” and providing a determination result as the detected number information, the aligned clock signal being ...

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Номер записи: 17
19-09-2013 дата публикации

Method of Synchronizing Two Electronic Devices of a Wireless Link, in Particular of a Mobile Telephone Network and System for Implementing This Method

Номер: US20130243142A1
Автор: Alain Rolland, Jean-Christophe Plumecoq, Stephane Blanc
Принадлежит: E-Blink

A method of synchronizing two electronic devices connected by a wireless link with at least one path including a transmission channel and a reception channel. The two devices are included in a network, such as a mobile telephone network. Synchronization information is transmitted directly from one electronic device to the other, as a clock pilot signal, via the channels. After recovery, the clock pilot signal is used for synchronization of a reference frequency of the receiving electronic device.

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Номер записи: 18
26-09-2013 дата публикации

Methods and apparatus for providing one-arm node clustering using a port channel

Номер: US20130250952A1
Автор: Chao Feng, Diheng Qu, Nitesh G. Soni, Pramod Cherukumilli, Samar Sharma, Suresh Kumar Nalluru
Принадлежит: Cisco Technology Inc

Methods and apparatus for providing one-arm node clustering using a port channel are provided herein. An example application node may be communicatively connected to at least one application node, and the application node may be connected to a network through a port channel. The application node may include: a link included in the port channel for accommodating the network data being communicated between the remote client and server; and a processor configured to send/receive a cluster control packet to/from the at least one application node through the link included in the port channel.

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Номер записи: 19
10-10-2013 дата публикации

Digital phase locked loop circuitry and methods

Номер: US20130265179A1
Автор: Chong H. Lee, Ramanand Venkata
Принадлежит: Altera Corp

Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.

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Номер записи: 20
17-10-2013 дата публикации

TRANSMISSION DEVICE, TRANSMISSION METHOD AND COMPUTER PROGRAM

Номер: US20130272352A1
Автор: Kamada Shinya
Принадлежит: NEC Corporation

Provided is a transmission device that transmits or receives synchronous data used to perform synchronization of a clock through a transmission path having a variable transmission band and includes a transmission band acquiring unit that acquires a current transmission band in the transmission path, a calculating unit that calculates a time necessary until the synchronous data is received after the synchronous data is transmitted through the transmission path based on the transmission band, and accumulates the calculated time and a staying time of the synchronous data in its own device as delay information recorded in the synchronous data, and a transmitting unit that writes a value of a result of accumulation by the calculating unit to the synchronous data as new delay information of the synchronous data, and transmits the synchronous data. 1. A transmission device that transmits or receives synchronous data used to perform synchronization of a clock through a transmission path having a variable transmission band , comprising:a transmission band acquiring unit that acquires a current transmission band in the transmission path;a calculating unit that calculates a time necessary until the synchronous data is received after the synchronous data is transmitted through the transmission path based on the transmission band, and accumulates the calculated time and a staying time of the synchronous data in its own device as delay information recorded in the synchronous data; anda transmitting unit that writes a value of a result of accumulation by the calculating unit to the synchronous data as new delay information of the synchronous data, and transmits the synchronous data.2. The transmission device according to claim 1 ,wherein the calculating unit stores a size of the synchronous data in advance, and calculates a time necessary until the synchronous data is received after the synchronous data is transmitted through the transmission path by dividing the size by the ...

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Номер записи: 21
17-10-2013 дата публикации

DISTRIBUTED DIGITAL REFERENCE CLOCK

Номер: US20130272463A1
Автор: Fischer Larry G., Hart David, Uyehara Lance K., Zavadsky Dean
Принадлежит:

A communication system includes master host unit, hybrid expansion unit, and remote antenna unit. Master host unit communicates analog signals with service provider interfaces. Master host unit and hybrid expansion unit communicate N-bit words of digitized spectrum over communication link. Hybrid expansion unit converts between N-bit words and analog spectrum. Hybrid expansion unit and remote antenna unit communicate analog spectrum over analog communication medium. Remote antenna unit transmits and receives wireless signals over air interfaces. Master host unit includes master clock distribution unit that generates digital master reference clock signal. Master host unit communicates digital master reference clock signal over communication link. Hybrid expansion unit receives digital master reference clock signal from master host unit over communication link and generates analog reference clock signal based on digital master reference clock signal. Hybrid expansion unit sends, and remote antenna unit receives, analog reference clock signal across analog communication medium. 1. A communication system , comprising:a master host unit adapted to communicate digital signals with a plurality of service provider interfaces, wherein the master host unit includes a master clock distribution unit that generates a digital master reference clock signal;a plurality of communication links coupled to the master host unit, wherein the master host unit is further adapted to communicate digitized spectrum in N-bit words over the plurality of communication links;the master host unit further adapted to interface between the digital signals for the plurality of service provider interfaces and N-bit words of digitized spectrum for the plurality of communication links;the master host unit further adapted to communicate the digital master reference clock signal over the plurality of communication links;at least one hybrid expansion unit, communicatively coupled to the master host unit ...

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Номер записи: 22
24-10-2013 дата публикации

NICAM Decoder with Output Resampler

Номер: US20130282385A1
Автор: Matthew F. Easley, Matthew S. Barnhill, Roger R. Darr
Принадлежит: THAT Corp

A NICAM audio signal re-sampler may include a non-linear interpolator configured to interpolate in a non-linear manner between sequential digital samples that are based on a stream of demodulated NICAM audio samples. A phase differential calculator may be included that compares phase information at different resolutions.

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Номер записи: 23
31-10-2013 дата публикации

Device and method for preventing lost synchronization

Номер: US20130287154A1
Автор: Masato Tomita
Принадлежит: Fujitsu Semiconductor Ltd

A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a synchronization clock from received data. A connection failure processor performs a connection failure process if synchronization based on the synchronization clock between connection nodes is not established when a first predetermined time from when the reception of the received data is started elapses. A correction processor corrects operation of the CDR circuit if synchronization based on the synchronization clock between connection nodes is not established when a second predetermined time, which is shorter than the first predetermined time, from when the reception of the received data is started elapses.

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Номер записи: 24
14-11-2013 дата публикации

Wireless Clock Distribution

Номер: US20130301519A1
Автор: Rofougaran Ahmadreza
Принадлежит:

Aspects of a method and system for 60 GHz wireless clock distribution may include configuring a microwave communication link established between a first chip and a second chip via a wireline communication bus. The configuration may comprise adjusting beamforming parameters of a first antenna array communicatively coupled to the first chip, and of a second antenna array communicatively coupled to the second chip. The first chip and the second chip may communicate a clock signal via said microwave communication link. The microwave communication link may be routed via one or more relay chips, when the first chip and the second chip cannot directly communicate. Control data may be transferred between the first chip, the second chip, and/or the one or more relay chips, which may comprise one or more antennas. The relay chips may be dedicated relay ICs or multi-purpose transmitter/receivers. 124-. (canceled)25. A wireless clock distribution system being operable to:configure a first wireless link between a first chip and a second chip by communicating messages over a first wireline communication bus that couples said first chip and said second chip;configure a second wireless link between said first chip and a third chip by communicating messages over a second wireline communication bus that couples said first chip and said third chip;relay a clock signal from said third chip to said second chip by said second wireless link and said first wireless link.26. The wireless clock distribution system of claim 25 , wherein said first chip relays said clock signal.27. The wireless clock distribution system of claim 25 , wherein said messages communicated over said first wireline communication bus comprise control data.28. The wireless clock distribution system of claim 25 , wherein said messages communicated over said second wireline communication bus comprise control data.29. The wireless clock distribution system of claim 25 , wherein said messages communicated over said first ...

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Номер записи: 25
09-01-2014 дата публикации

Electronic circuit and communication method

Номер: US20140010317A1
Автор: Akio Sasaki, Yukihiko OSHIKIRI
Принадлежит: Fujitsu Ltd

An electronic circuit includes: a memory, and a processor coupled to the memory, configured to sample a transmission signal at an edge timing of a pulse of a clock signal for synchronizing with a counterpart electronic circuit, transmit a sampled transmission signal to the counterpart electronic circuit, receive a response signal sent from the counterpart electronic circuit in response to the sampled transmission signal, and set any one of a rising edge and a falling edge of the clock signal as an edge trigger for a sampling timing of the sampling according to a reception result of the response signal.

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Номер записи: 26
06-02-2014 дата публикации

System Access and Synchronization Methods for MIMO OFDM Communications Systems and Physical Layer Packet and Preamble Design

Номер: US20140036823A1
Автор: Jianglei Ma, Ming Jia, Peiying Zhu, Wen Tong
Принадлежит: Apple Inc

A method and apparatus are provided for performing acquisition, synchronization and cell selection within an MIMO-OFDM communication system. A coarse synchronization is performed to determine a searching window. A fine synchronization is then performed by measuring correlations between subsets of signal samples, whose first signal sample lies within the searching window, and known values. The correlations are performed in the frequency domain of the received signal. In a multiple-output OFDM system, each antenna of the OFDM transmitter has a unique known value. The known value is transmitted as pairs of consecutive pilot symbols, each pair of pilot symbols being transmitted at the same subset of sub-carrier frequencies within the OFDM frame.

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Номер записи: 27
05-01-2017 дата публикации

Clock Frequency Adjustment for Semi-Conductor Devices

Номер: US20170005779A1
Автор: Rowland Paul
Принадлежит:

A method and an apparatus for clocking data processing modules, with different average clock frequencies and for transferring data between the modules are provided. The apparatus includes a device for providing a common clock signal to the modules. Clock pulses are deleted from the common clock signal to individual modules in dependence on the clocking frequency required by each module. The clock pulses are applied to the modules between which the data is to be transferred at times consistent with the data transfer. 1. A method of providing a clock signal to a processing module comprising:receiving a clock signal at a clock deletion circuit, the clock signal having a pattern of pulses and a duty cycle;generating a control signal in dependence on a clock frequency required by the processing module;at the clock deletion circuit, modifying the clock signal by removing one or more pulses from the pattern of pulses in dependence on the control signal; andproviding the modified clock signal to the processing module.2. A method as claimed in claim 1 , wherein the modified clock signal has a different frequency and duty cycle to the clock signal.3. A method as claimed in claim 2 , wherein the pulses of the clock signal have a first duration and the modified clock signal has pulses of the first duration.4. A method as claimed in claim 1 , wherein the clock frequency required by the processing module is variable.5. A method as claimed in claim 1 , wherein the clock frequency required by the processing module is dependent on algorithms running on the processing module.6. A method as claimed in claim 1 , wherein the modifying step comprising gating the clock signal so as to remove the one or more pulses.7. A method as claimed in claim 1 , wherein the clock signal is modified in dependence on a data element to be transferred to or from the processing module.8. A method as claimed in claim 1 , wherein the modifying step comprises retaining one or more pulses from the pattern of ...

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Номер записи: 28
05-01-2017 дата публикации

TRANSMISSION DEVICE, RECEPTION DEVICE, AND TRANSCEIVER SYSTEM

Номер: US20170005784A1
Автор: Miura Satoshi
Принадлежит: THINE ELECTRONICS, INC.

The present embodiment relates to, for example, a transceiver system capable of notifying a transmission device of an asynchronous state of a reception device with a simple configuration. The reception device includes an input unit, a synchronous-state detector, a resistance-value controller, and a terminal resistor. When the synchronous-state detector detects the asynchronous state, the resistance-value controller sets a resistance value of the terminal resistor to a resistance value indicating the asynchronous state. The transmission device includes an output unit, an amplitude detector, an output controller, and a transmission resistor. The output controller causes the output unit to output a signal constituting normal data including clock information when the synchronous state of the reception device is detected, and causes the output unit to output a signal constituting training data including the clock information when the asynchronous state of the reception device is detected. 1. A transmission device comprising:an output unit connected to a reception device through a transmission line, and configured to output a signal constituting data including clock information embedded therein to the reception device;an amplitude detector configured to detect amplitude of the signal output from the output unit in order to determine whether the reception device is in any of different types of states including a synchronous state in which the signal and a clock recovered from the signal are synchronous and an asynchronous state in which the signal and the clock are asynchronous; andan output controller configured to control a signal output action of the output unit to cause the output unit to output a signal constituting significant data including the clock information, to be transmitted to the reception device in the synchronous state, in accordance with a detection result of the amplitude in a first range indicating the synchronous state, detected by the amplitude ...

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Номер записи: 29
05-01-2017 дата публикации

COMMUNICATION APPARATUS, CONTROL METHOD THEREOF, AND STORAGE MEDIUM

Номер: US20170006125A1
Автор: FUJII Kenichi, SAKAI Tomoya, Yasuma Kensuke
Принадлежит:

A communication apparatus for communicating a push message with another communication apparatus, comprises an obtaining unit configured to obtain time information to synchronize a period in which processing related to the push message is possible with the other communication apparatus; and a communication unit configured to execute, during a period of processing in which the processing related to the push message is possible and which is specified based on the time information obtained by the obtaining unit, push message communication with the other communication apparatus. 1. A communication apparatus for communicating a push message with another communication apparatus , comprising:an obtaining unit configured to obtain time information to synchronize a period in which processing related to the push message is possible with the other communication apparatus; anda communication unit configured to execute, during a period of processing in which the processing related to the push message is possible and which is specified based on the time information obtained by the obtaining unit, push message communication with the other communication apparatus.2. The apparatus according to claim 1 , further comprising:a request unit configured to request proxy processing of the push message communication to the other communication apparatus,wherein the communication unit executes, during the period of the processing in which the processing related to the push message is possible and which is specified based on the time information obtained by the obtaining unit, push message communication with an external apparatus via the other communication apparatus.3. The apparatus according to claim 2 , further comprising:a reception unit configured to receive, as a response to the request by the request unit, a message indicating whether the proxy processing is possible from the other communication apparatus,wherein the communication unit executes, in accordance with reception of a message ...

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Номер записи: 30
07-01-2016 дата публикации

STORAGE SYSTEM AND CONTROL METHOD FOR STORAGE SYSTEM

Номер: US20160006810A1
Автор: CHIBA Takeru, Kawaguchi Tomohiro, Saito Hideo
Принадлежит:

A virtual storage apparatus based on a plurality of storage apparatuses including a first storage apparatus and a second storage apparatus is provided to a host computer. A first logical unit of the first storage apparatus and a second logical unit of the second storage apparatus are provided to the host computer in a form of a virtual logical unit. The first storage apparatus is configured to return a response to an inquiry about port statuses from the host computer designating the virtual logical unit, the response indicating that the status of the first port is a status as indicated by the first port management information and the second storage apparatus is unavailable to respond to the inquiry about port statuses. The second storage apparatus is configured to return no response to the inquiry. 1. A storage system configured to provide a host computer with a virtual storage apparatus based on a plurality of storage apparatuses including a first storage apparatus and a second storage apparatus capable of communicating with each other ,the first storage apparatus being configured to provide a first logical unit and including a first port associated with the first logical unit and first port management information including information on a status of the first port, andthe second storage apparatus being configured to provide a second logical unit and including a second port associated with the second logical unit and second port management information including information on a status of the second port,wherein the first logical unit and the second logical unit are provided to the host computer in a form of a virtual logical unit,wherein the first storage apparatus is configured to return a response to an inquiry about port statuses from the host computer designating the virtual logical unit, the response indicating that the status of the first port is a status as indicated by the first port management information and the second storage apparatus is unavailable to ...

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Номер записи: 31
04-01-2018 дата публикации

SHORT RANGE RADIO COMMUNICATION DEVICE AND A METHOD OF CONTROLLING A SHORT RANGE RADIO COMMUNICATION DEVICE

Номер: US20180006681A1
Автор: BI DONGSHENG, ERIKSSON HAKAN MAGNUS
Принадлежит:

A short range radio communication device and a method of controlling a short range radio communication device may include a processing circuit configured to: determine a time offset between an initial starting point of operation of a transceiver in accordance with a first frequency hopping sequence and a shifted starting point of operation of the transceiver in accordance with the first frequency hopping sequence so that a first segment of a frequency range is exclusive of a second segment of the frequency range; and control at least one of a controller and a clock circuit to operate the transceiver in accordance with the first frequency hopping sequence at the shifted starting point. 1. A short range radio communication device comprising:a transceiver;a clock circuit;a controller configured to operate the transceiver in a frequency range in accordance with a first frequency hopping sequence consisting of frequencies in a first segment of the frequency range and a second frequency hopping sequence consisting of frequencies in a second segment of the frequency range, wherein the first frequency hopping sequence and the second frequency hopping sequence are synchronized with the clock circuit, and determine a time offset between an initial starting point of operation of the transceiver in accordance with the first frequency hopping sequence and a shifted starting point of the operation of the transceiver in accordance with the first frequency hopping sequence so that the first segment is exclusive of the second segment; and', 'control at least one of the controller and the clock circuit to operate the transceiver in accordance with the first frequency hopping sequence at the shifted starting point., 'a processing circuit configured to2. The short range radio communication device of claim 1 ,wherein the shifted starting point is different from the initial starting point.3. The short range radio communication device of claim 1 ,wherein the processing circuit is further ...

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Номер записи: 32
04-01-2018 дата публикации

DATA ON CLOCK LANE OF SOURCE SYNCHRONOUS LINKS

Номер: US20180006797A1
Автор: GUPTA Nitin, NANDY Tapas
Принадлежит:

A source synchronous data transmission system includes a data transmitting device and a data receiving device. A dedicated data line carries a data signal from the data transmission device to the data receiving device. A dedicated clock line carries a modulated clock signal from the data transmission device to the data receiving device. The data transmission device includes a clock data driver configured to encode data into the modulated clock signal by modulating an amplitude of the modulated clock signal. Thus, the clock line of the source synchronous data transmission system carries the clock signal and additional data. 1. A device , comprising:a clock signal generator configured to generate a clock signal;a data source;a clock data driver coupled to the clock signal generator and to the data source, the clock data driver including a modulation circuit configured to generate a modulated clock signal, based on the clock signal, that encodes first data from the data source into the modulated clock signal by modulating an absolute value of an amplitude of the clock signal based on a value of the first data, the clock data driver modulates the amplitude of the clock signal between a first threshold value and a second threshold value, the first and second threshold values representing respective data values of the first data; anda clock output coupled to the clock data driver, the clock output configured to output the modulated clock signal to a receiving device.2. The device of wherein the modulation circuit includes:first and second output nodes;a plurality of first switches, each of the first switches being coupled to a respective resistor between a first voltage node and the first output node;a plurality of second switches, each of the second switches being coupled to a respective resistor between a second voltage node and the first output node;a plurality of third switches, each of the third switches being coupled to a respective resistor between the first ...

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Номер записи: 33
04-01-2018 дата публикации

METHODS AND NODES FOR SYNCHRONIZED STREAMING OF A FIRST AND A SECOND DATA STREAM

Номер: US20180007112A1
Автор: Åkerfeldt Erik
Принадлежит:

Disclosed is a method performed by a system of a communications network. The method comprises encoding the first data stream and the second data stream, analyzing time data related to the first and second data stream, in order to determine a time relationship between the first and second data streams. The method comprises creating an offset file comprising the time relationship between the first and second data streams and transmitting the first data stream, the first time metadata, the second time metadata and the offset file. The method comprises receiving the first data stream, the first time metadata, the second time metadata and the offset file and streaming the first data stream. The method comprises determining a start time for the second data stream, obtaining the second data stream and streaming the second data stream, such that the first and second data streams and synchronized. 1. A method performed by a system of a communications network , the network comprising a server and the system further comprising at least one client device , for synchronized streaming of at least two data streams , the at least two data streams being related to a same event , wherein the method comprises the steps of:encoding, by the server, the first data stream and the second data stream;analyzing, by the server, time data related to the first and second data stream, in order to determine a time relationship between the first and second data streams;creating, by the server, an offset file comprising the time relationship between the first and second data streams;transmitting, by the server, the first data stream, the second data stream, the first time metadata, the second time metadata and the offset file;receiving, by the client device, the first data stream, the first time metadata, the second time metadata and the offset file;streaming, by the client device, the first data stream;determining, by the client device, a start time for the second data stream;obtaining, by the ...

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Номер записи: 34
02-01-2020 дата публикации

Serializer/Deserializer (SerDes) Lanes with Lane-by-Lane Datarate Independence

Номер: US20200007305A1
Автор: Meninger Scott E.
Принадлежит:

A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques. 1. A circuit on a chip for serial data applications , the circuit comprising:an integer phase-locked loop (PLL) having a multiplying factor; anda serializer/deserializer (SerDes) lane, the SerDes lane including a fractional-N (frac-N) PLL, the frac-N PLL including an out-of-band parasitic pole, the multiplying factor in combination with the out-of-band parasitic pole configured to suppress quantization noise introduced by modulating the frac-N PLL.2. The circuit of claim 1 , wherein the integer PLL is configured to produce an on-chip reference clock signal from an off-chip reference clock signal and wherein the on-chip reference clock signal is distributed to the frac-N PLL and is higher in frequency relative to the off-chip reference clock signal.3. The circuit of claim 1 , wherein the multiplying factor is configured to effect a frequency of the quantization noise to enable the frac-N PLL to filter at least a portion of the quantization noise.4. The circuit of claim 1 , wherein the frac-N PLL further includes a divider with a divide value claim 1 , wherein the multiplying factor is configured to ...

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Номер записи: 35
03-01-2019 дата публикации

DEMODULATOR FOR PULSE-WIDTH MODULATED CLOCK SIGNALS

Номер: US20190007243A1
Автор: Burbano Oscar Sebastian, Nelson Reuben P.
Принадлежит:

A demodulator for pulse-width modulated clock signals is disclosed. In one aspect, the demodulator includes an edge detector configured to detect transitions in a reference clock and output a signal indicative of timing of the detected transitions. The demodulator may also include a modulation detection circuit configured to identify modulation events of at least one pulse-width modulated pulse in the reference clock based on the signal output from the edge detector and output a signal indicative of the at least one pulse-width modulated pulse modulation event being identified. The demodulator may further include a retiming circuit configured to generate an output clock synchronized with the at least one pulse-width modulated pulse modulation event based on the signal output from the modulation detection circuit. 1. A clock demodulation circuit for synchronizing an output clock with a pulse-modulated reference clock , the demodulation circuit comprising:an edge detector configured to detect transitions in the reference clock and output a signal indicative of timing of the detected transitions;a modulation detection circuit configured to identify modulation events of at least one pulse-width modulated pulse in the reference clock based on the signal output from the edge detector and output a signal indicative of the at least one pulse-width modulated pulse modulation event being identified; anda retiming circuit configured to generate an output clock synchronized with the at least one pulse-width modulated pulse modulation event based on the signal output from the modulation detection circuit.2. The demodulation circuit of claim 1 , further comprising:a sampling clock input configured to receive a sampling clock, the sampling clock having a higher frequency than the reference clock,wherein the edge detector is further configured to oversample the reference clock at a rate defined by the sampling clock.3. The demodulation circuit of claim 2 , wherein the sampling ...

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Номер записи: 36
03-01-2019 дата публикации

Identifying a synchronization master for radio nodes

Номер: US20190007916A1
Автор: Paul Petrus, Rajiv Gupta, Shailender Potharaju, Yves ETEVE
Принадлежит: ARRIS Enterprises LLC, Ruckus Wireless Inc

A radio node may calculate one or more performance metrics based on measured satellite signals, which are associated with a global positioning system, or wireless signals that are associated with a cellular-telephone network. Then, the radio node may determine, based on the one or more performance metrics, whether the radio node is a synchronization master in a cluster of radio nodes. When the radio node is the synchronization master, the radio node may provide information intended for a computer specifying that the radio node is the synchronization master and the one or more performance metrics. In response, the radio node may receive a synchronization request associated with another radio node in the cluster. Furthermore, the radio node may provide the synchronization information intended for the other radio node, where the synchronization information specifies time, frequency, and phase synchronization for at least the cluster.

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Номер записи: 37
11-01-2018 дата публикации

Systems and Methods for Wellbore Logging to Adjust for Downhole Clock Drift

Номер: US20180010445A1
Автор: CHENG Arthur Chuen Hon, COOPER Andrew Andrew
Принадлежит: Halliburton Energy Services, Inc.

A method for logging a wellbore includes positioning a downhole tool having a downhole clock in the wellbore, logging the wellbore with the downhole tool, transmitting a surface signal from a wellbore surface to the downhole tool, and receiving the surface signal at the downhole tool. The method also includes transmitting a downhole signal from the downhole tool to the surface, receiving the downhole signal at the wellbore surface, and determining clock drift based on an arrival time of the surface signal at the downhole tool and an arrival time of the downhole signal at the wellbore surface. 1. A method for logging a wellbore , the method comprising:positioning a downhole tool comprising a downhole clock in the wellbore;logging the wellbore with the downhole tool;transmitting a surface signal from a wellbore surface to the downhole tool;receiving the surface signal at the downhole tool;transmitting a downhole signal from the downhole tool to the surface;receiving the downhole signal at the wellbore surface;determining clock drift based on an arrival time of the surface signal at the downhole tool and an arrival time of the downhole signal at the wellbore surface.2. The method of claim 1 , wherein transmitting the surface signal comprises performing transmission of a data sequence from the wellbore surface to the downhole tool using at least one of mud-pulse telemetry claim 1 , electromagnetic telemetry claim 1 , and acoustic telemetry.3. The method of claim 1 , wherein transmitting the downhole signal comprises transmitting a data sequence from the downhole tool to the wellbore surface using at least one of mud-pulse telemetry claim 1 , electromagnetic telemetry claim 1 , and acoustic telemetry.4. The method of claim 1 , wherein transmitting the surface signal and transmitting the downhole signal comprise transmitting using a symmetric communication channel.5. The method of claim 1 , further comprising transmitting the downhole signal at a given time after the ...

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Номер записи: 38
11-01-2018 дата публикации

SYSTEMS AND METHODS FOR THE DESIGN AND IMPLEMENTATION OF AN INPUT AND OUTPUT PORTS FOR CIRCUIT DESIGN

Номер: US20180013540A1
Автор: FONG David, GIACONI Stefano, PRYOR Matthew, RINALDI Giacomo, TREVISAN MOREIRA Matheus
Принадлежит:

Systems and methods for providing input and output ports to connect to channels are provided. Input and output ports are the basic building blocks to create more complex data routing IP blocks. By aggregating these modular ports in different ways, different implementations of crossbar or Network on Chip (NoC) can be implemented, allowing flexible routing structure while maintaining all the benefits of channels such as robustness against delay variation, data compression and simplified timing assumptions. 1. An input port configured to accept a bundle of channels at an input and to convert and route the bundle of channels to a plurality of outputs , the input port comprising:a converter coupled with the bundle of channels at the input and configured to convert input encoding associated with data streams provided via the bundle of input channels to the encoding desired within an associated IP block;a buffer stage coupled with the converter configured to improve throughput for the data-path;a router configured to decompress address and then forward the data streams to the appropriate output of the plurality of outputs;a Quality of Service (QOS)/Fault Tolerant (FT) block configured to influence the routing selection for the data streams based on routing priority for resource sharing so that QoS is maintained, to avoid faulty link paths, or both; andoutput buffers configured to improve throughputs.2. The input port of claim 1 , wherein the router is further configured to decompress (QoS) information when the compression ratio used in the bundle of input channels is greater than 1.3. An output port configured to accept multiple bundles of channels at an input and to arbitrate and convert one of the bundles of channels to an associated output claim 1 , the output port comprising:buffer stages configured to improve data throughput for data streams associated with the multiple bundles of input channels;an arbiter configured to select which of the multiple bundle of channels ...

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Номер записи: 39
11-01-2018 дата публикации

METHOD AND DEVICE FOR SYNCHRONIZNG INPUT/OUTPUT SIGNALS BY RADIO FREQUENCY UNIT IN WIRELESS COMMUNICATION SYSTEM

Номер: US20180013542A1
Автор: IM Jaehyung, MARTYNOVICH Pavel, MIN Taeyoung, WOO Youngyoon
Принадлежит:

The present invention relates to an input/output signal synchronization method by a radio frequency unit. The input/output signal synchronization method according to the present invention comprises the steps of: generating a transmitter (Tx) input signal by adding, to a baseband signal, a test signal located at a frequency out of an operation frequency range of the radio frequency unit; collecting the Tx input signal and a Tx output signal obtained by outputting the input signal through a Tx function block; and synchronizing the Tx input signal and the Tx output signals, based on a result obtained by the collecting. 1. A method for synchronizing input/output signals of a radio frequency unit , comprising:generating a transmitter (Tx) input signal by adding, to a baseband signal, a test signal located at a frequency out of an operation frequency range of the radio frequency unit;collecting the Tx input signal and a Tx output signal obtained by outputting the input signal through a Tx function block; andsynchronizing the Tx input signal and the Tx output signal, based on a result obtained by the collecting.2. The method of claim 1 , wherein the test signal is removed by a filter not to affect an output signal transmitted through an antenna.3. The method of claim 1 , wherein the test signal is a pre-stored signal.4. The method of claim 1 , wherein the Tx function block includes at least one of a mixer claim 1 , a digital to analog converter (DAC) claim 1 , and a power amplifier.5. The method of claim 1 , wherein in the synchronizing claim 1 , a cross correlation between the Tx input signal and the Tx output signal is used.6. The method of claim 1 , wherein the test signal includes white Gaussian noise in a specific frequency range.7. A method for performing a digital pre-distortion (DPD) operation of a radio frequency unit claim 1 , comprising:generating a transmitter (Tx) input signal by adding, to a baseband signal, a test signal located at a frequency out of an ...

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Номер записи: 40
11-01-2018 дата публикации

PHASE CALIBRATION OF CLOCK SIGNALS

Номер: US20180013544A1
Автор: Aleksic Marko, Li Simon, Vu Roxanne
Принадлежит:

A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path. 1. A receiver comprising:a first sampling circuit to generate first digital samples based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal;a second sampling circuit to generate second digital samples based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal; and phase align the second clock signal with transitions of the input signal while the first clock signal is at a first phase and the first digital samples are selected as output data of the receiver,', 'phase align the first clock signal with transitions of the input signal while the second clock signal is at a second phase and the second digital samples are selected as the output data of the receiver,', 'determine a phase error between the first clock signal and the second clock signal in response to phase aligning the second clock signal with transitions of the input signal and phase aligning the first clock signal with transitions of the input signal; and', 'adjust at least one of the first phase or the second phase based on the phase error to phase align the first clock signal with the second clock signal., 'circuitry adapted to2. The receiver of claim 1 , wherein the ...

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Номер записи: 41
11-01-2018 дата публикации

DEVICE INCLUDING SINGLE WIRE INTERFACE AND DATA PROCESSING SYSTEM INCLUDING THE SAME

Номер: US20180013546A1
Автор: Huh Jun Ho, Jang Ho Rang, KIM Chul Jin, Lee Suh Ho, SCHERRER TOMAS
Принадлежит:

A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process. 110-. (canceled)11. A data processing system comprising: a first single pad;', 'a first control circuit;', 'a first frame generator configured to generate a first frame based on a control of the first control circuit; and', 'a first processing circuit configured to generate a first oversampling clock signal from a clock signal, configured to select one among a plurality of first clock phases of the first oversampling clock signal, and configured to sample a bit value included in a second frame using the same phase as the selected one among the plurality of first clock phases;, 'a master device including a second single pad;', 'a second control circuit;', 'a second frame generator configured to generate the second frame based on a control of the second control circuit; and', 'a second processing circuit configured to generate a second oversampling clock signal from the clock signal, configured to select one among a plurality of second clock phases of the second oversampling clock signal, and configured to sample a bit value included in the first frame using the same phase as the selected one among the plurality of second clock phases;, 'a slave device includinga clock source configured to provide the clock signal to the master device and the slave device; ...

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Номер записи: 42
14-01-2016 дата публикации

SYSTEM ACCESS AND SYNCHRONIZATION METHODS FOR MIMO OFDM COMMUNICATIONS SYSTEMS AND PHYSICAL LAYER PACKET AND PREAMBLE DESIGN

Номер: US20160013925A1
Автор: Jia Ming, Ma Jianglei, Tong Wen, ZHU PEIYING
Принадлежит:

A method and apparatus are provided for performing acquisition, synchronization and cell selection within an MIMO-OFDM communication system. A coarse synchronization is performed to determine a searching window. A fine synchronization is then performed by measuring correlations between subsets of signal samples, whose first signal sample lies within the searching window, and known values. The correlations are performed in the frequency domain of the received signal. In a multiple-output OFDM system, each antenna of the OFDM transmitter has a unique known value. The known value is transmitted as pairs of consecutive pilot symbols, each pair of pilot symbols being transmitted at the same subset of sub-carrier frequencies within the OFDM frame. 1. A transmitter in a communication network , comprising:a plurality of antennas; and map sub-carriers of a header OFDM symbol into a non-contiguous set of sub-carriers for each antenna of the plurality of antennas, wherein not all sub-carriers are used on all transmit antennas;', 'multiplex within the header OFDM symbol at least a dedicated pilot channel on dedicated pilot channel sub-carriers and a broadcasting channel on broadcast channel sub-carriers for each antenna of the plurality of antennas, wherein the broadcast channel comprises information for a particular cell; and', 'transmit each non-contiguous set of sub-carriers using each respective antenna of the plurality of antennas., 'circuitry coupled to the plurality of antennas, wherein the circuitry is configured to2. The transmitter of claim 1 , wherein the transmitter comprises a base station.3. The transmitter of claim 1 , wherein transmitting each non-contiguous set of sub-carriers comprises:transmitting on common synchronization channel sub-carriers for each of the plurality of antennas a complex sequence that is different for each antenna of the plurality of antennas.4. The transmitter of claim 3 , wherein the complex sequence is common for respective antennas of ...

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Номер записи: 43
14-01-2016 дата публикации

Image pickup apparatus, lens apparatus, and image pickup system

Номер: US20160014325A1
Автор: Koji Okada
Принадлежит: Canon Inc

A lens apparatus is detachable from an image pickup apparatus. The lens apparatus includes a controller configured to communicate with the image pickup apparatus in synchronization with a first signal. A communication contains a plurality of blocks in the same cycle of the first signal. The controller transmits information of a first time period to the image pickup apparatus, and prohibits a communication of an m-th block from starting before the first time period passes after a communication of an n-th block starts or ends where n is an integer equal to or larger than 1 and m is an integer larger than n.

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Номер записи: 44
10-01-2019 дата публикации

TIME SYNCHRONOUS SLAVE DEVICE AND COMMUNICATION CONTROL METHOD

Номер: US20190013926A1
Автор: SAKAUE Taichi
Принадлежит: Mitsubishi Electric Corporation

A token management slave device is included in a communication system. The communication system includes a master device, time asynchronous slave devices communicating with the master device and not being time synchronized with the master device, and time synchronous slave devices communicating with the master device and being time synchronized with the master device. The token management slave device sets an asynchronous communication period in which the master device and the time asynchronous slave devices communicate, between a plurality of synchronous communication periods that is a plurality of periods in which the master device and the time synchronous slave devices communicate. Then, the token management slave device instructs the time asynchronous slave devices to communicate with the master device, when the asynchronous communication period arrives. 1. A time synchronous slave device included in a communication system including a master device and a time asynchronous slave device communicating with the master device and not being time synchronized with the master device , the time synchronous slave device communicating with the master device and being time synchronized with the master device , the time synchronous slave device comprising:processing circuitry to:set an asynchronous communication period in which the maser device and the time asynchronous slave device communicate, between a plurality of synchronous communication periods that is a plurality of periods in which the master device and the time synchronous slave device communicate; andinstruct the time asynchronous slave device to communicate with the master device, when the asynchronous communication period arrives.2. The time synchronous slave device according to claim 1 ,wherein the communication system includes a plurality of synchronous slave devices,the time synchronous slave device is selected from the plurality of time synchronous slave devices, andthe processing circuitry sets the ...

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Номер записи: 45
10-01-2019 дата публикации

Serializer, data transmitting circuit, semiconductor apparatus and system including the same

Номер: US20190013928A1
Автор: Hyun bae Lee
Принадлежит: SK hynix Inc

A serializer may include a pre-buffer stage and a main buffer stage. The pre-buffer stage may be configured to generate a plurality of delayed signals by buffering a plurality of signals in synchronization with a plurality of pre-clock signals, respectively. The main buffer stage may be configured to generate an output signal by buffering the plurality of delayed signals in synchronization with a plurality of main clock signals, respectively. The plurality of pre-clock signals may have phase differences from the plurality of main clock signals, respectively.

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Номер записи: 46
10-01-2019 дата публикации

Transmission apparatus, transmission method, reception apparatus, reception method, and transmission/reception system

Номер: US20190014285A1
Автор: Kazuaki Toba, Toshihisa Hyakudai
Принадлежит: Sony Corp

This technology is to enable high quality audio reproduction on the reception side without supplying a transmission clock using a clock signal line from the reception side to the transmission side. The transmission apparatus receives encoded data capable of clock recovery from a reception apparatus (external device), generates an audio clock on the basis of a carrier clock recovered from the encoded data, and transmits audio data to the reception apparatus in synchronization with the audio clock. The reception apparatus transmits the encoded data capable of clock recovery to the external device in synchronization with the carrier clock generated on the basis of an self-generating audio clock, receives the audio data from the transmission apparatus (external device), and processes the audio data on the basis of the self-generating audio clock.

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Номер записи: 47
10-01-2019 дата публикации

FORWARD ERROR CORRECTION USING SOURCE BLOCKS WITH SYMBOLS FROM AT LEAST TWO DATASTREAMS WITH SYNCHRONIZED START SYMBOL IDENTIFIERS AMONG THE DATASTREAMS

Номер: US20190014353A1
Автор: HELLGE Cornelius, HENSEL Manuel, SANCHEZ Yago, SCHIERL Thomas
Принадлежит:

A forward error correction (FEC) data generator has an input for at least two datastreams for which FEC data shall be generated in a joint manner, each datastream having a plurality of symbols. A FEC data symbol is based on a FEC source block possibly having a subset of symbols of the at least two data streams. The FEC data generator further has a signaling information generator configured to generate signaling information for the FEC data symbol regarding which symbols within the at least two datastreams belong to the corresponding source block by determining pointers to start symbols within a first and a second datastream, respectively, of the at least two datastreams and a number of symbols within the first datastream and second datastreams, respectively, that belong to the corresponding source block. 1. A forward error correction data generator comprising:an input for at least two datastreams for which forward error correction data shall be generated in a joint manner, each datastream comprising a plurality of symbols, wherein a forward error correction data symbol is based on a forward error correction (FEC) source block;a signaling information generator configured to generate signaling information for the forward error correction data symbol regarding which symbols within the at least two datastreams belong to the corresponding FEC source block by determining a pointer to a start symbol within a first datastream of the at least two datastreams, a pointer to a start symbol within a second datastream of the at least two datastreams, a number of symbols within the first datastream that belong to the corresponding source block, and a number of symbols within the second datastream that belong to the corresponding source block;a synchronizer configured to determine a common identifier for the start symbols within the at least two datastreams;wherein the signaling information generator is configured to include the common identifier into the signaling information to ...

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Номер записи: 48
09-01-2020 дата публикации

Clock Frequency Adjustment For Semi-Conductor Devices

Номер: US20200014524A1
Автор: Rowland Paul
Принадлежит:

A method and an apparatus for clocking data processing modules, with different average clock frequencies and for transferring data between the modules are provided. The apparatus includes a device for providing a common clock signal to the modules. Clock pulses are deleted from the common clock signal to individual modules in dependence on the clocking frequency required by each module. The clock pulses are applied to the modules between which the data is to be transferred at times consistent with the data transfer. 1. A method of clocking processing modules comprising:providing a common clock to a respective clock deletion circuit for each of a first processing module and a second processing module, wherein the common clock has a pattern of pulses, each pulse having a first duration;at the clock deletion circuit for the first processing module, modifying the common clock by removing one or more pulses from the pattern of pulses so as to provide a first clock signal having pulses of the first duration and a different duty cycle than the common clock;at the clock deletion circuit for the second processing module, modifying the common clock by removing one or more pulses from the pattern of pulses so as to provide a second clock signal having pulses of the first duration and a different duty cycle than the common clock; andproviding the first and second clock signals to the first and second processing modules respectively to use as their clocking signals.2. The method as claimed in claim 1 , wherein the first clock signal has a different duty cycle to the second clock signal.3. The method as claimed in claim 1 , wherein the first clock signal has a different frequency to the second clock signal.4. The method as claimed in claim 1 , wherein:the clock deletion circuit for the first processing module is configured to modify the common clock in dependence on a first clock frequency required by the first processing module; andthe clock deletion circuit for the second ...

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Номер записи: 49
15-01-2015 дата публикации

Automatic Multimedia Upload For Publishing Data And Multimedia Content

Номер: US20150019695A1
Автор: Gurvinder Singh, Marcos Klein, Vince Laviano
Принадлежит: CellSpinSoft Inc

Disclosed herein is a method and system for utilizing a digital data capture device in conjunction with a Bluetooth (BT) enabled mobile device for publishing data and multimedia content on one or more websites automatically or with minimal user intervention. A client application is provided on the BT enabled mobile device. In the absence of inbuilt BT capability, a BT communication device is provided on the digital data capture device. The BT communication device is paired with the BT enabled mobile device to establish a connection. The client application detects capture of data and multimedia content on the digital data capture device and initiates transfer of the captured data, multimedia content, and associated files. The digital data capture device transfers the captured data, multimedia content, and the associated files to the client application. The client application automatically publishes the transferred data and multimedia content on one or more websites.

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Номер записи: 50
18-01-2018 дата публикации

MATRIX TOUCH SURFACE OF LARGE DIMENSIONS COMPRISING DOUBLE INJECTION ELECTRONICS OF THE ROWS OR OF THE COLUMNS

Номер: US20180018059A1
Автор: ABADIE Jean-Christophe, CONI Philippe, Renaud Frederic, Sontag Yves
Принадлежит:

A device with touch surface with projected capacitive detection comprising a matrix touchscreen comprises a plurality of conductive rows and of conductive columns, the screen linked to electronic control means generating, for each conductive row and for each conductive column, transmission signals and electronic means for receiving and analysing the reception signals from each conductive row and from each conductive column. Each row of the device comprises, at one of its ends, first means for generating a first transmission signal and first means for receiving a first reception signal and, at its opposite end, second means for generating a second transmission signal and second means for receiving a second reception signal, the first transmission signal and the second transmission signal being synchronous, having the same frequency, the same amplitude and the same phase. 1. A device with touch surface with projected capacitive detection comprising a matrix touchscreen comprising a plurality of conductive rows and of conductive columns , said screen being linked to electronic control means generating , for each conductive row and for each conductive column , transmission signals and electronic means for receiving and analysing the reception signals from each conductive row and each conductive column ,wherein each row comprises, at one of its ends, first means for generating a first transmission signal and first means for receiving a first reception signal and, at its opposite end, second means for generating a second transmission signal and second means for receiving a second reception signal, the first transmission signal and the second transmission signal being synchronous, having the same frequency, the same amplitude and the same phase.2. The device with touch surface according to claim 1 , wherein the first reception means and the second reception means comprise synchronous demodulation means and means for storing:{'sub': REFG', 'REFD, 'reception signals ...

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Номер записи: 51
19-01-2017 дата публикации

DIGITAL ACCESSORY INTERFACE

Номер: US20170019244A1
Автор: Zwart Willem
Принадлежит:

A method for transferring data over a half-duplex wired communications link, comprises, in each of a plurality of frames: 133.-. (canceled)34. A method for transferring data over a half-duplex wired communications link , comprising , in each of a plurality of frames:transferring a synchronization data pattern in a first direction;transferring first payload data in the first direction;transferring second payload data in a second direction opposite to the first direction; andtransferring control data, wherein the format of the frame is such that, irrespective of whether the control data is transferred in the first direction or in the second direction, there is only one pair of reversals of a direction of data transfer in each frame.35. A method as claimed in claim 34 , comprising transferring the control data claim 34 , either in the first direction or the second direction claim 34 , between transferring the synchronization data pattern in the first direction and transferring the second payload data in the second direction.36. A method as claimed in claim 34 , comprising transferring the synchronization data pattern in the first direction at a start of each frame.37. A method as claimed in claim 34 , wherein the synchronization data pattern comprises two symbols of different physical signal levels.38. A method as claimed in claim 34 , wherein the synchronization data pattern consists of only two symbols.39. A method as claimed in claim 34 , comprising transferring first payload data in the first direction for a configurable number of symbols in each frame.40. A method as claimed in claim 34 , comprising transferring second payload data in the second direction for a configurable number of symbols in each frame.41. A method as claimed in claim 34 , comprising transferring control data for four or fewer symbols in each frame.42. A method as claimed in claim 34 , comprising transferring control data for only one symbol in each frame.43. A method as claimed in claim 34 , ...

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Номер записи: 52
21-01-2016 дата публикации

ELECTRONIC DEVICE, DATE AND TIME SETTING METHOD, AND RECORDING MEDIUM

Номер: US20160021501A1
Автор: Sambongi Masao, WATANUKI Masatoshi
Принадлежит: CASIO COMPUTER CO., LTD.

A timer unit to counts a current date and time, a current position acquisition unit to acquire a current position, a determination unit to determine a time zone in which the acquired current position is included, and a local time acquisition unit to calculate local time corresponding to a time difference of the time zone determined by the determination unit are included. When a boundary line of the time zone is along a coastline, the determination unit changes the boundary line from the coastline to a side of a sea in a predetermined distance range and determines a time zone.

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Номер записи: 53
03-02-2022 дата публикации

COMPUTER SYSTEM, CONFIGURATION CHANGE CONTROL DEVICE, AND CONFIGURATION CHANGE CONTROL METHOD

Номер: US20220038339A1
Автор: TAGUCHI Yuta, Yamamoto Nobuyuki
Принадлежит:

Upon receiving an input of data, an input unit transmits a time notification to another input unit and transmits a data notification including the input clock time to a storage unit. Upon receiving a time notification from another input unit, the input unit transmits an empty notification including the input clock time to the storage unit to indicate there is no input before the input clock time. Upon receiving the data notification from an input unit having received the input of data and receiving the notification from the other input unit, the storage unit broadcasts the data in order, assuming that consensus of the plurality of storage units is confirmed. When adding an input unit to a computer system, a control device causes the storage unit to start confirming the consensus including the joining input unit after a window interval has elapsed after the joining input unit starts operation. 1. A computer system that performs total order broadcast , comprising:one or more input units configured to receive input of data and measure an input clock time at which the input of the data is received;a plurality of storage units configured to receive the data from the input units and broadcast the data to a predetermined processing device in the order of the input clock time; anda configuration change control device configured to control configuration change of the computer system, for adding an input unit to the computer system, whereinupon receiving the input of the data, the input unit transmits a time notification including the input clock time to another input unit and transmits a data notification including the data and the input clock time to the storage unit, and upon receiving the clock time notification of an input clock time from another input unit, the input unit transmits an empty notification including the input clock time to the storage unit, the empty notification indicating that there is no input to the input unit at a clock time earlier than the input ...

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Номер записи: 54
18-01-2018 дата публикации

ASYNCHRONOUS WIRELESS SENSING

Номер: US20180019862A1
Автор: Kliewer Joerg, Tang Wei
Принадлежит:

Low-complexity asynchronous wireless sensing and communication architecture is disclosed for low power wireless sensors. Schemes are based on asynchronous digital communications and Ultra-Wideband impulse radios. In asynchronous radio, combination of frequency-shift-keying (FSK) and on-off-keying (OOK) to remove clock synchronization is applied. Improved asynchronous non-coherent transmitters and receivers achieve both low power and low complexity while seamlessly combined with asynchronous level-crossing modulation. Both uncoded and coded asynchronous communication may be utilized. Coded asynchronous communication may use error correction. Forward error correction schemes for asynchronous sensor communication are utilized where dominant errors consist of pulse deletions and insertions, and where instantaneous encoding takes place. Forward error correction is also accomplished where a continuous-time sparse waveform signal is asynchronously sampled and communicated over a noisy channel via Q-ary frequency-shift keying. Concatenated code employs outer systematic convolutional codes and inner embedded marker codes that preserve timing information and protect against symbol insertions and deletions. 1. A method of asynchronous wireless sensing , comprising:utilizing a forward error correction scheme for asynchronous sensor communication, wherein dominant errors consist of pulse deletions and insertions, and encoding is instantaneous;combining a systematic convolutional code, an embedded marker code, and a power-efficient frequency shift keying (FSK) modulation at a sensor node;obtaining decoding via a maximum a-posteriori (MAP) decoder for the marker code to achieve synchronization for an insertion and deletion channel; and then MAP decoding for the convolutional code;wherein, effective data rate and energy efficiency are improved and bit-error-rate (BER) and electromagnetic noise emissions are reduced.2. The method of claim 1 , further includes utilizing both a ...

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Номер записи: 55
18-01-2018 дата публикации

Signal recovery circuit, electronic device, and signal recovery method

Номер: US20180019864A1
Автор: Yukito Tsunoda
Принадлежит: Fujitsu Ltd

A signal recovery circuit includes an oscillator that generates a first clock of which a frequency is variable, and a feedback circuit that controls the oscillator to synchronize the first clock with input data, depending on a phase relationship between the input data and the first clock, the feedback circuit including a control portion that controls the oscillator depending on the phase relationship between the input data and the first clock, a first phase detection circuit that generates a clock phase control signal depending on the phase relationship between the input data and the first clock, an output data generation circuit that generates output data by latching the input data at a change edge of the first clock, and a lock detection circuit that outputs a lock detection signal indicating whether a state is a lock state or a non-lock state.

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Номер записи: 56
17-01-2019 дата публикации

Method for Updating Clock Synchronization Topology, Method for Determining Clock Synchronization Path, and Device

Номер: US20190020463A1
Автор: Jiang Yuanlong, Liu Xian, Xu Jinchun, Zhu Hengjun
Принадлежит:

A method for determining a clock synchronization path, and a device, where the method includes determining a first clock synchronization path from a clock injection node of the first network to the first network element based on a request of the first network element and the clock synchronization topology of the first network. A clock synchronization topology is automatically updated based on clock synchronization capability information of a network element, and a clock synchronization path is determined to reduce costs of deploying a clock synchronization path. 1. A method for determining a clock synchronization path , comprising:receiving a first packet from a first network element, the first packet requesting to determine the clock synchronization path for the first network element, the first network element being a network element in a first network, and the first network element having a clock synchronization capability;determining a first clock synchronization path from a clock injection node of the first network to the first network element based on a clock synchronization topology of the first network, the clock synchronization topology of the first network comprising the clock injection node and the first network element; andsending first instruction information to the first network element instructing to obtain a clock signal from a previous-hop clock synchronization node of the first network element on the first clock synchronization path.2. The method of claim 1 , wherein the first packet further indicates that a second clock synchronization path from the clock injection node to the first network element is faulty claim 1 , and the second clock synchronization path comprising at least one network element not on the first clock synchronization path.3. The method of claim 1 , further comprising:receiving a second packet from the first network element, the second packet comprising clock synchronization capability information of the first network element, ...

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Номер записи: 57
16-01-2020 дата публикации

CLOCKING SCHEME IN NONLINEAR SYSTEMS FOR DISTORTION IMPROVEMENT

Номер: US20200021250A1
Автор: BHATTACHARYYA Prasun Kali, Bhowmik Prasenjit, Ghosh Abhishek
Принадлежит:

Systems and methods are provided for clocking scheme to reduce nonlinear distortion. An example system may include at least two processing paths, each including at least one circuit exhibiting nonlinear behavior. Nonlinearity may be managed during processing of signals, such as by assessing effects of the nonlinear behavior during the processing of signals, and controlling clocking applied via at least one path based on the assessed effects, to reduce the effects of the nonlinear behavior during the processing of signals, eliminating the need for post-processing corrections. The controlling of clocking may include adjusting timing of a clock applied in the at least path, such as by introducing a timing-delay adjustment to a clock when the clock is applied to a circuit after the circuit exhibiting nonlinear behavior. A timing-advancement may be applied to signals processed via the at least one path, particularly before the circuit exhibiting nonlinear behavior. 1. A method comprising: assessing effects of said nonlinear behavior during said processing of signals; and', 'controlling clocking applied via at least one processing path used during said processing of signals, based on said assessed effects,', 'wherein said controlling is configured to reduce said effects of said nonlinear behavior during said processing of signals., 'managing nonlinearity in a transceiver, wherein the transceiver comprises at least two separate processing paths for use when processing signals, and each processing path comprises at least one circuit exhibiting nonlinear behavior during said processing of signals, said managing of nonlinearity comprising2. The method of claim 1 , wherein said controlling of clocking comprises introducing a timing-advancement adjustment to signals processed in said at least one processing path.3. The method of claim 2 , comprising introducing said timing-advancement adjustment before said least one circuit exhibiting nonlinear behavior.4. The method of claim ...

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Номер записи: 58
21-01-2021 дата публикации

SIGNAL GENERATOR

Номер: US20210021368A1
Автор: Harrison Richard, Hill Paul
Принадлежит:

Disclosed is a method of producing an output signal from a signal generator, comprising: determining a driving input to the signal generator, the driving input for driving the signal generator to provide a predetermined output signal, wherein the output signal includes at least one frame, the at least one frame comprising an active period and a dummy period and wherein the active period and dummy period are determined by the driving input. Also disclosed is a method of producing an output signal from a signal generator, comprising: receiving a synchronisation signal; obtaining an input signal for controlling the signal generator to generate an output signal comprising at least one frame wherein the at least one frame comprises at least one active period and at least one dummy period; producing the output signal comprising a series of frames; and, synchronising the output signal with the synchronisation signal by varying a duration of the at least one of the dummy period or active period. 1. A method of producing an output signal from a signal generator , comprising:determining a driving input to the signal generator, the driving input for driving the signal generator to provide a predetermined output signal,wherein the output signal includes at least one frame, the at least one frame comprising an active period and a dummy period and wherein the active period and dummy period are determined by the driving input.2. A method as claimed in claim 1 , further comprising adjusting a duration of one or more of the active period and the dummy period to synchronise the output signal with a synchronisation signal.3. A method as claimed in claim 2 , further comprisingselecting a synchronisation point in the output signal;selecting a synchronisation point in the synchronisation signal; and,determining an offset error which relates to the difference between the two synchronisation points, wherein adjusting the duration of one or more active and dummy period reduces the offset ...

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Номер записи: 59
17-04-2014 дата публикации

Automatic Multimedia Upload For Publishing Data And Multimedia Content

Номер: US20140108552A1
Автор: Gurvinder Singh, Marcos Klein, Vince Laviano
Принадлежит: CellSpinSoft Inc

Disclosed herein is a method and system for utilizing a digital data capture device in conjunction with a Bluetooth (BT) enabled mobile device for publishing data and multimedia content on one or more websites automatically or with minimal user intervention. A client application is provided on the BT enabled mobile device. In the absence of inbuilt BT capability, a BT communication device is provided on the digital data capture device. The BT communication device is paired with the BT enabled mobile device to establish a connection. The client application detects capture of data and multimedia content on the digital data capture device and initiates transfer of the captured data, multimedia content, and associated files. The digital data capture device transfers the captured data, multimedia content, and the associated files to the client application. The client application automatically publishes the transferred data and multimedia content on one or more websites.

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Номер записи: 60
28-01-2016 дата публикации

MULTI-LANE N-FACTORIAL (N!) AND OTHER MULTI-WIRE COMMUNICATION SYSTEMS

Номер: US20160028534A1
Автор: Sengoku Shoichiro
Принадлежит:

System, methods and apparatus are described that facilitate communication of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A receiving device receives a sequence of symbols over a multi-wire link. The receiving device further receives a clock signal via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link. The receiving device decodes the sequence of symbols using the clock signal. In an aspect, a second clock signal is embedded in guaranteed transitions between pairs of consecutive symbols in the sequence of symbols. Accordingly, the receiving device decodes the sequence of symbols using the clock signal received via the dedicated clock line while ignoring the second clock signal. 1. A receiving device , comprising: receive a sequence of symbols over a multi-wire link,', 'receive a clock signal via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link, and', 'decode the sequence of symbols using the clock signal., 'a processing circuit configured to2. The receiving device of claim 1 , wherein:a second clock signal is embedded in guaranteed transitions between pairs of consecutive symbols in the sequence of symbols, andthe processing circuit is configured to decode the sequence of symbols using the clock signal received via the dedicated clock line while ignoring the second clock signal.3. The receiving device of claim 1 , wherein the processing circuit configured to decode is further configured to convert the sequence of symbols to a set of data bits using the clock signal.4. The receiving device of claim 3 , wherein the processing circuit configured to convert the sequence of symbols to the set of data bits is further configured to:use a transcoder to convert the sequence of symbols to a set of transition numbers; andconvert the set of transition numbers to the set of data ...

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Номер записи: 61
29-01-2015 дата публикации

Three phase clock recovery delay calibration

Номер: US20150030112A1
Автор: Chulkyu Lee, George Alan Wiley
Принадлежит: Qualcomm Inc

System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. A clock recovery circuit may be calibrated based on state transitions in a preamble transmitted on two or more connectors. A calibration method is described. The method includes detecting a plurality of transitions in a preamble of a multiphase signal and calibrating a delay element to provide a delay that matches a clocking period of the multiphase signal. Each transition may be detected by only one of a plurality of detectors. The delay element may be calibrated based on time intervals between detections of successive ones of the plurality of transitions.

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Номер записи: 62
28-01-2021 дата публикации

LOW VOLTAGE DRIVE CIRCUIT WITH VARIABLE OSCILLATING FREQUENCIES AND METHODS FOR USE THEREWITH

Номер: US20210026390A1
Автор: JR. Richard Stuart, Markison Timothy W., Morrison Gerald Dale, Seger, Van Ostrand Daniel Keith
Принадлежит: SigmaSense, LLC.

A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; generating a first oscillation at a first frequency; generating a second oscillation at the first frequency; and outputting the first oscillation or the second oscillation on a bit-by-bit basis in accordance with the transmit digital data to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analog outbound data, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit drives an analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus in a first frequency range and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus in a second frequency range. 1. A low voltage drive circuit (LVDC) comprises: generating a DC component that has a magnitude between magnitudes of power supply rails of the transmit digital to analog circuit; and', 'generating, via an output limited digital to analog converter, a first oscillation at a first frequency; generating a second oscillation at second frequency, wherein magnitude of the first and second oscillations is limited to a range that is less than a difference between the magnitudes of power supply rails; and outputting the first oscillation or the second oscillation on a bit-by-bit basis in accordance with the transmit digital data to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analog outbound data;, 'a transmit digital to analog circuit configured to convert transmit digital data into analog outbound data bya receive analog to digital circuit configured to convert analog inbound data into received digital data; ...

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Номер записи: 63
10-02-2022 дата публикации

TWO-WAY OPTICAL TIME TRANSFER USING A PHOTONIC CHIP

Номер: US20220045768A1
Автор: Cingoz Arman, Kowligy Abijith Sudarsan, Roslund Jonathan David
Принадлежит:

Embodiments herein describe sub-picosecond accurate two-way clock synchronization by optically combining received optical pulses with optical pulses generated locally in a photonic chip before the optical signals are then detected by a photodetector to obtain an interference measurement. That is, the optical pulses can be combined to result in different interference measurements. Optically combining the pulses in the photonic chip avoids much of the jitter introduced by the electronics. Further, the sites can obtain multiple interference measurements which can be evaluated to accurately determine when the optical pulses arrive at the site with femtosecond accuracy. 1. A photonic chip comprising:a first optical interface for receiving a first pulse train from an external source, wherein the external source comprises a remote clock, wherein pulses in the first pulse train have a first repetition rate;a second optical interface configured to receive a second pulse train having pulses with the first repetition rate; receive the first and second pulse trains, and', 'generate a control signal to adjust the first repetition rate and a time offset for the second pulse train such that the pulses of the second pulse train are coincident with the pulses of the first pulse train; and, 'a timing discriminator configured toat least one optical interface for outputting an output of the timing discriminator to a photodetector for synchronizing the remote clock to a local clock.2. The photonic chip of claim 1 , wherein the timing discriminator comprises:a first and a second interferometer configured to receive the first and second pulse trains;a first splitter to split and forward the first pulse train to the first and second interferometers; anda second splitter to split and forward the second pulse train to the first and second interferometers.3. The photonic chip of claim 2 , wherein at least one of the first and second interferometers comprises a first optical delay configured ...

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Номер записи: 64
10-02-2022 дата публикации

Communication Device and Method for Operating a Communication System for Transmitting Time Critical Data

Номер: US20220045835A1
Автор: WEICHLEIN Thomas
Принадлежит:

A communication device and method for operating a communication system for transmitting time-critical data, wherein a respective individual time window within predefined time intervals is specified for data flows assigned to selected control applications running on terminals, where time windows each have an individual cycle time that is a multiple of a general cycle time or corresponds to the general cycle time, first and second communication devices each check, for the selected control applications, whether a specified time window is available for data transmission, where information about a beginning of the time window within the predefined time intervals is in each case transmitted to the terminal upon which the respective selected control application is executing in the event of an available time window, and where data flows that are assigned to selected control applications are each transmitted according to the information about the beginning of the individual time window. 111.-. (canceled)12. A method for operating a communication system for transmitting time-critical data , the method comprising:transmitting selected datagrams from first communication devices at source network nodes to second communication devices at destination network nodes within predefined periodic time intervals;assigning the selected datagrams to data streams and transmitting the assigned selected datagrams via paths which comprise third communication devices at intermediate network nodes;synchronizing the predefined periodic time intervals at all network nodes;specify, by terminals connected to the first communication devices, in each particular case, quality of service parameters for the data streams to reserve resources to be provided by the first and third communication devices and second communication devices;specifying, by terminals connected to the second communication devices, in each particular case, a data stream identifier for a reservation request;assuming, by each ...

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Номер записи: 65
02-02-2017 дата публикации

Flash memory controller with calibrated data communication

Номер: US20170031854A1
Автор: Benedict Chung-Kwong Lau, Bruno W. Garlepp, Donald C. Stark, Jared Levan Zerbe, Jun Kim, Kevin S. Donnelly, Leung Yu, Mark A. Horowitz, Roxanne Vu, Stefanos Sidiropoulos, Tsyr-Chyang Ho
Принадлежит: RAMBUS INC

An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

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Номер записи: 66
31-01-2019 дата публикации

Two-wire communication interface system

Номер: US20190036677A1
Автор: Subrahmanya Bharathi Akondy
Принадлежит: Texas Instruments Inc

One example includes a master microcontroller in a communication interface system. The microcontroller includes a transmitter configured to generate a clock signal at a selected frequency and to provide the clock signal to a slave microcontroller on a two-wire communication cable during a clock learning mode. The transmitter can be further configured to provide master data signal requests at the selected frequency on the two-wire communication cable during a data transfer mode. The microcontroller also includes a receiver configured to receive slave data signals at the variable frequency via the two-wire communication cable in response to the master data signal requests during the data transfer mode.

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Номер записи: 67
30-01-2020 дата публикации

SINGLE-LINE SERIAL DATA TRANSMISSION CIRCUIT AND SINGLE-LINE SERIAL DATA TRANSMISSION METHOD

Номер: US20200036504A1
Автор: Fukumoto Yosuke
Принадлежит:

A single-line serial data transmission circuit having a master circuit and a slave circuit , the master circuit having a data clock adder for writes and a data receiver for reads. The slave circuit has an active generator , a data clock separator for writes, and a data transmitter for reads. The master circuit and the slave circuit are connected by one length of a signal line . When the master circuit writes data to the slave circuit , a signal synthesized from a clock signal and a data signal is transmitted to the slave circuit via the signal line by the master circuit , and the clock signal and the data signal are extracted from the transmitted signal in the slave circuit through the data clock separator 1. A single-line serial transmission circuit comprising a master circuit and a slave circuit , wherein a data clock adder used in writing transmission data from the master circuit to the slave circuit, and', 'a data receiver used in writing reception data from the slave circuit to the master circuit,, 'the master circuit includes a data clock separator used in writing the transmission data from the master circuit to the slave circuit,', 'a data transmitter used in writing the reception data from the slave circuit to the master circuit, and', 'an active generator, and, 'the slave circuit includesthe master circuit and the slave circuit are connected together via a single signal line.2. The single-line serial transmission circuit according to claim 1 , wherein during a write of the transmission data from the master circuit to the slave circuit claim 1 ,in the master circuit, a synthetic signal synthesized from a clock signal and a data signal by the data clock adder is transmitted to the slave circuit via the signal line, andin the slave circuit, the synthetic signal transmitted via the signal line is passed through the data clock separator, and is then passed through a delay circuit to extract the clock signal and through the data clock separator to extract the ...

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Номер записи: 68
30-01-2020 дата публикации

RECEIVER

Номер: US20200036508A1
Автор: MATSUDAIRA Nobuaki
Принадлежит:

A receiver includes: an A/D converter that performs an analog digital conversion of an input signal; an equalizer that equalizes an output from the A/D converter, eliminates inter code interference and obtains a data output; a timing recovery part that generates a recovery clock from the data output of the equalizer; a detector that detects the timing when an input signal varies from a no-signal state and has reached a predetermined threshold; and an initial phase setting part that sets as the initial phase of the recovery clock by the timing recovery part, a timing when the predetermined time has elapsed after the timing detected by the detector. 18-. (canceled)9. A receiver comprising:an A/D converter that performs an analog digital conversion to an input signal;an equalizer that equalizes an output of the A/D converter, eliminates an inter-code interference and obtains a data output;a timing recovery part that generates a recovery clock by using the data output of the equalizer;a detector that detects a timing when the input signal varies from a non-signal state and has reached a predetermined threshold;an initial phase setting part that sets as an initial phase of the recovery clock from the timing recovery part, a timing when a predetermined time has elapsed after the timing detected by the detector;a classic CAN receiver that performs a data reception to the input signal based on CAN standard;a selector that selects either a data output of the classic CAN receiver or the data output equalized and outputted by the equalizer; anda selection control part that selects the data output of the classic CAN receiver and the data output of the equalizer in a data phase by performing a selection control to the selector corresponding to a FDF value of an arbitration phase in the CAN standard.10. A receiver comprising:an A/D converter that performs an analog digital conversion to an input signal;an equalizer that equalizes an output of the A/D converter, eliminates an ...

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Номер записи: 69
12-02-2015 дата публикации

CIRCUIT ARRANGEMENT AND METHOD FOR TRANSMITTING SIGNALS

Номер: US20150043690A1
Автор: BLON Thomas, HOELTKE Holger, SUTTORP Thomas
Принадлежит: SILICON LINE GMBH

On the basis 1. A circuit arrangement for transmitting bothsingle-ended logic-level-based data signals and clock signals, anddifferential, in particular common-mode-based, data signals and clock signals,in the form of at least one serialised common signal stream between at least one transmission arrangement assignable to at least one data source and at least one receiving arrangement assignable to at least one data sink, wherein the data rate of the differential data signals and clock signals is different from the data rate of the single-ended, logic-level-based data signals and clock signals.2. The circuit arrangement according to claim 1 , wherein the data rate of the differential data signals and clock signals is smaller than the data rate of the single-ended claim 1 , logic-level-based data signals and clock signals.3. The circuit arrangement according to claim 1 , wherein the transmission arrangement comprises:at least one input for the data signals and clock signals,at least one transmission interface logic downstream of the input for picking up the data signals and clock signals,at least one serialiser downstream of the transmission interface logic for generating the common signal stream,at least one clock generator provided downstream of at least one clock module of the transmission interface logic, upstream of the serialiser and for generating at least one reference clock,at least one output driver downstream of the serialiser andat least one output downstream of the output driver for transmitting the common signal stream to the receiving arrangement.4. The circuit arrangement according to claim 3 , wherein the clock generator is configured at least as a phase-locked-loop claim 3 , in particular as an at least one clock multiplier unit.5. The circuit arrangement according to claim 3 , wherein the serialiser comprises:at least one framer downstream of the transmission interface logic for generating at least one frame recognisable in the receiving arrangement ...

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Номер записи: 70
12-02-2015 дата публикации

Circuit arrangement and method for transmitting signals

Номер: US20150043692A1
Автор: Florian Jansen, Holger Hoeltke, Thomas Blon
Принадлежит: SILICON LINE GMBH

On the basis of single-ended signals based on logic levels, and of differential, in particular common-mode-based, signals, a circuit arrangement and a corresponding method are proposed, in which it is possible to further reduce the size of tools, which are associated with said type of circuit arrangement and said type of method.

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Номер записи: 71
11-02-2016 дата публикации

SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR EFFICIENT CACHING OF HIERARCHICAL ITEMS

Номер: US20160043999A1
Автор: Gupta Shaival, Wongkar Adison Hana
Принадлежит:

Embodiments disclosed herein provide a “lazy” approach in caching a hierarchical navigation tree with one or more associated permission trees. In one embodiment, only a portion of a cached permission tree is updated. One embodiment of a method may comprise determining whether a dirty node exists by comparing tree timestamps of the permission tree and the master tree. If the tree timestamp of the master tree is temporally more recent than the tree timestamp of the permission tree, the permission tree has a dirty node and the method may operate to check node timestamps of the master and permission trees. This process may be repeated until the dirty node is found, at which time a portion of the permission tree associated with the dirty node may be reconstructed, rather than the entire permission tree itself, thereby eliminating or significantly reducing access time to the cached permission tree. 1. A method of caching hierarchical items in a network environment , the method comprising:receiving, by a server machine from a computing device communicatively connected to the server machine, a request for a change to a web site;updating, by the server machine, a master tree to reflect the change to the web site, the master tree having nodes representing hierarchical items of the web site and edges representing hierarchical relationships among the hierarchical items, each node of the nodes in the master tree having a tree timestamp and a node timestamp, the updating including updating the tree timestamp and the node timestamp of a first node affected by the change and updating the tree timestamp of any upstream parent node of the first node in the master tree;determining, by the server machine, a permission tree affected by the change, the permission tree associated with a user group permitted to view a particular portion of the hierarchical items of the web site, the permission tree having a set of nodes corresponding to the particular portion of the hierarchical items of ...

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Номер записи: 72
09-02-2017 дата публикации

Acoustic gesture recognition systems and methods

Номер: US20170041127A1
Автор: Bradley Sharpe-Geisler
Принадлежит: Lattice Semiconductor Corp

Methods and circuitry for relatively low-speed bus time stamping and triggering for use in acoustic object and gesture detection and recognition are presented in this disclosure. A master device and slave devices can be interfaced via a communication link that includes a data line and a clock line. The master device generates and controls a clock signal on the clock line and sends a synchronization command over the data line to the slave devices. The master device receives timestamp and/or other information corresponding to events detected at each slave device, such as a detected acoustic wave reflected from an object. The master device tracks transitions and frequencies of the clock signal, and determines a time of the event based on the timestamp information, the tracked transitions and the frequencies. The master device can use the event times to derive positions and gestures associated with detected objects.

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Номер записи: 73
08-02-2018 дата публикации

DYNAMIC CLOCK-DATA PHASE ALIGNMENT IN A SOURCE SYNCHRONOUS INTERFACE CIRCUIT

Номер: US20180041328A1
Автор: Chan Kok Hong, KHOR Chuan Thim, Patil Dinesh, Wong Wai Tat
Принадлежит: Altera Corporation

The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. Clock-data phase alignment circuitry is presented that may receive a differential clock with complementary clock signals CLK_P and CLK_N. An adjustable delay circuit and clock distribution network may delay clock signal CLK_P and provide the delayed clock signal to a storage circuit that may store the data signal. A replica clock distribution network and a replica adjustable delay circuit may form a feedback path and provide the delayed first clock signal back to clock phase adjustment circuitry which may control the adjustment of the adjustable delay circuit and the replica adjustable delay circuit. 1. Clock-data phase alignment circuitry , comprising:clock phase adjustment circuitry that receives a differential clock with first and second clock signals that are complementary to each other;a first clock distribution network that receives the first clock signal and propagates the first clock signal through a first branch that has a first delay and includes at least one first clock buffer to provide a delayed first clock signal and through a second branch that is parallel to the first branch, has a second delay that is substantially equal to the first delay, and provides a delayed second clock signal;a first storage circuit that receives the delayed first clock signal and a first data signal and stores the first data signal based on the delayed first clock signal;a second storage circuit that receives the delayed second clock signal and a second data signal and stores the second data signal based on the delayed second clock signal; anda second clock distribution network coupled between ...

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Номер записи: 74
09-02-2017 дата публикации

LOW POWER INTERMITTENT MESSAGING FOR HEARING ASSISTANCE DEVICES

Номер: US20170041896A1
Автор: Kroenke Randall A., Solum Jeffrey Paul
Принадлежит:

The present subject matter includes a system for communications between a transmitter and a receiver. In various embodiments, the system uses a sleep interval to allow the receiver to go to sleep between wake up times to “sniff” for transmissions from the transmitter. The system adjusts the length of the preamble of the transmitted signal or a repetition of packets to allow the receiver to detect a transmitted signal based on drift in the clocks of the system. In various embodiments, a receive channel is changed if a signal is not received at a prior channel selection. In various embodiments, the transmission is determined by detection of an event. In various embodiments, the event is an ear-to-ear event. In various embodiments, the receiver and transmitter are in opposite hearing aids adapted to be worn by one wearer. 1. A method for communications between a transmitter having a first clock and a receiver having a second clock , the method comprising:synchronizing the first clock and the second clock at a synchronization time;determining a time interval between the synchronization time and a transmission time of a transmission;calculating a drift window using a potential drift amount between the first clock and the second clock over the time interval;transmitting the transmission with the transmitter, the transmission including a repetition of packets having a duration based on the drift window; andreceiving with the receiver using a reception window that is adjustable based on the drift window.2. The method of claim 1 , wherein the first clock or the second clock or both clocks are adjusted to compensate for any measured difference in rate between the first clock and the second clock.3. The method of claim 1 , wherein the duration is at least the length of a clock accuracy multiplied by the time interval.4. The method of claim 1 , comprising receiving with the receiver at a plurality of predetermined sleep intervals by activating the receiver for a duration of ...

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Номер записи: 75
06-02-2020 дата публикации

Slave communication apparatus and master communication apparatus

Номер: US20200042073A1
Автор: Masashi AKAHANE
Принадлежит: Fuji Electric Co Ltd

A slave communication apparatus including a clock recovering section that recovers a clock signal from a transmission signal having a first signal value when the clock is a first level, a second signal value when the clock is a second level and data has a first data value, and a third signal value between the first and second signal values when the clock is the second level and the data has a second data value; and a data recovering section that recovers the data, wherein the data recovering section sets the data threshold value to be a first setting value between the second and third signal values in response to the recovered data having the second data value, and sets the data threshold value to be a second setting value between the first and third signal values in response to the recovered data having the first data value.

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Номер записи: 76
24-02-2022 дата публикации

MANAGING ENCODER UPDATES

Номер: US20220060530A1
Автор: Hegar Ryan Paul, Shams Khawaja Salman, Woodruff Eric
Принадлежит:

A video packaging and origination service can include one or more encoder components that receive content for encoding and transmitting to requesting entities. During the operation of the encoder components, a management service associated with the video packaging and origination service can receive information related to updates or modifications to the encoder components. Responsive to the information, the management service can instantiate and configure an updated encoder. Once the updated encoder component is instantiated and configured, both the updated and target encoder components receive content for streaming, encode content and generating encoding content. Additionally, the updated encoder component can initiate a notification to the target encoder component that a handover will be occurring and begin a negotiation process identifying a handover event. Based on the negotiated handover event, the target encoder component can illustratively cease operation upon evaluation and detection of the handover event. 1. A system to manage encoder components comprising:{'claim-text': ['generate first encoded output;', 'receive notification of an update from a second encoder component;', 'transmit first synchronization information to the second encoder component, the first synchronization information used to identify a handover event; and', 'responsive to a determined handover event, designate the first encoded output to have a lower priority than second encoded output of the second encoder component; and'], '#text': 'one or more computing devices associated with a first encoder component, wherein the first encoder component is configured to:'}{'claim-text': ['generate the second encoded output;', {'b': '2', '#text': 'transmit second synchronization information to the first encoder component, wherein the transmitted first and second synchronization information defines criteria for determining the handover event; and vresponsive to the determined handover event, generate ...

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Номер записи: 77
07-02-2019 дата публикации

JITTER SENSING AND ADAPTIVE CONTROL OF PARAMETERS OF CLOCK AND DATA RECOVERY CIRCUITS

Номер: US20190044693A1
Автор: HE Yun, Sarkar Sanjib, SRIKANTH Adhiveeraraghavan
Принадлежит:

In accordance with embodiments disclosed herein, there is provided systems and methods for jitter sensing and adaptive control of parameters of clock and data recovery (CDR) circuits. A receiver component includes an adaptive CDR loop dynamic control circuit. The adaptive CDR loop dynamic control circuit is to detect first sinusoidal jitter at a first frequency and a first amplitude and update parameters of the CDR circuit to a first plurality of values based on the first frequency and the first amplitude. The adaptive CDR loop dynamic control circuit is further to detect second sinusoidal jitter at a second frequency and a second amplitude and update the parameters of the CDR circuit to a second plurality of values based on the second frequency and the second amplitude. The first sinusoidal jitter is in a first incoming data signal and the second sinusoidal jitter is in a second incoming data signal. 1. A receiver component comprising: detect first sinusoidal jitter at a first frequency and a first amplitude, wherein the first sinusoidal jitter is in a first incoming data signal;', 'update parameters of the CDR circuit to a first plurality of values based on the first frequency and the first amplitude;', 'detect second sinusoidal jitter at a second frequency and a second amplitude, wherein the second sinusoidal jitter is in a second incoming data signal; and', 'update the parameters of the CDR circuit to a second plurality of values based on the second frequency and the second amplitude., 'an adaptive CDR loop dynamic control circuit to, 'a clock and data recovery (CDR) circuit comprising2. The receiver component of claim 1 , wherein the parameters of the CDR circuit comprise a first order loop gain and a second order loop gain.3. The receiver component of claim 1 , wherein the adaptive CDR loop dynamic control circuit comprises a sinusoidal jitter detector to detect the first frequency of the first sinusoidal jitter.4. The receiver component of claim 1 , wherein ...

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Номер записи: 78
07-02-2019 дата публикации

IMAGE PICKUP APPARATUS, LENS APPARATUS, AND IMAGE PICKUP SYSTEM

Номер: US20190045110A1
Автор: OKADA Koji
Принадлежит:

A lens apparatus is detachable from an image pickup apparatus. The lens apparatus includes a controller configured to communicate with the image pickup apparatus in synchronization with a first signal. A communication contains a plurality of blocks in the same cycle of the first signal. The controller transmits information of a first time period to the image pickup apparatus, and prohibits a communication of an m-th block from starting before the first time period passes after a communication of an n-th block starts or ends where n is an integer equal to or larger than 1 and m is an integer larger than n. 114-. (canceled)15. A lens apparatus detachable from an image pickup apparatus , the lens apparatus comprising a controller configured to communicate with the image pickup apparatus in synchronization with a synchronizing signal , and an actuator ,wherein a communication between the lens apparatus and the image pickup apparatus is a packet communication having a plurality of blocks in a cycle of the synchronizing signal,wherein the controller transmits information of predetermined time period stored in the lens apparatus to the image pickup apparatus, andwherein the information of the predetermined time period is information to prohibit, before the predetermined time period passes after a communication of a block in a specific cycle of the synchronizing signal starts or ends, a command of driving of the actuator from being issued from the image pickup apparatus.16. The lens apparatus according to claim 15 , wherein the controller transmits the information of the predetermined time period to the image pickup apparatus in a communication of a first block in the specific cycle of the synchronizing signal.17. The lens apparatus according to claim 15 , wherein the controller transmits the information of the predetermined time to the image pickup apparatus in an initial communication that is performed prior to the packet communication.18. The lens apparatus according to ...

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Номер записи: 79
18-02-2021 дата публикации

VLAN-Aware Clock Synchronization

Номер: US20210050988A1
Автор: Budnik Petr, Chan Jeff Jing Yuen, Fong Harold
Принадлежит:

Synchronization of clocks among computing devices in a network includes determining master/slave relations among the computing devices. Some computing devices (e.g., switches) include trunk ports configured to carry traffic for several logical networks; e.g., virtual local area networks, VLANs. A trunk port can be associated with a master/slave setting for each logical network that it is configured for. Synchronization of clocks among the computing devices further includes running a synchronization sequence between a trunk port and each computing device on each of the logical networks configured on the trunk port. 1. A method comprising:synchronizing a clock in a network device with a clock in a first participating device on a first logical network, including exchanging first synchronization messages between a port of the network device and a port on the first participating device, wherein exchanging first synchronization messages includes providing an identifier with the first synchronization messages that identifies the first logical network; andsynchronizing the clock in the network device with a clock in a second participating device on a second logical network different from the first logical network, including exchanging second synchronization messages between the port of the network device and a port on the second participating device, wherein exchanging second synchronization messages includes providing an identifier with the second synchronization messages that identifies the second logical network.2. The method of claim 1 , wherein the port on the network device is a master port with respect to the port on the first participating device and is a slave port with respect to the port on the second participating device.3. The method of claim 2 , further comprising the port on the network device:initiating a first synchronization sequence with the port on the first participating device; andperforming a second synchronization sequence with the port on the second ...

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Номер записи: 80
18-02-2016 дата публикации

METHOD AND APPARATUS FOR ADAPTIVE DEVICE RE-CONFIGURATION

Номер: US20160050111A1
Автор: JANG Kyoungdon, KIM Dohyoung, KIM Joohwan, PARK Hyunjin
Принадлежит:

An apparatus is provided comprising a memory and a processor configured to: execute a device driver for operating a device; detect a data throughput associated with the device driver; identify a configuration setting based on the data throughput; and re-configure the apparatus based on the configuration setting. 1. An apparatus comprising ,a memory; andat least one processor configured to:execute a device driver for operating a device;detect a data throughput associated with the device driver;identify a configuration setting based on the data throughput; andre-configure the apparatus based on the configuration setting.2. The apparatus of claim 1 , wherein the at least one processor is further configured to:generate, by a throughput collecting unit, a message including an indication of the data throughput and a device driver identifier, and provide the message to a resource controller; andaccess, by the resource controller, a data structure mapping the data throughput and device driver identifier to the configuration setting in order to identify the configuration setting.3. The apparatus of claim 1 , wherein the configuration setting includes at least one of a clock frequency associated with the device and an interrupt affinity setting associated with the device driver.4. The apparatus of claim 1 , wherein the data throughput is calculated based on at least one of an amount of data received by the device driver within a predetermined time period and an amount of data output by the device driver within the predetermined time period.5. The apparatus of claim 1 , wherein re-configuring the apparatus includes changing a clock frequency of one or more hardware components of the apparatus.6. The apparatus of claim 1 , further comprising a bus claim 1 , wherein re-configuring the apparatus includes changing a clock frequency of the bus.7. The apparatus of claim 6 , wherein the bus includes an internal bus of the processor.8. The apparatus of claim 6 , wherein the bus ...

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Номер записи: 81
03-03-2022 дата публикации

SYNCHRONIZING A USER DEVICE AND A KIOSK INTERFACE USING A VISUAL CODE, AND APPLICATIONS THEREOF

Номер: US20220068241A1
Автор: Broderick John, SCHURAN Brad, SCOTT Jeffrey Lee
Принадлежит:

A user can scan a QR code on a kiosk with her mobile device. Scanning the QR code will cause the mobile device to display an interface displayed on the kiosk. When a user enters information on the device corresponding information is displayed on the kiosk. In this way, a user can engage with the kiosk interface in a contactless manner.

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Номер записи: 82
26-02-2015 дата публикации

INTERNET GROUP MANAGEMENT PROTOCOL (IGMP) LEAVE MESSAGE PROCESSING SYNCHRONIZATION

Номер: US20150055662A1
Автор: Bhagavathiperumal Chidambaram, Hariharan Gangadhar, Sekhara Naveen C., Voicu Raluca
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Embodiments relate to synchronizing Internet Group Management Protocol (IGMP) leave processing in a system. One embodiment includes a system with a first access switch, a first virtual switch having a first timer, and a second virtual switch having a second timer. The first virtual switch and the second virtual switch are connected with the first access switch. The first access switch transmits an IGMP leave message to the first virtual switch. The first virtual switch transmits a synchronization message to the second virtual switch. The second virtual switch updates the second timer based on receiving the synchronization message. 1. A system , comprising:a first access switch;a first virtual switch having a first timer; anda second virtual switch having a second timer, the first virtual switch and the second virtual switch are coupled with the first access switch, wherein the first access switch transmits an Internet Group Management Protocol (IGMP) leave message to the first virtual switch, the first virtual switch transmits a synchronization message to the second virtual switch, wherein the second virtual switch updates the second timer based on receiving the synchronization message.2. The system of claim 1 , further comprising a multi-cast receiver coupled to the first access switch claim 1 , wherein the multi-cast receiver transmits the IGMP leave message to the first access switch.3. The system of claim 2 , wherein the first virtual switch is enabled as an IGMP querier.4. The system of claim 3 , wherein the synchronization message is transmitted over an inter-switch link (ISL) between the first virtual switch and the second virtual switch.5. The system of claim 4 , wherein the ISL uses an edge control protocol (ECP) transport mechanism.6. The system of claim 4 , wherein information comprises an IGMP group address claim 4 , a virtual local area network (vLAN) identification and a trunk identification for the IGMP querier.7. The system of claim 6 , wherein the ...

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Номер записи: 83
03-03-2022 дата публикации

TIME TRANSFER USING PASSIVE TAPPING

Номер: US20220069970A1
Автор: Mirabito David J., Snowdon David C.A.
Принадлежит:

Techniques for determining a clock offset between monitoring devices in a network. Such techniques include: obtaining, by a first monitoring device, a first set of network traffic data units sent between a first endpoint and a second endpoint via a first tap on a network link between the first endpoint and second endpoint; obtaining, by a second monitoring device, a second set of network traffic data units sent between the first endpoint and the second endpoint via a second tap on the network link; calculating the clock offset between the first monitoring device and the second monitoring device using the first set of network traffic data units and the second set of network traffic data units; and performing an offset action based on the clock offset.

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Номер записи: 84
03-03-2022 дата публикации

Method and receiving device for clock frequency synchronization

Номер: US20220069971A1
Автор: Binghai Gao
Принадлежит: Shenzhen Lenkeng Technology Co Ltd

Disclosed are a method and a receiving device for clock frequency synchronization. The method includes the following. A user datagram protocol (UDP) packet is obtained by a receiving device. A value of the data volume of the UDP packet in the cache and a first value are performed, by the receiving device, an operation to obtain the absolute value of the difference between the value of the data volume and the first value. When the absolute value is greater than the preset threshold, a clock frequency of the crystal oscillator in the receiving device is adjusted to obtain a target clock frequency, where after the clock frequency of the crystal oscillator is adjusted, the absolute value of the difference is less than or equal to the preset threshold. The receiving device maintains clock frequency synchronization between the receiving device and the transmitting device based on the target clock frequency.

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Номер записи: 85
03-03-2022 дата публикации

SIGNALING SYSTEM WITH ADAPTIVE TIMING CALIBRATION

Номер: US20220069975A1
Автор: Hampel Craig E., Stott Bret G., Ware Frederick A.
Принадлежит:

A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.

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Номер записи: 86
25-02-2016 дата публикации

METHOD AND APPARATUS FOR MANAGING ESTIMATION AND CALIBRATION OF NON-IDEALITY OF A PHASE INTERPOLATOR (PI)-BASED CLOCK AND DATA RECOVERY (CDR) CIRCUIT

Номер: US20160056949A1
Автор: CHAKRAVARTY SUJOY, CHATTOPADHYAY BIMAN, MEHTA RAVI, NAYAK GOPALKRISHNA
Принадлежит:

A method for managing estimation and calibration of non-ideality of a Clock and Data Recovery (CDR) circuit. The method comprises A) selecting a first output path for calibration comprising at least a first Phase Interpolator (PI) of a plurality of PIs, at least one of a plurality of output-side programmable delay elements, an external delay element, at least one sampler, a first and a second external multiplexer, B) programming the output-side programmable delay element using a Digital Delay Control Code (DDCC), C) calibrating the external delay element until a given predetermined criterion based on an early-late detection method is met, D) upon satisfaction of the predetermined criterion, retaining a corresponding Digital External Delay Control Code (DEDCC) in the external delay element for subsequent use, E) selecting a second output path for calibration comprising at least a second PI of the plurality of PIs, the at least one of the plurality of output-side programmable delay elements, external delay element, at least one sampler, the first and second external multiplexers, F) calibrating the output-side programmable delay element until the given predetermined criterion based on the early-late detection method is met, G) upon satisfaction of the predetermined criterion, retaining the corresponding DDCC in the output-side programmable delay element for subsequent use, H) repeating the steps E-G for each of the remaining PIs such that the remaining output-side programmable delay elements are each separately calibrated, I) selecting a first input path for calibration comprising the at least first Phase Interpolator (PI) of the plurality of PIs, at least one of the plurality of input-side programmable delay elements, the external delay element, at least one sampler, the first and second external multiplexers, J) programming the input-side programmable delay element using the Digital Delay Control Code (DDCC), K) calibrating the external delay element until the given ...

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Номер записи: 87
13-02-2020 дата публикации

LOW-POWER SOURCE-SYNCHRONOUS SIGNALING

Номер: US20200051610A1
Автор: Ware Frederick A., Zerbe Jared L.
Принадлежит:

A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information. 1. (canceled)2. An integrated circuit (IC) memory chip comprising:receiver circuitry to receive data signals from a memory controller and a first timing signal having a first phase relationship with the data signals, the receiver circuitry to receive a second timing signal, the second timing signal having a second phase relationship with the first timing signal;transmit circuitry to transmit feedback to the memory controller, the feedback based on a comparison between the first timing signal and an on-chip timing signal based on the second timing signal; andwherein an adjusted second timing signal is received by the receiver circuitry, the adjusted second timing signal exhibiting an updated second phase relationship relative to the first timing signal that is based on the transmitted feedback.3. The IC memory chip according to claim 2 , wherein the on-chip timing signal based on the second timing signal comprises:an internally distributed version of the second timing signal.4. The IC memory chip according to claim 2 , wherein the feedback comprises:error information.5. The IC memory chip according to claim 4 , wherein the error information represents a phase difference between the first timing signal and ...

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Номер записи: 88
14-02-2019 дата публикации

COMMUNICATION DEVICE AND COMMUNICATION SYSTEM

Номер: US20190052451A1
Автор: Kaneko Naoji, OOKAWA Takamori
Принадлежит:

A communication system includes a master node and one more slave nodes connected via a transmission line. The master node is configured to output a first PWM signal having a shorter low level time and a second PWM signal having a longer low level time. The slave node is configured to output the second PWM signal when detecting a high to low signal level change on the transmission line. The master node detects a time delay as measured from when an input signal to a transmission buffer falls to when an output signal from a reception buffer falls. The time delay is an index value used to change the low level time of the first PWM signal when the time delay is equal to or less than a preset value. 2. The communication device of further comprising:an output section configured to output the first PWM signal and the second PWM signal to the transmission line; anda determiner configured to determine whether a signal level of the transmission line is the first level or the second level by comparing the signal level of the transmission line with at least one threshold that is set as a potential between the first level and the second level, whereinthe detector detects the index value as a time delay from an instruction timing of giving an instruction to the output section for the signal level change of the transmission line from a pre-change level to a post-change level, the pre-change level being one of the first level and the second level and the post-change level being other one of the first level and the second level, to the detection timing of the signal level change of the transmission line from the pre-change level to the post-change level.3. The communication device of claim 2 , whereinthe instruction used for the detection of the time delay instructs the output section for outputting one of the first PWM signal and the second PWM signal from the communication device to the transmission line for the communication.5. The communication system of claim 4 , whereinthe ...

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Номер записи: 89
22-02-2018 дата публикации

DEVICE AND METHOD FOR SKEW COMPENSATION BETWEEN DATA SIGNAL AND CLOCK SIGNAL

Номер: US20180054336A1
Автор: Hori Yoshihiko, ITOIGAWA Keiichi, KANDA Kazuhiko, KUROSAWA Jun, KUWADA Hideaki, MINAKI Tomoo, SENO Takefumi, Tamura Takashi
Принадлежит:

A semiconductor device includes first and second buffers respectively outputting reception data and clock signals; a latch circuit latching the reception data signal in response to the reception clock signal; a delay circuitry delaying the reception clock signal by a set delay time; and a delay control circuitry which searches a first delay time while increasing the set delay time from an initial value; searches a second delay time while increasing the set delay time from the first delay time; searches a third delay time while decreasing the set delay time from the second delay time; and determines an optimum delay time from the first and third delay times. The first and third delay times are determined so that the reception data is stabilized to a first value and the second delay time is determined so that the reception data is stabilized to a second value. 1. A semiconductor device , comprising:a first buffer configured to receive an external data signal and to output a reception data signal corresponding to the external data signal;a second buffer configured to receive an external clock signal and to output a reception clock signal corresponding to the external clock signal;a latch circuit configured to latch, responsive to the reception clock signal, the reception data signal or a signal generated from the reception data signal to output reception data corresponding to the reception data signal;a delay circuitry configured to delay, by a set delay time, one of the reception data signal and the reception clock signal with respect to the other of the reception data signal and the reception clock signal; and set, in an initial setting operation, the set delay time to an initial value;', 'determine, in a first phase operation, a first delay time while the set delay time is increased from the initial value, wherein the first delay time is determined as a value of the set delay time at which a value of the reception data is stabilized to a first value;', 'determine, ...

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Номер записи: 90
25-02-2021 дата публикации

TIME SYNCHRONIZATION SYSTEM AND TIME SYNCHRONIZATION METHOD

Номер: US20210058223A1
Автор: Arai Kaoru, Hisashima Takaaki, Kurokawa Osamu, Matsumura Kazuyuki, Sakuma Hiroki, Sugiyama Ryuta, Tsuboi Shunichi
Принадлежит:

[Problem] To synchronize timings of transmitting and receiving a pulse signal (1 PPS signal) at a constant interval between communication apparatuses even in a case where an optical fiber connecting the communication apparatuses fluctuates in an optical characteristic and an optical fiber length. 1. A time synchronization system for transmitting and receiving a pulse signal at a constant interval at a synchronization timing between first and second communication apparatuses connected through a first optical fiber and a second optical fiber , which are two-core bidirectional , to synchronize time , the time synchronization system comprising:the first communication apparatus that includesa first transmitter configured to transmit a first pulse signal of a first wavelength and a second pulse signal of a second wavelength different from the first wavelength to the second communication apparatus through the first optical fiber, anda first receiver configured to receive a plurality of pulse signals including the first pulse signal and the second pulse signal transmitted from the second communication apparatus through the second optical fiber; andthe second communication apparatus that includesa second receiver configured to receive the first pulse signal and the second pulse signal from the first optical fiber, anda second transmitter configured to generate a third pulse signal of a wavelength identical to the second wavelength of the second pulse signal when receiving the first pulse signal, to simultaneously transmit the first pulse signal and the third pulse signal to the first communication apparatus through the second optical fiber, to generate a fourth pulse signal of a wavelength identical to the first wavelength of the first pulse signal when receiving the second pulse signal, and to simultaneously transmit the second pulse signal and the fourth pulse signal to the first communication apparatus through the second optical fiber,wherein the first communication ...

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Номер записи: 91
25-02-2021 дата публикации

FAST INITIAL PHASE SEARCH FOR DIGITAL CLOCK AND DATA RECOVERY AND RELATED SYSTEMS, DEVICES, AND METHODS

Номер: US20210058225A1
Автор: Chen Dixon, Yang Kevin, Yu Jiachi
Принадлежит:

Systems, devices, and methods related to selecting a sample phase of a signal are disclosed. A method includes sampling a signal including a plurality of symbols with a plurality of different sample phases to obtain sample values of each of the plurality of symbols at each of the plurality of different sample phases. The signal is received from a shared transmission medium. The method also includes determining an edge sample phase of the plurality of different sample phases that corresponds to edges of the symbols based on the sample values. The method further includes determining a center sample phase of the plurality of different sample phases based on the determined edge sample phase, and using the determined center sample phase to determine values of the symbols. 1. A physical layer device , comprising:an input configured to receive a signal including a plurality of symbols from a shared transmission medium of a wired local area network; and sample the signal using a plurality of different sample phases to obtain sample values of each of the plurality of symbols at each of the plurality of different sample phases;', 'determine an edge sample phase of the plurality of different sample phases responsive to the obtained sample values of each of the plurality of symbols at each of the plurality of different sample phases;', 'determine a center sample phase of the plurality of different sample phases responsive to the determined edge sample phase; and', 'use the determined center sample phase to determine values of each of the plurality of symbols., 'one or more processors configured to2. The physical layer device of claim 1 , wherein the one or more processors are configured to determine the edge sample phase by:performing, for each sample phase of the plurality of different sample phases, an exclusive or (XOR) computation between those of the sample values corresponding to a sample phase and those of the sample values corresponding to a sample phase immediately ...

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Номер записи: 92
23-02-2017 дата публикации

SIGNALING SYSTEM WITH ADAPTIVE TIMING CALIBRATION

Номер: US20170054549A1
Автор: Hampel Craig E., Stott Bret G., Ware Frederick A.
Принадлежит:

A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information. 1. (canceled)2. An integrated circuit (IC) memory controller , comprising:a timing signal pin to receive a timing signal;a first data pin to receive first data and having first sampling circuitry;a second data pin to receive second data and having second sampling circuitry; detect a first phase difference between a phase of the timing signal and a phase of the first data, and adjust the phase of the first data to a first calibrated phase based on the first phase difference, and', 'detect a second phase difference between the phase of the timing signal and a phase of the second data, and adjust the phase of the a second data to a second calibrated phase based on the second phase difference;, 'a timing controller coupled to the timing signal pin, the first data pin and the second data pin, the timing controller operative during a runtime operation mode to'} wherein the first sampling circuitry samples the first data based on the first calibrated phase; and', 'wherein the second sampling circuitry samples the second data based on the second calibrated phase., 'the timing controller to detect the first phase difference and the ...

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Номер записи: 93
14-02-2019 дата публикации

RADIO RESOURCE MANAGEMENT FRAMEWORK FOR 5G OR OTHER NEXT GENERATION NETWORK

Номер: US20190053235A1
Автор: Bendlin Ralf, Novlan Thomas
Принадлежит:

A radio resource measurement (RRM) and timing configuration (TC) framework can facilitate efficient configuration of RRM measurements in wireless communications systems with variable carrier and transmission bandwidths. The RMTC can comprise a list of synchronization signal (SS) block measurement and timing configurations (SMTCs) and a list of channel state information reference signal (CSI-RS) measurement and timing configurations (CMTCs). A framework is proposed to allow for efficient signaling of measurement configurations in cellular wireless communications systems with overlapping carriers of varying bandwidths comprising carriers without synchronization signals as well as bandwidth parts covering parts of the spectrum of a carrier. 1. A method , comprising:receiving, by a mobile device comprising a processor, configuration data related to a measurement and timing applicable to a radio resource of a wireless network, wherein the configuration data comprises a carrier frequency and bandwidth data representative of a bandwidth associated with the wireless network, and wherein the configuration data comprises quasi-colocation data representative of a relationship between a channel state data reference signal and a synchronization signal block;based on the quasi-colocation data, reporting, by the mobile device, a sequence identification associated with the wireless network; andbased on the configuration data, configuring, by the mobile device, a transceiver of the mobile device to receive the radio resource in accordance with the carrier frequency and the bandwidth data.2. The method of claim 1 , wherein the configuration data is utilized to configure a synchronization signal used to synchronize a frequency used for communication between the mobile device and the wireless network.3. The method of claim 2 , wherein the configuration data comprises instruction data representative of an instruction to associate a configuration of the synchronization signal with the ...

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Номер записи: 94
13-02-2020 дата публикации

ASYNCHRONOUS MEDIUM ACCESS CONTROL LAYER SCHEDULER FOR DIRECTIONAL NETWORKS

Номер: US20200053021A1
Автор: Chauvette Mark D., Rasa Matthew, Sherman Matthew J., Sherman Nicholas C.
Принадлежит: BAE Systems Information and Electronic Systems Integration Inc.

An asynchronous medium access control layer scheduler increases efficiency for directional mesh networks by removing extra overhead in the time slots. The efficiency is increased by dividing time slots into sub-slots to allow for a receiving node to be offset by at least one sub-slot from the transmitting node. This enables the scheduler to more efficiently schedule operations for the nodes so that nodes can be performing other functions rather than waiting to receive a transmission or waiting after transmitting a transmission. The sub-slots may be sized to approximate the transmission propagation time or time of flight delay. 1. An asynchronous medium access control (AMAC) scheduler comprising:at least one time slot including a first time slot;at least two sub-slots within each at least one time slot;a transmit packet block occupying at least one sub-slot within the first time slot; anda receiver packet block including at least one sub-slot independent from the transmit packets block of at least one sub-slot, both the transmit packet block and the receiver packer block occupying at least one sub-slot and the receiver packet block being offset by a non-negative integer value of minslots from the transmit packet block from the first time slot and at least one sub-slot from a second time slot that is adapted to free a transceiver during the other sub-slot in the first time slot to perform a different operation.2. The AMAC scheduler of claim 1 , further comprising:a device to account for time of flight (ToF) delays from a sender packet block to the receiver packet block.3. The AMAC scheduler of claim 2 , further comprising a transmitter node and receiver node wherein the receiver node performs a different task in a prior sub-slot during the ToF delay before the at least one sub-slot from the first time slot.4. The AMAC scheduler of claim 2 , wherein the ToF delay is at least equal to the time of one sub-slot.5. The AMAC scheduler of claim 1 , further comprising:a time ...

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Номер записи: 95
10-03-2022 дата публикации

SLAVE COMMUNICATION APPARATUS AND MASTER COMMUNICATION APPARATUS

Номер: US20220075439A1
Автор: AKAHANE Masashi
Принадлежит:

A slave communication apparatus including a clock recovering section that recovers a clock signal from a transmission signal having a first signal value when the clock is a first level, a second signal value when the clock is a second level and data has a first data value, and a third signal value between the first and second signal values when the clock is the second level and the data has a second data value; and a data recovering section that recovers the data, wherein the data recovering section sets the data threshold value to be a first setting value between the second and third signal values in response to the recovered data having the second data value, and sets the data threshold value to be a second setting value between the first and third signal values in response to the recovered data having the first data value. 1. A master communication apparatus comprising:a signal generating section that generates a transmission signal by embedding a clock in data, the transmission signal having a first signal value when the clock is a first level, a second signal value when the clock is a second level and the data has a first data value, and a third signal value between the first signal value and the second signal value when the clock is the second level and the data has a second data value; anda signal level switching section that switches signal levels of the second signal value and the third signal value according to a slave communication apparatus that is a destination of the data.2. The master communication apparatus according to claim 1 , whereina plurality of slave communication apparatuses, where each slave communication apparatus is the slave communication apparatus, are respectively assigned ranges of signal levels that do not overlap with each other, andthe signal level switching section switches the signal levels of the second signal value and the third signal value to be signal levels included within the range assigned to the slave communication ...

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Номер записи: 96
05-03-2015 дата публикации

Wireless communication apparatus

Номер: US20150063175A1
Автор: Ryuichi Fujimoto, Yoshiaki Yoshihara
Принадлежит: Toshiba Corp

According to an embodiment, a wireless communication apparatus includes a clock transmitting unit, a function circuit and a control unit. The clock transmitting unit is configured to transmit a clock signal through one of a plurality of transmission paths. The transmission paths are different from each other. The function circuit is configured to operate in synchronization with the clock signal transmitted by the clock transmitting unit. The control unit is configured to select one of the plurality of transmission paths according to an operation state of the wireless communication apparatus.

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Номер записи: 97
05-03-2015 дата публикации

METHOD, USER EQUIPMENT, AND BASE STATION FOR GENERATING PILOT SEQUENCE

Номер: US20150063284A1
Автор: LIU Kunpeng
Принадлежит: Huawei Technologies Co., Ltd.

The present invention discloses are a method, a user equipment, and a base station for generating a pilot sequence. The method includes: determining a first parameter used to generate a pilot sequence in a first parameter candidate set, where the first parameter candidate set includes at least two timeslot numbers of the following timeslot numbers: a timeslot number obtained after downlink synchronization, a predefined timeslot number, timeslot numbers in a second type pilot configuration parameter, a timeslot number obtained from a high layer notification, and a timeslot number obtained from a dynamic notification, where a second type pilot is different from a pilot corresponding to the pilot sequence; and generating the pilot sequence according to the first parameter. 1. A method for generating a pilot sequence , comprising:determining a first parameter used to generate the pilot sequence in a first parameter candidate set, wherein the first parameter candidate set comprises at least two timeslot numbers of the following timeslot numbers: a timeslot number obtained after downlink synchronization, a predefined timeslot number, timeslot numbers in a second type pilot configuration parameter, a timeslot number obtained from a high layer notification, and a timeslot number obtained from a dynamic notification, wherein a second type pilot is different from a pilot corresponding to the pilot sequence; andgenerating the pilot sequence according to the first parameter.2. The method according to claim 1 , further comprising:determining a second parameter used to generate the pilot sequence in a second parameter candidate set, wherein the second parameter represents a virtual identifier (ID);wherein the determining a first parameter used to generate the pilot sequence in a first parameter candidate set comprises:determining the first parameter according to the second parameter.3. The method according to claim 2 , wherein the determining the first parameter according to the ...

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Номер записи: 98
10-03-2022 дата публикации

ELECTRONIC COMMUNICATION DEVICE, MAGNETIC DISK DEVICE, AND SERIAL COMMUNICATION METHOD

Номер: US20220077956A1
Автор: Watanabe Akihiro, Yoshida Kenji
Принадлежит:

According to one embodiment, an electronic communication device includes a controller that changes an upper limit value capable of correcting an error of bit data in which an error occurs in packet data transferred by serial communication. 1. An electronic communication device comprising a controller that changes an upper limit value capable of correcting an error of bit data in which an error occurs in packet data transferred by serial communication.2. The electronic communication device according to claim 1 , wherein the controller changes the upper limit value according to a signal state of the packet data.3. The electronic communication device according to claim 2 , wherein the controller sets the upper limit value to be smaller when the signal state is not good.4. The electronic communication device according to claim 3 , wherein the controller sets the upper limit value to be smaller when boundaries of the packet data cannot be synchronized and the controller does not transition to a state of synchronizing the boundaries of the packet data.5. The electronic communication device according to claim 1 , wherein the controller includes a state machine that transitions to a state of synchronizing boundaries of the packet data when the upper limit value is exceeded four times in a row claim 1 , and the controller changes the upper limit value according to a signal state of the packet data in each state of the state machine.6. The electronic communication device according to claim 5 , wherein the controller sets the upper limit value to be smaller when the signal state of the packet data is not good in each state.7. The electronic communication device according to claim 6 , wherein the state machine corresponds to SAS Protocol Layer-4.8. The electronic communication device according to claim 7 , wherein the state machine is an SP_PS state machine.9. The electronic communication device according to claim 8 , wherein the state machine transitions to SP_PS0: AcquireSync ...

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Номер записи: 99
21-02-2019 дата публикации

READ-WRITE DATA TRANSLATION TECHNIQUE OF ASYNCHRONOUS CLOCK DOMAINS

Номер: US20190058573A1
Автор: Huang Wen-Hung, LIN Mu-Shan, Yang Shu-Chun
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

An electronic system includes transmitting circuitry of a first clock domain and receiving circuitry of a second domain. The transmitting circuitry re-times a digital input signal with rising edges of a clocking signal of the first clock domain when a phase of the clocking signal of the first clock domain leads a phase of a clocking signal associated with the digital input signal. Otherwise, the transmitting circuitry re-times the digital input signal with falling edges of the clocking signal of the first clock domain when the phase of the clocking signal of the first clock domain does not lead the phase of the clocking signal associated with a digital input signal. The receiving circuitry receives the re-timed digital input signal from the transmitting circuitry. Thereafter, the receiving circuitry re-times the re-timed digital input signal with rising edges of a phase of a clocking signal associated with the re-timed digital input signal when the phase of the clocking signal associated with the re-timed digital input signal leads a phase of a clocking signal of the second clock domain. Otherwise, the receiving circuitry re-times the re-timed digital input signal with falling edges of the phase of a clocking signal associated with the re-timed digital input signal when the phase of the clocking signal associated with the re-timed digital input signal does not lead the phase of a clocking signal of the second clock domain. 1. A transmitting circuitry , comprising:transmitter-edge-detect (TED) circuitry configured to compare a first clocking signal associated with a digital input signal and a second clocking signal of a first clock domain; and re-time the digital input signal in accordance with a falling edge of the second clocking signal when the first clocking signal is lagging the second clocking signal, and', 're-time the digital input signal in accordance with a rising edge of the second clocking signal when the first clocking signal is leading the second ...

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Номер записи: 100