СХЕМА ПРЕОБРАЗОВАНИЯ РАЗВЕРТКИ

Изобретение относится к схеме преобразования развертки. Техническим результатом является предотвращение в движущемся изображении, представленном видеосигналом, неестественного вида вертикальных и наклонных линий для воспроизведения изображения высокого качества. Технический результат достигается тем, что выводят видеосигнал, количество строк развертки которого удвоено путем встраивания в него интерполируемой строки развертки входных видеосигналов строк развертки, расположенных сверху и снизу, соответственно соседних с интерполируемой строкой развертки. Для этого схема преобразования развертки содержит блок обнаружения направления для обнаружения направления, имеющего наибольшую корреляцию, центрированных в точке интерполяции, включая вертикальное и наклонное направления, на основе входного видеосигнала, и блок вычисления среднего значения сигналов изображения в двух точках выборки на строках развертки, расположенных сверху и снизу, соответствующих обнаруженному направлению. Блок обнаружения ...

Universelle Videoausgangsvorrichtung

BILDSIGNALUMSETZER

SIGNALVERARBEITUNGSSYSTEM

FERNSEHKAMERA

FARBFERNSEHWIEDERGABEGERAET

VERFAHREN UND VORRICHTUNG ZUM ERZEUGEN VON BEWEGUNGSKOMPENSIERTEN BILDERN

Conversion of video frame rate

PROGRESSIVE SCAN TELEVISION SYSTEM

COEFFICIENT REDUCTION IN A LOW RATIO SAMPLING RATE CONVERTER

Generation of interlaced TV signals by interpolation

Controlling signal processing in a video down-converter

Signal processing apparatus eg. in a video scanning standards down-converter, comprises a control read only memory ROM storing: (i) two or more sets of signal processing parameter data to control signal processing operations of the apparatus; and (ii) configuration data specifying one of the sets of signal processing parameter data stored in the control read only memory; a control read/write memory 200 capable of storing: (i) at least one set of signal processing parameter data; and (ii) configuration data capable of specifying a set of signal processing parameter data stored in the control read only memory or a set of signal processing parameter data stored in the control read/write memory; and control logic, responsive to an input selection signal specifying whether the configuration data in the control read only memory or the configuration data in the read/write memory should be selected for use, for controlling the signal processing apparatus to perform signal processing operations ...

Controlling signal processing

Apparatus for converting the color television system

COMPATIBLE TRANSCODEABLE AND HIERARCHICAL DIGITAL TV SYSTEM

An image processor comprising an interpolator and an adaptable register store

An image processor is arranged in operation to generate an interpolated video signal from a received video signal representative of an image. The image processor comprises an adaptable register store coupled to a control processor which is operable to receive the video signal and to provide pixels of the received video signal, under control of the control processor, to an interpolator, the interpolator being coupled to the adaptable register store and is arranged in operation to generate the interpolated video signal by interpolating the pixels provided by the adaptable register store. The control processor controls in operation the adaptable register store to provide pixels to the interpolator to interpolate parts of the image in both vertical and horizontal directions. Performing diagonal interpolation can substantially reduce ringing effects and resolution loss on diagonal edges of an image. In order to interpolate a part or all of the image in both the vertical and a horizontal directions ...

Interpolation apparatus and video signal processing apparatus including the same

STANDARDS CONVERSION OF COLOUR TELEVISION SIGNALS

Global motion-compensated sequential-scanning method considering horizontal and vertical patterns

SCAN CONVERTER FOR A TELEVISION DISPLAY

Improvements in or relating to television standards conversion

... 1,068,101. Television standards conversion. BRITISH BROADCASTING CORPORATION. Jan. 25, 1966 [Feb. 4, 1966], No. 4965/65. Addition to 1,052,438. Heading H4F. Input signals at the 525/60 standard are applied to a delay line system 13 made up of 3 1/3 ms. sections 15-18 and output signals are taken from switch 12 which changes con. tact in the sequence, 1, II, III, IV, V, I &c. at the 50 frame/sec. rate (i.e. after each 20 ms.) whereby there is produced a first intermediate signal comprising five out of each six input fields (the sixth, which is within the delay line system, being discarded when the switch moves from contact V to contact I) and in which each 60 c/s. field of 16 2/3 ms. is followed by a redundant information or blank interval of 3 1/3 ms. to make up the 20 ms. appropriate to a 50 c/s. signal. This signal is then applied to a binary delay store 19 which is arranged to increase its delay by 12À7 Ás. following each input line interval. A second intermediate signal is thus produced ...

Interpolation of images

STATISTICAL RESOLUTION CONVERSION TECHNIQUE

METHOD OF AND APPARATUS FOR PROCESSING TELEVISION SIGNALS

FARBFERNSEHWIEDERGABEGERAET

A flat-field television image having reduced visibility of horizontal scan lines is generated by receiving first and second fields of interlaced video and progressively generating a scanned image within a time for one incoming field. The progressive scanned image is formed from "real" and interpolated lines of luminance. In this arrangement the interpolated line is formed by weighting samples from time-successive lines. To improve the vertical detail of a progressively scanned image vertical detail information which may be obtained from the chrominance channel is combined with both "real" and interpolated lines, or one to the exclusion of the other, to enhance the image displayed.

SIGNAL PROCESSING SYSTEM

ULTRASONIC AND ROENTGEN VIDEO EXCHANGE SYSTEM AND - PROCEDURES

SCANNING UMSETZSCHALTUNG

A HIGH SPEED INTERPOLATION FILTER FOR TELEVISION STANDARDS CONVERSION

SIGNAL-PROCESSING SYSTEM

STANDARD CONVERTING APPARATUS

In a standard converting apparatus of the invention for converting a television signal of the high definition television standard, for example, into that of the NTSC standard, data of an odd field and an even field of the NTSC standard are developed from one field data of the high definition television standard and stored into memories. Thus stored data are consecutively read out to perform the reproduction of a still picture and slow reproduction. Because the reproduction of the still picture and the slow reproduction are done using one frame data of the odd field and even field, the picture becomes distinct. Also, since the odd and even fields are developed from one field data, double images are not reproduced even if a picture movement occurs.

STANDARD CONVERTING APPARATUS

IMAGE DATA CONVERSION PROCESSING DEVICE AND INFORMATION PROCESSING DEVICE HAVING THE SAME

An image data conversion processing device including an issue unit (8), plural line storing units (3) and a generating unit (4) for converting to a television signal image data stored in plural kinds of developing formats in a storing unit. The image data comprises plural lines, and the television signal comprises a predetermined number of lines. The issue unit issues a transmission instruction of image data to the storing unit in accordance with a period specified by a ratio of the line number of the image data to be converted and the line number of the television signal. The plural line storing units cyclically stores the image data transmitted from the storing unit line by line on the basis of the transmission instruction of the issue unit. In synchronism with the horizontal synchronizing signal of the television signal, the generating unit multiplies the image data stored in the line storing unit by an interpolative coefficient corresponding to the developing format of the image data ...

DIGITAL TELEVISION SYSTEM

... 77 DIGITAL TELEVISION SYSTEM A digital television system (10) is provided. System (10) may receive a video signal at composite video interface and separation circuit (16). The video signal is separated into separate video signals by composite video interface and separation circuit (16). The separate video signals are converted to digital video signals in analog to digital converter circuit (18). Line slicer (14) divides each line of digital video signal into a plurality of channels such that each channel may be processed in parallel by channel signal processors (22a) through (22d). Each channel signal processor (22a) through (22d) may provide two lines of output for each line of video input. The processed digital video signals may be formatted for displays (26a) through (26c) in formatters (24a) through (24c).

Sample rate converting device and method

Apparatus and method for converting interlaced image into progressive image

DEVICE OF CONVERSION Of a SIGNAL OF TELEVISION.

PROCESS AND DEVICE OF TRANSCRIBING OF the FREQUENCY Of ECHAN TILLONNAGE HAVE FOUR SAMPLES

PROCEDE ET DISPOSITIF DE TRANSCODAGE DE LA FREQUENCE D'ECHANTILLONNAGE A QUATRE ECHANTILLONS

L'INVENTION CONCERNE UN DISPOSITIF DE PRODUCTION D'UN SIGNAL INTERPOLE. SELON L'INVENTION, IL COMPREND UN MOYEN 203, 207, 209 POUR RETARDER UN SIGNAL D'ENTREE POUR PRODUIRE QUATRE ECHANTILLONS SUCCESSIFS F, F, F, F, RESPECTIVEMENT, UN MOYEN 211 POUR ADDITIONNER LES ECHANTILLONS F ET F POUR FORMER UN PREMIER ECHANTILLON DE SIGNAL ADDITIONNE; DES PREMIER ET SECOND MOYENS 215, 217 POUR MULTIPLIER LES ECHANTILONS DE SIGNAUX F ET F RESPECTIVEMENT PAR DES COEFFICIENTS MEMORISES SE RAPPORTANT AU RAPPORT DES FREQUENCES ECHANTILLONS D'ENTREE ET DE SORTIE POUR FORMER DES PREMIER ET SECOND SIGNAUX DE PRODUIT; UN TROISIEME MOYEN 213 POUR MULTIPLIER LES PREMIERS ECHANTILLONS DE SIGNAL ADDITIONNES PAR UN COEFFICIENT MEMORISE EN RAPPORT AVEC LE RAPPORT DES FREQUENCES DES ECHANTILLONS D'ENTREE ET DE SORTIE POUR FORMER UN TROISIEME SIGNAL DE PRODUIT; ET UN MOYEN 223, 225 POUR COMBINER LES PREMIER, SECOND ET TROISIEME SIGNAUX DE PRODUIT POUR FORMER LES SIGNAUX INTERPOLES G. L'INVENTION S'APPLIQUE NOTAMMENT ...

VIDEO AND PROCEEDED SYSTEM Of USE OF THIS ONE

Un système vidéo en temps réel qui effectue une interpolation non uniforme entre des lignes de balayage verticales adjacentes est présenté. Le système vidéo comporte un convertisseur (70), une mémoire (72), un circuit de vidéo renforcée (74) et un générateur de synchronisation. Le système vidéo décode et numérise un signal vidéo composite analogique, tel un signal NTSC, PAL ou SECAM, et génère un signal vidéo numérique ayant un nombre supérieur de lignes de balayage verticales à celui du signal vidéo analogique. Le système vidéo peut être programmé de façon à permettre la présence d'un nombre différent de lignes de balayage dans le signal vidéo numérique de sortie.

PROCESS AND STATISTICAL DEVICE OF CONVERSION OF RESOLUTION

Process of conversion of format of sequences of images present in a first network of pointsd' image, in a second network of points of image

Selon ce procédé, dans lequel on forme les valeurs de luminosité de points d'image (BPN) d'un second réseau par interpolation à partir des points d'image (BP) d'un premier réseau en sélectionnant des points situés sur des droites (Z) du premier réseau, qui sont voisines du point d'image formé (X), points qui sont fixés par des droites d'interpolation pivotées (LN), et on fixe des variations de la valeur de luminosité à partir de ces points avec détermination de la variation de luminosité dans la direction de la droite d'interpolation verticale (LN), puis exécution de cette détermination dans les deux sens de rotation, jusqu'à ce que la variation atteigne le minimum. Application notamment au système de conversion de format d'images entre des types de transmission différents.

TELEVISION CAMERA

IMAGE RECORDER FOR PROCESSING IMAGE OUTPUTTED FROM COMPUTER AND SYSTEM INCLUDING SAME

According to an embodiment of the present invention, an image recorder for storing a camera image transmitted from a camera comprises: an input terminal; a receiver for receiving a monitor image through the input terminal, converting a first color space of the monitor image into a second color space, and generating a first converted image having the second color space; a scaler for converting a first resolution of the first converted image to a second resolution and generating a second converted image having the second resolution; an encoder for compressing the second converted image and generating a compressed second converted image; and a storage device for storing the compressed second converted image. COPYRIGHT KIPO 2018 (200) Image recorder (310) Camera (320) Computer ...

IMAGE SIGNAL PROCESSING DEVICE

Method and apparatus for video image interpolation with edge sharpening

Video processing method and circuit using thereof

A video processing method for enlarging and enhancing sharpness of input video data includes the following steps. Firstly, N rows of pixel data are respectively buffered in N line buffers, wherein N is a natural number. Then, I rows of enlarged pixel data are obtained by means of interpolation according to the N rows of pixel data and a currently inputted N+1th row of pixel data, wherein I is a natural number greater than N. After that, I rows of smoothed and enlarged pixel data are obtained according to the N rows of pixel data and the N+1th row of pixel data. Then, I rows of sharpness enhanced pixel data are obtained according to the I rows of enlarged pixel data and the I rows of smoothed and enlarged pixel data.

Image processing apparatus, image processing method, and program

An image processing apparatus includes a down-converter and an image converter converting first image data into higher quality second image data. The image converter includes a prediction tap extracting unit extracting, as prediction taps, a plurality of pixels used for predicting a subject pixel of the second image data from the first image data, a class tap extracting unit extracting, as class taps, a plurality of pixels used for classifying the subject pixel from the first image data, a classification unit classifying the subject pixel based on the class taps, a coefficient output unit outputting a coefficient corresponding to a class of the subject pixel from among coefficients, determined beforehand by learning, corresponding to the plurality of classes, and a calculator determining the subject pixel by performing prediction calculations by using the coefficient corresponding to the class of the subject pixel and the prediction taps.

A METHOD FOR USING A SYNCHRONOUS SAMPLING DESIGN IN A FIXED-RATE SAMPLING MODE

The present application generally relates to apparatuses such as television signal processing apparatus that process radio frequency signals. More specifically, the present application is particularly useful in integrated circuits that must combine circuitry operating in a synchronous-sampling mode that must be adapted for use with a fixed rate sampling mode application. According to an exemplary embodiment, the television signal processing apparatus 100 comprises a source of a fixed rate digital signal 220, signal processing circuitry 240 operating in a synchronous-sampling mode wherein the signal processing circuitry 240 comprises a signal representing a symbol rate, and an interpolator 230 for processing the fixed rate digital signal to yield samples at the symbol rate.

A METHOD FOR USING A SYNCHRONOUS SAMPLING DESIGN IN A FIXED-RATE SAMPLING MODE

The present application generally relates to apparatuses such as television signal processing apparatus that process radio frequency signals. More specifically, the present application is particularly useful in integrated circuits that must combine circuitry operating in a synchronous-sampling mode that must be adapted for use with a fixed rate sampling mode application. According to an exemplary embodiment, the television signal processing apparatus 100 comprises a source of a fixed rate digital signal 220, signal processing circuitry 240 operating in a synchronous-sampling mode wherein the signal processing circuitry 240 comprises a signal representing a symbol rate, and an interpolator 230 for processing the fixed rate digital signal to yield samples at the symbol rate.

METHOD AND SYSTEM FOR MPEG CHROMA DE-INTERLACING

A method (300) of converting interlaced Moving Picture Experts Group (MPEG) video signals to progressive video signals can include receiving an interlaced video signal representing a luma component specifying luma lines and a chroma component specifying chroma lines (310) wherein the chroma component can specify approximately one-half the number of lines of the luma component. The interlaced video signal can be decoded and the number of the chroma lines can be increased to approximately the same as the number of the luma lines (320). The number of chroma lines of the interlaced video signal then can be decreased (340), to substantially reverse the previous increase. The interlaced video signal then can be deinterlaced to produce a progressive video signal (350), which can be processed further (360) as needed.

Video processing system and method with dynamic tag architecture

An image processing system and method, in which a plurality of image processing operations are dynamically controlled based on dynamically changing tag data associated with pixels being processed.

Motion detection apparatus as for an interlace to non-interlace scan converter

A detector for detecting motion in an image represented by a video signal includes delay elements for providing lines of signal from five consecutive fields. Sums of signals from first and second fields are subtracted from sums of signals from third and fourth fields to generate first motion indicators. Differences of signals from the first and second fields are subtracted from differences of signals from the third and fourth fields to generate second motion indicators. Differences of signals from the first and fifth fields are generated to form third motion indicators. The first, second and third motion indicators are compared and the largest is provided as a motion signal which is subsequently limited, spread and scaled. Signals used in forming the motion indicators are selected to substantially reject any adverse influence of the chrominance subcarrier.

Interpolation method for a video signal, and display device with function of interpolation for a video signal

A video signal interpolation can adapt an image of input video signal to voluntary aspect ratios widely. The invention also allows a display device to uniformly line-sequential scan and uses at least two line-memories (LM1, LM2) which are applied with an input digital video signal and controls writing and reading for these line-memories to generate a video signal subjected to vertical interpolation from a reading output of the line-memories. In the control, any one of the line-memories are circularly selected, and a sample sequence of the input digital video signal is sequentially written into the selected line-memory at its sample rate while sequentially reading out samples of the written sequence at a constant rate which is higher than the sample rate and which is according to a desired ratio of interpolation (vertical expansion ratio), wherein, when one of the line-memories is in writing operation, the other one of the line-memories is repeatedly read out. The invention also relates ...

Video signal processing circuit and method for converting number of scan lines and image display device using the same

A double-rate signal achieved by subjecting a video signal to double-rate conversion is supplied to a scan line number converter. In the converter, the portion of the effective scan lines of the double-rate signal is written into a frame memory on the basis of a signal achieved by multiplying horizontal and vertical synchronous signals based on the double-rate signal. In the effective scan line section of HDTV signal, the video signal written in the frame memory is read out on the basis of horizontal and vertical reference signals based on the HDTV signal. Out of the effective scan line section of the HDTV signal, a pedestal level signal written in a memory is read out on the basis of the horizontal and vertical reference signals based on the HDTV signal, thereby achieving HDTV signal whose vertical scan line number is equal to 1125 lines. Accordingly, the HDTV signal suffers no degradation because the video signal in the section of 960 effective scan lines of the double-rate signal is ...

Signal processing system

A CMOS integrated signal processing system for a sampling receiver includes a timing recovery circuit, wherein an on-chip numerically controlled oscillator is operative at periods T that are initially equal to the nominal baud rate of the signals controls a sinc interpolator receiving samples at the sampling rate. A loop filter is coupled to the sinc interpolator and to the numerically controlled oscillator. The arrangement is capable of handling various symbol rates. The system includes a circuit for carrier recovery having a second on-chip numerically controlled oscillator, a digital derotation circuit responsive to the second numerically controlled oscillator, accepting an in phase component and a quadrature component of the sampled signals. An adaptive phase error estimation circuit is coupled in a feedback loop.

Video and Graphics System with Video Scaling

A video and graphics system has a reduced memory mode in which video images are reduced in half in horizontal direction during decoding. The video and graphics system includes a video decoder for decoding MPEG-2 video data. The video images may not be downscaled in the horizontal direction when no bi-directionally predicted pictures are used. The video and graphics system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format. The output having an SDTV format may be recorded using a video cassette recorder (VCR) while the HDTV video is being displayed.

Video signal processing apparatus and video signal processing method

A video-signal processor includes: a first correlation detector obtaining a correlation value of every symmetric pair of pixels positioned in point-symmetry around an interpolation pixel on an interpolation line interpolated between two real lines; a second correlation detector obtaining a correlation value of every pair of pixels for the symmetric pair of pixels and parallel pair(s) of pixels positioned in a direction parallel to a direction of the symmetric pair of pixels; a correlation-direction deciding unit deciding one of a correlation direction based on the correlation value from the first correlation detector and that based on the correlation value from the second correlation detector as a correlation direction which is a direction of the pair of pixels used for generating the interpolation pixel; and an interpolation pixel generator generating a pixel signal of the interpolation pixel using a pair of pixels based on decision result of the correlation-direction deciding unit.

Electronic apparatus and control method thereof

Disclosed is an electronic apparatus. The electronic apparatus includes a memory configured to store a plurality of frames included in an input image and a processor configured to: identify whether one frame of the plurality of frames is a first interpolated frame generated based on at least two frames from remaining frames of the plurality of frames, and select a reference frame to be used in frame interpolation of the plurality of frames based on the first interpolated frame being identified.

Method for generating distances representative of the edge orientations in a video picture, corresponding device and use of the method for deinterlacing or format conversion

The present invention relates to a method and device for the generation of a distance representative of the edge orientation at a current point of a video picture. The distances generated are particularly used for the deinterlacing or format conversion of video pictures. It can be implemented in a video coder or decoder. According to the invention, the distances representative of the edge orientation calculated are filtered with a conditional median filter applied to a window of p by q distances. This filter only takes into account the distances of points for which the local gradient module of the video components is greater than a threshold.

Video signal format converting circuit

Method and system for processing of a video signal

A video signal processing system for processing a video data VIN and graphic data DmuP includes a filter unit, which receives the video data VIN. The filter unit filters the video data VIN to convert the video data VIN into video pictures formated with a different number of columns and/or lines, and provides a filtered video signal indicative thereof. The filter unit buffers individual pixels and/or lines in a first memory device. A second memory device receives and stores the graphic data DmuP and the filtered video signal and provides stored signals indicative thereof. A third memory device is connected to the second memory, and stores data received from the second memory device. A mixing unit receives and mixes the stored graphic data and the stored filtered video data to provide a video output signal VOUT.

A sampling frequency conversion filter

IMAGE DISPLAY DEVICE AND METHOD, AND IMAGE PROCESSING DEVICE AND METHOD

PROBLEM TO BE SOLVED: To prevent deterioration particularly in the image quality of a telop portion in an image display device provided with a frame rate conversion (FRC) unit. SOLUTION: An FRC unit 100 includes a moving vector detecting unit 101 and an interpolation frame generating unit 102. The moving vector detecting unit 101 is comprised of a frame delaying unit 1 for delaying an input signal by one frame, an initial displacement vector selecting unit 2 for selecting and outputting an initial displacement vector used for detecting a vector, a moving vector arithmetic operation unit 3 for detecting the moving vector using the initial displacement vector, a vector memory 4 for saving a vector detecting result, and a telop information detecting unit 5 for detecting one or more telop existing domains and their moving speed using the vector detecting result for a previous frame supplied from the vector memory 4. The detection result of the telop information detecting unit 5 is reflected ...

СПОСОБ И УСТРОЙСТВО ДЛЯ ПЕРЕДАЧИ ИЗОБРАЖЕНИЯ

Способ получения служащей прежде всего для создания у зрителя визуального впечатления об имеющем временную размерность событии второй (целевой) последовательности кадров со второй частотой кадросмен и вторым соответствующим интервалом длительности изображений из первой (исходной) последовательности кадров с первой частотой кадросмен и первым соответствующим интервалом длительности изображений состоит в том, что при этом по меньшей мере часть изображений целевой последовательности кадров формируют путем аддитивного наложения по меньшей мере двух соседних по времени изображений исходной последовательности кадров, нормированных весовым коэффициентом интенсивности, причем все изображения целевой последовательности кадров получают путем наложения по меньшей мере двух изображений исходной последовательности, покадрово нормированных индивидуально рассчитанными весовыми коэффициентами интенсивности. Техническим результатом изобретения является коррекция дрожания кадров изображения при воспроизведении ...

Signalverarbeitungssystem

APPARATUS FOR STANDARDS CONVERSION OF COLOUR TELEVISION SIGNALS

Abwärts-Videoformatumwandlung

VERARBEITUNG VON VIDEOSIGNALEN

Gradient-based method for pixel interpolation e.g. for TV images, requires initial selection of first and second picture elements each assigned first and second image /picture information values

A method for interpolating a picture element (pixel) (P(x,y)) in an image/picture having a number of picture elements arranged in a matrix to each of which is assigned an image information value, involves selecting at least one first picture element (P( x+1, y)) assigned a first image information value (L( x+1, y)) and a second picture element assigned a second image information value (L( x-1, y)), determining in each case a gradient of the image information value, ascertaining a picture information value (L(x,y)) of the picture element to be interpolated by using the respective first information value and the second information value, in which the image information value (L( x+1, y)) of the picture element (P(x+1) y));P(x-1, y) is more heavily weighted and its associated gradient is smaller.

Gemeinsamer Zwischenformat-Umwandler mit verringerter Multipliziereranzahl

Method for sub-pixel value interpolation

Methods, apparatuses and computer programs for adapting content

A method comprising generating, for primary content to be broadcasted for output on a primary content output device, rendering adaptation information configured for use in adapting the rendering of the primary content on a secondary content output device thereby providing an output of secondary content which is derived from the broadcasted primary content; wherein the primary content comprises at least a first media portion having a first temporal output characteristic; wherein the rendering adaptation information comprises temporal information configured for use in adjusting the rendering of the at least first media portion so as to enable generation of secondary content comprising at least a second media portion having a second temporal output characteristic that can differ from the first temporal output characteristic of the at least first media portion. Also disclosed is a method comprising receiving the above primary content and rendering adaption information in order to generate secondary ...

Method and processor for streaming video processing

A method of video processing comprises performing sequentially one or a plurality of second image process (filtering) steps on an input image to generate an output image, wherein at least one of the second image processing steps achieves the effect of at least two, three, four, or five of first image process steps, selected from up-sampling, de-interlacing, a resizing, a vertical and horizontal resizing; a packet loss reconstruction, or data padding or data interpolation techniques used in combination with resizing and/or packet loss reconstruction. First, initial steps may comprise separable vertical and horizontal chroma up-sampling, motion adaptive de-interlacing, separable resizing, and missing data reconstruction. Second image steps may be implemented as a poly phase filter, clamped between the results of two other linear filters. Convolution filtering, e.g. per colour component, and diagonal filtering may be used.

Interpolator for use in signal processing

Image processor and method of processing images

Global motion-compensated sequential-scanning method considering horizontal and vertical patterns

TELEVISION STANDARDS CONVERSION

... 1391434 Television standards conversion BRITISH BROADCASTING CORP 24 March 1972 [26 March 1971] 7969/71 Heading H4F Television line standard conversion is effected by the following steps in either order (i) synthesising each output line by combining information taken from two or more input lines, and (ii) changing the line frequency by a simple ratio of small integers which ratio is slightly different from the actual ratio of the output to input line frequencies. When the simple ratio is slightly greater than the ratio of the output to input line frequencies, e.g. 3 : 2 for 625 to 405 conversion, or 5 : 6 or 4 : 5 for 525 to 625 conversion, then surplus lines are eliminated. The interpolation, i.e. synthesising of each output line, is effected with six one-line period delays connected in series, the resulting simultaneously available seven input lines being added together with different weighting coefficients. The line frequency changing, i.e. time redistribution, is effected using eight ...

Method for making look-up tables for video format conversion and scan format converter using the look-up tables

Objective picture quality measurement

SIGNAL PROCESSING SYSTEM

PROCESSING OF VIDEO SIGNALS

DIGITAL TELEVISION STANDARD TRANSFORMATION

DISPLAY SYSTEM FOR THE MIXTURE OF GRAPHIC DATA AND VIDEO DATA

FARBFERNSEHWIEDERGABEGERAET

MOVEMENT DETECTOR AS FOR A SCANNING CONVERTER OF LINE INTERLACING INTO WITHOUT LINE INTERLACING.

MORE BILINEARER DEZIMATOR WITH ERROR COMPENSATION

Signal processing system

Scanning conversion circuit

LOW BIT RATE COMPRESSION FORMAT CONVERSION FOR IMPROVED RESOLUTION

System and methods for 2-tap/3-tap flicker filtering

PROGRESSIVE SCAN TELEVISION SYSTEM

MULTIMODE VIDEO CONTROLLER FOR ULTRASOUND AND X-RAY VIDEO EXCHANGE SYSTEM

... ▓▓▓Systems and methods for exchanging ultrasound and X-ray video signals are ▓disclosed. The system may select an analog X-ray input signal from, for ▓example, either a fluoroscopic or roadmap video signal according to user ▓input. The analog X-ray input signal is digitized and converted using the ▓appropriate video conversion factors to a standard high-resolution format ▓suitable for display on, for example, an intravascular ultrasound monitor. The ▓digitized X-ray signal is electrically isolated from the graphics cards ▓operating the intravascular ultrasound display. The system also digitizes high-▓resolution ultrasound video and converts it to a format suitable for display ▓on a hospital X-ray monitor. The converted and digitized ultrasound video is ▓electrically isolated from the hospital X-ray monitors.▓ ...

METHOD AND SYSTEM FOR PREDICTIVE SCALING OF COLOUR MAPPED IMAGES

A method for scaling an original colour mapped image are disclosed. The method performs steps of transforming the original colour map into the scaled colour map based on the original colour map and the original image independently of the scaled image, scaling the original image into the scaled image, for each pixel of the scaled image determining a set of contributing pixels in the original image, which define a colour of the pixel, determining the colour of the pixel based on colours of the con-tributing pixels and geometric proximity of the pixel to the con-tributing pixels, establishing correspondence between the colour of the pixel and a colour in the scaled colour map, and determin-ing a corresponding colour map index thereof, and setting the de-termined colour map index in the scaled pixel map A correspond-ing system for scaling digital images is also provided.

TIME-BASE CONVERSION SYSTEM

A time-base conversion system including a first clock generator for generating a read clock based on a reference signal, a second clock generator for generating a write clock by dividing the read clock, a memory, a circuit for writing video data in the memory based on the write clock, a circuit for reading the video data recorded in the memory based on the read clock. and a time-base compressor for determining a compression ratio of the video data time-base by determining a division ratio of the write clock.

METHOD AND DEVICE FOR PROCESSING A VIDEO IMAGE

The invention concerns a method of processing a video image with image points in m1 lines, the points in the l1-th line having an intensity I1(t, l1) which depends on a parameter t, in particular time, in order to generate a second video image with m2 lines. The invention calls for the intensity I2(t, l2) of each image point in the l2-th line of the second video image to be interpolated from the intensities of the image points of the first video image I1(t, l1), the intensity I2 being obtained from the equation: I2(t,l2)=Max¢J(t,l2)+.DELTA.;0! in which J represents values, discretized with respect to the lines, of changes in signal defined by the scan theorem and which includes an offset .DELTA. for partial compensation of negative intensities of the discretized changes J in the signal, so that the interpolation is carried out with respect to the lines with A as a freely determined positive-value amplitude in accordance with the equation (1). The invention also concerns a device including ...

Graphics display system with video scaler

A method for processing video data includes performing by one or more processors and/or circuits in a video processing device, the one or more processors and/or circuits including a video scaler, a memory, and a scaler engine, functions including receiving a video image by the video processing device. The functions also include determining whether the video scaler requires less memory bandwidth to scale the video image before writing the video image to the memory or after reading the video image from the memory, and scaling the video image based on the determination. If the video scaler requires less memory bandwidth to scale the video image before writing the video image to the memory, performing by the one or more processors and/or circuits scaling of the video image in the video scaler using a video input clock of the video scaler to generate a first scaled video image.

Display device and display method

A display device includes: a display unit including plural display sections divided in a first direction and performing line sequential scanning in the first direction; and an interpolation picture generation unit generating an interpolation picture in accordance with a timing at which each display section is scanned based on supplied frame pictures, wherein the display unit displays the interpolation picture corresponding to the display section in each display section.

Display apparatus and control method thereof

A display apparatus includes a conversion unit for converting first video data having a first frame rate to second video data having a second frame rate which is “n” times as high as the first frame rate (“n” being an integer of two or larger), and a display unit for displaying the second video data. When the first video data is video data of two successive frame images having different brightnesses, the conversion unit performs a first frame rate converting process for converting the first video data to the second video data by outputting a frame image group made of two successive frame images in the first video data “n” times in a row at the second frame rate. Consequently, the frame rate converting process can be performed without causing a deterioration of a visual effect such as an HDR effect, and a viewing environment comfortable for the user can be realized.

Image interpolation method and apparatus

An image interpolation method and apparatus are provided. The image interpolation method includes: selecting different interpolation filters according to locations of sub pixels between integer pixels; and generating sub pixel values at the locations of the sub pixels using the selected interpolation filters.

Ringing suppression in video scalers

Embodiments are generally directed to ringing suppression in video scalers. An embodiment of a method includes receiving a stream of video data, received video data including sets of video data values, and storing a first set of video data values in a memory. A first set of scaled values for the set of video data values is determined based on a scaling technology, and a second set based on linear interpolation. The method includes detecting rate of change in amplitude for received video data, generating a mixing control signal based at least in part on the rate of change, mixing first set of scaled values and second set of scaled values based at least in part on mixing control signal to generate blended set of coefficients, and generating scaled video data output using the set of blended values.

VIDEO CONTROL DEVICE AND VIDEO CONTROL METHOD

A first quantization unit quantizes data of each pixel constituting a first frame data by a first logical formula to generate a second frame data with a predetermined number of lower bits deleted. A delay memory temporarily holds the second frame data and outputs third frame data. Interpolation unit generates interpolated frame data located between adjacent frames in the second frame data by using the second frame data and the third frame data. A second quantization unit quantizes data of each pixel constituting the first frame data by a second logical formula different from the first logical formula to generate a fourth frame data with a predetermined number of lower bits deleted. A frame memory temporarily holds the fourth frame data and the interpolated frame data, and outputs the fourth frame data and the interpolated frame data alternately at a second frame rate higher than the first frame late. 1. A video control device , comprising:a data acquisition unit configured to acquire first frame data having a first frame rate;a first quantization unit configured to quantize data of each pixel constituting the first frame data by a first logical formula to generate a second frame data with a predetermined number of lower bits deleted;a delay memory configured to temporarily hold the second frame data and output third frame data obtained by delaying the second frame data;one or a plurality of interpolation units configured to generate one or a plurality of sets of interpolated frame data located between adjacent frames in the second frame data by using the second frame data and the third frame data;one or a plurality of second quantization units configured to quantize data of each pixel constituting the first frame data or the interpolated frame data by a second logical formula different from the first logical formula to generate a fourth frame data with a predetermined number of lower bits deleted;a frame memory configured to temporarily hold the fourth frame data ...

LOW LATENCY CADENCE DETECTION FOR FRAME RATE CONVERSION

A receiver is configured to receive video frames. A cadence detector is in communication with the receiver and is configured to analyze a newly received video frame to determine the cadence of the video frames. A frame rate converter is configured to interpolate at least two of the video frames to form output frames in accordance with an interpolation parameter based on the cadence and with a frequency scaling factor. The frequency scaling factor corresponds to the frame rate of the output frames. 1. A method , comprising:receiving a plurality of video frames;adjusting an interpolation parameter based on detecting a cadence of the plurality of video frames; andinterpolating at least two of the plurality of video frames that were received based on the interpolation parameter and a frequency scaling factor to form a plurality of output frames, the frequency scaling factor corresponding to a frame rate for the plurality of output frames.2. The method of claim 1 , further comprising analyzing a newly received video frame to determine the cadence of the plurality of video frames.3. The method of claim 2 , wherein the interpolating is performed prior to a completion of the analyzing.4. The method of claim 1 , further comprising receiving an indicator of the cadence from an upstream video processor.5. The method of claim 4 , wherein the interpolation parameter indicates a position in fractional fourths relative to two of the plurality of video frames when the indicator of the cadence corresponds to a 2:2 pull-down pattern.6. The method of claim 1 , wherein the at least two of the plurality of video frames are chosen based on the cadence.7. The method of claim 1 , wherein the interpolation parameter identifies a position of at least one of the plurality of output frames relative to two of the plurality of video frames.8. The method of claim 1 , wherein detecting the cadence comprises comparing a first one of the plurality of video frames to a second one of the plurality of ...

TEMPORAL ALIASING REDUCTION AND CODING OF UPSAMPLED VIDEO

Embodiments of the invention provide techniques for upsampling a video sequence for coding. According to the method, an estimate of camera motion may be obtained from motion sensor data. Video data may be analyzed to detect motion within frames output from a camera that is not induced by the camera motion. When non-camera motion falls within a predetermined operational limit, video upsampling processes may be engaged. In another embodiment, video upsampling may be performed by twice estimating image content for a hypothetical new a frame using two different sources as inputs. A determination may be made whether the two estimates of the frame match each other sufficiently well. If so, the two estimates may be merged to yield a final estimated frame and the new frame may be integrated into a stream of video data. 1. A video recording device , comprising:a camera to capture image information and generate corresponding video data comprising a plurality of frames,a motion sensor to detect the orientation of the camera in free space and generate corresponding orientation data,a controller to interpret the orientation data and generate motion estimation data; anda video preprocessor to analyze the motion estimation data, determine non-camera motion in the video data, and enable upsampling of the video data when the non-camera motion is below a predetermined threshold.2. The device of claim 1 , wherein the preprocessor determines non-camera motion by comparing estimated image content of a frame and actual image content of the frame at a given time.3. The device of claim 1 , wherein the preprocessor enables upsampling of the video data if the non-camera motion is below the threshold and disables upsampling if the non-camera motion is above the threshold.4. The device of claim 1 , wherein the preprocessor determines whether the non-camera motion for a set of frames of a predetermined period of time is lower than the threshold for the entirety of the predetermined period ...

Image processing apparatus and image processing method

Each frame image is acquired as an input image. An image obtained by emphasizing high frequency components in the input image is generated as a high frequency component emphasized image, a composite image is generated by compositing the input image and an input image of a previous frame before the input image, and an image including low frequency components in the composite image is generated as a low frequency component image. Then, the high frequency component emphasized image and low frequency component image are alternately output as images of sub-frames of the input image.

Interpolation of images

Apparatus for interpolating images generates motion vectors having a vector confidence value and has a motion compensated interpolation to use the motion vectors to interpolate a new image from two input images at a position determined by a phase control signal. The vector confidence values are used to generate an interpolation confidence measure. The phase control signal is then modified to offset the position at which the new image is interpolated toward the position of the closer of the two input images, if said interpolation confidence measure reduces.

System and method for efficient video-based monitoring of traffic violations

A system and method for efficient video-based traffic monitoring are provided. The method includes receiving a first video stream potentially capturing road behavior violations; converting the first video stream into a second video stream, the first video stream having a first data rate and the second video stream having a second data rate, wherein the second data rate is lower than the first data rate; transmitting the second video stream to a remote node; receiving a request from the remote node for at least one portion of the first video stream; and transmitting the at least one portion of the first video stream, wherein the at least one portion is transmitted at the first data rate.

IMAGE DATA OUTPUT DEVICE, IMAGE DATA OUTPUT METHOD, INTEGRATED CIRCUIT, AND IMAGE DISPLAY DEVICE

Provided are an image data output device, an image data output method, an image display device, and an integrated circuit that are possible to eliminate stutter by selecting a frame rate from a plurality of frame rate candidates. The image data output device that switches a frame rate of a generated image for each frame and outputs the image to an image display device includes an image generation unit that, on a basis of image generation time required to generate the image, changes the frame rate to one of a plurality of frame rates which are predetermined. 1. An image data output device that switches a frame rate of a generated image for each frame and outputs the image to an image display device , the image data output device comprisingan image generation unit that, on a basis of image generation time required to generate the image, changes the frame rate to one of a plurality of frame rates which are predetermined.2. The image data output device according to claim 1 , whereinthe image is output to the image display device with a horizontal blanking interval and a vertical blanking interval and either or both lengths of the horizontal blanking interval and the vertical blanking interval are adjusted for each frame to thereby switch the frame rate.3. The image data output device according to claim 1 , whereinthe image generation unitnotifies the image display device of the frame rate of each frame.4. The image data output device according to claim 1 , further comprisinga control unit that determines a low frame rate threshold on a basis of which the frame rate is switched and a low frame rate candidate that has at least one element, whereinthe image generation unit changes the frame rate to one element of the low frame rate candidate, in a case where an image generation frequency that is an inverse number of the image generation time falls below the low frame rate threshold.5. The image data output device according to claim 4 , whereinthe control unitdetermines the ...

Trick Play Using CRT Scan modes

Video frames of a performance are provided at times at a slower input rate and at other times at a faster input rate. A video display is automatically switched to a first display scan mode when receiving frames at the slower input rate, and switched to a second display scan mode when receiving frames at the faster input rate. The second display scan mode being different than the first display scan mode. For example, the display scan modes may have different frame rates or the first display mode may be progressive and the second display scan mode may be interlaced. 1. A method comprising:at times, receiving video frames at a slower frame rate;at other times, receiving video frames at a faster frame rate;switching a video display to display frames in first display scan mode when receiving frames at the slower frame rate; andswitching the video display to display frames in a second display scan mode when receiving frames at the faster frame rate, the second display scan mode being different than the first display scan mode.2. The method of claim 1 , wherein: the slower frame rate is equal to a normal play rate of the video performance claim 1 , and the faster frame rate is associated with a fast motion trick mode.3. The method of claim 1 , wherein the frames received in both the slower frame rate and the faster frame rate are in a progressive scan format claim 1 , the first display scan mode being a 25 Hz or 30 Hz progressive scan mode claim 1 , and the second display scan mode being a 50 Hz or 60 Hz progressive scan mode.4. The method of claim 1 , wherein the frames received in both the slower frame rate and the faster frame rate are in a 2× interlaced scan format claim 1 , the first display scan mode being a 50 Hz or 60 Hz 2× interlaced scan mode claim 1 , and the second display scan mode being a 100 Hz or 120 Hz 2× interlaced scan mode.5. The method of claim 1 , the method comprising repeating the display of frames received at the slower frame rate to provide a ...

IMAGE PROCESSING APPARATUS WITH A LOOK-UP TABLE AND A MAPPING UNIT, IMAGE PROCESSING METHOD USING A LOOK-UP TABLE AND A MAPPING UNIT, AND STORAGE MEDIUM IN WHICH PROGRAM USING A LOOK-UP TABLE AND A MAPPING UNIT IS STORED

An image processing apparatus includes a storage unit that stores a look-up table having association information for associating at least one first image with at least one second image that is an image whose load on a brain has been adjusted, an image accepting unit that accepts at least one image, a mapping unit that acquires a whole or part of one or more second images associated with a whole or part of the at least one image accepted by the image accepting unit, using association information from among the one or more pieces of association information, and an image output unit that outputs at least one output image, which is the whole of the at least one second image acquired by the mapping unit or a group of part of the at least one second image acquired by the mapping unit. 1. An image processing apparatus , comprising:a storage unit that stores a look-up table having one or at least two pieces of association information for associating the whole or part of one or at least two first images with the whole or part of at least one second image, which is an image whose load on the brain has been adjusted compared with that of the first image and which is an image of the same object as the first image;an image accepting unit that accepts one or at least two images;a mapping unit that acquires the whole or part of one or at least two second images associated with the whole or part of the at least one image accepted by the image accepting unit, using association information from among the one or at least two pieces of association information; andan image output unit that outputs at least one output image, which is the whole of the at least one second image acquired by the mapping unit or a group of part of the at least one second image acquired by the mapping unit.2. The image processing apparatus according to claim 1 , whereinthe association information for associating the whole or part of one or at least two first images with the whole or part of at least one second ...

IMAGE PROCESSING APPARATUS, IMAGE PROCESSING METHOD, AND STORAGE MEDIUM IN WHICH PROGRAM IS STORED

An image processing apparatus includes a storage unit that is capable of storing a look-up table having association information for associating at least one first image with at least one second image that is an image whose load on a brain has been adjusted, an image accepting unit that accepts at least one image, a mapping unit that acquires a whole or part of one or more second images associated with a whole or part of the at least one image accepted by the image accepting unit, using association information from among the one or more pieces of association information, and an image output unit that outputs at least one output image, which is the whole of the at least one second image acquired by the mapping unit or a group of part of the at least one second image acquired by the mapping unit. 1. An image processing apparatus , comprising:a storage unit that is capable of storing a look-up table having one or more pieces of association information for associating a whole or part of one or more first images with a whole or part of at least one second image, which is an image whose load on a brain has been adjusted compared with that of the first image and which is an image of a same object as the first image;an image accepting unit that accepts one or more images;a mapping unit that acquires a whole or part of one or more second images associated with a whole or part of the at least one image accepted by the image accepting unit, using association information from among the one or more pieces of association information; andan image output unit that outputs at least one output image, which is the whole of the at least one second image acquired by the mapping unit or a group of part of the at least one second image acquired by the mapping unit.2. The image processing apparatus according to claim 1 , whereinthe look-up table has at least two pieces of association information,the image processing apparatus further comprises an image analysis unit that determines the ...

SYSTEM AND METHOD FOR VIDEO PROCESSING WITH ENHANCED TEMPORAL CONSISTENCY

A system and method for processing an input video while maintaining temporal consistency across video frames is provided. The method includes converting the input video from a first frame rate to a second frame rate, wherein the second frame rate is a faster frame rate than the first frame rate; generating processed frames of the input video at the second frame rate; and aggregating the processed frames using temporal sliding window aggregation to yield a processed output video at a third frame rate. 1. A method for processing an input video while maintaining temporal consistency across video frames , the method comprising:converting the input video from a first frame rate to a second frame rate, wherein the second frame rate is a faster frame rate than the first frame rate;generating processed frames of the input video at the second frame rate; andaggregating the processed frames using temporal sliding window aggregation to yield a processed output video at a third frame rate.2. The method of claim 1 , wherein converting the input video from the first frame rate to the second frame rate comprises:determining an intermediate frame by calculating a weighted sum of a first video frame at a first time step and a second video frame at a second time step.3. The method of claim 2 , wherein calculating the weighted sum of the first video frame at the first time step and the second video frame at the second time step comprises:calculating a forward warping grid from the first video frame to a third time step corresponding to the intermediate frame;calculating a backward warping grid from the second video frame to the third time step corresponding to the intermediate frame;determining the intermediate frame at the third time step by bilinearly warping the first video frame and the second video frame to the third time step.4. The method of claim 1 , wherein converting the input video from the first frame rate to the second frame rate comprises:converting both the input video ...

VIDEO INTERPOLATION USING ONE OR MORE NEURAL NETWORKS

Apparatuses, systems, and techniques to enhance video. In at least one embodiment, one or more neural networks are used to create, from a first video, a second video having a higher frame rate, higher resolution, or reduced number of missing or corrupt video frames. 1. A processor comprising:one or more arithmetic logic units (ALUs) to be configured to generate higher frame rate video from lower frame rate video using one or more neural networks.2. The processor of claim 1 , wherein one or more neural networks are trained using unsupervised training with at least one cycle consistency constraint.3. The processor of claim 2 , wherein the unsupervised training includes generating claim 2 , from a frame triplet claim 2 , a set of intermediate frames and generating a version of a middle triplet frame from the intermediate frames for determining a loss value to be minimized.4. The processor of claim 1 , wherein the one or more neural networks are refined using pseudo-supervised training for a domain other than was used for training the one or more neural networks.5. The processor of claim 4 , wherein the pseudo-supervised training includes generating claim 4 , using one or more already trained neural networks claim 4 , versions of an intermediate frame using each of two adjacent video frames for determining a loss value to be minimized.6. The processor of claim 1 , wherein the one or more neural networks utilize one or more image interpolation algorithms.7. The processor of claim 1 , wherein the one or more ALUs are further to be configured to generate enhanced video claim 1 , using the one or more neural networks claim 1 , having a higher resolution or lower frame drop rate than input video.8. A system comprising:one or more processors to be configured to generate higher frame rate video from lower frame rate video using one or more neural networks; andone or more memories to store the one or more neural networks.9. The system of claim 8 , wherein one or more neural ...

IMAGE PLAYBACK DEVICE, DISPLAY DEVICE, AND TRANSMISSION DEVICE

The system includes a display device causing a display unit to display video; a data transmission unit that transmits, to the display device, video data generated in a predetermined format based on information decoded from encoded information, and interpolation data for interpolating differences between the predetermined format and a format when decoding from the encoded information; an interpolation data selection unit that selects a kind of interpolation data to be transmitted to the display device, on the basis of priorities for a plurality of kinds of the interpolation data capable of being generated based on the encoded information; and a display processing unit that acquires the video data and the selected kind of the interpolation data in the display device, and causes the display unit to display video resulting from interpolation of the video data based on the interpolation data. 1. (canceled)2. A video playback apparatus comprising:a transmission apparatus configured to transmit video data; anda display apparatus configured to receive the video data transmitted from the transmission apparatus via an interface and display an image based on the video data,wherein the transmission apparatus comprises a first processor programmed to:receive an encoded data stream,generate decoded video data in a first format by decoding the encoded data stream,generate list information of available interpolation data indicating a plurality of kinds of interpolation data based on the decoded video data in the first format and video data in a second format being outputted to the display apparatus and transmit the list information to the display apparatus,receive selection information indicating a kind of interpolation data selected from the list information, from the display apparatus,generate the video data in the second format and interpolation data from the decoded video data in the first format based on the received selection information, andtransmit the generated video data ...

VIDEO SYSTEM WITH FRAME SYNTHESIS

A remote vehicle control system includes a vehicle mounted sensor system including a video camera system for producing video data. A data handling system is connected to a network to transmit data to and receive data from a remote teleoperation site. A virtual control system is configured to receive the video, provide a user with a live video stream supported by machine intelligence directed frame synthesis, and transmit control instructions to the remote vehicle over the network. The frame synthesis is supported by a convolutional neural network. The frame synthesis may be used to interpolate frames to increase effective frames per second. The frame synthesis may be used to extrapolate frames to replace missing or damaged video frames. 1. A remote vehicle control system comprising:a vehicle mounted sensor system including a video camera system for producing video data;a data handling system connected to a network to transmit data to and receive data from a remote teleoperation site; anda virtual control system configured to receive the video, provide a user with a live video stream supported by frame synthesis, and transmit control instructions to the remote vehicle over the network.2. The remote vehicle control system of claim 1 , wherein the network is a cell phone network.3. The remote vehicle control system of claim 1 , wherein frame synthesis is supported by a convolutional neural network.4. The remote vehicle control system of claim 1 , wherein frame synthesis is used to interpolate frames to increase effective frames per second.5. The remote vehicle control system of claim 1 , wherein frame synthesis is used to extrapolate frames to replace missing or damaged video frames.6. The remote vehicle control system of claim 1 , wherein the data handling system can compress and transmit the video over a cellular network using feed forward correction.7. The remote vehicle control system of claim 1 , wherein the virtual control system further comprises a virtual ...

Systems and Methods for Adaptive Scaling of Digital Images

Systems and methods are provided for upscaling a digital image. A digital image to be upscaled is accessed, where the digital image comprises a plurality of pixel values. A first half pixel value is computed for a first point in the digital image based on a plurality of pixel values of the digital image surrounding the first point and an activity level. A second half pixel value is computed for a second point in the digital image, and an interpolated pixel of an upscaled version of the digital image is determined using a plurality of the pixel values, the first half pixel value, and the second half pixel value.

IMAGE PROCESSING APPARATUS, IMAGE PROCESSING METHOD, AND PROGRAM

An image processing apparatus includes: a normal interpolated image generation unit to generate an image that is interpolated between a plurality of original images reproduced along time series, the image being a normal interpolated image, based on each of the plurality of original images; a high-frequency area extraction unit to extract a high-frequency area having a spatial frequency higher than a predetermined value in each of the plurality of original images; a high-frequency area interpolated image generation unit to generate an image that is interpolated between the plurality of original images, the image being a high-frequency area interpolated image, based on a change in position of the high-frequency area along with an elapse of time on the time series and on each of the plurality of original images; and a combination unit to execute combining processing to combine the normal interpolated image and the high-frequency area interpolated image. 1. An image processing apparatus , comprising:a normal interpolated image generation unit configured to generate an image that is interpolated between a plurality of original images reproduced along time series, the image being a normal interpolated image, based on each of the plurality of original images;a high-frequency area extraction unit configured to extract a high-frequency area having a spatial frequency higher than a predetermined value in each of the plurality of original images;a high-frequency area interpolated image generation unit configured to generate an image that is interpolated between the plurality of original images, the image being a high-frequency area interpolated image, based on a change in position of the high-frequency area along with an elapse of time on the time series and on each of the plurality of original images; anda combination unit configured to execute combining processing to combine the normal interpolated image and the high-frequency area interpolated image.2. The image processing ...

Frame Rate Extrapolation

In one implementation, a method of frame rate extrapolation is performed by a device including one or more processors, non-transitory memory, a scene camera, and a display. The method includes capturing, using the scene camera, an image of a scene. The method includes displaying, on the display, the image of the scene at a first time. The method includes generating an extrapolated image by transforming, using the one or more processors, the image of the scene based on movement of the device, wherein the extrapolated image includes a first area including a first plurality of pixels having respective first pixel values based on a single depth and a second area including a second plurality of pixels having respective second pixel values based on a plurality of depths. The method includes displaying, on the display, the extrapolated image at a second time after the first time. 118-. (canceled)19. A method comprising:at a device including one or more processors, non-transitory memory, and a display:obtaining an image of a scene;displaying, on the display, the image of the scene at a first time;generating an extrapolated image by transforming, using the one or more processors, the image of the scene based on movement of the device, wherein the extrapolated image includes a first area including a first plurality of pixels having respective first pixel values based on a single depth and a second area including a second plurality of pixels having respective second pixel values based on a plurality of depths; anddisplaying, on the display, the extrapolated image at a second time after the first time.20. The method of claim 19 , wherein transforming the image of the scene based on the movement of the device includes obtaining motion data indicative of a translation and/or a rotation of the device and transforming the image of the scene based on the motion data.21. The method of claim 20 , wherein the motion data is indicative of a translation and/or a rotation of the device ...

COMPUTED INFORMATION FOR METADATA EXTRACTION APPLIED TO TRANSCODING

Systems, methods and articles of manufacture for transcoding video content are described. Embodiments include receiving an instance of video content for processing. A plurality of shots within the instance of video content is determined. Embodiments analyze the instance of video content to generate metadata describing the media content. The generated metadata includes, for each of the plurality of shots, data describing a plurality of frames within the respective shot. An optimized transcoding schedule for transcoding the instance of video content from a first video encoding format to a second video encoding format is generated based on the generated metadata. Embodiments further include transcoding the instance of video content according to the optimized transcoding schedule. 1. A method , comprising:receiving an instance of video content for processing;determining a plurality of shots within the instance of video content;analyzing the instance of video content to generate metadata describing the media content, wherein the generated metadata includes, for each of the plurality of shots, data describing a plurality of frames within the respective shot;generating, by operation of one or more computer processors, an optimized transcoding schedule for transcoding the instance of video content from a first video encoding format to a second video encoding format, based on the generated metadata; andencoding the instance of video content according to the optimized transcoding schedule.2. The method of claim 1 , further comprising:storing the generated metadata for use by non-transcoding services.3. The method of claim 1 , wherein analyzing the instance of video content further comprises:determining, for each of the plurality of shots, a measure of motion within the plurality of frames within the respective shot,wherein the generated metadata includes the determined measure of motion for each of the plurality of frames.4. The method of claim 3 , wherein generating the ...

IMAGE PROCESSING DEVICE

An image processing device includes a frame memory, an image input unit, an image quality converter that converts, on a frame basis, image quality of image information stored in the frame memory, an image output unit that reads the image information from the frame memory and outputs the image information to a display device, a controller that controls a function of the image quality converter based on a traveling state of the vehicle and changes a frame delay amount from when each of frames of the image information is received until when the frame is outputted from the image output unit, and an interpolation frame setting unit that sets an interpolation frame of the image information to be outputted in a transition period in which the controller changes the frame delay amount from a first frame delay amount to a second frame delay amount. 1. An image processing device comprising:a frame memory in which image information is stored on a frame basis;an image input unit that receives and stores the image information about a captured image of a surrounding of a traveling vehicle in the frame memory;an image quality converter that converts, on a frame basis, image quality of the image information stored in the frame memory;an image output unit that reads the image information from the frame memory and outputs the image information to a display device;a controller that controls a function of the image quality converter based on a traveling state of the vehicle and changes a frame delay amount from when each of frames of the image information is received until when the frame is outputted from the image output unit; andan interpolation frame setting unit that sets an interpolation frame of the image information to be outputted in a transition period in which the controller changes the frame delay amount from a first frame delay amount to a second frame delay amount,wherein the image output unit outputs a frame of the image information having the second frame delay amount ...

IMAGE PLAYBACK DEVICE, DISPLAY DEVICE, AND TRANSMISSION DEVICE

The system includes a display device causing a display unit to display video; a data transmission unit that transmits, to the display device, video data generated in a predetermined format based on information decoded from encoded information, and interpolation data for interpolating differences between the predetermined format and a format when decoding from the encoded information; an interpolation data selection unit that selects a kind of interpolation data to be transmitted to the display device, on the basis of priorities for a plurality of kinds of the interpolation data capable of being generated based on the encoded information; and a display processing unit that acquires the video data and the selected kind of the interpolation data in the display device, and causes the display unit to display video resulting from interpolation of the video data based on the interpolation data. 1. A video playback device comprising:a display device causing a display unit to display video;a data transmission unit that transmits, to the display device, video data generated in a predetermined format based on information decoded from encoded information, and interpolation data for interpolating differences between the predetermined format and a format when decoding from the encoded information;an interpolation data selection unit that selects a kind of the interpolation data to be transmitted to the display device, on the basis of priorities for a plurality of kinds of interpolation data capable of being generated based on the encoded information; anda display processing unit that acquires the video data and the selected kind of the interpolation data in the display device, and causes the display unit to display video resulting from interpolation of the video data based on the interpolation data.2. The video playback device according to claim 1 ,comprising a transmission device including the data transmission unit,wherein: the transmission device includes an interpolation data ...

Electronic apparatus and control method thereof

Disclosed is an electronic apparatus. The electronic apparatus includes a memory configured to store a plurality of frames included in an input image and a processor configured to: identify whether one frame of the plurality of frames is a first interpolated frame generated based on at least two frames from remaining frames of the plurality of frames, and select a reference frame to be used in frame interpolation of the plurality of frames based on the first interpolated frame being identified.

Electronic apparatus and control method thereof

Disclosed is an electronic apparatus. The electronic apparatus includes a memory configured to store a plurality of frames included in an input image and a processor configured to: identify whether one frame of the plurality of frames is a first interpolated frame generated based on at least two frames from remaining frames of the plurality of frames, and select a reference frame to be used in frame interpolation of the plurality of frames based on the first interpolated frame being identified.

IMAGE ENLARGING APPARATUS, IMAGE ENLARGING METHOD, SURVEILLANCE CAMERA, PROGRAM AND RECORDING MEDIUM

In enlarging an image by a super-resolution process using learned data, a reference value obtained from each patch and the pixel values of peripheral pixels in the patch are compared to generate binary or ternary comparison codes, and a patch of a high-resolution component corresponding to a binary pattern code or a ternary pattern code generated from the comparison codes is read. When a high-frequency component is contained the binary pattern code may be used; otherwise the ternary pattern code may be used. It is possible to reduce the storage capacity of the coefficient data storage unit and to improve the sense of high resolution. 1: An image enlarging apparatus comprising:a linear interpolation unit for enlarging an input image by linear interpolation to generate an interpolated image;a high-resolution patch generating unit for performing high-resolution conversion on each of a plurality of patches respectively forming parts of the interpolated image, to generate a high-resolution patch;a pattern identification unit for identifying a pattern of a local region in the input image which corresponds to each patch in the interpolated image, to output a selection code;a coefficient data storage unit for storing a plurality of coefficient data respectively corresponding to a plurality of values which can be assumed by the selection code; anda coefficient data reading unit for reading a coefficient data corresponding to the selection code, from among the plurality of coefficient data stored in said coefficient data storage unit; whereinsaid high-resolution patch generating unit generates the high-resolution patch using the coefficient data read from said coefficient data storage unit; andsaid pattern identification unit comprises:a comparison code generating unit for using an average value of pixel values of pixels in the local region or the pixel value of the pixel positioned at a center of the local region as a reference value, comparing the pixel values of a ...

Image Processing Method And Apparatus, And Electronic Device

An image processing method is provided. The image sensor is controlled to output the merged image. The depth-of-field area is identified based on the merged image. The image sensor is controlled to output the color-block image. A first part of the color-block image within the depth-of-field area is converted into a first simulation image using a first interpolation algorithm. The second part of the color-block image outside the depth-of-field area is converted into a second simulation image using a second interpolation algorithm. The first simulation image and the second simulation image are merged to generate a simulation image corresponding to the color-block image.

SUPER-RESOLUTION OF DYNAMIC SCENES USING SAMPLING RATE DIVERSITY

Super-resolution of dynamic scenes using sampling rate diversity, processes and systems thereof are provided. The method implementing the processes includes: in a first stage, super-resolving secondary low-resolution (LR) images using a set of primary LR images to create LR dictionaries to represent polyphase components (PPCs) of high resolution (HR) patches of images; and, in a second stage, reverting to a single frame super-resolution (SR) applied to each frame which comprises an entire image, using the HR dictionaries extracted from the super-resolved sequence obtain in the first stage. 1. A method , comprising:in a first stage, super-resolving secondary low-resolution (LR) images using a set of primary LR images to create LR dictionaries to represent polyphase components (PPCs) of high resolution (HR) patches of images; andin a second stage, reverting to a single frame super-resolution (SR) applied to each frame which comprises an entire image, using the HR dictionaries extracted from the super-resolved sequence obtain in the first stage.2. The method of claim 1 , wherein the super-resolving of the secondary LR images comprise super-resolving downsampled versions of the secondary LR images into full PPCs of HR images of dynamic scenes.3. The method of claim 1 , wherein the second stage is a reiteration of a sparsity coding scheme claim 1 , using only one LR sequence and without involving the PPCs.4. The method of claim 3 , wherein the solving of the sparsity coding is based on a single-frame super-resolution (SFSR) problem for each frame of the primary LR image claim 3 , with local HR dictionaries that are extracted from the super-resolved sequence.5. The method of claim 1 , further comprising implementing Gaussian generative models to enforce sparsity in both the first stage and the second stage.6. The method of claim 1 , further comprising reducing estimation errors of the first stage by using anchors which are based on a relationship between the PPCs ...

SUPER-RESOLUTION OF DYNAMIC SCENES USING SAMPLING RATE DIVERSITY

Super-resolution of dynamic scenes using sampling rate diversity, processes and systems thereof are provided. The method implementing the processes includes: in a first stage, super-resolving secondary low-resolution (LR) images using a set of primary LR images to create LR dictionaries to represent polyphase components (PPCs) of high resolution (HR) patches of images; and, in a second stage, reverting to a single frame super-resolution (SR) applied to each frame which comprises an entire image, using the HR dictionaries extracted from the super-resolved sequence obtain in the first stage. 1. A computer system comprising:a CPU, a computer readable memory and a computer readable storage media;program instructions to super-resolve patches of secondary LR frames, in a first stage, into local areas within an entire HR image defined as patches;program instructions to create a dictionary to represent PPPCs of the local areas within the entire HR image, in the first stage; andprogram instructions to super-resolve primary LR frames into their HR counterparts, in a second stage, by super-resolving small patches with the secondary LR frames being discarded,wherein the program instructions are stored on the computer readable storage media for execution by the CPU via the computer readable memory.2. The computer system of claim 1 , wherein the program instructions further:super-resolve the patches of secondary LR frames with use of a dictionary whose atoms are extracted from the primary LR frames; andextract a patch of predetermined size from one of the patches of the secondary LR frames to super-resolve into a corresponding larger HR patch of images; andwork on smaller patches with more samples than in the patches of the secondary LR frames to estimate representation of only the HR patch of images.3. The computer system of claim 2 , wherein a primary set of LR frames of a same resolution level as that of PPPCs of the HR image is used to create a dictionary to represent the ...

IMAGING SYSTEM AND ELECTRONIC DEVICE

An imaging system that has an image processing function and is capable of generating an interpolation image is provided. The imaging system has an additional function such as image processing and can generate an interpolation image by using image data output from an imaging device. The imaging device can perform filter processing in parallel during a light exposure period, and thus can perform a large amount of arithmetic operation and generate a high-quality interpolation image. The number of arithmetic operations can be further increased particularly during image capturing in a dark place, which requires a long exposure time. Accordingly, the frame rate can be substantially increased, and high-quality moving image data can be generated. 1. An imaging system comprising:an imaging device, a first semiconductor device, a second semiconductor device, and a third semiconductor device,wherein the imaging device is configured to obtain first data and second data in each frame period,wherein the imaging device is configured to generate third data by filter processing of the first data and generate fourth data by filter processing of the second data,wherein the first semiconductor device is configured to generate fifth data by arithmetic operation using third data and fourth data that are obtained in an n-th frame, where n is a natural number,wherein the first semiconductor device is configured to generate sixth data by arithmetic operation using third data and fourth data that are obtained in an (n+1)th frame,wherein the second semiconductor device is configured to generate an interpolation image by using the fifth data and the sixth data, andwherein the third semiconductor device is configured to generate moving image data including first data obtained in the n-th frame, the interpolation image, and first data obtained in the (n+1)th frame in this order.2. The imaging system according to claim 1 ,wherein the third data is generated while the second data is obtained.3. An ...

CAMERA SYSTEM, VIDEO PROCESSING APPARATUS, AND CAMERA APPARATUS

Disclosed herein is a camera system including, a camera apparatus having, an image sensor, a correction section, a first transmission processing section, and a synchronization processing section, and a video processing apparatus having a second transmission processing section and a conversion section, wherein the video processing apparatus outputs the video data obtained by the conversion by the conversion section. 110-. (canceled)11. A video system comprising: an image sensor that includes pixels arranged in an array and that is configured to output an image signal having a pixel sequence corresponding to the array of the pixels, and', 'a first input/output section at the camera apparatus configured to output the image signal and communicate synchronous data used for synchronizing at least part of the camera apparatus;, 'a camera apparatus including'} a second input/output section at the video processing apparatus configured to communicate synchronous data with the camera apparatus; and', 'a cable, coupled to the camera apparatus and to the video processing apparatus, configured to transmit the image signal and synchronous data used for synchronizing at least part of the camera apparatus and the video processing apparatus;, 'a video processing apparatus including'} process the received image signal into a first video data having a pixel array specified by a first video format and at least substantially 4K horizontal resolution, and a second video data having a pixel array specified by a second video format and resolution less than the first video format, and', 'output the first video data and the second video data for displaying the image signal on a first display having at least substantially 4K horizontal resolution and on a second display having less resolution than the first display., 'a transmission processor configured to'}, 'wherein the video processing apparatus further includes12. A method for a video camera system comprising a camera apparatus having an ...

IMAGE SCALING

There is disclosed in one example a video processor, including: an input buffer to receive an input image; a slicer circuit to divide the input image into a plurality of N vertical slices; N parallel input buffers for de-rasterization; N parallel image scalers, wherein each scaler is hardware configured to scale in a raster form, one of the N vertical slices according to an image scaling algorithm; N parallel output buffers for rerasteriztion; and an output multiplexer to combine the scaled vertical slices into a combined scaled output image. 1. A video processor , comprising:an input buffer to receive an input image;a slicer circuit to divide the input image into a plurality of N vertical slices;N parallel image scalers, wherein each scaler is hardware configured to linewise scale one of the N vertical slices according to an image scaling algorithm; andan output multiplexer to combine the scaled vertical slices into a combined scaled output image.2. The video processor of claim 1 , further comprising logic and circuitry to receive an input video stream claim 1 , and to extract the input image from the input video stream.3. The video processor of claim 1 , wherein each vertical slice is substantially a quartile of the input image.4. The video processor of claim 1 , comprising logic and circuitry to receive an input video stream at a resolution selected from 480p claim 1 , 480i claim 1 , 720p claim 1 , 720i claim 1 , 1080p claim 1 , 1080i claim 1 , and 4K Ultra-High Definition (UHD) claim 1 , and to scale the input video stream to an output video stream at 8K UHD resolution via the N parallel image scalers.5. The video processor of claim 1 , comprising logic and circuitry to receive an input video stream at 8K UHD resolution claim 1 , and to downscale the image to a lower resolution via the N parallel image scalers.6. The video processor of claim 1 , wherein the image scaling algorithm includes a linear interpolation.7. The video processor of claim 1 , wherein the ...

APPARATUS AND METHODS FOR ARTIFACT DETECTION AND REMOVAL USING FRAME INTERPOLATION TECHNIQUES

Methods and apparatus for the generation of interpolated frames of video data. In one embodiment, the interpolated frames of video data are generated by obtaining two or more frames of video data from a video sequence; determining frame errors for the obtained two or more frames from the video sequence, determining whether the frame errors exceed a threshold value; performing a multi-pass operation; performing a single-pass operation; performing frame blending; performing edge correction; and generating the interpolated frame of image data. 17.-. (canceled)8. A computerized apparatus configured to enable generation of interpolated frames of video data , the computerized apparatus comprising:an imaging module;an optical flow module in operative communication with the imaging module;a frame blending module in operative communication with the optical flow module;an edge correction module in operative communication with the frame blending module;a multi-pass module in operative communication with the frame blending module; anda single-pass module in operative communication with the edge correction module.9. The computerized apparatus of claim 8 , wherein the multi-pass module further comprises an optical flow replacement module claim 8 , the optical flow replacement module configured to replace an optical flow value generated by the optical flow module for the generation of interpolated frames of video data.10. The computerized apparatus of claim 9 , wherein the multi-pass module further comprises a pixel intensity error module claim 9 , the pixel intensity error module being configured to calculate one or more estimated frames based at least on a forward and a backward optical flow generated by the optical flow module.11. The computerized apparatus of claim 10 , wherein the multi-pass module further comprises a segmentation module claim 10 , the segmentation module configured to reduce or eliminate artifacts in the generation of interpolated frames of video data by ...

IMAGE SCALING

There is disclosed in one example a video processor, including: an input buffer to receive an input image; a slicer circuit to divide the input image into a plurality of N vertical slices; N parallel input buffers for de-rasterization; N parallel image scalers, wherein each scaler is hardware configured to scale in a raster form, one of the N vertical slices according to an image scaling algorithm; N parallel output buffers for rerasteriztion; and an output multiplexer to combine the scaled vertical slices into a combined scaled output image. 1. A circuit , comprising:a scaler:to receive an input image;to divide the input image into N vertical slices;to scale up the N vertical slices; andto interpolate intermediate points between pixels for the input image to generate N individual upscaled slices associated with the input image.2. The circuit of claim 1 , wherein the N vertical slices are upscaled by providing at least three pixels from a previous slice to a next slice of the N vertical slices.3. The circuit of claim 1 , further comprising:a multiplexer to multiplex one or more scaled slices together such that they can be output as a single image.4. The circuit of claim 1 , wherein the scaler is configured to gather a plurality of lines for a particular output image to be provided to a display for 1/k second claim 1 , wherein the k is a frame rate per second.5. The circuit of claim 1 , wherein the input image is divided into four vertical slices by the circuit.6. The circuit of claim 1 , wherein the scaler is configured to operate in parallel with a plurality of individual per-slice scalers to scale up the N vertical slices and to interpolate intermediate points between selected pixels for one or more images.7. The circuit of claim 1 , wherein interpolation of the intermediate points includes linear interpolation between two points in a particular dimension.8. The circuit of claim 1 , wherein interpolation of the intermediate points includes polynomial interpolation ...

CAMERA SYSTEM, VIDEO PROCESSING APPARATUS, AND CAMERA APPARATUS

Disclosed herein is a camera system including, a camera apparatus having, an image sensor, a correction section, a first transmission processing section, and a synchronization processing section, and a video processing apparatus having a second transmission processing section and a conversion section, wherein the video processing apparatus outputs the video data obtained by the conversion by the conversion section. 111-. (canceled)12. A video system comprising: an image sensor that includes pixels arranged in a predetermined array and that is configured to output an image signal having a pixel sequence corresponding to the array of the pixels, the image signal having at least substantially 4K horizontal pixels per frame, and', 'a first input/output section at the camera apparatus configured to output the image signal and receive synchronous data for synchronizing operation of the image sensor;, 'a camera apparatus including'}a cable, coupled to the camera apparatus, configured to transmit the image signal; and a second input/output section at the video processing apparatus configured to output the synchronous data to the camera apparatus, and', process the received image signal into a first video data having a pixel array specified by a first video format and at least substantially 4K horizontal resolution, and a second video data having a pixel array specified by a second video format and resolution less than the first video format, and', 'output the first video data and the second video data for displaying, respectively, on a first display having at least substantially 4K horizontal resolution and on a second display having less resolution than the first display., 'processor apparatus configured to'}], 'a video processing apparatus coupled to the cable to receive the image signal and operable in synchronization with at least part of the camera apparatus, the video processing apparatus including'}13. The video system according to claim 12 ,wherein the processor ...

IMAGE PROCESSING APPARATUS AND IMAGE PROCESSING METHOD

For sharpening an input image by up-converting the input image in order to increase the number of pixels of an image and generating a frequency component higher than a frequency component contained in an input image signal representing the input image, the number of multipliers is reduced, thereby achieving significant downsizing of an apparatus and cost reduction. An image processing apparatus includes a path on a base image side for up-converting the input image signal and a path on a sharpening processing side for carrying out nonlinear arithmetic processing on the input image signal. The path on the sharpening processing side includes an up-converter at a subsequent stage of at least one filter, after which the nonlinear arithmetic processing is carried out. The at least one filter may be either a two-dimensional low pass filter for noise removal or a high pass filter for removing a DC component. 1. An image processing apparatus for generating an output image by up-converting an input image and sharpening an image , the image processing apparatus comprising:a path on a base image side for generating a first signal having an increased number of pixels by up-converting an input image signal representing the input image;a path on a sharpening processing side for generating a second signal for sharpening the input image by a sharpening processing unit having a nonlinear arithmetic unit configured to generate a frequency component higher than a frequency component contained in the input image signal representing the input image; andan adder configured to generate an output image signal representing the output image by combining the first signal and the second signal,at a subsequent stage of at least one filter in the path of the sharpening processing side, an up-converter is disposed, followed by the nonlinear arithmetic unit, whereinthe sharpening processing unit has at least one of:a first-configuration sharpening processing unit having: a filter unit configured to ...

VIDEO SIGNAL CONVERSION DEVICE, VIDEO SIGNAL CONVERSION METHOD, AND NON-TRANSITORY STORAGE MEDIUM

A video signal conversion device includes an RGB converter. The RGB converter converts gradation values of an input R signal, an input G signal, and an input B signal of three primary colors based on a conversion table or conversion formula to generate an output R signal, an output G signal, and an output B signal. The RGB converter, when it is designated, by a cataract degree designating signal that designates a degree of cataract including a degree of light scattering, that it is a cataract with light scattering, decreases the gradation values of the input R signal, the input G signal, and the input B signal, in a range from the minimum gradation value to a predetermined intermediate gradation value less than the maximum gradation value, with a linear characteristic of not converting gradation values as a reference. 1. A video signal conversion device comprising:an RGB converter configured to convert gradation values of an input R signal, an input G signal, and an input B signal of three primary colors based on a conversion table or a conversion formula to generate an output R signal, an output G signal, and an output B signal, whereinwhen it is designated, by a cataract degree designating signal that designates a degree of cataract including a degree of light scattering, that it is a cataract with light scattering,the RGB converter decreases the gradation values of the input R signal, the input G signal, and the input B signal, in a range from a minimum gradation value to a predetermined intermediate gradation value less than a maximum gradation value, with a linear characteristic of not converting gradation values of the output R signal, the output G signal, and the output B signal as a reference with respect to the gradation values of the input R signal, the input G signal, and the input B signal.2. The video signal conversion device according to claim 1 , whereinthe RGB converter increases a degree to which gradation values of the input R signal, the input G ...

SYSTEM AND METHOD FOR CREATING A VIDEO FRAME FROM A SINGLE VIDEO FIELD

A system and method of producing a frame of a video image from an interlaced field. In one embodiment, the method includes: (1) creating an equal-intensity trace from present samples in the field, (2) recognizing an equal-intensity path in the equal-intensity trace, (3) at least partially straightening the equal-intensity path and (4) using the equal-intensity path to determine an intensity value for a missing sample in the frame. 1. An integrated circuit operable to produce a frame from a field by:creating an equal-intensity trace from present samples in said field;recognizing an equal-intensity path in said equal-intensity trace;at least partially straightening said equal-intensity path; andusing said equal-intensity path to determine an intensity value for a missing sample in said frame.2. The integrated circuit as recited in claim 1 , wherein said using comprises interpolating between closest ones of present samples and said equal-intensity path to said missing sample.3. The integrated circuit as recited in claim 1 , wherein said recognizing is carried out based on a likelihood of reflecting true image features.4. The integrated circuit as recited in claim 1 , wherein said recognizing comprises selecting said equal-intensity path based on a direction of an extending trace of said equal-intensity path.5. The integrated circuit as recited in claim 1 , wherein said recognizing comprises selecting said equal-intensity trace based on a compatibility of intensity profiles at beginning point and end points of said equal-intensity path.6. The integrated circuit as recited in claim 1 , wherein said recognizing comprises bridging said equal-intensity path with another equal-intensity path in another equal-intensity trace.7. The integrated circuit as recited in claim 1 , wherein said creating comprises:linearly interpolating between present samples to locate equal-intensity points;drawing equal-intensity lines between said equal-intensity points; andconnecting said equal- ...

Generating synthetic video frames using optical flow

A novel method of using optical flow algorithm that maximizes the benefit of optical flow synthetic frames while minimizing the associated computation cost is provided. When using optical flow to produce synthetic frames between two actual/recorded frames, the method computes a set of estimates of optical flows (or a flow estimate) between the two frames. These flow estimates are then used to compute all synthetic frames that are needed between the two actual frames by interpolation, which creates each synthetic frame based on its temporal distances from the pair of actual frames.

Image pickup apparatus

An image pickup apparatus is equipped with a distance information calculator, a high frequency signal extractor, a focus assist signal generator, and a signal synthesizer. The distance information calculator calculates distance information of a video signal and generates an in-focus range signal from current focus information and the distance information. The high frequency signal extractor extracts a high frequency signal of the video signal. The focus assist signal generator generates a focus assist signal representing a focused region by using the high frequency signal and the in-focus range signal. The signal synthesizer synthesizes the focus assist signal with the video signal to generate a focus-assist-signal-added video signal.

Camera system, video processing apparatus, and camera apparatus

Disclosed herein is a camera system including, a camera apparatus having, an image sensor, a correction section, a first transmission processing section, and a synchronization processing section, and a video processing apparatus having a second transmission processing section and a conversion section, wherein the video processing apparatus outputs the video data obtained by the conversion by the conversion section.

DIRECTED INTERPOLATION AND DATA POST-PROCESSING

An encoding device evaluates a plurality of processing and/or post-processing algorithms and/or methods to be applied to a video stream, and signals a selected method, algorithm, class or category of methods/algorithms either in an encoded bitstream or as side information related to the encoded bitstream. A decoding device or post-processor utilizes the signaled algorithm or selects an algorithm/method based on the signaled method or algorithm. The selection is based, for example, on availability of the algorithm/method at the decoder/post-processor and/or cost of implementation. The video stream may comprise, for example, downsampled multiplexed stereoscopic images and the selected algorithm may include any of upconversion and/or error correction techniques that contribute to a restoration of the downsampled images. 1receiving, at a decoder, the video bitstream comprising at least one region comprising two images;receiving, by the decoder, metadata from the video bitstream indicating a width and height of an image of the two images;receiving first recommended information in the video bitstream identifying a first post-decoding process to be applied to the at least one region, the first post-decoding process being a spatial process;receiving second recommended information in the video bitstream identifying second post-decoding process to be applied to the at least one region,disregarding, by the decoder, the first recommended information without applying the first post-decoding process to the at least one region, andapplying the second post-decoding process identified by the second recommended information to the at least one region.. A method for decoding a video bitstream, the method comprising: This application is a continuation of U.S. patent application Ser. No. 16/261,196, filed on Jan. 29, 2019, which is a continuation of U.S. patent application Ser. No. 15/678,982, filed on Aug. 16, 2017, (now U.S. Pat. No. 10,194,172), which is a continuation of U.S. patent ...

TRANSFER OF VIDEO SIGNALS USING VARIABLE SEGMENTED LOOKUP TABLES

The disclosure is directed to transforming signals from one signal format to another signal format. For example, the format of a digital signal can change from storing video information in 12 bits of data to storing the video information in 32 bits of data. Other storage values and combinations can also be used. Since the number of bits available to store a portion of the video information can change when changing formats, a process is needed to translate or transform the video information appropriately. A transfer function utilizing a lookup table is used for the transforming. The lookup table utilizes a variable step size segmentation scheme that decreases the amount of lookup table storage space required and also decreases the number of estimation errors, i.e., interpolation errors. Estimation errors can occur when looking up a value not stored in the lookup table, and using neighboring values that are stored to estimate the value requested. In some applications, the logstep size or total size values can be stored in the lookup table to further reduce the amount of storage space required. A video parameter, such as the type of video content and the display room ambiance, can also be used to select the balance between further decreasing the size of the lookup table and further decreasing the estimation errors. 1. A method to adjust a video input in a processor , comprising:receiving a video input; andadjusting said video input, utilizing a transfer function employing a segmented lookup table (LUT), wherein said segmented LUT utilizes a variable segmentation step size.2. The method as recited in claim 1 , wherein said transfer function is one of a high dynamic range (HDR) electro-optical transfer function (EOTF) claim 1 , a HDR optical-electro transfer function (OETF) claim 1 , electrical to electrical transfer function (EETF) claim 1 , optical to optical transfer function (OOTF) claim 1 , or inverse EOTF.3. The method as recited in claim 1 , wherein said transfer ...

OPTICAL RECOGNITION SYSTEM FOR USE IN COMPUTER VISUAL PROCESSING

An optical recognition system includes a 4×4 kernel image sensor, two line buffers, and an interpolation unit. The 4×4 kernel image sensor includes two red pixels, eight green pixels, two blue pixels, and four IR pixels arranged in Bayer pattern. The two line buffers are configured to store the brightness information of the pixels. The interpolation unit is configured to provide missing components in each pixel according to the brightness information stored in the two line buffers, thereby outputting an image data which includes full-color brightness information associated with each pixel. 1. An optical recognition system for use in computer visual processing , comprising:an image capturing device comprising a first 4×4 kernel image sensor which includes a first red pixel, a second red pixel, a first through an eighth green pixels, a first blue pixel, a second blue pixel, and a first through a fourth infrared (IR) pixels forming a first through a fourth scan lines adjacent to each other;a buffer unit configured to store brightness information of at least two scan lines among the first through the fourth scan lines; andan interpolation unit configured to provide missing components in each pixel according to the brightness information stored in the buffer unit, thereby outputting an image data which includes full-color brightness information associated with each pixel.2. The optical recognition system of claim 1 , wherein:the first scan line sequentially includes the first green pixel, the first red pixel, the second green pixel and the first blue pixel;the second scan line sequentially includes the first IR pixel, the third blue pixel, the second IR pixel and the fourth green pixel;the third scan line sequentially includes the fifth green pixel, the second blue pixel, the sixth green pixel and the second red pixel; andthe fourth scan line sequentially includes the third IR pixel, the seventh green pixel, the fourth IR pixel, and the eighth green pixel.3. The optical ...

DETACHABLE-HEAD-TYPE CAMERA AND WORK MACHINE

The present invention provides a detachable-head-type camera which, when a camera head unit is exchanged, can perform correction processing with a unique value corresponding to a camera head unit after the exchange, and provides a work machine including the detachable-head-type camera. Camera head unit of detachable-head-type camera is detachably connected to image data generation section via dedicated cable. In non-volatile memory of camera head unit, unique value corresponding to the characteristics unique to at least one of imaging element or lens is stored. Unique value is used for correction processing of image data performed by at least one of image data generation section or image processing unit. 16.-. (canceled)7. A head separation-type camera comprising:a camera head unit including an imaging element, a lens configured to cause light from outside to form an image on the imaging element, and a first storage device configured to store a unique value corresponding to characteristics of at least one of the imaging element or the lens;a connection member, being connected to the camera head unit, which is configured to transmit pixel data that is photoelectrically converted by the imaging element; andan image data generation section, being detachably connected to the camera head unit via the connection member, which is configured to acquire the unique value from the first storage device, configured to generate image data to be subjected to the image processing in an image processing unit from the pixel data input from the imaging element via the connection member, the image processing unit being connected to the image data generation section via a camera cable to perform image processing, and configured to output the image data to the image processing unit via the camera cable, whereinthe unique value is used for correction processing on the image data performed in at least one of the image data generation section or the image processing unit.8. The detachable- ...

Image processing apparatus and recording medium

An image processing apparatus includes: a signal receiver configured to receive an input image; an image processor configured to process the input image and generate an output image; a storage configured to store a first patch corresponding to a first pixel of the input image; and a controller configured to control the image processor to generate the output image by applying the first patch stored in the storage to the first pixel.

IMAGE SENSING DEVICE

An image sensing device includes: a pixel array including a plurality of pixels arranged at each cross point of rows and columns, wherein the pixel array comprises a plurality of pixel blocks, each including N pixels, N being a natural number equal to or greater than 2, wherein the pixel blocks sequentially output a plurality of pixel signals having pixel information on the same color N times during one or more single row times; a plurality of column lines suitable for sequentially transferring the plurality of pixel signals from the pixel blocks, each column line being shared by two adjacent columns and coupled to at least one of the pixel blocks; a plurality of averaging blocks suitable for grouping the pixel signals to overlap each other, into a plurality of pixel signal groups, and averaging the pixel signal groups to output a plurality of averaged pixel signals, wherein the number of the averaging blocks is smaller than the number of the column lines; and a plurality of conversion blocks suitable for converting the averaged pixel signals into a plurality of digital signals.

IMAGE PROCESSING SYSTEM

The present invention provides an image processing system includes a first image processing device and a second image processing device. The second image processing device includes: a combining unit that generates combined image data by combining captured image data input via a first input terminal and assistant image data input via a second input terminal; and a converting unit that generates image data of a first resolution to be output to a third output terminal and image data of a second resolution to be output to a fourth output terminal by converting a resolution of the combined image data generated by the combining unit in accordance with a display resolution of a first display device and a display resolution of a second display device. 1. An image processing system , comprising:a first image processing device including a first output terminal that outputs captured image data obtained through image capture, and a second output terminal that outputs assistant image data to be combined with an image based on the captured image data; anda second image processing device including a first input terminal connected to the first output terminal, a second input terminal connected to the second output terminal, a third output terminal connectable to a first display device, and a fourth output terminal connectable to a second display device,wherein the second image processing device further includesa combining unit that generates combined image data by combining the captured image data input via the first input terminal and the assistant image data input via the second input terminal, anda converting unit that generates image data of a first resolution to be output to the third output terminal and image data of a second resolution to be output to the fourth output terminal by converting a resolution of the combined image data generated by the combining unit in accordance with a display resolution of the first display device and a display resolution of the second display ...

DIRECTED INTERPOLATION AND DATA POST-PROCESSING

An encoding device evaluates a plurality of processing and/or post-processing algorithms and/or methods to be applied to a video stream, and signals a selected method, algorithm, class or category of methods/algorithms either in an encoded bitstream or as side information related to the encoded bitstream. A decoding device or post-processor utilizes the signaled algorithm or selects an algorithm/method based on the signaled method or algorithm. The selection is based, for example, on availability of the algorithm/method at the decoder/post-processor and/or cost of implementation. The video stream may comprise, for example, downsampled multiplexed stereoscopic images and the selected algorithm may include any of upconversion and/or error correction techniques that contribute to a restoration of the downsampled images. 1. A method for decoding a video bitstream , the method comprising:receiving, at a decoder, the video bitstream comprising at least one region comprising two images;receiving, by the decoder, metadata from the video bitstream indicating a width and height of an image of the two images;receiving first recommended information in the video bitstream identifying a first post-decoding process to be applied to the at least one region, the first post-decoding process being a spatial process;receiving second recommended information in the video bitstream identifying second post-decoding process to be applied to the at least one region,disregarding, by the decoder, the first recommended information without applying the first post-decoding process to the at least one region, andapplying the second post-decoding process identified by the second recommended information to the at least one region;wherein the video bitstream further comprises a second region different from the at least one region, andwherein the second post-decoding process is not applied to the second region.2. A method for post-decoding processing of a video bitstream , the method comprising: ...

DATA INTERPOLTION

When a picture displayed on a client device is enlarged, the client device may be configured to insert new pixels between two adjacent pixels in the picture. When actual values of the new pixels are stored on a server, the client device may submit a request to the server for actual values of the new pixels. Responsive to the request, the server may first calculate interpolation values in accordance with the same interpolation algorithm and then calculate a difference value based on the interpolation values and the actual values stored on the server. If the calculated difference value is greater than a threshold value, the server may transmit the actual values for the new pixels to the client device. Otherwise, the server may instruct the client device to calculate the interpolation values. 1. A method for conditional buffering , comprising:calculating an interpolation value for a pixel to be inserted between two adjacent pixels that are displayed at a client device;calculating a difference value between the interpolation value and a pixel value that is stored on a server;transmitting the pixel value to the client device, responsive to determination that the calculated difference value is greater than a threshold value; andinstructing the client device to calculate the interpolation value for the pixel to be inserted between the two adjacent pixels, responsive to determination that the calculated difference value is less than the threshold value.2. The method of claim 1 , further comprising determining the threshold value based on factors that include network bandwidth between the client device and the server claim 1 , a graphic processing capability of the client device claim 1 , or memory size of the client device.3. The method of claim 1 , wherein the calculating the difference value includes:subtracting the interpolation value from the pixel value; andcalculating a square value for a result of the subtracting as the difference value.4. The method of claim 1 , ...

DEVICE AND METHOD FOR PROCESSING FRAMES

Embodiments disclosed herein relate to device and method for processing frames. For example, a buffer of a device is arranged to store a plurality of rendered frames rendered at a frame rendering rate and a time stamp for each of rendered frames. A compositor of a device is arranged to obtain a timestamp of a synchronisation signal for synchronising the display of frames with a display refresh rate. In response to obtaining a timestamp of a synchronisation signal, a compositor is arranged to trigger access to a buffer to obtain two rendered frames having timestamps closest to a timestamp of a synchronisation signal. An interpolator of a device is arranged to generate an interpolated rendered frame for display by performing an interpolation operation using two rendered frames. An interpolation operation takes into account the difference between timestamps of each of two rendered frames and a timestamp of a synchronisation signal. 1. A method of processing frames to display , the method comprising:storing a plurality of first frames having timestamps, the first frames being obtained at a first rate;identifying a timestamp of a synchronisation signal to display at a second rate;identifying two first frames among the first frames based on the timestamp of the synchronisation signal, the two first frames having timestamps closest to the timestamp of the synchronisation signal; andgenerating a second frame to display using the two first frames,wherein a timestamp for each of the first frames is delayed by a predetermined delay value or the predetermined delay value is subtracted from the timestamp of the synchronisation signal, for identifying the two first frames.2. The method of claim 1 , wherein one of the two first frames has a timestamp before the timestamp of the synchronisation signal claim 1 , and the other of the two first frames has a timestamp after the timestamp of the synchronisation signal.3. The method of claim 1 , wherein the second frame is an ...

FRAME RATE CONVERSION METADATA

Methods for encoding and decoding high-dynamic range signals are presented. The signals are encoded in a high frame rate and are accompanied by frame-rate conversion metadata defining a preferred set of frame-rate down-conversion parameters, which are determined according to the maximum luminance of a target display, display playback priority modes, or judder control modes. A decoder uses the frame-rate conversion metadata to apply frame-rate down-conversion to the input high-frame-rate signal according to at least the maximum luminance of the target display and/or the characteristics of the signal itself. Frame-based and pixel-based frame-rate conversions, and judder models for judder control via metadata are also discussed. 1. A method to encode a high-dynamic range (HDR) video signal , the method comprising:accessing an HDR video signal encoded at a first frame rate; 'wherein the set of frame-rate down-conversion parameters comprises: (i) a down-conversion factor for determining, at a target display, the second frame rate based at least on a function of maximum brightness of the target display, where the second frame rate increases with the maximum brightness; or (ii) metadata from which the down-conversion factor can be obtained;', 'determining a set of frame-rate down-conversion parameters suitable for adapting the HDR video signal for playback at a second frame rate, the second frame rate being lower than the first frame rate,'}generating frame-rate-conversion metadata based on the set of frame-rate down-conversion parameters; andgenerating a coded bitstream comprising the HDR video signal and the frame-rate-conversion metadata.2. The method of claim 1 , wherein the set of frame-rate down-conversion parameters comprises coefficients for a down-conversion filter claim 1 , the down-conversion filter being suitable for adapting the HDR video signal for playback claim 1 , at the target display claim 1 , at the second frame rate.3. The method of claim 1 , wherein ...

COLOR CORRECTION WITH A LOOKUP TABLE

Color correction in high dynamic range video (HDR) using 2D look-up table (LUT) may be provided. The color correction may be applied in a decoder after decoding the HDR video signal. For example, the color correction may be applied before, during, or after chroma upsampling of the HDR video signal. The 2D LUT may include a representation of the color space of the HDR video signal. The color correction may include applying triangle interpolation to the sample values of the color component of the color space. The 2D LUT may be estimated by an encoder and signaled to the decoder. The encoder may decide to reuse a prior-signaled 2D LUT or use a new 2D LUT. 1. A method for processing video content , the method comprising:receiving a first luma sample, a first chroma sample, and a two-dimensional (2D) look-up table (LUT) for producing corrected chroma values, wherein the 2D LUT defines a luma dimension and a chroma dimension associated with a 2D color space of the video content;determining an input luma value and an input chroma value to the 2D LUT based on at least one of the first luma sample or the first chroma sample, wherein the input luma value and the input chroma value are aligned to a same sampling location;producing an output chroma value based on the 2D LUT, the input chroma value and the input luma value; andreconstructing the video content using at least the output chroma value.2. The method of claim 1 , wherein the 2D color space of the video content is defined by a plurality of rectangular units with respective vertices claim 1 , and wherein the 2D LUT comprises chroma component values associated with the respective vertices.3. The method of claim 2 , wherein the plurality of rectangular units of the 2D color space are derived using quadtree partitioning.4. The method of claim 2 , wherein the producing of the output chroma value comprises:determining a first rectangular unit among the plurality of rectangular units to which the input luma value and the ...

VIDEO FRAME INTERPOLATION USING A CONVOLUTIONAL NEURAL NETWORK

According to one implementation, a video processing system includes a computing platform having a hardware processor and a system memory storing a frame interpolation software code, the frame interpolation software code including a convolutional neural network (CNN) trained using a loss function having an image loss term summed with a phase loss term. The hardware processor executes the frame interpolation software code to receive first and second consecutive video frames including respective first and second images, and to decompose the first and second images to produce respective first and second image decompositions. The hardware processor further executes the frame interpolation software code to use the CNN to determine an intermediate image decomposition corresponding to an interpolated video frame for insertion between the first and second video frames based on the first and second image decompositions, and to synthesize the interpolated video frame based on the intermediate image decomposition. 1. A video processing system comprising:a computing platform including a display, a hardware processor, and a system memory;a frame interpolation software code stored in the system memory, the frame interpolation software code including a convolutional neural network (CNN) trained using a loss function having an image loss term summed with a phase loss term, the CNN having a plurality of convolutional processing blocks including a first subset of the plurality of convolutional processing blocks trained independently of a second subset of the plurality of convolutional processing blocks; receive a first video frame including a first image and a second video frame including a second image, the first and second video frames being consecutive;', 'decompose the first and second images to produce respective first and second image decompositions;', 'use the CNN to determine an intermediate image decomposition based on the first and second image decompositions, the ...

Method for Processing Video Frames, Video Processing Chip, and Motion Estimation/Motion Compensation MEMC Chip

A method for processing video frames, a video processing chip, and a Motion Estimation/Motion Compensation (MEMC) chip are provided. The method performed by the video processing chip includes obtaining multiple video frames and adjusting each video frame from a first resolution to a second resolution. The method also includes inserting at least one invalid frame into the multiple video frames according to a second frame rate, so that a frame rate of a transport frame stream is the second frame rate; and sending the transport frame stream to an MEMC chip. The video processing chip and the MEMC chip may perform transmission of a frame stream according to an interface frequency corresponding to a resolution and a frame rate that are agreed upon. 1. A method comprising:obtaining, by a video processing chip, multiple video frames, wherein a frame rate of the multiple video frames is a first frame rate, wherein a resolution of the multiple video frames is a first resolution, and wherein the first resolution is an original resolution of the multiple video frames;adjusting, by the video processing chip, the multiple video frames from the first resolution to a second resolution, wherein the second resolution is a resolution agreed upon in advance by the video processing chip and a Motion Estimation/Motion Compensation (MEMC) chip, and wherein the second resolution is higher than the first resolution;inserting, by the video processing chip according to a second frame rate, at least one invalid frame into the multiple video frames, so a frame rate of a transport frame stream including the multiple video frames and the at least one invalid frame is the second frame rate; andsending the transport frame stream to the MEMC chip, and wherein a resolution of the at least one invalid frame is the second resolution.2. The method according to claim 1 , wherein the method further comprises:sending, by the video processing chip, agreement information to the MEMC chip, wherein the ...

Graphics display system with unified memory architecture

A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.

VIDEO FRAME INTERPOLATION METHOD, STORAGE MEDIUM AND TERMINAL

The present application provides a video frame interpolation method. The method includes the steps of: 1) successively determining a current frame, a frame prior to the current frame and a frame after the current frame of a video to which a frame to be interpolated; 2) inputting the current frame, the frame prior to the current frame and the frame after the current frame of the video to which the frames to be interpolated into a pre-configured video frame interpolation model, wherein the video frame interpolation model is configured by training a pre-set convolutional neural network model with current frames, frames prior to the current frames and frames after the current frames in a training set; and 3) performing frame interpolation on the video to which the frames to be interpolated via the video frame interpolation model, and obtaining frame interpolated video. 1. A video frame interpolation method , comprising the steps of:successively determining a current frame, a frame prior to the current frame and a frame after the current frame of a video to which a frame to be interpolated;inputting the current frame, the frame prior to the current frame and the frame after the current frame of the video to which the frames to be interpolated into a pre-configured video frame interpolation model, wherein the video frame interpolation model is configured by training a pre-set convolutional neural network model with current frames, frames prior to the current frames and frames after the current frames in a training set; andperforming frame interpolation on the video to which the frames to be interpolated via the video frame interpolation model, and obtaining a frame interpolated video.2. The video frame interpolation method according to claim 1 , wherein the pre-set convolutional neural network model comprises a first convolutional layer claim 1 , a second convolutional layer and a third convolutional layer claim 1 , the first convolutional layer and the second ...

Methods, apparatuses and computer programs for adapting content

In one aspect of the disclosure, there is provided a method comprising causing, at least in part, actions that result in: generating, for primary content to be broadcasted for output on a primary content output device, rendering adaptation information configured for use in adapting the rendering of the primary content on a secondary content output device thereby providing an output of secondary content which is derived from the broadcasted primary content; wherein the primary content comprises at least a first media portion having a first temporal output characteristic; wherein the rendering adaptation information comprises temporal information configured for use in adjusting the rendering of the at least first media portion so as to enable generation of secondary content comprising at least a second media portion having a second temporal output characteristic that can differ from the first temporal output characteristic of the at least first media portion.

METHOD AND SYSTEM FOR ANALYZING AUDIO, VIDEO, AND AUDIO-VIDEO MEDIA DATA STREAMS

A method and system for comparing video and audio information at first and second spaced-apart locations on a content distribution network. Network probes are located on the network and extract a respective first and second plurality of video frames and audio segments. Two fingerprints sequences are determined from each one of the frames and segments, then the sequences are matched and time-aligned. A beginning of a matched segment is determined and the individual fingerprints within each of the fingerprint sequences are compared from the beginning of the matched segment. Fingerprints that are determined to be different during the comparison process indicate a change in video or audio content between the two probes. 1. A method for comparing video information at first and second spaced-apart locations on a video transport network , the method comprising:at a first and second network probe located at the respective first and second spaced-apart locations, extracting a respective first and second plurality of video frames from the network;calculating a first and a second fingerprints sequence from each one of the respective first and second plurality video frames;matching and time-aligning a first block of the first fingerprints sequence and a second block of the second fingerprints sequence; andstarting with a first matched and time-aligned fingerprints sequence and a second matched and time-aligned fingerprints sequence determining a beginning of a matched segment of fingerprints.2. The method of further comprising determining an end of the matched segment of fingerprints.3. The method of wherein the end of the matched segment indicates the occurrence of a technical problem between the first and second locations or a change in video content between the first and second locations.4. The method of wherein the step of determining the beginning of the matched segment further comprises issuing a fingerprints matched alert and the step of determining the end of the ...

CAMERA SYSTEM, VIDEO PROCESSING APPARATUS, AND CAMERA APPARATUS

Disclosed herein is a camera system including, a camera apparatus having, an image sensor, a correction section, a first transmission processing section, and a synchronization processing section, and a video processing apparatus having a second transmission processing section and a conversion section, wherein the video processing apparatus outputs the video data obtained by the conversion by the conversion section. 110-. (canceled)11. A video system comprising: an image sensor that includes pixels arranged in an array and that is configured to output an image signal having a pixel sequence corresponding to the array of the pixels, and', 'a first input/output section at the camera apparatus configured to output the image signal and communicate synchronous data used for synchronizing at least part of the camera apparatus;, 'a camera apparatus including'} a second input/output section at the video processing apparatus configured to communicate synchronous data with the camera apparatus; and', 'a cable, coupled to the camera apparatus and to the video processing apparatus, configured to transmit the image signal and synchronous data used for synchronizing at least part of the camera apparatus and the video processing apparatus;, 'a video processing apparatus including'} process the received image signal into a first video data having a pixel array specified by a first video format and at least substantially 4K horizontal resolution, and a second video data having a pixel array specified by a second video format and resolution less than the first video format, and', 'output the first video data and the second video data for displaying the image signal on a first display having at least substantially 4K horizontal resolution and on a second display having less resolution than the first display., 'a transmission processor configured to'}, 'wherein the video processing apparatus further includes12. The video system according to claim 11 , wherein the transmission processor ...

Directed interpolation and data post-processing

An encoding device evaluates a plurality of processing and/or post-processing algorithms and/or methods to be applied to a video stream, and signals a selected method, algorithm, class or category of methods/algorithms either in an encoded bitstream or as side information related to the encoded bitstream. A decoding device or post-processor utilizes the signaled algorithm or selects an algorithm/method based on the signaled method or algorithm. The selection is based, for example, on availability of the algorithm/method at the decoder/post-processor and/or cost of implementation. The video stream may comprise, for example, downsampled multiplexed stereoscopic images and the selected algorithm may include any of upconversion and/or error correction techniques that contribute to a restoration of the downsampled images.

SYSTEM AND METHOD FOR LEARNING HUMAN ACTIVITIES FROM VIDEO DEMONSTRATIONS USING VIDEO AUGMENTATION

A system and method for learning human activities from video demonstrations using video augmentation is disclosed. The method includes receiving original videos from one or more data sources. The method includes processing the received original videos using one or more video augmentation techniques to generate a set of augmented videos. Further, the method includes generating a set of training videos by combining the received original videos with the generated set of augmented videos. Also, the method includes generating a deep learning model for the received original videos based on the generated set of training videos. Further, the method includes learning the one or more human activities performed in the received original videos by deploying the generated deep learning model. The method includes outputting the learnt one or more human activities performed in the original videos. 1. A system for learning human activities from video demonstrations using video augmentation , the system comprising:one or more hardware processors; anda memory coupled to the one or more hardware processors, wherein the memory comprises a plurality of subsystems in the form of programmable instructions executable by the one or more hardware processors, wherein the plurality of subsystem comprises:a receiver subsystem configured for receiving one or more original videos from one or more data sources, wherein the one or more original videos comprises one or more human activities;a video augmentation subsystem configured for processing the received one or more original videos using one or more video augmentation techniques to generate a set of augmented videos;a training video generator subsystem configured for generating a set of training videos by combining the received one or more original videos with the generated set of augmented videos;a deep learning model generator subsystem configured for generating a deep learning model for the received one or more original videos based on the ...

定向内插和数据后处理

本申请涉及一种定向内插和数据后处理。其中，一种用于处理从编码视频中解码的视频流的区域的方法包括以下步骤：接收表示要应用于解码之后的视频流的所述区域的后处理技术的信号，其中，基于应用于所述区域的后处理技术的相关性能，在对视频进行编码之前、在对视频进行编码期间、或在对视频进行编码之后，在解码之前选择后处理技术，其中，所接收的信号包括所选择的后处理技术的标识符，以及其中，标识符被打包为编码视频和编码视频的辅助信息中的至少一个；将所选择的后处理技术应用于解码的视频流的所述区域；其中，如果所述区域不是预定的，则所接收的信号包括关于所述区域的特性的信息。

定向内插和数据后处理

本申请涉及一种定向内插和数据后处理。其中，一种用于处理从编码视频中解码的视频流的区域的方法包括以下步骤：接收表示要应用于解码之后的视频流的所述区域的后处理技术的信号，其中，基于应用于所述区域的后处理技术的相关性能，在对视频进行编码之前、在对视频进行编码期间、或在对视频进行编码之后，在解码之前选择后处理技术，其中，所接收的信号包括所选择的后处理技术的标识符，以及其中，标识符被打包为编码视频和编码视频的辅助信息中的至少一个；将所选择的后处理技术应用于解码的视频流的所述区域；其中，如果所述区域不是预定的，则所接收的信号包括关于所述区域的特性的信息。

Video and graphics system with MPEG specific data transfer commands

A video and graphics system includes a video decoding system for processing compressed video data. The compressed video data includes MPEG-2 video data containing SDTV video data or HDTV video data. The video decoding system includes a video decoder for processing the compressed video data to generate displayable video, and a memory controller for transferring the compressed video data to and from an external memory. The video decoder requests to the memory controller to transfer the compressed video data using one of predetermined addressing patterns. The predetermined addressing patterns allow for more efficient transferring of the compressed video data to and from the external memory when compared to sequentially transferring a fixed number of data bytes starting at a fixed address. The use of the predetermined addressing patterns results in reading the compressed video data from the external memory in a predetermined order in a less number of clock cycles. The use of the predetermined addressing patterns also results in transferring the compressed video data over the data bus between the memory controller and the video decoder in a less number of clock cycles.

Graphics display system with window descriptors

A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip uses window descriptors to describe logical surfaces, or windows, of graphics information to be displayed on the screen. The chip incorporates a unified memory architecture that provides a high level of system performance while conserving memory bandwidth and chip size. Video and graphics scaling capabilities as well as anti-flutter filtering capability are provided.

Video and graphics system with video scaling

A video and graphics system has a reduced memory mode in which video images are reduced in half in horizontal direction during decoding. The video and graphics system includes a video decoder for decoding MPEG-2 video data. The video images may not be downscaled in the horizontal direction when no bi-directionally predicted pictures are used. The video and graphics system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format. The output having an SDTV format may be recorded using a video cassette recorder (VCR) while the HDTV video is being displayed.

Video and graphics system with a single-port RAM

A video and graphics system has an input for receiving compressed video data and an input for receiving graphics data. The compressed video data may include HDTV video and/or SDTV video, and may be included in compressed data streams such as an MPEG-2 Transport stream. The video and graphics system also includes a video decoder for processing the compressed video data to generate a video for displaying, a display engine for processing the graphics data to generate graphics for displaying, and an overlaying system for compositing the video and the graphics to generate an output video. The display engine includes a memory used during conversion of a graphics format from a first format to a second format to be in a format compatible with a video format The memory may be implemented in a single-port SRAM configured to simulate a dual-port SRAM. The system may be integrated on an integrated circuit chip.

Video, audio and graphics decode, composite and display system

A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I/O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format.

Video and graphics system with parallel processing of graphics windows

A display engine of a video and graphics system includes one or more processing elements and receives graphics from a memory. The graphics data define multiple graphics layers, and the processing elements process two or more graphics layers in parallel to generate blended graphics. Alpha values may be used while blending graphics. The processing elements may be integrated on an integrated circuit chip with an input for receiving the graphics data and other video and graphics components. The display engine may also include a graphics controller for receiving two or more graphics layers in parallel, for arranging the graphics layers in an order suitable for parallel processing, and for providing the arranged graphics layers to the processing elements. The blended graphics may be blended with HDTV video or SDTV video, which may be extracted from compressed data streams such as an MPEG Transport stream.

Video and graphics system with a video transport processor

A video and graphics system includes a data transport processor for receiving compressed data streams, a video transport processor for extracting video data, and an audio decode processor for extracting audio data. The data transport processor provides PCRs to the video transport processor and the audio decode processor. The video transport-processor stores the video data in external memory and generates a start code table to index the video data stored the external memory. In the start code table SLICEs of the video data are aligned to a suitable boundary. The compressed data streams may include MPEG Transport streams, and the video data may include SDTV or HDTV data. The video and graphics system may be implemented on an integrated circuit chip.

Video and graphics system with an MPEG video decoder for concurrent multi-row decoding

A video and graphics system processes video data including both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The video and graphics system includes a video decoder, which is capable of concurrently decoding multiple SLICEs of MPEG-2 video data. The video decoder includes multiple row decoding engines for decoding the MPEG-2 video data. Each row decoding engine concurrently decodes two or more rows of the MPEG-2 video data. The row decoding engines have a pipelined architecture for concurrently decoding multiple rows of MPEG-2 video data. The video decoder may be integrated on an integrated circuit chip with other video and graphics system components such as transport processors for receiving one or more compressed data streams and for extracting video data, and a video compositor for blending processed video data with graphics.

Apparatus and method for blending graphics and video surfaces

A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip blends graphics and video information by various graphics windows using alpha values for the windows, alpha values per pixel, or both. The chip calculates a composite alpha value based on the window's alpha values and the alpha values per pixel. Blended graphics and video may then be composited using the composite alpha value.

Video and graphics system with a single-port RAM

A video and graphics system has an input for receiving compressed video data and an input for receiving graphics data. The compressed video data may include HDTV video and/or SDTV video, and may be included in compressed data streams such as an MPEG-2 Transport stream. The video and graphics system also includes a video decoder for processing the compressed video data to generate a video for displaying, a display engine for processing the graphics data to generate graphics for displaying, and an overlaying system for compositing the video and the graphics to generate an output video. The display engine includes a memory used during conversion of a graphics format from a first format to a second format to be in a format compatible with a video format The memory may be implemented in a single-port SRAM configured to simulate a dual-port SRAM. The system may be integrated on an integrated circuit chip.

Graphics display system with video synchronization feature

A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, graphics input and audio input simultaneously. The system includes a video decoder having a chroma-locked sample rate converter. The chroma-locked sample rate converter converts the samples to those taken at a sample rate that is a multiple of the chroma subcarrier frequency and that is locked to chroma bursts of the analog video signal in a control loop. The video decoder also includes a line-locked sample rate converter that receives samples at a multiple of the chroma subcarrier frequency and converts the samples to samples with a sample frequency that is a multiple of the horizontal line rate of the video input. The line-locked sample rate converter measures the horizontal line rate to an accuracy of a fraction of a pixel and adjusts the sample rate and phase of the line-locked sample rate converter to produce accurate line-locked samples. The time base corrector receives samples at the output of the line-locked sample rate converter and provides samples synchronized to the display clock for reducing undesirable artifacts such as jitter.

Graphics display system with unified memory architecture

A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.

Video and graphics system with video scaling

A video and graphics system has a reduced memory mode in which video images are reduced in half in horizontal direction during decoding. The video and graphics system includes a video decoder for decoding MPEG-2 video data. The video images may not be downscaled in the horizontal direction when no bi-directionally predicted pictures are used. The video and graphics system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format. The output having an SDTV format may be recorded using a video cassette recorder (VCR) while the HDTV video is being displayed.

Graphics display system with anti-flutter filtering and vertical scaling feature

A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.

Video, audio and graphics decode, composite and display system

A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I/O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format.

Graphics display system with anti-aliased text and graphics feature

A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The system may use anti-aliased text and graphics to provide high quality display of graphical elements, or glyphs, which represent an image of a character of text or graphics, on television and other displays. The graphical elements may be superimposed over live video or arbitrary graphics imagery.

Graphics display system with anti-flutter filtering and vertical scaling feature

A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.

Graphics display system with video scaler

A method for processing video data includes performing by one or more processors and/or circuits in a video processing device, the one or more processors and/or circuits including a video scaler, a memory, and a scaler engine, functions including receiving a video image by the video processing device. The functions also include determining whether the video scaler requires less memory bandwidth to scale the video image before writing the video image to the memory or after reading the video image from the memory, and scaling the video image based on the determination. If the video scaler requires less memory bandwidth to scale the video image before writing the video image to the memory, performing by the one or more processors and/or circuits scaling of the video image in the video scaler using a video input clock of the video scaler to generate a first scaled video image.

Graphics display system with window descriptors

A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip uses window descriptors to describe logical surfaces, or windows, of graphics information to be displayed on the screen. The chip incorporates a unified memory architecture that provides a high level of system performance while conserving memory bandwidth and chip size. Video and graphics scaling capabilities as well as anti-flutter filtering capability are provided.

Graphics display system with color look-up table loading mechanism

A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip includes a display engine that processes graphics images organized as windows. The display engine processes graphics images formatted in any one of a plurality of formats including a color look up table (CLUT) format. A color look-up (CLUT) table loading mechanism preferably facilitates the transfer of real-time CLUT table data during graphics composition. The loading mechanism may be triggered by a window descriptor that contains a color look-up table load command.

Graphics display system with line buffer control scheme

A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip includes a display engine that processes graphics images organized as windows. The system includes plurality of line buffers for receiving the graphics contents. The graphics contents are composited into each of the plurality of line buffers by blending the graphics contents with the existing contents of the line buffer until all of the graphics surfaces for the line have been composited.

Video and graphics system with parallel processing of graphics windows

A display engine of a video and graphics system includes one or more processing elements and receives graphics from a memory. The graphics data define multiple graphics layers, and the processing elements process two or more graphics layers in parallel to generate blended graphics. Alpha values may be used while blending graphics. The processing elements may be integrated on an integrated circuit chip with an input for receiving the graphics data and other video and graphics components. The display engine may also include a graphics controller for receiving two or more graphics layers in parallel, for arranging the graphics layers in an order suitable for parallel processing, and for providing the arranged graphics layers to the processing elements. The blended graphics may be blended with HDTV video or SDTV video, which may be extracted from compressed data streams such as an MPEG Transport stream.

Graphics display system with anti-flutter filtering and vertical scaling feature

A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.

Video, audio and graphics decode, composite and display system

A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I/O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format.

Graphics display system with anti-flutter filtering and vertical scaling feature

A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.

Graphics display system with video synchronization feature

A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, graphics input and audio input simultaneously. The system includes a video decoder having a chroma-locked sample rate converter. The chroma-locked sample rate converter converts the samples to those taken at a sample rate that is a multiple of the chroma subcarrier frequency and that is locked to chroma bursts of the analog video signal in a control loop. The video decoder also includes a line-locked sample rate converter that receives samples at a multiple of the chroma subcarrier frequency and converts the samples to samples with a sample frequency that is a multiple of the horizontal line rate of the video input. The line-locked sample rate converter measures the horizontal line rate to an accuracy of a fraction of a pixel and adjusts the sample rate and phase of the line-locked sample rate converter to produce accurate line-locked samples. The time base corrector receives samples at the output of the line-locked sample rate converter and provides samples synchronized to the display clock for reducing undesirable artifacts such as jitter.

Graphics display system with anti-aliased text and graphics feature

A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The system may use anti-aliased text and graphics to provide high quality display of graphical elements, or glyphs, which represent an image of a character of text or graphics, on television and other displays. The graphical elements may be superimposed over live video or arbitrary graphics imagery.

Graphics display system with unified memory architecture

A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.

Graphics display system with video synchronization feature

A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, graphics input and audio input simultaneously. The system includes a video decoder having a chroma-locked sample rate converter. The chroma-locked sample rate converter converts the samples to those taken at a sample rate that is a multiple of the chroma subcarrier frequency and that is locked to chroma bursts of the analog video signal in a control loop. The video decoder also includes a line-locked sample rate converter that receives samples at a multiple of the chroma subcarrier frequency and converts the samples to samples with a sample frequency that is a multiple of the horizontal line rate of the video input. The line-locked sample rate converter measures the horizontal line rate to an accuracy of a fraction of a pixel and adjusts the sample rate and phase of the line-locked sample rate converter to produce accurate line-locked samples. The time base corrector receives samples at the output of the line-locked sample rate converter and provides samples synchronized to the display clock for reducing undesirable artifacts such as jitter.

Video and graphics system with MPEG specific data transfer commands

A video and graphics system includes a video decoding system for processing compressed video data. The compressed video data includes MPEG-2 video data containing SDTV video data or HDTV video data. The video decoding system includes a video decoder for processing the compressed video data to generate displayable video, and a memory controller for transferring the compressed video data to and from an external memory. The video decoder requests to the memory controller to transfer the compressed video data using one of predetermined addressing patterns. The predetermined addressing patterns allow for more efficient transferring of the compressed video data to and from the external memory when compared to sequentially transferring a fixed number of data bytes starting at a fixed address. The use of the predetermined addressing patterns results in reading the compressed video data from the external memory in a predetermined order in a less number of clock cycles. The use of the predetermined addressing patterns also results in transferring the compressed video data over the data bus between the memory controller and the video decoder in a less number of clock cycles.

Graphics display system with video synchronization feature

A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, graphics input and audio input simultaneously. The system includes a video decoder having a chroma-locked sample rate converter. The chroma-locked sample rate converter converts the samples to those taken at a sample rate that is a multiple of the chroma subcarrier frequency and that is locked to chroma bursts of the analog video signal in a control loop. The video decoder also includes a line-locked sample rate converter that receives samples at a multiple of the chroma subcarrier frequency and converts the samples to samples with a sample frequency that is a multiple of the horizontal line rate of the video input. The line-locked sample rate converter measures the horizontal line rate to an accuracy of a fraction of a pixel and adjusts the sample rate and phase of the line-locked sample rate converter to produce accurate line-locked samples. The time base corrector receives samples at the output of the line-locked sample rate converter and provides samples synchronized to the display clock for reducing undesirable artifacts such as jitter.

Graphics display system with anti-flutter filtering and vertical scaling feature

A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.

Video and graphics system with video scaling

A video and graphics system has a reduced memory mode in which video images are reduced in half in horizontal direction during decoding. The video and graphics system includes a video decoder for decoding MPEG-2 video data. The video images may not be downscaled in the horizontal direction when no bi-directionally predicted pictures are used. The video and graphics system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format. The output having an SDTV format may be recorded using a video cassette recorder (VCR) while the HDTV video is being displayed.

Graphics display system with unified memory architecture

A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.