Austenitic stainless steel pipe excellent in steam oxidation resistance and manufacturing method therefor

There is provided an austenitic stainless steel pipe excellent in steam oxidation resistance. The austenitic stainless steel pipe excellent in steam oxidation resistance contains, by mass percent, 14 to 28% of Cr and 6 to 30% of Ni, and is configured so that a region satisfying the following Formula exists in a metal structure at a depth of 5 to 20 μm from the inner surface of the steel pipe: (α/β)×δ/ε×100≧0.3 where the meanings of symbols in the above Formula are as follows: α: sum total of the number of pixels of digital image in region in which orientation difference of adjacent crystals detected by electron backscattering pattern is 5 to 50 degrees β: the number of total pixels of digital image in region of measurement using electron backscattering pattern ε: analysis pitch width of electron backscattering pattern (μm) δ: grain boundary width (μm).

Filed programmable gate array device with programmable interconnect in back end of line portion of the device

A Field-Programmable Gate Array device is provided with programmable interconnect points in the form of interconnect circuits comprising one or more pass transistors, wherein at least some components of the interconnect circuits are implemented in the Back-End-Of-Line part of the Field-Programmable Gate Array device's production process. The memory element in an interconnect point is not produced as a Static Random Access Memory cell, but as a Dynamic Random Access Memory cell, requiring only a single select transistor and a storage capacitor for each memory element. The fabrication of at least the select transistor and the pass transistor involves the use of a thin film semiconductor layer, e.g., Indium Gallium Zinc Oxide, enabling production of transistors with low leakage in the Back-End-Of-Line.

System and Method for Producing a Nano Metal Mesh using a Brittle Film Template for Lithography

This disclosure teaches a method for producing a nano metal mesh. A brittle layer can be deposited onto a flexible substrate, the brittle layer having a thickness on the flexible substrate. The flexible substrate can be bent to produce a plurality of gaps on the brittle material. A material can be deposited at the surface of the flexible substrate filling the gaps of the brittle layer. Then, the brittle layer can be etched from the flexible substrate using an etchant, a nano metal mesh formed by the material previously in the gaps. The disclosure also teaches a nano metal mesh made using this method. 1. A nano metal mesh manurfactured bydepositing a brittle layer onto a flexible substrate, said brittle layer having a thickness on said flexible substrate;bending said flexible substrate to produce a plurality of gaps on said brittle material;depositing a material at the surface of said flexible substrate filling said gaps of said brittle layer;etching said brittle layer from said flexible substrate using an etchant, a nano metal mesh formed by said material previously in said gaps.2. The nano metal mesh of wherein said flexible substrate is a bendable Optical grade Poly-ethylene Terephthalate (PET) film.3. The nano metal mesh of wherein said brittle layer comprises a Spin On Glass (SOG) liquid glass.4. The nano metal mesh of wherein said water solution is a Sodium Chloride (NaCl) water solution.5. The system of wherein said etchant is a hydrofluoric acid solution. This application is a continuation of pending utility application entitled, “Method for Producing a Nano Metal Mesh using a Brittle Film Template for Lithography” by Ethan Pfeiffer filed Sep. 21, 2015.This disclosure relates to a system and method for producing a nano metal mesh using a brittle film template for lithography.In the recent years, the growth of touch related devices and touch related applications made a huge impact in the development of transparent conductive film. Currently, the transparent ...

Bonded structure and method for manufacturing the same

An amorphous structure layer is formed on a surface layer of a bonded portion of each of side brackets. A bottomed hole layer including a plurality of bottomed holes is formed on a surface layer of the amorphous structure layer. Each of the bottomed holes has a reverse-tapered shape, which has, between an opening portion and a bottom portion of each of the bottomed holes, a bulged portion having a larger inner circumference than the opening portion. An adhesive is injected into the bottomed holes. An outer circumferential surface of the bonded portion of each of the side brackets and an inner circumferential surface of an end portion of a center beam face toward each other with the adhesive interposed therebetween.

Method for Dry Etching Compound Materials

A method for treating a substrate includes receiving the substrate in a vacuum process chamber. The substrate includes a III-V film layer disposed on the substrate. The III-V film layer includes an exposed surface, an interior portion underlying the exposed surface, and one or more of the following: Al, Ga, In, N, P, As, Sb, Si, or Ge. The method further includes altering the chemical composition of the exposed surface and a fraction of the interior portion of the III-V film layer to form an altered portion of the III-V film layer using a first plasma treatment, removing the altered portion of the III-V film layer using a second plasma treatment, and repeating the altering and removing of the III-V film layer until a predetermined amount of the III-V film layer is removed from the substrate.

Batch-processing method for super-high aspect ratio diffractive optics

A method for fabrication of diffractive optics by batch processing is disclosed, having applicability to high resolution ultra-high aspect ratio Fresnel Zone Plates for focusing of X-rays or gamma-rays having energies up to hundreds of keV. An array of precursor forms is etched into a planar substrate. Sidewalls of the forms are smoothed to a required surface roughness. A sequence of alternating layers of different complex refractive index, for binary or higher order diffractive optics, are deposited on the precursor forms by atomic layer deposition (ALD), to provide diffractive line patterns. Thinnest layers may have nanometer thicknesses. After front surface planarization and thinning of the substrate to expose first and second surfaces of the diffractive line patterns of the diffractive optic, the height h in the propagation direction provides a designed absorption difference and/or phase shift difference between adjacent diffractive lines. Optionally, post-processing enhances mechanical, thermal, electrical and optical properties.

Methods, systems, and computer program products for generating semiconductor circuit layouts

A method of generating electronic circuit layout data can include electronically providing data representing a first standard cell layout including a first scaling enhanced circuit layout in an electronic storage medium. The first scaling enhanced circuit layout included in the first standard cell layout can be electronically defined using a marker layer. The first scaling enhanced circuit layout can be electronically swapped for a second scaling enhanced circuit layout to electronically generate data representing a second standard cell layout in the electronic storage medium. The data representing the second standard cell layout can be electronically verified.

Manufacturing high speed low leakage radiation hardened CMOS/SOI devices

A method of fabricating high speed, low leakage, radiation hardened integrated circuit semiconductor devices. In accordance with the method a SIMOX (separation by ion implantation of oxygen) wafer is masked with a separation mask to form silicon islands. The separation mask forms groups of N-channel and P-channel devices that are isolated from each other. The N- and P-channel device separation assists in preventing device latch-up. N- and N-channel devices are isolated by controlling the process due to high field inversion thresholds and radiation hardened field oxide to eliminate any channel-to-channel leakage current after high dosage irradiation. A relatively thin gate oxide layer is formed over the islands, and the island edges are covered with phosphoroborosilicate glass deposited at a relatively low temperature (850° C.) to eliminate sharp island edges and hence edge leakage. The use of SIMOX substrate materials, phosphoroborosilicate glass and thin oxide provides the benefits of improved speed and reduced leakage due to intrinsic oxide isolation, shallow wells and source and drain junctions. The use of a thin thermal oxide layer and phosphoroborosilicate glass eliminates the edge leakage and channel-to-channel leakage upon high dosage irradiation, thus providing improved radiation hardness. The method of the present invention provides for devices having stable field behavior after irradiation. The method produces radiation hardened devices that exhibit high speed and reliability and which are stable when irradiated with up to a 10 MRad dosage level.

Procedure for fabricating a pressure transducer using the silicon on isolation technique and transducer thus obtained

Method for manufacturing a pressure sensor using silicon on insulator technology and sensor obtained.

Process for passivating crystal defects in a polycrystalline silicon material

A process for passivating crystal defects in polycrystalline or amorphous silicon material by thermal treatment in a hydrogen- containing atmosphere is intended to make it readily possible to achieve beneficial diode properties and/or beneficial passivation properties in amorphous or polycrystalline silicon material. Hydrogen/oxygen compounds are reduced at the surface of the silicon material, producing atomic hydrogen which diffuses into the silicon material. <IMAGE>

Method of reclaiming a semiconductor wafer

A method of reclaiming a semiconductor wafer wherein wafers which have been rejected due to electrical failures or visual defects can be processed to form a purer wafer capable of providing above average yields. The method comprises the steps of gettering to draw undesired point defects (impurities and vacancies) toward the wafer surface and chemical etching to remove most of the point defects whose presence in silicon would lower semiconductor yields. Other steps include grinding the back surface of the wafer to form an insitu getter region and finally polishing the front of the wafer to form a strain-free mirrorlike finish.

Method of reclaiming processed semiconductior wafers

A METHOD OF PROCESSING SEMICONDUCTOR WAFERS WHEREIN WAFERS HAVING EPITAXIAL LAYERS CONTAINING DIFFUSION REGIONS WHICH HAVE BEEN REJECTED DUE TO ELECTRICAL FAILURES OR VISUAL DEFECTS CAN BE ECONOMICALLY PROCESSED AND RECLAIMED FOR FURTHER DEVICE FABRICATION. THE METHOD UTILIZES THE COMBINATION OF AN EPITAXIAL LAYER AND AN OVERLYING OXIDE LAYER TO ESSENTIALLY ELIMINATE AUTO-DOPING BY IMPURITIES DIFFUSED OR CONTAINED THEREIN DURING SUBSEQUENT FABRICATION STEPS.

Formation of self-aligned stacked CMOS structures by lift-off

A process for fabricating a self-aligned three-dimensionally integrated circuit structure having two channel regions responsive to a common gate electrode. A relatively thick lift-off region is formed over and in alignment with the gate electrode. A thick oxide layer is then deposited over the structure so as to form stressed oxide extending from the lift-off layer sidewalls. A selective etch of the stressed oxide follows. The relatively thick oxide covering the lift-off layer is then removed with the etch of the lift-off layer, the lift-off etch acting through the exposed lift-off layer sidewalls. The formation of an upper field effect transistor gate oxide and a conformal deposition of polysilicon for the channel and source/drain regions follows. The conformally deposited polysilicon retains the contour of the recess formed by the lift-off. The gate aligned recess is then filled with a dopant masking material by deposition and etching, which dopant masking material thereafter defines during implant or diffusion an upper field effect transistor channel region self-aligned with the common gate electrode. The characteristics of the upper field effect transistor can be improved by applying laser recrystallization techniques.

Silicon dioxide etch process which protects metal

The present invention is directed to a novel etching process for a semiconductor material which inhibits corrosion of metal comprised of pretreating the material, preferably with a surfactant, and then exposing the material to a mixture comprising salt, a buffered oxide etch, and optionally a surfactant.

Method for forming a void free isolation pattern utilizing etch and refill techniques

The void-free pattern of isolation in a semiconductor substrate is described. There is contained within a semiconductor body a pattern of substantially vertically sided trenches. The pattern of isolation trenches isolate regions of monocrystalline semiconductor material which may contain active and passive semiconductor devices. The depth of the pattern of trenches is greater than about 3 micrometers. A first insulating layer is located upon the sidewalls of the trenches. The base or bottom of the trenches is open to the monocrystalline semiconductor body. An epitaxial layer extending from the base of the trenches fills the pattern of trenches up to between about 500 to 1500 nanometers from the upper surface of the trenches. A capping second insulating layer fills the additional portion of the pattern of trenches above the upper surfaces of the epitaxial layer for isolation of the pattern of trenches from the ambient. It is the dense epitaxial monocrystalline semiconductor which prevents the formation of voids within the pattern of trenches. The epitaxial layer must be grown in such a way so as no spurious growth occurs upon the principal surfaces of the substrate, because such growth would prevent the satisfactory chemical-mechanical polishing of the C.V.D. insulator layer.

Planarization process

A method for forming a multilayer integrated circuit is described wherein the resultant top surface thereof is substantially planar. The method involves first forming a layer of connecting metallization on integrated circuit components formed in a conventional manner. Then a first layer of dielectric is formed on the metallization layer. Next a second dielectric layer is formed on the first dielectric layer. Via areas are then formed by etching the first and second dielectric layers in order to expose selected areas of the first metallization layer, and filled with metal to form vias. A layer of photoresist is deposited on all surfaces. Lastly, the surface is etched using an etchant that etches dielectric, metal and photoresist at substantially the same rate such that said vias are exposed and a planar top surface produced.

Semiconductor double heterostructure laser device with InP current blocking layer

A semiconductor laser device comprising a semiconductor substrate, a multi-layered double heterostructure having active layers, a pair of cladding layers, a ridged waveguide structure and a current confining structure formed between the semiconductor substrate and the active layer. With such an arrangement, injected current is narrowed not only on the side above the ridge of the active layer but also on the substrate side of the active layer to improve the threshold current and its current confinement performance. When the two lateral trenches of the ridge are embedded with resin layers, the ridge stripe width can be made narrow to improve the threshold current of the device. When the active layer is realized in a DCC structure having two active layers and having an intermediary clad layer sandwiched therebetween, the device will show a low threshold current circular beam divergence and stabilized thermal characteristics.

Method for low temperature bonding and bonded structure

A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO 2 . The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.

Method for manufacturing semiconductor device

Method of planarization of topologies in integrated circuit structures

A method is disclosed for making a highly planarized integrated circuit structure having deposited oxide portions planarized to the level of adjacent portions of the integrated circuit structure which comprises: deposition, over an integrated circuit structure having first portions at a height higher than the remainder of the integrated circuit structure, a conformal oxide layer; depositing a layer of a planarizing material such as polysilicon over the conformal oxide layer; polishing the structure a first time to expose the highest portions of the underlying conformal oxide layer; etching the structure a first time with an etchant system capable of removing the conformal oxide preferentially to the planarizing material; further polishing the structure a second time to remove planarizing material left from the first etching step; and then optionally etching the remainder of the structure to remove any remaining planarizing material and the remaining conformal oxide over the raised portions of the underlying integrated circuit structure to provide the desired highly planarized structure.

Method of planarization of topologies in integrated circuit structures

A method is disclosed for making a highly planarized integrated circuit structure having deposited oxide portions planarized to the level of adjacent portions of the integrated circuit structure which comprises: depositing, over an integrated circuit structure having first portions at a height higher than the remainder of the integrated circuit structure, a conformal oxide layer having a thickness which exceeds the height of said first portions above the remainder of the integrated circuit structure; forming a patterned mask layer over said deposited oxide layer with one or more openings therein in registry with the higher height first portions of the integrated circuit structure; etching exposed portions of said conformal oxide layer through the mask openings down to a level approximately equal to the level of the unexposed portion of the conformal oxide layer; removing the mask layer; and polishing the oxide layer to remove raised portions of the conformal oxide layer remaining after the etching step to form a highly planarized structure. Optionally, the oxide layer may be further etched anisotropically until the upper surfaces of the underlying integrated circuit structure is exposed.

Method of forming late isolation with polishing

Isolation and passivation structures are formed in a single step, after transistor fabrication, by CVD deposition of a layer of oxide or BPSG over the wafer. The passivation/isolation layer overfills trenches formed for isolation and covers the patterned transistor device The layer is subsequently planarized by chem-mech polishing. With only one deposition step involved, to form both isolation structures and a passivation layer, there is significantly less strain on the thermal budget. Process and product by process are disclosed.

Techniques for forming isolation structures

Various techniques of forming isolation structures between adjacent diffusion regions are disclosed. In one technique, a thermally-grown oxide isolation structure is gouged out, and subsequent poly extending into the gouged out isolation structure is substantially level with the diffusion region. In another technique, a trench (bathtub) is formed, lightly oxidized, overfilled with polysilicon or amorphous silicon, gouged out, and thermally treated to form a substantially planar isolation structure. In another technique, an isolation structure exhibiting bird's-heads and bird's-beaks is polished until the bird's-beaks are removed. Gouging of the diffusion area may be permitted to occur. A bipolar transistor structure can be formed in the gouged diffusion area, and will exhibit reduced spacing between the intrinsic base and collector without proportionally reduced spacing between the extrinsic base and the collector.

Refractory metal capped low resistivity metal conductor lines and vias

A contact structure for a semiconductor device having a first refractory metal layer formed only at the bottom of a contact hole. The first refractory metal is selected from a group comprising titanium (Ti), titanium alloys or compounds such as Ti/TiN, tungsten (W), titanium/tungsten (Ti/W) alloys, or chromium (Cr) or tantalum (Ta) and their alloys or some other suitable material. A low resistivity layer comprising a single, binary or ternary metalization is deposited over the first refractory metal layer in the contact hole by a method such as PVD using evaporation or collimated sputtering. The low resistivity layer has side walls which taper inwardly toward one another with increasing height of the layer and the low resistivity layer does not contact the side walls of the contact hole. The low resistivity layer may be Al x Cu y (x+y=1; x≧0, y≧0), ternary alloys such as Al-Pd-Cu or multicomponent alloys such as Al-Pd-Nb-Au. A second refractory metal layer is deposited over the low resistivity layer. The second refractory metal layer may be tungsten, cobalt, nickel, molybdenum or alloys/compounds such as Ti/TiN. The first and second refractory metal layers completely encapsulate the low resistivity layer. The first and second refractory metal layers can comprise an alloy containing silicon with a higher incorporated silicon content near the top of the contact hold present as a distinct or graded composition than at a location closer to the bottom of the contact hole.

Semiconductor device having a ternary boron nitride film and a method for forming the same

A non-silyated, ternary boron nitride film (18, 38) is provided for semiconductor device applications. The non-silyated, ternary boron nitride film is preferably formed by plasma-enhanced chemical vapor deposition using non-silyated compounds of boron, nitrogen, and either oxygen, germanium, germanium oxide, fluorine, or carbon. In one embodiment, boron oxynitride (BNO) is deposited in a plasma-enhanced chemical vapor deposition reactor using ammonia (NH 3 ), diborane (B 2 H 6 ), and nitrous oxide (N 2 O). The BNO film has a dielectric constant of about 3.3 and exhibits a negligible removal rate in a commercial polishing apparatus. Because of its low dielectric constant and high hardness, the ternary boron nitride film formed in accordance with the invention can be advantageously used as a polish-stop layer and as a interlevel dielectric layer in a semiconductor device.

Shallow trench etch

A trench mask is formed of two dissimilar layers of material deposited over a substrate. The lower of the two layers is an insulating layer such as silicon dioxide or silicon nitride, or combinations of both, and the upper of the two layers is doped or undoped polysilicon. Together, the two layers are patterned in a first etch step to form a trench mask for subsequent etching of trenches in the substrate. The upper layer is deposited to a thickness "t" related to the desired depth "d" of the trenches to be etched. In a second etch step, the trenches are formed in the substrate. In the case of substantially uniform etching of the polysilicon and the substrate, the thickness of the polysilicon is substantially equal to the desired trench depth. In the case of unequal etching of the polysilicon and the substrate, the thickness of the polysilicon is based on the etch rate disparity. In either case, trench etch endpoint detection is provided by clearing of the polysilicon and consequent exposure of the lower layer of the trench mask. In both cases, loading effects during the second etch step are alleviated, or completely eliminated, because both the upper layer and the substrate are silicon-based materials.

Method for producing a metallization level having contacts and interconnects connecting the contacts

An insulating layer wherein contact holes to regions to be contacted are opened is applied surface-wide onto a substrate. For producing an interconnect mask, a photoresist layer is applied, exposed and developed such that the surface of the regions to be contacted remains covered with photoresist in exposed regions, whereas the surface of the insulating layer is uncovered in the exposed regions. Using the interconnect mask as etching mask, trenches are etched into the insulating layer. Contacts and interconnects of a metallization level are finished by filling the contact holes and the trenches with metal.

Method of manufacturing a III-V semiconductor gate structure

A manufacturable III-V semiconductor gate structure having small geometries is fabricated. A silicon nitride layer is formed on a III-V semiconductor material and a dielectric layer comprised of aluminum is formed on the silicon nitride layer. Another dielectric layer comprised of silicon and oxygen is formed over the dielectric layer comprised of aluminum. The dielectric layer comprised of aluminum acts as an etch stop for the etching of the dielectric layer comprised of silicon and oxygen with a high power reactive ion etch. The dielectric layer comprised of aluminum may then be etched with a wet etchant which does not substantially etch the silicon nitride layer. Damage to the surface of the semiconductor material by exposure to the high power reactive ion etch is prevented by forming the dielectric layer comprised of aluminum between the silicon nitride layer and the dielectric layer comprised of silicon and oxygen.

Dense flash semiconductor memory structure

Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.

Method of etching a lens for a semiconductor solid state image sensor

Methods of etching optical elements in association with photosensitive elements are described. In some of the arrangements, the optical elements are formed integrally with a substrate containing the photosensitive elements. In other arrangements, an optical element is mounted to a package, or the like, containing the substrate and photosensitive elements. In other arrangements, two or more optical elements are employed, including conventional refractive elements, refractive focusing elements, and refractive beam splitting elements. Utility as solid state image sensors is discussed. Utility for monochromatic and color imaging is discussed.

Method of manufacturing a semiconductor wafer

Process for the production of components with field effect transistors arranged one above the other with a tungsten grating and the resulting structure.

Method for depositing interconnection metallurgy using low temperature alloy processes

A method for filling VLSI high aspect ratio vias and lines in VLSI interconnection structures, with a low resistivity metal at temperatures below 400° C. A low melting point alloy of a desired low resistivity metal is deposited into the high aspect ratio vias or lines. The alloy is then purified in place by bringing the alloying element to the surface of the deposited alloy and removing the element from said surface thereby leaving the low resistivity metal in the interconnection structure. In one embodiment, the alloy is purified by using a low temperature oxidation process to allow the alloying element to diffuse to the surface of the deposited alloy where a surface oxide is formed. The surface oxide is then removed by chemical etching or by chemical mechanical polishing. In a second embodiment, a continuous exposure to a plasma etching or reactive ion etching will steadily remove the alloying element from the surface of the deposited alloy. In a third embodiment, the deposited alloy is planarized and then a sink layer is deposited onto the planarized interconnection structure. The structure is annealed in order to allow the alloying element to diffuse into the sink layer. The sink layer is then removed by chemical mechanical polishing.

Metal plug forming method and wiring forming method

Preparation of semiconductor devices having uniform junctions

Semiconductor-metal-semiconductor structure

Techniques for forming isolation structures

Various techniques of forming isolation structures between adjacent diffusion regions are disclosed. In one technique, a thermally-grown oxide isolation structure is gouged out, and subsequent poly extending into the gouged out isolation structure is substantially level with the diffusion 58 region. In another technique, a trench (bathtub) is formed, lightly oxidized, overfilled with polysilicon or amorphous silicon, gouged out, and thermally treated to form a substantially planar isolation structure. In another technique, an isolation structure exhibiting bird's-heads and bird's-beaks is polished until the bird's-beaks are removed. Gouging of the diffusion area may be permitted to occur. A bipolar transistor structure can be formed in the gouged diffusion area, and will exhibit reduced spacing between the intrinsic base and collector without proportionally reduced spacing between the extrinsic base and the collector.

Refractory metal capped low resistivity metal conductor lines and vias

Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the-hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH 4 to WF 6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metalizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below lmtorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1 mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.

Refractory metal capped low resistivity metal conductor lines and vias

A device includes a substrate, at least one dielectric layer positioned on said substrate, and metalization positioned in an opening in the at least one dielectric layer and extending a predetermined distance towards the substrate from a surface which is substantially coplanar with a surface of the at least one dielectric layer. The metalization includes a low resistivity metal or alloy encapsulated by a refractory metal or alloy having a resistivity greater than that of the low resistivity metal or alloy and having a columnar structure. The metalization has a plurality of sides in cross-section, at least three sides of the plurality of sides being substantially formed of a refractory metal or alloy having a common composition, at least two sides of the plurality of sides extending substantially the predetermined distance, and all of the plurality of sides being formed within the opening in the at least one dielectric layer.

Refractory metal capped low resistivity metal conductor lines and vias

Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH 4 to WF 6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metalizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1 mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1 mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.

Refractory metal capped low resistivity metal conductor lines and vias

Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH 4 to WF 6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metalizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1 mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1 mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.

Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD

Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH 4 to WF 6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metalizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1 mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1 mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.

Method of forming image with binary lens element array

Methods of etching optical elements in association with photosensitive elements are described. In some of the arrangements, the optical elements are formed integrally with a substrate containing the photosensitive elements. In other arrangements, an optical element is mounted to a package, or the like, containing the substrate and photosensitive elements. In other arrangements, two or more optical elements are employed, including conventional refractive elements, refractive focusing elements, and refractive beam splitting elements. Utility as solid state image sensors is discussed. Utility for monochromatic and color imaging is discussed.

Packing density for flash memories

Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.

Packing density for flash memories

Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.

Readable alignment mark structure formed using enhanced chemical mechanical polishing

A structure of a readable alignment mark and method of manufacturing the readable alignment mark in an alignment mark area on a semiconductor substrate. A semiconductor substrate 10 comprising a product area 12 and an alignment mark area 30 is provided. The alignment mark area 30 has an outer area 40 and an inner area 50. The outer area surrounds 40 the inner area 50. A plurality of alignment mark trenches 24 is formed in the substrate 10 within the inner area 50. A pad oxide layer 20 and a silicon nitride layer 44 are formed sequentially in at least the alignment mark area 12. An isolation trench 43 is formed in the substrate 10 in at least the outer area 40. An insulating layer 46 is formed at least over the alignment mark area 30. The insulating layer 46 is chemical-mechanical polished thereby removing a first thickness of the insulating layer from the inner alignment mark area 50 and leaving a residual insulating layer 46A in the alignment mark trenches 48. Etches are used to remove the residual insulating layer 46A, silicon nitride layer 44, and pad oxide layer 42 in the alignment mark area 30 thereby exposing the alignment marks 48 and making the alignment marks readable.

Process for forming trenches and contacts during the formation of a semiconductor memory device

A method of forming a contact to a semiconductor memory device feature comprises the steps of forming a first oxide layer over a feature such as a semiconductor substrate or a conductive line or plate, then forming a hard mask over the first oxide layer. A first patterned resist layer is formed on the hard mask, then the hard mask is patterned using the first resist layer as a pattern. The first resist layer is removed and a second oxide layer is formed over the hard mask. A second patterned resist layer is formed over the second oxide layer and the second oxide layer is etched using the second resist layer as a pattern while, during a single etch step, the first oxide layer is etched using the hard mask as a pattern, the hard mask functioning as an etch stop. The second resist layer is removed and a conductive layer is formed over the second dielectric layer and the hard mask, with the conductive layer (including any adhesion layers required to adhere the conductive layer to the underlying layer) contacting the feature and forming contacts. The conductive layer is then planarized.

Method of manufacturing semiconductor device using chemical-mechanical polishing

A method of manufacturing a semiconductor device in which a portion of a monocrystalline silicon layer protruded from a surface of an insulating member is polished up to the surface by a chemical-mechanical polishing is disclosed. A polycrystalline silicon layer and a leveling material are formed in sequence on the protruded portion of the monocrystalline silicon layer and on an exposed part of the surface of the insulating member, and a reactive ion etching and the chemical-mechanical polishing are carried out.

Method of making integrated circuits

A method is provided for forming a fully planarized trench isolated region in a semiconductor substrate for an integrated circuit, for example, a trench isolated field oxide region, or a trench isolated semiconductor region in which thin film semiconductor devices are formed. Planarization is accomplished by a chemical mechanical polishing process in which coplanar layers of a chemical mechanical polish resistant material are provided in a centre region of wide trenches as well as on the semiconductor substrate surface adjacent the trenches. The chemical mechanical polish resistant layer in the centre region of a wide trench forms an etch stop to prevent dishing of layers filling the trench during overall wafer planarization by chemical mechanical polishing. The method is compatible with CMOS, Bipolar and Bipolar CMOS processes for submicron VLSI and ULSI integrated circuit structures.

Trench isolator structure in an integrated circuit

The reliability of integrated circuits fabricated with trench isolation is improved by increasing the thickness of the gate dielectric overlying the trench corner. After the trench isolation region (40, 56) has been formed a thin layer of silicon dioxide (44) is chemically vapor deposited over the trench isolation region (44) and the adjacent active region (23). A transistor gate electrode (46) is subsequently formed over the thin layer of silicon dioxide (44). The thin layer of silicon dioxide (44) increases the thickness of the gate dielectric that lies between the transistor gate electrode (46) and the trench corner, and therefore the breakdown voltage of the gate dielectric at the trench corner is increased.

Process for fabricating a semiconductor device using dual planarization layers

An improved planarization process includes the steps of forming recessed regions (38) and elevated regions (34) in a semiconductor substrate (30). The substrate is oxidized to form an oxide liner (39) overlying the recessed regions, and a fill material (40) is deposited to overlie the substrate (30) filling the recessed regions (38). An etching process is used to remove portions of the fill material (40) and to expose portions of a first planarization layer (44) overlying the elevated regions (34) of the substrate (30). The fill material is etched and a second planarization layer (46) is deposited to overlie dielectric portions (42), and portions (44) of first planarization layer (32) exposed by the etching process. A chemical-mechanical-polishing process is then carried out to form a planar surface (47), and remaining portions of the planarization layers and fill material are removed.

Shallow trench isolation process for high aspect ratio trenches

Disclosed is a method of planarizing the surface of a silicon wafer in integrated circuit manufacture where shallow trench isolation techniques are employed. The etched trenches are first coated with a silicon nitride protective liner before the trenches and active area mesas are conformally coated with a layer of silicon oxide. The conformal oxide then is steam annealed to densify the conformal oxide, and then the surface of the silicon wafer is etched and polished back down to the tops of the active area mesas, to form a substantially planar surface.

Chemical-mechanical alignment mark and method of fabrication

A method for forming an alignment mark during semiconductor device manufacturing. A first alignment mark having a first step height is formed in a semiconductor substrate. An interlayer dielectric is formed over the alignment mark and planarized to a first thickness. During contact/via etch an opening is formed through the first dielectric layer away from the first alignment mark. The opening is then filled with a material until the material in the bottom of the opening has a thickness less than thickness of the planarized dielectric layer.

Application of thin crystalline Si3 N4 liners in shallow trench isolation (STI) structures

Silicon integrated circuits use a crystalline layer of silicon nitride (Si 3 N 4 ) in shallow trench isolation (STI) structures as an O 2 -barrier film. The crystalline Si 3 N 4 lowers the density of electron traps as compared with as-deposited, amorphous Si 3 N 4 . Further, a larger range of low-pressure chemical-vapor deposited (LPCVD) Si 3 N 4 films can be deposited, providing a larger processing window for thickness controllability. An LPCVD-Si 3 N 4 film is deposited at temperatures of 720° C. to 780° C. The deposited film is in an amorphous state. Subsequently, a high-temperatures rapid-thermal anneal in pure nitrogen or ammonia is conducted at 1050° C. to 1100° C. for 60 seconds.

Method for providing trench isolation and borderless contact

A trench isolation region (32) is fabricated to include a trench liner (28) comprised of aluminum nitride. The aluminum nitride trench liner is useful in borderless contact applications wherein a contact opening (56) is etched in an interlayer dielectric (54) and overlies both an active region (e.g. doped region 52) and the trench isolation region. During formation of opening using etch chemistry which is selective to aluminum nitride, the trench liner protects a P-N junction at a corner region (58) of the trench to prevent exposing the junction. By protecting the junction, subsequent formation of a conductive plug (60) will not electrically short circuit the junction, and will keep diode leakage to within acceptable levels.

Shallow trench isolation method employing self-aligned and planarized trench fill dielectric layer

A method for forming within a trench within a substrate within an integrated circuit a planarized trench fill layer. There is first provided a substrate having a trench formed therein. There is formed upon the substrate at regions other than those within the trench a first integrated circuit layer which has a composition which inhibits formation upon the first integrated circuit layer of a trench fill layer which is subsequently formed upon the substrate and within the trench. There is also formed within the trench but not upon the substrate at regions other than those within the trench a second integrated circuit layer which has a composition which promotes formation within the trench of the trench fill layer which is subsequently formed upon the substrate and within the trench. Finally, there is formed upon the substrate and within the trench the trench fill layer. The trench fill layer is formed to a thickness over the trench such that when the trench fill layer is planarized through a chemical mechanical polish (CMP) planarizing method there is avoided formation of a dish within a planarized trench fill layer formed within the trench.

Silicon chemical mechanical polish etch (CMP) stop for reduced trench fill erosion and method for formation

A method for forming shallow trench isolation (STI) (100) begins by forming an oxidizable layer (106) preferably made of polysilicon. An opening is patterned and etched through this layer (106) to define and form the trench isolation region (108). Silicon sidewalls of the trench (108) and the polysilicon layer (106) are then exposed to an oxidizing ambient to form a thermal oxide trench liner (107a) and an erosion-protection polysilicon-oxide layer (107b). A trench fill material (110a) is then deposited and chemically mechanically polished (CMP) utilizing the polysilicon layer (106) as a polish stop. The final polished trench fill plug comprises an ozone TEOS bulk material (110c) and an annular peripheral upper erosion-protection portion formed of the polysilicon-oxide (107d). The annular polysilicon-oxide protection regions (107d) either reduce or entirely eliminate adverse sidewall parasitic erosion which occurs in conventional trench technology when processing active areas (124).

Method for improving the planarity of shallow trench isolation

A method for improving the planarity of a semiconductor chip using chemical-mechanical polishing during a shallow trench isolation process is described. Specifically, an polish-stop layer, preferably of silicon nitride, is formed over a semiconductor wafer (or optionally formed over a pad oxide layer formed on the wafer). A cap layer, preferably of polysilicon, is then formed over the polish-stop layer. The active regions of the chip are defined, preferably using a photoresist mask by photolithography. The wafer, polish-stop and cap layers are then etched, between the active regions, to form shallow trenches. A lining dielectric layer, preferably an oxide, is formed over the etched and non-etched regions to fill the shallow trenches for isolation purposes. The dielectric layer has an etching rate at least three times greater than the etching rate of cap layer. When polysilicon is selected as the cap layer and oxide is selected as the dielectric layer, the selectivity rate is greater than ten. However, the conventional oxide dielectric/nitride layer etching selectivity rate is less than three. Accordingly, the present invention provides a far greater etching selectivity rate than the prior art. In addition, the polish rate of the cap layer is much higher that that of the polish-stop layer. Therefore, the cap layer can be easily removed which reduces the CMP time while minimizing the dishing effect.

Method of performing a field implant subsequent to field oxide fabrication by utilizing selective tungsten deposition to produce encroachment-free isolation

An improved field implant process is disclosed wherein the field implant is performed after the field oxide isolation structure is fabricated by masking the active surface regions of the substrate with tungsten. The tungsten may be selectively deposited or blanket deposited. The energy of the field implant is controlled and adjusted to produce a maximum number of ions contiguous to a thinnest portion of field oxide with other portions being self-regulating.

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Solvent mixture with nitric acid and hydrofluoric acid for wet chemical etching of silicon

Self-planarized gapfilling for shallow trench isolation

A new method is disclosed to form a shallow trench isolation with a ozone-TEOS as a gapfilling material. The formation of the shallow trench isolation described herein includes a pad layer, a silicon nitride layer formed on a semiconductor substrate. A thermal oxide layer is subsequently formed on the silicon nitride layer. Then a shallow trench is created via photolithography and dry etching steps to etch the thermal oxide layer, the silicon nitride layer and the pad layer. After photoresist is removed, an ozone-TEOS layer is form in the shallow trench and on the top of the thermal oxide layer for the purpose of isolation. A CMP is perform to make the surface of the substrate with a planar surface. Then, a thermal annealing is used for densification of the ozone-TEOS layer and for forming a lining oxide to provide better isolation.

Method for manufacturing a semiconductor acceleration sensor device

On a silicon wafer there is formed a movable gate MOS transistor (sensing element: functional element). A bonding frame consisting of a silicon thin film is patterned around an element formation region on the surface of the silicon wafer. On a cap forming silicon wafer there is projectively provided a leg portion on the bottom surface of which a bonding layer consisting of a gold film is formed. The cap forming silicon wafer is disposed on the silicon wafer, whereupon heating with respect thereto is performed at a temperature equal to higher than a gold/silicon eutectic temperature to thereby make bondage between the bonding frame of the silicon wafer and the bonding layer of the cap forming silicon wafer. Thereafter, the both wafers are diced in chip units.

Planarization of integrated circuit surfaces through selective photoresist masking

An integrated circuit substrate surface, particularly a surface of electrically insulative material, having a pattern of elevated areas and a complementary pattern of unelevated areas is planarized by forming the photoresist pattern in registration with the pattern of unelevated areas, the photoresist pattern having narrower lateral dimensions than said elevated pattern whereby registration is facilitated, flowing the photoresist pattern to laterally expand the photoresist to cover and thereby mask the unelevated areas, and etching to lower the elevated area which remain uncovered by the photoresist.

Maytansinoids, pharmaceutical compositions thereof and method of use thereof

Novel maytansinoids of the formula: ##STR1## wherein X is H or Cl, and R is ##STR2## wherein R 1 and R 2 may be the same or different, and each is H or a substituted or unsubstituted hydrocarbon residue or heterocyclic group, or R 1 and R 2 may, taken together with the adjacent N atom, form a heterocyclic group, and R 3 is a substituted or unsubstituted hydrocarbon residue, have antimitotic, antitumor and antimicrobial activities.

Stainless steel drill screw

A drilling and tapping screw constructed from a 300 series stainless steel material which has the corrosive resistance of the high chromium high nickel content stainless steel while still being capable of drilling through carbon steel materials or the like. The product is constructed by forging the point at very slow forging speeds, resulting in a drill screw which is a predominantly martensitic structure at the drill point while predominantly austenitic in the shank and head regions.

Methods for making cutting tools

Improvements are provided in the structures of cutting tools and methods for producing such tools. The tool structures include providing a select portion or portions of a cutting tool, such as one or more portions adjacent a cutting or forming portion or edge or plurality of edges of a tool, of amorphous or non-crystalline metal or metal alloy having strength and wear characteristics which are superior to those of conventional metals and alloys which are crystalline in structure. Such amorphous metal may be formed in situ along the cutting edge portion of a cutting tool or blade by intense radiation beam scanning or may be formed of deposited or otherwise secured amorphous metal strip.

MEDICAL DEVICE THAT INCLUDES A REFRACTORY METAL ALLOY

A medical device that is at least partially formed of a refractory metal alloy, and a method for inserting the medical device in a patient. 1. A medical device for implantation into a body passageway; said medical device includes an expandable metal frame that is configured to expand in the body passageway when said medical device is positioned in a treatment site in the body passageway; said expandable metal frame expandable to an outer diameter of at least 25 mm; at least 50 wt. % of said expandable metal frame formed of a refractory metal alloy; said refractory metal alloy is not a self-expanding metal alloy; said expandable metal frame of said medical device includes a plurality of struts and strut joints; said expandable metal frame has a) a plurality of strut joints that is less than 0.7 mm , b) a plurality of struts having an average width along a longitudinal of said strut that is no more than 0.3 mm , c) a recoil percentage of less than 5% when said expandable metal frame is crimped to a crimped state , d) a recoil of less than 5% when said expandable metal frame is expanded from said crimped state , and/or e) a foreshortening percentage of less than 20% when said expandable metal frame is expanded from said crimped state.2. The medical device as defined in claim 1 , wherein said expandable metal frame i) has a recoil percentage of no more than 2% when said expandable metal frame is crimped to a crimped state claim 1 , ii) a recoil of no more than 2% when said expandable metal frame is expanded from said crimped state claim 1 , and/or iii) a foreshortening percentage of no more than 15% when said expandable metal frame is expanded from said crimped state.3. The medical device as defined in claim 1 , wherein claim 1 , said refractory metal alloy is selected from the group consisting of MoRe alloy claim 1 , ReW alloy claim 1 , MoReCr alloy claim 1 , MoReTa alloy claim 1 , MoReTi alloy claim 1 , WCu alloy claim 1 , ReCr alloy claim 1 , Mo alloy claim 1 , Re ...

Integrated circuit process with TiN-gate transistor

Disclosed is an integrated circuit process which includes forming two types of active devices: a first set of IGFETs has silicide gates, and the second set has TiN gates. The same TiN thin film layer also provides local interconnect. Optionally the TiN-gate devices may be used for high-voltage devices and the silicide-gate devices used for logic devices. The TiN gates in the second set of transistors and the TiN interconnect are formed by providing a thin film insulator pattern, depositing a titanium layer overall, heating the titanium in a nitrogen bearing atmosphere, and subsequently etching the titanium nitride obtained.

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Method of fabricating an integrated pressure sensor

A method of fabricating an integrated pressure sensor, which is capable of decreasing adverse effects caused by the distortion occurring at the time when a silicon wafer and a seat are joined together. On a silicon wafer 1 are formed a thin diaphragm 2 for each of the chips, a piezo-resitance layer for each of the chips, and a signal processing circuit with an adjusting resistor for each of the chips. The silicon wafer 1 is joined onto a glass seat 6 that has pressure-adjusting passges 7 formed therein to adjust the pressure exerted on the diaphragms 2 of the silicon wafer 1. Half-dicing is effected that reaches a predetermined depth of the glass seat 6 penetrating through the silicon wafer 1 for each of the chips, and resistance of the adjusting resistor is adjusted for each of the chips while adjusting the pressure applied to the diaphragms 2 via pressure-adjusting passages 7 in the seat in a step of adjusting the pressure sensitivity by trimming the wafer and by applying a negative pressure. Finally, the silicon wafer 1 and the glass seat 6 are cut by full-dicing for each of the chips.

Thin film resistors on organic surfaces

A method for fabricating a thin film resistor comprises applying a tantalum nitride layer over a dielectric layer, applying a metallization layer over the tantalum nitride layer, and patterning the metallization layer with a first portion of the metallization layer situated apart from a second portion of the metallization layer and both the first and second portions being at least partially situated on the tantalum nitride layer. In one embodiment, after patterning the metallization layer, the resistance value between the first and second portions of the metallization layer is determined and compared to a predetermined resistance value, and at least one of the first and second portions is trimmed to obtain a modified resistance value between the first and second portions that is closer to the predetermined resistance value than the determined resistance value.

Method of forming thin film resistors on organic surfaces

A method for fabricating a thin film resistor comprises applying a tantalum nitride layer over a dielectric layer, applying a metallization layer over the tantalum nitride layer, and patterning the metallization layer with a first portion of the metallization layer situated apart from a second portion of the metallization layer and both the first and second portions being at least partially situated on the tantalum nitride layer. In one embodiment, after patterning the metallization layer, the resistance value between the first and second portions of the metallization layer is determined and compared to a predetermined resistance value, and at least one of the first and second portions is trimmed to obtain a modified resistance value between the first and second portions that is closer to the predetermined resistance value than the determined resistance value.

PROCESS FOR PRODUCING THIN FILMS OF SEMICONDUCTOR MATERIAL.

Procédé de préparation de films minces de matériau semiconducteur caractérisé en ce qu'il consiste à soumettre une plaquette d'un matériau semiconducteur comportant une face plane dans le cas où le matériau est polycristallin, aux trois étapes suivantes: - une première étape d'implantation par bombardement (2) de la face (4) de ladite plaquette (1) au moyen d'ions créant dans le volume de la dite plaquette une couche (3) de microbulles gazeuses délimitant dans le volume de la dite plaquette une région inférieure (6) constituant la masse du substrat et une région supérieure (5) constituant le film mince, - une deuxième étape de mise en contact intime de la face plane (4) de la dite plaquette avec un raidisseur (7) constitué d'au moins une couche de matériau rigide; - une troisième étape de traitement thermique de l'ensemble de la dite plaquette (1) et du dit raidisseur (7) à une température supérieure à la température à laquelle est réalisé le bombardement (2) ionique et suffisante pour créer par effet de réarrangement cristallin dans la dite plaquette (1) et de pression dans les microbulles une séparation entre le film mince (5) et la masse du substrat (6). Process for the preparation of thin films of semiconductor material, characterized in that it consists in subjecting a wafer of semiconductor material comprising a flat face in the case where the material is polycrystalline, to the following three steps: - a first step of implantation by bombardment (2) of the face (4) of said wafer (1) by means of ions creating in the volume of said wafer a layer (3) of gaseous microbubbles delimiting in the volume of said wafer a lower region ( 6) constituting the mass of the substrate and an upper region (5) constituting the thin film, - a second step of bringing the flat face (4) of said wafer into intimate contact with a stiffener (7) consisting of at least a layer of rigid material; - a third step of heat treatment of the assembly of said wafer (1) ...

Light-sensitive electric device

Patent DE2931432C2

Method of forming a SOI transistor having a self-aligned body contact

An SOI transistor has a self-aligned body contact formed through an extension to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body, as in prior art schemes that passed the body contact through the source. The body contact aperture is formed by raising the source and drain to define an initial aperture, depositing a conformal layer that is etched to create aperture-defining sidewalls and etching the contact aperture using these sidewalls to define sidewall support members that support insulating sidewalls to isolate the collection electrode from both the gate and from the source and drain.

SOI transistor having a self-aligned body contact

An SOI transistor has a self-aligned body contact formed through an extension to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body, as in prior art schemes that passed the body contact through the source. The body contact aperture is formed by raising the source and drain to define an initial aperture, depositing a conformal layer that is etched to create aperture-defining sidewalls and etching the contact aperture using these sidewalls to define sidewall support members that support insulating sidewalls to isolate the collection electrode from both the gate and from the source and drain.

METHOD FOR PRODUCING A PASSIVATION LAYER.

Process for photo-assisted epitaxial growth using remote plasma with in-situ etching

A process for forming deposited film, which comprises: (a) the step of preparing a substrate having crystal nuclei or regions where crystal nuclei are selectively formed scatteringly on the surface for forming deposited film in a film forming space for formation of deposited film; (b) the step of forming deposited film on the above substrate by introducing an activated species (A) formed by decomposition of a compound (SX) containing silicon and a halogen and an activated species (B) formed from a chemical substance for film formation (B) which is chemically mutually reactive on said activated species (A) separately from each other into said film-forming space to effect chemical reaction therebetween; (c) the step of introducing a gaseous substance (E) having etching action on the deposited film to be formed or a gaseous substance (E 2 ) forming said gaseous substance (E) into said film-forming space during said film-forming step (b) and exposing the deposited film growth surface to said gaseous substance (E) to apply etching action thereon, thereby effecting preferentially crystal growth in a specific face direction; (d) irradiating said gaseous substance (E) with light energy during said step (c), and (e) the step of increasing etching activity of said gaseous substance (E) by irradiation of light energy.

How to Form Crystalline Silicon Nitride Thin Liner in Shallow Trench Isolation and Improved Shallow Trench Isolation

실리콘 집적 회로는 얕은 트렌치 격리(STI) 구조에 O 2 배리어 막과 같은 실리콘 질화물(Si 3 N 4 )의 결점 층을 사용한다. 상기 결점 Si 3 N 4 는 비결정 Si 3 N 4 를 증착된 것에 비해 전자 포획의 밀도를 더 낮춘다. 더욱이, 넓은 범위로 저압 화학-기상 증착(LPCVD)된 Si 3 N 4 는 두께 제어성을 위한 더 큰 처리 창을 제공하여 증착될 수 있다. LPCVD-Si 3 N 4 는 720℃ 내지 780℃의 온도에서 증착 된다. 상기 증착된 막은 비결정 상태이다. 실질적으로,순수한 질소 또는 암모니아에서의 고온 급속 열 어닐링은 60초 동안 1050℃ 내지 1100℃에서 수행된다. Silicon integrated circuits use a defect layer of silicon nitride (Si 3 N 4 ), such as an O 2 barrier film, in a shallow trench isolation (STI) structure. The defect Si 3 N 4 lowers the density of electron trapping compared to the deposition of amorphous Si 3 N 4 . Moreover, a wide range of low pressure chemical-vapor deposition (LPCVD) Si 3 N 4 can be deposited by providing a larger processing window for thickness controllability. LPCVD-Si 3 N 4 is deposited at a temperature of 720 ° C to 780 ° C. The deposited film is in an amorphous state. Substantially, high temperature rapid thermal annealing in pure nitrogen or ammonia is carried out at 1050 ° C. to 1100 ° C. for 60 seconds.

Способ получени полупроводниковой светоизлучающей структуры

Isolation structure of semiconductor device and manufacturing method thereof

본 발명은 반도체 기판내에 형성되고 상기 반도체 기판의 상면(A MAJOR SURFACE)으로부터 아래로 향하는 방향을 갖는 트렌치와, 상기 트렌치의 표면에 형성된 실리콘 산화막의 트렌치안감과, 상기 트렌치내를 충진하는 절연층의 트렌치플러그와, 상기 트렌치안감의 형성을 위한 열처리 공정시 동시에 형성되어 상기 트렌치 바닥 아래에, 상기 트렌치안감과 인접하여 형성된 아일랜드(ISLAND)형의 매몰(BURIED) 절연영역을 포함하여 이루어진 반도체 소자 격리구조와, 반도체기판내에 상기 반도체기판의 상면(A MAJOR SURFACE)으로부터 아래로 향하는 방향을 갖는 트렌치를 형성하는 공정과, 상기 반도체기판의 상기 트렌치 바닥 아래 부위에 산소이온을 선택적으로 주입하는 공정과, 상기 트렌치내를 충진하는 트렌치플러그를 형성하는 공정을 포함하여 이루어진 반도체 소자 격리구조 형성방법에 관한 것이다. The present invention provides a trench formed in a semiconductor substrate and having a downward direction from an upper surface (A MAJOR SURFACE) of the semiconductor substrate, trench lining of a silicon oxide film formed on the surface of the trench, and an insulating layer filling the trench. A semiconductor device isolation structure including a trench plug and an island-type buried insulation region formed at the same time during the heat treatment process for forming the trench lining and formed below the trench bottom and adjacent to the trench lining. Forming a trench having a direction downward from an upper surface of the semiconductor substrate (A MAJOR SURFACE) in the semiconductor substrate, selectively implanting oxygen ions into a portion below the trench bottom of the semiconductor substrate; Half that includes the process of forming a trench plug to fill the trench Body element isolation structure relates to a forming method.

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Method of trench isolation

STI(Shallow Trench Isolation) 공정에서 발생되는 험프(Hump)특성을 개선한 트렌치 분리방법이 개시되어 있다. A trench isolation method is disclosed which improves a hump characteristic generated in a shallow trench isolation (STI) process. 본 발명은 반도체 기판위에 패드 산화막과 질화막을 순차적으로 증착하는 제1공정과, 사진식각 공정에 의해 정의된 비활성영역의 상기 질화막 및 패드 산화막을 이방성 식각하여 상기 반도체 기판을 노출하는 제2공정과, 상기 질화막 패턴을 마스크로하여 상기 노출된 반도체 기판을 식각하여 트렌치를 형성하는 제3공정과, 상기 트렌치 표면에 열산화막을 형성하는 제4공정과, 상기 트렌치를 매립하고 평탄화하여 소자분리 산화막을 형성하는 제5공정과, 상기 소자분리 산화막을 소정 두께로 이방성 식각한 후 상기 질화막 패턴을 마스크로 트렌치 측벽 이온주입을 실시하는 제6공정과, 상기 질화막 패턴을 제거한 후 웰 형성 및 문턱 전압 조절용 이온주입을 실시하는 제7공정과, 게이트 전극을 형성하는 제8공정을 구비하여, STI 공정에서 발생되는 전류의 험프(Hump) 현상 및 기생 효과를 효과적으로 억제할 수 있다. The present invention includes a first process of sequentially depositing a pad oxide film and a nitride film on a semiconductor substrate, a second process of anisotropically etching the nitride film and the pad oxide film in an inactive region defined by a photolithography process to expose the semiconductor substrate; A third process of forming a trench by etching the exposed semiconductor substrate using the nitride film pattern as a mask, a fourth process of forming a thermal oxide film on the surface of the trench, and filling and planarizing the trench to form a device isolation oxide film And a fifth step of anisotropically etching the device isolation oxide film to a predetermined thickness, and performing trench sidewall ion implantation using the nitride film pattern as a mask, and ion implantation for well formation and threshold voltage adjustment after removing the nitride film pattern. And a seventh step of forming a gate electrode and an eighth step of forming a gate electrode, and the current generated in the STI process. It is possible to effectively suppress the hump (Hump) developing and parasitic effects.

Integrated circuit isolation method

요약없음 No summary

焼結摺動部材

半導体装置の製造方法

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Making method of bicmos device

The method comprises the steps of; forming a selective oxide layer by a common LOCOS method; ion injecting; removing polysilicone layer and gate oxide layer; As ion injecting; forming gate of N channel MOS transistor, gate of P channel MOS transistor, emitter electrode and collector electrode of NPN transistor and base electrode for VPNP transistor; P ion injecting; B ion or BF+2 ion injecting; forming oxide side wall; As ion injecting; and forming source/drain diffusion region of N channel MOS transistor, source/drain diffusion region of P channel MOS transistor, emitter diffusion region and outer base diffusion region of VPNP transistor, emitter diffusion region and outer base diffusion region of NPN transistor, thereby realizing an analog and digital BiCMOS device.

Polycrystalline film having controlled grain size and method of making same

A FILM OF A POLYCRYSTALLINE MATERIAL IS DEPOSITED PYROLYTICALLY ON AN ELECTRICALLY INSULATING SURFACE OF A SUBSTRATE. BY CONTROLLING THE RATE OF DEPOSITION OF THE MATERIAL ON THE SUBSTRATE AND THE TEMPERATURE OF THE SUBSTRATE, THE GRAIN SIZE OF THE POLYCRYSTALLINE FILM IS REGULATED SO THAT PN JUNCTIONS HAVING A SHARP REVERSE BIASED BREAKDOWN MAY BE FORMED THEREIN.

반도체장치의 제조방법

저온에서 단차 피복율이 우수한 전극 또는 배선을 형성하기에 적합한 반도체 장치의 제조 방법으로서, 다결정 Si막으로의 붕소 이온 또는 2플루오르화 붕소 이온의 주입에 의해 pnp 바이폴라 트랜지스터의 이미터를 형성하는 경우에는 900℃ 이상의 고온 열처리가 다결정 Si막내의 붕소를 활성화시키기 위해 필요하고, 확산도가 큰 붕소가 긴 거리에 걸쳐서 확산해서 얕은 접합의 형성을 곤란하게 하여 pnp 트랜지스터의 동작 속도를 개선할 수 없는 것을 해소하기 위해서, 붕소가 도프된 비정질 Si막을 디실란과 트리실란 중의 적어도 하나와 디보란을 포함하는 혼합 가스를 원료 가스로서 사용하는 감압 CVD에 의해 200℃ 이상, 400℃ 이하의 온도 범위에서 형성한다. 이러한 반도체 장치의 제조 방법에 의해, 비정질 실리콘 막이 종래 방법에 의해 형성된 다결정 실리콘 막의 경우와 비교해서 더 낮은 온도에서 불순물을 확산시킬 수 있고, 종래 기술에서 보다 더 얕은 pn접합을 형성할 수 있다.

通过高速变形而形成的不等强度材料

本发明是关于在相邻的区域具有不同强度和延展性的材料的。这种材料通过使有带状组织的金属母材高速变形而制成，目的是使金属母材产生高速的内能变化。内能的高速变化压低了金属母材的转变温度并引起同素异构转变。具体说，金属母材在变形前要保持相当低的温度而工具则要保持相当高的温度。高速变形使表面区域产生极高的加热速度，压低了转变温度，使之转变为等轴晶粒，而芯部因温度不够高，仍保持冷作加工后的带状组织。

サイリスタ

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

막 유전체 격리 ic 제조(membrane dielectric isolation ic fabrication)

High-strength welded steel pipe and method of its production

FIELD: metallurgy. SUBSTANCE: steel sheet parent metal comprises the following components, in wt %: 0.010-0.080%, Si: 0.01-0.50%, Mn: 0.50-2.00%, S: 0.0001-0.0050%, Ti: 0.003-0.030%, Mo: 0.05-1.00%, B: 0.0003-0.0100%, O: 0.0001-0.0080%, N: 0.006-0.,0118%, P: at least 0,050% or smaller, Al: at least 0.008% or smaller, Fe and unavoidable impurities making the rest. Carbon equivalent (Ceq) makes 0.30 to 0.53, crack growth resistance in welding (Pcm) makes 0.10 to 0.20, while [N]-[Ti]/3.4 does not exceed 0.003. Mean size of primary γ-grains in thermal effects zone in steel sheet makes 250 mcm or smaller, while primary γ-grains include bainite and intragranular bainite. EFFECT: sufficient low-temperature toughness. 9 cl, 3 dwg, 2 tbl, 1 ex РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) 2 509 171 (13) C1 (51) МПК C22C 38/14 B21C 37/08 (2006.01) (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ИЗОБРЕТЕНИЯ К ПАТЕНТУ (21)(22) Заявка: 2012132957/02, 04.02.2011 (24) Дата начала отсчета срока действия патента: 04.02.2011 (73) Патентообладатель(и): НИППОН СТИЛ КОРПОРЕЙШН (JP) (45) Опубликовано: 10.03.2014 Бюл. № 7 2 5 0 9 1 7 1 (56) Список документов, цитированных в отчете о поиске: JP 2003-064449 A, 05.03.2003. RU 2208747 C2, 20.07.2003. RU 2205246 C2, 27.05.2003. RU 2152450 C1, 10.07.2000. JP 2005-290526 A, 20.10.2005. JP 11-172374 A, 29.06.1999. (85) Дата начала рассмотрения заявки PCT на национальной фазе: 04.09.2012 2 5 0 9 1 7 1 R U (87) Публикация заявки РСТ: WO 2011/096510 (11.08.2011) C 1 C 1 (86) Заявка PCT: JP 2011/052348 (04.02.2011) Адрес для переписки: 129090, Москва, ул. Б. Спасская, 25, стр.3, ООО "Юридическая фирма Городисский и Партнеры" (54) ВЫСОКОПРОЧНАЯ СВАРНАЯ СТАЛЬНАЯ ТРУБА И СПОСОБ ЕЕ ПОЛУЧЕНИЯ (57) Реферат: Изобретение относится к области металлургии, а именно к получению высокопрочной сварной стальной трубы путем шовной сварки участка стального листа, которому придана форма трубы. Основной металл стального листа включает, в мас.%, C: 0, ...

Sätt att framställa elektroniska och elektro-optiska komponenter och kretsar

Method of manufacturing semiconductor integrated circuit device

본 발명은 반도체 집적회로 장치의 제조방법에 관한 것으로서, 실리콘 기판상에 실리콘 산화막, 실리콘 질화막, 다결성 실리콘막 및 보호막을 순차적으로 형성하는 단계와, 얕은 홈 형성 영역상의 상기 보호막을 에칭제거하여 상기 다결정 실리콘막의 표면을 노출시키는 단계와 깊은 홈 형성 영역상의 상기 보호막, 다결정 실리콘막, 실리콘 질화막 및 실리콘 산화막을 에칭 제거하여 실리콘 기판의 표면을 노출시키는 단계와, 상기 보호막을 마스크로 이용하여 상기 노출된 실리콘 기판 및 다결정 실리콘막을 에칭제거하여 깊은 홈 형성 영역에 소정 깊이의 홈을 형성하는 단계와, 상기 얕은 홈 형성 영역상에 남아있는 실리콘 질화막, 실리콘 산화막을 에칭 제거하여 상기 실리콘 기판의 표면을 노출시키는 단계와, 상기 보호막을 마스크로 이용하여 깊은 홈 형성 영역과 얕은 홈 형성 영역의 실리콘 기판을 동시에 에칭하여 깊은 홈과 얕은 홈을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 집적회로 장치의 제조 방법이다. The present invention relates to a method for manufacturing a semiconductor integrated circuit device, comprising the steps of sequentially forming a silicon oxide film, a silicon nitride film, a polysilicon film and a protective film on a silicon substrate, and etching and removing the protective film on a shallow groove forming region. Exposing the surface of the polycrystalline silicon film and etching away the protective film, the polycrystalline silicon film, the silicon nitride film and the silicon oxide film on the deep groove forming region to expose the surface of the silicon substrate; and using the protective film as a mask to expose the exposed surface. Etching away the silicon substrate and the polycrystalline silicon film to form grooves of a predetermined depth in the deep groove forming region, and etching away the silicon nitride film and silicon oxide film remaining on the shallow groove forming region to expose the surface of the silicon substrate. Step, using the protective film as a mask A method of manufacturing a semiconductor integrated circuit device by etching the silicon substrate to form a groove area and a shallow groove formed in the area at the same time comprising the steps of forming the deep grooves and shallow grooves.

Method for manufacturing heterojunction bipolar transistor

본 발명은 바이폴러 트랜지스터의 제조방법에 있어서, 저심도랑과 폴리실리콘 측벽막 형성공정, 자기정렬된 컬렉터-베이스 형성 공정, 및 선택적 컬렉터 이온주입에 의한 선택적 컬렉터 영역 형성공정이 개별적인 마스크의 사용없이 하나의 마스크에 의해 수행되므로 제작이 용이하며, 소자간의 격리를 위해 저심 도랑을 사용함으로써, 격리공정이 단순하며 용이할 뿐만 아니라 베이스 기생저항의 증가가 상기 저심도랑 상부에 형성된 다결정 규소 측벽막에 의해 방지되고, 상기 저심도랑에 의해 다결정 규소 측벽막 밑의 기생용량 형성이 방지된다. The present invention provides a method of manufacturing a bipolar transistor, wherein a low depth trench, a polysilicon sidewall film forming process, a self-aligned collector-base forming process, and a selective collector region forming process by selective collector ion implantation are performed without the use of a separate mask. Since it is performed by one mask, it is easy to manufacture, and by using a low core trench for isolation between devices, the isolation process is not only simple and easy, but an increase in base parasitic resistance is applied to the polycrystalline silicon sidewall film formed on the low depth trench. The parasitic capacitance under the polycrystalline silicon sidewall film is prevented by the low depth trench.