Настройки

Укажите год
-

Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

Подробнее
-

Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

Подробнее

Форма поиска

Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Укажите год
Укажите год
Применить Всего найдено 5. Отображено 5.
04-07-1995 дата публикации

VERTICAL BIPOLAR TRANSISTOR

Номер: JP0007169775A
Автор: AKBAR SHAH, KROESEN PATRICIA L, OGURA SEIKI, ROVEDO NIVO
Принадлежит:

PURPOSE: To provide a bipolar transistor in which a structure with a base contact point extending-layer which extends to one side of an emitter and a subcollector extending-layer extending to the other side is provided, and no collector reacting through contact point is contained, enabling manufacturing with high integration density using a polysilicon emitter. CONSTITUTION: A subcollector layer 26 formed on an epitaxial layer 34, a collector layer 12 in contact with a subcollector layer 28, a base layer 14 on the collector layer 12 and a polysilicon emitter layer 16 on the base layer are contained. A base contact point extension layer 22 is provided, while being brought into contact with the base layer 14, and a top surface 62 thereof is put in a position lower than the lower surface of the emitter layer 16, so that the breakdown voltage of an emitter base is raised. A subcollector extension layer 30 in contact with the subcollector layer 26 is provided on the side opposite to the base ...

Подробнее
Номер записи: 1
04-08-1995 дата публикации

METHOD FOR FORMING SEMICONDUCTOR DEVICE AND INTEGRATED CIRCUIT DEVICE

Номер: JP0007201979A
Автор: GALLI CAROL, HSU LOUIS LU-CHEN, OGURA SEIKI, SHEPARD JOSEPH F
Принадлежит:

PURPOSE: To provide a shallow groove separation structure formed by a process having the reduced number of processing processes and heat balance. CONSTITUTION: A groove is packed with the liquid accumulation of an insulating semiconductor oxide, the heat treatment of the accumulated oxide is operated, and a thermal oxide layer 30 of high quality is formed on a boundary face between the accumulated oxide film and a substrate 12. This process applies a separation structure for reducing stresses and charge leakages. When a grinding stop layer 14 is provided on a semiconductor material main body, this structure can be easily made flat. The void of the accumulated oxide and a contaminant can be almost removed by self-aligned accumulation on the groove within the capacity of an opening on resist used for forming the groove. COPYRIGHT: (C)1995,JPO ...

Подробнее
Номер записи: 2
25-02-1994 дата публикации

INTEGRATED CIRCUIT CELL

Номер: JP0006053435A
Автор: HSIEH CHANG-MING, HSU LOUIS L C, OGURA SEIKI
Принадлежит:

PURPOSE: To provide a high-density DRAM cell array which is composed of a common-gate double-bit array, allowing conventional photolithographic process to be used. CONSTITUTION: A high-density DRAM cell array has very short-channel vertical gate transfer transistors, which can be made by the conventional photolithographic process. The DRAM array is composed of a common-gate double-bit array. Trench storage capacitors and vertical FETs face opposite common vertical gates and common substrate and can share bits and substrate contact through adjacent cells. COPYRIGHT: (C)1994,JPO ...

Подробнее
Номер записи: 3
04-03-1994 дата публикации

VERTICAL GATE FIELD-EFFECT TRANSISTOR AND MANUFACTURE THEREOF

Номер: JP0006061493A
Автор: HSIEH CHANG-MING, HSU LOUIS L C, OGURA SEIKI
Принадлежит:

PURPOSE: To provide a field-effect transistor(FET) having a vertical gate and a very thin channel sandwiched between a source layer and a drain layer. CONSTITUTION: An FET is formed on a silicon-on-insulator(SOI) substrate having an Si layer 12 acting as a first layer, e.g. source layer. A very thin channel 22 (e.g. of 0.1 μm) is formed by a low temp. epitaxial(LTE) process. A chemical vapor deposition polysilicon layer 28 forms a top layer (e.g. drain layer). An opening is etched through the three layers down to an insulation substrate and the opening wall is oxidized to form a gate oxide layer 33. Polysilicon fills the openings and is deposited to form a vertical gate 34. COPYRIGHT: (C)1994,JPO ...

Подробнее
Номер записи: 4
04-08-1995 дата публикации

MANUFACTURE OF SEMICONDUCTOR DEVICE

Номер: JP0007202013A
Автор: HSU LOUIS LU-CHEN, SHEPARD JOSEPH F, OGURA SEIKI
Принадлежит:

PURPOSE: To achieve the smallest horizontal size, without losing insulation effects by forming an insulating sidewall in an opening for an insulating body, and isolating a gate contact terminal from each contact terminal of a source and a drain. CONSTITUTION: A gate stack is constituted of a gate oxide layer 102, a polysilicon layer 110 and a nitride layer 120, and the doping of the polysilicon layer is carried out, and an interposed layer 124 is formed as an oxide layer as an etch stop material, and an opening is opened to the gate laminate in a region which is a field insulating part. Then, the opening is stopped on the oxide layer 102, and a sidewall formed at the side part insulates the gate stack from a strap connection working as a mask for implant of a source or a drain. Then, when the polysilicon layer is deposited in the opening and the nitride layer 120 is removed, an insulating layer 113 for protecting a polysilicon contact terminal 115 is grown, a gate 110 is exposed, and a ...

Подробнее
Номер записи: 5