Semiconductor packaging structure

The invention discloses a semiconductor packaging structure which comprises a packaging substrate and a groove area arranged in the middle of the packaging substrate, and the groove area is composed of a chip installation area and a filling area surrounding the chip installation area. A plurality of wiring bonding pads are arranged on the left side wall and the right side wall of the groove area where the filling area is located in a staggered mode and used for achieving stacked packaging of multiple chips, connecting contacts are formed on the bottom face of the packaging substrate through embedded transmission lines, and a plurality of semiconductor tube cores are installed in the chip installation area in a stacked mode and bonded to the wiring bonding pads through leads. The plurality of semiconductor tube cores are in signal communication through a coaxial transmission structure, the groove area is filled with an insulating sealing material, and the packaging substrate is packaged ...