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Применить Всего найдено 2. Отображено 2.
09-03-2017 дата публикации

SEMICONDUCTOR CHIP, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR PACKAGE INCLUDING SEMICONDUCTOR CHIP

Номер: KR1020170026700A
Автор: JO, A HYUN, KANG, SEUNG MO, BANG, YOON CHEOL, HONG, SEOK WOO
Принадлежит:

The present invention relates to a semiconductor chip, a manufacturing method thereof, and a semiconductor package including the same. More specifically, the semiconductor chip comprises: an integrated circuit on a substrate; a center pad which is electrically connected to the integrated circuit; a lower insulation structure which has a contact hole exposing the center pad, and includes a plurality of sequentially laminated lower insulation films; a conductive pattern which includes a contact portion filling the contact hole, a conductive line portion extending in one direction on the lower insulation structure, and a pad portion; and an upper insulation structure which has a first opening portion exposing the pad portion. The pad portion includes an inspection area and a bonding area, and the upper insulation structure includes an upper insulation film which covers the lower insulation structure and rewiring, and a polymer film on the upper insulation film. COPYRIGHT KIPO 2017 ...

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Номер записи: 1
09-03-2017 дата публикации

SEMICONDUCTOR CHIP, METHOD FOR FABRICATING SAME, AND SEMICONDUCTOR PACKAGE INCLUDING SAME

Номер: KR1020170026703A
Автор: CHOI, KYO SEON, KANG, SEUNG MO, KIM, SANG KI, BANG, YOON CHEOL
Принадлежит:

The present invention relates to a semiconductor chip, a method for fabricating the same, and a semiconductor package including the same, capable of performing an efficient process and improving a process difficulty level. More specifically, the semiconductor device includes: a substrate including a chip region provided therein with an integrated circuit, and a scribe lane region; a center pad electrically connected to the integrated circuit in the chip region; a boundary pad provided in the scribe lane region; a lower insulating structure provided on the chip region and the scribe lane region, and having a first contact hole for exposing the center pad; a first conductive pattern including a contact portion for filling the first contact hole, a conductive line portion extending in one direction on the lower insulating structure in the chip region, and a bonding pad portion; and an upper insulating structure having a first opening for exposing the bonding pad portion, and a second opening ...

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Номер записи: 2