Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same

An integrated circuit with a transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the transistor includes a source/drain including a lightly or heavily doped region adjacent the channel region, and an oppositely doped well extending under the channel region and a portion of the lightly or heavily doped region of the source/drain. The transistor also includes a channel extension, within the oppositely doped well, under the channel region and extending under a portion of the lightly or heavily doped region of the source/drain. 1. A transistor , comprising:a semiconductor substrate;a channel region recessed into said semiconductor substrate;a gate located over said channel region;a source/drain including a doped region adjacent said channel region;an oppositely doped well under said channel region and said doped region of said source/drain; anda channel extension, within said oppositely doped well, under at least a portion of said channel region.2. The transistor as recited in wherein said channel extension extends under a portion of said doped region of said source/drain by a channel extension length.3. The transistor as recited in wherein said channel extension is of like type to said oppositely doped well.4. The transistor as recited in wherein said channel extension has a doping concentration profile greater than a doping concentration profile of said oppositely doped well.5. The transistor as recited in wherein said channel extension has a doping concentration greater than a doping concentration profile of said channel region.6. The transistor as recited in further comprising another source/drain including a doped region adjacent an opposing side of said channel region.7. The transistor as recited in wherein said channel extension extends under at least a portion of said doped region of said ...

Receiver DC offset compensation

In a receiver, e.g. for GSM, dc offset in the baseband signal output of a mixer (3) is initially estimated by closing switches (12 and 13) low pass filtering (in 14) the baseband signal to produce an estimate of the dc offset, and storing the estimate in a register (16). Switches (12 and 13) are then opened. The stored estimate is subtracted from the baseband signal in a summing amplifier (5). Residual dc offset remaining, or arising later, in the baseband signal is estimated by a residual dc offset estimator (8), and the estimate is stored in a register (9). The estimates stored in registers (9 and 16) are summed in a summer (10) prior to subtraction from the baseband signal in amplifier (5) to produce a baseband signal substantially free of dc offset enabling both the full dynamic range of A/D converter (7) to be used, and satisfactory operation of demodulator (18).

Speed binning for dynamic and adaptive power control

A representative digital circuit of the invention has an on-chip, non- volatile memory, to which chip-specific speed-binning data that characterize performance of the digital circuit are written during production testing. During normal operation, the power controller that controls power-supply signals applied to the digital circuit reads the speed-binning data from the on-chip memory for use as input parameters for dynamic supply-voltage scaling, dynamic clock scaling, and/or adaptive power control that optimize (e.g., minimize) power consumption in the digital circuit. Advantageously over the prior art, the accuracy and efficiency of dynamic and/or adaptive power control arc improved because the chip-specific speed-binning data enable the power controller to better customize the power-management algorithm for the given digital circuit.

Dc offset correction circuit

The present invention relates to a radio receiver adapted for use in a time division multiple access (TDMA) system. The radio receiver includes DC compensator circuits configured to decrease the time required to cancel DC offset before received data bursts by DC coupling a radio frequency (RF) demodulator to a baseband channel. The radio receiver may also employ AC capacitive coupling having time modification so as to increase the AC coupled setting time and provide a low pole in a RF-to-Baseband interface.

Very low distortion amplifier

An operational amplifier and method for making same, with predetermined common mode voltage gain, adapted to form an amplifier and a voltage regulator. The predetermined common mode voltage gain allows for substantially reduced differential mode gain and wider operating bandwidth with little distortion, compared to amplifiers and voltage regulators using operational amplifiers of the prior art. Further, examples of operational amplifiers, having the reduced differential mode gain and predetermined common mode gain, are given for implementation in CMOS and bipolar technologies.

Recessible integrated pocket clip for mobile devices and the like

In one embodiment, an apparatus comprising a housing and a fastener, such as a clip (101, 201) for fastening the apparatus (100, 200) to an article of clothing. The housing (102, 202) has a recess (103, 203) formed therein, such that at least a portion of the fastener is adapted to fit within the recess. The fastener is adapted to travel slidably within the recess (103, 203) between a first position in which the fastener enables the apparatus (100, 200) to be fastened to an external object and a second position in which the fastener is stowed away.

Low-dropout regulator with startup overshoot control

The present invention provides an LDO regulator having a greatly improved overshoot characteristic through the use of an output voltage based feedback loop. More specifically, in the invention, one or more resistors in the divider network in a conventional LDO regulator is replaced with a variable resistor. By varying the resistance of the variable resistor as a function of the output voltage of the LDO regulator, the closed-loop gain of the LDO amplifier may be modulated in such a way as to reduce overshoot in the output voltage of the LDO regulator. In particular, the targeted final output voltage value may be arbitrarily lowered for a predetermined period of time, so that the LDO regulator output may rapidly reach a steady state voltage that is very close to the final desired regulating value without exceeding the final desired regulating value during regulator startup.

Versatile and intelligent power controller

The invention provides a monolithic, highly integrated power supply circuit capable of providing various voltages for circuits on an expansion card, either from a main supply source or an auxiliary supply source. The monolithic power supply circuit preferably includes two switching converters, two low-drop-out regulators, a standby regulator, a reset circuit, and a control circuit. An associated method for providing various voltages via a monolithic power supply circuit is also disclosed.

Software based thermal charging regulation loop

The present invention implements a software controlled thermal feedback system for battery charging circuitry in portable devices, specifically in cellular telephones. The charging hardware block is integrated into a mixed-signal analog base-band (ABB) circuit. In addition to standard function controls, integrated within the ABB are silicon temperature sensors used to monitor the temperature of any silicon components integrated on the ABB and detect any temperature change due to thermal heating. The temperature value is passed to the digital base band (DBB) circuit. Here, a microcontroller is programmed to perform power management functions relating to the ABB. Thermal control software, implemented on the DBB microcontroller, monitors the silicon temperature of the ABB and adjusts the power levels on the ABB accordingly to provide a controlled chip temperature.

Integrated current fault controller

A fault monitoring and management system integrates a fault controller with the power load functions within the power management device of a battery operated system. Multiple input load lines allow the fault controller to diagnose and disable defective or faulty power load functions that draw current from the system supply or battery. In addition, the fault monitor allows the system to stay operational if the fault is non-catastrophic to the critical functions.

Continuous tuning of switched capacitor circuits using DC-isolated tuning elements

Circuits having switched capacitors (C 1 , C 2 , C 3 ) are implemented with T-structures in which one (C 2 ) of the three capacitors in the T-structure is implemented with a buffer amplifier (402) configured to receive a control signal (e.g., a control voltage) and to apply a buffered control signal to an active device (404) having a capacitance that is dependent on the control signal level. In one embodiment, the control signal is a control voltage, the active device is a varactor diode, and the circuit is a ladder filter having one or more switched capacitors, each of which is implemented using the T-structure of the present invention. Under the present invention, continuously tunable circuits can be implemented with discrete elements where the circuits can be tuned by changing the control signal in one or more of the switched capacitors, without having to provide a continuously tunable clock.

多重出力デジタル−アナログ・コンバータ

(57)【要約】 【課題】 複数のデジタル出力を変換できるコンバータ を提供すること。 【解決手段】 インピーダンス列には抵抗器などの複数 の直列に結合されたインピーダンスが含まれている。第 一の複数のスイッチは第一の出力ノードと対応するひと つの中間タップの間に結合されている。第一の選択回路 が第一のデジタル的にコード化された信号を受信し、第 一の複数の各スイッチに結合されている。上記第一の選 択回路は提供される第一のデジタル的にコード化された 信号に基づいて第一のスイッチ群を所定の状態に切り替 えて第一のアナログ出力を発生する。第二の複数のスイ ッチは第二の出力ノードと対応するひとつの中間タップ との間に結合されている。第二の選択回路は上記複数の スイッチ群の各スイッチに結合されて、提供される第二 のデジタル的にコード化された信号に応じて第二のスイ ッチ群のいくつかのスイッチを選択的に所定の状態に切 り替えて第二のアナログ出力を発生する。

Method and apparatus for an over-voltage detection circuit

A method and apparatus for embedding over-limit voltage detector and recording mechanisms on the silica wafer of integrated circuits to detect, protect and record voltage overages of pre-set voltage limits is presented. A detector circuit and a recorder circuit are placed in series or in parallel on the electrical connections between the integrated circuit devices and the voltage pins connected to outside power sources. When a voltage source is connected and an overvoltage condition is detected, the detector circuit short-circuits the connection while the recorder circuit records the event for later investigation.

Abtast- und Verriegelungsschaltung für Schmelzsicherungsabgleichverbindungen auf einem Chip

On-chip trim link sensing and latching circuit for fuse links

Abtast- und Verriegelungsschaltung für Schmelzsicherungsabgleichverbindungen auf einem Chip

集積回路

(57)【要約】 【課題】 はしご形フィルタのようなスイッチトキャパ シタを有する回路を、連続的に調整可能なように実現す る。 【解決手段】 スイッチトキャパシタを有する集積回路 において、スイッチトキャパシタは、ＤＣ絶縁可変キャ パシタとして実現される。ＤＣ絶縁可変キャパシタは、 ３個のキャパシタを有するＴ構造として実現され、３個 のキャパシタのうちの１つは、バッファ増幅器とともに 実現される。このバッファ増幅器は、制御信号を受け取 り、バッファした制御信号のレベルに依存するキャパシ タンスを有する能動デバイスに、バッファした制御信号 を入力する。例えば、Ｔ構造のキャパシタＣ 2 は、電圧 制御バッファ４０２およびバラクタダイオード４０４を 用いて実現される。バッファ４０２は、絶縁を提供し、 制御電圧をあらかじめ調整あるいは増減する高インピー ダンス出力バッファである。