Reducing Distortion Using Joint Storage

A method for data storage includes predefining an order of programming a plurality of analog memory cells that are arranged in rows. The order specifies that for a given row having neighboring rows on first and second sides, the memory cells in the given row are programmed only while the memory cells in the neighboring rows on at least one of the sides are in an erased state, and that the memory cells in the given row are programmed to assume a highest programming level, which corresponds to a largest analog value among the programming levels of the cells, only after programming all the memory cells in the given row to assume the programming levels other than the highest level. Data is stored in the memory cells by programming the memory cells in accordance with the predefined order.

INDEPENDENT MANAGEMENT OF DATA AND PARITY LOGICAL BLOCK ADDRESSES

A data storage method includes identifying, in a set of data items associated with respective logical addresses for storage in a memory, a first subset of the logical addresses associated with the data items containing application data, and a second subset of the logical addresses associated with the data items containing parity information that has been calculated over the application data. The data items associated with the first identified subset are stored in one or more first physical memory areas of the memory, and the data items associated with the second identified subset are stored in one or more second physical memory areas of the memory, different from the first physical memory areas. A memory management task is performed independently in the first physical memory areas and in the second physical memory areas. 1. A data storage method , comprising:in a set of data items associated with respective logical addresses for storage in a memory, identifying a first subset of the logical addresses associated with the data items containing application data, and a second subset of the logical addresses associated with the data items containing parity information that has been calculated over the application data;storing the data items associated with the first identified subset in one or more first physical memory areas of the memory, and storing the data items associated with the second identified subset in one or more second physical memory areas of the memory, different from the first physical memory areas; andperforming a memory management task independently in the first physical memory areas and in the second physical memory areas.2. The method according to claim 1 , wherein performing the memory management task comprises assigning a first over-provisioning overhead to the first physical memory areas claim 1 , and assigning a second over-provisioning overhead claim 1 , different from the first over-provisioning overhead claim 1 , to the second physical memory ...

REDUNDANT STORAGE IN NON-VOLATILE MEMORY BY STORING REDUNDANCY INFORMATION IN VOLATILE MEMORY

A method for data storage includes storing two or more data items in a non-volatile memory. Redundancy information is calculated over the data items, and the redundancy information is stored in a volatile memory. Upon a failure to retrieve a data item from the non-volatile memory, the data item is reconstructed from remaining data items stored in the non-volatile memory and from the redundancy information stored in the volatile memory. 1. A method for data storage , comprising:storing two or more data items in a non-volatile memory;calculating redundancy information over the data items, and storing the redundancy information in a volatile memory; andupon a failure to retrieve a data item from the non-volatile memory, reconstructing the data item from remaining data items stored in the non-volatile memory and from the redundancy information stored in the volatile memory.2. The method according to claim 1 , wherein calculating the redundancy information comprises calculating an exclusive-OR (XOR) over the data items claim 1 , and wherein reconstructing the data item comprises calculating the XOR over the remaining data items and the redundancy information.3. The method according to claim 1 , wherein calculating the redundancy information comprises encoding the data items with an Error Correction Code (ECC).4. The method according to claim 1 , wherein the data items are defined by respective physical storage locations in the non-volatile memory.5. The method according to claim 1 , wherein the data items are defined by respective logical addresses that are mapped to respective physical storage locations in the non-volatile memory in accordance with a logical-to-physical address translation scheme.6. The method according to claim 1 , wherein storing the redundancy information comprises protecting the redundancy information stored in the volatile memory from interruption of electrical power supply.7. The method according to claim 6 , wherein protecting the redundancy ...

Efficient Readout from Analog Memory Cells Using Data Compression

A method for data storage includes storing data in a group of analog memory cells by writing respective input storage values to the memory cells in the group. After storing the data, respective output storage values are read from the analog memory cells in the group. Respective confidence levels of the output storage values are estimated, and the confidence levels are compressed.

ADAPTIVE MAPPING OF LOGICAL ADDRESSES TO MEMORY DEVICES IN SOLID STATE DRIVES

A method for data storage includes receiving data items associated with respective logical addresses for storage in a memory that includes multiple memory units. Respective estimates of a performance characteristic are obtained for the multiple memory units. A mapping, which maps the logical addresses to respective physical storage locations in the multiple memory units, is adapted based on the estimates so as to balance the performance characteristic across the memory units. The data items are stored in the physical storage locations in accordance with the adapted mapping. 1. A method for data storage , comprising:receiving data items associated with respective logical addresses for storage in a memory that includes multiple memory units;obtaining respective estimates of a performance characteristic for the multiple memory units;based on the estimates, adapting a mapping that maps the logical addresses to respective physical storage locations in the multiple memory units, so as to balance the performance characteristic across the memory units; andstoring the data items in the physical storage locations in accordance with the adapted mapping.2. The method according to claim 1 , wherein adapting the mapping comprises modifying a total number of the logical addresses that are mapped to a given memory unit.3. The method according to claim 1 , wherein storing the data items comprises distributing the data items among the memory units in accordance with a weighted Round-Robin scheduling scheme that assigns respective weights to the memory units claim 1 , and wherein adapting the mapping comprises modifying one or more of the weights.4. The method according to claim 3 , wherein modifying the weights comprises assigning to a given memory unit different first and second weights for respective different first and second types of memory access commands.5. The method according to claim 1 , wherein obtaining the estimates comprises evaluating the performance characteristic for ...

Adaptive Estimation of Memory Cell Read Thresholds

A method for operating a memory () that includes a plurality of analog memory cells () includes storing data in the memory by writing first storage values to the cells. Second storage values are read from the cells, and a Cumulative Distribution Function (CDF) of the second storage values is estimated. The estimated CDF is processed so as to compute one or more thresholds. A memory access operation is performed on the cells using the one or more thresholds. 149-. (canceled)50. A method , comprising:receiving data to be stored in a memory, wherein the memory includes a plurality of data storage cells;writing first storage values in the plurality of data storage cells;reading second storage values from the plurality of data storage cells;determining a number of data memory cells of the plurality of data memory cells associated with a plurality of programming levels dependent upon the read second storage values;estimating a probability density function (PDF) for each programming level of the plurality of programming levels;scaling each PDF dependent upon the determined number of data storage cells;integrating the plurality of PDFs to produce a cumulative distribution function (CDF);computing one or more thresholds dependent upon the CDF;reading third storage values from the plurality of data storage cells;comparing the third storage values to the computed one or more thresholds; andgenerating data bits dependent upon the comparison.51. The method of claim 50 , wherein each data storage cell of the plurality of data storage cells comprises an analog memory cell.52. The method of claim 50 , wherein each data storage cell of the plurality of data storage cells comprises a multi-bit analog memory cell.53. The method of claim 50 , wherein reading second storage values comprises converting an electrical charge into digital samples.54. The method of claim 50 , wherein writing first storage values comprises encoding the received data using an error correction code (ECC).55. An ...

Optimized execution of interleaved write operations in solid state drives

A method for data storage includes receiving a plurality of data items for storage in a memory, including at least first data items that are associated with a first data source and second data items that are associated with a second data source, such that the first and second data items are interleaved with one another over time. The first data items are de-interleaved from the second data items, by identifying a respective data source with which each received data item is associated. The de-interleaved first data items and the de-interleaved second data items are stored in the memory.

METHOD AND APPARATUS FOR TESTING A DEVICE-UNDER-TEST

A method for testing a device-under-test includes receiving, from at least one test channel circuit dedicated to communicate with an input/output pin of the device-under-test by means of at least one hardware resource, at least one logical control command describing a desired operation of the at least one hardware resource, and converting, by means of a resource controller, the at least one logical control command into at least one dedicated control command for the at least one hardware resource, wherein the at least one dedicated control command is adapted to be received by a physical implementation of the at least one hardware resource. 1. An apparatus for testing a device , the apparatus comprising:a test channel circuit operable to communicate with an input/output pin of the device using a hardware resource; anda resource controller coupled to the test channel circuit and operable to receive a logical control command describing a requested operation of the hardware resource, wherein the resource controller is operable to convert the logical control command into a dedicated control command for the hardware resource, and wherein further the dedicated control command is adapted to be received by a physical implementation of the hardware resource.2. The apparatus according to claim 1 , wherein the logical control command is generated by the test channel circuit and is independent from the physical implementation of the hardware resource.3. The apparatus according to claim 1 , wherein the test channel circuit comprises:a digital test pattern generator operable for generating a digital test pattern; anda time formatter operable for associating a timing to binary values of the digital test pattern.4. The apparatus according to claim 1 , wherein the test channel circuit comprises:a digital test pattern comparator operable for comparing a test pattern received from the input/output pin with an expected digital test pattern.5. The apparatus according to claim 1 , wherein ...

AUTOMATIC DEFECT MANAGEMENT IN MEMORY DEVICES

A method for data storage in a memory including multiple memory cells arranged in blocks, includes storing first and second pages in respective first and second groups of the memory cells within a given block of the memory. A pattern of respective positions of one or more defective memory cells is identified in the first group. The second page is recovered by applying the pattern identified in the first group to the second group of the memory cells. 1. A method comprising:a processor identifying, within a memory device including a plurality of multilevel memory cells, defective memory cells;retaining information corresponding to the defective memory cells;the processor skipping the defective memory cells upon writing to and reading from the memory device based upon the information corresponding to the defective memory cells.2. The method of claim 1 , wherein identifying the defective memory cells includes the processor performing memory diagnostics on the memory device.3. The method of claim 1 , wherein identifying the defective memory cells includes the processor performing normal memory operations on the memory device.4. The method of claim 1 , wherein identifying the defective memory cells includes an external testing unit performing diagnostics on the memory device.5. The method of claim 1 , wherein retaining information corresponding to the defective memory cells includes the processor storing the information within a specific segment of the memory device.6. The method of claim 1 , wherein retaining information corresponding to the defective memory cells includes the processor storing the information within another memory device.7. The method of claim 1 , wherein retaining information corresponding to the defective memory cells includes an external testing unit providing the information to the processor.8. The method of claim 1 , wherein the processor skipping the defective memory cells includes the processor writing a received data segment to a grouping of ...

EFFICIENT ENFORCEMENT OF COMMAND EXECUTION ORDER IN SOLID STATE DRIVES

A method in a storage device includes receiving from a host storage commands for execution in a non-volatile memory of the storage device. At least a subset of the storage commands are to be executed in accordance with an order-of-arrival in which the storage commands in the subset are received. The received storage commands are executed in the non-volatile memory in accordance with internal scheduling criteria of the storage device, which permit deviations from the order-of-arrival, but such that execution of the storage commands in the subset reflects the order-of-arrival to the host. 1. A method , comprising:in a storage device, receiving from a host storage commands for execution in a non-volatile memory of the storage device, wherein at least a subset of the storage commands are to be executed in accordance with an order-of-arrival in which the storage commands in the subset are received; andexecuting the received storage commands in the non-volatile memory in accordance with internal scheduling criteria of the storage device, which permit deviations from the order-of-arrival, but such that execution of the storage commands in the subset reflects the order-of-arrival to the host.2. The method according to claim 1 , wherein executing the storage commands comprises permitting unblocked execution of the storage commands other than the subset concurrently with execution of the storage commands in the subset.3. The method according to claim 1 , wherein the non-volatile memory comprises multiple memory devices claim 1 , and wherein executing the storage commands in accordance with the internal scheduling criteria comprises scheduling the storage commands for execution across the multiple memory devices.4. The method according to claim 1 , wherein receiving the storage commands comprises receiving from the host an indication that distinguishes the storage commands in the subset from the storage commands other than the subset.5. The method according to claim 4 , ...

FAST EXECUTION OF FLUSH COMMANDS USING ADAPTIVE COMPACTION RATIO

A method includes receiving one or more storage commands and at least one flush command in a storage device, which includes a non-volatile memory and a volatile buffer for buffering data received for storage in the non-volatile memory. The flush command instructs the storage device to commit the data buffered in the volatile buffer to the non-volatile memory. The storage commands are executed in accordance with a first storage rule. The flush command is executed in accordance with a second storage rule having smaller latency relative to the first storage rule. 1. A method , comprising:in a storage device, which includes a non-volatile memory and a volatile buffer for buffering data received for storage in the non-volatile memory, receiving one or more storage commands and at least one flush command, which instructs the storage device to commit the data buffered in the volatile buffer to the non-volatile memory;executing the storage commands in accordance with a first storage rule; andexecuting the flush command in accordance with a second storage rule having smaller latency relative to the first storage rule.2. The method according to claim 1 , wherein executing the flush command in accordance with the second storage rule comprises limiting a number of programming operations to be performed in the non-volatile memory per each compaction operation to a predefined ratio claim 1 , and wherein executing the storage commands in accordance with the first storage rule comprises permitting the number to exceed the predefined ratio.3. The method according to claim 2 , wherein executing the storage commands in accordance with the first storage rule comprises enforcing an alternative ratio claim 2 , which is larger than the predefined ratio.4. The method according to claim 2 , wherein limiting the number of programming operations per compaction operation comprises modifying the predefined ratio depending on a count of free memory blocks that are available in the non-volatile ...

Virtual Mirror with Automatic Zoom Based on Vehicle Sensors

In one approach, a method includes: displaying, to a user of a first vehicle, image data obtained using a first field of view of a camera of the first vehicle, where the camera collects the image data for objects located outside of the first vehicle; detecting, by at least one processing device of the first vehicle, a second vehicle; determining, by the one processing device, whether the second vehicle is within a predetermined region relative to the first vehicle; and in response to determining that the second vehicle is within the predetermined region, displaying image data obtained using a second field of view of the camera. 1. A system comprising:a camera mounted on a first vehicle, wherein the camera is configured to collect image data, and to adjust a field of view of the camera, wherein the field of view can be adjusted to provide at least a first field of view and a second field of view, and wherein the first field of view is narrower than the second field of view;at least one processing device; and determine whether the first vehicle is traveling faster than a predetermined speed;', 'determine whether a vehicle is present on a side of the first vehicle; and', 'in response to determining that the first vehicle is traveling faster than the predetermined speed and determining that no vehicle is present on the side of the first vehicle, adjust the camera to the first field of view., 'memory containing instructions configured to instruct the at least one processing device to2. The system of claim 1 , further comprising:a display screen positioned for viewing by a person in the first vehicle;wherein the instructions are further configured to instruct the at least one processing device to, in response to determining that the first vehicle is traveling faster than the predetermined speed, present images on the display screen based on data collected using the first field of view of the camera.3. The system of claim 1 , further comprising:a display screen located in ...

Memory Mapping for Hibernation

A computing system has a processing device (e.g., CPU, FPGA, or GPU) and memory regions (e.g., in a DRAM device) used by the processing device during normal operation. The computing system is configured to: monitor use of the memory regions in volatile memory; based on monitoring the use of the memory regions, identify at least one of the memory regions of the volatile memory; initiate a hibernation process; and during the hibernation process, copy data stored in the identified memory regions to non-volatile memory. 1. An apparatus comprising:volatile memory;non-volatile memory; and receive a request from a first process associated with a first memory region of the volatile memory;', 'use the first memory region to store first data, wherein the first data is generated during execution of the first process;', 'associate a respective flag to memory regions of the volatile memory, the respective flag identifying each memory region for copying or not copying, wherein a first flag is associated to the first memory region;', 'detect an event associated with the volatile memory;', 'in response to detecting the event, determine that the first memory region is associated to the first flag; and', 'in response to determining that the first memory region is associated to the first flag, copy the first data stored in the first memory region to the non-volatile memory., 'at least one processing device configured to2. The apparatus of claim 1 , wherein the event is an impending loss of power to the volatile memory.3. The apparatus of claim 1 , wherein the event is initiation of a hibernation process.4. The apparatus of claim 1 , wherein the request includes a memory characterization claim 1 , and the first flag is associated to the first memory region based on the memory characterization.5. The apparatus of claim 1 , wherein the first flag is associated to the first memory region based on usage of the first memory region by the first process.6. The apparatus of claim 1 , wherein ...

Detecting Road Conditions Based on Braking Event Data Received from Vehicles

Data is received regarding vehicle braking events, each event occurring on one of a plurality of vehicles, and each event associated with a location. A determination is made that the braking events correspond to a pattern. Based on determining that the braking events correspond to the pattern, a first location is identified. In response to identifying the first location, at least one action is performed. 1. An apparatus comprising:at least one processor; and monitor a respective operating status for each of a plurality of autonomous vehicles, the monitoring including receiving data regarding objects detected by the vehicles;', 'determine that a first vehicle of the vehicles is failing to properly detect objects when operating in an autonomous driving mode; and', 'in response to determining that the first vehicle is failing to properly detect objects, send a communication to the first vehicle, the communication causing the first vehicle to deactivate the autonomous driving mode of the first vehicle., 'memory storing instructions configured to instruct the at least one processor to2. The apparatus of claim 1 , wherein the communication further causes updating firmware of a controller of the first vehicle.3. The apparatus of claim 1 , wherein the first vehicle comprises a storage device configured to store an artificial neural network (ANN) model used to detect objects when operating in the autonomous driving mode.4. The apparatus of claim 3 , wherein the instructions are further configured to instruct the at least one processor to:in response to determining that the first vehicle is failing to properly detect objects, send updated firmware to the first vehicle;wherein the updated firmware is stored in the storage device, and the updated firmware is used by the first vehicle to update the ANN model.5. The apparatus of claim 3 , wherein the ANN model is trained using training data claim 3 , and the training data comprises data collected by sensors of the autonomous ...

Sensor Fusion to Determine Reliability of Autonomous Vehicle Operation

A method for an autonomous vehicle includes: receiving first object data from a first sensor module; receiving second object data from a second sensor module; comparing the first object data to the second object data; determining, based on comparing the first object data to the second object data, whether the first object data corresponds to the second object data; and in response to determining that the first object data does not correspond to the second object data, performing an action for the autonomous vehicle. 1. A system comprising:a central processing device configured to receive object data provided by sensors of a vehicle; and receive first object data based on a first object detection by a first sensor of the vehicle;', 'receive second object data based on a second object detection by a second sensor of the vehicle;', 'make a comparison of the first object data to the second object data, the comparison comprising performing a correlation of the first object data to the second object data;', 'determine, based on the comparison of the first object data to the second object data, whether the first object data corresponds to the second object data; and', 'in response to determining that the first object data does not correspond to the second object data, change a configuration of at least one of the first sensor or the second sensor., 'memory storing instructions configured to instruct the central processing device to2. The system of claim 1 , wherein the instructions are further configured to instruct the central processing device to:in response to determining that the first object data does not correspond to the second object data, perform a diagnostic test of at least one of the first sensor or the second sensor;wherein the configuration of the first sensor or the second sensor is changed based on the diagnostic test.3. The system of claim 2 , wherein the instructions are further configured to instruct the central processing device to determine claim 2 , ...

DYNAMIC ADAPTATION OF AUTOMOTIVE AI PROCESSING POWER AND ACTIVE SENSOR DATA

Systems, methods, and apparatus related to dynamically adjusting sensing and/or processing resources of a vehicle. In one approach, sensor data is collected by sensing devices of the vehicle. A controller of the vehicle uses the sensor data to control one or more functions of the vehicle. The controller evaluates the sensor data to determine a context of operation (e.g., weather, lighting, and/or traffic) for the vehicle. Based on the context of operation, the controller adjusts the operation of one or more of the sensing or processing devices in real-time during operation of the vehicle. In one example, the adjustment reduces power consumption by the vehicle. 1. A system comprising:at least one sensing device to generate sensor data;a non-volatile memory device to store the generated sensor data;at least one artificial neural network (ANN) processor to process the sensor data to provide at least one output, wherein at least one function of a vehicle is controlled based on the at least one output; and evaluate, based on the stored sensor data, a context of operation of the vehicle; and', 'adjust, based on evaluating the context of operation, at least one operating characteristic for one or more of the at least one sensing device or the at least one ANN processor., 'at least one memory containing instructions configured to instruct the at least one processing device to2. The system of claim 1 , wherein adjusting the at least one operating characteristic comprises adjusting at least one of a number of sensing devices that are in an active state claim 1 , a resolution for one or more sensing devices claim 1 , or a rate at which frames are generated by a sensing device.3. The system of claim 1 , wherein adjusting the at least one operating characteristic comprises adjusting a processing capability of the ANN processor.4. The system of claim 1 , further comprising a power supply that provides power to at least one of the sensing device or the ANN processor claim 1 , ...

MASTER SLAVE MANAGED MEMORY STORAGE

Systems, methods, and apparatus related to data storage devices. In one approach, a string of storage devices are chained together and coupled to a host device for storing data. Each storage device may, for example, execute read, write, or erase commands received from the host device. Each storage device in the chain is a master to the next storage device in the chain, and each storage device is a slave to the previous storage device in the chain. In one example, the host device is a system-on-chip. The chain can manage itself and is seen as a single large storage space to the host device. The host device does not require knowledge about each individual storage device, and each storage device does not require knowledge about the other storage devices in the chain (other than whether the storage device is attached to another storage device on its master port). 1. A method comprising:receiving, from a host device by a first storage device, a first request regarding a first storage capacity of the first storage device;in response to the first request, determining, by the first storage device, that a second storage device is coupled to the first storage device; in response to receiving the second request, determine that no storage device, other than the first storage device, is coupled to the second storage device; and', 'in response to determining that no storage device is coupled to the second storage device, send the second storage capacity to the first storage device;, 'in response to determining that the second storage device is coupled to the first storage device, sending, to the second storage device, a second request regarding a second storage capacity of the second storage device, wherein the second storage device is configured toreceiving, by the first storage device from the second storage device, the second storage capacity;adding the first storage capacity and the second storage capacity to provide a total storage capacity; andin response to the first ...

Vehicle Navigation Using Object Data Received from Other Vehicles

A method includes: receiving, by a computing device, object data regarding a first object detected by a first vehicle, the object data including an object type and a location; storing the object data; generating, based on the object data, navigation data; and sending the navigation data to a second vehicle, the navigation data for use by the second vehicle to control navigation. 1. A method comprising:receiving, by at least one processor, object data regarding a first object detected by at least one sensor of a first vehicle;generating, by the at least one processor and based on the object data, navigation data;determining, by the at least one processor based on comparing a first location of the first vehicle to a second location of a second vehicle, that the first vehicle is within a predetermined distance of the second vehicle; andin response to determining that the first vehicle is within the predetermined distance, sending, the navigation data to the second vehicle, the navigation data for use by a controller of the second vehicle to control navigation.2. The method of claim 1 , wherein the first object is beyond a detection range of the second vehicle when the first vehicle sends the object data to the server.3. The method of claim 1 , wherein the first object is greater than a predetermined distance from the second vehicle when the object data is received from the first vehicle.4. The method of claim 1 , wherein the first object is a traffic sign claim 1 , a traffic light claim 1 , a road lane claim 1 , or a physical structure.5. The method of claim 1 , wherein the navigation data includes at least a portion of the object data.6. The method of claim 1 , further comprising receiving object data regarding a second object detected by at least one sensor of a third vehicle claim 1 , wherein the navigation data includes the object data regarding the second object.7. The method of claim 1 , further comprising determining claim 1 , by the at least one processor claim ...

TRIMS CORRESPONDING TO LOGICAL UNIT QUANTITY

Instructions can be executed to determine a quantity of logical units that are part of a memory device. The instructions can be executed to operate the logical units with a programming time sufficient to provide a required throughput for storage of time based telemetric sensor data received from a host. The instructions can be executed to operate the logical units with a trim that correspond to the programming time. 1. A non-transitory computer-readable storage medium comprising instructions that , when executed by a processing device , cause the processing device to:determine a quantity of logical units that comprise a memory device;operate the quantity of logical units with a programming time sufficient to provide a required throughput for storage of time based telemetric sensor data received from a host; andoperate the quantity of logical units with one of a plurality of trims that correspond to the programming time.2. The medium of claim 1 , further comprising instructions to:select the programming time from a plurality of programming times that the memory device is capable of using; andselect a slowest one of the plurality of programming times that is sufficient to provide the required throughput.3. The medium of claim 1 , wherein each of the plurality of trims that correspond to the programming time also correspond to a different performance target.4. The medium of claim 3 , further comprising instructions to select the one of the plurality of trims based on a desired one of the different performance targets.5. The medium of claim 1 , further comprising instructions to select the one of the plurality of trims from a library of trims stored with correspondence to programming times.6. The medium of claim 1 , further comprising instructions to determine the required throughput based on input from the host.7. The medium of claim 1 , further comprising instructions to receive an input defining the required throughput.8. The medium of claim 1 , wherein the ...

SEPARATE PARTITION FOR BUFFER AND SNAPSHOT MEMORY

A system includes a processing device and trigger circuitry to signal the processing device responsive, at least in part, based on a determination that a trigger event has occurred. The system can further include a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion having a first endurance characteristic and a first reliability characteristic associated therewith. The memory device can further include a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can have a second endurance characteristic and a second reliability characteristic associated therewith. The processing device can perform operations including writing received data sequentially to the cyclic buffer partition portion and writing, based at least in part on the determination that the trigger event has occurred, data from the cyclic buffer partition portion to the snapshot partition portion. 1. A system comprising:a processing device;trigger circuitry to signal the processing device responsive, at least in part, based on a determination that a trigger event has occurred; and{'claim-text': ['a cyclic buffer partition portion having a first endurance characteristic and a first reliability characteristic associated therewith; and', {'claim-text': ['writing received data sequentially to the cyclic buffer partition portion; and', 'writing, based at least in part on the determination that the trigger event has occurred, data from the cyclic buffer partition portion to the snapshot partition portion.'], '#text': 'a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors, the snapshot partition portion having a second endurance characteristic and a second reliability characteristic associated therewith, wherein the processing device is to perform operations comprising:'}], '#text': 'a memory device communicatively ...

PARTITIONS WITHIN SNAPSHOT MEMORY FOR BUFFER AND SNAPSHOT MEMORY

A system includes a processing device and a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion and a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can further include a first sub-partition portion having a first programming characteristic and a second sub-partition portion having a second programming characteristic. The processing device can write received data sequentially to the cycle buffer partition portion and write, based at least in part on a determination that a trigger event has occurred, data from the cyclic buffer partition portion to the first sub-partition portion or the second sub-partition portion, or both. 1. A system comprising:a processing device; and{'claim-text': ['a cyclic buffer partition portion; and', {'claim-text': ['a first sub-partition portion having a first programming characteristic; and', 'a second sub-partition portion having a second programming characteristic;'], '#text': 'a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors, the snapshot partition portion further comprising:'}], '#text': 'a memory device communicatively coupled to the processing device and comprising:'}{'claim-text': ['writing received data sequentially to the cyclic buffer partition portion; and', 'writing, based at least in part on a determination that a trigger event has occurred, data from the cyclic buffer partition portion to the first sub-partition portion or the second sub-partition portion, or both.'], '#text': 'wherein the processing device is to perform operations comprising:'}2. The system of claim 1 , wherein:the memory device is further coupled to a primary power supply; andthe hold-up capacitors are a secondary power supply;{'claim-text': 'writing the data from the cyclic partition portion to the first sub-partition portion, or the second sub- ...

PARTITIONED MEMORY HAVING ERROR DETECTION CAPABILITY

A memory component comprises a cyclic buffer partition portion and a snapshot partition portion. In response to receiving a signal that a trigger event has occurred, a processing device included in the memory component performs an error correction operation on a portion of data stored in the cyclic buffer partition portion, copies the data stored in the cyclic buffer partition portion to the snapshot partition portion in response to the error correction operation being successful, and sends the data stored in the cyclic buffer partition portion to a processing device operatively coupled to the memory component in response to the error correction operation not being successful. 1. A system , comprising:a memory component comprising a cyclic buffer partition portion and a snapshot partition portion; and{'claim-text': ['perform an error correction operation on a portion of data stored in the cyclic buffer partition portion;', 'copy the data stored in the cyclic buffer partition portion to the snapshot partition portion without transferring the data to or from a processing device operatively coupled to the memory component in response to the error correction operation being successful; and', 'send the data stored in the cyclic buffer partition portion to the processing device operatively coupled to the memory component in response to the error correction operation not being successful.'], '#text': 'a processing device included in the memory component to, in response to receiving a signal that a trigger event has occurred:'}2. The system of claim 1 , wherein the portion of data on which the error correction operation is performed comprises less than all of the data stored in the cyclic buffer partition portion.3. The system of claim 1 , wherein the data copied to the snapshot partition portion comprises all of the data stored in the cyclic buffer partition portion.4. The system of claim 1 , wherein the processing device included in the memory component is to:generate ...

THRESHOLD VOLTAGE DISTRIBTUTION ADJUSTMENT FOR BUFFER

A method includes writing received data sequentially to a particular location of a cyclic buffer of a memory device according to a first set of threshold voltage distributions. The method further includes performing a touch up operation on the particular location by adjusting the first set of threshold voltage distributions of the data to a second set of threshold voltage distributions in response to a determination that a trigger event has occurred. The second set of threshold voltage distributions can have a larger read window between adjacent threshold voltage distributions of the second set than that of the first set of threshold voltage distributions. 1. A method , comprising:writing, within a first set of threshold voltage distributions, received data sequentially to a particular location of a memory device comprising a cyclic buffer; and 'performing a touch up operation on the particular location that adjusts the first set of threshold voltage distributions to a second set of threshold voltage distributions having a larger read window between adjacent threshold voltage distributions than that of the first set of threshold voltage distributions.', 'in response to a determination that a trigger event has occurred2. The method of claim 1 , wherein the particular location is flagged as the cyclic buffer; andwherein the method further comprises, subsequent to performing the touch up operation on the particular location, flagging the particular location as a snapshot.3. The method of claim 1 , further comprising: retrieving data associated with the different trigger event to a processing device; and', 'writing, within the adjusted second set of threshold voltage distributions, the data back to a different location;', 'flagging the different location as a snapshot., 'in response to the determination that a different trigger event has occurred4. The method of claim 1 , further comprising operating memory cells of the cyclic buffer in a single-level cell (SLC) mode ...

Protection against unintended content change in dram during standby mode

Systems, methods, and apparatus related to protecting data stored in volatile memory of a computing system during a standby mode. In one approach, a first signature is generated for data stored in volatile memory. In some cases, the stored data may include sensor data obtained from one or more sensors of a vehicle, mobile device or other electronic device. The first signature is stored in a non-volatile memory device, and then the computing system enters the standby mode. Subsequently, after exiting the standby mode, a second signature is generated for the data stored in the volatile memory. The first signature is read from the non-volatile memory device and compared to the second signature. A signature mismatch indicates that an unintended change has occurred in the stored data during the standby mode. One or more remedial actions are performed by the computing system in response to this signature mismatch.

VALIDATION OF DRAM CONTENT USING INTERNAL DATA SIGNATURE

Systems, methods, and apparatus related to validating data stored in a memory system. In one approach, a DRAM stores data for a host device. A controller that manages the DRAM receives a command from the host device to generate a signature. The controller also receives data from the host device that indicates a region of the DRAM. In response to receiving the command, the controller reads data from the indicated region. A signature is generated by the controller based on the data read from the indicated region. The generated signature is sent to the host device in response to the command. 1. A system comprising:a dynamic random access memory (DRAM) configured to store data for a host device; and{'claim-text': ['receive, from the host device, a command to generate a signature, and data indicating a region of the DRAM for which the signature is to be generated;', 'in response to receiving the command, read data from the indicated region of the DRAM;', 'generate, based on the data read from the indicated region of the DRAM, the signature; and', 'store the signature in a first register;', 'in response to generating the signature, update a value stored in a second register from a first value to a second value, wherein the first value indicates that the signature has not been generated, and the second value indicates that the signature has been generated.'], '#text': 'a controller configured to:'}2. The system of claim 1 , wherein the second value further indicates that the signature is stored in the first register.3. The system of claim 1 , further comprising an address register configured to receive an address from the host device claim 1 , wherein the address includes at least a portion of the data indicating the region of the DRAM.4. The system of claim 1 , wherein:the DRAM comprises banks of memory arrays;the data indicating the region of the DRAM comprises a range for a first bank including a starting row and an ending row; andreading the data comprises reading data ...

THRESHOLD VOLTAGE BASED ON PROGRAM/ERASE CYCLES

A method includes during a first portion of a service life of a memory device, programming at least one memory cell of the memory device to a first threshold voltage corresponding to a desired data state. The method can include during a second portion of the service life of the memory device subsequent to the first portion of the service life of the memory device, programming at least one memory cell of the memory device to a second threshold voltage corresponding to the desired data state. The second threshold voltage can be different than the first threshold voltage. 1. A method , comprising:during a first portion of a service life of a memory device, programming at least one memory cell of the memory device to a first threshold voltage corresponding to a desired data state; andduring a second portion of the service life of the memory device subsequent to the first portion of the service life of the memory device, programming at least one memory cell of the memory device to a second threshold voltage corresponding to the desired data state,wherein the second threshold voltage is different than the first threshold voltage.2. The method of claim 1 , wherein the desired data state is a programmed state claim 1 , andwherein the second threshold voltage is greater than the first threshold voltage.3. The method of claim 2 , further comprising:during the first portion of the service life, programming the at least one memory cell to a third threshold voltage corresponding to an erased state; andduring the second portion of the service life, programming the at least one memory cell to a fourth threshold voltage corresponding to the erased state,wherein the fourth threshold voltage is less than or more negative than the third threshold voltage.4. The method of claim 1 , wherein the desired data state is an erased state claim 1 , andwherein the second threshold voltage is less than or more negative than the first threshold voltage.5. The method of claim 1 , further ...

TRIM DETERMINATION BASED ON POWER AVAILABILITY

A system includes a processing device and a memory device coupled to the processing device. The memory device is further coupled to the processing device and to a primary power supply and a secondary power supply. The processing device is to determine, based at least in part on availability of the primary power supply to the memory device, whether to operate the memory device with a first trim tailored to data reliability or a second trim tailored to programming time. The processing device is further to operate the memory device with the determined one of the first trim or the second trim. 1. A system comprising:a processing device; anda memory device coupled to the processing device and to a primary power supply and a secondary power supply; store, using a first trim tailored to data reliability, telemetric sensor data in a first portion of the memory device;', 'copy, in response to a trigger event and the memory device being powered by the secondary power supply, the telemetric sensor data to a second portion of the memory device using a second trim tailored to programming time; and', 'copy, in response to the trigger event and the primary power supply being available despite the trigger event, the telemetric sensor data to the second portion of the memory device using the first trim tailored to programming time., 'wherein the processing device is to2. The system of claim 1 , wherein the first trim provides a relatively high data reliability; andwherein the second trim provides a relatively low data reliability.3. The system of claim 1 , wherein the second trim provides a relatively fast programming time; andwherein the first trim provides a relatively slow programming time.4. The system of claim 1 , wherein:the memory device comprises non-volatile memory; andthe secondary power supply is to provide power in response to a loss of the primary power supply.5. (canceled)6. The system of claim 1 , wherein the processing device is further to perform a media management ...

DETERMINATION OF RELIABILITY OF VEHICLE CONTROL COMMANDS VIA REDUNDANCY

A vehicle having a control element for the speed, acceleration or direction of the vehicle, two identical or redundant computing devices (e.g., each implemented as a system on chip (SoC)) to separately generate driving commands in parallel during autonomous driving of the vehicle, and a command controller coupled between the control element and the computing devices. In response to the commands from the identical or redundant computing devices, the command controller determines whether the commands are identical (or agree with each other); and if so, the command controller forwards one of the commands to the control element for execution. When there is a mismatch in the commands from the computing devices, the command controller tests the memories of the computing devices to identify a faulty one of the computing devices. 1. A method comprising:receiving, in a command controller of a vehicle, two commands respectively from two computing devices configured on the vehicle, the two commands configured to adjust operations of the vehicle;determining, by the command controller, whether the two commands match;testing portions of memories of the respective computing devices in response to a determination the two commands do not match; andskipping the testing in response to a determination that the two commands.2. The method of claim 1 , further comprising:in response to the determination that the two commands match, forwarding by the command controller one of the two commands for execution via a control element of the vehicle.3. The method of claim 1 , further comprising:in response to the determination that the two commands do not match with each other, determining whether results of the tests match with each other.4. The method of claim 3 , further comprising claim 3 , in response to a determination that the results of the tests do not match with each other:selecting a first command from the two commands based on the results of the tests; andforwarding by the command ...

DATA MANAGEMENT DURING A COPYBACK OPERATION

A method includes performing a copyback operation comprising transferring, using an internal processing device, user data and header data corresponding to the user data from a first block of memory in a memory device to a register in the memory device, decoupling the user data from the header data, performing an error correction code (ECC) operation on updated header data using an external processing device, transferring, via the external processing device, the updated header data to the register, and transferring the user data and the updated header data from the register to a second block of memory in the memory device.

SEPARATE TRIMS FOR BUFFER AND SNAPSHOT

A system includes a processing device and a memory device coupled to the processing device. The memory device can include a cyclic buffer portion and a snapshot portion. The processing device can store time based telemetric sensor data in the cyclic buffer portion, copy an amount of the telemetric sensor data from the cyclic buffer portion to the snapshot portion in response to a trigger event, operate the cyclic buffer portion with a first trim tailored to a performance target of the cyclic buffer portion, and operate the snapshot portion with a second trim tailored to a performance target of the snapshot portion.

VIRTUAL MIRROR WITH AUTOMATIC ZOOM BASED ON VEHICLE SENSORS

In one approach, a method includes: displaying, to a user of a first vehicle, image data obtained using a first field of view of a camera of the first vehicle, where the camera collects the image data for objects located outside of the first vehicle; detecting, by at least one processing device of the first vehicle, a second vehicle; determining, by the one processing device, whether the second vehicle is within a predetermined region relative to the first vehicle; and in response to determining that the second vehicle is within the predetermined region, displaying image data obtained using a second field of view of the camera. 1. A method comprising:adjusting a field of view of a camera of a first vehicle based on a speed of the first vehicle, wherein the camera collects image data for objects located outside of the first vehicle;determining whether the first vehicle is traveling faster than a predetermined speed;in response to determining that the first vehicle is traveling faster than the predetermined speed, displaying, to a user of the first vehicle, image data obtained using a first field of view of the camera;detecting, by at least one processing device of the first vehicle, a second vehicle;determining, by the one processing device, whether the second vehicle is within a predetermined region relative to the first vehicle; andin response to determining that the second vehicle is within the predetermined region, displaying image data obtained using a second field of view of the camera.2. The method of claim 1 , wherein the first field of view is narrower than the second field of view.3. The method of claim 1 , wherein the second field of view includes a first region on a side of the first vehicle claim 1 , the first region including a region associated with a blind spot of the user when operating the vehicle.4. The method of claim 1 , wherein determining whether the second vehicle is within the predetermined region comprises determining whether the second ...

READ VOLTAGE CALIBRATION FOR COPYBACK OPERATION

A system includes a memory device having a plurality of groups of memory cells and a processing device communicatively coupled to the memory device. The processing device is be configured to read a first group of memory cells of the plurality to determine a calibrated read voltage associated with the group of memory cells. The processing device is further configured to determine, using the calibrated read voltage associated with the first group of memory cells, a bit error rate (BER) of a second group of memory cells of the plurality. Prior to causing the memory device to perform a copyback operation on the plurality of groups of memory cells, the processing device is further configured to determine whether to perform a subsequent read voltage calibration on at least the second group of the plurality based, at least partially, on a comparison between the determined BER and a threshold BER. 1. A system , comprising:a memory device comprising a plurality of groups of memory cells; and read a first group of memory cells of the plurality to determine a calibrated a read voltage associated with the first group of memory cells;', 'determine, using the calibrated read voltage associated with the first group of memory cells, a bit error rate (BER) of a second group of memory cells of the plurality;', 'determine whether to perform a subsequent read voltage calibration on at least the second group of the plurality based, at least partially, on a comparison between the determined BER and a threshold BER.', 'prior to causing the memory device to perform a copyback operation on the plurality of groups of memory cells], 'a processing device communicatively coupled to the memory device, wherein the processing device is configured to2. The system of claim 1 , wherein:the plurality of groups of memory cells corresponds to a first superblock and the memory device further comprises a second superblock; perform, to obtain a calibrated read voltage to be used with the second superblock, ...

Memory mapping for hibernation

A computing system has a processing device (e.g., CPU, FPGA, or GPU) and memory regions (e.g., in a DRAM device) used by the processing device during normal operation. The computing system is configured to: monitor use of the memory regions in volatile memory; based on monitoring the use of the memory regions, identify at least one of the memory regions of the volatile memory; initiate a hibernation process; and during the hibernation process, copy data stored in the identified memory regions to non-volatile memory.

ADVANCED DRIVER-ASSISTANCE SYSTEM (ADAS) OPERATION UTILIZING ALGORITHMIC SKYLINE DETECTION

Disclosed are techniques for improving an advanced driver-assistance system (ADAS) by pre-processing image data. In one embodiment, a method is disclosed comprising receiving one or more image frames captured by an image sensor installed on a vehicle; identifying a position of a skyline in the one or more image frames, the position comprising a horizontal position of the skyline; cropping one or more future image frames based on the position of the skyline, the cropping generating cropped images comprising a subset of the corresponding future image frames; and processing the cropped images at an advanced driver-assistance system (ADAS). 1. A method comprising:receiving one or more image frames captured by an image sensor installed on a vehicle;identifying a position of a skyline in the one or more image frames, the position comprising a horizontal position of the skyline;cropping one or more future image frames based on the position of the skyline, the cropping generating cropped images comprising a subset of the corresponding future image frames; andprocessing the cropped images at an advanced driver-assistance system (ADAS).2. The method of claim 1 , further comprising determining that a current time corresponds to daytime and that the vehicle is in motion prior to identifying the position of the skyline in the one or more image frames.3. The method of claim 1 , the identifying a position of a skyline comprising identifying horizontal line numbers corresponding to each of the one or more image frames claim 1 , the horizontal line numbers representing the position of the skyline in each respective frame.4. The method of claim 3 , further comprising:performing a Gaussian analysis on the horizontal line numbers, the Gaussian analysis generating a Gaussian distribution;identifying a maximum bucket value of the Gaussian distribution; andusing the maximum bucket value as the position of the skyline.5. The method of claim 3 , wherein identifying a horizontal line number ...

MEMORY MANAGEMENT SCHEMES FOR NON-VOLATILE MEMORY DEVICES

A method includes storing data in a non-volatile memory that includes multiple memory blocks. At least first and second regions are defined in the non-volatile memory. A definition is made of a first over-provisioning ratio between a first logical address space and a first physical memory space of the first region, and a second over-provisioning ratio, different from the first over-provisioning ratio, between a second logical address space and a second physical memory space of the second region. Portions of the data are compacted, individually within each of the first and second regions and independently of the other region, by copying the portions from one or more source memory blocks to one or more destination memory blocks using the first and second over-provisioning ratios, respectively. 1. An apparatus , comprising:a memory, wherein the memory includes a plurality of regions, wherein each region of the plurality of regions includes a plurality of blocks, and wherein each block of the plurality of blocks includes a plurality of memory cells; anda controller coupled to the memory, wherein the controller is configured to:assign a first over-provisioning ratio to a first region of the plurality of regions;assign a second over-provisioning ratio to a second region of the plurality of regions;copy stored data from at least one block of the plurality of blocks of the first region to another block of the plurality of blocks of the first region dependent upon the first over-provisioning ratio; andcopy stored data from at least one block of the plurality of blocks of the second region to another block of the plurality of blocks of the second region dependent upon the second over-provisioning ratio.2. The apparatus of claim 1 , wherein to assign the first over-provisioning ratio claim 1 , the controller is further configured to determine the first over-provisioning ratio responsive to a determination that the first region stores data that changes at a first frequency ...

MEMORY MANAGEMENT SCHEMES FOR NON-VOLATILE MEMORY DEVICES

A method includes storing data in a non-volatile memory that includes multiple memory blocks. At least first and second regions are defined in the non-volatile memory. A definition is made of a first over-provisioning ratio between a first logical address space and a first physical memory space of the first region, and a second over-provisioning ratio, different from the first over-provisioning ratio, between a second logical address space and a second physical memory space of the second region. Portions of the data are compacted, individually within each of the first and second regions and independently of the other region, by copying the portions from one or more source memory blocks to one or more destination memory blocks using the first and second over-provisioning ratios, respectively. 1. A method , comprising:in a memory controller that stores data for a host in a memory, defining independently of the host execution priorities for two or more types of memory access tasks to be applied to the memory;accepting multiple un-prioritized memory access tasks submitted by the host to the memory controller, each of the accepted memory access tasks belonging to a respective one of the types; andapplying the accepted memory access tasks to the memory in accordance with the defined execution priorities responsively to the respective types.2. The method according to claim 1 , wherein defining the execution priorities comprises giving precedence to memory readout tasks over tasks other than the memory readout tasks.3. The method according to claim 1 , wherein defining the execution priorities comprises giving precedence to the memory access tasks relating to selected storage addresses over the memory access tasks relating to storage addresses other than the selected storage addresses.4. The method according to claim 1 , wherein defining the execution priorities comprises giving precedence to the memory access tasks relating to a selected file type over the memory access ...

Re-USING PROCESSING ELEMENTS OF AN ARTIFICIAL INTELLIGENCE PROCESSOR

The disclosed embodiments are directed toward improved control circuitry for artificial intelligence processors. In one embodiment, a device is disclosed comprising a processing element, the processing element including a processing device configured to receive a first set of vectors; a hijack control circuit, the hijack control circuit configured to replace the first set of vectors with a second set of vectors in response to detecting that the processing element is idle; and a processing element control circuit (PECC), the PECC storing a set of values representing the second set of vectors, the set of values retrieved from a remote data source.

MEMORY SUB-SYSTEM LOGICAL BLOCK ADDRESS REMAPPING

A system includes a memory device and a processing device coupled to the memory device. The processing device can determine a data rate from a first sensor and a data rate from a second sensor. The processing device can write a first set of data received from the first sensor at a first logical block address (LBA) in the memory device. The processing device can write a second set of data received from the second sensor and subsequent to the first set of data at a second LBA in the memory device. The processing device can remap the first LBA and the second LBA to be logically sequential LBAs. The second LBA can be associated with an offset from the first LBA and the offset can correspond to a data rate of the first sensor. 1. A system , comprising:a memory device; and{'claim-text': ['determining a data rate from a first sensor and a data rate from a second sensor;', {'claim-text': ['a first set of data received from the first sensor at a first logical block address (LBA) in the memory device; and', 'a second set of data received from the second sensor subsequent to the first set of data at a second LBA in the memory device; and', 'remapping the first LBA and the second LBA to be logically sequential LBAs;', 'wherein the second LBA is associated with an offset from the first LBA and the offset corresponds to a data rate of the first sensor; and'], '#text': 'writing:'}, 'updating a logical to physical (L2P) table indicating a starting position of the first LBA without updating a starting position of the second LBA in the memory device.'], '#text': 'a processing device coupled to the memory device, the processing device to perform operations comprising:'}2. The system of claim 1 , wherein the processing device is to perform operations further comprising:receiving a third set of data subsequent to the second set of data from the first sensor; andwriting a third set of data at a third LBA in the memory device, wherein the third LBA is logically sequential with the second ...

HIERARCHICAL DATA STORAGE SYSTEM

A data storage system includes a plurality of non-volatile memory devices arranged in one or more sets, a main controller and one or more processors. The main controller is configured to accept commands from a host and to convert the commands into recipes. Each recipe includes a list of multiple memory operations to be performed sequentially in the non-volatile memory devices belonging to one of the sets. Each of the processors is associated with a respective set of the non-volatile memory devices, and is configured to receive one or more of the recipes from the main controller and to execute the memory operations specified in the received recipes in the non-volatile memory devices belonging to the respective set. 1. An apparatus , comprisinga plurality of memory devices, wherein each memory device of the plurality of memory devices includes a plurality of non-volatile memory cells;one or more processors; receive one or more commands from a host processor;', 'send a signal to the host processor that causes the host processor to retrieve one or more information items relating to at least some of the plurality of memory cells in one or more of the non-volatile memory devices;', 'convert, dependent upon the one or more information items, the one or more commands into one or more groups of operations, wherein each group of operations includes a plurality of memory operations to be performed sequentially by a given one of the one or more processors on a given subset of the plurality of non-volatile memory devices; and, 'a controller configured to delete at least one data storage command from a given group of operations responsive to determining the at least one data storage command results in an unnecessary access to a given non-volatile memory device of the plurality of non-volatile memory devices; and', 'execute the one or more operations included in a respective group of operations of the one or more groups of operations., 'wherein each one of the one or more ...

Parallel Access to Volatile Memory by A Processing Device for Machine Learning

A memory system having a processing device (e.g., CPU) and memory regions (e.g., in a DRAM device) on the same chip or die. The memory regions store data used by the processing device during machine learning processing (e.g., using a neural network). One or more controllers are coupled to the memory regions and configured to: read data from a first memory region (e.g., a first bank), including reading first data from the first memory region, where the first data is for use by the processing device in processing associated with machine learning; and write data to a second memory region (e.g., a second bank), including writing second data to the second memory region. The reading of the first data and writing of the second data are performed in parallel. 1. A system , comprising:a processing device;a plurality of memory regions configured to store data used by the processing device; and read data from a first memory region of the plurality of memory regions, including reading first data from the first memory region, the first data for use by the processing device in processing associated with machine learning; and', 'write data to a second memory region of the plurality of memory regions, including writing second data to the second memory region;', 'wherein reading the first data and writing the second data are performed in parallel., 'at least one controller coupled to the plurality of memory regions and configured to2. The system of claim 1 , wherein the at least one controller comprises a respective controller used for read or write access to each of the memory regions.3. The system of claim 1 , wherein the first memory region is used in a continuous burst mode when the first data is read.4. The system of claim 3 , wherein the second memory region is used in a continuous burst mode when the second data is written.5. The system of claim 1 , wherein:the first data is used as an input to a neural network;the second data is an output from the neural network; andduring ...

Black box data recorder for autonomous driving vehicle

An improved black box data recorder for use with autonomous driving vehicles (AVD). In one embodiment, two cyclic buffers are provided to record vehicle sensors data. A first cyclic buffer records raw vehicle sensor data on a volatile memory, while a second cyclic buffer records the same vehicle sensor data, as compressed data, on a non-volatile memory. In a case of a collision or near collision, in one embodiment the buffers are flushed into a non-volatile (NV) storage for retrieval. As long as there is no power interruption, the raw vehicle sensor data will be accessible from the NV storage. If a power interruption occurs, the raw vehicle sensor data held in the volatile memory of the first cyclic buffer will be lost and only the compressed form of the vehicle sensor data from the second cyclic buffer will survive and be accessible.

Reuse of Host Hibernation Storage Space By Memory Controller

A method for data storage includes, in a host system that operates alternately in a normal state and a hibernation state, reserving a hibernation storage space in a non-volatile storage device for storage of hibernation-related information in preparation for entering the hibernation state. While the host system is operating in the normal state, a storage task other than storage of the hibernation-related information is performed using at least a portion of the reserved hibernation storage space. 1. A method for data storage , comprising:operating a host system alternately between a normal state and a hibernation state;reserving a hibernation storage space in a non-volatile storage device to store hibernation-related information in preparation for the host entering the hibernation state, wherein the non-volatile storage device includes memory blocks allocated as a user data storage space, over-provisioning memory, and the hibernation storage space; andallocating at least a portion of the hibernation storage space as over-provisioning memory during operation in the normal state, thereby allowing the over-provisioning memory to be used as a cache for valid data from partially-programmed memory blocks in a user data storage space subsequent to an erasure operation being performed on one or more locations of the user data storage space.2. The method according to claim 1 , further comprising allocating at least another portion of the hibernation storage space as a cache claim 1 , and caching user data accepted from the host system in the at least another portion of the hibernation storage space at a first data rate claim 1 , and subsequently copying the cached user data to storage locations outside the hibernation storage space at a second data rate that is slower than the first data rate.3. The method according to claim 1 , wherein reserving the hibernation storage space includes the host system allocating a set of storage locations of the user data storage space to ...

Efficient Readout from Memory Cells Using Data Compression

A method for data storage includes storing data in a group of analog memory cells by writing respective input storage values to the memory cells in the group. After storing the data, respective output storage values are read from the analog memory cells in the group. Respective confidence levels of the output storage values are estimated, and the confidence levels are compressed. The output storage values and the compressed confidence levels are transferred from the memory cells over an interface to a memory controller. 1. An apparatus , comprising:a plurality of memory cells; read a plurality of values from a subset of the plurality of memory cells, wherein each value of the plurality of values corresponds to data stored in a respective one of the subset of the plurality of memory cells;', 'determine a plurality of confidence levels dependent upon the plurality of values; and', 'compress the plurality of confidence levels., 'circuitry configured to2. The apparatus of claim 1 , wherein to compress the plurality of confidence levels claim 1 , the circuitry is further configured to determine a first number of confidence levels of the plurality of confidence levels having a first value claim 1 , and a second number of confidence levels of the plurality of confidence levels having a second value.3. The apparatus of claim 2 , wherein the circuitry is further configured to send the first number and the second number to a controller.4. The apparatus of claim 1 , wherein to compress the plurality of confidence levels claim 1 , the circuitry is further configured to combine each confidence level of the plurality of confidence levels using a logical-AND operation to generate an indicator value.5. The apparatus of claim 4 , wherein the circuitry is coupled to a controller via a data bus claim 4 , and wherein the circuitry is further configured to send the indicator value to a controller using at least one wire separate from the data bus.6. The apparatus of claim 1 , wherein ...

HIGH-RELIABILITY NON-VOLATILE MEMORY USING A VOTING MECHANISM

A memory system includes a processing device (e.g., a controller implemented using a CPU, FPGA, and/or logic circuitry) and memory regions (e.g., in a flash memory or other non-volatile memory) storing data. The processing device receives an access request from a host system that is requesting to read the stored data. In one approach, the memory system is configured to: receive, from the host system over a bus, a read command to access data associated with an address in a non-volatile memory; in response to receiving the read command, access, by the processing device, multiple copies of data stored in at least one memory region of the non-volatile memory; match, by the processing device, data from the copies with each other; select, based on matching data from the copies with each other, first data from a first copy of the copies; and provide, to the host system over the bus, the first data as output data. 1. A system comprising:a communication interface configured to receive a request from a host system, and provide output data to the host system in response to the request;a non-volatile memory configured to store copies of data; anda majority voter configured to, in response to receiving the request, access the copies of data, and select one of the copies as the output data.2. The system of claim 1 , further comprising a cache configured to receive the copies of data accessed by the majority voter.3. The system of claim 2 , wherein the majority voter is further configured to read data from the copies in the cache to perform an evaluation of the copies to select the one of the copies as the output data.4. The system of claim 1 , wherein the majority voter selects the one of the copies based on matching data from the copies with each other.5. The system of claim 4 , wherein the request is a read command claim 4 , and matching data from the copies with each other comprises matching each of a sequential series of corresponding entries read in parallel from each of the ...

STORING AND RECOVERING CRITICAL DATA IN A MEMORY DEVICE

The disclosed embodiments are related to storing critical data in a memory device such as Flash memory device. In one embodiment, a method performed by a controller of a memory device comprises receiving a critical operation from a host processor, the critical operation accessing a memory array; retrieving a temperature value of the memory array from a temperature sensor; and conditionally processing the critical operation based on the temperature value. 1. A device comprising:a memory array, the memory array comprising a plurality of addressable memory cells;a temperature sensor positioned at a first location with respect to the memory array, the temperature sensor configured to record an average temperature of the memory array; and receive a critical operation from a host processor, the critical operation accessing one or more of the memory cells of the memory array,', 'retrieve a temperature value of the memory array from the temperature sensor, and', 'conditionally process the critical operation based on the temperature value., 'a controller, the controller positioned at a second location with respect to the memory array, the controller configured to2. The device of claim 1 , wherein the critical operation comprises a critical read operation claim 1 , the critical read operation including an address.3. The method of claim 2 , the controller further configured to:query a critical access table using the address, the querying returning a plurality of addresses;read temperature data from the plurality of addresses; andprocess the critical read operation based on the temperature data and the temperature value returned by the temperature sensor.4. The device of claim 1 , wherein processing the critical read operation comprises executing a majority voter function on the temperature data claim 1 , the majority voter function returning a selected temperature value from the temperature data.5. The device of claim 4 , wherein processing the critical read operation ...

Parallel Memory Access and Computation in Memory Devices

An integrated circuit (IC) memory device encapsulated within an IC package. The memory device includes first memory regions configured to store lists of operands; a second memory region configured to store a list of results generated from the lists of operands; and at least one third memory region. A communication interface of the memory device can receive requests from an external processing device; and an arithmetic compute element matrix can access memory regions of the memory device in parallel. When the arithmetic compute element matrix is processing the lists of operands in the first memory regions and generating the list of results in the second memory region, the external processing device can simultaneously access the third memory region through the communication interface to load data into the third memory region, or retrieve results that have been previously generated by the arithmetic compute element matrix. 1. An integrated circuit memory device , comprising:a plurality of memory regions;an arithmetic compute element matrix coupled to access the plurality of memory regions in parallel; anda communication interface coupled to the arithmetic compute element matrix and configured to receive a first request;wherein, in response to the first request, the arithmetic compute element matrix is configured to access a plurality of lists of operands stored in first memory regions in the plurality of memory regions, generate a list of results from the plurality of lists of operands, and store the list of results in a second memory region in the plurality of memory regions; the communication interface is configured to receive a second request to access a third memory region in the plurality of memory regions; and', 'in response to the second request and during the time period, the integrated circuit memory device is configured to provide, in parallel, memory access to the first memory regions and the second memory region to the arithmetic compute element matrix in ...

Accelerated Access to Computations Results Generated from Data Stored in Memory Devices

An integrated circuit (IC) memory device encapsulated within an IC package. The memory device includes: multiple memory regions configured to store one or more lists of operands; an arithmetic compute element matrix coupled to access the memory regions in parallel; and a communication interface to receive a request from an external processing device. In response to the request, the arithmetic compute element matrix computes an output from the plurality of lists of operands stored in the plurality of memory regions; and the communication interface provides the output as a response to the request. For example, the request can be a memory read command addressing a memory location where an opcode is stored; and the output can be provided as if the output had been pre-calculated and stored at the memory location. 1. An integrated circuit memory device , comprising:a plurality of memory regions configured to store a plurality of lists of operands;an arithmetic compute element matrix coupled to access the plurality of memory regions in parallel; anda communication interface coupled to the arithmetic compute element matrix and configured to receive a request; the arithmetic compute element matrix is configured to compute an output from the plurality of lists of operands stored in the plurality of memory regions; and', 'the communication interface is configured to provide the output as a response to the request; and, 'wherein, in response to the request,'}wherein the integrated circuit memory device is encapsulated within an integrated circuit package.2. The integrated circuit memory device of claim 1 , wherein the plurality of memory regions provides dynamic random access memory (DRAM).3. The integrated circuit memory device of claim 2 , wherein the DRAM is formed on a first integrated circuit die; and the arithmetic compute element matrix is formed on a second integrated circuit die different from the first integrated circuit die.4. The integrated circuit memory device of ...

Memory Mapping for Hibernation

A computing system has a processing device (e.g., CPU, FPGA, or GPU) and memory regions (e.g., in a DRAM device) used by the processing device during normal operation. The computing system is configured to: monitor use of the memory regions in volatile memory; based on monitoring the use of the memory regions, identify at least one of the memory regions of the volatile memory; initiate a hibernation process; and during the hibernation process, copy data stored in the identified memory regions to non-volatile memory. 1. A system , comprising:at least one processing device; and monitor use of memory regions in volatile memory;', 'based on monitoring the use of the memory regions, identify at least one of the memory regions of the volatile memory;', 'initiate a hibernation process; and', 'during the hibernation process, copy data stored in the identified memory regions to non-volatile memory., 'memory storing instructions configured to instruct the at least one processing device to2. The system of claim 1 , wherein identifying the at least one of the memory regions includes associating a flag with each of the memory regions claim 1 , the flag identifying the respective memory region as critical for hibernation.3. The system of claim 2 , wherein the flag is a first flag claim 2 , the identified memory regions are first memory regions claim 2 , and the instructions are further configured to instruct the at least one processing device to associate a second flag with each of at least one second memory region of the volatile memory claim 2 , the second flag identifying each of the at least one second memory region as non-critical for hibernation.4. The system of claim 3 , wherein the instructions are further configured to instruct the at least one processing device to claim 3 , during the hibernation process claim 3 , copy data stored in the second memory regions to the non-volatile memory claim 3 , wherein the data stored in the second memory regions is copied to the non- ...

Adapted scanning window in image frame of sensor for object detection

A scanning window is used to scan an image frame of a sensor when doing object detection. In one approach, positions within the image frame are stored in memory. Each position corresponds to an object detection at that position for a prior frame of data. A first area of the image frame is determined based on the stored positions. When starting to analyze a new frame of data, the first area is scanned to detect at least one object. After scanning within the first area, at least one other area of the new image frame is scanned.

Determination of Reliability of Vehicle Control Commands using a Voting Mechanism

A vehicle having a control element for the speed, acceleration or direction of the vehicle, multiple identical or redundant computing devices (e.g., each implemented as a system on chip (SoC)) to separately generate driving commands in parallel during autonomous driving of the vehicle, and a command controller coupled between the control element and the computing devices. The commands may have one or more matching groups, where commands within each respective group agree with each other and thus vote for a candidate command representing the group. The computing device outputs a candidate command that represents the largest group for execution by the control element.

MEMORY MANAGEMENT SCHEMES FOR NON-VOLATILE MEMORY DEVICES

A method includes storing data in a non-volatile memory that includes multiple memory blocks. At least first and second regions are defined in the non-volatile memory. A definition is made of a first over-provisioning ratio between a first logical address space and a first physical memory space of the first region, and a second over-provisioning ratio, different from the first over-provisioning ratio, between a second logical address space and a second physical memory space of the second region. Portions of the data are compacted, individually within each of the first and second regions and independently of the other region, by copying the portions from one or more source memory blocks to one or more destination memory blocks using the first and second over-provisioning ratios, respectively. 1. An apparatus , comprising:a memory including a plurality of memory cells; and receive data from a host for storage in the memory;', 'store the data using a first storage density in response to a determination that the data is included in a file of a first file type; and', 'store the data using a second storage density in response to a determination that the data is included in a file of a second file type., 'a controller coupled to the memory, wherein the controller is configured to2. The apparatus of claim 1 , wherein the first file type includes sensitive files claim 1 , and wherein the second file type includes non-sensitive files.3. The apparatus of claim 1 , wherein the first storage density is less than the second storage density.4. The apparatus of claim 1 , wherein to store the data using the first storage density claim 1 , the controller is further configured to store the data using a first number of data bits per memory cell claim 1 , and wherein to store the data using the second storage density claim 1 , the controller is further configured to store the data using a second number of data bits per memory cell claim 1 , wherein the second number of data bits is ...

PARTITIONS WITHIN SNAPSHOT MEMORY FOR BUFFER AND SNAPSHOT MEMORY

A system includes a processing device and a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion and a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can further include a first sub-partition portion having a first programming characteristic and a second sub-partition portion having a second programming characteristic. The processing device can write received data sequentially to the cycle buffer partition portion and write, based at least in part on a determination that a trigger event has occurred, data from the cyclic buffer partition portion to the first sub-partition portion or the second sub-partition portion, or both. 1. A system , comprising:a processing device; and a cyclic buffer portion; and', a first portion having a first programming characteristic; and', 'a second portion having a second programming characteristic;, 'a snapshot portion coupled to the cyclic buffer portion, the snapshot portion further comprising], 'a memory device communicatively coupled to the processing device and comprising write received data sequentially to the first portion; and', 'write, based at least in part on a determination that a trigger event has occurred, data from the cyclic buffer to the first or second portion of the snapshot portion, or both., 'wherein the processing device is to2. The system of claim 1 , wherein the processing device is to:operate memory cells of the first portion in a single-level cell (SLC) mode; andoperate memory cells of the second portion in a multiple level cell mode.3. The system of claim 1 , wherein an energy consumption per bit associated with the first programming characteristic is less than an energy consumption per bit associated with the second programming characteristic.4. The system of claim 1 , wherein the first portion of memory cells of the snapshot portion having the first ...

Data Link Between Volatile Memory and Non-Volatile Memory

A computing system has a first processing device (e.g., CPU, FPGA, or GPU) and memory regions (e.g., in a DRAM device) used by the processing device during normal operation. In one approach, the computing system is configured to: collect data associated with operation of an autonomous vehicle; monitor, by a first processing device, the collected data; and based on the monitoring, determine that an event on the autonomous vehicle has occurred. The computing system is further configured to, in response to determining that the event has occurred, initiate a transfer of data controlled by a second processing device, the transfer including copying data stored in volatile memory of the autonomous vehicle to non-volatile memory of the autonomous vehicle, wherein the second processing device controls copying of the data independently of the first processing device. The computing system is also further configured to, in response to determining that the event has occurred, reduce or terminate power to the first processing device.

HIGH-RELIABILITY NON-VOLATILE MEMORY USING A VOTING MECHANISM

A memory system includes a processing device (e.g., a controller implemented using a CPU, FPGA, and/or logic circuitry) and memory regions (e.g., in a flash memory or other non-volatile memory) storing data. The processing device receives an access request from a host system that is requesting to read the stored data. In one approach, the memory system is configured to: receive, from the host system over a bus, a read command to access data associated with an address in a non-volatile memory; in response to receiving the read command, access, by the processing device, multiple copies of data stored in at least one memory region of the non-volatile memory; match, by the processing device, data from the copies with each other; select, based on matching data from the copies with each other, first data from a first copy of the copies; and provide, to the host system over the bus, the first data as output data. 1. A method for a non-volatile memory , comprising:receiving, from a host system over a bus, a read command to access data associated with an address in the non-volatile memory;in response to receiving the read command, accessing, by a processing device, multiple copies of data stored in at least one memory region of the non-volatile memory;matching, by the processing device, data from the copies with each other;selecting, based on matching data from the copies with each other, first data from a first copy of the copies; andproviding, to the host system over the bus, the first data as output data.2. The method of claim 1 , wherein matching data from the copies with each other comprises matching each of a sequential series of corresponding entries read in parallel from each of the copies for responding to the read command.3. The method of claim 1 , wherein the data associated with an address in the non-volatile memory is boot code stored in a boot partition of the non-volatile memory.4. The method of claim 1 , wherein a threshold number of data entries from the ...

DEFERRED ERROR CODE CORRECTION WITH IMPROVED EFFECTIVE DATA BANDWIDTH PERFORMANCE

A deferred error correction code (ECC) scheme for memory devices is disclosed. In one embodiment, a method is disclosed comprising starting a deferred period of operation of a memory system in response to detecting the satisfaction of a condition; receiving an operation during the deferred period, the operation comprising a read or write operation access one or more memory banks of the memory system; deferring ECC operations for the operation; executing the operation; detecting an end of the deferred period of operation; and executing the ECC operations after the end of the deferred period. 1. A method comprising:starting a deferred period of operation of a memory system in response to detecting a satisfaction of a condition;issuing a command to a memory bank of the memory system in response to an operation received from a processor;generating ECC data prior to receiving a response to the command from the memory bank;caching the ECC data in a local cache; andreturning a result of the command to the processor while the ECC data is present in the local cache.2. The method of claim 1 , further comprising:receiving the operation during the deferred period, the operation comprising a read or write operation access one or more memory banks of the memory system; andexecuting the operation prior to issuing the command to the memory bank of the memory system.3. The method of claim 1 , the detecting the satisfaction of the condition comprising detecting one of:a receipt of a second command to start the deferred period from the processor; ora data bus utilization above a predetermined threshold.4. The method of claim 2 , the operation comprising a write operation and the generating ECC data comprising:generating ECC parity bits based on data in the write operation; andstoring the ECC parity bits and an address associated with the data in the local cache.5. The method of claim 4 , further comprising writing the ECC parity bits to the memory bank using the address.6. The method ...

Sensor fusion to determine reliability of autonomous vehicle operation

A method for an autonomous vehicle includes: receiving first object data from a first sensor module; receiving second object data from a second sensor module; comparing the first object data to the second object data; determining, based on comparing the first object data to the second object data, whether the first object data corresponds to the second object data; and in response to determining that the first object data does not correspond to the second object data, performing an action for the autonomous vehicle.

Wear leveling for non-volatile memory using data write counters

A memory system has a controller (e.g., CPU, FPGA, or GPU) and recording segments in a non-volatile memory (e.g., a flash memory device) used by the controller to store data. The controller is configured to: maintain data write counters for the recording segments; select a first segment of the recording segments for recording data from a host system, wherein selecting the first segment comprises scanning the data write counters to identify a first data write counter corresponding to the first segment; receive, from the host system, data to be recorded by the non-volatile memory; and write the received data to the selected first segment.

DETERMINING AUTONOMOUS VEHICLE STATUS BASED ON MAPPING OF CROWDSOURCED OBJECT DATA

A map in a cloud service stores physical objects previously detected by other vehicles that have previously traveled over the same road that a current vehicle is presently traveling on. New data received by the cloud service from the current vehicle regarding new objects that are being encountered by the current vehicle can be compared to the previous object data stored in the map. Based on this comparison, an operating status of the current vehicle is determined. In response to determining the status, an action such as terminating an autonomous navigation mode of the current vehicle is performed. 1. A system comprising:at least one memory; and receive data regarding objects detected by a plurality of vehicles including a first vehicle, the detected objects including a first object detected by one of the vehicles other than the first vehicle;', 'store, in the memory, a map comprising the detected objects, each object having an object type and a location;', 'receive first data regarding objects detected by the first vehicle;', 'determine, based on comparing the received first data to the map, that the first vehicle has failed to detect the first object; and', 'in response to determining that the first vehicle has failed to detect the first object, update firmware of a controller of the first vehicle., 'at least one processor configured to2. The system of claim 1 , wherein the first object is a traffic sign claim 1 , a traffic light claim 1 , a road lane claim 1 , or a physical structure.3. The system of claim 1 , wherein the processor is further configured to determine a location of the first vehicle claim 1 , and determining that the first vehicle has failed to detect the first object includes comparing the location of the first vehicle to the location of the first object stored in the map.4. The system of claim 1 , wherein the first vehicle is an autonomous vehicle.5. The system of claim 1 , wherein the processor is further configured to analyze the first data ...

SELECTION OF REDUNDANT STORAGE CONFIGURATION BASED ON AVAILABLE MEMORY SPACE

A method includes, in a memory controller that controls a memory, evaluating an available memory space remaining in the memory to write data. A redundant storage configuration is selected in the memory controller depending on the available memory space. Redundancy information is calculated over the data using the selected redundant storage configuration. The data and the redundancy information are written to the available memory space in the memory. 1. A method , comprising:in a memory controller that controls a memory, evaluating an available memory space remaining in the memory to write data;selecting in the memory controller a redundant storage configuration depending on the available memory space;calculating redundancy information over the data using the selected redundant storage configuration; andwriting the data and the redundancy information to the available memory space in the memory.2. The method according to claim 1 , wherein selecting the redundant storage configuration comprises choosing claim 1 , based on the available memory space claim 1 , a number of memory blocks over which the redundancy information is calculated.3. The method according to claim 1 , wherein selecting the redundant storage configuration comprises choosing an Error Correction Code (ECC) having a code rate that depends on the available memory space claim 1 , and wherein calculating the redundancy information comprises computing the redundancy information using the chosen ECC.4. The method according to claim 1 , wherein selecting the redundant storage configuration comprises reassigning one or more memory blocks from storing a part of the redundancy information to storing a portion of the data.5. The method according to claim 1 , wherein selecting the redundant storage configuration comprises switching from a first storage configuration that protects against failure of one or more entire memory blocks to a second storage configuration that protects against failure of only portions of ...

Determination of Reliability of Vehicle Control Commands via Memory Test

A vehicle having a control element for the speed, acceleration or direction of the vehicle, a computing device to generate a command in autonomous driving of the vehicle, and a command controller coupled between the control element and the computing device. In response to the command, the command controller initiates a test of a portion of the memory of the computing device. If the portion of the memory passes the test, the command controller forwards the command for execution via the control element of the vehicle; otherwise, the command controller blocks the command and/or issues a replacement command for the vehicle. 1. A method implemented on a vehicle , the method comprising:receiving, from a computing device configured on the vehicle, a command for operations of a control element of the vehicle, the computing device having a memory, at least one processor, and firmware stored in the memory and executed in the at least one processor to generate the command; initiating a test of a portion of the memory of the computing device; and', 'determining whether the portion of the memory passes the test; and, 'in response to the command,'} forwarding the command for execution via the control element of the vehicle, in response to a determination that the portion of the memory passes the test; and', 'preventing the command from being executed via the control element of the vehicle, in response to a determination that the portion of the memory fails the test., 'based on a result of the test, performing one of2. The method of claim 1 , further comprising:receiving input data from at least one sensor configured on the vehicle; andgenerating, by the computing device, the command based on the input data.3. The method of claim 2 , wherein the at least one sensor includes at least one of:a camera;an infrared camera;a sonar;a radar; anda lidar.4. The method of claim 3 , wherein the computing device generates commands for autonomous driving of the vehicle.5. The method of claim 3 ...

Determination of Reliability of Vehicle Control Commands via Redundancy

A vehicle having a control element for the speed, acceleration or direction of the vehicle, two identical or redundant computing devices (e.g., each implemented as a system on chip (SoC)) to separately generate driving commands in parallel during autonomous driving of the vehicle, and a command controller coupled between the control element and the computing devices. In response to the commands from the identical or redundant computing devices, the command controller determines whether the commands are identical (or agree with each other); and if so, the command controller forwards one of the commands to the control element for execution. When there is a mismatch in the commands from the computing devices, the command controller tests the memories of the computing devices to identify a faulty one of the computing devices. 1. A method implemented on a vehicle , the method comprising:receiving, in a command controller, two commands respectively from two computing devices configured on the vehicle, the two commands configured to adjust operations of a control element of the vehicle, wherein each of the two computing devices having a memory, at least one processor, and firmware stored in the memory and executed in the at least one processor to generate a respective one of the two commands;determining, by the command controller, whether the two commands match with each other; and initiating tests of portions of memories of the computing devices in response to a determination that the two commands do not match with each other; and', 'skipping the tests in response to a determination that the two commands match with each other., 'based on a result of the determining, performing one of2. The method of claim 1 , further comprising:in response to the determination that the two commands match with each other, forwarding by the command controller one of the two commands for execution via the control element of the vehicle.3. The method of claim 1 , further comprising:in ...

Determination of Reliability of Vehicle Control Commands using a Voting Mechanism

A vehicle having a control element for the speed, acceleration or direction of the vehicle, multiple identical or redundant computing devices (e.g., each implemented as a system on chip (SoC)) to separately generate driving commands in parallel during autonomous driving of the vehicle, and a command controller coupled between the control element and the computing devices. The commands may have one or more matching groups, where commands within each respective group agree with each other and thus vote for a candidate command representing the group. The computing device outputs a candidate command that represents the largest group for execution by the control element. 1. A method implemented on a vehicle , the method comprising:receiving, in a command controller, multiple commands respectively from multiple computing devices configured on the vehicle, the multiple commands configured to adjust operations of a control element of the vehicle during autonomous driving;matching, by the command controller, the multiple commands with each other to identify votes for the multiple commands, wherein a vote count of each respective command in the multiple commands identifies a number of matching ones in the multiple commands that match with the respective command;identifying, by the command controller, a first command from the multiple commands based on a has a winning vote count of the first command; andforwarding, from the command controller, the first command for execution via the control element of the vehicle.2. The method of claim 1 , wherein the first command has the winning vote count when a vote count of the first command is above a threshold.3. The method of claim 2 , wherein the threshold is more than half of a count of the multiple computing devices.4. The method of claim 2 , wherein the threshold is less than half of a count of the multiple computing devices.5. The method of claim 2 , further comprising:stopping the matching to identify additional matches within ...

DETERMINATION OF RELIABILITY OF VEHICLE CONTROL COMMANDS VIA MEMORY TEST

A vehicle having a control element for the speed, acceleration or direction of the vehicle, a computing device to generate a command in autonomous driving of the vehicle, and a command controller coupled between the control element and the computing device. In response to the command, the command controller initiates a test of a portion of the memory of the computing device. If the portion of the memory passes the test, the command controller forwards the command for execution via the control element of the vehicle; otherwise, the command controller blocks the command and/or issues a replacement command for the vehicle. 1. A method implemented on a vehicle , the method comprising:receiving, from a computing device configured on the vehicle, a command for operations of a control element of the vehicle, the computing device having a memory, at least one processor, and firmware stored in the memory and executed in the at least one processor to generate the command; initiating a test of a portion of the memory of the computing device; and', 'determining whether the portion of the memory passes the test; and, 'in response to the command,'} forwarding the command for execution via the control element of the vehicle, in response to a determination that the portion of the memory passes the test; and', 'preventing the command from being executed via the control element of the vehicle, in response to a determination that the portion of the memory fails the test., 'based on a result of the test, performing one of2. The method of claim 1 , further comprising:receiving input data from at least one sensor configured on the vehicle; andgenerating, by the computing device, the command based on the input data.3. The method of claim 2 , wherein the at least one sensor includes at least one of:a camera;an infrared camera;a sonar;a radar; anda lidar.4. The method of claim 3 , wherein the computing device generates commands for autonomous driving of the vehicle.5. The method of claim 3 ...

ARTIFICIAL INTELLIGENCE-BASED PERSISTENCE OF VEHICLE BLACK BOX DATA

The disclosed embodiments are directed to improving the persistence of pre-accident data in vehicles. In one embodiment a method is disclosed comprising receiving events broadcast over a vehicle bus; classifying the events using a machine learning model, the classifying comprising indicating that a collision is imminent; and copying data from a cyclic buffer of a black box device into a long-term storage device in response to the classifying. 1. A method comprising:receiving signaling indicative of events related to a vehicle, the signaling broadcast or multicast over a bus configured to communicate data signals or control signals, or both, between components of a computing system within the vehicle;classifying the events using a machine learning model based at least in part on the received signaling, the classifying comprising indicating that a collision between the vehicle and another object is imminent; andcopying data from a cyclic buffer of a first device within the computing system into a storage device in response to the classifying.2. The method of claim 1 , the receiving the signaling indicative of events comprising receiving raw event data from a plurality of subsystems of the vehicle.3. The method of claim 1 , the indicating that a collision is imminent comprising identifying that the collision likely to occur within a threshold level of confidence.4. The method of claim 1 , the classifying the events comprising classifying the events using a neural network.5. The method of claim 4 , further comprising re-training the neural network using the data stored in the storage device.6. The method of claim 5 , the re-training further comprising labeling the data stored in the long-term storage device based on whether an actual collision was detected after the classifying.7. The method of claim 1 , further comprising identifying a set of false positive and false negative events and adjusting parameters of the machine learning model based on the false positive and ...

BLACK BOX OPERATIONS CONTROLLED BY DRIVER MENTAL STATE EVALUATION

The disclosed embodiments are directed to adjusting the operational characteristics of a black box installed in a vehicle. In one embodiment a method is disclosed comprising classifying a mental state of a driver of an automobile, loading at least one setting based on the mental state, the setting defining an operational characteristic of a black box installed in the automobile, configuring the black box using the at least one setting, and recording one or more events by the black box. 1. A method comprising:receiving, from a sensor of an automobile, signaling that indicates a characteristic of a driver of the autmobile or the driver's input to the automobile;classifying a mental state of the driver of the automobile based at least in part on the signaling;loading at least one setting in a processor or computing device of a monitoring system in the automobile based on the mental state, the setting defining an operational characteristic of memory or storage of the monitoring system in the automobile;configuring the monitoring system using the at least one setting; andrecording one or more events by the monitoring system.2. The method of claim 1 , the classifying the mental state of the driver comprising analyzing one or more outputs of vehicle components.3. The method of claim 2 , the analyzing the one or more outputs of vehicle components comprising storing a set of negative events detected in the outputs and using the negative events to classify the mental state of the driver.4. The method of claim 1 , the classifying the mental state of the driver comprising classifying the mental state as drowsy claim 1 , tired claim 1 , or impaired.5. The method of claim 1 , the loading at least one setting comprising loading a setting increasing an amount of data captured by the monitoring system.6. The method of claim 1 , the loading at least one setting comprising loading a setting increasing a sampling fidelity of the monitoring system.7. The method of claim 1 , the loading ...

ARTIFICIAL INTELLIGENCE-ENABLED ALARM FOR DETECTING PASSENGERS LOCKED IN VEHICLE

The disclosed embodiments are directed to detecting persons or animals trapped in vehicles and providing automated assistance to such persons or animals. In one embodiment a method is disclosed comprising detecting that a vehicle is stopped; activating at least one camera and recording at least one image of an interior of the vehicle using the at least one camera; classifying the at least one image using a machine learning model; and operating at least one subsystem of the vehicle in response to detecting that classifying indicates that a person or animal is present in the at least one image. 1. A method comprising:receiving signaling from one or more sensors of a vehicle, the signaling indicating that the vehicle is stopped;activating at least one camera and recording at least one image of an interior of the vehicle using the at least one camera in response to receiving the signaling;classifying the at least one image using a machine learning model; andoperating at least one subsystem of the vehicle in response to detecting that classifying indicates that a person or animal is present in the at least one image.2. The method of claim 1 , the detecting that the vehicle is stopped comprising detecting that the vehicle is not running and one or more doors of the vehicle are locked.3. The method of claim 1 , the classifying the at least one image using the machine learning model comprising classifying the at least one image using a neural network.4. The method of claim 1 , further comprising recording a second image in response to determining that the at least one image does not include a person or animal.5. The method of claim 1 , the operating the at least one subsystem comprising monitoring a temperature of the vehicle and operating the at least one subsystem in response to detecting that the temperature exceeds a pre-defined threshold.6. The method of claim 5 , the operating the at least one subsystem comprising operating an air conditioning system of the vehicle.7. ...

Configuring a host interface of a memory device based on mode of operation

A memory device stores data for a host device. In one approach, a method includes: selecting, by the memory device, a first mode of operation for a host interface that implements a communication protocol for communications between the memory device and the host device. The host interface is configured to implement the communication protocol using a mode selected by the memory device from one of several available modes. In response to selecting the first mode, resources of the memory device are configured to customize the host interface for operation in the first mode.

Identifying Suspicious Entities Using Autonomous Vehicles

Systems and methods for identifying suspicious entities using autonomous vehicles are disclosed. In one embodiment, a method is disclosed comprising identifying a suspect vehicle using at least one digital camera equipped on an autonomous vehicle; identifying a set of candidate autonomous vehicles; enabling, on each of the candidate autonomous vehicles, a search routine, the search routine instructing each respective autonomous vehicle to coordinate tracking of the suspect vehicle; recording, while tracking the suspect vehicle, a plurality of images of the suspect vehicle; periodically re-calibrating the search routines executed by the autonomous vehicles based on the plurality of images; and re-routing the autonomous vehicles based on the re-calibrated search routines. 1. A method comprising:identifying a suspect vehicle using at least one digital camera equipped on an autonomous vehicle;identifying a set of candidate autonomous vehicles;enabling, on each of the candidate autonomous vehicles, a search routine, the search routine instructing each respective autonomous vehicle to coordinate tracking of the suspect vehicle;recording, while tracking the suspect vehicle, a plurality of images of the suspect vehicle;periodically re-calibrating the search routines executed by the autonomous vehicles based on the plurality of images; andre-routing the autonomous vehicles based on the re-calibrated search routines.2. The method of claim 1 , wherein identifying a suspect vehicle comprises analyzing at least one image captured by the digital camera using a deep neural network.3. The method of claim 2 , wherein identifying a suspect vehicle comprises identifying a suspect vehicle based on detecting a license plate number claim 2 , make claim 2 , model claim 2 , or color of the suspect vehicle appearing within the image.4. The method of claim 1 , wherein identifying a suspect vehicle further comprises identifying the suspect vehicle using one or more sensors of the autonomous ...

ANN TRAINING THROUGH PROCESSING POWER OF PARKED VEHICLES

A system for ANN training through processing power of parked vehicles. The system can include a master computing device having a controller configured to control training of an ANN. The training can be performed at least partially in separate parts by computing devices of parked vehicles. The controller can be configured to separate computing tasks of training the ANN into separated tasks. Also, the controller can be configured to assign at least some of the separated tasks to selected computing devices of parked vehicles. The controller can also be configured to receive and assemble results of the separated tasks to train the ANN. The controller can also be configured to train the ANN according to the results. The master computing device can be configured to send the assigned tasks to the selected devices of the vehicles as well as receive, from the selected devices, the results of the assigned tasks. 1. A system comprising:at least one processing device; and determine vehicles comprising processing resources that are available for processing computing tasks used to train an artificial neural network (ANN);', 'separate the computing tasks;', 'assign each of the separated tasks one or more of the vehicles;', 'send, by a communication interface, communications including the assigned tasks to the processing resources of the vehicles, wherein the processing resources are configured to process the assigned tasks to provide results;', 'receive, by the communication interface, communications from the processing resources of the vehicles including the results; and', 'train the ANN according to the results., 'memory containing instructions configured to instruct the at least one processing device to2. The system of claim 1 , wherein the determining processing resources that are available comprises receiving communications from the processing resources claim 1 , each communication from a respective processing resource including an indication of availability determined by the ...

Data Recorders of Autonomous Vehicles

Systems, methods and apparatus to collect sensor data generated in an autonomous vehicle. Sensors of the vehicle generate a sensor data stream that is buffered, in parallel and in a cyclic way, in a first cyclic buffer and a larger second cyclic buffer respectively. An advanced driver assistance system of the vehicle generates an accident signal when detecting or predicting an accident and provides a training signal when detecting a fault in object detection, recognition, identification or classification. The accident signal causes a sensor data stream segment to be copied from the first cyclic buffer into a slot of a non-volatile memory, selected from a plurality of slots in a round robin way. The training signal causes a sensor data stream segment to be copied from the second cyclic buffer into an area of the non-volatile memory outside of the slots reserved for the first cycle buffer. 1. An autonomous vehicle , comprising:sensors configured to generate a sensor data stream during operations of the autonomous vehicle on a road;an advanced driver assistance system configured to operate the autonomous vehicle on the road based on the sensor data stream, wherein the advanced driver assistance system is further configured to generate an accident signal in response to detection or prediction of an accident and generate a training signal in response to a fault in object detection, recognition, identification or classification;a non-volatile memory;a first cyclic buffer having a capacity to buffer first sensor data generated by the sensors up to a first period of time;a second cyclic buffer having a capacity to buffer second sensor data generated by the sensors up to a second period of time that is longer than the first period of time, wherein the first cyclic buffer and the second cyclic buffer are configured to buffer the sensor data stream in parallel and cyclically within the capacity of the first cyclic buffer and the capacity of the second cyclic buffers ...

Autonomous Vehicle Data Recorders

Systems, methods and apparatus to collect sensor data generated in an autonomous vehicle. Sensors in the vehicle generate a sensor data stream during operations of the vehicle on a road. An advanced driver assistance system (ADAS) of the vehicle uses the sensor data stream to operate the vehicle and generate a trigger signal in response to a fault in object detection, recognition, identification or classification and/or in response to the detection/prediction of an accident. A cyclic buffer buffers at least a portion of the sensor data stream. In response to the trigger signal, a selected segment of the sensor data stream is stored into a non-volatile memory. The selected segment can be partially before the trigger signal and partially after the trigger signal; and selected segment can be longer than what can be fully buffered in the cyclic buffer at the time of the trigger signal. 1. An autonomous vehicle , comprising:sensors configured to generate a sensor data stream during operations of the autonomous vehicle on a road;an advanced driver assistance system configured to operate the autonomous vehicle on the road based on the sensor data stream, wherein the advanced driver assistance system is further configured to generate a training signal in response to a fault in object detection, recognition, identification or classification;a non-volatile memory;a cyclic buffer configured to buffer the sensor data stream; anda controller configured to receive a training signal and in response, store a first segment of the sensor data stream into the non-volatile memory, wherein the first segment is longer than a second segment of the sensor data stream buffered in the cyclic buffer at the time of the training signal.2. The autonomous vehicle of claim 1 , wherein the first segment includes the second segment.3. The autonomous vehicle of claim 2 , wherein the controller is configured to claim 2 , as a response to the training signal claim 2 , copy the second segment from the ...

Configuring a Host Interface of a Memory Device Based on Mode of Operation

A memory device stores data for a host device. In one approach, a method includes: selecting, by the memory device, a first mode of operation for a host interface that implements a communication protocol for communications between the memory device and the host device. The host interface is configured to implement the communication protocol using a mode selected by the memory device from one of several available modes. In response to selecting the first mode, resources of the memory device are configured to customize the host interface for operation in the first mode. 1. An apparatus comprising:a temperature sensor;a host interface configured to receive commands from a host device;at least one of memory resources or processing resources to process the received commands based on a mode selected from one of a plurality of modes of operation;at least one processing device; and select, based on signaling from the temperature sensor, a first mode of operation; and', 'in response to selecting the first mode, configure the at least one of memory resources or processing resources for operation in the first mode., 'memory containing instructions configured to instruct the at least one processing device to2. The apparatus of claim 1 , wherein the instructions are further configured to instruct the at least one processing device to:analyze at least one of commands or data received from the host device; anddetermine a context of operation based on the analyzing;wherein selecting the first mode is further based on the determined context of operation.3. The apparatus of claim 2 , wherein the temperature sensor is configured in a vehicle claim 2 , and determining the context of operation includes determining that the vehicle is in a crash.4. The apparatus of claim 1 , further comprising an accelerometer claim 1 , wherein selecting the first mode is further based on signaling from the accelerometer.5. The apparatus of claim 1 , wherein the instructions are further configured to ...

EFFICIENT READOUT FROM MEMORY CELLS USING DATA COMPRESSION

A method for data storage includes storing data in a group of analog memory cells by writing respective input storage values to the memory cells in the group. After storing the data, respective output storage values are read from the analog memory cells in the group. Respective confidence levels of the output storage values are estimated, and the confidence levels are compressed. The output storage values and the compressed confidence levels are transferred from the memory cells over an interface to a memory controller.

Independent Management of Data and Parity Logical Block Addresses

A data storage method includes identifying, in a set of data items associated with respective logical addresses for storage in a memory, a first subset of the logical addresses associated with the data items containing application data, and a second subset of the logical addresses associated with the data items containing parity information that has been calculated over the application data. The data items associated with the first identified subset are stored in one or more first physical memory areas of the memory, and the data items associated with the second identified subset are stored in one or more second physical memory areas of the memory, different from the first physical memory areas. A memory management task is performed independently in the first physical memory areas and in the second physical memory areas. 1. An apparatus , comprising:an interface configured to receive at least application data for storage in a memory; and identify, in a set of data items associated with respective logical addresses for storage in the memory, a first subset of the logical addresses associated with the data items that include the application data;', 'identify a second subset of the logical addresses with the data items containing parity information that has been calculated over the application data;', 'store data items associated with the first subset in first physical areas of the memory;', 'store data items associated with the second identified subset in second physical memory areas of the memory, wherein the second physical areas of the memory are different from the first physical areas of the memory; and', 'perform a memory management task independently in the first physical areas of the memory and in the second physical areas of the memory., 'a processor configured to2. The apparatus of claim 1 , wherein the interface is further configured to:accept the set of data items and the respective logical addresses from the host; andprovide the data items and the ...

Automotive Electronic Control Unit Reliability and Safety During Power Standby Mode

Disclosed are devices and methods for improved automotive electronic control unit reliability and safety during power standby mode. In one embodiment, a method is disclosed comprising recording statistics of a dynamic random-access memory in a device, while the device is in a power on state; detecting a command to enter a standby state; analyzing the statistics to determine whether a health check should be performed; powering down the device when determining that a health check should be performed; and placing the device in standby mode when determining that a health check should not be performed. 1. A method comprising:recording statistics of a volatile memory by monitoring operations issued to the volatile memory;detecting a command to enter a standby state;determining, in response to the command, that a health check should be performed based on the statistics; andpowering down in response to the determining, wherein the powering down causes data stored at the volatile memory to be erased.2. The method of claim 1 , wherein recording statistics of a volatile memory comprises incrementing a count of errors corrected by the volatile memory.3. The method of claim 1 , wherein recording statistics of a volatile memory comprises incrementing a count of memory leaks occurring in the volatile memory.4. The method of claim 3 , wherein incrementing the count of memory leaks occurring in the volatile memory comprises:receiving a report of memory usages of one or more currently active processes; andidentifying a memory leak if the memory usage of an active process has increased when compared to previously recorded memory usages of the active process.5. The method of claim 3 , wherein determining that the health check should be performed comprises determining if the count of memory leaks is greater than zero.6. The method of claim 2 , wherein determining that the health check should be performed comprises determining if the count of errors is greater than a pre-determined ...

Black Box Data Recorder for Autonomous Driving Vehicle

An improved black box data recorder for use with autonomous driving vehicles (AVD). In one embodiment, two cyclic buffers are provided to record vehicle sensors data. A first cyclic buffer records raw vehicle sensor data on a volatile memory, while a second cyclic buffer records the same vehicle sensor data, as compressed data, on a non-volatile memory. In a case of a collision or near collision, in one embodiment the buffers are flushed into a non-volatile (NV) storage for retrieval. As long as there is no power interruption, the raw vehicle sensor data will be accessible from the NV storage. If a power interruption occurs, the raw vehicle sensor data held in the volatile memory of the first cyclic buffer will be lost and only the compressed form of the vehicle sensor data from the NV second cyclic buffer will survive and be accessible. 1. A data recording unit for an autonomous driving vehicle comprising:A first cyclic buffer comprising of volatile memory to hold raw vehicle sensor data collected from vehicle sensors, wherein if power to the first cyclic buffer is interrupted the data held in the first cyclic buffer is lost;A data compression unit to perform compression on the raw vehicle sensor data collected from the vehicle sensors and generate compressed vehicle sensor data; andA second cyclic buffer comprising non-volatile memory, coupled to the data compression unit, to hold the compressed vehicle sensor data, wherein if power to the second cyclic buffer is interrupted the data held in the second cyclic buffer is retained.2. The data recording unit of claim 1 , further comprising a non-volatile storage coupled to the first cyclic buffer and second cyclic buffer claim 1 , to store the raw vehicle sensor data and store the compressed vehicle sensor data claim 1 , wherein in response to an event claim 1 , data held in the first and second cyclic buffers are flushed into the non-volatile storage.3. The data recording unit of claim 1 , wherein in response to the ...

Deferred error code correction with improved effective data bandwidth performance

A deferred error correction code (ECC) scheme for memory devices is disclosed. In one embodiment, a method is disclosed comprising starting a deferred period of operation of a memory system in response to detecting the satisfaction of a condition; receiving an operation during the deferred period, the operation comprising a read or write operation access one or more memory banks of the memory system; deferring ECC operations for the operation; executing the operation; detecting an end of the deferred period of operation; and executing the ECC operations after the end of the deferred period.

TWO-STAGE FLASH PROGRAMMING FOR EMBEDDED SYSTEMS

Disclosed are devices and methods for improving the initialization of devices housing memories. In one embodiment, a method is disclosed comprising writing a test program to a first region of a memory device during production of the memory device; executing a self-test program in response to detecting a first power up of the memory device, the self-test program stored within the test program; and retrieving and installing an image from a remote data source in response to detecting a subsequent power up of the memory device, the retrieving performed by the test program.

EFFICIENT ENFORCEMENT OF COMMAND EXECUTION ORDER IN SOLID STATE DRIVES

A method in a storage device includes receiving from a host storage commands for execution in a non-volatile memory of the storage device. At least a subset of the storage commands are to be executed in accordance with an order-of-arrival in which the storage commands in the subset are received. The received storage commands are executed in the non-volatile memory in accordance with internal scheduling criteria of the storage device, which permit deviations from the order-of-arrival, but such that execution of the storage commands in the subset reflects the order-of-arrival to the host. 1. An apparatus , comprising:a memory;a host interface configured to receive a plurality of commands for execution on the memory; assign a respective sequence number to each command of a first subset of the plurality of commands, wherein the respective sequence number corresponds to an order in which each command of the first subset is received;', 'execute each command of the first subset in accordance with an internal scheduling criteria; and', 'send, via the host interface, an acknowledgement that a given command of the first subset has been executed in response to a determination that each command of the first subset with a respective sequence number less than the respective sequence number for the given command has been successfully executed., 'a processor configured to2. The apparatus of claim 1 , wherein to execute each command of the first subset claim 1 , the processor is further configured to store claim 1 , in the memory claim 1 , corresponding data along with the respective sequence number for each executed command.3. The apparatus of claim 2 , wherein the processor is further configured to claim 2 , upon recovery from a power disruption claim 2 , identify a first number of a gap in the respective sequence numbers stored in the memory.4. The apparatus of claim 3 , wherein the processor is further configured to:invalidate data stored in the memory that corresponds to each ...

SELECTION OF REDUNDANT STORAGE CONFIGURATION BASED ON AVAILABLE MEMORY SPACE

A method includes, in a memory controller that controls a memory, evaluating an available memory space remaining in the memory to write data. A redundant storage configuration is selected in the memory controller depending on the available memory space. Redundancy information is calculated over the data using the selected redundant storage configuration. The data and the redundancy information are written to the available memory space in the memory. 1. An apparatus , comprising:an interface coupled to a memory, wherein the memory includes at least one Redundant Array of Independent Disks (RAID) stripe, wherein the at least one RAID stripe includes a first set of blocks, and a second set of blocks; and determine an amount of space available in the memory for storing new data;', 'increase a number of blocks in the first set of blocks in response to a determination that the amount of space available in the memory for storing new data is less than a predefined threshold value;', 'calculate redundancy information for data to be stored in the at least one RAID stripe; and', 'store the data in the first set of blocks and the redundancy information in the second set of blocks., 'a processor configured to2. The apparatus of claim 1 , wherein to increase the number of blocks in the first set of blocks claim 1 , the processor is further configured to reassign a block from the second set of blocks to the first set of blocks.3. The apparatus of claim 1 , wherein the processor is further configured to select a code rate for an Error Correction Code (ECC) dependent upon the amount of space available for storing new data.4. The apparatus of claim 3 , wherein to calculate the redundancy information claim 3 , the processor is further configured to calculate the ECC using the code rate.5. The apparatus of claim 1 , wherein to calculate the redundancy information the processor is further configured to calculate a bit-wise XOR for the data to be stored in the first set of blocks.6. The ...

Determining Autonomous Vehicle Status Based on Mapping of Crowdsourced Object Data

A map in a cloud service stores physical objects previously detected by other vehicles that have previously traveled over the same road that a current vehicle is presently traveling on. New data received by the cloud service from the current vehicle regarding new objects that are being encountered by the current vehicle can be compared to the previous object data stored in the map. Based on this comparison, an operating status of the current vehicle is determined. In response to determining the status, an action such as terminating an autonomous navigation mode of the current vehicle is performed.

AUTOMOTIVE ELECTRONIC CONTROL UNIT PRE-BOOTING FOR IMPROVED MAN MACHINE INTERFACE PERFORMANCE

Disclosed are devices and methods for improving the pre-booting of electronic control unit devices in vehicles. In one embodiment, a method is disclosed comprising detecting a triggering of a pre-booting condition based on one or more interactions with a vehicle; transmitting a power-on signal to at least one electronic control unit (ECU) in the vehicle, the at least one ECU operating in a low-power state; and fully booting the at least one ECU upon determining that the vehicle has been started 1. A method comprising:detecting a triggering of a pre-booting condition based on one or more interactions with a vehicle;transmitting a power-on signal to at least one electronic control unit (ECU) in the vehicle, the at least one ECU operating in a low-power state; andfully booting the at least one ECU upon determining that the vehicle has been started.2. The method of claim 1 , further comprising powering off the at least one ECU upon determining that the vehicle has not been started.3. The method of claim 1 , the detecting a triggering of a pre-booting condition comprising one or more of:detecting a door unlock signal;detecting a change in weight of a seat of the vehicle;detecting a person nearby to the vehicle;detecting an over-the-air command received by an ECU of the vehicle; orpolling a behavioral model using the current day and time.4. The method of claim 3 , the detecting a door unlock signal comprising:detecting if a driver's side door received the door unlock signal and pre-booting critical driver ECUs in response;detecting if a passenger door received the door unlock signal and pre-booting additional ECUs in response; ordetecting if a trunk received the door unlock signal and delaying pre-booting of an ECU in response.5. The method of claim 3 , the detecting a change in weight of a seat of the vehicle comprising detecting if a current weight exceeds a pre-determined threshold.6. The method of claim 3 , the polling a behavioral model using the current day and time ...

AUTOMOTIVE ELECTRONIC CONTROL UNIT RELIABILITY AND SAFETY DURING POWER STANDBY MODE

Disclosed are devices and methods for improved automotive electronic control unit reliability and safety during power standby mode. In one embodiment, a method is disclosed comprising periodically recording memory statistics of a dynamic random-access memory in a device, while the device is in a power on state; detecting a command to enter a standby state; analyzing the memory statistics to determine whether a health check should be performed; powering down the device when determining that a health check should be performed; and placing the device in standby mode when determining that a health check should not be performed. 1. A method comprising:periodically recording memory statistics of a dynamic random-access memory (DRAM) in a device, while the device is in a power on state;detecting a command to enter a standby state;analyzing the memory statistics to determine whether a health check should be performed;powering down the device when determining that a health Check should be performed; andplacing the device in standby mode when determining that a wealth check should not be performed.2. The method of claim 1 , the periodically recording memory statistics of a dynamic random-access memory comprising incrementing a count of errors corrected by the DRAM3. The method of claim 1 , the periodically recording memory statistics of a dynamic random-access memory comprising incrementing a count of memory leaks occurring in the DRAM.4. The method of claim 3 , the incrementing a count of memory leaks occurring in the DRAM comprising:receiving a report of memory usages of one or more currently active processes; andidentifying a memory leak if the memory usage of an active process has increased when compared to previously recorded memory usages of the active process.5. The method of claim 3 , the analyzing the memory statistics to determine whether a health check should be performed comprising determining if the count of memory leaks is greater than zero.6. The method of ...

IDENTIFYING SUSPICIOUS ENTITIES USING AUTONOMOUS VEHICLES

Systems and methods for identifying suspicious entities using autonomous vehicles are disclosed. In one embodiment, a method is disclosed comprising identifying a suspect vehicle using at least one digital camera equipped on an autonomous vehicle; identifying a set of candidate autonomous vehicles; enabling, on each of the candidate autonomous vehicles, a search routine, the search routine instructing each respective autonomous vehicle to coordinate tracking of the suspect vehicle; recording, while tracking the suspect vehicle, a plurality of images of the suspect vehicle; periodically re-calibrating the search routines executed by the autonomous vehicles based on the plurality of images; and re-routing the autonomous vehicles based on the re-calibrated search routines. 1. A method comprising:receiving an identification of a suspect vehicle;identifying a set of candidate autonomous vehicles near the suspect vehicle;instructing one or more of the candidate autonomous vehicles to coordinate tracking of the suspect vehicle;recording, by one or more candidate autonomous vehicles, a plurality of images; andre-routing the autonomous vehicles based on identifying the suspect vehicle in one or more of the plurality of images.2. The method of claim 1 , wherein re-routing the autonomous vehicles comprises terminating the routing of a given autonomous vehicle if an image recorded by the given autonomous vehicle does not include the suspect vehicle.3. The method of claim 1 , wherein re-routing the autonomous vehicles comprises transmitting updated routing information to a given autonomous vehicle if an image recorded by the given autonomous vehicle includes the suspect vehicle.4. The method of claim 1 , wherein receiving an identification of a suspect vehicle comprises receiving an image captured by a digital camera installed in one of the candidate autonomous vehicles and analyzing the image using a deep neural network.5. The method of claim 1 , wherein the deep neural network ...

Vehicle Navigation Using Object Data Received from Other Vehicles

A method includes: receiving, by a computing device, object data regarding a first object detected by a first vehicle, the object data including an object type and a location; storing the object data; generating, based on the object data, navigation data; and sending the navigation data to a second vehicle, the navigation data for use by the second vehicle to control navigation.

Detecting Road Conditions Based on Braking Event Data Received from Vehicles

Data is received regarding vehicle braking events, each event occurring on one of a plurality of vehicles, and each event associated with a location. A determination is made that the braking events correspond to a pattern. Based on determining that the braking events correspond to the pattern, a first location is identified. In response to identifying the first location, at least one action is performed. 1. A system comprising:at least one processor; and receive data regarding braking events, each event occurring on one of a plurality of vehicles, and each event associated with a location;', 'determine that the braking events correspond to a pattern;', 'identify, based on determining that the braking events correspond to the pattern, a first location; and', 'in response to identifying the first location, perform at least one action., 'memory storing instructions configured to instruct the at least one processor to2. The system of claim 1 , wherein determining that the braking events correspond to the pattern comprises comparing a deceleration of the respective vehicle for each of the braking events to a predetermined threshold.3. The system of claim 1 , wherein determining that the braking events correspond to the pattern comprises at least one of:determining that the respective location for each of the braking events is within a predetermined distance of the first location; ordetermining that a distance between the respective locations for the braking events is within a predetermined value.4. The system of claim 1 , wherein each of the braking events corresponds to activation of at least one of an automatic emergency braking system or an anti-lock braking system of the respective vehicle.5. The system of claim 1 , wherein determining that the braking events correspond to the pattern comprises comparing a measurement associated with activation of a braking system of the respective vehicle to a predetermined threshold.6. The system of claim 5 , wherein the ...

Dynamic Memory Refresh Interval to Reduce Bandwidth Penalty

A dynamic memory system having multiple memory regions respectively storing multiple types of data. A controller coupled to the dynamic memory system via a communication channel and operatively to: monitor usage of a communication bandwidth of the communication channel; determine to reduce memory bandwidth penalty caused by refreshing the dynamic memory system; and in response, reduce a refresh rate of at least one of the memory regions based on a type of data stored in the respective memory region.

INTERRUPT-DRIVEN CONTENT PROTECTION OF A MEMORY DEVICE

The disclosed embodiments describe methods, devices, and computer-readable media for protecting the integrity of volatile memory devices. In one embodiment, a method is disclosed comprising detecting a power interrupt condition of a memory device; and executing at least one operation in response to detecting the power interrupt condition, the operation selected from the group of operations consisting of: placing the memory device in a pre-charge mode, pausing a self-refresh mode of the memory device, forcing the memory device into a reset mode, or rewriting data in the memory device. 1. A method comprising:detecting a power interrupt condition of a memory device; and placing the memory device in a pre-charge mode,', 'pausing a self-refresh mode of the memory device,', 'forcing the memory device into a reset mode, or', 'rewriting data in the memory device., 'executing at least one operation in response to detecting the power interrupt condition, the operation selected from the group of operations consisting of2. The method of claim 1 , the detecting the power interrupt condition comprising detecting a drop in voltage of the memory device.3. The method of claim 1 , the detecting the power interrupt condition comprising detecting the power interrupt condition while the memory device is in standby or normal mode.4. The method of claim 1 , the detecting the power interrupt condition comprising detecting the power interrupt condition of a dynamic random-access memory device.5. The method of claim 1 , the placing the memory device in the pre-charge mode comprising placing each row of the memory device in the pre-charge mode.6. The method of claim 1 , the pausing the self-refresh mode of the memory device comprising pausing the self-refresh mode for a predefined period of time claim 1 , the predefined period time set based on the data retention time of cells of the memory device.7. The method of claim 1 , the forcing the memory device into the reset mode comprising forcing ...

MEMORY DEVICE WITH CRYPTOGRAPHIC KILL SWITCH

The disclosed embodiments describe devices and methods for preventing unauthorized access to memory devices. The disclosed embodiments utilize a one-time programmable (OTP) memory added to both a memory device and a processing device. The OTP memory stores encryption keys and the encryption and decryption of messages between the two devices are used as a heartbeat to determine that the memory device has not been separated from the processing device and, in some instances, connected to a malicious processing device. 1. A method comprising:transmitting, by a memory device, an encrypted command to a processing device;receiving, by the memory device, a response from the processing device;decrypting, by the memory device, the response;detecting, by the memory device, that the decrypting failed; anddisabling, by the memory device, a command/address interface in response to detecting that the decrypting failed.2. The method of claim 1 , further comprising generating the encrypted command by encrypting a plaintext command using a shared private key.3. The method of claim 2 , the decrypting the response comprising decrypting the response using the shared private key.4. The method of claim 1 , further comprising generating the encrypted command by encrypting a plaintext command using a public key.5. The method of claim 4 , the decrypting the response comprising decrypting the response using a private key corresponding to the public key.6. The method of claim 1 , the disabling the command/address interface causing the memory device to ignore any instructions transmitted over the command/address interface.7. The method of further comprising scrubbing one or more memory banks upon detecting a successful decryption after detecting that the decrypting failed.8. The method of claim 1 , the detecting that the decrypting failed further comprising determining whether the response is valid or invalid.9. A device comprising:a memory array;control logic communicatively coupled to the ...

Adapted scanning window in image frame of sensor for object detection

A scanning window is used to scan an image frame of a sensor when doing object detection. In one approach, positions within the image frame are stored in memory. Each position corresponds to an object detection at that position for a prior frame of data. A first area of the image frame is determined based on the stored positions. When starting to analyze a new frame of data, the first area is scanned to detect at least one object. After scanning within the first area, at least one other area of the new image frame is scanned.

SEPARATE PARTITION FOR BUFFER AND SNAPSHOT MEMORY

A system includes a processing device and trigger circuitry to signal the processing device responsive, at least in part, based on a determination that a trigger event has occurred. The system can further include a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion having a first endurance characteristic and a first reliability characteristic associated therewith. The memory device can further include a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can have a second endurance characteristic and a second reliability characteristic associated therewith. The processing device can perform operations including writing received data sequentially to the cyclic buffer partition portion and writing, based at least in part on the determination that the trigger event has occurred, data from the cyclic buffer partition portion to the snapshot partition portion. 1. A system comprising:a processing device;trigger circuitry to signal the processing device responsive, at least in part, based on a determination that a trigger event has occurred; and a cyclic buffer partition portion having a first endurance characteristic and a first reliability characteristic associated therewith; and', writing received data sequentially to the cyclic buffer partition portion to provide real time buffering of the received data such that older received data is overwritten with newly received data after a capacity of the cyclic buffer partition portion is reached; and', 'writing, based at least in part on the determination that the trigger event has occurred, data from the cyclic buffer partition portion to the snapshot partition portion., 'a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors, the snapshot partition portion having a second endurance characteristic and a second reliability ...

AUTOMATIC OPERATING MODE MANAGEMENT FOR MEMORY USING WORKLOAD PROFILE DATA

The disclosed embodiments relate to logging activities of memory devices and adjusting the operation of a controller based on the activities. In one embodiment, a method comprises monitoring, by a memory device, die temperatures and data sizes of commands issued to the memory device; determining, by the memory device, a target size for a buffer based on the die temperatures and data sizes; and adjusting, by the memory device, a current size of the buffer to meet the target size.

WORKLOAD PROFILE DATA AND PERFORMANCE-BASED MEMORY MANAGEMENT

The disclosed embodiments relate to logging activities of memory devices and adjusting the operation of a controller based on the activities. In one embodiment, a method comprises collecting, by a memory device, profile data, the profile data associated with read and write commands and corresponding address information issued to the memory device from a host device; storing, by the memory device, the profile data in a portion of a storage array managed by the memory device; receiving, by the memory device, an update generated based on the profile data, the update adjusting a configuration setting of the memory device; and processing, by the memory device, a received command based on the configuration setting. 1. A method comprising:collecting, by a memory device, profile data, the profile data associated with read and write commands and corresponding address information issued to the memory device from a host device;storing, by the memory device, the profile data in a portion of a storage array managed by the memory device;updating, by the memory device, a configuration setting based on the profile data; andprocessing, by the memory device, a received command based on the configuration setting.2. The method of claim 1 , wherein updating the configuration setting comprises generating claim 1 , by the memory device claim 1 , the configuration setting based on the profile data.3. The method of claim 2 , wherein collecting the profile data comprises adding a timestamp to the commands as the commands are received.4. The method of claim 2 , wherein collecting the profile data comprises adding a timestamp to the commands after the commands are executed by the memory device.5. The method of claim 1 , wherein collecting the profile data further includes recording a temperature of the memory device.6. The method of claim 1 , further comprising identifying the portion of the storage array by identifying an unused portion of the storage array.7. The method of claim 1 , further ...

GENERATING ICE HAZARD MAP BASED ON WEATHER DATA TRANSMITTED BY VEHICLES

Systems, methods, and apparatus related to determining ice hazards on roads based on crowdsourced data from vehicles. In one approach, a server receives weather data and location data from each of several vehicles. The weather data is timestamped when received. The server determines, using the location data, a geographic region in which each vehicle is located. The weather data is stored in a database associated with the respective geographic region for the vehicle that transmitted the weather data. The server periodically scans the database to select weather data received over a selected time period. The selected data is analyzed to determine whether an ice hazard exists for one or more regions. A communication is sent to vehicles in those regions having the determined ice hazard.

MANAGED NAND FLASH MEMORY REGION CONTROL AGAINST ENDURANCE HACKING

The disclosed embodiments are directed to improving the lifespan of a memory device. In one embodiment, a system is disclosed comprising: a host processor and a memory device, wherein the host processor is configured to receive a write command from a virtual machine, identify a region identifier associated with the virtual machine, augment the write command with the region identifier, and issue the write command to the memory device, and the memory device is configured to receive the write command, identify a region comprising a subset of addresses writable by the memory device using a region configuration table, and write the data to an address in the subset of addresses. 120-. (canceled)21. A system comprising:a host processor and a memory device, wherein:the host processor is configured to receive a write command from a virtual machine, augment the write command with a region identifier, and issue the write command to the memory device, andthe memory device is configured to identify a region of a storage array using the region identifier and write data to an address in the region.22. The system of claim 21 , wherein host processor comprises a hypervisor.23. The system of claim 21 , wherein the memory device comprises a solid-state device (SSD).24. The system of claim 23 , the memory device further comprising a NAND Flash memory array.25. The system of claim 21 , wherein the host processor maps a plurality of virtual machines to a plurality of corresponding region identifiers claim 21 , wherein at least two of the plurality of virtual machines are mapped to a same region identifier.26. The system of claim 21 , wherein the host processor maps a plurality of virtual machines to a plurality of unique corresponding region identifiers.27. The system of claim 21 , wherein the host processor is configured to augment the write command with the region identifier by inserting the region identifier into a configuration section of the write command.28. The system of claim 21 ...

Sensor fusion to determine reliability of autonomous vehicle operation

A method for an autonomous vehicle includes: receiving first object data from a first sensor module; receiving second object data from a second sensor module; comparing the first object data to the second object data; determining, based on comparing the first object data to the second object data, whether the first object data corresponds to the second object data; and in response to determining that the first object data does not correspond to the second object data, performing an action for the autonomous vehicle.

Laboratory mill

Proces for producing trialkylisocyanurates

Estimation of non-linear distortion in memory devices

A method for operating a memory ( 24 ) includes storing data in analog memory cells ( 32 ) of the memory by writing respective analog values to the analog memory cells. A set of the analog memory cells is identified, including an interfered cell having a distortion that is statistically correlated with the respective analog values of the analog memory cells in the set. A mapping is determined between combinations of possible analog values of the analog memory cells in the set and statistical characteristics of composite distortion levels present in the interfered memory cell. The mapping is applied so as to compensate for the distortion in the interfered memory cell.

Data storage with incremental redundancy

A method for operating a memory includes encoding input data with an Error Correction Code (ECC) to produce input encoded data including first and second sections, such that the ECC is decodable based on the first section at a first redundancy, and based on both the first and the second sections at a second redundancy that is higher than the first redundancy. Output encoded data is read and a condition is evaluated. The input data is reconstructed using a decoding level selected, responsively to the condition, from a first level, at which a first part of the output encoded data corresponding to the first section is processed to decode the ECC at the first redundancy, and a second level, at which the first part and a second part of the output encoded data corresponding to the second section are processed jointly to decode the ECC at the second redundancy.