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Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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26-01-2018 дата публикации

DEVICE AND METHOD FOR CHARACTERIZING SAMPLES BY IMAGING SPECTROSCOPY PWR

Номер: FR0003054320A1
Автор: HARTE ETIENNE, IHRKE IVO, ELEZGARAY JUAN, ALVES ISABEL, LECOMTE SOPHIE
Принадлежит: UNIVERSITE DE BORDEAUX, INSTITUT POLYTECHNIQUE DE BORDEAUX, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE - CNRS -, INRIA - INSTITUT NATIONAL DE LA RECHERCHE EN INFORMATIQUE ET EN AUTOMATIQUE, INSTITUT D'OPTIQUE GRADUATE SCHOOL

La présente invention concerne un dispositif et un procédé pour la mesure par spectroscopie d'un échantillon dans lequel on réalise les étapes suivantes: - envoyer un faisceau lumineux vers une surface (12) d'incidence d'un capteur optique, ledit faisceau lumineux formant un angle d'incidence avec ladite surface d'incidence, ledit faisceau lumineux comportant des ondes électromagnétiques p-polarisées et des ondes électromagnétiques s-polarisées, - ledit capteur optique comprenant un prisme (13) comportant une surface de réflexion, un premier film (15) conducteur ou semi-conducteur et un deuxième film (16) diélectrique pour générer deux modes guidés, un premier desdits modes guidés étant généré pour des ondes électromagnétiques p-polarisées et pour un premier angle d'incidence Qi dudit faisceau lumineux sur ladite surface (12) d'incidence et un second desdits modes guidés étant généré pour les ondes électromagnétiques s-polarisés et pour un second angle d'incidence Ω2 dudit faisceau lumineux ...

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Номер записи: 1
19-04-2012 дата публикации

METHODS FOR THE DEPOSITION OF TERNARY OXIDE GATE DIELECTRICS AND STRUCTURES FORMED THEREBY

Номер: US20120091542A1
Автор: BRAZIER MARK R., HATTENDORF Michael L., Kuhn Markus, MCSWINEY Michael L., Metz Matthew V.
Принадлежит:

Methods and associated structures of forming a microelectronic device are described. Those methods may include introducing a first metal source, a second metal source and an oxygen source into a chamber and then forming a ternary oxide film comprising a first percentage of the first metal, a second percentage of the second metal, and a third percentage of oxygen. 1. A structure comprising:a gate oxide comprising a first binary oxide and a second binary oxide, wherein the first binary oxide and the second binary oxide comprise a first metal and a second metal.2. The structure of wherein the first metal and the second metal comprise at least one of Hf claim 1 , Zr claim 1 , Si claim 1 , Al claim 1 , Y claim 1 , a lanthanide Ti claim 1 , and Ta.3. The structure of wherein the gate oxide comprises a mixture of the first binary oxide and the second binary oxide.4. The structure of wherein the thickness of the gate oxide comprises below about 30 angstroms.5. The structure of wherein the gate oxide is disposed on a silicon dioxide layer and a metal gate is disposed on the gate oxide claim 1 , and wherein the gate oxide comprises a high k gate oxide claim 1 , and wherein the silicon dioxide layer is disposed on a channel region of a transistor structure.6. The structure of wherein a percentage of the first metal may comprise about 1 percent to about 99 percent claim 1 , and wherein the gate oxide comprises a concentration gradient in the percentage of the first binary oxide throughout a thickness of the gate oxide.7. The structure of wherein the gate oxide comprises a concentration gradient in the percentage of the first binary oxide throughout a thickness of the gate oxide.8. A structure comprising:a gate oxide comprising a first binary oxide and second binary oxide, wherein the first binary oxide and the second binary oxide comprise a first metal and a second metal, and wherein at least one layer each of the first binary oxide and the second binary oxide are alternately ...

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Номер записи: 2
10-05-2012 дата публикации

Metal-insulator-semiconductor tunneling contacts

Номер: US20120115330A1
Автор: Gilbert Dewey, Jack Kavalieros, Matthew V. Metz, Niloy Mukherjee, Robert S. Chau
Принадлежит: Individual

A contact to a source or drain region. The contact has a conductive material, but that conductive material is separated from the source or drain region by an insulator.

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Номер записи: 3
17-05-2012 дата публикации

Proximally Self-Locking Long Bone Prosthesis

Номер: US20120123554A1
Автор: Matthew V. Fonte
Принадлежит: MX Orthopedics Corp

A femoral stem hip implant for insertion into a surgically created aperture in a femur includes a monolithic femoral stem made of shape memory material. The stem is configured to be inserted into the aperture, has a proximal portion and a longitudinal axis. The shape memory material within the proximal portion has a cross-section perpendicular to the longitudinal axis. At least a portion of the shape memory material within the proximal portion is in a compressed state by application of a plurality of compressive forces at a temperature below an austenitic finish temperature of the shape memory material so that the cross-section expands through shape memory effect via the formation of austenite in response to a temperature increase after insertion into the aperture thereby causing a locking-force to be exerted against an inner surface of the aperture, the locking force being sufficient to stabilize the implant in the aperture.

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Номер записи: 4
24-05-2012 дата публикации

EFFICIENT STRING PATTERN MATCHING FOR LARGE PATTERN SETS

Номер: US20120130983A1
Автор: Hodgkinson Andrew, Ryan Matthew V., Young Russell
Принадлежит: MICROSOFT CORPORATION

A string matching system is described herein that provides for very fast and efficient pattern matching against large sets of certain types of pattern strings. If a set of pattern strings is comprised of strings that can be logically divided into segments, these pattern strings can be stored efficiently in a tree-like data structure, segment by segment, storing pattern-match syntax segments separately from literal string segments. After segmentation, individual match candidate strings are compared, segment by segment, against elements in the tree. The system uses a data structure that is conceptually a combination of a tree and a hash table. Using a hash table to implement the branching elements at each level in the tree contributes to quick matching speed at each level. By consistently separating strings into segments, the system can also share storage locations for like elements in the data structure. 1. A computer-implemented method for determining whether a candidate string matches any string stored in a string data store , the method comprising:receiving a candidate string for which to search the string data store to identify zero or more matches to the candidate string;dividing the received string into one or more segments;selecting a root node of the string data store that identifies an entry to a data structure for efficiently storing a set of strings in a tree-like form;searching the string data store segment-by-segment to identify segments that match the segments of the candidate string; and{'b': '340', 'upon determining that each segment in the candidate string matches a segment stored in the string data store, reporting that the candidate string matches a string stored in the string data store,'}wherein the preceding steps are performed by at least one processor.2. The method of wherein receiving the candidate string comprises receiving the string from an application through an application-programming interface (API) provided by a string matching system. ...

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Номер записи: 5
05-07-2012 дата публикации

METHOD TO REDUCE CONTACT RESISTANCE OF N-CHANNEL TRANSISTORS BY USING A III-V SEMICONDUCTOR INTERLAYER IN SOURCE AND DRAIN

Номер: US20120168877A1
Автор: Chau Robert S., Dewey Gilbert, Metz Matthew V., Mukherjee Niloy, Radosavljevic Marko
Принадлежит:

A method to reduce contact resistance of n-channel transistors by using a III-V semiconductor interlayer in source and drain is generally presented. In this regard, a device is introduced comprising an n-type transistor with a source region and a drain region a first interlayer dielectric layer adjacent the transistor, a trench through the first interlayer dielectric layer to the source region, and a conductive source contact in the trench, the source contact being separated from the source region by a III-V semiconductor interlayer. Other embodiments are also disclosed and claimed. 1. A device , comprising:an n-type transistor with a source region and a drain region;a first interlayer dielectric layer adjacent the transistor;a trench through the first interlayer dielectric layer to the source region; anda conductive source contact in the trench, the source contact being separated from the source region by a III-V semiconductor interlayer.2. The device of claim 1 , wherein the transistor is a multigate transistor including a fin.3. The device of claim 2 , wherein the III-V semiconductor layer is on a top surface and side walls of the fin.4. The device of claim 1 , wherein the III-V semiconductor layer has a thickness of between about 1 and 50 nanometers.5. The device of claim 1 , further comprising:a second interlayer dielectric layer;a first metallization layer adjacent the second interlayer dielectric layer and having a plurality of conductive vias and a plurality of conductive lines;a third interlayer dielectric layer over the second interlayer dielectric layer;a second metallization layer adjacent the third interlayer dielectric layer and having a plurality of conductive vias and a plurality of conductive lines; andwherein at least some of the plurality of conductive vias and the plurality of conductive lines of the first metallization layer and at least some of the plurality of conductive vias and the plurality of conductive lines of the second metallization ...

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Номер записи: 6
02-08-2012 дата публикации

GERMANIUM-BASED QUANTUM WELL DEVICES

Номер: US20120193609A1
Автор: Chau Robert S., Chu-Kung Benjamin, Dewey Gilbert, Jin Been-Yin, Kavalieros Jack T., Kotlyar Roza, Metz Matthew V., Mukherjee Niloy, Pillarisetty Ravi, Rachmady Willy, Radosavljevic Marko
Принадлежит:

A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric. 1. A device , comprising:a lower barrier region comprising a large band gap material;a quantum well channel region comprising germanium on the lower barrier region;an upper barrier region comprising a large band gap material on the quantum well region;a gate dielectric on the quantum well channel region and not in contact with the quantum well channel region;a gate electrode on the gate dielectric; andwherein at least one of the lower barrier region or the upper barrier region comprises a group III-V material.2. The device of claim 1 , wherein the lower barrier region comprises a group III-V material.3. The device of claim 2 , wherein the lower barrier region comprises GaAs.4. The device of claim 1 , wherein one of the lower barrier region or the upper barrier region comprises silicon germanium and does not comprise a group III-V material.5. The device of claim 1 , wherein the lower barrier region comprises silicon germanium and the upper barrier region comprises a group III-V material.6. The device of claim 1 , wherein both the lower barrier region and the upper barrier region comprise a group III-V material.7. The device of claim 1 , further comprising:a spacer region on the quantum well channel region and below the upper barrier region; anda doped region on the spacer region and below the upper barrier region.8. The device of claim 7 , wherein the spacer region claim 7 , the lower barrier region claim 7 , and the upper barrier region all comprise III-V material.9. The device of claim 8 , wherein the doped region comprises a doped III-V material.10. The device of claim 1 , ...

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Номер записи: 7
09-08-2012 дата публикации

EXTREME HIGH MOBILITY CMOS LOGIC

Номер: US20120199813A1
Автор: AmIan Majumdar, Brask Justin K., Chau Robert S., Datta Suman, DOCZY Mark L., Hudait Mantu K., Jin Been-Yih, Kavalieros Jack T., Metz Matthew V.
Принадлежит: Intel Corporation

A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate. 1. A method of manufacturing a CMOS device comprising:forming a PMOS transistor on a substrate, the PMOS transistor having a first quantum well structure;forming an NMOS transistor on the substrate, the NMOS transistor having a second quantum well structure; andforming an isolation layer between the PMOS transistor and the NMOS transistor.2. The method of claim 1 , further comprising:forming a first buffer layer on first portions of the substrate;forming a first bottom barrier layer on the first buffer layer; forming a first quantum well layer on the first bottom barrier layer;forming a first top barrier layer on first quantum well layer;forming a nucleation layer on second portions of the substrate;forming a second buffer layer on the nucleation layer;forming a second bottom barrier layer on the second buffer layer;forming a second quantum well layer on the second bottom barrier layer; andforming a second top barrier layer on the second quantum well layer.3. The method of claim 2 , further comprising:forming a first spacer layer over the first quantum well layer;forming a first delta doped layer over the first spacer layer;forming a second spacer layer over the second quantum well layer; andforming a second delta doped layer over the second spacer layer.4. The method of claim 2 , further comprising:forming a first cap layer over the first top barrier layer; andforming a second cap layer over the second top barrier layer.5. The method of claim 1 , comprising:forming a high-k gate dielectric layer over the first quantum well structure and a high-k gate dielectric layer over the second quantum well structure; andforming metal gate electrodes over the high-k gate dielectric layers.6. A CMOS device claim 1 , comprising:a highly resistive substrate; a PMOS transistor formed on the ...

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Номер записи: 8
06-09-2012 дата публикации

Ergonomic Paint Roller Tray With End Handles

Номер: US20120223085A1
Автор: Bergman Christopher M., Bergman Mark W., Given Jeffrey T., Leyden Matthew V., Waffensmith Jeffrey B.
Принадлежит: Bercom international, LLC

A paint tray includes a cavity defined by a bottom wall, a first side wall, a second side wall, a first end wall, and a second sloping end wall. Each of the first side wall, second side wall, first end wall, and second sloping end wall inclines upwardly and outwardly from the bottom wall. The cavity terminates at a top edge. The paint tray also includes a top tray rim adjacent the top edge of the cavity, a perimeter rim that inclines downwardly and outwardly from the top tray rim, a handle disposed at an edge of the perimeter rim proximate each end wall, and a leg panel extending downwardly and outwardly from each of a first side and a second side of the perimeter rim proximate the second sloping end wall. The leg panel has a bottom edge that is co-planar with the bottom wall. 120-. (canceled)21. A paint tray comprising: 'a second sloping end wall, wherein the cavity terminates at a top edge;', 'a cavity defined by a bottom wall and a plurality of walls extending upwardly from the bottom wall, including, a first end wall and'}a top tray rim adjacent the top edge;a perimeter rim that extends downwardly and outwardly from the top tray rim, wherein the perimeter rim includes an opening proximate each end wall that is defined in part by a handle disposed at a lower edge of the perimeter rim.22. The paint tray of wherein the handle for each opening is aligned between the bottom wall and the top edge.23. The paint tray of wherein each wall of the plurality of walls inclines outwardly from the bottom wall.24. The paint tray of claim 21 , and further comprising a first leg panel extending downwardly from the perimeter rim proximate the second end wall claim 21 , the first leg panel having a bottom edge that is co-planar with the bottom wall.25. The paint tray of claim 24 , and further comprising a second leg panel extending downwardly from the perimeter rim proximate the second end wall claim 24 , the second leg panel having a bottom edge that is co-planar with the bottom ...

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Номер записи: 9
13-09-2012 дата публикации

TWO-WIRE DIMMER SWITCH FOR LOW-POWER LOADS

Номер: US20120230073A1
Автор: Harte Matthew V., Jr. Robert C., Newman, Salvestrini Christopher J.
Принадлежит:

A two-wire load control device (such as, a dimmer switch) for controlling the amount of power delivered from an AC power source to an electrical load (such as, a high-efficiency lighting load) includes a thyristor coupled between the source and the load, a gate coupling circuit coupled between a first main load terminal and the gate of the thyristor, and a control circuit coupled to a control input of the gate coupling circuit. The control circuit generates a drive voltage for causing the gate coupling circuit to conduct a gate current to thus render the thyristor conductive at a firing time during a half cycle of the AC power source, and to allow the gate coupling circuit to conduct the gate current at any time from the firing time through approximately the remainder of the half cycle, where the gate coupling circuit conducts approximately no net average current to render and maintain the thyristor conductive. 1. A load control device for controlling the amount of power delivered from an AC power source to an electrical load , the load control device comprising:a thyristor having first and second main load terminals adapted to be coupled in series electrical connection between the AC power source and the electrical load for conducting a load current from the AC power source to the electrical load, the thyristor having a gate for conducting a gate current to render the thyristor conductive;a gate coupling circuit coupled to conduct the gate current through the gate of the thyristor;a controllable switching circuit coupled between the gate coupling circuit and the gate of the thyristor for conducting the gate current when the controllable switching circuit is conductive; anda control circuit operable to render the controllable switching circuit conductive and to control the gate coupling circuit to conduct the gate current to thus render the thyristor conductive at a firing time during a half cycle of the AC power source, the control circuit continuing to control the ...

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Номер записи: 10
07-03-2013 дата публикации

Stress Induced Crystallographic Phase Transformation and Texturing in Tubular Products Made of Cobalt and Cobalt Alloys

Номер: US20130055612A1
Автор: Fonte Matthew V.
Принадлежит: DYNAMIC FLOWFORM CORP.

A method of producing a superalloy gun barrel includes providing a tubular workpiece made of a cobalt-based superalloy material, the workpiece having at least about 30% by weight of fcc phase and having an inner diameter and an outer diameter. The method further includes placing the workpiece on a mandrel such that the inner diameter is adjacent to the mandrel and compressing the outer diameter of the workpiece at a temperature below a recrystallization temperature of the workpiece using a combination of axial and radial forces so that the mandrel contacts the inner diameter and imparts a compressive hoop stress to the inner diameter of the workpiece. 1. A method of producing a superalloy gun barrel , the method comprising:providing a tubular workpiece having at least about 30% by weight of fcc phase and having an inner diameter and an outer diameter, wherein the workpiece is made of a cobalt-based superalloy material;placing the workpiece on a mandrel such that the inner diameter is adjacent to the mandrel; andcompressing the outer diameter of the workpiece at a temperature below a recrystallization temperature of the workpiece using a combination of axial and radial forces so that the mandrel contacts the inner diameter and imparts a compressive hoop stress to the inner diameter of the workpiece.2. The method of claim 1 , wherein compressing the outer diameter of the workpiece causes at least a portion of the fcc phase to transform to an hcp crystal structure claim 1 , increasing claim 1 , by at least two times claim 1 , an amount of basal planes radially oriented perpendicular to the inner diameter of the workpiece.3. The method of claim 1 , wherein the compressed workpiece forms a liner and further comprising placing the liner on an inner diameter of the gun barrel.4. The method of claim 1 , wherein compressing the outer diameter of the workpiece subjects the workpiece to at least about a 20% wall reduction.5. The method of claim 4 , wherein the workpiece has at ...

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Номер записи: 11
27-06-2013 дата публикации

GATE ELECTRODE HAVING A CAPPING LAYER

Номер: US20130161766A1
Автор: Brask Justin K., Datta Suman, Dewey Gilbert, DOCZY Mark L., Metz Matthew V.
Принадлежит:

A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed. 1. A non-planar semiconductor device , comprising:a substrate having a three-dimensional semiconductor body thereon;a monolayer of an oxide of the three-dimensional semiconductor body, the monolayer disposed directly on the three-dimensional semiconductor body;a high-k dielectric material layer disposed directly on the monolayer, the high-k dielectric material layer including a first portion of a capping layer in vacant sites therein, wherein the monolayer of the oxide of the three-dimensional semiconductor body includes an element not included in the high-k dielectric material layer; anda gate electrode disposed above the high-k dielectric material layer.2. The non-planar semiconductor device of claim 1 , further comprising:a second portion of the capping layer disposed above the high-k dielectric material layer and below the gate electrode.3. The non-planar semiconductor device of claim 2 , wherein the first and second portions of the capping layer comprise silicon.4. The non-planar semiconductor device of claim 2 , further comprising:a barrier layer disposed directly between the high-k dielectric material layer and the second portion of the capping layer.5. The non-planar semiconductor device of claim 1 , wherein the high-k dielectric material layer has a thickness approximately in the range of 5-25 Angstroms.6. The non-planar semiconductor device of claim 1 , wherein the non-planar semiconductor device is a tri-gate transistor.7. A non-planar semiconductor device claim 1 , comprising:a substrate having a three-dimensional semiconductor body thereon;an ultra-thin transition oxide layer disposed on the three-dimensional semiconductor body, the ultra-thin transition oxide layer consisting essentially of a ...

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Номер записи: 12
05-12-2013 дата публикации

METHODS TO ENHANCE DOPING CONCENTRATION IN NEAR-SURFACE LAYERS OF SEMICONDUCTORS AND METHODS OF MAKING SAME

Номер: US20130320417A1
Автор: Chau Robert S., Dewey Gilbert, GOEL Niti, KABEHIE Sanaz, Metz Matthew V., Mukherjee Niloy, Radosavljevic Marko
Принадлежит:

A die includes a semiconductive prominence and a surface-doped structure on the prominence. The surface-doped structure makes contact with contact metallization. The prominence may be a source- or drain contact for a transistor. Processes of making the surface-doped structure include wet- vapor- and implantation techniques, and include annealing techniques to drive in the surface doping to only near-surface depths in the semiconductive prominence. 1. A contact on a semiconductive prominence , comprising:a semiconductive substrate;a prominence disposed on the semiconductive substrate, wherein the prominence is semiconductive;a surface-doped structure on the prominence Wherein the surface-doped structure has a first concentration of a dopant and the prominence has a second concentration of a dopant, and wherein the first concentration of dopant is different than the second concentration of dopant; anda contact metallization coupled to the surface-doped structure, wherein the prominence has a prominence form factor, and wherein the contact metallization contact area reflects the prominence form factor.2. The contact of claim 1 , wherein the prominence is a first prominence claim 1 , further including a second prominence claim 1 , wherein the first- and second prominences are source- and drain contacts of a transistor.3. The contact of claim 1 , wherein the prominence is a first prominence claim 1 , further including a second prominence claim 1 , wherein the first- and second prominences are source- and drain contacts of a transistor that are spaced apart by a gate structure.4. The contact of claim 1 , wherein the prominence is a first prominence claim 1 , further including a second prominence claim 1 , wherein the first- and second prominences are source- and drain contacts of a transistor that are spaced apart by a gate structure claim 1 , and father including a contact interconnect is disposed in a first interconnect ILD layer claim 1 , wherein the contact ...

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Номер записи: 13
12-12-2013 дата публикации

EXTREME HIGH MOBILITY CMOS LOGIC

Номер: US20130328015A1
Автор: AmIan Majumdar, Brask Justin K., Chau Robert S., Datta Suman, DOCZY Mark L., Hudait Mantu K., Jin Been-Yih, Kavalieros Jack T., Metz Matthew V.
Принадлежит:

A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate. 1. An NMOS transistor , comprising:an indium phosphide (InP) substrate;an indium aluminum arsenide (InAlAs) buffer layer disposed above the InP substrate;a bottom barrier layer disposed above the InAlAs barrier layer;an indium arsenide (InAs) quantum well layer disposed above the bottom barrier layer;a top barrier layer disposed above the InAs quantum well layer;a gate stack disposed above the top barrier layer, the gate stack comprising:{'sub': 2', '3, 'an aluminum oxide (AlO) high-k gate dielectric layer disposed above the top barrier layer; and'}{'sub': 2', '3, 'a metal gate electrode disposed above the AlOhigh-k gate dielectric layer; and'}raised source and drain regions disposed above an etch stop layer disposed above the top barrier layer, the raised source and drain regions disposed on either side of the gate stack.2. The NMOS transistor of claim 1 , wherein the raised source and drain regions are formed in an indium gallium arsenide (InGaAs) cap layer disposed above the etch stop layer.3. The NMOS transistor of claim 2 , wherein the InGaAs cap layer has a thickness approximately in the range of 10-50 nanometers.4. The NMOS transistor of claim 1 , further comprising:source/drain metal contacts disposed on each of the raised source and drain regions, the source/drain metal contacts comprising titanium (Ti).5. The NMOS transistor of claim 1 , wherein the etch stop layer comprises indium phosphide (InP).6. The NMOS transistor of claim 1 , wherein the etch stop layer has a thickness approximately in the range of 1-5 nanometers.7. The NMOS transistor of claim 1 , wherein the AlOhigh-k gate dielectric layer has a thickness approximately in the range of 1.5-7.5 nanometers.8. The NMOS transistor of claim 1 , further comprising:a silicon (Si) delta-doping layer disposed proximate ...

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Номер записи: 14
19-12-2013 дата публикации

Quantum-well-based semiconductor devices

Номер: US20130337623A1
Автор: Gilbert Dewey, Marko Radosavljevic, Matthew V. Metz, Ravi Pillarisetty, Robert S. Chau
Принадлежит: Intel Corp

Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.

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Номер записи: 15
26-12-2013 дата публикации

AUTOMATED ORTHOTIC DEVICE WITH TREATMENT REGIMEN AND METHOD FOR USING THE SAME

Номер: US20130345612A1
Автор: Bannister Ed, Barnhouse Jeffery W., Berger John W., Chan Sai Chung, Ghosh Dipankar, Lucero Roberto A., Martin Michael L., Villa Oscar A., Waidelich Matthew V.
Принадлежит: Bio Cybernetics International, Inc.

An automated orthotic device with a treatment regimen and a method for using an automated orthotic device with a treatment regimen to provide a plurality of prescribed tension settings. The orthotic device may comprise a body brace, a controller, a data storage means, and a communication means to address the problem of patients being required to visit the physician's office every time an adjustment must be made in the prescribed tension setting in their automated orthotic device. In one embodiment, a plurality of prescribed tension settings in the automated orthotic device are sorted so that as the patient's condition improves, the next prescribed tension setting in the treatment regimen may be applied. In another embodiment, the physician is allowed to edit or supplement a patient's treatment regimen remotely by connecting to the automated orthotic device over a network. 1. An automated orthotic device with a treatment regimen program comprising:a body brace configured to be worn around a portion of a human body;a data storage means; anda controller, whereinthe data storage means is configured to store a treatment regimen program that has been determined by a physician, the treatment regimen program comprising a plurality of prescribed tension settings to be carried out in a specified order, andthe controller is configured to carry out the treatment regimen program by causing the body brace to apply each of the plurality of prescribed tension settings according to the specified order of the treatment regimen program.2. The automated orthotic device of wherein the treatment regimen program further comprises a set period of time associated with each of the plurality of prescribed tension settings claim 1 , and wherein the controller is further configured to carry out the treatment regimen program by(1) causing the body brace to apply a first prescribed tension setting for the set period of time associated with the first prescribed tension setting, and then(2) ...

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Номер записи: 16
16-01-2014 дата публикации

HAND-HELD VESSEL

Номер: US20140014670A1
Автор: Bergman Mark W., Leyden Matthew V., Waffensmith Jeffrey B.
Принадлежит: Bercom international, LLC

A hand-held vessel has a bottom wall, a sidewall and a supportive strap attached to the bottom wall and the sidewall. The bottom wall and sidewall have an inner and outer surface. The sidewall extends from the bottom wall, whereby the inner surfaces of the bottom wall and sidewall define a cavity for holding fluids or loose materials therein. The strap has a first end and a second end, whereby the first end is fixedly attached to the sidewall and the second end is selectively secured to the bottom wall. The strap is adaptable to accept a user's hand disposed between the strap and the outer surface of the sidewall. The strap urges the hand against the outer surface of the sidewall to secure the vessel to the hand and stabilize the vessel with respect to movement relative to the hand. 1. A hand-held vessel comprising:a bottom wall having an inner surface and an outer surface;a sidewall extending from the bottom wall, the sidewall having an inner surface and an outer surface, wherein the inner surfaces of the bottom wall and the sidewall define a fluid holding cavity; anda strap having a first end and a second end, wherein the first end is connected to the outer surface of the sidewall and the second end is connectable to the outer surface of the bottom wall.2. The hand-held vessel of claim 1 , wherein the second end of the strap is connectable to a plurality of locations along the outer surface of the bottom wall.3. The hand-held vessel of claim 2 , wherein the outer surface of the bottom wall comprises one or more protrusions claim 2 , and wherein the second end of the strap comprises one or more holes engagable with the protrusions.4. The hand-held vessel of claim 1 , wherein a lower portion of the sidewall extends beyond the outer surface of the bottom wall in a direction substantially normal to the outer surface of the bottom wall.5. The hand-held vessel of claim 4 , wherein the lower portion of the sidewall defines a cutout for receiving the second end of the ...

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Номер записи: 17
06-03-2014 дата публикации

GERMANIUM-BASED QUANTUM WELL DEVICES

Номер: US20140061589A1
Автор: Chau Robert S., Chu-Kung Benjamin, Dewey Gilbert, Jin Been-Yin, Kavalieros Jack T., Kotlyar Roza, Metz Matthew V., Mukherjee Niloy, Pillarisetty Ravi, Rachmady Willy, Radosavljevic Marko
Принадлежит:

A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric. 1. A device , comprising:a lower barrier region comprising a large band gap material;a quantum well channel region comprising germanium on the lower barrier region;an upper barrier region comprising a large band gap material on the quantum well region;a spacer region on the quantum well channel region;an etch stop region on the spacer region, the etch stop region comprising silicon and being substantially free from germanium;a gate dielectric on the etch stop region;a gate electrode on the gate dielectric.2. The device of claim 1 , wherein the spacer region comprises silicon germanium.3. The device of claim 1 , wherein the gate dielectric is directly on the etch stop region.4. The device of claim 1 , wherein the etch stop region comprises a first portion comprising silicon and a second portion on the first portion.5. The device of claim 4 , wherein the second portion comprises silicon dioxide.6. The device of claim 5 , wherein the gate dielectric is directly on the second portion of the etch stop region.7. The device of claim 1 , wherein the etch stop region has a thickness of less than twenty angstroms.8. The device of claim 1 , further comprising:a doped region on the lower barrier region, the doped region comprising silicon germanium doped with boron; anda lower spacer region comprising silicon germanium on the doped region and under the quantum well channel region.9. The device of claim 1 , wherein the lower barrier region and the upper barrier region each comprises silicon germanium.10. The device of claim 1 , wherein the lower barrier region comprises a group III-V ...

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Номер записи: 18
03-04-2014 дата публикации

TRENCH CONFINED EPITAXIALLY GROWN DEVICE LAYER(S)

Номер: US20140091360A1
Автор: Chau Robert S., DASGUPTA Sansaptak, Dewey Gilbert, GOEL Niti, Kavalieros Jack T., Le Van H., Metz Matthew V., Mukherjee Niloy, Pillarisetty Ravi, Rachmady Willy, Radosavljevic Marko, SUNG Seung Hoon, Then Han Wui
Принадлежит:

Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric. In embodiments, non-planar devices CMOS devices having high carrier mobility may be made from the semiconductor device layer. 1. A method of forming a heteroepitaxial device layer on a substrate , the method comprising:receiving a substrate with a semiconductor seeding surface;forming a hardmask fin over the seeding surface;forming an isolation region adjacent the hardmask fin;forming a trench with the seeding surface at the bottom of the trench by removing the hardmask fin; andepitaxially growing a semiconductor layer within the trench, the semiconductor layer having at least one of a lattice constant mismatch or CTE mismatch with the semiconductor seeding surface.2. The method of claim 1 , wherein forming the hardmask fin further comprises depositing a polycrystalline silicon or a silicon nitride layer over the seeding surface; and patterning the polycrystalline silicon or silicon nitride layer with an anisotropic etch.3. The method of claim 2 , wherein forming the hardmask fin further comprises depositing an etch stop layer directly on the seeding surface ...

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Номер записи: 19
03-04-2014 дата публикации

METHODS OF CONTAINING DEFECTS FOR NON-SILICON DEVICE ENGINEERING

Номер: US20140091361A1
Автор: Chau Robert S., Chu-Kung Benjamin, Dewey Gilbert, GOEL Niti, Kavalieros Jack T., Le Van H., Metz Matthew V., Mukherjee Niloy, Pillarisetty Ravi, Rachmady Willy, Radosavljevic Marko, SUNG Seung Hoon
Принадлежит:

An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor. 1. An apparatus comprising:a semiconductor device comprising a channel material having a first lattice structure on a well of a well material having a matched lattice structure, the well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, wherein the well comprises an aspect ratio of height to width and height to length each greater than 1.5.2. The apparatus of claim 1 , wherein the semiconductor device comprises an n-type metal oxide semiconductor field effect transistor comprising a source region and a drain region of the channel material.3. The apparatus of claim 1 , wherein the channel material is a Group III-V compound semiconductor material.4. The apparatus of claim 3 , wherein the buffer material comprises Germanium.5. The apparatus of claim 1 , wherein the semiconductor device is a first semiconductor device comprising an n-type metal oxide semiconductor field effect transistor claim 1 , the apparatus further comprising a second semiconductor device comprising a p-type metal oxide ...

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Номер записи: 20
03-01-2019 дата публикации

GESTURE-BASED CONTROL DEVICE FOR CONTROLLING AN ELECTRICAL LOAD

Номер: US20190005809A1
Автор: Dimberg Chris, Harte Matthew V., McDonald Matthew Philip, Twaddell Daniel L.
Принадлежит: Lutron Electroncis Co., Inc.

A control device may be configured to control one or more electrical loads in a load control system. The control device may be a wall-mounted device such as dimmer switch, a remote control device, or a retrofit remote control device. The control device may include a gesture-based user interface for applying advanced control over the one or more electrical loads. The types of control may include absolute and relative control, intensity and color control, preset, zone, or operational mode selection, etc. Feedback may be provided on the control device regarding a status of the one or more electrical loads or the control device. 1. A control device configured for use in a load control system to control a plurality of electrical loads external to the control device , the control device comprising:a user input device configured to detect a user input;a plurality of light sources configured to backlight at least a portion of the user input device to display multiple discrete points of illumination each representing a preset associated with the plurality of electrical loads; and illuminate one or more of the plurality of light sources to display the multiple discrete points of illumination;', 'determine that a discrete point of the multiple discrete points of illumination has been selected;', 'control the plurality of light sources to illuminate the selected discrete point in a manner distinguishable from the rest of the multiple discrete points of illumination; and', 'generate control data to control the plurality of electrical loads based on the preset associated with the selected discrete point., 'a control circuit configured to2. The control device of claim 1 , wherein the preset corresponds to at least one predetermined setting of the plurality of electrical loads.3. The control device of claim 2 , wherein the preset corresponds to a combination of multiple predetermined settings associated with the plurality of electrical loads.4. The control device of claim 1 , ...

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Номер записи: 21
02-01-2020 дата публикации

DIELECTRIC LINING LAYERS FOR SEMICONDUCTOR DEVICES

Номер: US20200006501A1
Автор: Ghani Tahir, Gilbert Dewey, HUANG CHENG-YING, Kavalieros Jack T., Ma Sean T., Metz Matthew V., MINUTILLO Nicholas G., Murthy Anand S., Rachmady Willy
Принадлежит: Intel Corporation

Solid-state assemblies including dielectric lining layers having localized charges are provided. Processes to form the solid-state assemblies also are provided. The solid-state assemblies can included in CMOS transistors, where first dielectric lining layers having localized charges of positive polarity can be adjacent to the PMOS member and a second dielectric lining layers having localized charges of positive polarity can be adjacent to an NMOS member. The first dielectric lining layers can be adjacent to a first gate electrode of the CMOS transistor, and the second dielectric lining can be adjacent to a second gate electrode of the CMOS transistor. The first dielectric lining layers and the second dielectric lining layers can improve, at least in part, the performance of the CMOS transistor by attracting mobile carriers into respective transport channels of the PMOS member and the NMOS member. 125-. (canceled)26. A solid assembly , comprising:a carrier-doped semiconductor layer including mobile charges of a first polarity;a dielectric layer including localized charges of a second polarity opposite the first polarity; andan electrode member adjacent to the dielectric layer and further adjacent to the carrier-doped semiconductor layer.27. The solid assembly of claim 26 , wherein the carrier-doped semiconductor layer comprises an n-type III-V semiconductor compound claim 26 , and wherein the second polarity is positive polarity.28. The solid assembly of claim 26 , wherein the carrier-doped semiconductor layer comprises a p-type III-V semiconductor compound claim 26 , and wherein the second polarity is negative polarity.29. The solid assembly of claim 26 , wherein the dielectric layer comprises a low-K material comprising oxygen claim 26 , nitrogen claim 26 , carbon claim 26 , or silicon.30. The solid assembly of claim 26 , wherein the localized charges of the second polarity are arranged within the dielectric layer to an average charge density in a range of 10cmto ...

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Номер записи: 22
02-01-2020 дата публикации

Transistors with non-vertical gates

Номер: US20200006510A1
Автор: Anand S. Murthy, Cheng-Ying Huang, Gilbert Dewey, Harold W. KENNEL, Jack T. Kavalieros, Matthew V. Metz, Sean T. MA, Tahir Ghani, Willy Rachmady
Принадлежит: Intel Corp

In various embodiments, the disclosure describes transistors having non-vertical gates. In one embodiment, the non-vertical gates can have a curved or wide angle gate in order to reduce the electric field crowing on the drain side of the gate edge and/or portions having corners and thereby reduce leakage current in the transistor. In one embodiment, the non-vertical gate can be generated by one or more etching steps (for example, isotropic etching steps) of an underlying channel during the fabrication of a transistor having the non-vertical gate. In one embodiment, the non-vertical gate can be generated by one or more directional etching steps that may expose various facets having predetermined orientations of a source and/or drain associated with the transistor.

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Номер записи: 23
02-01-2020 дата публикации

VERTICAL THIN FILM TRANSISTORS HAVING SELF-ALIGNED CONTACTS

Номер: US20200006572A1
Автор: Chu-Kung Benjamin, Dewey Gilbert, Ghani Tahir, HARATIPOUR Nazila, Kavalieros Jack T., Le Van H., Metz Matthew V., SHARMA Abhishek A., SHIVARAMAN Shriram, SUNG Seung Hoon, Wang Yih
Принадлежит:

Thin film transistors are described. An integrated circuit structure includes a first source or drain contact above a substrate. A gate stack pedestal is on the first source or drain contact, the gate stack pedestal including a first gate dielectric layer, a gate electrode layer on the first gate dielectric layer, a second gate dielectric layer on the gate electrode layer, and gate dielectric sidewalls along the first gate dielectric layer, the gate electrode layer and the second gate dielectric layer. A channel material layer is over and along sidewalls of the gate stack pedestal, the channel material layer further on a portion of the first source or drain contact. Dielectric spacers are adjacent portions of the channel material layer along the sidewalls of the gate stack pedestal. A second source or drain contact is over a portion of the channel material layer over the gate stack pedestal. 1. An integrated circuit structure , comprising:a first source or drain contact above a substrate;a gate stack pedestal on the first source or drain contact, the gate stack pedestal comprising a first gate dielectric layer, a gate electrode layer on the first gate dielectric layer, a second gate dielectric layer on the gate electrode layer, and gate dielectric sidewalls along the first gate dielectric layer, the gate electrode layer and the second gate dielectric layer;a channel material layer over and along sidewalls of the gate stack pedestal, the channel material layer further on a portion of the first source or drain contact;dielectric spacers adjacent portions of the channel material layer along the sidewalls of the gate stack pedestal; anda second source or drain contact over a portion of the channel material layer over the gate stack pedestal.2. The integrated circuit structure of claim 1 , wherein the dielectric spacers comprise silicon nitride or silicon oxynitride.3. The integrated circuit structure of claim 1 , wherein channel material layer comprises a semiconducting ...

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Номер записи: 24
27-01-2022 дата публикации

METHOD FOR ASSEMBLING INTERIOR REARVIEW MIRROR ASSEMBLY

Номер: US20220024385A1
Автор: Krebs Peter, Steffes Matthew V.
Принадлежит:

A method for assembling a vehicular interior rearview mirror assembly includes providing a mirror mount, a mirror casing, a mirror reflective element at the mirror casing, and a toggle mechanism, which includes a body portion and a toggle lever joined to the body portion. A lower pivot mount of the toggle mechanism is inserted into a lower receiving portion of the mirror casing and an upper pivot mount of the toggle mechanism is inserted into an upper receiving portion of the mirror casing. An outer surface of the body portion corresponds with adjacent outer surfaces of the mirror casing. With a pivot element of the toggle mechanism attached at the mirror mount, and when the toggle lever pivots relative to the lower receiving portion of the mirror casing, the mirror casing pivots relative to the body portion to flip the mirror head between a first orientation and a second orientation. 1. A method for assembling a vehicular interior rearview mirror assembly , the method comprising:providing a mirror mount configured for mounting at an interior portion of a vehicle;providing a mirror casing, wherein the mirror casing comprises an upper receiving portion and a lower receiving portion;accommodating a mirror reflective element at the mirror casing;providing a toggle mechanism comprising (i) a body portion and (ii) a toggle lever joined to the body portion;inserting the toggle lever through an aperture established through a lower region of the mirror casing;moving the toggle mechanism to insert a lower pivot mount of the toggle mechanism into the lower receiving portion of the mirror casing;pivoting the toggle mechanism about the lower pivot mount to insert an upper pivot mount of the toggle mechanism into the upper receiving portion of the mirror casing; andwherein, when the upper and lower pivot mounts of the toggle mechanism are inserted into the respective upper and lower receiving portions of the mirror casing, an outer surface of the body portion corresponds with ...

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Номер записи: 25
09-01-2020 дата публикации

Flowforming Gun Barrels and Similar Tubular Devices

Номер: US20200009632A1
Автор: Fonte Matthew V.
Принадлежит:

Gun barrels and similar tubular devices for repeatedly guiding fired projectiles are fabricated from superalloys, titanium metals, tantalum metals, and similar metal materials by a flowforming process. Combinations of these metals are also flowformed to produce gun barrels and projectile-guiding tubes. In addition, inner liners for such barrels and tubes are made with these metals and flowforming processes. These barrels and tubular devices can withstand high temperatures and corrosive environments. The flowforming process is efficient and produces strong, yet thin and/or light weight, gun barrels and similar tubular devices. 156-. (canceled)57. A method of making a machine gun barrel , the method comprising:flowforming a metal preform below the recrystallization temperature of the metal preform to provide an inner liner comprising an inner surface, wherein the metal preform includes a first metal and a second metal integrally bonded together, wherein the first metal is selected from the group consisting of tantalum, a tantalum alloy, chromium, a chromium alloy, zirconium, a zirconium alloy, niobium, and a niobium alloy, and the second metal consists of a steel that is not an iron-based superalloy or a high strength steel, and wherein flowforming the metal preform includes imparting helical rifling to the inner surface; andassembling the inner liner together with an outer supporting structure to form a machine gun barrel.58. The method of making a machine gun barrel of claim 57 , further comprising performing at least one machining step on the first metal before flowforming the metal preform.59. The method of making a machine gun barrel of claim 57 , further comprising performing at least one machining step on the second metal before flowforming the metal preform.60. The method of making a machine gun barrel of claim 57 , further comprising performing at least one machining step on the inner liner before assembling the inner liner together with the outer supporting ...

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Номер записи: 26
12-01-2017 дата публикации

GERMANIUM-BASED QUANTUM WELL DEVICES

Номер: US20170012116A1
Автор: Chau Robert S., Chu-Kung Benjamin, Dewey Gilbert, Jin Been-Yih, Kavalieros Jack T., Kotlyar Roza, Metz Matthew V., Mukherjee Niloy, Pillarisetty Ravi, Rachmady Willy, Radosavljevic Marko
Принадлежит: Intel Corporation

A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric. 1. A microelectronic device , comprising: a lower barrier region;', 'a germanium channel region on the lower barrier region;', 'an upper barrier region on the germanium channel region;', 'a gate dielectric on the upper barrier region; and', 'a gate electrode on the gate dielectric;, 'a germanium quantum well channel region transistor, comprising a lower barrier region;', 'a group III-V material channel region on the lower barrier region;', 'an upper barrier region on the germanium channel region;', 'a gate dielectric on the upper barrier region; and', 'a gate electrode on the gate dielectric; and, 'a group III-V material quantum well channel region transistor, comprisingan isolation region disposed between the germanium quantum well region transistor and the group III-V material quantum well channel region transistor.2. The microelectronic device of claim 1 , wherein the germanium quantum well channel region transistor and the group III-V material quantum well channel region transistor abut the isolation region.3. The microelectronic device of claim 1 , wherein the germanium quantum well channel region transistor claim 1 , the group III-V material quantum well channel region transistor claim 1 , and the isolation region are formed on a common substrate4. The microelectronic device of claim 1 , wherein the lower barrier region of the germanium quantum well channel region transistor comprises a group III-V material.5. The microelectronic device of claim 1 , wherein the lower barrier region of the germanium quantum well channel region transistor comprises GaAs.6. The ...

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Номер записи: 27
12-01-2017 дата публикации

ASPECT RATIO TRAPPING (ART) FOR FABRICATING VERTICAL SEMICONDUCTOR DEVICES

Номер: US20170012125A1
Автор: Chau Robert S., Chu-Kung Benjamin, Dewey Gilbert, Kavalieros Jack T., Le Van H., Metz Matthew V., Mukherjee Niloy, Pillarisetty Ravi, Rachmady Willy, Radosavljevic Marko
Принадлежит:

Aspect ratio trapping (ART) approaches for fabricating vertical semiconductor devices and vertical semiconductor devices fabricated there from are described. For example, a semiconductor device includes a substrate with an uppermost surface having a first lattice constant. A first source/drain region is disposed on the uppermost surface of the substrate and has a second, different, lattice constant. A vertical channel region is disposed on the first source/drain region. A second source/drain region is disposed on the vertical channel region. A gate stack is disposed on and completely surrounds a portion of the vertical channel region. 1. A semiconductor device , comprising:a substrate with an uppermost surface having a first lattice constant;a first source/drain region disposed on the uppermost surface of the substrate and having a second, different, lattice constant;a vertical channel region disposed on the first source/drain region;a second source/drain region disposed on the vertical channel region; anda gate stack disposed on and completely surrounding a portion of the vertical channel region.2. The semiconductor device of claim 1 , further comprising:a plurality of lattice defects confined to the first source/drain region, wherein the vertical channel region is essentially defect-free.3. The semiconductor device of claim 1 , wherein the first and second source/drain regions comprise a semiconductor material different from a semiconductor material of the vertical channel region.4. The semiconductor device of claim 3 , wherein the semiconductor material of the first and second source/drain regions is lattice mismatched from the semiconductor material of the vertical channel region claim 3 , and wherein the first and second source/drain regions impart a strain to the vertical channel region.5. The semiconductor device of claim 1 , further comprising:a first contact disposed on the uppermost surface of the substrate and electrically coupled to the first source/ ...

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Номер записи: 28
11-01-2018 дата публикации

APPARATUS AND METHODS OF FORMING FIN STRUCTURES WITH ASYMMETRIC PROFILE

Номер: US20180013000A1
Автор: Dewey Gilbert, Ghani Tahir, Glass Glenn A., Kavalieros Jack T., Metz Matthew V., Mohapatra Chandra S., Murthy Anand S., Rachmady Willy, Rahhal-Orabi Nadia M.
Принадлежит: Intel Corporation

An embodiment includes a microelectronic device comprising: a substrate comprising a raised portion and a non-raised portion, wherein a dielectric material is disposed adjacent the raised portion, an epitaxial sub-fin structure disposed on the raised portion, wherein a bottom portion of the epitaxial sub-fin structure comprises an asymmetric profile, and an epitaxial fin device structure disposed on the sub-fin structure. Other embodiments are described herein. 125-. (canceled)26. A microelectronic device structure comprising:{'b': '111', 'a substrate comprising a raised portion and a non-raised portion, wherein a dielectric material is disposed adjacent the raised portion, and wherein a top surface of the raised portion comprises a single sided () facet of the raised portion material;'}a sub-fin structure disposed on the top surface of the raised portion, wherein a bottom portion of the sub-fin structure comprises an asymmetric profile;a fin device structure disposed on the sub-fin structure;a gate oxide disposed on a portion of the fin device structure; anda gate material disposed on the gate oxide.27. The structure of wherein the sub-fin structure comprises a first side and a second side claim 26 , wherein the first and second sides are of unequal length.28. The structure of wherein the fin device structure and the sub-fin structure comprise an epitaxial material selected from the group consisting of group III elements claim 26 , group IV elements claim 26 , and group V elements.29. The structure of wherein the microelectronic device comprises a device selected from the group consisting of a multi-gate transistor and a gate all around transistor.30111. The structure of wherein the bottom portion of the sub-fin structure comprises a () silicon plane of the raised portion of the substrate.31111. The structure of wherein the single sided () facet is disposed along a length of the fin device structure.32. The structure of wherein the raised portion of the substrate ...

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Номер записи: 29
09-01-2020 дата публикации

Gesture-based control device for controlling an electrical load

Номер: US20200013279A1
Автор: Brad Michael Krescholiek, Chris DIMBERG, Daniel L. Twaddell, Jason C. Killo, Matthew Philip McDonald, Matthew V. Harte
Принадлежит: Lutron Technology Co LLC

A control device may be configured to control one or more electrical loads in a load control system. The control device may be a wall-mounted device such as dimmer switch, a remote control device, or a retrofit remote control device. The control device may include a gesture-based user interface for applying advanced control over the one or more electrical loads. The types of control may include absolute and relative control, intensity and color control, preset, zone, or operational mode selection, etc. Feedback may be provided on the control device regarding a status of the one or more electrical loads or the control device.

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Номер записи: 30
14-01-2021 дата публикации

Battery-powered control device including a rotating portion

Номер: US20210014954A1
Автор: Jaykrishna A. Shukla, Jeffrey S. Hayes, Matthew V. Harte, Robert C. Newman, Jr., Stephen M. Ludwig, Jr.
Принадлежит: Lutron Technology Co LLC

Provided herein are examples of a remote control device that provides a retrofit solution for an existing switched control system. The remote control device may comprise a control circuit, a rotatable portion, a magnetic ring coupled to the rotatable portion, and first and second Hall-effect sensor circuits configured to generate respective first and second sensor control signals in response to magnetic fields generated by the magnetic elements. The control circuit may operate in a normal mode when the rotatable portion is being rotated, and in a reduced-power mode when the rotatable portion is not being rotated. The control circuit may disable the second Hall-effect sensor circuit in the reduced-power mode. The control circuit may detect movement of the rotatable portion in response to the first sensor control signal in the reduced-power mode and enable the second Hall-effect sensor circuit in response to detecting movement of the rotatable portion.

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Номер записи: 31
16-01-2020 дата публикации

Breath Analyte Detection Device

Номер: US20200015707A1
Автор: Ratto Matthew V., Ratto Timothy V.
Принадлежит:

A breath analyte device includes a breath volume in fluid communication with a sampling volume. The device also includes a sampling sensor configured to generate a breath signal that varies in response to changes in gas pressure (e.g., sound waves) in the breath volume and an analyte sensor configured to generate an analyte signal that varies in response to a concentration of a target analyte present in the sampling volume. A control unit is configured to determine a time at which to measure the concentration of the target analyte in the sampling volume based on the breath signal and measure the concentration of the target analyte in the sampling volume based on the analyte signal at the determined time. The device may also include a pump configured to motivate gas from the breath volume into the sampling volume prior to measuring the concentration of the target analyte. 1. A method for measuring concentration of a breath analyte , the method comprising:receiving gas exhaled by a user in a breath volume;receiving, from a sampling sensor, a breath signal that varies in response to changes in gas pressure in the breath volume identifying a sample time based on the breath signal;receiving, from an analyte sensor, an analyte signal that varies in response to a concentration of the breath analyte present in a sampling volume; andmeasuring the concentration of the breath analyte in the sampling volume based on the analyte signal.2. The method of claim 1 , wherein identifying the sample time comprises:detecting the breath signal increasing above a breath-detection threshold;identifying a maximum in the breath signal after the breath signal increased above the breath-detection threshold; anddetecting the breath signal dropping below an end-of-breath threshold after the maximum in the breath signal, wherein the sample time is when the breath signal drops below the end-of-breath threshold.3. The method of claim 1 , further comprising pumping a portion of the gas exhaled by ...

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Номер записи: 32
21-01-2021 дата публикации

ERGONOMIC CONTAINER WITH THUMB HOLE

Номер: US20210016930A1
Автор: Bergman Mark W., Given Jeffrey T., Leyden Matthew V., Waffensmith Jeffrey B.
Принадлежит:

An apparatus includes a bottom wall, a plurality of connected walls attached to the bottom wall to define a cavity having a top rim, and a flange extending laterally outward from the top rim. At least a portion of the flange extends downwardly from the top rim. The portion of the flange includes an aperture configured to accept a user's thumb, and the portion of the flange is substantially symmetrical about a center line of the apparatus. 114.-. (canceled)15. A method of holding a product comprising: a bottom wall;', 'a plurality of connected walls attached to the bottom wall to define the cavity having a top rim; and', the flange is substantially symmetrical about a center line of the container; and', 'the flange comprises an aperture disposed on the center line; and, 'a flange extending laterally outward and downward from the top rim, wherein], 'placing the product in a cavity of a container, the container comprisinginserting a user's thumb through the aperture from a bottom of the flange.16. The method of wherein the flange comprises a depression in a top of the flange claim 15 , the method comprising positioning at least a portion of the user's thumb in the depression.17. The method of comprising positioning the user's fingers against at least one of the plurality of connected walls.18. The method of comprising positioning a portion of the user's fingers against the bottom of the flange.19. The method of comprising positioning a portion of the user's fingers against the bottom of the flange.20. The method of comprising positioning the user's palm against at least one of the plurality of connected walls.21. The method of wherein the container comprises a notch in the top rim claim 15 , the method comprising positioning a portion of the user's thumb in the notch.22. The method of comprising positioning the user's fingers against the bottom wall.23. The method of wherein the product is a liquid claim 15 , the method comprising depositing a portion of the liquid on ...

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Номер записи: 33
17-04-2014 дата публикации

GATE ELECTRODE HAVING A CAPPING LAYER

Номер: US20140103458A1
Автор: Brask Justin K., Datta Suman, Dewey Gilbert, DOCZY Mark L., Metz Matthew V.
Принадлежит:

A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed. 1. A semiconductor transistor , comprising:a substrate;a transition oxide layer disposed on the substrate;a high-k dielectric material layer disposed on the transition oxide layer, the high-k dielectric material layer having a thickness approximately in the range of 5-25 Angstroms;a barrier layer disposed on the high-k dielectric material layer;a capping layer disposed on the barrier layer and comprising a material different than the barrier layer; anda gate electrode disposed above the capping layer and comprising a material different than the capping layer, wherein the gate electrode comprises a workfunction controlling metal;wherein a thickness of the barrier layer is less than 25 Angstroms.2. The semiconductor transistor of claim 1 , wherein the substrate comprises silicon.3. The semiconductor transistor of claim 1 , wherein the high-k dielectric material comprises hafnium.4. The semiconductor transistor of claim 1 , wherein the barrier layer comprises Ti and N.5. The semiconductor transistor of claim 1 , wherein the gate electrode comprises Ti or Al.6. A semiconductor transistor claim 1 , comprising:a semiconductor body formed on a substrate, the semiconductor body having a top surface and a pair of laterally opposite sidewalls;a transition oxide layer disposed on the a top surface and the sidewalls of the semiconductor body;a high-k dielectric material layer disposed on the ultra thin transition oxide layer, the high-k dielectric material layer having a thickness approximately in the range of 5-25 Angstroms;a barrier layer disposed on the high-k dielectric material layer;a capping layer disposed on the barrier layer and comprising a material different than the barrier layer; anda gate electrode disposed above ...

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Номер записи: 34
17-04-2014 дата публикации

Two-wire dimmer switch for low-power loads

Номер: US20140103827A1
Автор: Chris J. Salvestrini, Matthew V. Harte, Robert C. Newman, Jr.
Принадлежит: Lutron Electronics Co Inc

A two-wire load control device (such as, a dimmer switch) for controlling the amount of power delivered from an AC power source to an electrical load (such as, a high-efficiency lighting load) includes a thyristor coupled between the source and the load, a gate coupling circuit coupled between a first main load terminal and the gate of the thyristor, and a control circuit coupled to a control input of the gate coupling circuit. The control circuit generates a drive voltage for causing the gate coupling circuit to conduct a gate current to thus render the thyristor conductive at a firing time during a half cycle of the AC power source, and to allow the gate coupling circuit to conduct the gate current at any time from the firing time through approximately the remainder of the half cycle, where the gate coupling circuit conducts approximately no net average current to render and maintain the thyristor conductive.

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Номер записи: 35
17-01-2019 дата публикации

GESTURE-BASED CONTROL DEVICE FOR CONTROLLING AN ELECTRICAL LOAD

Номер: US20190019403A1
Автор: Dimberg Chris, Harte Matthew V., Killo Jason C., Kreschollek Brad Michael, McDonald Matthew Philip, Twaddell Daniel L.
Принадлежит: LUTRON ELECTRONICS CO., INC.

A control device may be configured to control one or more electrical loads in a load control system. The control device may be a wall-mounted device such as dimmer switch, a remote control device, or a retrofit remote control device. The control device may include a gesture-based user interface for applying advanced control over the one or more electrical loads. The types of control may include absolute and relative control, intensity and color control, preset, zone, or operational mode selection, etc. Feedback may be provided on the control device regarding a status of the one or more electrical loads or the control device. 1. A control device configured for use in a lighting control system to control respective amount of power delivered to a plurality of lighting loads , the lighting loads being external to the control device , the control device comprising:a base portion configured to be mounted over a toggle actuator of a mechanical switch that controls power delivered to at least one of the lighting loads; anda control unit comprising a touch sensitive surface configured to detect a first user input and a second user input, a control circuit responsive to the touch sensitive surface, and a communication circuit configured to transmit control signals;wherein the control circuit is configured to generate first control data to adjust the respective amount of power delivered to each of the plurality of lighting loads to an absolute power level based on the first user input, the absolute power level corresponding to a percentage of respective maximum power levels of the plurality of lighting loads, the control circuit configured to generate second control data to adjust the respective amount of power delivered to the plurality of lighting loads by a relative amount based on the second user input, the relative amount corresponding to an amount of adjustment relative to respective present power levels of the plurality of lighting loads, the control circuit further ...

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Номер записи: 36
24-01-2019 дата публикации

METHOD OF MAKING A CORROSION RESISTANT TUBE

Номер: US20190022801A1
Автор: Fonte Matthew V.
Принадлежит:

One method for producing a bimetallic tubular component comprises hot isostatic pressing an assembly comprising two concentrically-positioned tubes including an inner tube comprising a corrosion-resistant nickel alloy, and an outer tube comprising a steel alloy, thereby forming a bimetallic tubular preform. The bimetallic tubular preform is flowformed, thereby forming a bimetallic tubular component comprising an inner corrosion-resistant nickel alloy layer and an outer steel alloy layer. 2. The method of claim 1 , wherein the inner tube comprising the corrosion-resistant nickel alloy and the outer tube comprising the steel alloy have different hardness values claim 1 , and wherein the hardness value of the inner tube before the flowforming is greater than two times the hardness value of the outer tube before the flowforming.3. The method of claim 1 , wherein the steel alloy comprises a low-carbon steel claim 1 , a high-carbon steel claim 1 , or a stainless steel; and wherein the nickel alloy comprises Alloy 625 or Alloy C-276.4. The method of claim 1 , wherein the steel alloy comprises a duplex stainless steel; and wherein the nickel alloy comprises Alloy 625 or Alloy C-276.5. The method of claim 1 , wherein the steel alloy comprises a low carbon steel; and wherein the nickel alloy comprises Alloy 625 or Alloy C-276.6. The method of claim 1 , wherein the steel alloy comprises an AISI 1018 type steel claim 1 , an AISI 1020 type steel claim 1 , or an AISI 4130 type steel; and wherein the nickel alloy comprises Alloy 625 or Alloy C-276.7. The method of claim 1 , wherein the steel alloy comprises an AISI 1018 type steel or an AISI 1020 type steel; and wherein the nickel alloy comprises Alloy 625.8. A method for producing a bimetallic tubular component claim 1 , the method comprising: the inner layer comprises a corrosion-resistant alloy, and', 'the outer layer comprises a duplex stainless steel or an aluminum alloy; and, 'forming a bimetallic tubular preform comprising ...

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Номер записи: 37
10-02-2022 дата публикации

INTEGRATED CIRCUIT STRUCTURES INCLUDING A METAL LAYER FORMED USING A BEAM OF LOW ENERGY ATOMS

Номер: US20220042162A1
Автор: Jezewski Christopher J., Karpov Elijah V., Metz Matthew V.
Принадлежит:

Systems and approaches for fabricating an integrated circuit structure including a metal layer formed using a beam of low energy atoms are described. In an example, a system for fabricating an integrated circuit structure includes a sample holder for supporting a 300 mm wafer facing down, the substrate having a feature thereon. The system also includes a source for providing a beam of low energy metal atoms to form a metal layer on the feature of the substrate. The system also includes a source of gas atoms for controlling the texture of the layer 1. A system for fabricating an integrated circuit structure , the system comprising:a sample holder for supporting a substrate wafer facing down, the substrate having a feature thereon;a source for providing a beam of low energy metal atoms to form a metal layer on the feature of the substrate;a source of gas atoms with energy 50-800 eV, the source of gas atoms for removing weakly held metal atoms from the feature.2. The system of claim 1 , wherein the source for providing the beam of low energy metal atoms and the source of gas atoms are operated simultaneously.3. The system of claim 1 , wherein the source for providing the beam of low energy metal atoms and the source of gas atoms are operated alternately.4. The system of claim 1 , wherein the beam of low energy metal atoms has an energy of approximately 0.1 eV claim 1 , wherein the beam of low energy metal atoms has a linear shape claim 1 , and wherein a metal source of the metal layer is continuously supplied to the source for providing the beam of low energy metal atoms.5. The system of claim 1 , wherein the feature is a source/drain contact trench exposing a semiconductor source/drain structure claim 1 , and wherein the metal layer is a conductive contact layer for the semiconductor source/drain structure.6. The system of claim 1 , wherein the feature is a conductive line of a back end-of-line (BEOL) metallization layer claim 1 , and wherein the metal layer is ...

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Номер записи: 38
04-02-2016 дата публикации

Flowforming corrosion resistant alloy tubes

Номер: US20160033059A1
Автор: Matthew V. Fonte
Принадлежит: ATI Properties LLC

Flowforming processes for the production of corrosion resistant alloy tubes are disclosed.

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Номер записи: 39
04-02-2016 дата публикации

CONTACT TECHNIQUES AND CONFIGURATIONS FOR REDUCING PARASITIC RESISTANCE IN NANOWIRE TRANSISTORS

Номер: US20160035860A1
Автор: Chu-Kung Benjamin, Dewey Gilbert, Le Van H., Metz Matthew V., Mukherjee Niloy, Pillarisetty Ravi, Rachmady Willy, Radosavljevic Marko, Then Han Wui
Принадлежит:

Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nano-wire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor. 1. A method , comprising:providing a semiconductor substrate;depositing an isolation layer on the semiconductor substrate;depositing a channel layer on the isolation layer, the channel layer to provide a channel tier a transistor; andforming a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, material of the channel layer and to provide a source terminal or drain terminal for the transistor.2. The method of claim 1 , wherein the at least one planar dimension is substantially perpendicular to a planar surface of the semiconductor substrate upon which the transistor is formed.3. The method of claim 1 , further comprising:depositing a buffer layer on the semiconductor substrate, wherein the buffer layer is disposed between the semiconductor substrate and the isolation layer.4. The method of claim 1 , wherein depositing the channel layer comprises epitaxially depositing the channel layer on the isolation layer.5. The method of claim 4 , wherein forming the contact comprises:selectively removing material of the isolation layer using an etch process; anddepositing a metal to replace the selectively removed material of the isolation layer to form the contact.6. The method of claim 5 , wherein forming the contact further comprises:epitaxially depositing an epitaxial film on the channel layer prior to ...

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Номер записи: 40
31-01-2019 дата публикации

APPARATUS AND METHODS TO CREATE AN ACTIVE CHANNEL HAVING INDIUM RICH SIDE AND BOTTOM SURFACES

Номер: US20190035889A1
Автор: Dewey Gilbert, Ghani Tahir, Glass Glenn A., Kavalieros Jack T., Metz Matthew V., Mohapatra Chandra S., Murthy Anand S., Rachmady Willy
Принадлежит: Intel Corporation

Transistor devices having an indium-containing ternary or greater III-V compound active channels, and processes for the fabrication of the same, may be formed that enables improved carrier mobility when fabricating fin shaped active channels, such as those used in tri-gate or gate all around (GAA) devices. In one embodiment, an indium-containing ternary or greater III-V compound may be deposited in narrow trenches on a reconstructed upper surface of a sub-structure, which may result in a fin that has indium rich side surfaces and an indium rich bottom surface. These indium rich surfaces will abut a gate oxide of a transistor and may result in high electron mobility and an improved switching speed relative to conventional homogeneous compositions of indium-containing ternary or greater III-V compound active channels. 1. A microelectronic structure having an indium-containing ternary or greater III-V compound active channel , wherein the indium-containing ternary or greater III-V compound active channel includes at least one side surface and a bottom surface , wherein the at least one side surface and the bottom surface have an indium content higher than the average indium content of the indium-containing ternary or greater III-V compound active channel.2. The microelectronic structure of claim 1 , wherein the indium-containing ternary or greater III-V compound active channel comprises one of indium gallium arsenide claim 1 , indium gallium antimonide claim 1 , indium gallium arsenide antimonide claim 1 , indium gallium phosphide claim 1 , indium gallium arsenide phosphide claim 1 , indium gallium antimonide phosphide claim 1 , and indium gallium arsenide antimonide phosphide.3. The microelectronic structure of claim 1 , wherein the indium-containing ternary or greater III-V compound active channel comprises a fin.4. The microelectronic structure of claim 1 , further including a substrate over which the indium-containing ternary or greater III-V compound active ...

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Номер записи: 41
31-01-2019 дата публикации

DOPANT DIFFUSION BARRIER FOR SOURCE/DRAIN TO CURB DOPANT ATOM DIFFUSION

Номер: US20190035897A1
Автор: Dewey Gilbert, Ghani Tahir, Glass Glenn A., Kavalieros Jack T., Kennel Harold W., Ma Sean T., Metz Matthew V., Mohapatra Chandra S., Murthy Anand S., RACHMADY Will
Принадлежит:

An apparatus including a transistor device on a substrate including an intrinsic layer including a channel; a source and a drain on opposite sides of the channel; and a diffusion barrier between the intrinsic layer and each of the source and the drain, the diffusion barrier including a conduction band energy that is less than a conduction band energy of the channel and greater than a material of the source and drain. A method including defining an area of an intrinsic layer on a substrate for a channel of a transistor device; forming a diffusion barrier layer in an area defined for a source and a drain; and forming a source on the diffusion barrier layer in the area defined for the source and forming a drain in the area defined for the drain. 1. An apparatus comprising:a substrate; an intrinsic layer comprising a channel;', 'a source material on a first side of the channel and a drain material on a second side of the channel; and', 'a diffusion barrier between the intrinsic layer and each of the source material and the drain material, the diffusion barrier comprising a conduction band energy that is less than a conduction band energy of the channel and higher than a conduction band energy of the source material or the drain material., 'a transistor device on the substrate comprising2. The apparatus of claim 1 , wherein the intrinsic layer comprises a group III-V compound semiconductor material.3. The apparatus of claim 2 , wherein the diffusion barrier comprises a dilute nitride alloy of the group III-V compound semiconductor of the intrinsic layer.4. The apparatus of claim 1 , wherein the intrinsic layer comprises indium gallium arsenide (InGaAs) and the diffusion barrier comprises InGaAsN claim 1 , wherein y is less than 0.03.5. The apparatus of claim 2 , wherein the source material and the drain material comprise a group III-V compound semiconductor material.6. The apparatus of claim 4 , wherein the diffusion barrier comprises a group III-V compound semiconductor ...

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Номер записи: 42
31-01-2019 дата публикации

HIGH MOBILITY ASYMMETRIC FIELD EFFECT TRANSISTORS WITH A BAND-OFFSET SEMICONDUCTOR DRAIN SPACER

Номер: US20190035921A1
Автор: Chu-Kung Benjamin, Dewey Gilbert, HUANG CHENG-YING, Kavalieros Jack T., Metz Matthew V., Rachmady Willy, Rios Rafael
Принадлежит:

An embodiment includes a field effect transistor, comprising: a source region comprising a first III-V material doped to a first conductivity type; a drain region comprising a second III-V material doped to a second conductivity type that is opposite the first conductivity type; a gate electrode disposed over a channel region comprising a third III-V material; and a first spacer, between the channel and drain regions, comprising a fourth III-V material having a charge carrier-blocking band offset from the third III-V material. Other embodiments are described herein. 1. A field effect transistor , comprising:a source region comprising a first III-V material doped to a first conductivity type;a drain region comprising a second III-V material doped to a second conductivity type that is opposite the first conductivity type;a gate electrode disposed over a channel region comprising a third III-V material; anda first spacer, between the channel and drain regions, comprising a fourth III-V material having a conduction band that is offset from a conduction band of the third III-V material.2. The transistor of claim 1 , wherein along a first horizontal axis no spacer is between the channel region and the source region.3. The transistor of claim 1 , wherein the first spacer directly contacts the channel region along an interface; and the interface is directly below the gate electrode.4. The transistor of claim 1 , wherein:the drain region is laterally spaced apart from a sidewall of the gate electrode by a second spacer;the first spacer directly contacts the channel region along an interface; andthe interface is directly below the second spacer.6. The transistor of claim 1 , wherein each of the first claim 1 , second claim 1 , and third III-V materials includes Ga and As and the fourth III-V material includes P.7. The transistor of claim 1 , wherein the fourth III-V material is doped to the second conductivity type.8. The transistor of claim 1 , wherein a first horizontal ...

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Номер записи: 43
06-02-2020 дата публикации

FLUID DELIVERY DEVICE AND BONE SCREW

Номер: US20200038646A1
Автор: Leyden Matthew V., Sweeney Patrick J.
Принадлежит: Spinal Generations, LLC

A delivery device for delivering substance to bone includes a luer portion configured to be detachably coupled to a bit driver, the luer portion having a luer thread. A bit portion is rigidly coupled the luer portion, and the bit portion is configured to accommodate the bit driver. A fluted portion is rigidly coupled to the bit portion, the fluted portion comprising a flute, the flute configured to create a hole in the bone. A conduit extends through the luer portion and the bit portion, at least partially through the fluted portion. The flute defines an aperture extending from the conduit entirely through the flute, and the aperture is configured to allow a substance to pass therethrough. 1. A device for delivering substance to bone , comprising:a luer portion configured to be detachably coupled to a bit driver, the luer portion comprising a luer thread;a bit portion rigidly coupled to the luer portion, the bit portion configured to accommodate the bit driver;a fluted portion rigidly coupled to the bit portion, the fluted portion comprising a flute, the flute configured to create a hole in the bone; and 'wherein the flute defines an aperture, the aperture extending from the conduit entirely through the flute, and the aperture is configured to allow a substance to pass therethrough.', 'a conduit, the conduit extending entirely through the luer portion and the bit portion, and the conduit extending at least partially through the fluted portion;'}2. The device of claim 1 , wherein the bit portion further comprises at least one hex bit configured to be detachably coupled to a hex bit driver.3. The device of claim 1 , wherein the luer portion defines a cutout claim 1 , the cutout configured to detachably couple to a screwdriver.4. The device of claim 1 , further comprising a threaded portion rigidly coupled to the bit portion claim 1 , the threaded portion comprising a thread..5. The device of claim 4 , wherein the thread is configured to secure the device into a bone.6 ...

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Номер записи: 44
15-02-2018 дата публикации

EXTERIOR REARVIEW MIRROR ASSEMBLY FOR VEHICLE

Номер: US20180043830A1
Автор: Peterson Kenneth C., Steffes Matthew V.
Принадлежит:

An exterior rearview mirror assembly for a vehicle includes a mirror head adjustably mounted at a mounting arm and adjustable between a retracted position and an extended position. The mirror reflective element is oriented to provide a driver of the vehicle a field of view rearward and sideward of the vehicle with the mounting arm attached at the side of the vehicle when the mirror head is in the retracted position and when the mirror head is in the extended position. The mirror head is connected to the mounting arm via pivotable first and second links that cooperatively pivot relative to the mounting arm and the mirror head to move the mirror head between the retracted and extended positions. An actuator is disposed at an end of the first link and operates to pivot the first link to move the mirror head between the retracted position and the extended position. 1. An exterior rearview mirror assembly for a vehicle , said exterior rearview mirror assembly comprising:a mirror head having a mirror casing and a mirror reflective element;a mounting arm configured for attachment at a side of a vehicle, wherein said mirror head is adjustably mounted at said mounting arm and adjustable between a retracted position and an extended position, and wherein said mirror head is closer to the side of the vehicle at which said mounting arm is attached when in said retracted position as compared to said extended position;wherein said mirror reflective element is oriented to provide a driver of the vehicle a field of view rearward and sideward of the vehicle with said mounting arm attached at the side of the vehicle both (a) when said mirror head is in said retracted position and (b) when said mirror head is in said extended position;wherein said mirror head is connected to said mounting arm via pivotable first and second links that cooperatively pivot relative to said mounting arm and said mirror head to move said mirror head between said retracted and extended positions;an actuator ...

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Номер записи: 45
06-02-2020 дата публикации

SUBFIN LEAKAGE SUPPRESSION USING FIXED CHARGE

Номер: US20200044059A1
Автор: Dewey Gilbert W., Ghani Tahir, HUANG CHENG-YING, Kavalieros Jack T., Kennel Harold W., LILAK AARON D., Ma Sean T., Metz Matthew V., Murthy Anand S., Rachmady Willy, Weber Justin R.
Принадлежит: Intel Corporation

Disclosed herein are tri-gate transistor arrangements, and related methods and devices. For example, in some embodiments, a transistor arrangement may include a fin stack shaped as a fin extending away from a base, and a subfin dielectric stack. The fin includes a subfin portion and a channel portion, the subfin portion being closer to the base than the channel portion. The subfin dielectric stack includes a transistor dielectric material, and a fixed charge liner material disposed between the transistor dielectric material and the subfin portion of the fin. 1. A tri-gate transistor arrangement , comprising:a fin stack of one or more semiconductor materials shaped as a fin extending away from a base, the fin comprising a subfin portion and a channel portion, the subfin portion being closer to the base than the channel portion; and a transistor dielectric material, and', 'a fixed charge liner material disposed between the transistor dielectric material and the subfin portion of the fin., 'a subfin dielectric stack, including2. The tri-gate transistor arrangement according to claim 1 , wherein the fixed charge liner material comprises a material having a higher concentration of fixed charges than a concentration of fixed charges in the transistor dielectric material.3. The tri-gate transistor arrangement according to claim 1 , wherein the fixed charge liner material has a thickness between 2 nanometers and 20 nanometers.4. The tri-gate transistor arrangement according to claim 1 , wherein the fixed charge liner material is in contact with the subfin portion and/or with the transistor dielectric material.5. The tri-gate transistor arrangement according to claim 1 , wherein the fixed charge liner material comprises a dielectric material having a concentration of fixed charges greater than 5fixed charges per square centimeter.6. The tri-gate transistor arrangement according to claim 5 , wherein the fixed charges are positive fixed charges when the tri-gate transistor ...

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Номер записи: 46
15-02-2018 дата публикации

METHOD FOR FABRICATING TRANSISTOR WITH THINNED CHANNEL

Номер: US20180047846A1
Автор: Brask Justin K., Chau Robert S., Datta Suman, DOCZY Mark L., Doyle Brian S., Kavalieros Jack T., Majumdar Amlan, Metz Matthew V., Radosavljevic Marko
Принадлежит:

A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process. 1. (canceled)2. An apparatus comprising:a substrate comprising Si;a fin comprising Si formed on the substrate;a gate electrode formed of a work function metal comprising: W, Ta, Ti, and N;a first spacer;a second spacer, wherein the first and second spacers comprise N;a gate dielectric between: the gate electrode and the fin, the gate electrode and the first spacer, and the gate electrode and the second spacer, wherein the gate dielectric comprises Hf and O,a source; anda drain; a portion of the fin under the gate electrode has a first width,', 'a portion of the fin outside the gate electrode and closer to the drain or source regions has a second width, and', 'the second width is greater than the first width., 'wherein3. The apparatus of claim 2 , wherein the source and drain comprise As or Ph.4. The apparatus of claim 2 , wherein the gate electrode has a work function in a range of 3.9 eV to 4.6 eV claim 2 , and wherein the gate electrode is of an n-type device.5. The apparatus of claim 2 , wherein the gate electrode has a work function in a range of 4.6 eV to 5.2 eV claim 2 , and wherein the gate electrode is of a p-type device.6. The apparatus of claim 2 , wherein the substrate is a delta-doped substrate.7. The apparatus of claim 2 , wherein the gate dielectric is a dual layer gate dielectric having a first structure and a second structure claim 2 , wherein the first structure comprises Si and O claim 2 , and wherein the second structure comprises Hf and O.8. A method comprising:forming a substrate comprising Si;forming a fin comprising Si formed on the substrate;forming a gate electrode formed of a work function metal comprising: W, Ta, Ti, and N;forming a first spacer;forming a second spacer, wherein the first and second spacers comprise ...

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Номер записи: 47
25-02-2021 дата публикации

Multi-Sensor Breath Analyte Detection Device

Номер: US20210052192A1
Автор: Ratto Matthew V., Ratto Timothy V.
Принадлежит:

A breath analyte device includes a breath volume in fluid communication with a sampling volume. The device also includes a sampling sensor configured to generate a breath signal that varies in response to changes in gas pressure (e.g., sound waves) in the breath volume and one or more analyte sensors configured to generate one or more analyte signals that vary in response to a concentration of one or more target analytes present in the sampling volume. A control unit is configured to determine a time at which to measure the concentration of target analytes in the sampling volume based on the breath signal and measure the concentration of the target analytes based on the analyte signals at the determined time. The device may also include a pump configured to motivate gas from the breath volume into the sampling volume prior to measuring the concentration of the target analytes. 1. A pocketable , hand-held breath analyte device comprising:a housing having a length between five and twenty centimeters, a width between two and ten centimeters, and a depth between one and three centimeters;a breath volume within the housing;an input aperture fluidly connecting the breath volume to an exterior environment and configured for a user to blow into such that a portion of the user's breath enters the breath volume;a sampling volume within the housing and in fluid communication with the breath volume;a sampling sensor located within the housing in or adjacent to the breath volume and configured to generate a breath signal that varies in response to changes in gas pressure in the breath volume;a first analyte sensor within the housing and in fluid communication with the sample volume, the first analyte sensor configured to generate a first analyte signal that varies in response to a concentration of a first analyte present in the sampling volume;a second analyte sensor within the housing and in fluid communication with the sample volume, the second analyte sensor configured to ...

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Номер записи: 48
23-02-2017 дата публикации

REARVIEW MIRROR ASSEMBLY FOR VEHICLE

Номер: US20170050568A1
Автор: De Wind Darryl P., Deuel Eric S., Mohan Jake A., Peterson Kenneth C., Sobecki Justin E., Steffes Matthew V.
Принадлежит:

An exterior rearview mirror assembly for a vehicle includes a mirror head and a light module disposed at a mirror casing. A blind zone indicator light emitting diode and a turn signal indicator light emitting diode are disposed at a single circuit board and are operable to emit light for a blind zone indicator and a turn signal indicator, respectively. The blind zone indicator and the turn signal indicator are disposed along a forward and sideward portion of the mirror casing, where the turn signal indicator is viewable and the blind zone indicator is not viewable along the forward and sideward portion of the mirror casing. When the blind zone indicator light emitting diode is operated and when the exterior rearview mirror assembly is attached at the side of the vehicle, the blind zone alert is viewable by the driver of the vehicle outboard of the mirror reflective element. 1. An exterior rearview mirror assembly for a vehicle , said exterior rearview mirror assembly comprising:a mirror head and a mounting base configured for attachment at a side of a vehicle equipped with said exterior rearview mirror assembly, wherein said mirror head comprises a mirror casing and a reflective element;a light module disposed at said mirror casing, wherein said light module, when said mounting base of said exterior rearview mirror assembly is attached at the side of the equipped vehicle, is operable to (i) provide a blind zone alert viewable by a driver of the equipped vehicle and (ii) provide a turn signal indication viewable by drivers of other vehicles at a side lane adjacent the equipped vehicle;wherein said light module comprises a single circuit board;wherein a blind zone indicator light emitting diode is disposed at said single circuit board and is operable to emit light for a blind zone indicator, and wherein the blind zone indicator, when said blind zone indicator light emitting diode is operated, provides the blind zone alert;wherein a turn signal indicator light emitting ...

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Номер записи: 49
25-02-2021 дата публикации

III-V SOURCE/DRAIN IN TOP NMOS TRANSISTORS FOR LOW TEMPERATURE STACKED TRANSISTOR CONTACTS

Номер: US20210057413A1
Автор: Dewey Gilbert, HUANG CHENG-YING, Jun Kimin, Kavalieros Jack T., LILAK AARON D., Mehandru Rishabh, Metz Matthew V., MORROW Patrick, PHAN ANH, Pillarisetty Ravi, Rachmady Willy, Yoo Hui Jae
Принадлежит:

An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS transistors having a group III-V material source/drain region. 1. An integrated circuit structure , comprising:a lower device layer that includes a first structure comprising a plurality of PMOS transistors; andan upper device layer formed on the lower device layer, the upper device layer including a second structure comprising a plurality of NMOS transistors having a group III-V material source/drain region.2. The integrated circuit structure of claim 1 , wherein the plurality of NMOS transistors are non-planar.3. The integrated circuit structure of claim 1 , wherein the group III-V material source/drain region comprises a narrow band gap alloy of indium gallium arsenide (InGaAs).4. The integrated circuit structure of claim 1 , wherein the group III-V material source/drain region comprises one of: indium arsenide (InAs) claim 1 , indium antimony (InSb) claim 1 , indium arsenide antimony (InAsSb) claim 1 , gallium arsenide (GaAs) claim 1 , gallium arsenide antimony (GaAsSb) claim 1 , indium phosphorus (InP) claim 1 , germanium (Ge) claim 1 , and silicon germanium (SiGe).5. The integrated circuit structure of claim 1 , wherein use of the group III-V material reduces a highest temperature budget for processing a stack comprising the plurality of NMOS transistors formed on the plurality of PMOS transistors.6. The integrated circuit structure of claim 1 , wherein ones of the plurality of NMOS transistors comprise:a gate electrode formed on a gate dielectric layer formed on a fin;a pair of sidewall spacers formed along opposite sides of the gate electrode; andthe group III-V source/drain region formed on opposite sides of and extending beneath the gate electrode, and wherein the group III ...

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Номер записи: 50
21-02-2019 дата публикации

MODULAR FEMORAL NAIL AND METHOD OF USE THEREOF

Номер: US20190053836A1
Автор: Leyden Matthew V., Sweeney Patrick J.
Принадлежит: Spinal Generations, LLC

An intramedullary nail for implantation within a fractured bone. The intramedullary nail includes two or more nail modules. Each nail module has an elongated body with a first end and a second end. For each nail module, at least one of the first end or the second end is a connecting end configured to connect to a second connecting end on a second nail module. 1. An intramedullary nail for implantation within a fractured bone , the nail comprising:two or more nail modules, each nail having an elongated body with a first end and a second end;wherein, for each nail module, at least one of the first end or the second end is a connecting end configured to connect to a second connecting end on a second nail module; andan engagement mechanism configured to prevent at least one of rotation of a first nail module relative to a second, adjacent nail module and separation of the first nail module from the second, adjacent nail module.2. The intramedullary nail of claim 1 , wherein each connecting end is one of a male connecting end or a female connecting end and is configured to connect to the other of the male connecting end or the female connecting end on a second nail module.3. The intramedullary nail of claim 1 , wherein each connecting end comprises at least one notch claim 1 , and wherein the intramedullary nail further comprises a key comprising a ring with a top side and a bottom side and at least one ridge formed on each side claim 1 , the key configured to interlock between the connecting ends of two nail modules with the ridges of the key fitting in the notches of the connecting ends.4. The intramedullary nail of claim 3 , wherein the at least one top ridge is offset from the at least one bottom ridge.5. The intramedullary nail of claim 1 , wherein each connecting end includes a scalloped edge such that scallops on one scalloped edge are configured to interlock with scallops on another scalloped edge.6. The intramedullary nail of claim 1 , wherein at least one of ...

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Номер записи: 51
21-02-2019 дата публикации

LOW BAND GAP SEMICONDUCTOR DEVICES HAVING REDUCED GATE INDUCED DRAIN LEAKAGE (GIDL) AND THEIR METHODS OF FABRICATION

Номер: US20190058053A1
Автор: Chu-Kung Benjamin, Dewey Gilbert, Kavalieros Jack T., Kim Seiyon, Le Van H., Metz Matthew V., Rachmady Willy
Принадлежит:

Embodiments of the present invention are directed to low band gap channel semiconductor devices. In an example, a device includes a first semiconductor material formed above a substrate, the first semiconductor material having a first band gap. A gate dielectric layer is on a surface of the first semiconductor material. A gate electrode is on the gate dielectric layer. A pair of source/drain regions is on opposite sides of the gate electrode. A channel is disposed in the first semiconductor material between the pair of source/drain regions and beneath the gate electrode. The pair of source/drain regions includes a second semiconductor material having a second band gap, and a third semiconductor material having a third band gap. The second semiconductor material is between the first semiconductor material and the third semiconductor material, and the second band gap is greater than the first bandgap. 1. A device comprising:a first semiconductor material formed above a substrate, the first semiconductor material having a first band gap;a gate dielectric layer on a surface of the first semiconductor material;a gate electrode on the gate dielectric layer;a pair of source/drain regions on opposite sides of the gate electrode;a channel disposed in the first semiconductor material between the pair of source/drain regions and beneath the gate electrode; andwherein the pair of source/drain regions comprises a second semiconductor material having a second band gap, and a third semiconductor material having a third band gap, wherein the second semiconductor material is between the first semiconductor material and the third semiconductor material and wherein the second band gap is greater than the first bandgap.2. The device of wherein the second bandgap is at least 150 meV greater than the first band gap.3. The device of wherein the second bandgap is between 150 meV-500 meV greater than the first band gap.4. The device of wherein the second bandgap is greater than the third ...

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Номер записи: 52
10-03-2022 дата публикации

MICROPHONE ARRAY WITH AUTOMATED ADAPTIVE BEAM TRACKING

Номер: US20220078547A1
Автор: Juszkiewicz Richard S., Kotvis Matthew V., McCowan Iain Alexander, Metzar Nicholas William
Принадлежит:

An example method of operation may include initializing a microphone array in a defined space to receive one or more sound instances based on a preliminary beamform tracking configuration, detecting the one or more sound instances within the defined space via the microphone array, modifying the preliminary beamform tracking configuration, based on a location of the one or more sound instances, to create a modified beamform tracking configuration, and saving the modified beamform tracking configuration in a memory of a microphone array controller. 1. A method , comprising:scanning each of a plurality of sub-regions of a defined space for one or more sound instances;based on the scanning, combining a local acoustic energy map for each of the plurality of sub-regions into an acoustic energy map representative of the defined space;identifying local acoustic energy map locations for each sub-region based on the acoustic energy map representative of the defined space; andcreating a modified beamform tracking configuration based on the locations.2. The method of claim 1 , further comprising:designating each of the plurality of sub-regions as a desired sound sub-region or an unwanted noise sub-region based on the sound instances received by the plurality of microphone arrays during the scanning of the plurality of sub-regions.3. The method of claim 1 , wherein the one or more sound instances comprise a human voice.4. The method of claim 1 , further comprising:saving the modified beamform tracking configuration in a memory of a microphone array controller.5. The method of claim 1 , further comprising:subsequently re-scanning each of the plurality of sub-regions for new desired sound instances;creating a new modified beamform tracking configuration based on new locations of the new desired sound instances; andsaving the new modified beamform tracking configuration in a memory of a microphone array controller.6. The method of claim 1 , wherein a preliminary beamform tracking ...

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Номер записи: 53
03-03-2016 дата публикации

Germanium-based quantum well devices

Номер: US20160064520A1
Автор: Been-Yin Jin, Benjamin Chu-Kung, Gilbert Dewey, Jack T. Kavalieros, Marko Radosavljevic, Matthew V. Metz, Niloy Mukherjee, Ravi Pillarisetty, Robert S. Chau, Roza Kotlyar, Willy Rachmady
Принадлежит: Intel Corp

A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

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Номер записи: 54
03-03-2016 дата публикации

CONTROLLABLE-LOAD CIRCUIT FOR USE WITH A LOAD CONTROL DEVICE

Номер: US20160066379A1
Автор: Bedell Ryan S., Harte Matthew V., Salvestrini Christopher James
Принадлежит:

A load control device for controlling the amount of power delivered from an AC power source to an electrical load is operable to conduct enough current through a thyristor of a connected dimmer switch to exceed rated latching and holding currents of the thyristor. The load control device comprises a controllable-load circuit operable to conduct a controllable-load current through the thyristor of the dimmer switch. The load control device disables the controllable-load circuit when the phase-control voltage received from the dimmer switch is a reverse phase-control waveform. When the phase-control voltage received from the dimmer switch is a forward phase-control waveform, the load control device is operable to decrease the magnitude of the controllable-load current so as to conduct only enough current as is required in order to exceed rated latching and holding currents of the thyristor. 1. A load control device for controlling the power delivered from an AC power source to an electrical load , the load control device adapted to be coupled to the AC power source through a dimmer switch , the load control device comprising:a load control circuit adapted to be coupled to the electrical load for controlling the power delivered to the electrical load;a control circuit coupled to the load control circuit for controlling the amount of power delivered to the electrical load in response to a conduction period of a phase-control voltage received from the dimmer switch;a controllable-load circuit configured to conduct a controllable-load current from the AC power source through the dimmer switch, the controllable-load circuit configured to maintain the magnitude of the controllable-load circuit constant for at least a portion of each half-cycle of the AC power source; anda communication circuit configured to transmit and receive digital messages;wherein the control circuit is configured to control the controllable-load circuit in response to receiving a digital message via ...

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Номер записи: 55
17-03-2022 дата публикации

METALLIZATION STACKS WITH SELF-ALIGNED STAGGERED METAL LINES

Номер: US20220084942A1
Автор: CHANDHOK Manish, Jezewski Christopher J., Kabir Nafees A., Karpov Elijah V., Metz Matthew V.
Принадлежит: Intel Corporation

Methods for fabricating metallization stacks with one or more self-aligned staggered metal lines, and related semiconductor devices, are disclosed. Methods and devices are based on providing a spacer material conformal to bottom metal lines of a first layer of a metallization stack. By carefully designing parameters of the deposition process, the spacer material may be deposited in such a manner that, for each pair of adjacent bottom metal lines of the first layer, an opening in the spacer material is formed in a layer above the bottom metal lines (i.e., in the second layer of the metallization stack), the opening being substantially equidistant to the adjacent bottom metal lines of the first layer. Top metal lines are formed by filling the openings with an electrically conductive material, resulting in the top metal lines being self-aligned and staggered with respect to the bottom metal lines. 1. An integrated circuit (IC) structure , comprising:a support structure;a first metallization layer, comprising a pair of first electrically conductive lines; anda second metallization layer, comprising a second electrically conductive line and an interconnect configured to provide electrical connectivity between the second electrically conductive line and one of the first electrically conductive lines, the first metallization layer is between the support structure and the second metallization layer,', 'the interconnect is coupled to the one of the first electrically conductive lines and to a sidewall of the second electrically conductive line,', 'projections of the pair of the first electrically conductive lines and of the second electrically conductive line onto the support structure are substantially parallel, and', 'the projection of the second electrically conductive line is between the projections of the pair of the first electrically conductive lines., 'wherein2. The IC structure according to claim 1 , wherein a lower face of the interconnect and a lower face of the ...

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Номер записи: 56
27-02-2020 дата публикации

ENGINEERING TENSILE STRAIN BUFFER IN ART FOR HIGH QUALITY GE CHANNEL

Номер: US20200066515A1
Автор: Agrawal Ashish, Chu-Kung Benjamin, FRENCH Marc C., Kavalieros Jack T., Le Van H., Metz Matthew V., Rachmady Willy, SUNG Seung Hoon
Принадлежит:

An apparatus including a transistor device including a channel including germanium disposed on a substrate; a buffer layer disposed on the substrate between the channel and the substrate, wherein the buffer layer includes silicon germanium; and a seed layer disposed on the substrate between the buffer layer and the substrate, wherein the seed layer includes germanium. A method including forming seed layer on a silicon substrate, wherein the seed layer includes germanium; forming a buffer layer on the seed layer, wherein the buffer layer includes silicon germanium; and forming a transistor device including a channel on the buffer layer. 1. An transistor device comprising:a layer comprising germanium disposed over a substrate;a buffer layer disposed between the layer comprising germanium and the substrate, wherein the buffer layer comprises silicon germanium; anda seed layer disposed between the buffer layer and the substrate, wherein the seed layer comprises germanium.2. The transistor device of claim 1 , wherein the buffer layer is tensile strained.3. The transistor device of claim 1 , wherein the substrate comprises silicon.4. The transistor device of claim 1 , wherein the seed layer comprises a thickness such that the germanium is fully relaxed.5. The transistor device of claim 1 , wherein the silicon germanium of the buffer layer comprises a similar lattice constant as a lattice constant of the germanium of the seed layer.6. The transistor device of claim 1 , wherein the silicon germanium of the buffer layer comprises a similar lattice constant as a lattice constant of the layer comprising germanium.7. The transistor device of claim 1 , wherein the transistor device comprises a p-type transistor device.8. A p-type transistor device comprising:a layer comprising germanium disposed over a substrate;a buffer layer disposed between the layer comprising germanium and the substrate, wherein the buffer layer comprises silicon germanium; anda seed layer disposed between ...

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Номер записи: 57
27-02-2020 дата публикации

FIELD EFFECT TRANSISTORS WITH WIDE BANDGAP MATERIALS

Номер: US20200066843A1
Автор: Dewey Gilbert, Ghani Tahir, HUANG CHENG-YING, Kavalieros Jack T., Kennel Harold W., Ma Sean T., Metz Matthew V., Murthy Anand S., Rachmady Willy
Принадлежит:

An electronic device comprises a channel layer on a buffer layer on a substrate. The channel layer has a first portion and a second portion adjacent to the first portion. The first portion comprises a first semiconductor. The second portion comprises a second semiconductor that has a bandgap greater than a bandgap of the first semiconductor. 1. An electronic device comprising:a semiconductor channel layer on a buffer layer on a substrate, the semiconductor channel layer having a first portion and a second portion adjacent to the first portion, the first portion comprising a first semiconductor, the second portion comprising a second semiconductor that has a bandgap greater than a bandgap of the first semiconductor; anda gate electrode on the semiconductor channel layer.2. The electronic device of claim 1 , wherein the second semiconductor has a conduction band that has a zero offset relative to the conduction band of the first semiconductor.3. The electronic device of claim 1 , wherein the second semiconductor has a dopant concentration equal or smaller than 10{circumflex over ( )}16 atoms/cm{circumflex over ( )}.4. The electronic device of claim 1 , wherein each of the first semiconductor and the second semiconductor comprises a III-V semiconductor material.5. The electronic device of claim 1 , wherein the first semiconductor comprises indium gallium arsenide claim 1 , indium arsenide claim 1 , indium antimonide claim 1 , indium gallium antimonide claim 1 , indium gallium arsenide antimonide (InGaAsSb) claim 1 , indium gallium arsenide phosphide (InGaAsP) claim 1 , indium gallium phosphide antimonide (InGaPSb) claim 1 , indium aluminum arsenide antimonide (InAlAsSb) claim 1 , indium aluminum arsenide phosphide (InAlAsP) claim 1 , where 0≤x≤1 claim 1 , 0≤y≤1 claim 1 , or any combination thereof.6. The electronic device of claim 1 , wherein the second semiconductor comprises gallium arsenide claim 1 , indium phosphide claim 1 , gallium phosphide claim 1 , indium ...

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Номер записи: 58
27-02-2020 дата публикации

AN INDIUM-CONTAINING FIN OF A TRANSISTOR DEVICE WITH AN INDIUM-RICH CORE

Номер: US20200066855A1
Автор: Dewey Gilbert, Ghani Tahir, Glass Glenn A., Kavalieros Jack T., Kennel Harold W., Ma Sean T., Metz Matthew V., Mohapatra Chandra S., Murthy Anand S., Rachmady Willy
Принадлежит:

An apparatus including a transistor device disposed on a surface of a circuit substrate, the device including a body including opposing sidewalls defining a width dimension and a channel material including indium, the channel material including a profile at a base thereof that promotes indium atom diffusivity changes in the channel material in a direction away from the sidewalls. A method including forming a transistor device body on a circuit substrate, the transistor device body including opposing sidewalls and including a buffer material and a channel material on the buffer material, the channel material including indium and the buffer material includes a facet that promotes indium atom diffusivity changes in the channel material in a direction away from the sidewalls; and forming a gate stack on the channel material. 1. An apparatus comprising:a transistor device disposed on a surface of a circuit substrate, the device comprising a body comprising opposing sidewalls defining a width dimension and a channel material comprising indium, the channel material comprising a profile at a base thereof that promotes indium atom diffusivity changes in the channel material in a direction away from the sidewalls.2. The apparatus of claim 1 , wherein the channel material is a Group III to Group V compound material.3. The apparatus of claim 2 , wherein the channel material comprises indium-gallium-arsenide.4. The apparatus of claim 1 , wherein the channel material is disposed on a buffer material comprising a facet at an interface with the channel material that promotes indium atom diffusivity changes in the channel material in a direction away from the sidewalls.5. The apparatus of claim 4 , wherein the buffer material comprises germanium or a Group III to Group V compound material that is different than the channel material.6. The apparatus of claim 4 , wherein the facet comprises an inverse {111} facet.7. The apparatus of claim 1 , further comprising a gate stack on the ...

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Номер записи: 59
19-03-2015 дата публикации

CRUCIBLES MADE WITH THE COLD FORM PROCESS

Номер: US20150075418A1
Автор: Fonte Matthew V.
Принадлежит:

A crucible for growing crystals, the crucible being formed from Molybdenum and Rhenium. A crucible for growing crystals, the crucible being formed from a metal selected from Group V of the Periodic Table of the Elements. A crucible for growing crystals, the crucible comprising a body and a layer formed on at least a portion of the body, the layer being formed out of Molybdenum. 1. A crucible for growing crystals , the crucible including a material selected from tantalum , niobium , a tantalum alloy , and a niobium alloy , wherein the material has an ASTM grain size of 7 to 14.2. The crucible of claim 1 , wherein the material is tantalum.3. The crucible of claim 1 , wherein the material is niobium.4. The crucible of claim 1 , wherein the material is a tantalum alloy.5. The crucible of claim 1 , wherein the material is a niobium alloy.6. The crucible of claim 1 , wherein the material is niobium C-103 alloy.7. The crucible of claim 1 , wherein the material is one of a tantalum alloy and a niobium alloy claim 1 , and wherein the material further comprises at least one of silicon and thorium.8. The crucible of claim 1 , wherein the material is one of a tantalum alloy and a niobium alloy claim 1 , and wherein the material further comprises up to 700 ppm silicon.9. The crucible of claim 1 , wherein the material is one of a tantalum alloy and a niobium alloy claim 1 , and wherein the material further comprises up to 500 ppm thorium.10. The crucible of claim 1 , wherein the crucible is carbonized prior to use.11. The crucible of claim 10 , wherein the crucible is carbonized by annealing the crucible in a carbon-containing atmosphere.12. The crucible of claim 10 , wherein the crucible is carbonized at a temperature of 2200° to 2500° C.13. The crucible of claim 1 , wherein the material has an ASTM grain size of 10 to 14.14. A method for forming a crucible for growing crystals claim 1 , the method comprising:forming a preform blank of a material selected from tantalum, niobium, ...

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Номер записи: 60
27-02-2020 дата публикации

Load Control Device for High-Efficiency Loads

Номер: US20200067419A1
Автор: Harte Matthew V., Jr. Robert C., Newman, Salvestrini Chris J.
Принадлежит: Lutron Technology Company LLC

A two-wire load control device (such as, a dimmer switch) for controlling the amount of power delivered from an AC power source to an electrical load (such as, a high-efficiency lighting load) includes a thyristor coupled between the source and the load, a gate coupling circuit coupled between a first main load terminal and the gate of the thyristor, and a control circuit coupled to a control input of the gate coupling circuit. The control circuit generates a drive voltage for causing the gate coupling circuit to conduct a gate current to thus render the thyristor conductive at a firing time during a half cycle of the AC power source, and to allow the gate coupling circuit to conduct the gate current at any time from the firing time through approximately the remainder of the half cycle, where the gate coupling circuit conducts approximately no net average current to render and maintain the thyristor conductive. 1. A dimmer switch for controlling an amount of power delivered from an AC power source to a lighting load for controlling an intensity of the lighting load , the dimmer switch comprising:a triac adapted to be electrically coupled between the AC power source and the lighting load, the triac having first and second main terminals through which current can be conducted to energize the lighting load and a gate terminal through which current can be conducted to render the triac conductive between the first and second main terminals;a gate coupling circuit arranged to conduct current through the gate terminal of the triac; anda control circuit configured to control the gate coupling circuit to conduct a pulse of current through the gate terminal of the triac at a firing time during a present half-cycle of an AC mains voltage of the AC power source to render the triac conductive, the control circuit configured to control the firing time to adjust the intensity of the lighting load, the control circuit configured to control the gate coupling circuit to allow the ...

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Номер записи: 61
19-03-2015 дата публикации

METHOD OF FABRICATING METAL-INSULATOR-SEMICONDUCTOR TUNNELING CONTACTS USING CONFORMAL DEPOSITION AND THERMAL GROWTH PROCESSES

Номер: US20150076571A1
Автор: Chau Robert S., Dewey Gilbert, Kavalieros Jack T., Metz Matthew V., Mukherjee Niloy
Принадлежит: Intel Corporation

A contact to a source or drain region. The contact has a conductive material, but that conductive material is separated from the source or drain region by an insulator. 1. A device , comprising:a transistor with a source region and a drain region;an interlayer dielectric layer adjacent the transistor;a trench through the first interlayer dielectric layer to at least one of the source region and the drain region; anda conductive contact in the trench, the conductive contact being separated from the at least one of the source region and the drain region by a conformal insulating layer, wherein the conductive contact comprises a conformal conductive layer.2. The device of claim 1 , wherein the conductive contact further comprises a conductive fill material on the conformal conductive layer and substantially filling the trench.3. The device of claim 1 , wherein the transistor is a multigate transistor including a fin.4. The device of claim 3 , wherein the conformal insulating layer is on a top surface and side walls of the fin.5. The device of claim 1 , wherein the conformal insulating layer has a thickness of about 4 nanometers or less.6. The device of claim 1 , wherein the conductive contact conformal conductive layer has a thickness of less than 100 nanometers.7. The device of claim 1 , wherein the transistor is a P-type transistor and the conductive contact comprises a metal with a workfunction above about 5 eV.8. The device of claim 1 , wherein the transistor is an N-type transistor and the conductive contact comprises a metal with a workfunction below about 3.2 eV.9. The device of claim 1 , wherein the conductive contact conformal conductive layer comprises aluminum or nickel.10. The device of claim 1 , wherein the transistor has a channel region that comprises a group III-V material.11. The device of claim 1 , wherein the conformal insulating layer comprises hafnium oxide.12. The device of claim 1 , further comprising:a second interlayer dielectric layer;a first ...

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Номер записи: 62
07-03-2019 дата публикации

REMOTE LOAD CONTROL DEVICE CAPABLE OF ORIENTATION DETECTION

Номер: US20190073898A1
Автор: Dimberg Chris, Gage Alexander Wade, Harte Matthew V., Killo Jason C., Kreschollek Brad Michael, McDonald Matthew Phillip, Twaddell Daniel L.
Принадлежит: LUTRON ELECTRONICS CO., INC.

A remote control device is provided that is configured for use in a load control system that includes one or more electrical loads. The remote control device includes a mounting structure and a control unit, and the control unit is configured to be attached to the mounting structure in a plurality of different orientations. The control unit includes a user interface, an orientation sensing circuit, and a communication circuit. The control unit is configured to determine an orientation of the control unit via the orientation sensing circuit. The control unit is also configured to translate a user input from the user interface into control data to control an electrical load of the load control system based on the orientation of the control unit and/or provide a visual indication of an amount of power delivered to the electrical load based on the orientation of the control unit. 1. A control unit configured to be mounted to a mounting structure , the control unit comprising:a user interface;an orientation sensing circuit;a communication circuit configured to communicate messages; and determine an orientation of the control unit relative to the mounting structure in response to the orientation sensing circuit;', 'translate a user input from the user interface into control data based on the orientation of the control unit, the control data configured to control an electrical load of a load control system; and', 'cause the communication circuit to transmit a control signal comprising the control data., 'a control circuit, wherein the control unit is configured to be supported by the mounting structure in a plurality of orientations, and wherein the control circuit is configured to2. The control unit of claim 1 , wherein the user interface comprises an actuation portion configured to receive the user input.3. The control unit of claim 2 , wherein the control circuit is configured to translate an actuation of an upper portion of the actuation portion into an on command for ...

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Номер записи: 63
14-03-2019 дата публикации

ERGONOMIC CONTAINER WITH THUMB HOLE

Номер: US20190077545A1
Автор: Bergman Mark W., Given Jeffrey T., Leyden Matthew V., Waffensmith Jeffrey B.
Принадлежит:

An apparatus includes a bottom wall, a plurality of connected walls attached to the bottom wall to define a cavity having a top rim, and a flange extending laterally outward from the top rim. At least a portion of the flange extends downwardly from the top rim. The portion of the flange includes an aperture configured to accept a user's thumb, and the portion of the flange is substantially symmetrical about a center line of the apparatus. 1. An apparatus including:a bottom wall;a plurality of connected walls attached to the bottom wall to define a cavity having a top rim; and at least a portion of the flange extends downwardly from the top rim;', "the portion of the flange includes an aperture configured to accept a user's thumb; and", 'the portion of the flange is substantially symmetrical about a center line of the apparatus., 'a flange extending laterally outward from the top rim, wherein2. The apparatus of wherein the apparatus is substantially symmetrical about the center line.3. The apparatus of further including a depression located on the flange claim 1 , wherein the aperture is located on the depression.4. The apparatus of further including a notch on the top rim.5. The apparatus of wherein the notch connects the aperture and the cavity.6. The apparatus of further including a surface that extends laterally from at least one of the connected walls and below the top rim.7. The apparatus of further including a portion connected to the surface claim 6 , wherein the portion does not extend a full width of the surface.8. The apparatus of wherein the portion includes a raised element.9. The apparatus of wherein the raised element is formed as a curvilinear ridge.10. The apparatus of wherein the curvilinear ridge includes a peak along the center line.11. The apparatus of wherein the surface extends from an end wall that is connected to two opposed outer side walls claim 6 , and wherein a width of the surface is less than a distance between the two opposed outer ...

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Номер записи: 64
14-03-2019 дата публикации

Load Control Device for High-Efficiency Loads

Номер: US20190081568A1
Автор: Christopher J. Salvestrini, Daniel F. Carmen, Matthew V. Harte, Robert C. Newman, Jr.
Принадлежит: Lutron Electronics Co Inc

A load control device for controlling the power delivered from an AC power source to an electrical load includes a thyristor, a gate coupling circuit for conducting a gate current through a gate of the thyristor, and a control circuit for controlling the gate coupling circuit to conduct the gate current through a first current path to render the thyristor conductive at a firing time during a half cycle. The gate coupling circuit is able to conduct the gate current through the first current path again after the firing time, but the gate current is not able to be conducted through the gate from a transition time before the end of the half-cycle until approximately the end of the half-cycle. The load current is able to be conducted through a second current path to the electrical load after the transition time until approximately the end of the half-cycle.

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Номер записи: 65
14-03-2019 дата публикации

Load Control Device for High-Efficiency Loads

Номер: US20190081569A1
Автор: Harte Matthew V., Jr. Robert C., Newman, Salvestrini Chris J.
Принадлежит: LUTRON ELECTRONICS CO., INC.

A two-wire load control device (such as, a dimmer switch) for controlling the amount of power delivered from an AC power source to an electrical load (such as, a high-efficiency lighting load) includes a thyristor coupled between the source and the load, a gate coupling circuit coupled between a first main load terminal and the gate of the thyristor, and a control circuit coupled to a control input of the gate coupling circuit. The control circuit generates a drive voltage for causing the gate coupling circuit to conduct a gate current to thus render the thyristor conductive at a firing time during a half cycle of the AC power source, and to allow the gate coupling circuit to conduct the gate current at any time from the firing time through approximately the remainder of the half cycle, where the gate coupling circuit conducts approximately no net average current to render and maintain the thyristor conductive. 1. A dimmer switch for controlling an amount of power delivered from an AC power source to an lighting load for controlling an intensity of the lighting load , the dimmer switch comprising:a triac adapted to be electrically coupled between the AC power source and the lighting load, the triac having first and second main terminals through which current can be conducted to energize the lighting load and a gate terminal through which current can be conducted to render the triac conductive between the first and second main terminals;a gate coupling circuit electrically coupled to the first main terminal of the triac and arranged to conduct current through the gate terminal of the triac;a controllable switching circuit electrically coupled in series between the gate coupling circuit and the gate terminal of the triac and configured to conduct current through the gate terminal of the triac; anda control circuit configured to render the controllable switching circuit conductive and to control the gate coupling circuit to conduct a pulse of current through the gate ...

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Номер записи: 66
02-04-2015 дата публикации

HAND-HELD VESSEL

Номер: US20150090747A1
Автор: Bergman Mark W., Leyden Matthew V., Waffensmith Jeffrey B.
Принадлежит:

A hand-held vessel has a bottom wall, a sidewall and a supportive strap attached to the bottom wall and the sidewall. The bottom wall and sidewall have an inner and outer surface. The sidewall extends from the bottom wall, whereby the inner surfaces of the bottom wall and sidewall define a cavity for holding fluids or loose materials therein. The strap has a first end and a second end, whereby the first end is fixedly attached to the sidewall and the second end is selectively secured to the bottom wall. The strap is adaptable to accept a user's hand disposed between the strap and the outer surface of the sidewall. The strap urges the hand against the outer surface of the sidewall to secure the vessel to the hand and stabilize the vessel with respect to movement relative to the hand. 1. A hand-held vessel comprising:a bottom wall having an inner surface and an outer surface;a sidewall extending from the bottom wall, the sidewall having an inner surface and an outer surface, wherein the inner surfaces of the bottom wall and the sidewall define a fluid holding cavity; anda strap having a first end and a second end, wherein the first end is connected to the outer surface of the sidewall and the second end is connectable to the outer surface of the bottom wall.2. The hand-held vessel of claim 1 , wherein the second end of the strap is connectable to a plurality of locations along the outer surface of the bottom wall.3. The hand-held vessel of claim 2 , wherein the outer surface of the bottom wall comprises one or more protrusions claim 2 , and wherein the second end of the strap comprises one or more holes engagable with the protrusions.4. The hand-held vessel of claim 1 , wherein a lower portion of the sidewall extends beyond the outer surface of the bottom wall in a direction substantially normal to the outer surface of the bottom wall.5. The hand-held vessel of claim 4 , wherein the lower portion of the sidewall defines a cutout for receiving the second end of the ...

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Номер записи: 67
31-03-2022 дата публикации

LOW RESISTANCE APPROACHES FOR FABRICATING CONTACTS AND THE RESULTING STRUCTURES

Номер: US20220102521A1
Автор: Chouksey Siddharth, Dewey Gilbert, GANGULY Koustav, Glass Glenn A., HARATIPOUR Nazila, JHA Jitendra Kumar, Kavalieros Jack T., KEECH Ryan, LU Mengcheng, Metz Matthew V., Murthy Anand S., Sen Gupta Arnab
Принадлежит:

Low resistance approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is directly on the first or second semiconductor source or drain structure, the source or drain contact including a barrier layer and an inner conductive structure. 1. An integrated circuit structure , comprising:a semiconductor structure above a substrate;a gate electrode over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure;a first semiconductor source or drain structure at a first end of the channel region at a first side of the gate electrode;a second semiconductor source or drain structure at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end; anda source or drain contact directly on the first or second semiconductor source or drain structure, the source or drain contact comprising a barrier layer and an inner conductive structure, wherein the barrier layer is metal nitride barrier layer or a metal carbide barrier layer.2. The integrated circuit structure of claim 1 , wherein the barrier layer comprises a metal carbide material selected from the group consisting of zirconium carbide claim 1 , hafnium carbide claim 1 , titanium carbide claim 1 , tantalum carbide claim 1 , tungsten carbide claim 1 , titanium aluminum carbide claim 1 , tantalum aluminum carbide claim 1 , ...

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Номер записи: 68
31-03-2022 дата публикации

Low resistance and reduced reactivity approaches for fabricating contacts and the resulting structures

Номер: US20220102522A1
Автор: Anand S. Murthy, Arnab SEN GUPTA, Christopher J. Jezewski, Gilbert Dewey, I-Cheng Tung, Matthew V. Metz, Nazila Haratipour, Siddharth Chouksey
Принадлежит: Intel Corp

Low resistance and reduced reactivity approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is on the first or second semiconductor source or drain structure, the source or drain contact including an alloyed metal barrier layer and an inner conductive structure.

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Номер записи: 69
12-03-2020 дата публикации

USER INTERFACE FOR A CONTROL DEVICE

Номер: US20200084866A1
Автор: Bard Benjamin F., Dimberg Chris, Harte Matthew V., Killo Jason C., McDonald Matthew Philip, Twaddell Daniel L.
Принадлежит: Lutron Technology Company LLC

A battery-powered control device may be configured to control an amount of power delivered to one or more electrical loads and provide various feedback associated with the control device and/or the electrical loads. The feedback may indicate a low battery condition and/or the amount of power delivered to the one or more electrical loads. The control device may include a light bar and/or one or more indicator lights for providing the feedback. The control device may operate in different modes including a normal mode and a low battery mode. 1. A battery-powered control device for controlling an electrical load in a load control system , the control device comprising:a base portion;a control unit configured to control an amount of power delivered to the electrical load;a battery compartment configured to store a battery for powering the control unit;a control unit removal device operable to release the control unit from the base portion to provide access to the battery compartment; anda low battery indicator configured to be illuminated by one or more light sources to indicate a low battery condition and a location of the control unit removal device;wherein the control unit is further configured to detect the low battery condition and control the one or more light sources to illuminate the low battery indicator in response to detecting the low battery condition.2. The control device of claim 1 , wherein the control unit removal device comprises a release tab configured to provide access to the battery compartment when the release tab is pulled or pushed.3. The control device of claim 1 , wherein the control unit is configured to detect the low battery condition and control the one or more light sources to illuminate the low battery indicator in further response to determining that the control device has been activated.4. The control device of claim 3 , wherein the control unit is configured to determine that the control device has been activated based on detection of a ...

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Номер записи: 70
25-03-2021 дата публикации

Self-aligned gate endcap (sage) architectures without fin end gap

Номер: US20210091075A1
Автор: Diane LANCASTER, Florian Gstrein, Jessica TORRES, Kiran Chikkadi, Lukas BAUMGARTEL, Martin M. MITAN, Matthew V. Metz, Rami HOURANI, Scott B. Clendenning, Szuya S. LIAO
Принадлежит: Intel Corp

Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

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Номер записи: 71
21-03-2019 дата публикации

SELECTIVE EPITAXIALLY GROWN III-V MATERIALS BASED DEVICES

Номер: US20190088747A1
Автор: Chau Robert S., Chu-Kung Benjamin, Dewey Gilbert, GOEL Niti, Kavalieros Jack T., Metz Matthew V., Mukherjee Niloy, RADOSAVLIJEVIC Marko
Принадлежит:

A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer. 1. An integrated circuit structure , comprising:a substrate comprising monocrystalline silicon;an insulating layer on the substrate, the insulating layer comprising silicon and oxygen, and the insulating layer having a trench therein exposing a monocrystalline silicon surface of the substrate;a first buffer layer in the trench and on the monocrystalline silicon surface of the substrate, the first buffer layer comprising indium and phosphorous;a second buffer layer in the trench and on the first buffer layer, the second buffer layer comprising indium, gallium, arsenic and antimony; anda device channel layer on the second buffer layer, the device layer comprising indium, gallium, and arsenic, the device channel layer having a top and sidewalls.2. The integrated circuit structure of claim 1 , further comprising a gate dielectric layer and a gate electrode on the top and sidewalls of the device channel layer.3. The integrated circuit structure of claim 2 , further comprising:a first source or drain region at a first side of the gate electrode; anda second source or drain region at a second side of the gate electrode, the second side opposite the first side.4. The integrated circuit structure of claim 2 , wherein the gate dielectric layer comprises hafnium and oxygen.5. The integrated circuit structure of claim 2 , wherein the gate dielectric layer comprises silicon and oxygen.6. The integrated circuit structure of claim 1 , wherein the device channel layer is a transistor channel layer.7. The integrated circuit structure of claim 1 , wherein the second buffer layer extends above the insulating layer.8. The integrated circuit structure of claim 1 , wherein the device channel layer has ...

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Номер записи: 72
30-03-2017 дата публикации

TEMPORARY SUSPENSION OF ELECTRONIC COMMUNICATIONS

Номер: US20170093773A1
Автор: Abbott Matthew V., Alvarado David, Brett Jason B., Busler Eric, Cai Jason, Dernavich Jeffrey S., Tsymbler Sergey
Принадлежит:

Disclosed are various embodiments for a transmission service to suspend temporarily transmission of electronic communications to a recipient. In one embodiment, the transmission service receives a request to suspend receiving electronic communications temporarily for a suspension period. In response, the transmission service suspends transmitting electronic communications to the recipient during the duration of the suspension period. Then, the transmission service resumes transmitting electronic communications to the recipient upon the expiration of the suspension period. 1. A non-transitory computer-readable medium embodying a program executable in a computing device , comprising:code configured to receive a first request to suspend transmission of electronic communications to a recipient during a suspension period, wherein the first request is associated with a recipient identifier (ID) and is received in response to a determination to suspend transmission based at least in part on a magnitude of sales associated with a previous transmission of electronic communications to the recipient;code configured to associate the recipient ID with a suspension state in response to receiving the first request to suspend transmission of the electronic communications;code configured to receive a second request to transmit an electronic communication to the recipient; andcode configured to prevent transmitting the electronic communication to the recipient during the suspension period based on the association of the recipient ID with the suspension state.2. The non-transitory computer-readable medium of claim 1 , further comprising:code configured to receive a distribution list comprising correspondence information of a plurality of recipients;code configured to determine whether each one of the recipients included in the distribution list has previously requested to suspend receiving electronic communications; andresponsive to the determination that one of the recipients has not ...

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Номер записи: 73
12-05-2022 дата публикации

REMOTE LOAD CONTROL DEVICE CAPABLE OF ORIENTATION DETECTION

Номер: US20220148827A1
Автор: Dimberg Chris, Gage Alexander Wade, Harte Matthew V., Killo Jason C., Kreschollek Brad Michael, McDonald Matthew Philip, Twaddell Daniel L.
Принадлежит: Lutron Technology Company LLC

A remote control device is provided that is configured for use in a load control system that includes one or more electrical loads. The remote control device includes a mounting structure and a control unit, and the control unit is configured to be attached to the mounting structure in a plurality of different orientations. The control unit includes a user interface, an orientation sensing circuit, and a communication circuit. The control unit is configured to determine an orientation of the control unit via the orientation sensing circuit. The control unit is also configured to translate a user input from the user interface into control data to control an electrical load of the load control system based on the orientation of the control unit and/or provide a visual indication of an amount of power delivered to the electrical load based on the orientation of the control unit. 1. A method for controlling a control device that is configured for use in a load control system , the method comprising:determining an orientation of a control unit of the control device relative to a mounting structure of the control device via an orientation sensing circuit of the control device, wherein the control unit is configured to be attached to the mounting structure in a plurality of orientations;translating a user input from a user interface of the control device into control data based on the orientation of the control unit, the control data configured to control an electrical load of a load control system; andcontrolling the at least one light source to provide a visual indication based on the orientation.2. The method of claim 1 , wherein the at least one light source comprises a plurality of light sources claim 1 , and the user interface comprises a light bar configured to be illuminated by the plurality of light sources claim 1 , and wherein the method further comprises:controlling the plurality of light sources based on the orientation of the control unit to provide a visual ...

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Номер записи: 74
28-03-2019 дата публикации

BEADED FIN TRANSISTOR

Номер: US20190097055A1
Автор: Dewey Gilbert, Ghani Tahir, Kavalieros Jack T., Metz Matthew V., Mohapatra Chandra S., Murthy Anand S., Rachmady Willy
Принадлежит: Intel Corporation

Techniques are disclosed for forming a beaded fin transistor. As will be apparent in light of this disclosure, a transistor including a beaded fin configuration may be formed by starting with a multilayer finned structure, and then selectively etching one or more of the layers to form at least one necked (or relatively narrower) portion, thereby forming a beaded fin structure. The beaded fin transistor configuration has improved gate control over a finned transistor configuration having the same top down area or footprint, because the necked/narrower portions increase gate surface area as compared to a non-necked finned structure, such as finned structures used in finFET devices. Further, because the beaded fin structure remains intact (e.g., as compared to a gate-all-around (GAA) transistor configuration where nanowires are separated from each other), the parasitic capacitance problems caused by GAA transistor configurations are mitigated or eliminated. 1. An integrated circuit including at least one transistor , the integrated circuit comprising:a gate structure including a gate dielectric and a gate electrode; and a first layer including a first semiconductor material, the first layer having a first minimum width between the portions of the gate structure, and', 'a second layer in contact with the first layer, the second layer including a second semiconductor material compositionally different from the first semiconductor material, the second layer having a second minimum width between the portions of the gate structure, the first minimum width less than the second minimum width., 'a fin below the gate structure, the fin also between portions of the gate structure, the fin including'}2. The integrated circuit of claim 1 , wherein the first minimum width is in the range of 2 to 15 nanometers.3. The integrated circuit of claim 1 , wherein the second minimum width is in the range of 4 to 30 nanometers.4. The integrated circuit of claim 1 , wherein the first minimum ...

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Номер записи: 75
12-05-2022 дата публикации

CENTRALLY CONTROLLING COMMUNICATION AT A VENUE

Номер: US20220150360A1
Автор: Damori Jason E., Juszkiewicz Richard S., Kotvis Matthew V., Metzar Nicholas William
Принадлежит:

One example may include a method that includes receiving, at a server, a data set from one or more mobile devices located in a presentation space, combining the received data set with additional data to create a combined data set, creating a presentation signal based on the combined data set, subtracting a portion of one or more of the data set and the additional data set from the combined data set to create a modified presentation signal, forwarding the modified presentation signal to one or more of a display and a loudspeaker located in the presentation space, and playing the modified presentation signal via one or more of the loudspeaker and the display device. 1. A method comprising:receiving a data set comprising recorded audio from one or more mobile devices;combining the received data set with additional audio data recorded from a different device to create a combined data set;subtracting a portion of the recorded audio from the combined data set to create a modified presentation signal, wherein the subtracted portion of the one or more of the data set and the additional data comprises audio output of a loudspeaker recorded during a recording of the received data set; andplaying the modified presentation signal via the loudspeaker.2. The method of claim 1 , wherein the received data set further comprises one or more of textual data claim 1 , image data and video data.3. The method of claim 1 , wherein the subtracted portion of the one or more of the data set and the additional data further comprises audio output associated with audience members of the presentation near the mobile device which recorded the data set.4. The method of claim 1 , comprisingadding a watermark signal to the data set prior to forwarding the data set from the one or more mobile devices.5. The method of claim 4 , wherein the watermark signal comprises identification information associated with the one or more mobile devices claim 4 , location information of the one or more mobile ...

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Номер записи: 76
13-04-2017 дата публикации

MODULAR TURF SYSTEM AND METHOD OF TURF INSTALLATION

Номер: US20170101743A1
Автор: Scavo Matthew V., Sternberg David J.
Принадлежит:

The present subject matter relates to a method and system for synthetic turf and the installation thereof. Modular turf sections are formed by attaching a turf section to a corresponding base structure of any desired size and shape. The base structure has a smooth top surface and smooth edges, and can be cut to any desired shape, angle or cutout. The base structure may include a PVC flushing system. The modular turf sections are laid side by side to cover a surface having any size and shape. The modular turf sections are portable and can be individually lifted after having been installed, thereby allowing for cleaning, repair and/or access under one or more selected modular turf sections, or for the replacement of selected modular turf sections which become worn or damaged. 1. A modular turf section , comprising:a base structure having a customizable size and shape;a turf section of a size and shape substantially corresponding to the size and shape of the base structure;one or more fasteners for securing the turf section to the base structure- andat least one flush pipe associated with the base structure.2. The modular turf section of claim 1 , wherein the base structure is formed from interconnecting drainage tiles.3. The modular turf section of claim 2 , wherein the interconnecting drainage include a flushing system.4. The modular turf section of claim 1 , wherein the turf section comprises synthetic turf having a permeable backing.5. The modular turf section of claim 4 , wherein the synthetic turf further includes antimicrobial agents.6. The modular turf section of claim 1 , wherein the modular turf section is portable.7. A modular turf system claim 1 , comprising:a plurality of modular turf sections, each comprising a base structure having a customizable size and shape with a corresponding turf section attached thereto; anda flushing system incorporated within the plurality of modular turf sections,wherein the modular turf sections have smooth edges; andwherein ...

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Номер записи: 77
23-04-2015 дата публикации

LOAD CONTROL DEVICE FOR HIGH-EFFICIENCY LOADS

Номер: US20150108913A1
Автор: Harte Matthew V., Jr. Robert C., Newman, Salvestrini Chris J.
Принадлежит:

A two-wire load control device (such as, a dimmer switch) for controlling the amount of power delivered from an AC power source to an electrical load (such as, a high-efficiency lighting load) includes a thyristor coupled between the source and the load, a gate coupling circuit coupled between a first main load terminal and the gate of the thyristor, and a control circuit coupled to a control input of the gate coupling circuit. The control circuit generates a drive voltage for causing the gate coupling circuit to conduct a gate current to thus render the thyristor conductive at a firing time during a half cycle of the AC power source, and to allow the gate coupling circuit to conduct the gate current at any time from the firing time through approximately the remainder of the half cycle, where the gate coupling circuit conducts approximately no net average current to render and maintain the thyristor conductive. 1. A load control device for controlling power delivered from an AC power source to an electrical load , the load control device comprising:a thyristor adapted to be electrically coupled between the AC power source and the electrical load, the thyristor having first and second main terminals through which current can be conducted to energize the electrical load and a gate terminal through which current can be conducted to render the thyristor conductive between the first and second main terminals;a gate coupling circuit electrically coupled to the first main terminal of the thyristor and arranged to conduct current through the gate terminal of the thyristor;a controllable switching circuit electrically coupled in series between the gate coupling circuit and the gate terminal of the thyristor and configured to conduct current through the gate terminal of the thyristor; anda control circuit configured to render the controllable switching circuit conductive and to control the gate coupling circuit to conduct a pulse of current through the gate terminal of the ...

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Номер записи: 78
26-03-2020 дата публикации

HIGH PERFORMANCE SEMICONDUCTOR OXIDE MATERIAL CHANNEL REGIONS FOR NMOS

Номер: US20200098753A1
Автор: Dewey Gilbert, Ghani Tahir, HUANG CHENG-YING, Kavalieros Jack T., KENNEL Harold, Ma Sean T., Metz Matthew V., Rachmady Willy, SHARMA Abhishek A.
Принадлежит: Intel Corporation

Techniques are disclosed for integrating semiconductor oxide materials as alternate channel materials for n-channel devices in integrated circuits. The semiconductor oxide material may have a wider band gap than the band gap of silicon. Additionally or alternatively, the high mobility, wide band gap semiconductor oxide material may have a higher electron mobility than silicon. The use of such semiconductor oxide materials can provide improved NMOS channel performance in the form of less off-state leakage and, in some instances, improved electron mobility as compared to silicon NMOS channels. 1. An integrated circuit structure , comprising:a first fin comprising a semiconductor oxide material, the semiconductor oxide material including oxygen and one or more of indium (In), gallium (Ga), zinc (Zn), copper (Cu), tin (Sn), nickel (Ni), titanium (Ti), aluminum (Al), or antimony (Sb);a first gate structure over the first fin and in contact with the semiconductor oxide material, the first gate structure being part of an NMOS transistor device;a second fin comprising semiconductor material; anda second gate structure over the second fin and in contact with the semiconductor material of the second fin, the second gate structure being part of a PMOS device.2. The integrated circuit structure of claim 1 , wherein the semiconductor oxide material is InGaZnO.3. The integrated circuit structure of claim 1 , wherein the semiconductor oxide material is InO.4. The integrated circuit structure of claim 1 , wherein the semiconductor oxide material is ITO.5. The integrated circuit structure of claim 1 , wherein the semiconductor oxide material is InSbO.6. The integrated circuit structure of claim 1 , wherein the semiconductor oxide material is ZnO.7. The integrated circuit structure of claim 1 , wherein the semiconductor oxide material is AlZnO.8. The integrated circuit structure of claim 1 , wherein the semiconductor oxide material is GaO.9. The integrated circuit structure of claim ...

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Номер записи: 79
26-03-2020 дата публикации

CONTACT STACKS TO REDUCE HYDROGEN IN SEMICONDUCTOR DEVICES

Номер: US20200098874A1
Автор: Chu-Kung Benjamin, Ghani Tahir, JEZEWSKI CHRISTOPHER, Kavalieros Jack T., KENNEL Harold, Le Van H., Metz Matthew V., Sen Gupta Arnab, Sharma Abhishek, WEBER Justin
Принадлежит:

Embodiments herein describe techniques for an integrated circuit that includes a substrate, a semiconductor device on the substrate, and a contact stack above the substrate and coupled to the semiconductor device. The contact stack includes a contact metal layer, and a semiconducting oxide layer adjacent to the contact metal layer. The semiconducting oxide layer includes a semiconducting oxide material, while the contact metal layer includes a metal with a sufficient Schottky-barrier height to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack. Other embodiments may be described and/or claimed. 1. An integrated circuit , comprising:a substrate;a semiconductor device on the substrate; a contact metal layer; and', 'a semiconducting oxide layer above the contact metal layer, wherein the semiconducting oxide layer includes a semiconducting oxide material, the contact metal layer includes a metal with a sufficient Schottky-barrier height (SBH) to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack., 'a contact stack above the substrate and coupled to the semiconductor device, wherein the contact stack includes2. The integrated circuit of claim 1 , wherein the interstitial hydrogen behaves exclusively as a donor in the semiconducting oxide layer claim 1 , and the rejected interstitial hydrogen is positively charged atomic hydrogen.3. The integrated circuit of claim 1 , wherein the interstitial hydrogen behaves exclusively as an acceptor in the semiconducting oxide layer claim 1 , and the rejected interstitial hydrogen is negatively charged atomic hydrogen.4. The integrated circuit of claim 1 , wherein the semiconducting oxide material is an n-type material or a p-type material.5 ...

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Номер записи: 80
26-03-2020 дата публикации

Ferroelectric gate stack for band-to-band tunneling reduction

Номер: US20200098925A1
Автор: Cheng-Ying Huang, Gilbert Dewey, Harold Kennel, Jack T. Kavalieros, Matthew V. Metz, Sean T. MA, Tahir Ghani, Willy Rachmady
Принадлежит: Intel Corp

Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.

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Номер записи: 81
26-03-2020 дата публикации

VERTICAL THIN-FILM TRANSISTORS BETWEEN METAL LAYERS

Номер: US20200098931A1
Автор: Chu-Kung Benjamin, Dewey Gilbert, Ghani Tahir, HARATIPOUR Nazila, Kavalieros Jack T., Le Van H., Metz Matthew V., Sen Gupta Arnab, Sharma Abhishek, SHIVARAMAN Shriram, SUNG Seung Hoon
Принадлежит:

Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate oriented in a horizontal direction and a transistor above the substrate. The transistor includes a gate electrode above the substrate, a gate dielectric layer around the gate electrode, and a channel layer around the gate dielectric layer, all oriented in a vertical direction substantially orthogonal to the horizontal direction. Furthermore, a first metal electrode located in a first metal layer is coupled to a first portion of the channel layer by a first short via, and a second metal electrode located in a second metal layer is coupled to a second portion of the channel layer by a second short via. Other embodiments may be described and/or claimed. 1. A semiconductor device , comprising:a substrate oriented in a horizontal direction; a gate electrode above the substrate, oriented in a vertical direction substantially orthogonal to the horizontal direction;', 'a gate dielectric layer including a gate dielectric material, the gate dielectric layer oriented in the vertical direction, around the gate electrode, and above the substrate;', 'a channel layer including a channel material, the channel layer oriented in the vertical direction, around the gate dielectric layer, and above the substrate;', 'a first metal electrode located in a first metal layer, and a first short via below the channel layer, wherein the first metal electrode is coupled to the first short via, and the first short via is coupled to a first portion of the channel layer and separated from the gate electrode; and', 'a second metal electrode located in a second metal layer, and a second short via above the channel layer, wherein the second metal electrode is coupled to the second short via, and the second short via is coupled to a second portion of the channel layer and separated from the gate electrode., 'a transistor above the substrate, wherein the transistor includes2. The semiconductor device ...

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Номер записи: 82
13-04-2017 дата публикации

CONTROLLABLE-LOAD CIRCUIT FOR USE WITH A LOAD CONTROL DEVICE

Номер: US20170105255A1
Автор: Bedell Ryan S., Harte Matthew V., Salvestrini Christopher James
Принадлежит:

A load control device for controlling the amount of power delivered from an AC power source to an electrical load is operable to conduct enough current through a thyristor of a connected dimmer switch to exceed rated latching and holding currents of the thyristor. The load control device comprises a controllable-load circuit operable to conduct a controllable-load current through the thyristor of the dimmer switch. The load control device disables the controllable-load circuit when the phase-control voltage received from the dimmer switch is a reverse phase-control waveform. When the phase-control voltage received from the dimmer switch is a forward phase-control waveform, the load control device is operable to decrease the magnitude of the controllable-load current so as to conduct only enough current as is required in order to exceed rated latching and holding currents of the thyristor. 1. A method for controlling an amount of power delivered from an AC power source to an electrical load , the method comprising:receiving a phase-control voltage from a dimmer switch, the phase-control voltage characterized by a conduction period;controlling the amount of power delivered to the electrical load in response to the conduction period of the phase-control voltage;conducting a controllable-load current from the AC power source through the dimmer switch;maintaining the magnitude of the controllable-load current constant for at least a portion of each half-cycle of the AC power source; anddecreasing the magnitude at which the controllable-load current is maintained constant from an initial magnitude in a first half-cycle to a decreased magnitude in a second subsequent half-cycle, such that the conduction period of the phase-control voltage in the first and half-cycles.2. The method of claim 1 , further comprising:monitoring the conduction period of the phase-control voltage; andadjusting the magnitude at which the controllable-load current is maintained constant in response ...

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Номер записи: 83
04-04-2019 дата публикации

GERMANIUM TRANSISTOR STRUCTURE WITH UNDERLAP TIP TO REDUCE GATE INDUCED BARRIER LOWERING/SHORT CHANNEL EFFECT WHILE MINIMIZING IMPACT ON DRIVE CURRENT

Номер: US20190103486A1
Автор: Agrawal Ashish, Chu-Kung Benjamin, Kavalieros Jack T., Le Van H., Metz Matthew V., Rachmady Willy
Принадлежит:

An apparatus including a transistor device including a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel includes a length dimension between source and drain that is greater than a length dimension of the gate electrode such that there is a passivated underlap between an edge of the gate electrode and an edge of the channel relative to each of the source and the drain. A method including forming a channel of a transistor device on a substrate; forming first and second passivation layers on a surface of substrate on opposite sides of the channel; forming a gate stack on the channel between first and second passivation layers; and forming a source on the substrate between the channel and the first passivation layer and a drain on the substrate between the channel and the second passivation layer. 1. An apparatus comprising:a transistor device comprising a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel comprises a length dimension between the source and the drain that is greater than a length dimension of the gate electrode such that there is an underlap between an edge of the gate electrode and an edge of the channel relative to each of the source and the drain, wherein the underlap is passivated.2. The apparatus of claim 1 , wherein the channel comprises germanium.3. The apparatus of claim 1 , wherein the underlap is passivated with silicon.4. The apparatus of claim 3 , wherein the silicon has a thickness of 3 angstroms to 9 angstroms.5. The apparatus of claim 1 , further comprising a sidewall spacer on the underlap.6. The apparatus of claim 1 , wherein the underlap is at least two nanometers.7. The apparatus of claim 1 , wherein the transistor device comprises a p-type transistor device.8. An apparatus comprising:a p-type transistor device comprising:a channel comprising germanium between a source and a drain, each of ...

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Номер записи: 84
21-04-2016 дата публикации

EXTREME HIGH MOBILITY CMOS LOGIC

Номер: US20160111423A1
Автор: AmIan Majumdar, Brask Justin K., Chau Robert S., Datta Suman, DOCZY Mark L., Hudait Mantu K., Jin Been-Yih, Kavalieros Jack T., Metz Matthew V.
Принадлежит:

A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate. 1. A transistor , comprising:a doped silicon semi-insulating substrate;a buffer layer disposed above the doped silicon semi-insulating substrate;a bottom barrier layer disposed above the buffer layer wherein the bottom barrier layer comprises a material different than the buffer layer;a group III-V material quantum well layer disposed above the bottom barrier layer;a top barrier layer disposed above the group III-V material quantum well layer; a high-k gate dielectric layer disposed above the top barrier layer; and', 'a metal gate electrode disposed above the high-k gate dielectric layer; and, 'a gate stack disposed above the top barrier layer, the gate stack comprisingraised source and drain regions disposed above an etch stop layer disposed above the top barrier layer, the raised source and drain regions disposed on either side of the gate stack.2. The transistor of claim 1 , wherein the group III-V material quantum well layer is an indium arsenide (InAs) quantum well layer.3. The transistor of claim 1 , wherein the high-k gate dielectric layer is an aluminum oxide (AlO) high-k gate dielectric layer.4. The transistor of claim 3 , wherein the aluminum oxide (AlO) high-k gate dielectric layer has a thickness approximately in the range of 1.5-7.5 nanometers.5. The transistor of claim 1 , wherein the metal gate electrode has a gate length approximately in the range of 20-250 nanometers.6. The transistor of claim 1 , wherein the etch stop layer has a thickness approximately in the range of 1-5 nanometers.7. The transistor of claim 1 , wherein the group III-V material quantum well layer has a thickness approximately in the range of 5-30 nanometers.8. The transistor of claim 1 , wherein the buffer layer comprises indium (In) and aluminum (Al).9. The transistor of claim 1 , wherein ...

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Номер записи: 85
28-04-2016 дата публикации

ANKLE FLOAT BUOY

Номер: US20160114234A1
Автор: Bayer Philip M., DiLorenzo Matthew V., Sola Kyle D., Wang Yang
Принадлежит:

A unitary ankle float buoy for immobilizing the legs during swim training. The buoy is formed of a central portion connecting a top wall and a lower wall and a pair of ankle openings disposed on each side of the central portion. The ankle float buoy is designed and configured to be worn upon both ankles of a swimmer below the calf and above the foot. 1. A unitary ankle float buoy for immobilizing the legs during swim training , said buoy comprising:a central body;a left set of jaws comprising a first left jaw element comprising a first end attached to a left upper outside edge of the central body and extending away from the central body to a second end which curves downward, and a second left jaw element with a first end attached to a left lower outside edge of the central body and mirroring the first jaw element;a left gap formed between the second end of the first left jaw element and the second end of the second left jaw element;a right set of jaws comprising a first right jaw element comprising a first end attached to a right upper outside edge of the central body and extending away from the central body to a second end which curves downward, and a right second jaw element with a first end attached to a right lower outside edge of the central body and mirroring the first jaw element; anda right gap formed between the second end of the first right jaw element and the second end of the second right jaw element;wherein the first left jaw element, the second left jaw element, the first right jaw element, and second right jaw element all have a closed position to which the jaw elements are biased and return to without application of an outside force.2. The unitary ankle float buoy of claim 1 , wherein a rear edge narrows from the central body to a distal end to comfortably accommodate a swimmer's lateral malleolus.3. The unitary ankle float buoy of claim 1 , wherein a space between the first right jaw element and the second right jaw element forms a right ankle ...

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Номер записи: 86
09-04-2020 дата публикации

FGFR/PD-1 COMBINATION THERAPY FOR THE TREATMENT OF CANCER

Номер: US20200108141A1
Автор: Karkera Jayaprakash, LORENZI Matthew V., Platero Suso Jesus, Verona Raluca
Принадлежит: ASTEX THERAPEUTICS LTD

Provided herein are combination therapies for the treatment of cancer. In particular, the disclosed methods are directed to treatment of cancer in a patient comprising administering an antibody that blocks the interaction between PD-1 and PD-L1 and an FGFR inhibitor, wherein the antibody that blocks the interaction between PD-1 and PD-L1 and the FGFR inhibitor are administered if one or more FGFR variants are present in a biological sample from the patient. 1. A method of treating cancer in a patient , comprising:administering to the patient a pharmaceutically effective amount of an antibody that blocks the interaction between PD-1 and PD-L1 and a pharmaceutically effective amount of an FGFR inhibitor, wherein the antibody that blocks the interaction between PD-1 and PD-L1 and the FGFR inhibitor are administered if one or more FGFR variants are present in a biological sample from the patient.2. The method of claim 1 , further comprising evaluating the presence of one or more FGFR variants in the biological sample before the administering step.3. The method of claim 1 , further comprising evaluating PD-L1 expression in a biological sample.4. The method of claim 3 , wherein the biological sample for the one or more FGFR variants and the PD-L1 is the same biological sample.5. The method of claim 3 , wherein the biological sample for the one or more FGFR variants is different from the biological sample for PD-L1 expression.6. The method of claim 1 , wherein the biological sample is blood claim 1 , lymph fluid claim 1 , bone marrow claim 1 , a solid tumor sample claim 1 , or any combination thereof.7. The method of claim 1 , wherein the administering step is performed if PD-L1 expression is low in the biological sample.8. The method of claim 1 , wherein the cancer is lung cancer claim 1 , bladder cancer claim 1 , gastric cancer claim 1 , breast cancer claim 1 , ovarian cancer claim 1 , head and neck cancer claim 1 , esophageal cancer claim 1 , glioblastoma claim 1 , or ...

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Номер записи: 87
26-04-2018 дата публикации

Battery-powered control device

Номер: US20180116039A1
Автор: Jaykrishna A. Shukla, Jeffrey S. Hayes, Matthew V. Harte, Robert C. Newman, Jr., Stephen M. Luwig, JR.
Принадлежит: Lutron Electronics Co Inc

Provided herein are examples of a remote control device that provides a retrofit solution for an existing switched control system. The remote control device may comprise a control circuit, a rotatable portion, a magnetic ring coupled to the rotatable portion, and first and second Hall-effect sensor circuits configured to generate respective first and second sensor control signals in response to magnetic fields generated by the magnetic elements. The control circuit may operate in a normal mode when the rotatable portion is being rotated, and in a reduced-power mode when the rotatable portion is not being rotated. The control circuit may disable the second Hall-effect sensor circuit in the reduced-power mode. The control circuit may detect movement of the rotatable portion in response to the first sensor control signal in the reduced-power mode and enable the second Hall-effect sensor circuit in response to detecting movement of the rotatable portion.

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Номер записи: 88
09-06-2022 дата публикации

CAPACITORS WITH BUILT-IN ELECTRIC FIELDS

Номер: US20220181433A1
Автор: Avci Uygar E., CHANG Sou-Chi, LIN Chia-Ching, Metz Matthew V., Oguz Kaan, Penumatcha Ashish Verma, Sen Gupta Arnab, TUNG I-Cheng, Young Ian A.
Принадлежит: Intel Corporation

Disclosed herein are capacitors including built-in electric fields, as well as related devices and assemblies. In some embodiments, a capacitor may include a top electrode region, a bottom electrode region, and a dielectric region between and in contact with the top electrode region and the bottom electrode region, wherein the dielectric region includes a perovskite material, and the top electrode region has a different material structure than the bottom electrode region. 1. An integrated circuit (IC) die , comprising: a top electrode region;', 'a bottom electrode region; and', 'a dielectric region between and in contact with the top electrode region and the bottom electrode region;', 'wherein the dielectric region includes a perovskite material, and the top electrode region has a different material structure than the bottom electrode region., 'a capacitor, including2. The IC die of claim 1 , wherein the top electrode region has a different material composition than the bottom electrode region.3. The IC die of claim 2 , wherein the top electrode region includes germanium claim 2 , lanthanum claim 2 , hafnium claim 2 , zirconium claim 2 , yttrium claim 2 , barium claim 2 , lead claim 2 , calcium claim 2 , magnesium claim 2 , beryllium claim 2 , or lithium.4. The IC die of claim 3 , wherein the top electrode region has a thickness between 0.1 nanometers and 5 nanometers.5. The IC die of claim 3 , wherein the top electrode region is a first top electrode region claim 3 , the capacitor further includes a second top electrode region claim 3 , the first top electrode region is between the second top electrode region and the dielectric region claim 3 , and the second top electrode region has a different material composition than the first top electrode region.6. The IC die of claim 5 , wherein the second top electrode region includes ruthenium claim 5 , iridium claim 5 , copper claim 5 , titanium and nitrogen claim 5 , titanium claim 5 , gold claim 5 , platinum claim 5 , ...

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Номер записи: 89
09-06-2022 дата публикации

FIELD EFFECT TRANSISTORS WITH GATE ELECTRODE SELF-ALIGNED TO SEMICONDUCTOR FIN

Номер: US20220181442A1
Автор: Dewey Gilbert, Ghani Tahir, Kavalieros Jack T., Ma Sean T., Metz Matthew V., Mohapatra Chandra S., Murthy Anand S., Rachmady Willy
Принадлежит: Intel Corporation

Monolithic FETs including a fin of a first semiconductor composition disposed on a sub-fin of a second composition. In some examples, an InGaAs fin is grown over GaAs sub-fin. The sub-fin may be epitaxially grown from a seeding surface disposed within a trench defined in an isolation dielectric. The sub-fin may be planarized with the isolation dielectric. The fin may then be epitaxially grown from the planarized surface of the sub-fin. A gate stack may be disposed over the fin with the gate stack contacting the planarized surface of the isolation dielectric so as to be self-aligned with the interface between the fin and sub-fin. Other embodiments may be described and/or claimed. 1. A method of forming a field effect transistor (FET) structure , the method comprising:forming an isolation dielectric;forming a sub-fin comprising a first semiconductor material adjacent to sidewall of the isolation dielectric;epitaxially growing a fin from the sub-fin, the fin comprising a second semiconductor material laterally overhanging the isolation dielectric;forming a mask over a channel region of the fin; andforming source and drain semiconductor material on a surface of the fin not covered by the mask.2. The method of claim 1 , further comprising planarizing the sub-fin with the isolation dielectric.3. The method of claim 2 , wherein epitaxially growing the fin comprises growing the second semiconductor upon a surface of the fin that has been planarized with the isolation dielectric.4. The method of claim 1 , wherein:forming the mask further comprises forming a gate insulator over the channel region and a gate electrode over the gate insulator; and forming a trench in the isolation dielectric, the trench exposing a surface of a crystalline substrate; and', 'epitaxially growing the first semiconductor material within the trench., 'forming the sub-fin further comprises5. The method of claim 4 , wherein the first semiconductor material is a first III-V semiconductor material.6. The ...

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Номер записи: 90
24-07-2014 дата публикации

METHODS OF FORMING HETERO-LAYERS WITH REDUCED SURFACE ROUGHNESS AND BULK DEFECT DENSITY ON NON-NATIVE SURFACES AND THE STRUCTURES FORMED THEREBY

Номер: US20140203326A1
Автор: Chu-Kung Benjamin, GOEL Niti, Le Van H., Lemay Mark R., Metz Matthew V., Mukherjee Niloy, POWERS James M., Radosavljevic Marko
Принадлежит:

Methods of forming hetero-layers with reduced surface roughness and bulk defect density on non-native surfaces and the devices formed thereby are described. In one embodiment, the method includes providing a substrate having a top surface with a lattice constant and depositing a first layer on the top surface of the substrate. The first layer has a top surface with a lattice constant that is different from the first lattice constant of the top surface of the substrate. The first layer is annealed and polished to form a polished surface. A second layer is then deposited above the polished surface. 1. A method of forming a structure comprising:providing a substrate having a top surface with a first lattice constant;depositing a first layer on the top surface of the substrate, wherein the first layer has a top surface with a second lattice constant that is different from the first lattice constant;annealing the first layer;polishing the first layer to form a first polished surface with a third lattice constant; anddepositing a second layer above said first polished surface, wherein the second layer has a top surface with a fourth lattice constant.2. The method of claim 1 , wherein the first layer is annealed at a sufficiently high temperature and for a sufficiently long time to achieve a bulk defect density of <1E7 defects/cm2 in the first layer and/or a root-mean-square surface roughness on the top surface of first layer that is greater than 20 nm and wherein the first polished surface has a root-mean-square surface roughness of less than 1 nm and a peak-to-valley surface roughness range of less than 10 nm.3. The method of claim 1 , wherein the first lattice constant has a lattice constant mismatch with the second lattice constant of at least about 1%.4. The method of claim 1 , further comprising removing an oxide layer from the first polished surface prior to depositing the second layer.5. The method of claim 1 , further comprising depositing an initial layer on the ...

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Номер записи: 91
25-04-2019 дата публикации

INTERIOR REARVIEW MIRROR ASSEMBLY

Номер: US20190118713A1
Автор: Steffes Matthew V.
Принадлежит:

An interior rearview mirror assembly for a vehicle includes a mirror reflective element, a mirror support element having at least one attachment surface at which the mirror reflective element is adhesively attached, and a mounting assembly having a mirror mount and a mounting arm that is pivotally attached at the mirror support element. The mirror mount includes a plastic structure with a metallic clip attached thereat. The metallic clip is configured to slide onto a mirror mounting button adhesively attached at a vehicle windshield. The metallic clip includes a stop tab at one end to limit sliding movement of the metallic clip onto the mirror mounting button and anti-backout tabs at another end to limit movement of the metallic clip at the mirror mounting button in the opposite direction, so as to retain the metallic clip and the mirror mount at the mirror mounting button without use of a fastener. 1. An interior rearview mirror assembly for a vehicle , said interior rearview mirror assembly comprising:a mirror reflective element;a mirror support element comprising at least one attachment surface at which said mirror reflective element is adhesively attached;a mounting assembly comprising a mirror mount and a mounting arm, wherein said mounting arm is pivotally attached at said mirror support element;wherein said mirror mount comprises a plastic structure with a metallic clip attached thereat, and wherein said metallic clip is configured to slide onto a mirror mounting button with the mirror mounting button adhesively attached at a vehicle windshield;wherein said metallic clip comprises a stop tab at a first end and anti-backout tabs at a second end opposite the first end;wherein said stop tabs limit sliding movement of said metallic clip onto the mirror mounting button when said metallic clip slides onto the mirror mounting button in a first direction; andwherein said anti-backout tabs, with said metallic slip slid onto the mirror mounting button to where the stop ...

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Номер записи: 92
04-05-2017 дата публикации

GE AND III-V CHANNEL SEMICONDUCTOR DEVICES HAVING MAXIMIZED COMPLIANCE AND FREE SURFACE RELAXATION

Номер: US20170125524A1
Автор: Cea Stephen M., Chau Robert S., Chu-Kung Benjamin, DASGUPTA Sansaptak, Dewey Gilbert, GOEL Niti, Kavalieros Jack T., Kennel Harold W., Le Van H., Metz Matthew V., Mukherjee Niloy, Pillarisetty Ravi, Rachmady Willy, Radosavljevic Marko
Принадлежит:

Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin. 1. A semiconductor device , comprising:a semiconductor fin disposed above a semiconductor substrate, the semiconductor fin having a central recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin;a cladding layer region disposed on the central recessed segment of the semiconductor fin;a gate stack disposed on the cladding layer region; andsource/drain regions disposed in the pair of protruding outer segments of the semiconductor fin.2. The semiconductor device of claim 1 , further comprising:a second cladding layer region disposed on one of the pair of protruding outer segments; anda third cladding layer region disposed on the other of the pair of protruding outer segments, wherein the second and third cladding regions are discrete from, but contiguous with, the cladding layer region disposed on the central recessed segment of the semiconductor fin.3. The semiconductor device of claim 1 , wherein the semiconductor fin and the cladding layer region together provide a compliant substrate.4. The semiconductor device of claim 1 , wherein the central recessed segment is spaced apart from the pair of protruding outer segments by an isolation layer.5. The semiconductor device of claim 1 , wherein the ...

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Номер записи: 93
25-04-2019 дата публикации

WIDE BANDGAP GROUP IV SUBFIN TO REDUCE LEAKAGE

Номер: US20190122972A1
Автор: Agrawal Ashish, Chu-Kung Benjamin, Kavalieros Jack T., Le Van H., Metz Matthew V., Rachmady Willy, SUNG Seung Hoon
Принадлежит:

A subfin layer is deposited on a substrate. A fin layer is deposited on the subfin layer. The subfin layer has a conduction band energy offset relative to the fin layer to prevent a leakage in the subfin layer. In one embodiment, the subfin layer comprises a group IV semiconductor material layer that has a bandgap greater than a bandgap of the fin layer. 1. An apparatus comprisinga subfin layer on a substrate;a fin layer on the subfin layer, the subfin layer having a conduction band energy offset relative to the fin layer to prevent a leakage in the subfin layer.2. The apparatus of claim 1 , wherein the conduction band energy offset is at least 0.2 eV.3. The apparatus of claim 1 , wherein the subfin layer has a bandgap greater than that of the fin layer.4. The apparatus of claim 1 , wherein the subfin layer comprises a group IV material semiconductor.5. The apparatus of claim 1 , wherein the subfin layer comprises carbon.6. The apparatus of claim 1 , further comprisinga gate dielectric layer on the fin layer;a gate electrode layer on the gate dielectric layer; andsource/drain regions on portions of the fin layer.7. The apparatus of claim 1 , further comprisinga buffer layer between the substrate and the subfin layer.8. An electronic device to prevent a leakage comprising:a subfin layer on a substrate;a fin layer on the subfin layer, the subfin layer comprising a first group IV semiconductor material layer that has a bandgap greater than a bandgap of the fin layer to prevent the subfin layer leakage.9. The electronic device of claim 8 , wherein the subfin layer has a conduction band energy offset of to the fin layer of at least 0.2 eV.10. The electronic device of claim 8 , wherein the first group IV semiconductor material layer comprises carbon.11. The electronic device of claim 8 , wherein the fin layer comprises a second group IV semiconductor material layer.12. The electronic device of claim 8 , further comprisinga gate dielectric layer on the fin layer;a gate ...

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Номер записи: 94
31-07-2014 дата публикации

CONTACT TECHNIQUES AND CONFIGURATIONS FOR REDUCING PARASITIC RESISTANCE IN NANOWIRE TRANSISTORS

Номер: US20140209865A1
Автор: Chu-Kung Benjamin, Dewey Gilbert, Le Van H., Metz Matthew V., Mukherjee Niloy, Pillarisetty Ravi, Rachmady Willy, Radosavljevic Marko, Then Han Wui
Принадлежит:

Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nanowire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor. 1. An apparatus comprising:a semiconductor substrate;an isolation layer formed on the semiconductor substrate;a channel layer including nanowire material formed on the isolation layer to provide a channel for a transistor; anda contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor.2. The apparatus of claim 1 , wherein the at least one planar dimension is substantially perpendicular to a planar surface of the semiconductor substrate upon which the transistor is formed.3. The apparatus of claim 1 , further comprising:an epitaxial film disposed on and epitaxially coupled with the channel layer, the epitaxial film being configured to surround, in the at least one planar dimension, the nanowire material of the channel layer and being disposed between the nanowire material of the channel layer and material of the contact.4. The apparatus of claim 3 , wherein:the nanowire material of the channel layer includes N-type or P-type semiconductor material; andthe epitaxial film includes a group III-V semiconductor material and has a thickness from 50 Angstroms to 1000 Angstroms.5. The apparatus of claim 4 , wherein:the channel layer is epitaxially coupled with the isolation layer;the nanowire material of the ...

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Номер записи: 95
16-04-2020 дата публикации

Load Control Device for High-Efficiency Loads

Номер: US20200119656A1
Автор: Carmen Daniel F., Harte Matthew V., Jr. Robert C., Newman, Salvestrini Christopher J.
Принадлежит: Lutron Technology Company LLC

A load control device for controlling the power delivered from an AC power source to an electrical load includes a thyristor, a gate coupling circuit for conducting a gate current through a gate of the thyristor, and a control circuit for controlling the gate coupling circuit to conduct the gate current through a first current path to render the thyristor conductive at a firing time during a half cycle. The gate coupling circuit is able to conduct the gate current through the first current path again after the firing time, but the gate current is not able to be conducted through the gate from a transition time before the end of the half-cycle until approximately the end of the half-cycle. The load current is able to be conducted through a second current path to the electrical load after the transition time until approximately the end of the half-cycle. 1. A dimmer switch for controlling an amount of power delivered from an AC power source to a lighting load for controlling an intensity of the lighting load , the dimmer switch comprising:a triac adapted to be electrically coupled between the AC power source and the lighting load, the triac having first and second main terminals through which current can be conducted to energize the lighting load and a gate terminal through which current can be conducted to render the triac conductive;a gate coupling circuit electrically coupled between the first main terminal and the gate terminal of the triac to conduct current through the gate terminal of the triac;a controllable switching circuit electrically coupled in parallel with the first and second main terminals of the triac; anda control circuit configured to render the gate coupling circuit conductive to conduct a pulse of current through the gate terminal of the triac to render the triac conductive at a firing time during a present half-cycle of an AC mains voltage of the AC power source, the control circuit is configured to control the firing time to adjust the ...

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Номер записи: 96
11-05-2017 дата публикации

Fiber reinforced helmet

Номер: US20170128817A1
Автор: Biju Mathew, Douglas W. Heimer, Matthew V. Vacek, Scott J. Sorensen
Принадлежит: Rawlings Sporting Goods Co Inc

A helmet with an outer shell made from a fiber reinforced material, and preferably, a fiber reinforced polymer. The helmet preferably has a critical impact area that contains a greater concentration of fibers. Preferably, the helmet has a weight, offset, and dimensions which are comparable to a helmet with an outer shell that is not made from a fiber reinforced material. The helmet is preferably stiffer and more protective than a conventional helmet not having a fiber reinforced outer shell.

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Номер записи: 97
10-05-2018 дата публикации

WELL-BASED INTEGRATION OF HETEROEPITAXIAL N-TYPE TRANSISTORS WITH P-TYPE TRANSISTORS

Номер: US20180130801A1
Автор: Dewey Gilbert, Ghani Tahir, Kavalieros Jack T., Metz Matthew V., Mohapatra Chandra S., Murthy Anand S., Rachmady Willy, Rahhal-Orabi Nadia M.
Принадлежит:

Non-silicon fin structures extend from a crystalline heteroepitaxial well material in a well recess of a substrate. III-V finFETs may be formed on the fin structures within the well recess while group IV finFETs are formed in a region of the substrate adjacent to the well recess. The well material may be electrically isolated from the substrate by an amorphous isolation material surrounding pillars passing through the isolation material that couple the well material to a seeding surface of the substrate and trap crystal growth defects. The pillars may be expanded over the well-isolation material by lateral epitaxial overgrowth, and the well recess filled with a single crystal of high quality. Well material may be planarized with adjacent substrate regions. N-type fin structures may be fabricated from the well material in succession with p-type fin structures fabricated from the substrate, or second epitaxial well. 120-. (canceled)21. Integrated circuit (IC) structures , comprising:a well recess in a first region of a substrate, the well recess containing an amorphous well-isolation material over a bottom of the well recess, and a crystalline well material over the well-isolation material, wherein the well material is coupled to a seeding surface of the substrate at the bottom of the well recess by a crystalline pillar material that extends through the well-isolation material;an amorphous fin-isolation material over the well recess and over a second region of the substrate adjacent to the first region;a first fin comprising a first crystalline material, wherein the first fin extends from the well material and protrudes through the fin-isolation material; anda second fin a second crystalline material, wherein the second fin extends from the second region of the substrate and protruding through the fin-isolation material.22. The IC structures of claim 21 , wherein a minimum lateral dimension of the well recess is at least an order of magnitude larger than a longest ...

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Номер записи: 98
10-05-2018 дата публикации

Load Control Device for High-Efficiency Loads

Номер: US20180131288A1
Автор: Harte Matthew V., Jr. Robert C., Newman, Salvestrini Chris J.
Принадлежит: LUTRON ELECTRONICS CO., INC.

A two-wire load control device (such as, a dimmer switch) for controlling the amount of power delivered from an AC power source to an electrical load (such as, a high-efficiency lighting load) includes a thyristor coupled between the source and the load, a gate coupling circuit coupled between a first main load terminal and the gate of the thyristor, and a control circuit coupled to a control input of the gate coupling circuit. The control circuit generates a drive voltage for causing the gate coupling circuit to conduct a gate current to thus render the thyristor conductive at a firing time during a half cycle of the AC power source, and to allow the gate coupling circuit to conduct the gate current at any time from the firing time through approximately the remainder of the half cycle, where the gate coupling circuit conducts approximately no net average current to render and maintain the thyristor conductive. 1. A load control device for controlling power delivered from an AC power source to an electrical load , the load control device comprising:a thyristor adapted to be electrically coupled between the AC power source and the electrical load, the thyristor having a first main terminal and a second main terminal through which current is conducted to energize the electrical load and a gate terminal through which current is conducted to render the thyristor conductive;a gate coupling circuit electrically coupled to conduct current through the gate terminal of the thyristor;a control circuit configured to control the gate coupling circuit to conduct a pulse of current through the gate terminal of the thyristor at a firing time during a present half-cycle of the AC power source to render the thyristor conductive; anda power supply electrically coupled to conduct current through the electrical load to generate a supply voltage;wherein the control circuit is further configured to control the gate coupling circuit to allow the gate coupling circuit to conduct at least ...

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Номер записи: 99
03-06-2021 дата публикации

MULTILAYER HIGH-K GATE DIELECTRIC FOR A HIGH PERFORMANCE LOGIC TRANSISTOR

Номер: US20210167182A1
Автор: Avci Uygar E., CHANG Sou-Chi, HARATIPOUR Nazila, Kavalieros Jack T., LIN Chia-Ching, LOH Owen, MATTSON Eric Charles, MERRILL Devin, Metz Matthew V., Penumatcha Ashish Verma, SHIVARAMAN Shriram, SUNG Seung Hoon, TUNG I-Cheng, Young Ian A.
Принадлежит:

A integrated circuit structure comprises a fin extending from a substrate. The fin comprises source and drain regions and a channel region between the source and drain regions. A multilayer high-k gate dielectric stack comprises at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant and combinations thereof. A gate electrode ix over and on a topmost high-k material in the multilayer high-k gate dielectric stack. A selector element is above the metal layer. 1. An integrated circuit structure , comprising:a fin extending from a substrate, the fin comprising source and drain regions, and a channel region between the source and drain regions;a multilayer high-k gate dielectric stack comprising at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant; anda gate electrode over and on a topmost high-k material in the multilayer high-k gate ...

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Номер записи: 100
28-05-2015 дата публикации

LOAD CONTROL DEVICE FOR HIGH-EFFICIENCY LOADS

Номер: US20150146465A1
Автор: Harte Matthew V., Jr. Robert C., Newman, Salvestrini Christopher J.
Принадлежит:

A two-wire load control device (such as, a dimmer switch) for controlling the amount of power delivered from an AC power source to an electrical load (such as, a high-efficiency lighting load) includes a thyristor coupled between the source and the load, a gate coupling circuit coupled between a first main load terminal and the gate of the thyristor, and a control circuit coupled to a control input of the gate coupling circuit. The control circuit generates a drive voltage for causing the gate coupling circuit to conduct a gate current to thus render the thyristor conductive at a firing time during a half cycle of the AC power source, and to allow the gate coupling circuit to conduct the gate current at any time from the firing time through approximately the remainder of the half cycle, where the gate coupling circuit conducts approximately no net average current to render and maintain the thyristor conductive. 1. A load control device for controlling power delivered from an AC power source to an electrical load , the load control device comprising:a thyristor adapted to be electrically coupled between the AC power source and the electrical load, the thyristor having first and second main terminals through which current can be conducted to energize the electrical load and a gate terminal through which current can be conducted to render the thyristor conductive between the first and second main terminals;a first circuit electrically coupled between the first main terminal of the thyristor and the gate terminal of the thyristor to conduct current through the gate terminal of the thyristor;a second circuit electrically coupled between the first and second main terminals of the thyristor to conduct current through the electrical load when the thyristor is non-conductive; anda control circuit configured to individually control the first and second circuits to be conductive and non-conductive, the control circuit configured to render the first circuit conductive to ...

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Номер записи: 101