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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Форма поиска

Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 592. Отображено 100.
12-01-2012 дата публикации

Touch-sensitive display apparatus

Номер: US20120007810A1
Автор: Chi-Ming Tseng
Принадлежит: Individual

A touch-sensitive display apparatus includes a shell having two protruding platforms at two opposite ends thereof and a receiving cavity located between the two protruding platforms, a display module accommodated in the receiving cavity, a touch device placed on the display module. The touch device includes two opposite end plates placed on the respective protruding platforms, a touch panel and a top film. At least one end plate defines a hole for positioning the protrusion protruded from the corresponding protruding platform. At least one of two opposite ends of the touch panel extends beyond the display module and is located on an inner side of the corresponding protruding platform to be located at the same plane with the corresponding end plate and adjacent to the corresponding end plate to form a gap therebetween. The top film is attached on the conducting layer and end plates.

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Номер записи: 1
26-01-2012 дата публикации

Platinum (ii) tetradentate oncn complexes for organic light-emitting diode applications

Номер: US20120018711A1
Автор: Chi Chung Kwok, Chi Fai Kui, Chi Ming Che
Принадлежит: University of Hong Kong HKU

Described are novel platinum (II) containing organometallic materials. These materials show green to orange emissions with high emission quantum efficiencies. Using the materials as emitting materials; pure green emitting organic light-emitting diodes can be fabricated. Since the novel platinum (II) containing organometallic materials are soluble in common solvents, solution process methods such as spin coating and printing can be used for device fabrication.

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Номер записи: 2
19-04-2012 дата публикации

BOOTSTRAP CIRCUIT WITHOUT A REGULATOR OR A DIODE

Номер: US20120091976A1
Автор: Chen Chi-Ming, HSIEH Chung-Ming
Принадлежит:

A bootstrap circuit without a regulator and a diode includes a comparator, a first switch, and a capacitor. The comparator has a first terminal for receiving a reference voltage, a second terminal coupled to a bootstrap voltage output terminal of the bootstrap circuit, and a third terminal for outputting a switch control signal. The first switch has a first terminal for receiving an input voltage, a second terminal for receiving the switch control signal, and a third terminal coupled to the bootstrap voltage output terminal. The capacitor is coupled between a voltage switching terminal and the second terminal of the comparator. 1. A bootstrap circuit without a regulator or a diode , the bootstrap circuit comprising:a comparator having a first terminal for receiving a reference voltage, a second terminal coupled to a bootstrap voltage output terminal of the bootstrap circuit, and a third terminal for outputting a switch control signal;a first switch having a first terminal for receiving an input voltage, a second terminal for receiving the switch control signal, and a third terminal coupled to the bootstrap voltage output terminal; anda capacitor coupled between a voltage switching terminal and the second terminal and the comparator.2. The bootstrap circuit of claim 1 , further comprising:a first voltage dividing resistor coupled between the bootstrap voltage output terminal and the second terminal of the comparator; anda second voltage dividing resistor coupled between the second terminal of the comparator and a ground.3. The bootstrap circuit of claim 2 , further comprising:a second switch coupled between the bootstrap voltage output terminal and the first voltage dividing resistor, wherein a second terminal of the second switch is coupled to the third terminal of the comparator to receive the switch control signal.4. The bootstrap circuit of claim 1 , wherein the first switch is a P-type metal-oxide-semiconductor.5. The bootstrap circuit of claim 1 , wherein the ...

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Номер записи: 3
31-05-2012 дата публикации

REDUCING WAFER DISTORTION THROUGH A HIGH CTE LAYER

Номер: US20120132921A1
Автор: Chen Chi-Ming, Hwang Ho-Yung David, Tsai Chia-Shiung, Yu Chung-Yi
Принадлежит: TAWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon () surface. The method includes forming a high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate. The high CTE layer has a CTE greater than the CTE of silicon. The method includes forming a buffer layer over the second side of the silicon substrate. The buffer layer has a CTE greater than the CTE of silicon. The method includes forming a III-V family layer over the buffer layer. The III-V family layer has a CTE greater than the CTE of the buffer layer. 1. A method , comprising:providing a wafer having opposite first and second sides;forming a layer over the first side of the wafer, the layer having a coefficient-of-thermal-expansion (CTE) that is higher than that of the wafer; andforming a III-V family layer over the second side of the wafer, the III-V family layer having a CTE that is higher than that of the wafer.2111. The method of claim 1 , wherein the wafer includes a silicon () surface.3. The method of claim 1 , wherein the forming the layer having the CTE higher than that of the wafer is carried out in a manner so that the layer has a thickness that is less than about 2 microns.4. The method of claim 1 , wherein the forming the III-V family layer is carried out using an epitaxial process claim 1 , the epitaxial process having a process temperature range from about 800 degrees Celsius to about 1400 degrees Celsius; and further including:after the forming the III-V family layer, cooling the III-V family layer and the wafer to a temperature range from about 20 degrees Celsius to about 30 degrees Celsius.5. The method of claim 1 , wherein the forming the III-V family layer is carried out in a manner so that the III-V family layer includes a gallium nitride material.6. The method of claim 1 , wherein the forming the ...

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Номер записи: 4
05-07-2012 дата публикации

SILICON WAFER STRENGTH ENHANCEMENT

Номер: US20120168911A1
Автор: Chen Chi-Ming, Hwang Ho-Yung David, Kalnitsky Alexander, Tsai Chia-Shiung, Yu Chung-Yi
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

Provided is a method of fabricating a semiconductor device. The method includes: receiving a silicon wafer that contains oxygen; forming a zone in the silicon wafer, the zone being substantially depleted of oxygen; causing a nucleation process to take place in the silicon wafer to form oxygen nuclei in a region of the silicon wafer outside the zone; and growing the oxygen nuclei into defects. Also provided is an apparatus that includes a silicon wafer. The silicon wafer includes: a first portion that is substantially free of oxygen, the first portion being disposed near a surface of the silicon wafer; and a second portion that contains oxygen; wherein the second portion is at least partially surrounded by the first portion. 1. A method , comprising:receiving a silicon wafer that contains oxygen;forming a zone in the silicon wafer, the zone being substantially depleted of oxygen;causing a nucleation process to take place in the silicon wafer to form oxygen nuclei in a region of the silicon wafer outside the zone; andgrowing the oxygen nuclei into defects.2. The method of claim 1 , wherein:the forming the zone includes subjecting the silicon wafer to a first temperature, the first temperature being high enough to cause oxygen out-diffusion;the causing the nucleation process includes subjecting the silicon wafer to a second temperature that is less than the first temperature; andthe growing the oxygen nuclei includes subjecting the silicon wafer to a third temperature that is greater than the second temperature but less than the first temperature.3. The method of claim 2 , wherein:the first temperature is greater than about 1100 degrees Celsius;the second temperature is in a range from about 750 degrees Celsius to about 850 degrees Celsius; andthe third temperature is in a range from about 950 degrees Celsius to about 1050 degrees Celsius.4. The method of claim 2 , wherein:the forming the zone includes subjecting the silicon wafer to the first temperature for more than ...

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Номер записи: 5
02-08-2012 дата публикации

DRIVING CIRCUIT CAPABLE OF ENHANCING ENERGY CONVERSION EFFICIENCY AND DRIVING METHOD THEREOF

Номер: US20120194073A1
Автор: Chen Chi-Ming, Wang Jing-Chyi
Принадлежит:

A driving circuit includes a switch, a detecting unit, a current supply unit, and an energy storage unit. The current supply unit is used for providing a driving current for at least one series of light emitting diodes. The detecting unit is used for comparing a voltage of a first terminal of the detecting unit with a reference voltage to generate a switch control signal. When the switch is turned on according the switch control signal, a first voltage drives the series of light emitting diodes through the switch and the energy storage unit is charged according a charge current. When the switch is turned off according the switch control signal, the energy storage unit drives the series of light emitting diodes according to a discharge current. 1. A driving circuit capable of enhancing energy conversion efficiency , the driving circuit comprising:a switch having a first terminal for receiving a first voltage, a second terminal, and a third terminal for being coupled to a first terminal of at least one series of light emitting diodes;a detecting unit having a first terminal for being coupled to a second terminal of the at least one series of light emitting diodes, a second terminal coupled to the second terminal of the switch for outputting a switch control signal, and a third terminal coupled to ground, wherein the detecting unit is used for generating the switch control signal according to a voltage of the second terminal of the at least one series of light emitting diodes;a current supply unit having a first terminal for being coupled to the second terminal of the at least one series of light emitting diodes, and a second terminal coupled to the ground, wherein the current supply unit is used for providing a driving current to the at least one series of light emitting diodes; andan energy storage unit having a first terminal for being coupled to the first terminal of the at least one series of light emitting diodes, and a second terminal coupled to the ground, ...

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Номер записи: 6
23-08-2012 дата публикации

STRUCTURE AND METHOD TO REDUCE WAFER WARP FOR GALLIUM NITRIDE ON SILICON WAFER

Номер: US20120211759A1
Автор: Chen Chi-Ming, Liu Ming Chyi, Liu Shih-Chang, Pei Hsieh Ching, Tsai Chia-Shiung, Yu Chung-Yi, Yu Jiun-Lei
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

The present disclosure provides a semiconductor structure. The semiconductor structure includes a dielectric material layer on a silicon substrate, the dielectric material layer being patterned to define a plurality of regions separated by the dielectric material layer; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer grown on the heterogeneous buffer layer only within the plurality of regions. 1. A semiconductor structure comprising:a dielectric material layer on a silicon substrate, the dielectric material layer being patterned to define a plurality of regions separated by the dielectric material layer;a first buffer layer disposed on the silicon substrate;a heterogeneous buffer layer disposed on the first buffer layer; anda gallium nitride layer selectively grown on the heterogeneous buffer layer only within the plurality of regions.2. The semiconductor structure of claim 1 , wherein the silicon substrate has a (111) oriented surface.3. The semiconductor structure of claim 1 , wherein the dielectric material layer includes a material selected from the group consisting of silicon oxide claim 1 , silicon nitride claim 1 , and silicon oxynitride.4. The semiconductor structure of claim 1 , whereinthe dielectric material layer includes a first set of features extended in a first direction and a second set of features extended in a second direction different from the first direction; andthe first set of features intersects the second set of features, defining the plurality of regions.5. The semiconductor structure of claim 4 , wherein the first set of features and second set of features include solid lines and dashed lines;each of the solid lines and the dashed lines has a width ranging between about 0.1 micron and about 5 mm; andthe solid lines and dashed lines in each of the first and second sets are spaced from each other with a spacing ranging between about 100 ...

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Номер записи: 7
23-08-2012 дата публикации

CABLE CONNECTOR ASSEMBLY ADAPTED FOR POWER AND SIGNAL TRANSMITTING

Номер: US20120214326A1
Автор: Chen Chi-Ming, Ko David, LI CHANG-MAO, Zong Jun
Принадлежит: HON HAI PRECISION INDUSTRY CO., LTD.

A cable connector assembly () includes a first connector () used for transmitting power, a second connector () for transmitting signal, a cover () holding the first connector and the second connector, a cable () connected with the first connector and the second connector and a ferrule () mounted to the cover. The first connector has a body portion (), the ferrule has a main portion () around the body portion of the first connector and a number of equally spaced spring tabs (), the spring tabs are extending along a transverse direction and elastically pressing onto the body portion of the first connector. 1. A cable connector assembly , comprising:a first connector used for transmitting power, the first connector having a body portion;a second connector for transmitting signal;a cover holding the first connector and the second connector;a cable connected with the first connector and the second connector; anda ferrule mounted to the cover and having a main portion around the body portion of the first connector and a plurality of equally spaced spring tabs, the spring tabs extending along a transverse direction and elastically pressing onto the body portion of the first connector.2. The cable connector assembly as claimed in claim 1 , wherein the ferrule has a plurality of retaining tabs formed at opposite ends of the main portion symmetrically claim 1 , and the retaining tabs on a same side are arranged along a front-to-back direction.3. The cable connector assembly as claimed in claim 2 , wherein the ferrule is hollow claim 2 , and the spring tabs extend into to press the first connector.4. The cable connector assembly as claimed in claim 3 , wherein the first connector has a rear flange claim 3 , and a rear end of the ferrule is adjacent to a front end of the flange.5. The cable connector assembly as claimed in claim 4 , wherein both the main portion and the body portion are substantially cylindrical claim 4 , and there is an annular gap between the main portion and ...

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Номер записи: 8
20-09-2012 дата публикации

Method and Apparatus for Forming a III-V Family Layer

Номер: US20120238076A1
Автор: Chen Chi-Ming, Hwang Ho-Yung David, Tsai Chia-Shiung, Yu Chung-Yi
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

Provided is an apparatus. The apparatus includes: a first deposition component that is operable to form a compound over a semiconductor wafer, the compound including at least one of: a III-family element and a V-family element; a second deposition component that is operable to form a passivation layer over the compound; and a transfer component that is operable to move the semiconductor wafer between the first and second deposition components, the transfer component enclosing a space that contains substantially no oxygen and substantially no silicon; wherein the loading component, the first and second deposition components, and the transfer component are all integrated into a single fabrication tool. 1. A method , comprising:forming a first layer over a wafer, the first layer containing a group III-V compound; andforming a second layer over the first layer, the second layer and the first layer containing different material compositions;wherein the forming the first layer and the forming the second layer are performed in a manner such that the wafer is prevented from being exposed to at least one of oxygen and silicon between the forming the first layer and the forming the second layer.2. The method of claim 1 , wherein:the forming the first layer is performed in a first deposition chamber of a cluster semiconductor fabrication tool;the forming the second layer is performed in a second deposition chamber of the cluster semiconductor fabrication tool; andthe first deposition chamber and the second deposition chamber are interconnected by a transfer chamber that is substantially free of oxygen and silicon.3. The method of claim 2 , wherein:the first deposition chamber includes a metal-organic chemical vapor deposition (MOCVD) chamber; andthe second deposition chamber includes a low-pressure chemical vapor deposition (LPCVD) chamber.4. The method of claim 1 , wherein the group III-V compound includes gallium nitride.5. The method of claim 1 , wherein the second layer ...

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Номер записи: 9
11-10-2012 дата публикации

Multi-mode display device and power-saving method of the same

Номер: US20120256892A1
Автор: Chi-Ming Hung, Chih-Ming Ma, Jun-Lin Huang, Pei-Cheng Huang
Принадлежит: QUANTA COMPUTER INC

A power-saving method adapted in a multi-mode display device is provided. The power-saving method comprises the steps as follows. A brightness of an ambient light is detected. When the brightness of the ambient light lies within a transmissive range, the multi-mode display device is operated in a transmissive mode and enables the backlight module of the multi-mode display. When the brightness of the ambient light lies within a transflective range, the multi-mode display device is operated in a transflective mode and the brightness of the backlight module is dynamically adjusted according to a compensation method. When the brightness of the ambient light lies within a reflective range, the multi-mode display device is operated in a reflective mode and turns off the backlight module.

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Номер записи: 10
11-10-2012 дата публикации

Cloud computing method capable of hiding real file paths

Номер: US20120259964A1
Автор: Chi-Hsiu Huang, Chi-Ming Luo, Chih-Chiang Lin, Cho-Hsuan Lee, Heng-Chang Lin, Hsiao-Yun Chen, Hung-Chun Kao, Jia-Bin Lai, Kuan-Yi Chang, Min-Hui Wu, Shih-Hui Wu, Ting-Yu Chiang, Wen-Yuan Wang, Yi-Hua Liang, Yu-Hsiang Wang, Yu-Sheng Lin
Принадлежит: D Link Corp

The present invention is to provide a cloud computing method capable of hiding real file paths, which includes the steps of: triggering a web browsing button of an application program and sending a browsing activation signal to a management server by a terminal device; reading a directory list of at least one file from a file server and sending a file browsing program and the directory list to the terminal device by the management server; displaying the directory list via the file browsing program and sending a file processing signal to the management server by the terminal device; downloading from the file server a file specified by the file processing signal and sending the specified file to the terminal device by the management server; and sending the specified file to a third-party application server via the application program and terminating the file browsing program by the terminal device.

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Номер записи: 11
15-11-2012 дата публикации

POSITIVE PHOTOSENSITIVE RESIN COMPOSITION AND METHOD FOR FORMING PATTERNS BY USING THE SAME

Номер: US20120287393A1
Автор: Liu Chi-ming, Shih Chun-An
Принадлежит: CHI MEI COOPERATION

A positive photosensitive resin composition and a method for forming patterns by using the same are disclosed. The photosensitive resin composition comprises a novolac resin (A), an ortho-naphthoquinone diazide sulfonic acid ester (B), a dye (C) and a solvent (D). The novolac resin (A) includes a high-ortho novolac resin (A-1) that has ortho-ortho methylene bonding to all methylene bonding in a ratio of 18% to 25%, thereby exhibiting excellent temporal stability and forming patterns with high resolution. 1. A positive photosensitive resin composition , comprising:a novolac resin (A);an ortho-naphthoquinone diazide sulfonic acid ester (B);a dye (C); anda solvent (D),wherein the novolac resin (A) includes a high-ortho novolac resin (A-1) that has ortho-ortho methylene bonding to all methylene bonding in a ratio of 18% to 25%.2. The positive photosensitive resin composition of claim 1 , wherein an amount of the high-ortho novolac resin (A-1) is 30 to 100 parts by weight based on 100 parts by weight of the novolac resin (A).3. The positive photosensitive resin composition of claim 1 , wherein an amount of the high-ortho novolac resin (A-1) is 40 to 100 parts by weight based on 100 parts by weight of the novolac resin (A).4. The positive photosensitive resin composition of claim 1 , wherein an amount of the high-ortho novolac resin (A-1) is 50 to 100 parts by weight based on 100 parts by weight of the novolac resin (A).5. The positive photosensitive resin composition of claim 1 , wherein an amount of the dye (C) is 0.1 to 5 parts by weight based on 100 parts by weight of the novolac resin (A).6. The positive photosensitive resin composition of claim 1 , wherein the dye (C) is selected from the group consisting of an acid dye claim 1 , a basic dye claim 1 , a direct dye claim 1 , a sulphur dye claim 1 , a vat dye claim 1 , a naphthol dye claim 1 , a reactive dye claim 1 , a disperse dye and an oil-soluble dye.7. A method for forming patterns by subjecting a positive ...

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Номер записи: 12
06-12-2012 дата публикации

SUPPRESSION OF CANCER METASTASIS

Номер: US20120309682A1
Автор: Chiu Ching-Feng, Hung Shao-Wen, Liang Chi-Ming, Liang Shu-Mei, Peng Jei-Ming
Принадлежит:

Methods are provided for suppressing cancer metastasis. Cancer metastasis is the most common cause of treatment failure and death in cancer patients. Tumor cell invasion and/or migration can be significantly inhibited after fibrillar proteins (rVP1, F-HSA, and F-BSA) treatment in vitro. In addition, rVP1 can significantly suppress murine and human breast cancer metastasis and human prostate and ovarian cancer metastasis in vivo while F-HSA can significantly suppress murine breast cancer metastasis. Compositions of fibrillar proteins as anti-cancer metastasis therapeutics and methods of use thereof are provided herein. 141-. (canceled)42. A pharmaceutical composition for suppressing cancer metastasis in a subject comprising a fibrillar protein and a pharmaceutically acceptable excipient.43. The composition of claim 42 , wherein said fibrillar protein comprises fibrillar albumin.44. The composition of claim 42 , wherein said fibrillar protein comprises fibrillar human serum albumin.45. The composition of claim 42 , wherein said fibrillar protein comprises capsid proteins of the foot-and-mouth-disease virus.46. A pharmaceutical composition comprising a therapeutically effective amount of fibrillar human serum albumin and a pharmaceutically acceptable carrier for use in treating a mammal having cancer.47. The pharmaceutical composition of claim 46 , wherein said cancer is characterized by overexpression of α5β1 and/or αvβ3 integrin.48. A method of manufacturing the composition according to claim 44 , comprising the following steps:manufacturing fibrillar human serum albumin; andmixing the fibrillar human serum albumin in a therapeutically effective amount with a pharmaceutically acceptable carrier.49. The method of claim 48 , wherein the step of manufacturing the fibrillar human serum albumin comprises the following steps:dissolving human serum albumin in a detergent solution;applying the dissolved human serum albumin through a gel filtration column with a pore size to ...

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Номер записи: 13
06-12-2012 дата публикации

Phosphorescent material, their preparations and applications

Номер: US20120309979A1
Автор: Chi Ming Che, Kai Li
Принадлежит: University of Hong Kong HKU

The subject invention is directed to tetradentate bis-(NHC carbenes) alkylene ligand Pt(II) complexes, tetradentate bis-(NHC carbenes) alkylene ligands, and its ligand precursors, for preparation of the Pt(II) complexes. The Pt(II) complexes show a deep blue emission with an improved quantum efficiency and can be used for fabrication of OLEDs with an electroluminescence layer that comprise the bis-(NHC carbenes) alkylene ligand Pt(II) complexes.

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Номер записи: 14
13-12-2012 дата публикации

PROCESS TO PRODUCE FIBRILLAR PROTEINS AND METHOD OF TREATMENT USING FIBRILLAR PROTEINS

Номер: US20120316117A1
Автор: HUANG CHUN-YUNG, Liang Chi-Ming, Liang Shu-Mei
Принадлежит: Academia Sinica

A method for inhibiting survival of cancer cells in a subject is disclosed. The method comprises administering to a subject in need thereof a therapeutically effective amount of fibrillar albumin. The preparation of the fibrillar albumin comprises: (i) forming a solution comprising an isolated and/or purified globular albumin; (ii) adding a detergent to the solution containing the isolated and/or purified globular albumin, wherein the detergent is one selected from the group consisting of sodium dodecyl sulfate (SDS) and n-tetradecyl-N,N-dimethyl-3-ammonio-1-propanesulfonate; (iii) applying the solution to a molecular sizing column with a pore size that permits separation of a protein with a molecular weight of at least about 70 kDa so as to promote column-induced formation of the fibrillar albumin from the isolated and/or purified globular albumin; and (iv) eluting the fibrillar albumin from the column, wherein the eluted albumin has a fibrillar structure. 1. A method for inhibiting growth of cancer cells in a subject in need thereof , comprising:administering to the subject a therapeutically effective amount of fibrillar albumin.2. The method of claim 1 , wherein the cancer cells are selected from the group consisting of kidney cancer cells claim 1 , breast cancer cells claim 1 , lung cancer cells claim 1 , prostate cancer cells claim 1 , liver cancer cells claim 1 , and ovarian cancer cells.3. The method of claim 1 , wherein the fibrillar albumin causes an inhibition of the growth of the cancer cell in a dose-dependent manner.4. The method of claim 1 , further comprising causing the fibrillar albumin to bind to integrin α5β1 of the cancer cells.5. The method of claim 1 , wherein the fibrillar albumin inhibits the growth of the cancer cells via binding to integrin α5β1 of the cancer cells.6. The method of claim 1 , further con rising causing an increases in caspase-3 activity of the cancer cells.7. The method of claim 1 , thither comprising causing apoptosis of ...

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Номер записи: 15
28-03-2013 дата публикации

OPTICAL-ELECTRICAL CONNECTOR HAVING A MAGNETIC MEMBER

Номер: US20130077919A1
Автор: Chen Chi-Ming, HOU YUN-CHENG, ZHU YA-DONG, Zong Jun
Принадлежит: HON HAI PRECISION INDUSTRY CO., LTD.

An optical-electrical connector () includes a housing (), a circuit board () received in the housing and having a transducer for bidirectional optical-electrical signal conversion, a lens member () mounted on the circuit board, a ferrule () receiving a number of optical channels and having a resisting face (), and a magnetic member (). The ferrule is situated behind the lens member and aligned with the lens member along a front-to-back direction. The magnetic member has a metal sheet () and at least one magnetic component () secured in the housing. The metal sheet abuts against the resisting face of the ferrule under a magnetic force provided by the at least one magnetic component, to provide a forward resilient force to the ferrule for fixing the ferrule to the lens member. 1. An optical-electrical connector comprising:a housing;a circuit board received in the housing and having a transducer for bidirectional optical-electrical signal conversion;a lens member mounted on the circuit board;a ferrule receiving a plurality of optical channels and having a resisting face, one of the lens member and the ferrule having a guide pin, and another one of the lens member and the ferrule having a guide hole, said ferrule being situated behind the lens member within the housing and aligned with the lens member along a front-to-back direction via an engagement between the guide pin and the guide hole; anda magnetic member having a metal sheet and at least one magnetic component secured in the housing, said metal sheet abutting against the resisting face of the ferrule under a magnetic force provided by the at least one magnetic component, to provide a forward resilient force to the ferrule for fixing the ferrule to the lens member.2. The optical-electrical connector as claimed in claim 1 , further comprising a cover attached to an upper portion of the housing.3. The optical-electrical connector as claimed in claim 2 , wherein there are a pair of magnetic components claim 2 , said ...

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Номер записи: 16
25-04-2013 дата публикации

SUBSTRATE BREAKDOWN VOLTAGE IMPROVEMENT FOR GROUP III-NITRIDE ON A SILICON SUBSTRATE

Номер: US20130099243A1
Автор: Chang Chin-Cheng, Chen Chi-Ming, Hwang Ho-Yung David, LIN Hung-Ta, Liu Po-Chun, Tsai Chia-Shiung, Yu Chung-Yi
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A circuit structure includes a substrate, a nucleation layer of undoped aluminum nitride, a graded buffer layer comprising aluminum, gallium, nitrogen, one of silicon and oxygen, and a p-type conductivity dopant, a ungraded buffer layer comprising gallium, nitrogen, one of silicon and oxygen, and a p-type conductivity dopant without aluminum, and a bulk layer of undoped gallium nitride over the ungraded buffer layer. The various dopants in the graded buffer layer and the ungraded buffer layer increases resistivity and results in layers having an intrinsically balanced conductivity. 1. A circuit structure comprising:a silicon substrate;a nucleation layer of undoped aluminum nitride over the silicon substrate;a buffer layer comprising gallium, nitrogen, one of silicon and oxygen, and a p-type conductivity dopant over the nucleation layer; and,a bulk layer of undoped gallium nitride over the buffer layer.2. The circuit structure of claim 1 , wherein the buffer layer comprises a graded buffer layer and an ungraded buffer layer claim 1 , said graded buffer layer further comprising aluminum.3. The circuit structure of claim 1 , wherein the p-type conductivity dopant comprises at least one of carbon claim 1 , iron claim 1 , magnesium claim 1 , and zinc.4. The circuit structure of claim 3 , wherein the p-type conductivity dopant in the graded buffer layer is an impurity having a total concentration of between about 1 E/cmand 1 E/cm.5. The circuit structure of claim 3 , wherein the p-type conductivity dopant in the ungraded buffer layer and the graded buffer layer is different with respect to composition and/or concentration.6. The circuit structure of claim 1 , wherein the buffer layer is about 1 to about 3 microns thick.7. The circuit structure of claim 1 , wherein the ungraded buffer layer is about 0.5 to about 3 microns thick.8. The circuit structure of claim 1 , further comprising an active layer over the bulk layer claim 1 , the active layer including a layer of ...

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Номер записи: 17
25-04-2013 дата публикации

FinFET Device And Method Of Manufacturing Same

Номер: US20130099282A1
Автор: Chen Chi-Ming, Hwang Ho-Yung David, Yu Chung-Yi
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first dielectric layer disposed over the substrate. The semiconductor device further includes a buffer layer disposed over the substrate and between first and second walls of a trench of the dielectric layer. The semiconductor device further includes an insulator layer disposed over the buffer layer and between the first and second wall of the trench of the dielectric layer. The semiconductor device also includes a second dielectric layer disposed over the first dielectric layer and the insulator layer. Further, the semiconductor device includes a fin structure disposed over the insulator layer and between first and second walls of a trench of the second dielectric layer. 1. A semiconductor device comprising:a substratea first dielectric layer disposed over the substrate;a buffer layer disposed over the substrate and between first and second walls of a trench of the dielectric layer;an insulator layer disposed over the buffer layer and between the first and second wall of the trench of the dielectric layer;a second dielectric layer disposed over the first dielectric layer and the insulator layer; anda fin structure disposed over the insulator layer and between first and second walls of a trench of the second dielectric layer.2. The semiconductor device of further comprising:a gate structure disposed over the fin structure, the gate structure separating source and drain regions of the semiconductor device, the source and drain regions defining a channel region therebetween.3. The semiconductor device of wherein the buffer layer is a type III/V material having a crystal structure claim 1 , and wherein insulator layer is a type III/V material having a crystal structure.4. The semiconductor device of wherein the buffer layer includes a material selected from the group consisting of AlAs claim 1 , AlAs/Ge claim 1 , InP ...

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Номер записи: 18
25-04-2013 дата публикации

III-V Multi-Channel FinFETs

Номер: US20130099283A1
Автор: Chen Chi-Ming, LIN Hung-Ta, NIEH Chun-Feng, Yu Chung-Yi
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A device includes insulation regions over portions of a semiconductor substrate, and a III-V compound semiconductor region over top surfaces of the insulation regions, wherein the III-V compound semiconductor region overlaps a region between opposite sidewalls of the insulation regions. The III-V compound semiconductor region includes a first and a second III-V compound semiconductor layer formed of a first III-V compound semiconductor material having a first band gap, and a third III-V compound semiconductor layer formed of a second III-V compound semiconductor material between the first and the second III-V compound semiconductor layers. The second III-V compound semiconductor material has a second band gap lower than the first band gap. A gate dielectric is formed on a sidewall and a top surface of the III-V compound semiconductor region. A gate electrode is formed over the gate dielectric. 1. A device comprising:a semiconductor substrate;insulation regions over portions of the semiconductor substrate, wherein the insulation regions comprise sidewalls substantially facing each other; a first and a second III-V compound semiconductor layer formed of a first III-V compound semiconductor material having a first band gap; and', 'a third III-V compound semiconductor layer formed of a second III-V compound semiconductor material between the first and the second III-V compound semiconductor layers, wherein the second III-V compound semiconductor material has a second band gap lower than the first band gap;, 'a III-V compound semiconductor region over top surfaces of the insulation regions, wherein the III-V compound semiconductor region overlaps a region between the sidewalls of the insulation regions, and wherein the III-V compound semiconductor region comprisesa gate dielectric on a sidewall and a top surface of the III-V compound semiconductor region; anda gate electrode over the gate dielectric.2. The device of claim 1 , wherein the first III-V compound ...

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Номер записи: 19
09-05-2013 дата публикации

NEW III-NITRIDE GROWTH METHOD ON SILICON SUBSTRATE

Номер: US20130112939A1
Автор: Chang Chin-Cheng, Chen Chi-Ming, Hwang Ho-Yung David, LIN Hung-Ta, Liu Po-Chun, Tsai Chia-Shiung, Yu Chung-Yi
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A circuit structure includes a substrate and a patterned dielectric layer over the substrate. The patterned dielectric layer includes a plurality of vias; and a number of group-III group-V (III-V) compound semiconductor layer. The III-V compound semiconductor layers include a first layer in the vias, a second layer over the first layer and the dielectric layer, and a bulk layer over the second layer. 1. A circuit structure comprising:a silicon substrate;a patterned dielectric layer over and in direct contact with an top surface of the silicon substrate, the patterned dielectric layer comprising a plurality of vias through a dielectric layer, said plurality of vias arranged in a hexagonal pattern;a vertical growth layer disposed over the substrate and within the vias in the patterned dielectric layer;a lateral growth layer of group-III to group-V (III-V) compound semiconductor layer disposed over the vertical growth layer and the patterned dielectric layer, forming a continuous layer over the patterned dielectric layer and the vertical growth layer; and,a bulk layer of group III-V compound semiconductor layer over the lateral growth layer.2. The circuit structure of claim 1 , further comprising a graded group III-V superlattice layer.3. The circuit structure of claim 1 , wherein the patterned dielectric layer is a thermal silicon oxide layer.4. The circuit structure of claim 1 , wherein the vertical growth layer and the lateral growth layer consist essentially of a same material.5. The circuit structure of claim 1 , wherein the vias have an aspect ratio of about 2 to about 5.6. The circuit structure of claim 5 , wherein each via is separated from an adjacent via by about 2 microns to about 5 microns.7. The circuit structure of claim 5 , wherein each via is about 3000 angstroms to about 5000 angstroms deep.8. The circuit structure of claim 5 , wherein each via has a diameter of about 1000 angstroms to about 2000 angstroms.9. The circuit structure of claim 5 , wherein ...

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Номер записи: 20
16-05-2013 дата публикации

Anti-tumor Fibrillar Human Serum Albumin Methods and Compositions

Номер: US20130123183A1
Автор: Liang Chi-Ming, Liang Shu-Mei
Принадлежит: Academia Sinica

Fibrillar human serum albumin was shown to be effective in the treatment of various types of cancers. Methods and compositions are disclosed for using fibrillar human serum albumin as a medicament to treat subjects having cancer. 1. A composition comprising:fibrillar human serum albumin and a pharmaceutically acceptable carrier.2. The composition of claim 1 , wherein the fibrillar human serum albumin is produced by a method comprising:dissolving human serum albumin in an SDS solution or other suitable detergents;applying the dissolved human serum albumin through a gel filtration column with a pore size that can separate proteins of 70 kDa molecular weight and above; removing the human serum albumin from the column; anddialyzing the solution against phosphate buffered saline to remove the SDS.3. A method comprising:administering to a subject having cancer a therapeutically effective amount of fibrillar human serum albumin.4. The method of claim 3 , wherein said administering is selected from the group consisting of intravenous injection claim 3 , subcutaneous injection claim 3 , intraperitoneal injection claim 3 , intraarterial injection claim 3 , intramuscular injection claim 3 , intralesional injection into the tumor claim 3 , intralesional injection adjacent to the tumor claim 3 , intravenous infusion claim 3 , and intraarterial infusion.5. The method of claim 3 , wherein the cancer is breast cancer.6. The method of claim 3 , wherein the cancer is ovarian or cervical cancer.7. The method of claim 3 , wherein the cancer is prostate cancer.8. The method of claim 3 , wherein the cancer is lung cancer.9. A method comprising:manufacturing a composition useful in the treatment of cancer, the medication comprising fibrillar human serum albumin and a pharmaceutically acceptable carrier.109. The method claim 3 , wherein the fibrillar human serum albumin is manufactured by:dissolving human serum albumin in a detergent solution;applying the dissolved human serum albumin ...

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Номер записи: 21
23-05-2013 дата публикации

HARDNESS-ADJUSTABLE PLATFORM FOR SUPPORTING CONVEYOR BELT OF TREADMILL

Номер: US20130130868A1
Автор: CHEN Terry, CHIU Ren, Chung Fong-chiao, HOU Kuang-Hua, Liu Chi-ming, Yang Hung
Принадлежит:

A hardness adjustable platform for supporting a conveyor belt of a treadmill includes a platform body having internal spaces, and a plurality of elastic fillers moveably and respectively disposed in the internal spaces of the platform body for providing a cushion effect. The fillers are moveable relative to the platform body by an external force and divide the platform body into first and second regions having different hardness. As a result, the runner who uses the treadmill equipped with the aforesaid platform may adjust the positions of the fillers according to his/her physical condition and running speed to change the hardness distribution of the platform so as to enhance his/her running efficiency and reduce the risk of exercise injury. 1. A hardness-adjustable platform for supporting a conveyor belt of a treadmill , the hardness-adjustable platform comprising:a platform body having at least one internal space; andat least one filler moveably disposed in the at least one internal space of the platform body to define the platform body a first region without the at least one filler and a second region with the at least one filler, such that the first region has a hardness smaller than that of the second region.2. The hardness-adjustable platform as claimed in claim 1 , comprising a plurality of said fillers disposed side by side along a longitudinal direction of the platform body in the at least one internal space and moveable relative to the platform body along a transverse direction of the platform body.3. The hardness-adjustable platform as claimed in claim 1 , comprising a plurality of said fillers disposed side by side along a transverse direction of the platform body in the at least one internal space and moveable relative to the platform body along a longitudinal direction of the platform body.4. The hardness-adjustable platform as claimed in claim 1 , wherein the platform body comprises a wooden plate claim 1 , a reinforcement plate above the wooden plate ...

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Номер записи: 22
23-05-2013 дата публикации

PLATFORM FOR SUPPORTING CONVEYOR BELT OF TREADMILL

Номер: US20130130869A1
Автор: CHEN Terry, CHIU Ren, Chung Fong-chiao, HOU Kuang-Hua, Liu Chi-ming, Yang Hung
Принадлежит:

A platform for supporting a conveyor belt of a treadmill includes a wooden plate, a reinforcement plate above the wooden plate, and a shock-absorbing plate sandwiched between the wooden plate and the reinforcement plate. The shock-absorbing plate has a surface facing the wooden plate base, and a plurality of cushions protruding from the surface and stopping against the wooden plate for providing good elastic support force and cushion effect. 1. A platform for supporting a conveyor belt of a treadmill , the platform comprising:a wooden plate;a reinforcement plate above the wooden plate; anda shock-absorbing plate sandwiched between the wooden plate and the reinforcement plate and provided with a surface facing the wooden plate base, and a plurality of cushions protruding from the surface and stopping against the wooden plate.2. The platform as claimed in claim 1 , wherein the cushions each are an inverted truncated cone having a relatively wide top end connected with the surface of the shock-absorbing plate claim 1 , and a relatively narrow bottom end stopped at the wooden plate.3. The platform as claimed in claim 1 , wherein the cushions are spacedly arranged in a matrix in rows and columns.4. The platform as claimed in claim 3 , wherein an interval between each two of the rows of the matrix is equal to an interval between each two of the columns of the matrix.53. The platform as claimed in clam claim 3 , wherein each two of the rows of the matrix have an equal interval and the columns that are arranged at a front portion of the shock-absorbing plate have an interval smaller than that of the columns that are arranged at a rear portion of the shock-absorbing plate. 1. Field of the InventionThe present invention relates generally to parts of a treadmill, and more particularly, to a platform for supporting a conveyor belt of the treadmill.2. Description of the Related ArtA treadmill is an apparatus capable of simulating walking and/or running for cardiorespiratory ...

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Номер записи: 23
06-06-2013 дата публикации

GALLIUM NITRIDE GROWTH METHOD ON SILICON SUBSTRATE

Номер: US20130140525A1
Автор: Chen Chi-Ming, Hwang Ho-Yung David, LIN Hung-Ta, Liu Po-Chun, Tsai Chia-Shiung, Yu Chung-Yi
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A semiconductor structure includes a silicon substrate; more than one bulk layer of group-III/group-V (III-V) compound semiconductor atop the silicon substrate; and each bulk layer of the group III-V compound is separated by an interlayer. 1. A semiconductor structure comprising:a silicon substrate;a first bulk layer of group III-V compound semiconductor over the silicon substrate;an interlayer over the first bulk layer of group III-V compound semiconductor; anda second bulk layer of group III-V compound semiconductor over the interlayer.2. The semiconductor structure of claim 1 , further comprising a graded group III-V superlattice layer.3. The semiconductor structure of claim 1 , further comprising an AlN nucleation layer.4. The semiconductor structure of claim 1 , wherein the interlayer is made of AlN.5. The semiconductor structure of claim 1 , wherein the first bulk layer of group III-V compound is GaN.6. The semiconductor structure of claim 2 , wherein the graded group III-V superlattice layer has a thickness between 500 and 1000 nm.7. The semiconductor structure of claim 3 , wherein the AlN nucleation layer has a thickness between 150 and 300 nm.8. The semiconductor structure of claim 1 , wherein a second interlayer is over the second bulk layer of group III-V compound semiconductor.9. The semiconductor structure of claim 1 , wherein a third bulk layer of group III-V compound semiconductor is over the second interlayer.10. The semiconductor structure of claim 1 , wherein more than two bulk layers of group III-V compound semiconductor are over the silicon substrate.11. The semiconductor structure of claim 10 , wherein each bulk layer of group III-V compound semiconductor is separated by an interlayer.12. The semiconductor structure of claim 1 , wherein the bulk layer is about 0.5 to about 5 microns.1318-. (canceled)19. The method of claim 1 , wherein the semiconductor structure is a light emitting diode.20. The method of claim 1 , wherein the semiconductor ...

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Номер записи: 24
11-07-2013 дата публикации

Pixel structure and manufacturing method thereof

Номер: US20130175532A1
Автор: Chi-Ming Chiou, Chin-Tzu Kao, Yu-Tsung Lee
Принадлежит: Chunghwa Picture Tubes Ltd

A method for manufacturing a pixel structure is provided. A thin film transistor is formed on a substrate and an insulating layer is formed to cover the substrate and the thin film transistor. The insulating layer is patterned by a half-tone mask to form a protruding pattern, a sunken pattern connecting the protruding pattern, and a contact window inside the sunken pattern. A transparent conductive layer is formed to cover the protruding pattern and the sunken pattern, and filled in the contact window. A passivation layer is formed to cover the transparent conductive layer. A pixel electrode pattern is formed from the transparent conductive layer by removing a part of the passivation layer located on the protruding pattern, a part of the transparent conductive layer on the protruding pattern, and a part of the passivation layer located within the contact window. A pixel structure manufactured by the method is provided.

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Номер записи: 25
29-08-2013 дата публикации

METHOD OF MANUFACTURING A LAMINATE CIRCUIT BOARD WITH A MULTILAYER CIRCUIT STRUCTURE

Номер: US20130219713A1
Автор: Chen Ya-Hsiang, Hsu Jun-Chung, Lin Chi-Ming, Yeh Tso-Hung
Принадлежит: KINSUS INTERCONNECT TECHNOLOGY CORP.

A method of manufacturing a laminate circuit board with a multilayer circuit structure which includes the steps of forming a metal layer on a substrate, patterning the metal layer to form a circuit metal layer, forming a nanometer plating layer on the circuit metal layer, forming a cover layer to cover the substrate and the nanometer plating layer, forming through holes in the cover layer to generate openings exposing part of the nanometer plating layer, and finally forming a second metal layer on the cover layer to fill up the openings is disclosed. The nanometer plating layer is used to obtain same effect of previously roughening by chemical bonding, such that no circuit width is reserved for compensation, and the density of the circuit increases such that much more dense circuit can be implemented. 1. A method of manufacturing a laminate circuit board with a multilayer circuit structure , comprising:forming a metal layer on both an up side and a down side of a substrate;patterning the metal layer to form a circuit metal layer through an image transfer process;forming a nanometer plating layer with a thickness of 5˜40 nm on the circuit metal layer; andforming a cover layer made of a binder or a solder resist on the substrate for covering the circuit metal layer and the nanometer plating layer to generate the multi-layer circuit structure,wherein at least one of the up side and the down side of the substrate is a smooth surface, and an outer surface of the circuit metal layer, the smooth surface of the substrate and an outer surface of the nanometer plating layer have a roughness which is defined by Ra (Arithmetical mean roughness)<0.35 μm and Rz (Ten-point mean roughness)<3 μm and not recognizable by cross-sectional examination through an optical microscope of 1,000 magnifications.2. The method as claimed in claim 1 , further comprising:forming at least one through hole on the cover layer with respect to the circuit metal layer to generate at least one opening ...

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Номер записи: 26
29-08-2013 дата публикации

LAMINATE CIRCUIT BOARD WITH A MULTI-LAYER CIRCUIT STRUCTURE

Номер: US20130224513A1
Автор: Chen Ya-Hsiang, Hsu Jun-Chung, Lin Chi-Ming, Yeh Tso-Hung
Принадлежит: KINSUS INTERCONNECT TECHNOLOGY CORP.

A laminate circuit board with a multi-layer circuit structure which includes a substrate, a first circuit metal layer, a second circuit metal layer, a first nanometer plating layer, a second nanometer plating layer and a cover layer is disclosed. The first circuit metal layer is embedded in the substrate or formed on at least one surface of the substrate which is smooth. The first nanometer plating layer with a smooth surface overlaps the first circuit metal layer. The second nanometer plating layer is formed on the other surface of the substrate and fills up the opening in the cover layer to electrically connect the first circuit metal layer. The junction adhesion is improved by the chemical bonding between the nanometer plating layer and the cover layer/the substrate. Therefore, the circuit metal layer does not need to be roughened and the density of the circuit increases. 1. A laminate circuit board with a multi-layer circuit structure , comprising:a substrate, one of an up and down surfaces of the substrate is a smooth surface;a first circuit metal layer, formed on the up surface of the substrate;a second circuit metal layer, formed on the down surface of the substrate;a first nanometer plating layer, overlapping the first circuit metal layer;a second nanometer plating layer, overlapping the second circuit metal layer; anda cover layer, formed on the substrate to cover the first nanometer plating layer on the first circuit metal layer and the second nanometer plating layer on the second circuit metal layer,wherein each of the first circuit metal layer, the second circuit metal layer, the first nanometer plating layer and the second nanometer plating layer has a smooth surface which has a roughness defined by Ra (Arithmetical mean roughness)<0.35 μm and Rz (Ten-point mean roughness)<3 μm and not recognizable by cross-sectional examination through an optical microscope of 1,000 magnifications.2. The laminate circuit board as claimed in claim 1 , wherein the first ...

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Номер записи: 27
03-10-2013 дата публикации

METHOD OF MANUFACTURING A LAMINATE CIRCUIT BOARD

Номер: US20130255858A1
Автор: Chen Ya-Hsiang, Hsu Jun-Chung, Lin Chi-Ming, Yeh Tso-Hung
Принадлежит:

A method of manufacturing a laminate circuit board is disclosed. The method includes forming a metal layer on a substrate, patterning the metal layer to form a circuit metal layer, forming a nanometer plating layer with a thickness of 5 to 40 nm over the circuit metal layer, and forming a cover layer covering the substrate and the nanometer plating layer with improved adhesion by chemical bonding to form the laminate circuit board. Another method includes forming the circuit metal layer and the nanometer plating layer on a preforming substrate, pressing the preforming substrate against a substrate to push the circuit metal layer and the nanometer plating layer into the substrate, and removing the preforming substrate. By the present invention, the density of circuit is increased and much denser circuit can be implemented on the substrate with the same area. 1. A method of manufacturing a laminate circuit board , comprising steps of:forming a metal layer on a substrate having a rough upper surface;patterning the metal layer to form a circuit metal layer through a pattern transfer process;forming a nanometer plating layer with a thickness of 5 to 40 nm over the circuit metal layer, said nanometer plating layer having a roughness which is defined by Ra (Arithmetical mean roughness) less than 0.35 μm and Rz (Ten-point mean roughness) less than 3 μm; andforming a cover layer by a binder or a solder resist covering the substrate and the nanometer plating layer with adhesion by chemical bonding so as to form the laminate circuit board,wherein each of said nanometer plating layer and said circuit metal layer has an outer surface, which does not have a recognizable roughness by cross-sectional examination through an optical microscope of 1,000 magnifications.2. The method as claimed in claim 1 , wherein said substrate is made of FR4 glass fiber or bismaleimide triazime resin claim 1 , said metal layer is made of at least one of copper claim 1 , aluminum claim 1 , silver and ...

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Номер записи: 28
17-10-2013 дата публикации

Platinum(ii) complexes for oled applications

Номер: US20130274473A1
Автор: Chi Chung Kwok, Chi Fai Kui, Chi Ming Che
Принадлежит: University of Hong Kong HKU

The current invention relates to novel platinum(II) based organometallic materials. These materials show high emission quantum efficiencies and low self-quenching constant. Also provided are high efficiency, green to orange emitting organic light-emitting diode (OLED) that are fabricated using platinum(II) based organometallic materials as the light-emitting material. The organometallic materials of the invention are soluble in common solvents; therefore, solution process methods such as spin coating and printing can be used for device fabrication. The devices fabricated from these materials show low efficiency roll-off.

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Номер записи: 29
31-10-2013 дата публикации

LAMINATE CIRCUIT BOARD STRUCTURE

Номер: US20130284500A1
Автор: Chen Ya-Hsiang, Hsu Jun-Chung, Lin Chi-Ming, Yeh Tso-Hung
Принадлежит:

A laminate circuit board structure from button up including a substrate, a circuit metal layer, a nanometer plating layer and a cover layer is disclosed. The nanometer plating layer is smooth a thickness of 5-40 nm, and can be directly forming on the outer surface of the circuit metal layer or manufactured by firstly forming the nanometer plating layer on a preforming substrate, then pressing the substrate against the nanometer plating layer, and finally removing the preforming substrate. The junction adhesion between the nanometer plating layer and the cover layer or the substrate is improved by chemical bonding. Therefore it does not need to roughen the circuit metal layer or reserve circuit width for compensation such that the density of the circuit increases and much more dense circuit can be implemented in the substrate with the same area. 1. A laminate circuit board structure , comprising:a substrate, having a rough upper surface;a circuit metal layer, formed on the upper surface of the substrate;a nanometer plating layer, formed on the circuit metal layer and having a thickness of 5-40 nm and a rough outer surface with a roughness defined by Ra (Arithmetical mean roughness) <0.35 μm and Rz (Ten-point mean roughness) <3 μm; anda cover layer, made of a binder or a solder resist, having an outer surface and covering the circuit metal layer and the nanometer plating layer,wherein the outer surfaces of the circuit metal layer and the nanometer plating layer are smooth and do not have a recognizable roughness by cross-sectional examination through an optical microscope of 1,000 magnifications.2. The laminate circuit board structure as claimed in claim 1 , wherein said substrate is made of FR4 glass fiber or bismaleimide triazime resin claim 1 , said metal layer is made of at least one of copper claim 1 , aluminum claim 1 , silver and gold claim 1 , and said nanometer plating layer is made of at least two of copper claim 1 , tin claim 1 , aluminum claim 1 , nickel ...

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Номер записи: 30
07-11-2013 дата публикации

LOCK AND THE APPLICATION THEREOF

Номер: US20130291605A1
Автор: Liu Chi-ming
Принадлежит: CELESTICA TECHNOLOGY CONSULTANCY (SHANGHAI) CO., LTD

The present invention discloses a lock and the application thereof. The lock is applied on a base having an inner surface and an outer surface. The lock comprises a locking plate and a motion module. The motion module has a curved surface facing the locking plate. The curved surface has a first surface and a second surface. A main feature of the present invention is that the lock has a close status and a far status. The locking plate contacts with the first surface and has a first distance from the base in the close status, and contacts with the second surface of the base and has a second distance, which is greater than the first distance, from the base in the far status. The invention has the advantages of low cost and simplicity, and solves the long lasting problem of the prior arts. 1. A lock mounted to a base , the base having an inner surface and an outer surface , the lock comprising:a lock plate; and 'wherein the lock has a close status and a far status, and the lock plate abuts against the first surface and has a first distance from the base when the lock is in the close status, and abuts against the second surface and has a second distance, which is greater than the first distance, from the base when the lock is in the far status.', 'a motion module having a curved surface facing the lock plate, the curved surface comprising a first surface and a second surface;'}2. The lock of claim 1 , wherein the lock plate comprises:a fixed portion fixed to the inner surface of the base;a movable portion extending outwards from the fixed portion;a through-hole portion formed in the movable portion and through the lock plate, and the through-hole portion having a sidewall; andan abutting portion extending in an normal direction from the sidewall and abutting against the curved surface of the lock to adjust a relative distance between the lock plate and the base.3. The lock of claim 2 , wherein the fixed portion claim 2 , the movable portion claim 2 , the through-hole ...

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Номер записи: 31
02-01-2014 дата публикации

Graded Aluminum-Gallium-Nitride and Superlattice Buffer Layer for III-V Nitride Layer on Silicon Substrate

Номер: US20140001439A1
Автор: Chen Chi-Ming, Liu Po-Chun, Yu Chung-Yi
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure is directed to an integrated circuit and a method for the fabrication of the integrated circuit. The integrated circuit includes a lattice matching structure. The lattice matching structure can include a first buffer region, a second buffer region and a superlattice structure formed from AlGaN/AlGaN layer pairs. 1. An integrated circuit comprising:a silicon substrate having a first lattice structure;a group III nitride layer overlying the silicon substrate and having a second lattice structure; a first buffer region', 'a second buffer region; and', {'sub': x', '1−x', 'y', '1−y, 'a superlattice structure comprising AlGaN/AlGaN repeating layer pairs.'}], 'a lattice-matching structure arranged between the silicon substrate and the group III nitride layer configured to provide an interface between the first lattice structure and the second lattice structure, comprising2. The integrated circuit of claim 1 , wherein the first buffer region of the lattice matching structure comprises a first layer of an AlN formed at a thickness from about 20 nm to about 80 nm and a second layer of an aluminum nitride formed at a thickness of from about 50 to about 200 nm.3. The integrated circuit of claim 1 , wherein the second buffer region of the lattice-matching structure comprises a plurality of graded AlGaN layers.4. The integrated circuit of claim 3 , wherein x decreases continuously from an first graded AlGaN layer to a subsequent graded AlGaN layer.5. The integrated circuit of claim 3 , wherein the plurality of graded AlGaN layers comprises three layers.6. The integrated circuit of claim 3 , wherein x comprises from about 0.9 to about 0.7 in a first layer claim 3 , x comprises from about 0.4 to about 0.6 in a second layer claim 3 , and x comprises from about 0.15 to about 0.2 in a third layer.7. The integrated circuit of claim 6 , wherein the first layer comprises a thickness of from about 50 nm to about 200 nm claim 6 , the second layer comprises a ...

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Номер записи: 32
16-01-2014 дата публикации

Diffusion Barrier Layer for Group III Nitride on Silicon Substrate

Номер: US20140014967A1
Автор: Chen Chi-Ming, Chiu Han-Chin, Tsai Chia-Shiung, Yu Chung-Yi
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure is directed to an integrated circuit and its formation. In some embodiments, the integrated circuit includes a diffusion barrier layer. The diffusion barrier layer can be arranged to prevent diffusion of the Si and Ofrom a Si substrate into a Group III nitride layer. The diffusion barrier layer can comprise AlO. In some embodiments, the integrated circuit further comprises a lattice-matching structure disposed between the silicon substrate and a Group III nitride layer. 1. An integrated circuit comprising:a silicon substrate having a first lattice structure;a GaN layer disposed over the silicon substrate and having a second lattice structure that differs from the first lattice structure;a lattice-matching structure arranged between the silicon substrate and the GaN layer and arranged to interface the first lattice structure to the second lattice structure; anda diffusion-barrier layer arranged between the silicon substrate and the lattice matching structure, the diffusion-barrier layer configured to limit diffusion of silicon Of and oxygen from the silicon substrate to the lattice matching structure.2. The integrated circuit of claim 1 , wherein the barrier layer comprises a single crystal alpha or gamma crystal structure.3. The integrated circuit of claim 1 , wherein the barrier layer comprises AlO claim 1 , SiN claim 1 , ZnO claim 1 , MgO claim 1 , LaO claim 1 , or YO.4. The integrated circuit of claim 1 , wherein the silicon substrate is Si(111).5. The integrated circuit of claim 1 , wherein the lattice matching structure comprises a first region and a second region.6. The integrated circuit of claim 5 , wherein the first region of the lattice matching structure comprises a first layer of an aluminum nitride formed at a first temperature and a second layer of an aluminum nitride formed at second temperature higher than the first temperature.7. The integrated circuit of claim 6 , wherein the thickness of the first aluminum nitride layer is ...

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Номер записи: 33
13-02-2014 дата публикации

HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME

Номер: US20140042446A1
Автор: Chen Chi-Ming, CHIANG Chen-Hao, Chiu Han-Chin, Liu Po-Chun, Yu Chung-Yi
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are in contact with the second III-V compound layer. A n-type doped region underlies each source feature and drain feature in the second III-V compound layer. A p-type doped region underlies each n-type doped region in the first III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the source feature and the drain feature. 1. A high electron mobility transistor (HEMT) comprising:a first III-V compound layer;a second III-V compound layer on the first III-V compound layer and different from the first III-V compound layer in composition;a source feature and a drain feature in contact with the second III-V compound layer;a n-type doped region underlying each source feature and drain feature in the second III-V compound layer;a p-type doped region underlying each n-type doped region in the first III-V compound layer; anda gate electrode over a portion of the second III-V compound layer between the source feature and the drain feature.2. The HEMT of claim 1 , wherein the n-type doped region comprises a Group IV element.3. The HEMT of claim 1 , wherein the n-type doped region comprises silicon or oxygen.4. The HEMT of claim 1 , wherein the p-type doped region comprises a Group II element.5. The HEMT of claim 1 , wherein the p-type doped region comprises magnesium claim 1 , calcium claim 1 , beryllium or zinc.6. The HEMT of claim 1 , wherein the source feature and the drain feature comprise Ti claim 1 , Co claim 1 , Ni claim 1 , W claim 1 , Pt claim 1 , Ta claim 1 , Pd claim 1 , Mo claim 1 , Al or TiN.7. The HEMT of further comprising a carrier channel located in the first III-V compound layer along an interface between the first III-V compound layer and the ...

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Номер записи: 34
13-02-2014 дата публикации

Hybrid-type rechargeable battery module

Номер: US20140045003A1
Автор: Chi-Ming Lan, Chien-Lee LIU
Принадлежит: Compal Electronics Inc

Disclosed herein is a hybrid-type rechargeable battery module that includes a first cell block, a second cell block, a first switch, a second switch and a control unit. The control unit is configured to obtain the statuses of the first and second cell blocks and control the charging/discharging process of the first and second cell blocks. The first switch is electrically connected to the first cell block and the control unit so as to use the control unit to allow the first cell block to enter a discharging condition based on a difference value between the first and second electric capacities. The second switch is electrically connected to the second cell block and the control unit so as to use the control unit to allow the second cell block to enter a discharging condition based on the difference value between the first and second electric capacities.

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Номер записи: 35
07-01-2016 дата публикации

ISOLATION TRENCH THROUGH BACKSIDE OF SUBSTRATE

Номер: US20160005642A1
Автор: Chang Che-Ming, Chen Chi-Ming, CHOU Chung-Yen, Liu Ming Chyi, Liu Sheng-de, Tsai Chia-Shiung
Принадлежит:

Among other things, one or more semiconductor arrangements comprising isolation trenches, and techniques for forming such isolation trenches are provided. A substrate comprises a front side surface and a backside surface. One or more devices are formed over the front side surface. A wet etch is performed to form a tapered portion of an isolation trench. A dry etch is performed to form a non-tapered portion of the isolation trench. Because both the wet etch and the dry etch are performed, etching time is reduced compared to merely using the dry etch due to the wet etch having a relatively faster etch rate than the dry etch. In an embodiment, the isolation trench provides isolation for a current leakage path associated with a device or other material formed over the front side surface. In an embodiment, metal is formed within the isolation trench for backside metallization. 1. A method for forming an isolation trench through a backside surface of a substrate , comprising:applying a pattern mask to a backside surface of a substrate, the substrate comprising a front side surface over which one or more devices are formed;performing a wet etch to form a tapered portion of an isolation trench within the substrate; andperforming a dry etch to form a non-tapered portion of the isolation trench within the substrate, the non-tapered portion having a non-tapered width that is less than a tapered width of the tapered portion.2. The method of claim 1 , the wet etch performed before the dry etch.3. The method of claim 1 , the performing a wet etch comprising applying an acid base corresponding to at least one of a hydrofluoric nitric acetic (HNA) mixture claim 1 , a hydrofluoric acid-hydrogen peroxide mixture (FPM) mixture claim 1 , or a hydrofluoric acid-ozone mixture (FOM) mixture.4. The method of claim 1 , the performing a wet etch comprising applying an alkali base corresponding to at least one of ammonium hydroxide claim 1 , tetramethylammonium hydroxide claim 1 , or ...

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Номер записи: 36
08-01-2015 дата публикации

ISOLATION TRENCH THROUGH BACKSIDE OF SUBSTRATE

Номер: US20150008556A1
Автор: Chang Che-Ming, Chen Chi-Ming, CHOU Chung-Yen, Liu Ming Chyi, Liu Sheng-de, Tsa Chia-Shiung
Принадлежит:

Among other things, one or more semiconductor arrangements comprising isolation trenches, and techniques for forming such isolation trenches are provided. A substrate comprises a front side surface and a backside surface. One or more devices are formed over the front side surface. A wet etch is performed to form a tapered portion of an isolation trench. A dry etch is performed to form a non-tapered portion of the isolation trench. Because both the wet etch and the dry etch are performed, etching time is reduced compared to merely using the dry etch due to the wet etch having a relatively faster etch rate than the dry etch. In an embodiment, the isolation trench provides isolation for a current leakage path associated with a device or other material formed over the front side surface. In an embodiment, metal is formed within the isolation trench for backside metallization. 1. A semiconductor arrangement , comprising:a substrate comprising a front side surface and a backside surface;one or more devices formed over the front side surface; andan isolation trench formed through the backside surface of the substrate, the isolation trench comprising a tapered portion and a non-tapered portion, the non-tapered portion having a non-tapered width that is less than a tapered width of the tapered portion.2. The semiconductor arrangement of claim 1 , the tapered portion formed between the backside surface of the substrate and the non-tapered portion.3. The semiconductor arrangement of claim 1 , the non-tapered portion formed between the front side surface of the substrate and the tapered portion.4. The semiconductor arrangement of claim 1 , the non-tapered portion formed by a wet etch technique and the tapered portion formed by a dry etch technique.5. The semiconductor arrangement of claim 4 , the dry etch technique performed after the wet etch technique.6. The semiconductor arrangement of claim 1 , the tapered portion comprising a curved profile.7. The semiconductor arrangement ...

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Номер записи: 37
09-01-2020 дата публикации

METHOD FOR CALCULATING GLOMERULAR FILTRATION RATE (GFR)

Номер: US20200011882A1
Автор: CHANG SHIH-TAI, CHU CHI-MING, HSIAO PO-JEN, SHIH YUN-WEN
Принадлежит:

A method for calculating glomerular filtration rate (GFR) is revealed. A circumference of a patent's neck is measured and then is substituted into an exponential formula together with clinical factors and patient's age for estimating GFR. The present method has a better performance compared with methods for evaluating renal function by GFR available now. The methods available now have poor performance in prediction of loss of renal function at early stage. Some patients are diagnosed at an advanced stage so that they miss the opportunity of early treatment. 2. The method as claimed in claim 1 , wherein the exponential formula for estimating the GFR is: 24×(the age)×(the concentration value of serum creatinine)×(the concentration value of cystatin C)×(the circumference)×(the concentration value of albuminuria)×0.502 when the patient is female.4. A method for calculating glomerular filtration rate (GFR) comprising the steps of:measuring a circumference of a patient's neck;detecting concentration of a plurality of clinical factors in a specimen from the patient to get a plurality of concentration values while the clinical factors having serum creatinine, cystatin C, albuminuria and a combination thereof, andsubstituting the concentration values, the circumference and the patient's age into a formula to get a logarithm (log) of glomerular filtration rate (GFR).5. The method as claimed in claim 4 , wherein the formula for getting a log of GFR is: A+x log (the circumference)+y log (the age)+z log (the serum creatinine) when the clinical factor is serum creatinine; wherein the formula to get a log of GFR is: A+x log (the circumference)+y log (the age)+z log (the serum creatinine)+B when the clinical factor is serum creatinine and the patient is female; wherein A is ranging from 0.4 to 3.4 claim 4 , x is ranging from 0.2 to 1.5 claim 4 , y is ranging from −1.2 to −0.4 claim 4 , z is ranging from −1.2 to −0.7 claim 4 , and B is ranging from −0.2 to 0.6. The method as claimed ...

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Номер записи: 38
22-01-2015 дата публикации

TRANSISTOR HAVING A BACK-BARRIER LAYER AND METHOD OF MAKING THE SAME

Номер: US20150021660A1
Автор: Chen Chi-Ming, Chen Xiaomeng, CHING Ming-Chang, Hsiung Chih-Wen, Liu Po-Chun, Yu Chung-Yi
Принадлежит:

A transistor includes a substrate and a buffer layer on the substrate, wherein the buffer layer comprises p-type dopants. The transistor further includes a channel layer on the buffer layer and a back-barrier layer between a first portion of the channel layer and a second portion of the channel layer. The back-barrier layer has a band gap discontinuity with the channel layer. The transistor further includes an active layer on the second portion of the channel layer, wherein the active layer has a band gap discontinuity with the second portion of the channel layer. The transistor further includes a two dimensional electron gas (2-DEG) in the channel layer adjacent an interface between the channel layer and the active layer. 1. A transistor comprising:a substrate;a buffer layer on the substrate, wherein the buffer layer comprises p-type dopants;a channel layer on the buffer layer;a back-barrier layer between a first portion of the channel layer and a second portion of the channel layer, wherein the back-barrier layer has a band gap discontinuity with the channel layer;an active layer on the second portion of the channel layer, wherein the active layer has a band gap discontinuity with the second portion of the channel layer, and the active layer has a first width smaller than a second width of the channel layer; anda two dimensional electron gas (2-DEG) in the channel layer adjacent an interface between the channel layer and the active layer.2. The transistor of claim 1 , wherein the back-barrier layer comprises aluminum nitride (AlN).3. The transistor of claim 1 , wherein the back-barrier layer comprises aluminum gallium nitride (AlGaN).4. The transistor of claim 3 , wherein x ranges from about 0.1 to about 0.9.5. The transistor of claim 1 , wherein the back-barrier layer comprises indium aluminum nitride (InAlN).6. The transistor of claim 5 , wherein y is equal to or greater than 0.5.7. The transistor of claim 1 , wherein a dopant concentration of the p-type dopants ...

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Номер записи: 39
22-01-2015 дата публикации

TRANSISTOR HAVING BACK-BARRIER LAYER AND METHOD OF MAKING THE SAME

Номер: US20150021665A1
Автор: Chen Chi-Ming, CHIANG Chen-Hao, CHING Ming-Chang, LIU MING-CHYI, Liu Po-Chun, Yu Chung-Yi
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A transistor includes a substrate, a channel layer over the substrate, a back-barrier layer over the channel layer, and an active layer over the back-barrier layer. The back-barrier layer has a band gap discontinuity with the channel layer. The band gap of the active layer is less than the band gap of the back-barrier layer. A two dimensional electron gas (2-DEG) is formed in the channel layer adjacent an interface between the channel layer and the back-barrier layer. 1. A transistor comprising:a substrate;a channel layer over the substrate;a back-barrier layer over the channel layer, the back-barrier layer having a band gap discontinuity with the channel layer;an active layer over the back-barrier layer, a band gap of the active layer being less than the band gap of the back-barrier layer;a two dimensional electron gas (2-DEG) in the channel layer adjacent an interface between the channel layer and the back-barrier layer; anda source electrode and a drain electrode over the channel layer, wherein a portion of at least one of the source electrode or the drain electrode is embedded in the channel layer.2. The transistor of claim 1 , wherein the back-barrier layer comprises aluminum nitride (AlN).3. The transistor of claim 1 , wherein a band gap of the back-barrier layer is at least 0.5 electron volt (eV) greater than a band gap of the active layer.4. The transistor of claim 1 , wherein a band gap of the back-barrier layer is about 1.8 eV greater than a band gap of the active layer.5. The transistor of claim 1 , further comprising a nucleation layer between the substrate and the channel layer.6. The transistor of claim 5 , wherein the nucleation layer comprises:a first seed layer having a first lattice structure; anda second seed layer on the first seed layer, the second seed layer having a second lattice structure different from the first lattice structure.7. The transistor of claim 1 , further comprising a buffer layer between the substrate and the channel layer.8. ...

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Номер записи: 40
22-01-2015 дата публикации

TRANSISTOR HAVING PARTIALLY OR WHOLLY REPLACED SUBSTRATE AND METHOD OF MAKING THE SAME

Номер: US20150021666A1
Автор: Chen Chi-Ming, Chen Xiaomeng, HSIEH Yuan-Chih, Hsiung Chih-Wen, Liu Ming Chyi, Liu Po-Chun, Tsai Chia-Shiung, Yu Chung-Yi
Принадлежит:

A transistor includes a substrate, a channel layer over the substrate, an active structure over the channel layer, a gate electrode over the channel layer, and a drain electrode over the channel layer. The active structure is configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active structure. The gate electrode and the drain electrode define a first space therebetween. The substrate has a first portion directly under the first space defined between the gate electrode and the drain electrode, and the first portion has a first electrical conductivity value less than that of intrinsic silicon and a thermal conductivity value greater than that of intrinsic silicon. 19-. (canceled)10. A method of forming a transistor , comprising:forming a channel layer over a first substrate, the first substrate having a first thickness;forming an active structure over the channel layer, the active structure being configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active structure;forming a gate electrode over the channel layer;forming a drain electrode over the channel layer;converting the first substrate to a second substrate, the second substrate having a second thickness less than the first thickness;removing a portion of the second substrate to form an opening, the opening being directly under a first space defined between the gate electrode and the drain electrode; andfilling the opening with a material having an electrical conductivity value lower than that of intrinsic silicon and a thermal conductivity value greater than that of intrinsic silicon.11. The method of claim 10 , wherein the material comprises aluminum nitride (AlN) or silicon carbide (SiC).12. The method of claim 10 , further comprising:forming an interconnection structure over the active structure;mounting a supporting substrate ...

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Номер записи: 41
22-01-2015 дата публикации

High Electron Mobility Transistor and Method of Forming the Same

Номер: US20150021667A1
Автор: Chen Chi-Ming, Liu Po-Chun, Yu Chung-Yi
Принадлежит:

A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A fluorine region is embedded in the second III-V compound layer under the gate electrode. A diffusion barrier layer is disposed on top of the second III-V compound layer. A gate dielectric layer is disposed over the second III-V compound layer. The gate dielectric layer has a fluorine segment on the fluorine region and under at least a portion of the gate electrode. 1. A semiconductor structure comprising:a first III-V compound layer;a second III-V compound layer disposed on the first III-V compound layer and different from the first III-V compound layer in composition;a third III-V compound layer disposed over the second III-V compound layer, wherein a diffusion barrier layer is interposed between the second III-V compound layer and the third III-V compound layer; anda source contact and a drain contact disposed on the second III-V compound layer, wherein the third III-V compound layer is interposed between the source contact and the drain contact.2. The semiconductor structure of claim 1 , further comprising a gate electrode disposed over the third III-V compound layer.3. The semiconductor structure of claim 2 , wherein a width of the third III-V compound layer is less than a width of the gate electrode.4. The semiconductor structure of claim 2 , further comprising a gate dielectric layer claim 2 , the gate dielectric layer being interposed between the gate electrode and the second III-V compound layer.5. The semiconductor structure of claim 1 , wherein a ...

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Номер записи: 42
10-02-2022 дата публикации

Platinum (ii) schiff base complexes with increased emission quantum yield for red oled applications

Номер: US20220045285A1
Автор: Chi Ming Che, Chun Lam Kwong, Tsz Lung LAM
Принадлежит: Sichuan Knowledge Express Institute for Innovative Technologies Co Ltd

Red-emitting platinum (II) Schiff base complexes with high emission quantum efficiency are prepared. These materials can be used to fabricate OLEDs.

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Номер записи: 43
24-01-2019 дата публикации

SEMICONDUCTOR STRUCTURE HAVING SETS OF III-V COMPOUND LAYERS AND METHOD OF FORMING

Номер: US20190027360A1
Автор: Chen Chi-Ming, Liu Po-Chun, Tsai Chia-Shiung, Yu Chung-Yi
Принадлежит:

A semiconductor structure including a substrate and a nucleation layer over the substrate. The semiconductor structure further includes a first III-V layer over the nucleation layer, wherein the first III-V layer includes a first dopant type. The semiconductor structure further includes one or more sets of III-V layers over the first III-V layer. Each set of the one or more sets of III-V layers includes a lower III-V layer, wherein the lower III-V layer has a second dopant type opposite the first dopant type, and an upper III-V layer on the lower III-V layer, wherein the upper III-V layer has the first dopant type. The semiconductor structure further includes a second III-V layer over the one or more sets of III-V layers, the second III-V layer having the second dopant type. 1. A semiconductor structure comprising:a substrate;a nucleation layer over the substrate;a first III-V layer over the nucleation layer, wherein the first III-V layer includes a first dopant type; a lower III-V layer, wherein the lower III-V layer has a second dopant type opposite the first dopant type, and', 'an upper III-V layer on the lower III-V layer, wherein the upper III-V layer has the first dopant type; and', 'a second III-V layer over the one or more sets of III-V layers, the second III-V layer having the second dopant type., 'one or more sets of III-V layers over the first III-V layer, each set of the one or more sets of III-V layers comprising2. The semiconductor structure of claim 1 , further comprising a dielectric layer over the second III-V layer.3. The semiconductor structure of claim 2 , further comprising an active layer between the dielectric layer and the second III-V layer.4. The semiconductor structure of claim 2 , further comprising a gate electrode over the dielectric layer.5. The semiconductor structure of claim 1 , further comprising a pair of source/drain (S/D) electrodes claim 1 , wherein each of the pair of S/D electrodes directly contacts the second III-V layer.6. ...

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Номер записи: 44
28-01-2021 дата публикации

SEMICONDUCTOR STRUCTURE HAVING SETS OF III-V COMPOUND LAYERS AND METHOD OF FORMING

Номер: US20210028016A1
Автор: Chen Chi-Ming, Liu Po-Chun, Tsai Chia-Shiung, Yu Chung-Yi
Принадлежит:

A semiconductor structure includes a substrate. The semiconductor structure further includes a buffer layer over the substrate, wherein the buffer layer comprises a plurality of III-V layers, and a dopant type of each III-V layer of the plurality of III-V layers is opposite to a dopant of adjacent III-V layers of the plurality of III-V layers. The semiconductor structure further includes an active layer over the buffer layer. The semiconductor structure further includes a dielectric layer over the active layer. 1. A semiconductor structure comprising:a substrate;a buffer layer over the substrate, wherein the buffer layer comprises a plurality of III-V layers, and a dopant type of each III-V layer of the plurality of III-V layers is opposite to a dopant of adjacent III-V layers of the plurality of III-V layers;an active layer over the buffer layer; anda dielectric layer over the active layer.2. The semiconductor structure of claim 1 , further comprising a channel layer between the buffer layer and the active layer.3. The semiconductor structure of claim 2 , further comprising a source electrode directly contacting the channel layer.4. The semiconductor structure of claim 1 , wherein at least one of plurality of III-V layers comprises GaN.5. The semiconductor structure of claim 1 , further comprising a nucleation layer between the substrate and the buffer layer.6. The semiconductor structure of claim 5 , wherein the nucleation layer comprises AlN.7. The semiconductor structure of claim 5 , wherein the nucleation layer is configured to reduce lattice mismatch between the substrate and the buffer layer.8. The semiconductor structure of claim 1 , wherein the buffer layer directly contacts the substrate.9. A method of forming a semiconductor structure claim 1 , the method comprising:forming a nucleation layer over a substrate;growing a buffer layer over the nucleation layer, wherein growing the buffer layer comprises growing a plurality of pairs of layers, each pair of ...

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Номер записи: 45
01-05-2014 дата публикации

LOCK STRUCTURE

Номер: US20140116102A1
Автор: Chen Chi-Ming, Lu Shih-Min
Принадлежит: TAIWAN FU HSING INDUSTRIAL CO., LTD.

A lock structure includes a lock cylinder, a plug and a pin assembly, the plug is within an accommodating space of the lock cylinder. The plug comprises an outer lateral wall, a plurality of first lower pin holes and at least one second lower pin hole, each of the first lower pin holes comprises a first blocking edge, the second lower pin hole comprises a second blocking edge, wherein a second depth defined between the second blocking edge and the outer lateral wall is smaller than a first depth defined between the first blocking edge and the outer lateral wall. By height difference between the position of the first blocking edge and the position of the second blocking edge, an unmatched key can not contact with the second lower pin under instantaneous bump to prevent an unlock situation. Therefore, the burglar proof function is achieved. 1. A lock structure includes:a lock cylinder having an accommodating space;a plug disposed in the accommodating space and having an outer lateral wall, a plurality of first lower pin holes, at least one second lower pin hole and a keyhole, wherein each of the first lower pin holes and the at least one second lower pin hole are recessed from the outer lateral wall, each of the first lower pin holes comprises a first hole surface and a first blocking edge formed at the first hole surface, the at least one second lower pin hole comprises a second hole surface and a second blocking edge formed at the second hole surface, wherein a second depth defined between the second blocking edge and the outer lateral wall is smaller than a first depth defined between the first blocking edge and the outer lateral wall; anda pin assembly including a plurality of first lower pins and at least one second lower pin, each of the first lower pins is disposed at each of the first lower pin holes, and the at least one second lower pin is disposed at the at least one second lower pin hole.2. The lock structure in accordance with claim 1 , wherein the lock ...

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Номер записи: 46
01-02-2018 дата публикации

Graphics Pipeline That Supports Multiple Concurrent Processes

Номер: US20180033114A1
Автор: Chen Chi-Ming, Chung Hsin-Hao
Принадлежит:

A Graphics Processing Unit (GPU) concurrently executes kernel codes programmed in more than one programming framework. The GPU includes a first command decoder that decodes a first set of commands issued by a first Application Programming Interface (API) for executing a first kernel code. The GPU also includes a second command decoder that decodes a second set of commands issued by a second API for executing a second kernel code. The GPU also includes a plurality of shader cores and a pipe manager. According to decoded commands, the pipe manager assigns a first set of shader cores and a second set of shader cores to concurrently execute the first kernel code and the second kernel code, respectively. 1. A Graphics Processing Unit (GPU) operative to concurrently execute kernel codes programmed in more than one programming framework , the GPU comprising:a first command decoder to decode a first set of commands issued by a first Application Programming Interface (API) for executing a first kernel code of a first programming framework;a second command decoder to decode a second set of commands issued by a second API for executing a second kernel code of a second programming framework;a plurality of shader cores; anda pipe manager coupled to the first command decoder, the second command decoder and the shader cores, the pipe manager to assign a first set of shader cores and a second set of shader cores to concurrently execute the first kernel code and the second kernel code, respectively, according to decoded commands.2. The GPU of claim 1 , further comprising:a fixed-function pipeline operative to execute the first kernel code with the first set of the shader cores according to the first set of commands decoded by the first command decoder.3. The GPU of claim 2 , wherein the fixed-function pipeline and the first set of the shader cores are operative to perform operations of 3D graphics rendering and image composition according to the first kernel code.4. The GPU of claim ...

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Номер записи: 47
12-02-2015 дата публикации

SEMICONDUCTOR DEVICE, HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) AND METHOD OF MANUFACTURING

Номер: US20150041825A1
Автор: Chen Chi-Ming, Chen Xiaomeng, CHIANG Chen-Hao, Liu Po-Chun, Tsai Chia-Shiung, Yu Chung-Yi
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A semiconductor device includes a substrate, a channel layer over the substrate, an active layer over the channel layer, and a barrier structure between the substrate and the channel layer. The active layer is configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer. The barrier structure is configured to block diffusion of at least one of a material of the substrate or a dopant toward the channel layer. 1. A semiconductor device , comprising:a substrate;a channel layer over the substrate;an active layer over the channel layer, the active layer configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; anda barrier structure between the substrate and the channel layer, the barrier structure configured to block diffusion of at least one of a material of the substrate or a dopant toward the channel layer.2. The semiconductor device of claim 1 , further comprising:a buffer layer between the substrate and the channel layer, the buffer layer having a higher resistivity than a resistivity of the channel layer.3. The semiconductor device of claim 2 , wherein the barrier structure comprises a first barrier layer between the substrate and the buffer layer claim 2 , the first barrier layer configured to block diffusion of the material of the substrate to the buffer layer.4. The semiconductor device of claim 3 , wherein the barrier structure comprises a second barrier layer between the buffer layer and the channel layer claim 3 , the second barrier layer configured to block diffusion of the dopant from the buffer layer to the channel layer.5. The semiconductor device of claim 4 , wherein at least one of the first barrier layer or the second barrier layer comprises at least one material selected from the group consisting of SiC claim 4 , SiCNand BN.6. The semiconductor device of ...

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Номер записи: 48
04-02-2021 дата публикации

SEMICONDUCTOR DEVICE HAVING DOPED SEED LAYER AND METHOD OF MANUFACTURING THE SAME

Номер: US20210036140A1
Автор: Chen Chi-Ming, Lee Ru-Liang, Liu Po-Chun, Tsai Chia-Shiung, Yu Chung-Yi
Принадлежит:

A semiconductor device includes a doped substrate and a seed layer in direct contact with the substrate. The seed layer includes a first seed sublayer having a first lattice structure. The first seed layer is doped with carbon. The seed layer further includes a second seed sublayer over the first see layer, wherein the second seed layer has a second lattice structure. The semiconductor device further includes a graded layer in direct contact with the seed layer. The graded layer includes a first graded sublayer including AlGaN having a first Al:Ga ratio; a second graded sublayer including AlGaN having a second Al:Ga ratio different from the first Al:Ga ratio; and a third graded sublayer over including AlGaN having a third Al:Ga ratio different from the second Al:Ga ratio. The semiconductor device includes a channel layer over the graded layer. The semiconductor device includes an active layer over the channel layer. 1. A semiconductor device comprising:a doped substrate; a first seed sublayer having a first lattice structure, wherein the first seed layer comprises AlN, and the first seed layer is doped with carbon, and', 'a second seed sublayer over the first seed layer, wherein the second seed layer has a second lattice structure different from the first lattice structure;, 'a seed layer in direct contact with the substrate, wherein the seed layer comprises a first graded sublayer including AlGaN, wherein the first graded sublayer has a first Al:Ga ratio;', 'a second graded sublayer over the first graded sublayer, wherein the second graded sublayer includes AlGaN, and the second graded sublayer has a second Al:Ga ratio different from the first Al:Ga ratio; and', 'a third graded sublayer over the second graded sublayer, wherein the third graded sub layer includes AlGaN, and the third graded sublayer has a third Al:Ga ratio different from the second Al:Ga ratio;, 'a graded layer in direct contact with the seed layer, wherein the graded layer comprisesa channel layer ...

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Номер записи: 49
18-02-2021 дата публикации

HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) HAVING AN INDIUM-CONTAINING LAYER AND METHOD OF MANUFACTURING THE SAME

Номер: US20210050209A1
Автор: Chen Chi-Ming, CHIANG Chen-Hao, CHING Min-Chang, Hsu Chung-Chieh, Liu Po-Chun, Yu Chung-Yi
Принадлежит:

A high electron mobility transistor includes: a first semiconductor layer over a substrate, and a second semiconductor layer over the first semiconductor layer, the second semiconductor layer having a band gap discontinuity with the first semiconductor layer, and at the first semiconductor layer and/or the second conductive layer includes indium. A top layer is over the second semiconductor layer, and a metal layer is over, and extends into, the top layer, the top layer separating the metal layer from the second semiconductor layer. A gate electrode is over the top layer, a third semiconductor layer being between the gate electrode and the top layer, where a sidewall of the third semiconductor layer and a sidewall of the metal layer are separated. A source and drain are on opposite sides of the gate electrode, the top layer extending continuously from below the source, below the gate electrode, and below the drain. 1. A high electron mobility transistor (HEMT) comprising:a substrate;a first semiconductor layer over the substrate;a second semiconductor layer over the first semiconductor layer, wherein the second semiconductor layer has a band gap discontinuity with the first semiconductor layer, and at least one of the first semiconductor layer or the second semiconductor layer comprises indium;a top layer over the second semiconductor layer;a metal layer over and extending into the top layer, wherein the top layer separates the metal layer from the second semiconductor layer;a gate electrode over the top layer;a third semiconductor layer between the gate electrode and the top layer, wherein a sidewall of the third semiconductor layer is separated from a sidewall of the metal layer; anda source and a drain on opposite sides of the gate electrode, wherein the top layer extends continuously from below the source, below the gate electrode, and to below the drain.2. The HEMT of claim 1 , wherein the first semiconductor layer comprises an InGaN material.3. The HEMT of ...

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Номер записи: 50
19-02-2015 дата публикации

Soft Magnetic Composite Materials

Номер: US20150050178A1
Автор: CHAN Chi Ming, Ng Kai Mo
Принадлежит:

A soft magnetic composite (SMC) material is formed from atomized ferromagnetic particles. The particles of a predetermined size range are formed and are coated with at least one layer of electrically insulating nano-sized inorganic fillers to form insulated ferromagnetic powder as the SMC material. The particles are further coated with a lubricating agent to facilitated demoulding. 121-. (canceled)22. Method of forming a soft magnetic composite (SMC) material , said method comprising:forming atomized ferromagnetic particles of a predetermined size range;coating the particles with at least one layer of electrically insulating inorganic nanofillers to form an insulated ferromagnetic powder as the SMC material; andfurther coating the particles with a lubricating agent to facilitate demoulding.23. The method according to claim 22 , wherein the ferromagnetic powder comprises at least one material selected from the group consisting of iron claim 22 , nickel claim 22 , ferrosilicon alloys claim 22 , ferrosilicon (FeSi) and ferronickel alloys (FeNi).24. The method according to claim 22 , wherein the coating the particles further comprises:compacting the mixture at a high temperature; anddemoulding the compacted mixture.25. The method according to claim 24 , whereinthe lubricating agent comprises an organic lubricant.26. The method of claim 24 , further comprising:selecting, as the lubricant an inorganic/oganometallic based lubricant.27. The method according claim 24 , whereinthe lubricating agent comprises an organic lubricant selected from the group consisting of fatty acids having C12-C22, and their derivatives such as stearic acid and fatty acid amides, such as stearamide and bisethylenestearamide.28. The method according to any of claim 24 , whereinthe lubricating agent comprises an organic lubricant applied by dissolving the lubricant in a solvent (e.g., alcohol) and then coating the insulated ferromagnetic powder with the dissolved solvent or without solvent.29. The ...

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Номер записи: 51
18-02-2016 дата публикации

Scheme for activating or deactivating shipping mode for battery via battery connecting interface without additional signal port(s)

Номер: US20160049815A1
Автор: Chi-Ming Lee, Chih-Yuan Hsu, Jui-Chi Wu
Принадлежит: MediaTek Inc

A method for controlling a state of a battery includes: providing and using a specific connecting interface to connect the battery and a portable device; and controlling the battery to enter a shipping mode and exit the shipping mode by using the specific connecting interface.

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Номер записи: 52
25-02-2016 дата публикации

SUPPRESSION OF CANCER METASTASIS

Номер: US20160051634A1
Автор: Chiu Ching-Feng, Hung Shao-Wen, Liang Chi-Ming, Liang Shu-Mei, Peng Jei-Ming
Принадлежит:

Methods of using fibrillar proteins are provided for suppressing cancer metastasis. Cancer metastasis is the most common cause of treatment failure and death in cancer patients. Tumor cell invasion and/or migration can be significantly inhibited after fibrillar proteins (rVP1, F-HSA, and F-BSA) treatment in vitro. In addition, rVP1 can significantly suppress murine and human breast cancer metastasis and human prostate and ovarian cancer metastasis in vivo while F-HSA can significantly suppress murine breast cancer metastasis. 1. A method for suppressing cancer metastasis comprising:administering to a subject an effective amount of fibrillar proteins and a pharmaceutically acceptable carrier, wherein said administering reduces cancer metastasis in said subject.2. The method according to claim 1 , wherein said fibrillar proteins comprise fibrillar albumin protein.3. The method according to claim 2 , wherein said fibrillar proteins comprise fibrillar human serum albumin.4. The method according to claim 1 , wherein said fibrillar proteins comprise fibrillar capsid proteins of the foot-and-mouth-disease virus.5. The method of claim 1 , wherein said fibrillar protein is a chimeric.6. The method of claim 1 , wherein said subject is human.7. The method of claim 1 , wherein said cancer is breast cancer.8. The method of claim 1 , wherein said cancer is prostate cancer.9. The method of claim 1 , wherein said cancer is ovarian cancer.10. The method of claim 1 , wherein said cancer is cervical cancer.11. The method of claim 1 , wherein said administering is selected from the group consisting of intravenous injection claim 1 , subcutaneous injection claim 1 , intraperitoneal injection claim 1 , intraarterial injection claim 1 , intramuscular injection claim 1 , intralesional injection into the tumor claim 1 , intralesional injection adjacent to the tumor claim 1 , intravenous infusion claim 1 , and intraarterial infusion.12. The method of claim 1 , wherein said administering is ...

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Номер записи: 53
26-02-2015 дата публикации

TRANSISTOR HAVING AN OHMIC CONTACT BY SCREEN LAYER AND METHOD OF MAKING THE SAME

Номер: US20150053990A1
Автор: Chen Chi-Ming, Chen Xiaomeng, CHIANG Chen-Hao, Liu Po-Chun, Tsai Chia-Shiung, Yu Chung-Yi
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A transistor includes a substrate, a channel layer over the substrate and an active layer over the channel layer. The active layer includes a first portion and a screen layer over the first portion. The transistor includes a metal layer over the screen layer. 1. A transistor comprising:a substrate;a channel layer over the substrate; a first portion;', 'a screen layer over the first portion; and', 'an interface layer over the first portion, wherein the interface layer comprises n-doped gallium nitride (n-GaN); and, 'an active layer over the channel layer, wherein the active layer comprisesa metal layer over the screen layer.2. The transistor of claim 1 , wherein the screen layer comprises aluminum nitride (AlN).3. The transistor of claim 2 , wherein a thickness of the screen layer is less than or equal to 3 angstroms (Å).4. The transistor of claim 2 , wherein the first portion comprises aluminum gallium nitride (AlGaN).5. The transistor of claim 1 , further comprising:a buffer layer between the substrate and the channel layer.6. The transistor of claim 5 , wherein the buffer layer comprises:a first aluminum gallium nitride layer having a first aluminum concentration;a second aluminum gallium nitride layer having a second aluminum concentration less than the first aluminum concentration; anda third aluminum gallium nitride layer having a third aluminum concentration less than the second aluminum concentration.7. The transistor of claim 1 , further comprising a nucleation layer between the substrate and the channel layer claim 1 , wherein the nucleation layer comprises:a first seed layer having a first lattice structure; anda second seed layer on the first seed layer, the second seed layer having a second lattice structure different from the first lattice structure.8. (canceled)9. The transistor of claim 1 , further comprising:a first electrode on the active layer, wherein the first electrode forms an ohmic contact with the first portion;a second electrode on the ...

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Номер записи: 54
26-02-2015 дата публикации

TRANSISTOR HAVING AN OHMIC CONTACT BY GRADIENT LAYER AND METHOD OF MAKING THE SAME

Номер: US20150053991A1
Автор: Chen Chi-Ming, Chen Xiaomeng, CHIANG Chen-Hao, Liu Po-Chun, Tsai Chia-Shiung, Yu Chung-Yi
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A transistor includes a substrate, a channel layer over the substrate and an active layer over the channel layer. The active layer includes a gradient having a first concentration of a first material at an interface with the channel layer and a second concentration of the first material at a surface opposite the channel layer, and the first concentration is higher than the second concentration. 1. A transistor comprising:a substrate;a channel layer over the substrate;an active layer over the channel layer, wherein the active layer comprises a gradient layer having a first concentration of a first material at an interface with the channel layer and a second concentration of the first material at a surface opposite the channel layer, and the first concentration is higher than the second concentration, wherein the first concentration steadily decreases from the first value at the interface to the second value at the surface opposite the channel layer.2. The transistor of claim 1 , wherein the gradient layer comprises aluminum gallium nitride (AlGaN) claim 1 , and the first material comprises aluminum.3. The transistor of claim 2 , wherein the first concentration y ranges from about 0.2 to about 0.3 claim 2 , and the second concentration y ranges from about 0.1 to about 0.4. The transistor of claim 2 , wherein y gradually decreases from a maximum value at the interface with the channel layer to a minimum value at the surface opposite the channel layer.5. The transistor of claim 1 , further comprising:a buffer layer between the substrate and the channel layer.6. The transistor of claim 5 , wherein the buffer layer comprises:a first aluminum gallium nitride layer having a first aluminum concentration;a second aluminum gallium nitride layer having a second aluminum concentration less than the first aluminum concentration; anda third aluminum gallium nitride layer having a third aluminum concentration less than the second aluminum concentration.7. The transistor of claim 1 ...

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Номер записи: 55
26-02-2015 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING

Номер: US20150053992A1
Автор: Chen Chi-Ming, Chen Xiaomeng, CHIANG Chen-Hao, Liu Po-Chun, Tsai Chia-Shiung, Yu Chung-Yi
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A semiconductor device includes a substrate, a channel layer over the substrate, an active layer over the channel layer, a gate structure over the active layer, and a barrier layer between the gate structure and the active layer. The active layer is configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer. The gate structure is configured to deplete the 2DEG under the gate structure. The gate structure includes a dopant. The barrier layer is configured to block diffusion of the dopant from the gate structure into the active layer. 1. A semiconductor device , comprising:a substrate;a channel layer over the substrate;an active layer over the channel layer, the active layer configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer;a gate structure over the active layer, the gate structure configured to deplete the 2DEG under the gate structure, the gate structure comprising a dopant; anda barrier layer between the gate structure and the active layer, the barrier layer configured to block diffusion of the dopant from the gate structure into the active layer.2. The semiconductor device of claim 1 , wherein the barrier layer is configured to further deplete the 2DEG under the gate structure and partially deplete the 2DEG in a region surrounding the gate structure.3. The semiconductor device of claim 1 , whereinthe semiconductor device comprises a source region, a drain region, and a gate region corresponding to the gate structure,the barrier layer is continuous in the gate region, andthe barrier layer is discontinuous between (i) the gate region and (ii) at least one of the source region or the drain region.4. The semiconductor device of claim 3 , wherein claim 3 , between (i) the gate region and (ii) the at least one of the source region or the drain region claim 3 , the ...

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Номер записи: 56
10-03-2022 дата публикации

Capsule coffee machine

Номер: US20220071434A1
Автор: Chi-Ming Tseng
Принадлежит: Cheng Uei Precision Industry Co Ltd

A capsule coffee machine includes a base, a capsule channel formed at a top surface of the base, a gate, an optics lens, a guiding unit, a drip container, a collecting groove, a water injection unit connected with the guiding unit, a driving unit connected with the guiding unit, and an actuator. A bottom of the capsule channel is equipped with the gate. An inside of the capsule channel is equipped with the optics lens. The guiding unit is disposed under the gate and accommodated in the base. The drip container is connected with the guiding unit. The drip container has a mouth, a stopping wall opposite to the mouth, and a peripheral wall extended between the mouth and the stopping wall. The collecting groove is recessed towards a downward direction and in the peripheral wall of the drip container. The actuator is connected with the gate.

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Номер записи: 57
12-03-2015 дата публикации

LOCK STRUCTURE

Номер: US20150069769A1
Автор: Chen Chi-Ming
Принадлежит: TAIWAN FU HSING INDUSTRIAL CO., LTD.

A lock structure includes a first mounting plate and a positioning ring. The first mounting plate comprises a bottom plate and a plurality of fixing holes. The positioning ring comprises a ring body, an opening and a plurality of positioning members, and each of the positioning members comprises a positioning barrel having a body and a penetration hole. Each of the penetration holes is surrounded by each of the bodies. Each of the penetration holes corresponds to each of the fixing holes to make a fixing member passing through the fixing hole and fixedly secured at a positioning rod via guidance of each of the penetration holes. Therefore, the difficulty of assembly caused by the reason the fixing member is unable to align with the positioning member is eliminated. 1. A lock structure includes:a first mounting plate having a bottom plate and a plurality of fixing holes penetrating the bottom plate; anda positioning ring having a ring body, an opening and a plurality of positioning members, the opening is surrounded by the ring body, each of the positioning members comprises a positioning barrel having a body and a penetration hole surrounded by the body, each of the penetration holes corresponds to each of the fixing holes of the first mounting plate, each of the penetration holes is revealed by each of the fixing holes.2. The lock structure in accordance with claim 1 , wherein each of the positioning members comprises a connection rib claim 1 , one end of each of the connection ribs connects to the ring body claim 1 , and the other end of each of the connection ribs connects to each of the bodies.3. The lock structure in accordance with claim 2 , wherein the connection rib extends toward a center line of the ring body.4. The lock structure in accordance with claim 1 , wherein the first mounting plate comprises a lateral wall formed on the bottom plate claim 1 , the positioning ring comprises a plurality of protrusions formed at the ring body claim 1 , each of the ...

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Номер записи: 58
12-03-2015 дата публикации

POSITIVE PHOTOSENSITIVE RESIN COMPOSITION AND METHOD FOR FORMING PATTERN BY USING THE SAME

Номер: US20150072275A1
Автор: Liu Chi-ming, Shih Chun-An
Принадлежит:

The present invention relates to a positive photosensitive resin composition and a method for forming a pattern by using the same. The positive photosensitive resin composition includes a novolac resin (A), a polysiloxane (B), an ortho-naphthoquinone diazide sulfonic acid ester (C) and a solvent (D). The novolac resin (A) includes a xylenol-type novolac resin (A-1). The xylenol-type novolac resin (A-1) is synthesized by polycondensing an aldehyde compound with a xylenol compound. 1. A positive photosensitive resin composition , comprising:a novolac resin (A);a polysiloxane (B);an ortho-naphthoquinone diazide sulfonic acid ester (C); anda solvent (D).2. The positive photosensitive resin composition of claim 1 , wherein the polysiloxane (B) is formed by polymerizing a compound having a structure of formula (I):{'br': None, 'sub': 1', 'a', '2', '4-a, 'Si(R)(OR)\u2003\u2003(I)'}{'sub': 1', '2, 'in formula (I), Rrepresents a hydrogen atom, an alkyl group of 1 to 10 carbons, an alkenyl group of 2-10 carbons, an aromatic group of 6 to 15 carbons, an alkyl group having an anhydride group, an alkyl group having an epoxy group, or an alkoxy group having an epoxy group; Rrepresents a hydrogen atom, an alkyl group of 1 to 6 carbons, an acyl group of 1 to 6 carbons, or an aromatic group of 6 to 15 carbons; and a represents an integer of 0 to 3.'}3. The positive photosensitive resin composition of claim 2 , wherein at least one of the Rcomprises an alkyl group having an anhydride group claim 2 , an alkyl group having an epoxy group claim 2 , or an alkoxy group having an epoxy group.4. The positive photosensitive resin composition of claim 1 , wherein the novolac resin (A) includes a xylenol-type novolac resin (A-1) claim 1 , and the xylenol-type novolac resin (A-1) is formed by polycondensing an aldehyde compound with an aromatic hydroxy compound claim 1 , wherein the aromatic hydroxy compound at least comprises a xylenol compound.5. The positive photosensitive resin composition ...

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Номер записи: 59
10-03-2016 дата публикации

HIGH ELECTRON MOBILITY TRANSISTOR WITH INDIUM NITRIDE LAYER

Номер: US20160071969A1
Автор: Chen Chi-Ming, CHIANG Chen-Hao, CHING Min-Chang, Lee Ru-Liang, Liu Po-Chun, Tsai Chia-Shiung, Yu Chung-Yi
Принадлежит:

A semiconductor device includes a substrate, a first layer over the substrate, a second layer over the first layer, and a third layer over the second layer. The third layer has a first portion and a second portion. The first portion of the third layer is separated from the second portion of the third layer. The semiconductor device also includes a first blended region beneath the first portion of the third layer. The first blended region includes aluminum atoms drawn from the first layer into at least the second layer. The semiconductor device further includes a second blended region beneath the second portion of the third layer. The second blended region includes aluminum atoms drawn from the first layer into at least the second layer. The semiconductor device also includes a source contact and a drain contact. 1. A semiconductor device comprising:a substrate;a first layer comprising aluminum nitride over the substrate;a second layer comprising aluminum gallium nitride over the first layer;a third layer comprising indium gallium nitride over the second layer, the third layer having a first portion and a second portion, the first portion of the third layer being separated from the second portion of the third layer;a first blended region beneath the first portion of the third layer, the first blended region comprising aluminum atoms drawn from the first layer into at least the second layer;a second blended region beneath the second portion of the third layer, the second blended region comprising aluminum atoms drawn from the first layer into at least the second layer;a source contact over the first portion of the third layer; anda drain contact over the second portion of the third layer.2. The semiconductor device of claim 1 , wherein the third layer comprises between about 5% and about 20% indium.3. The semiconductor device of claim 1 , wherein the first layer is over at least one layer having 0% aluminum content.4. The semiconductor device of claim 1 , wherein the ...

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Номер записи: 60
16-03-2017 дата публикации

RADIOFREQUENCY ABLATION CATHETER AND THERAPY DEVICE INCLUDING THE RADIOFREQUENCY ABLATION CATHETER

Номер: US20170071668A1
Автор: CHAN Chi Ming, LI Linhua
Принадлежит: ANGEL MEDICAL TECHNOLOGY (NANJING) CO., LTD.

A radiofrequency ablation catheter includes an electrode ablation head (), a Positive Temperature Coefficient (PTC) thermistor (), and an inner conductor (), where the electrode ablation head () is disposed at an end portion of the inner conductor (), the PTC thermistor is disposed between the electrode ablation head () and the inner conductor (), and the inner conductor () is connected to a cable plug component (). The radiofrequency ablation catheter and a therapy device including the radiofrequency ablation catheter can precisely control the ablation temperature by means of PTC, such that upon coagulation of tissues, the ablation catheter is not adhered to the tissues, thus avoiding the risk of complications such as rebleeding. 1102030103010303040. A radiofrequency ablation catheter , comprising an electrode ablation head () , a Positive Temperature Coefficient (PTC) thermistor () , and an inner conductor () , wherein the electrode ablation head () is disposed at an end portion of the inner conductor () , the PTC thermistor is disposed between the electrode ablation head () and the inner conductor () , and the inner conductor () is connected to a cable plug component ().210. The radiofrequency ablation catheter according to claim 1 , wherein the electrode ablation head () is a tubular body claim 1 , and a tail end thereof is smooth and arc-shaped.310. The radiofrequency ablation catheter according to claim 1 , wherein a material of the electrode ablation head () is 304 medical stainless steel.420. The radiofrequency ablation catheter according to claim 1 , wherein a critical temperature of the PTC thermistor () is 80° C. to 120° C.512344411274714267765. A radiofrequency ablation catheter claim 1 , comprising an outer connector () claim 1 , a Positive Temperature Coefficient (PTC) thermistor () claim 1 , an inner conductor () claim 1 , an insulated conduit () claim 1 , wherein the insulated conduit () is rod-like claim 1 , and a tail end thereof is arc-shaped; an ...

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Номер записи: 61
24-03-2022 дата публикации

Thermal-Control System for a Security Camera and Associated Security Camera

Номер: US20220091484A1
Автор: Ali Ihab A., Cheng Kok Yen, Kraz Mark Benjamin, Lin Chi-Ming, Raghupathy Arun Prakash
Принадлежит: Google LLC

This document describes a thermal-control system that is integrated into a security camera. The thermal-control system includes a combination of heatsinks and thermal interface materials with high thermal conductivities. The thermal-control system may transfer and spread energy from a high thermal-loading condition effectuated upon the security camera to concurrently maintain temperatures of multiple thermal zones on or within the security camera at or below prescribed temperature thresholds. 1. A thermal-control system for a security camera , the thermal-control system comprising: a first thermal interface material, the first thermal interface material located between a system-on-chip integrated circuit device and a first heat sink, the system-on-chip integrated circuit device mounted to a first surface of a first printed circuit board;', 'a second thermal interface material, the second thermal interface material located between a memory integrated circuit device and the first heat sink, the memory integrated circuit device mounted to the first surface of the first printed circuit board; and', 'a third thermal interface material, the third thermal interface material located between a second surface of the first printed circuit board and a second heat sink, the second surface of the first printed circuit board opposite the first surface of the first printed circuit board; and, 'a first thermal-control subsystem, the first thermal-control subsystem configured to transfer a first quantity of heat to a housing, the first thermal-control subsystem including 'a fourth thermal interface material, the fourth thermal interface material located between a second surface of a second printed circuit board and a heat spreader, the second surface of the second printed circuit board opposite a first surface of the second printed circuit board to which a passive infrared sensor integrated circuit device and an image sensor integrated circuit device are mounted.', 'a second thermal- ...

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Номер записи: 62
24-03-2016 дата публикации

ABLATION APPARATUS

Номер: US20160081741A1
Автор: CHAN Chi Ming
Принадлежит:

An ablation needle is disclosed as including a needle body () and a needle head (), and a positive temperature coefficient (PTC) sleeve () in a heat-transferrable relationship with the needle body (). 1. An ablation device including:a needle with a needle body and a needle head, andat least one positive temperature coefficient (PTC) member in a heat-transferrable relationship with said needle body.2. A device according to wherein said PTC member comprises a sleeve member surrounding at least part of said needle body.3. A device according to wherein said needle body is solid.4. A device according to further including an inner electrically insulating sleeve surrounding and in contact with at least part of an outer cylindrical surface of said needle body claim 1 , an electrode sleeve surrounding and in contact with at least part of an outer cylindrical surface of said inner insulating sleeve claim 1 , an outer electrically insulating sleeve surrounding and in contact with at least part of an outer cylindrical surface of said electrode sleeve claim 1 , and an isolating electrically insulating layer surrounding and in contact with at least part of an outer cylindrical surface of said needle body.5. A device according to wherein said needle body and said needle head are integral with each other.6. A device according to wherein said isolating insulating layer is made at least principally of polytetrafluoroethylene.7. A device according to wherein said inner electrically insulating sleeve and/or said outer electrically insulating sleeve is made at least principally of polytetrafluoroethylene.8. A device according to wherein said needle body and/or said needle head is made at least principally of stainless steel.9. A device according to wherein the pointed end of said needle head is of an angle of between 10° to 20°.10. A device according to wherein the pointed end of said needle head is of an angle of substantially 14.5°.11. A device according to wherein said needle body is ...

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Номер записи: 63
05-03-2020 дата публикации

DOPED BUFFER LAYER FOR GROUP III-V DEVICES ON SILICON

Номер: US20200075314A1
Автор: Chen Chi-Ming, Chen Kuei-Ming, Yu Chung-Yi
Принадлежит:

Various embodiments of the present application are directed towards a group III-V device including a seed buffer layer that is doped and that is directly on a silicon substrate. In some embodiments, the group III-V device includes the silicon substrate, the seed buffer layer, a heterojunction structure, a pair of source/drain electrodes, and a gate electrode. The seed buffer layer overlies and directly contacts the silicon substrate. Further, the seed buffer layer includes a group III nitride (e.g., AlN) that is doped with p-type dopants. The heterojunction structure overlies the seed buffer layer. The source/drain electrodes overlie the heterojunction structure. The gate electrode overlies the heterojunction structure, laterally between the source/drain electrodes. The p-type dopants prevent the formation of a two-dimensional hole gas (2DHG) in the silicon substrate, along an interface at which the silicon substrate and the seed buffer layer directly contact. 1. A semiconductor device comprising:a substrate;a seed buffer layer overlying and directly contacting the substrate, wherein the seed buffer layer comprises a group III-V material that is doped and at an interface at which the substrate and the seed buffer layer directly contact;a heterojunction structure overlying the seed buffer layer;a pair of source/drain electrodes overlying the heterojunction structure; anda gate electrode overlying the heterojunction structure, laterally between the source/drain electrodes.2. The semiconductor device according to claim 1 , wherein the seed buffer layer comprises a group III nitride claim 1 , and wherein the substrate and the seed buffer layer are doped with same doping type.3. The semiconductor device according to claim 1 , wherein the seed buffer layer comprises aluminum nitride.4. The semiconductor device according to claim 1 , wherein the seed buffer layer is p-type.5. The semiconductor device according to claim 1 , wherein the seed buffer layer has a doping ...

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Номер записи: 64
26-03-2015 дата публикации

METHOD OF FORMING A HIGH ELECTRON MOBILITY TRANSISTOR

Номер: US20150087118A1
Автор: Chen Chi-Ming, CHIANG Chen-Hao, Chiu Han-Chin, Liu Po-Chun, Yu Chung-Yi
Принадлежит:

A method of forming a high electron mobility transistor may include: forming a second III-V compound layer on a first III-V compound layer, the second III-V compound layer and the first III-V compound layer differing in composition; forming a p-type doped region in the first III-V compound layer; forming an n-type doped region in the second III-V compound layer, the n-type doped region overlying the p-type doped region; forming a source feature over the second III-V compound layer, the source feature overlying the n-type doped region; and forming a gate electrode over the second III-V compound layer, the gate electrode disposed laterally adjacent to the source feature. 1. A method of forming a high electron mobility transistor (HEMT) , the method comprising:forming a second III-V compound layer on a first III-V compound layer, the second III-V compound layer and the first III-V compound layer differing in composition;forming a p-type doped region in the first III-V compound layer;forming an n-type doped region in the second III-V compound layer, the n-type doped region overlying the p-type doped region;forming a source feature over the second III-V compound layer, the source feature overlying the n-type doped region; andforming a gate electrode over the second III-V compound layer, the gate electrode disposed laterally adjacent to the source feature.2. The method of claim 1 , wherein the forming the second III-V compound layer on the first III-V compound layer comprises epitaxially growing the second III-V compound layer on the first III-V compound layer.3. The method of claim 1 , wherein the forming the p-type doped region comprises selectively implanting p-type dopants into the first III-V compound layer through the second first III-V compound layer.4. The method of claim 3 , wherein the p-type dopants comprise a Group II element.5. The method of claim 3 , wherein the p-type dopants comprise magnesium claim 3 , calcium claim 3 , beryllium or zinc.6. The method of ...

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Номер записи: 65
23-03-2017 дата публикации

CABLE CONNECTOR ASSEMBLY HAVING AN ILLUMINATION FUNCTION

Номер: US20170085041A1
Автор: Chen Chi-Ming, LI ZHI-YANG, ZHANG DE-GANG
Принадлежит:

A cable connector assembly includes a cable and a connector electrically connected with the cable for further electrically connecting with a power source. The connector includes: a main body; a plurality of contacts retained to the main body; a light emitting element; a first printed circuit board for controlling the light emitting element to emit light; and an outer case enclosing the connector and defining a conductive area; wherein the connector further includes a conducting member mounted on the first printed circuit board, the conducting member is a shrapnel made of metal material pressing upon the conductive area of the outer case, a front end of the outer case defines a transparent portion made of transparent material, and upon pressing the conductive area the light emitting element is turned on to emit light through the transparent portion. 1. A cable connector assembly comprising:a cable; and a main body;', 'a plurality of contacts retained to the main body;', 'a light emitting element;', 'a first printed circuit board for controlling the light emitting element to emit light; and', 'an outer case enclosing the connector and defining a conductive area; wherein, 'a connector electrically connected with the cable for further electrically connecting with a power source, the connector includingthe connector further includes a conducting member mounted on the first printed circuit board, the conducting member is a shrapnel made of metal material pressing upon the conductive area of the outer case, a front end of the outer case defines a transparent portion made of transparent material, and upon pressing the conductive area the light emitting element is turned on to emit light through the transparent portion.2. The cable connector assembly as described in claim 1 , wherein the connector comprises a second printed circuit board parallel to the first printed circuit board and electrically connected between the contacts of the connector and the cable.3. The cable ...

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Номер записи: 66
12-03-2020 дата публикации

SEMICONDUCTOR DEVICE HAVING DOPED SEED LAYER AND METHOD OF MANUFACTURING THE SAME

Номер: US20200083362A1
Автор: Chen Chi-Ming, Lee Ru-Liang, Liu Po-Chun, Tsai Chia-Shiung, Yu Chung-Yi
Принадлежит:

A semiconductor device includes a substrate. The semiconductor device includes an AlN seed layer in direct contact with the substrate. The AlN seed layer includes an AlN first seed sublayer, and an AlN second seed sublayer, wherein a portion of the AlN seed layer closest to the substrate includes carbon dopants and has a different lattice structure from a substrate lattice structure. The semiconductor device includes a graded layer in direct contact with the AlN seed layer. The graded layer includes a first graded sublayer including AlGaN, a second graded sublayer including AlGaN, and a third graded sublayer including AlGaN. The semiconductor device includes a channel layer over the graded layer. The semiconductor device includes an active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer. 1. A semiconductor device comprising:a substrate having a substrate lattice structure; an AlN first seed sublayer having a first lattice structure, and', 'an AlN second seed sublayer having a second lattice structure, the second lattice structure being different than the first lattice structure, wherein a portion of the AlN seed layer closest to the substrate comprises carbon dopants and has a different lattice structure from the substrate lattice structure;, 'an AlN seed layer in direct contact with the substrate, the AlN seed layer comprising a first graded sublayer including AlGaN, wherein the first graded sublayer has a first Al:Ga ratio;', 'a second graded sublayer including AlGaN, wherein the second graded sublayer has a second Al:Ga ratio different from the first Al:Ga ratio; and', 'a third graded sublayer including AlGaN, wherein the third graded sublayer has a third Al:Ga ratio different from each of the first Al:Ga ratio and the second Al:Ga ratio;, 'a graded layer in direct contact with the AlN seed layer, wherein the graded layer comprisesa channel layer over the graded layer; andan active layer over the channel ...

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Номер записи: 67
30-03-2017 дата публикации

High Electron Mobility Transistor and Method of Forming the Same

Номер: US20170092738A1
Автор: Chen Chi-Ming, CHIANG Chen-Hao, Chiu Han-Chin, Liu Po-Chun, Yu Chung-Yi
Принадлежит:

A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is smaller than the first band gap. The HEMT further includes a third III-V compound layer having a third band gap over the second III-V compound layer, wherein the third band gap is greater than the first band gap. A gate electrode is formed over the third III-V compound layer. A source region and a drain region are over the third III-V compound layer and on opposite sides of the gate electrode. 1. A method of forming a High Electron Mobility Transistor (HEMT) , the method comprising:epitaxially growing a first III-V compound layer having a first band gap;epitaxially growing a second III-V compound layer having a second band gap smaller than the first band gap over the first III-V compound layer;epitaxially growing a third III-V compound layer having a third band gap greater than the first band gap over the second III-V compound layer;forming a gate electrode over the third III-V compound layer; andforming a source region and a drain region over the third III-V compound layer and on opposite sides of the gate electrode.2. The method of claim 1 , wherein the second III-V compound layer is undoped or unintentionally doped during the step of epitaxially growing the second III-V compound layer.3. The method of further comprising:forming a dielectric passivation layer over and contacting the third III-V compound layer;patterning the dielectric passivation layer to form an opening, wherein a portion of the third III-V compound layer is exposed through the opening; anddepositing a gate dielectric layer, wherein the gate dielectric layer comprises a first portion extending into the opening, and a second portion overlapping the dielectric passivation layer.4. The method of claim 3 , wherein after the source region and the drain region are formed claim 3 , ...

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Номер записи: 68
03-07-2014 дата публикации

HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME

Номер: US20140183598A1
Автор: Chen Chi-Ming, Chiu Han-Chin, Tsai Chia-Shiung, Yu Chung-Yi
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A dielectric passivation layer is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer, and extend through the dielectric passivation layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. The gate electrode has an exterior surface. An oxygen containing region is embedded at least in the second III-V compound layer under the gate electrode. A gate dielectric layer has a first portion and a second portion. The first portion is under the gate electrode and on the oxygen containing region. The second portion is on a portion of the exterior surface of the gate electrode. 1. A high electron mobility transistor (HEMT) comprising:a first III-V compound layer;a second III-V compound layer disposed on the first III-V compound layer and different from the first III-V compound layer in composition;a dielectric passivation layer disposed on the second III-V compound layer;a source feature and a drain feature disposed on the second III-V compound layer, and extending through the dielectric passivation layer;a gate electrode disposed over the second III-V compound layer between the source feature and the drain feature, the gate electrode having an exterior surface;an oxygen containing region embedded at least in the second III-V compound layer under the gate electrode; anda gate dielectric layer comprising a first portion and a second portion, wherein the first portion is under the gate electrode and on the oxygen containing region, and the second portion is on a portion of the exterior surface of the gate electrode.2. The HEMT of claim 1 , wherein the oxygen containing region is embedded in the second III-V compound layer and a ...

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Номер записи: 69
26-03-2020 дата публикации

SIDEWALL PASSIVATION FOR HEMT DEVICES

Номер: US20200098889A1
Автор: Chen Chi-Ming, Chiu Han-Chin, TSAI Cheng-Yuan, YAO Fu-Wei
Принадлежит:

Some embodiments of the present disclosure relate to a HEMT. The HEMT includes a heterojunction structure having a second III/V semiconductor layer arranged over a first III/V semiconductor layer. Source and drain regions are arranged over the substrate and spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. A first passivation layer is disposed about sidewalls of the gate structure and extending over an upper surface of the gate structure, wherein the first passivation layer is made of a III-V material. A second passivation layer overlies the first passivation layer and made of a material composition different from a material composition of the first passivation layer. The second passivation layer has a thickness greater than that of the first passivation layer. 1. A high electron mobility transistor (HEMT) , comprising:a heterojunction structure arranged over a substrate, the heterojunction structure comprising: a first III/V semiconductor layer, and a second III/V semiconductor layer arranged over the first III/V semiconductor layer and made of a material composition different from a material composition of the first III/V semiconductor layer;source and drain regions arranged over the substrate and spaced apart laterally from one another;a gate structure arranged over the heterojunction structure and arranged between the source and drain regions;a first passivation layer disposed about sidewalls of the gate structure and extending over an upper surface of the gate structure, wherein the first passivation layer is made of a III-V material; anda second passivation layer overlying the first passivation layer and made of a material composition different from a material composition of the first passivation layer;wherein the second passivation layer has a thickness greater than that of the first passivation layer.2. The HEMT of claim 1 , wherein the first passivation ...

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Номер записи: 70
21-04-2016 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING A BARRIER STRUCTURE

Номер: US20160111520A1
Автор: Chen Chi-Ming, Chen Xiaomeng, CHIANG Chen-Hao, Liu Po-Chun, Tsai Chia-Shiung, Yu Chung-Yi
Принадлежит:

A method of manufacturing a semiconductor device includes forming a barrier structure over a substrate. The method further includes forming a channel layer over the barrier structure. The method further includes depositing an active layer over the channel layer. The method further includes forming source/drain electrodes over the channel layer. The method further includes annealing the source/drain electrodes to form ohmic contacts in the active layer under the source/drain electrodes. 1. A method of manufacturing a semiconductor device , the method comprising:forming a barrier structure over a substrate;forming a channel layer over the barrier structure;depositing an active layer over the channel layer;forming source/drain electrodes over the channel layer; andannealing the source/drain electrodes to form ohmic contacts in the active layer under the source/drain electrodes.2. The method of claim 1 , wherein forming the barrier structure comprises:forming a first barrier layer over the substrate;forming a buffer layer over the first barrier layer; andforming a second barrier layer over the buffer layer.3. The method of claim 2 , wherein forming the barrier structure comprises forming at least one of the first barrier layer or the second barrier layer comprising at least one material selected from the group consisting of SiC claim 2 , SiCNand BN.4. The method of claim 2 , wherein forming the buffer layer comprises forming the buffer layer comprising the p-type dopant.5. The method of claim 4 , wherein forming the buffer layer comprises forming the buffer layer comprising at least one element selected from the group consisting of C claim 4 , Fe claim 4 , Mg and Zn.6. The method of claim 2 , wherein forming the first barrier layer comprises forming the first barrier layer over the substrate comprises a Si substrate claim 2 , forming the buffer layer comprises forming the buffer layer comprising GaN doped with C claim 2 , and forming the channel layer comprises forming ...

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Номер записи: 71
11-04-2019 дата публикации

Mouse device

Номер: US20190107900A1
Автор: Chi-Ming Tseng, Chin-Chung Lin
Принадлежит: Cheng Uei Precision Industry Co Ltd

A mouse device includes at least one electronic switch and at least one button module. The at least one electronic switch includes a switch assembly, and a lower magnet mounted to the switch assembly. The at least one electronic switch is disposed under the at least one button module. A bottom surface of the at least one button module is equipped with an upper magnet disposed over a top of the lower magnet. Magnetic poles of the top of the lower magnet and a bottom of the upper magnet are the same. When the at least one button module is pressed downward, the lower magnet drives the switch assembly to convert a switch-off state into a switch-on state by virtue of a repelling force of the upper magnet pushing against the lower magnet, so that the at least one electronic switch is triggered.

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Номер записи: 72
28-04-2016 дата публикации

CABLE CONNECTOR ASSEMBLY WITH IMPROVED LUMINOUS EFFECT

Номер: US20160118755A1
Автор: Chen Chi-Ming, LI ZHI-YANG, ZHANG DE-GANG
Принадлежит:

A cable connector assembly () comprises: a first connector () having a main body (), a number of contacts () retained in the main body, a first circuit board () electrically connected to the contacts, and a metal shell () enclosing the first circuit board; a cable () electrically connected between the first circuit board and a power source to provide a power to the first circuit board; a second circuit board () vertically fixed on the metal shell; a cover enclosing the first and the second circuit board; a luminous element () disposed on a front side of the second circuit board and electrically connected to the first circuit board; and a translucent portion () defined on a front end of the cover to pass light emitted by the luminous element. 1. A cable connector assembly comprising:a first connector having a main body, a plurality of contacts retained in the main body, a first circuit board electrically connected to the contacts, and a metal shell enclosing the first circuit board;a cable electrically connected between the first circuit board and a power source to provide a power to the first circuit board;a second circuit board vertically fixed on the metal shell;a cover enclosing the first and the second circuit boards;a luminous element disposed on a front side of the second circuit board and electrically connected to the first circuit board; anda translucent portion defined on a front end of the cover to pass the light emitted by the luminous element.2. The cable connector assembly as recited in claim 1 , wherein the cover includes a tubular portion and a front plate portion fixed on a front end of the tubular portion claim 1 , and the translucent portion is defined on the front plate portion or forms the entire front plate portion.3. The cable connector assembly as recited in claim 2 , wherein:the tubular portion encloses the first circuit board, the main body, and the second circuit board;the cable is exposed from a rear opening of the tubular portion;the ...

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Номер записи: 73
17-07-2014 дата публикации

SEMICONDUCTOR STRUCTURE HAVING SETS OF III-V COMPOUND LAYERS AND METHOD OF FORMING THE SAME

Номер: US20140197418A1
Автор: Chen Chi-Ming, Liu Po-Chun, Tsai Chia-Shiung, Yu Chung-Yi
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A semiconductor structure includes a substrate, a first III-V compound layer over the substrate, one or more sets of III-V compound layers over the first III-V compound layer, a second III-V compound layer over the one or more sets of III-V compound layers, and an active layer over the second III-V compound layer. The first III-V compound layer has a first type doping. Each of the one or more sets of III-V compound layers includes a lower III-V compound layer and an upper III-V compound layer over the lower III-V compound layer. The upper III-V compound layer having the first type doping, and the lower III-V compound layer is at least one of undoped, unintentionally doped having a second type doping, or doped having the second type doping. The second III-V compound layer is either undoped or unintentionally doped having the second type doping. 1. A semiconductor structure , comprising:a substrate;a first III-V compound layer over the substrate, the first III-V compound layer having a first type doping;one or more sets of III-V compound layers over the first III-V compound layer, each of the one or more sets of III-V compound layers comprising a lower III-V compound layer and an upper III-V compound layer over the lower III-V compound layer, the upper III-V compound layer having the first type doping, and the lower III-V compound layer being at least one of undoped, unintentionally doped having a second type doping, or doped having the second type doping;a second III-V compound layer over the one or more sets of III-V compound layers, the second III-V compound layer being either undoped or unintentionally doped having the second type doping; andan active layer over the second III-V compound layer.2. The semiconductor structure of claim 1 , wherein the first type doping is P-type doping claim 1 , and the second type doping is N-type doping.3. The semiconductor structure of claim 2 , wherein the first type doping is implemented by dopants including carbon claim 2 , ...

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Номер записи: 74
27-05-2021 дата публикации

FLEXIBLE SPLICE PROTECTOR ASSEMBLY AND METHOD FOR PREPARING SAME

Номер: US20210157055A1
Автор: Elnatour Ibrahim M., Wang Chi Ming
Принадлежит:

A method of protecting a fusion splice of first and second fiber optic cables includes: 1. An assembly , comprising:first and second fiber optic cables, each of the first and second fiber optic cables including an exposed portion of an optical fiber and an overlying jacket, wherein the optical fiber of the first fiber optic cable is fusion spliced to the optical fiber of the second fiber optic cable to form a splice area;a splice protector that surrounds the splice area of the first and second fiber optic cables;a lower shell member;an upper shell member that overlies the lower channel to form a shell with a cavity therein; anda member formed of activatable material residing in the upper shell member within the cavity;wherein the splice protector and the exposed portions of optical fibers of the first and second fiber optic cables reside in the cavity.2. The assembly defined in claim 1 , wherein the member of activatable material is melted and at least partially covers the splice protector.3. The assembly defined in claim 1 , wherein the activatable material comprises a material that is activatable by heat.4. The assembly defined in claim 3 , wherein the activatable material comprises a hot melt adhesive.5. The assembly defined in claim 1 , wherein the lower shell member comprises a channel.6. The assembly defined in claim 5 , wherein the upper shell member comprises a channel.7. An assembly claim 5 , comprising:first and second fiber optic cables, each of the first and second fiber optic cables including an exposed portion of an optical fiber and an overlying jacket, wherein the optical fiber of the first fiber optic cable is fusion spliced to the optical fiber of the second fiber optic cable to form a splice area;a splice protector that surrounds the splice area of the first and second fiber optic cables;a lower channel having side walls that define a gap;an upper member formed of activatable material positioned in the gap in the lower channel, the upper member ...

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Номер записи: 75
31-07-2014 дата публикации

Thick ALN Inter-Layer for III-Nitride Layer on Silicon Substrate

Номер: US20140209918A1
Автор: Chen Chi-Ming, Liu Po-Chun, Yu Chung-Yi
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure relates to a gallium-nitride (GaN) transistor device having a composite gallium nitride layer with alternating layers of GaN and aluminum nitride (AlN). In some embodiments, the GaN transistor device has a first GaN layer disposed above a semiconductor substrate. An AlN inter-layer is disposed on the first GaN layer. A second GaN layer is disposed on the AlN inter-layer. The AlN inter-layer allows for the thickness of the GaN layer to be increased over continuous GaN layers, mitigating bowing and cracking of the GaN substrate, while improving the breakdown voltage of the disclosed GaN device. 1. A gallium nitride (GaN) semiconductor device , comprising:a first gallium nitride (GaN) layer disposed above a semiconductor substrate;a first aluminum nitride (AlN) inter-layer disposed onto the first GaN layer;a second gallium nitride (GaN) layer disposed onto the first AlN inter-layer;an active layer disposed onto the second GaN layer;a source region abutting a top surface of the second GaN layer and further abutting a first sidewall of the active layer;a drain region abutting the top surface of the second GaN layer and further abutting a second sidewall of the active layer opposite the first sidewall; anda gate region located above the active layer at a position between the source region and the drain region.2. The GaN semiconductor device of claim 1 , further comprising:an aluminum nitride (AlN) nucleation layer disposed between the semiconductor substrate and the first GaN layer.3. The GaN semiconductor device of claim 2 , further comprising:a graded aluminum gallium nitride (AlGaN) layer disposed between the AlN nucleation layer and the first GaN layer, wherein the graded AlGaN layer has an aluminum concentration that varies as a function of position.4. The GaN semiconductor device of claim 1 , further comprising:a second aluminum nitride (AlN) inter-layer disposed onto the second gallium nitride (GaN) layer; anda third gallium nitride (GaN) ...

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Номер записи: 76
31-07-2014 дата публикации

METHOD OF IMPLANTING DOPANTS INTO A GROUP III-NITRIDE STRUCTURE AND DEVICE FORMED

Номер: US20140209919A1
Автор: Chen Chi-Ming, CHIANG Chen-Hao, Chiu Han-Chin, Yu Chung-Yi
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopant and a second dopant, and the second dopant comprises a group V material. 1. A method of forming a semiconductor device , the method comprising:forming a III-V compound layer on a substrate;implanting a main dopant into the III-V compound layer to form source and drain regions; andimplanting a group V species within the source and drain regions.2. The method of claim 1 , further comprising performing an annealing process to activate the combination of dopants and group V species in the source and drain regions.3. The method of claim 2 , wherein performing the annealing process comprises performing the annealing process at a temperature ranging from about 800° C. to about 1200° C.4. The method of claim 1 , wherein implanting the main dopants comprises implanting at least one of silicon claim 1 , magnesium claim 1 , beryllium claim 1 , calcium claim 1 , zinc claim 1 , germanium or sulfur.5. The method of claim 1 , wherein implanting the group V species comprises implanting the group V species in a ratio of the main dopants to the group V species ranging from about 1 claim 1 ,000:1 to about 10:1.6. The method of claim 1 , further comprising forming source and drain contacts electrically connected to the source and drain regions.7. The method of claim 6 , wherein forming the source and drain contacts comprises forming an ohmic contact with the source and drain regions.8. The method of claim 1 , further comprising:forming a capping layer over the source and drain regions; andforming a gate ...

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Номер записи: 77
31-07-2014 дата публикации

High Electron Mobility Transistor Structure

Номер: US20140209920A1
Автор: Chen Chi-Ming, Liu Po-Chun, Tsai Chia-Shiung, Yu Chung-Yi
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure relates to a channel layer of bi-layer of gallium nitride (GaN) within a HEMT. A first breakdown voltage layer of GaN is disposed beneath an active layer of the HEMT. A second breakdown voltage layer of GaN is disposed beneath the first breakdown voltage layer, wherein the first resistivity value is less than the second resistivity value. An increased resistivity of the second breakdown voltage layer results from an increased concentration of carbon dopants which increases the breakdown voltage in the second breakdown voltage layer, but can degrade the crystal structure. To alleviate this degradation, a crystal adaptation layer is disposed beneath the second breakdown voltage layer and configured to lattice-match to the second breakdown voltage layer of GaN. As a result, the HEMT achieves a high breakdown voltage without any associated degradation to the first breakdown voltage layer, wherein a channel of the HEMT resides. 18-. (canceled)9. A high electron mobility transistor (HEMT) , comprising:a first breakdown voltage layer comprising a first resistivity value, wherein the first breakdown voltage layer exhibits a first lattice-constant and is doped with a first dopant at a first doping concentration;a second breakdown voltage layer disposed beneath the first breakdown voltage layer and comprising a second resistivity value that is greater than, the first resistivity value, wherein the second breakdown voltage layer exhibits a second lattice-constant that is substantially equal to the first lattice-constant and is doped with a second dopant at a second doping concentration that is greater than the first doping concentration; anda crystal adaptation layer disposed beneath the second breakdown voltage layer, wherein the crystal adaptation layer exhibits a third lattice-constant which is substantially equal to each of the first and second lattice-constants; and wherein the crystal adaptation layer is doped with a third dopant at a third doping ...

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Номер записи: 78
11-05-2017 дата публикации

LASER POINTER

Номер: US20170130913A1
Автор: Chen Chi-Ming, Jiang Hao, ZHANG DE-GANG
Принадлежит:

A laser pointer includes a case (), a laser module (), a printed circuit board assembly () and a charging connector (). The case () includes a lighting end () at a front end thereof, a mounting port () at a rear end thereof, a receiving cavity between the lighting end and the mounting port, and an inner wall (). The laser module () and the printed circuit board assembly () are received in the receiving cavity (). The printed circuit board assembly connects with the rear side of the laser module (). The charging connector () mounted on the rear end of the printed circuit board assembly () electrically connects to the laser module () through the printed circuit board assembly (). 1. A laser pointer comprising:a case including a lighting end at a front end thereof, a mounting port at a rear end thereof, a receiving cavity between the lighting end and the mounting port, and an inner wall;a laser module received in the receiving cavity;a printed circuit board assembly received in the receiving cavity and connecting to the rear side of the laser module; anda charging connector mounted on the rear end of the printed circuit board assembly; whereinthe charging connector electrically connects to the laser module through the printed circuit board assembly and is adapted to supply an external power to the laser module.2. The laser pointer as claimed in claim 1 , wherein the laser pointer includes a touch sensing plate located between the inner wall and the printed circuit board assembly.3. The laser pointer as claimed in claim 2 , wherein the touch sensing plate includes a main board claim 2 , a contact plate upwardly extending from the main board claim 2 , and a plurality of connection pins downwardly extending from the main board claim 2 , the contact plate being curved and fitting the inner wall claim 2 , the plurality of connection pin being fixedly connected with the printed circuit board assembly.4. The laser pointer as claimed in claim 2 , wherein the printed circuit ...

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Номер записи: 79
02-05-2019 дата публикации

METHOD OF IMPLANTING DOPANTS INTO A GROUP III-NITRIDE STRUCTURE AND DEVICE FORMED

Номер: US20190131416A1
Автор: Chen Chi-Ming, CHIANG Chen-Hao, Chiu Han-Chin, Yu Chung-Yi
Принадлежит:

A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material. 1. A method comprising:depositing a first III-V compound layer on a substrate;depositing a second III-V compound layer over the first III-V compound layer, the second III-V compound layer having a higher bandgap than the first III-V compound layer; andimplanting a first dopants and a group V species into the first III-V compound layer and the second III-V compound layer to define a source/drain region extending through the second III-V compound layer into the first III-V compound layer, wherein a region of the source/drain region below a bottommost surface of the second III-V compound layer comprises the group V species as a result of implanting the group V species into the first III-V compound layer.2. The method of claim 1 , wherein implanting the first dopants and the group V species into the first III-V compound layer and the second III-V compound layer comprises simultaneously implanting the first dopants and the group V species.3. The method of claim 1 , wherein implanting the first dopants and the group V species into the first III-V compound layer and the second III-V compound layer comprises implanting the first dopants before implanting the group V species.4. The method of claim 1 , wherein implanting the first dopants and the group V species into the first III-V compound layer and the second III-V compound layer comprises implanting the first dopants after implanting the group V species.5. The method of ...

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Номер записи: 80
28-05-2015 дата публикации

WIRE-WINDING DEVICE

Номер: US20150144728A1
Автор: Chen Chi-Ming, YANG KAI-FENG, Zhou Feng
Принадлежит:

A wire-winding device comprising: an upper cover; a spiral spring; a rotary base having a groove to accommodate the spiral spring on the bottom surface thereof; a transmission line winding around the rotary base; a lower cover assembled with the upper cover; and a pillar, an outlet, and a wire casing formed on one side of the groove, and two spacers surrounding the peripheral edge of the groove, the pillar having a first end portion which shifts outward to the edge of rotary base, the wire casing having a smooth curved surface formed on the bottom surface thereof near the outlet to enlarge the accommodating space near the outlet and reduce the friction between the transmission line and the spacers. 1. A wire-winding device comprising:an upper cover;a spiral spring;a rotary base having a groove to accommodate the spiral spring on the bottom surface thereof;a transmission line winding around the rotary base;a lower cover assembled with the upper cover; anda pillar, an outlet, and a wire casing formed on one side of the groove, and two spacers surrounding the peripheral edge of the groove, the pillar having a first end portion which shifts outward to the edge of rotary base, the wire casing having a smooth curved surface formed on the bottom surface thereof near the outlet to enlarge the accommodating space near the outlet and reduce the friction between the transmission line and the spacers.2. The wire-winding device as claimed in claim 1 , further having a decorative piece claim 1 , and wherein the upper cover has a circular groove formed on the upper surface claim 1 , and the decorative piece is accommodated in the circular groove of the upper cover.3. The wire-winding device as claimed in claim 1 , wherein the wire-winding device further having an elastic positioning element having a base and a positioning part extruding from the lower surface of the base claim 1 , the base having an elastic part and a respective fixed part at each of two ends thereof claim 1 , the ...

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Номер записи: 81
28-05-2015 дата публикации

WIRE-WINDING DEVICE

Номер: US20150144729A1
Автор: Chen Chi-Ming, YANG KAI-FENG
Принадлежит:

A wire-winding device comprising: an upper cover having a bottom surface and a slot deviating from a center of the bottom surface; a rotary base having an annular track on a top surface thereof, the annual track and the slot of the upper cover constituting an orbit; a spiral spring received in the rotary base; a transmission line winding around the rotary base; a lower cover assembled with the upper cover; and an elastic positioning element having a base and a positioning part extruding from the lower surface of the base, the base having an elastic part and a respective fixed part at each of two ends thereof, the elastic positioning element being moveable along the orbit in response to a rotational movement of the rotary base to avoid the transmission line to be tied a knot. 1. A wire-winding device comprising:an upper cover having a bottom surface and a slot deviating from a center of the bottom surface;a rotary base having an annular track on a top surface thereof, the annual track and the slot of the upper cover constituting an orbit;a spiral spring received in the rotary base;a transmission line winding around the rotary base;a lower cover assembled with the upper cover; andan elastic positioning element having a base and a positioning part extruding from the lower surface of the base, the base having an elastic part and a respective fixed part at each of two ends thereof, the elastic positioning element being moveable along the orbit in response to a rotational movement of the rotary base.2. The wire-winding device as claimed in claim 1 , wherein the base of the elastic positioning element is accommodated in the slot of the lower surface of the upper cover claim 1 , and the positioning part of the elastic positioning element is accommodated in the annual track of the rotary base.3. The wire-winding device as claimed in claim 1 , wherein the rotary base has a groove on the lower surface thereof for accommodating the spiral spring claim 1 , the groove having a ...

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Номер записи: 82
10-06-2021 дата публикации

FLEXIBLE SPLICE PROTECTOR ASSEMBLY AND METHOD FOR PREPARING SAME

Номер: US20210173146A1
Автор: Elnatour Ibrahim M., Wang Chi Ming
Принадлежит:

An assembly includes: first and second fiber optic cables, each of the first and second fiber optic cables including an exposed portion of an optical fiber and an overlying jacket, wherein the optical fiber of the first fiber optic cable is fusion spliced to the optical fiber of the second fiber optic cable to form a splice area; a splice protector that surrounds the splice area of the first and second fiber optic cables; a flexible tube that encircles the splice protector, the exposed portions of the first and second fiber optic cables, and end portions of the jackets of the first and second fiber optic cables, wherein the splice protector, the exposed portions of optical fibers of the first and second fiber optic cables reside in a lumen of the flexible tube; first and second adhesive barriers positioned between an inner surface of the flexible tube and the end portions of the first and second fiber optic cables, respectively; and an outer sleeve that circumferentially overlies the flexible tube and portions of the jackets of the first and second fiber optic cables. 1. An assembly , comprising:first and second fiber optic cables, each of the first and second fiber optic cables including an exposed portion of an optical fiber and an overlying jacket, wherein the optical fiber of the first fiber optic cable is fusion spliced to the optical fiber of the second fiber optic cable to form a splice area;a splice protector that surrounds the splice area of the first and second fiber optic cables;a flexible tube that encircles the splice protector, the exposed portions of the first and second fiber optic cables, and end portions of the jackets of the first and second fiber optic cables;wherein the splice protector, the exposed portions of optical fibers of the first and second fiber optic cables reside in a lumen of the flexible tube;first and second adhesive barriers positioned between an inner surface of the flexible tube and the end portions of the first and second ...

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Номер записи: 83
26-05-2016 дата публикации

CABLE CONNECTOR ASSEMBLY WITH IMPROVED INDICATION EFFECT

Номер: US20160149353A1
Автор: Chen Chi-Ming, LI ZHI-YANG, ZHANG DE-GANG
Принадлежит:

A cable connector assembly () includes: a cable () having a number of inner wires; a first connector () including a main body (), plural contacts () retained in the main body, a first circuit board (), a luminous element (), and a cover; and a second circuit board () assembled on a rear end of the first circuit board and getting power and grounding source from the first circuit board. The second circuit board includes a detection contact () electrically connected to an inner wire of the cable, and a chip () electrically connected respectively to the luminous element and the detection contact. The chip detects a voltage difference between the power source and the first connector. A light is emitted by the luminous element passing through the cover to indicate a charging status of the charging device. 1. A cable connector assembly comprising:a cable having a number of inner wires, a end of the cable adapted to connect to a power source for receiving a power signal and a grounding signal;a first connector including a main body, a plurality of contacts retained in the main body, a first circuit board assembled on a rear end of the main body and electrically connected with the contacts and the cable, a luminous element, and a cover enclosing the main body and the first circuit board; anda second circuit board assembled on a rear end of the first circuit board and getting power and grounding source from the first circuit board, the second circuit board comprising a chip and a detection contact, the detection contact electrically connected to an inner wire of the cable, the chip electrically connected respectively to the luminous element and the detection contact, the chip detecting a voltage difference between the power source and the first connector when mating with a charging device and changing a lighting mode of the luminous element according to the voltage difference, a light emitted by the luminous element passing through the cover to indicate a charging status of ...

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Номер записи: 84
09-05-2019 дата публикации

SEMICONDUCTOR STRUCTURE AND ASSOCIATED MANUFACTURING METHOD

Номер: US20190139949A1
Автор: Chen Chi-Ming, Lin Yeong-Jyh, Liu Ping-Yin
Принадлежит:

A semiconductor structure is disclosed. The semiconductor structure includes: a first light-emitting diode (LED) layer including a first LED of a first color type, the first LED layer having a first side and a second side opposite to the first side; a second LED layer over the first LED layer, the second LED layer including a second LED of a second color type, and the second LED layer having a first side and a second side opposite to the first side; and a third LED layer over the second LED layer, the third LED layer including a third LED of a third color type, and the third LED layer having a first side and a second side opposite to the first side; wherein the first color type, the second color type, and the third color type are different from each other. 1. A semiconductor structure , comprising:a first light-emitting diode (LED) layer including a first LED of a first color type, the first LED layer having a first side and a second side opposite to the first side;a second LED layer over the first LED layer, the second LED layer including a second LED of a second color type, and the second LED layer having a first side and a second side opposite to the first side;a third LED layer over the second LED layer, the third LED layer including a third LED of a third color type, and the third LED layer having a first side and a second side opposite to the first side; anda transparent filling over the first LED layer, the second LED layer and the third LED layer, wherein a distance between a top surface of the transparent filling and the second side of the first LED layer is greater than a distance between the top surface of the transparent filling and the second side of the second LED layer, and the distance between the top surface of the transparent filling and the second side of the second LED layer is greater than a distance between the top surface of the transparent filling and the second side of the third LED layer;wherein the first color type, the second color type, ...

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Номер записи: 85
09-05-2019 дата публикации

Charging method, charging system and electronic device

Номер: US20190140456A1
Автор: Chi-Ming Lee, Chih-Yuan Hsu, Shih-Ming Chen
Принадлежит: MediaTek Inc

A charging method, a charging system and an electronic device are provided. The charging method includes the following steps: An inputting current limit is set. An inputting current of at least one charger is measured. A power source voltage of a power source is adjusted until a current difference between the inputting current and the inputting current limit is within a predetermined range.

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Номер записи: 86
21-08-2014 дата публикации

HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME

Номер: US20140231816A1
Автор: Chen Chi-Ming, Chiu Han-Chin, Liu Po-Chun, Wong King-Yuen, Yu Chung-Yi
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is greater than the first band gap. A crystalline interfacial layer is overlying and in contact with the second III-V compound layer. A gate dielectric is over the crystalline interfacial layer. A gate electrode is over the gate dielectric. A source region and a drain region are over the second III-V compound layer, and are on opposite sides of the gate electrode. 1. A High Electron Mobility Transistor (HEMT) comprising:a first III-V compound layer having a first band gap;a second III-V compound layer having a second band gap over the first III-V compound layer, wherein the second band gap is greater than the first band gap;a crystalline interfacial layer over and in contact with the second III-V compound layer;a gate dielectric over the crystalline interfacial layer;a gate electrode over the gate dielectric; anda source region and a drain region over the second III-V compound layer and on opposite sides of the gate electrode.2. The HEMT of claim 1 , wherein the first III-V compound layer and the second III-V compound layer are configured so that a Two-Dimensional Electron Gas (2DEG) is formed in the first III-V compound layer and close to an interface between the first III-V compound layer and the second III-V compound layer.3. The HEMT of claim 1 , wherein the crystalline interfacial layer is a dielectric layer.4. The HEMT of claim 1 , wherein the crystalline interfacial layer is a semiconductor layer.5. The HEMT of claim 1 , wherein the gate electrode claim 1 , the gate dielectric claim 1 , and the crystalline interfacial layer are co-terminus claim 1 , with edges of the crystalline interfacial layer aligned to respective edges of the gate electrode and the gate dielectric.6. The HEMT of claim 1 , wherein the crystalline interfacial layer ...

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Номер записи: 87
07-05-2020 дата публикации

EQUIPMENT CHECKING SYSTEM AND DEVICE HAVING THE SAME

Номер: US20200142556A1
Автор: Chang Chi-Yuan, HU SHU-BING, Lin Chi-Ming
Принадлежит:

A device for checking aspects of equipment includes a display screen, a memory, a processor, and an equipment checking system in a computer. The system includes a control unit and a checklist generating unit. The display screen can display a checking interface of an equipment. The checking interface includes item information of items for checking corresponding to the equipment, a data inputting area, and first and second confirmation icons. Data arising from inspections and checks can be input into the data inputting area. The checklist generating unit generates a checklist of all items for checking and checks carried out in response to an operation on the first confirmation icon. The checklist includes information as to an equipment, data as to checks required, and data as to results of checks carried out. 1. An equipment checking system executed to:control a display screen to display a checking interface of an equipment, the checking interface comprising item information of at least one checking item corresponding to the equipment, a checking data inputting area and a first confirmation icon, the checking data inputting area configured to input a checking data which is acquired when the checking item of the equipment is checked; andgenerate a checklist of all the checking item having been checked in response to an operation on the first confirmation icon, the checklist comprising an equipment information of the equipment and the checking data of the checking item.2. The equipment checking system of claim 1 , wherein the equipment checking system is further executed to identify the equipment information of the equipment according to an equipment identity tag corresponding to the equipment approached an equipment checking device and record time information when the equipment information is identified claim 1 , the item information is corresponding to the checking item of the equipment identified claim 1 , the checklist comprises the time information.3. The equipment ...

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Номер записи: 88
11-06-2015 дата публикации

POSITIVE-TYPE PHOTOSENSITIVE RESIN COMPOSITION, PATTERN FORMING METHOD, THIN FILM TRANSISTOR ARRAY SUBSTRATE, AND LIQUID CRYSTAL DISPLAY DEVICE

Номер: US20150160554A1
Автор: Liu Chi-ming, Shih Chun-An
Принадлежит:

A positive-type photosensitive resin composition, a pattern forming method, a thin film transistor array substrate, and a liquid crystal display device are provided. The positive-type photosensitive resin includes a novolac resin (A), an alkali-soluble resin (B), an ester (C) of an o-naphthoquinone diazide sulfonic acid, and a solvent (D). The alkali-soluble resin (B) includes a first alkali-soluble resin (B-1) produced by polymerizing a mixture. The mixture includes an epoxy compound (i) and a compound (ii), wherein the epoxy compound (i) has at least two epoxy groups, and the compound (ii) has at least one carboxylic acid group and at least one ethylenically unsaturated group. 1. A positive-type photosensitive resin composition , comprising:a novolac resin (A);an alkali-soluble resin (B);an ester (C) of an o-naphthoquinone diazide sulfonic acid; anda solvent (D);wherein the alkali-soluble resin (B) contains a first alkali-soluble resin (B-1), the first alkali-soluble resin (B-1) is produced by performing a polymerization on a mixture; the mixture contains an epoxy compound (i) and a compound (ii), the epoxy compound (i) has at least two epoxy groups, and the compound (ii) has at least one carboxylic acid group and at least one ethylenically unsaturated group.4. The positive-type photosensitive resin composition of claim 1 , wherein based on 100 parts by weight of the novolac resin (A) claim 1 , a usage quantity of the alkali-soluble resin (B) is 5 parts by weight to 50 parts by weight claim 1 , a usage quantity of the ester (C) of an o-naphthoquinone diazide sulfonic acid is 5 parts by weight to 50 parts by weight claim 1 , and a usage quantity of the solvent (D) is 100 parts by weight to 1000 parts by weight; and based on a usage quantity of 100 parts by weight of the alkali-soluble resin (B) claim 1 , a usage quantity of the first alkali-soluble resin (B-1) is 30 parts by weight to 100 parts by weight.5. The positive-type photosensitive resin composition of ...

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Номер записи: 89
31-05-2018 дата публикации

High Electron Mobility Transistor and Method of Forming the Same

Номер: US20180151692A1
Автор: Chen Chi-Ming, Chiu Han-Chin, Tsai Chia-Shiung, Yu Chung-Yi
Принадлежит:

A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A dielectric passivation layer is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer, and extend through the dielectric passivation layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. The gate electrode has an exterior surface. An oxygen containing region is embedded at least in the second III-V compound layer under the gate electrode. A gate dielectric layer has a first portion and a second portion. The first portion is under the gate electrode and on the oxygen containing region. The second portion is on a portion of the exterior surface of the gate electrode. 1. A method of forming a transistor , the method comprising:epitaxially growing a second semiconductor layer on a first semiconductor layer;forming a dielectric layer on the second semiconductor layer, a first portion of the second semiconductor layer being exposed;oxidizing the first portion of the second semiconductor layer, thereby forming an oxidized portion of the second semiconductor layer;depositing a gate dielectric layer on the oxidized portion of the second semiconductor layer;forming a gate electrode on the gate dielectric layer and over the oxidized portion of the second semiconductor layer; andafter forming the gate electrode, forming a source feature and a drain feature on the second semiconductor layer, the source feature and the drain feature extending through the dielectric layer to the second semiconductor layer.2. The method of claim 1 , wherein the first semiconductor layer is a first III-V compound.3. The method of claim 2 , wherein the second semiconductor layer is a second III-V compound.4. The method of claim 1 , wherein the gate ...

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Номер записи: 90
17-06-2021 дата публикации

Method of Implanting Dopants into a Group III-Nitride Structure and Device Formed

Номер: US20210184011A1
Автор: Chen Chi-Ming, CHIANG Chen-Hao, Chiu Han-Chin, Yu Chung-Yi
Принадлежит:

A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material. 1. A method comprising:depositing a first III-V compound layer on a substrate;depositing a second III-V compound layer over the first III-V compound layer, the second III-V compound layer having a higher bandgap than the first III-V compound layer; andimplanting a first dopants and a group V species into the first III-V compound layer and the second III-V compound layer to define a source/drain region extending through the second III-V compound layer into the first III-V compound layer, wherein a region of the source/drain region below a bottommost surface of the second III-V compound layer comprises the group V species.2. The method of claim 1 , wherein implanting the first dopants and the group V species into the first III-V compound layer and the second III-V compound layer comprises simultaneously implanting the first dopants and the group V species.3. The method of claim 1 , wherein implanting the first dopants and the group V species into the first III-V compound layer and the second III-V compound layer comprises implanting the first dopants before implanting the group V species.4. The method of claim 1 , wherein implanting the first dopants and the group V species into the first III-V compound layer and the second III-V compound layer comprises implanting the first dopants after implanting the group V species.5. The method of further comprising performing an annealing process to activate the first dopants ...

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Номер записи: 91
28-08-2014 дата публикации

HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME

Номер: US20140239306A1
Автор: Chen Chi-Ming, Liu Po-Chun, Yu Chung-Yi
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A fluorine region is embedded in the second III-V compound layer under the gate electrode. A diffusion barrier layer is disposed on top of the second III-V compound layer. A gate dielectric layer is disposed over the second III-V compound layer. The gate dielectric layer has a fluorine segment on the fluorine region and under at least a portion of the gate electrode. 1. A semiconductor structure comprising:a first III-V compound layer;a second III-V compound layer disposed on the first III-V compound layer and different from the first III-V compound layer in composition, wherein a carrier channel is located between the first III-V compound layer and the second III-V compound layer;a source feature and a drain feature disposed on the second III-V compound layer;a gate electrode disposed over the second III-V compound layer between the source feature and the drain feature, wherein a fluorine region is embedded in the second III-V compound layer under the gate electrode;a third III-V compound layer disposed over the second III-V compound layer, wherein a diffusion barrier layer is located between the second III-V compound layer and the third III-V compound layer; anda gate dielectric layer disposed over portions of the second III-V compound layer and over an entire top surface of the third III-V compound layer.2. The semiconductor structure of claim 1 , wherein the carrier channel under the gate electrode comprises a depletion region.3. The semiconductor ...

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Номер записи: 92
28-08-2014 дата публикации

POSITIVE PHOTOSENSITIVE RESIN COMPOSITION AND METHOD FOR FORMING PATTERNS BY USING THE SAME

Номер: US20140242504A1
Автор: Liu Chi-ming, Shih Chun-An
Принадлежит: CHI MEI CORPORATION

The present invention relates to a positive photosensitive resin composition and a method for forming patterns by using the same. The positive photosensitive resin composition includes a novolac resin (A), an ortho-naphthoquinone diazide sulfonic acid ester (B), a hydroxycompound (C) and a solvent (D). The novolac resin (A) further includes a hydroxy-type novolac resin (A-1) and a xylenol-type novolac resin (A-2). The hydroxy-type novolac resin (A-1) is synthesized by condensing hydroxyl benzaldehyde compound with aromatic hydroxyl compound. The xylenol-type novolac resin (A-2) is synthesized by condensing aldehyde compound with xylenol compound. The postbaked positive photosensitive resin composition can be beneficially formed to patterns with high film thickness and well cross-sectional profile. 1. A positive photosensitive resin composition , comprising:novolac resin (A), wherein the novolac resin (A) comprises hydroxy-type novolac resin (A-1) and xylenol-type novolac resin (A-2), the hydroxy-type novolac resin (A-1) is formed by condensing hydroxyl benzaldehyde compound with aromatic hydroxyl compound, and the xylenol-type novolac resin (A-2) is synthesized by condensing aldehyde compound with xylenol compound;ortho-naphthoquinone diazide sulfonic acid ester (B);a hydroxycompound (C); anda solvent (D).2. The positive photosensitive resin composition of claim 1 , wherein the ortho-naphthoquinone diazide sulfonic acid ester (B) comprises hydroxybenzophenone and/or hydroxyaryl compound and/or (hydroxyphenyl) hydrocarbon compound.3. The positive photosensitive resin composition of claim 1 , wherein the hydroxycompound (C) comprises hydroxybenzophenone and/or hydroxyaryl compound and/or (hydroxyphenyl) hydrocarbon compound.4. The positive photosensitive resin composition of claim 1 , wherein based on an amount of the novolac resin (A) as 100 parts by weight claim 1 , an amount of the hydroxy-type novolac resin (A-1) is 50 to 95 parts by weight claim 1 , an amount of ...

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Номер записи: 93
28-08-2014 дата публикации

REDUCING WAFER DISTORTION THROUGH A HIGH CTE LAYER

Номер: US20140242759A1
Автор: Chen Chi-Ming, Hwang Ho-Yung David, Tsai Chia-Shiung, Yu Chung-Yi
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon () surface. The method includes forming a high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate. The high CTE layer has a CTE greater than the CTE of silicon. The method includes forming a buffer layer over the second side of the silicon substrate. The buffer layer has a CTE greater than the CTE of silicon. The method includes forming a III-V family layer over the buffer layer. The III-V family layer has a CTE greater than the CTE of the buffer layer. 1. A method of fabricating a semiconductor device , comprising:{'b': '111', 'providing a silicon substrate having opposite first and second sides, at least one of the first and second sides including a silicon () surface;'}forming a first high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate, the first high CTE layer having a CTE greater than a CTE of silicon;forming a buffer layer over the second side of the silicon substrate, the buffer layer having a CTE greater than the CTE of silicon;forming a second high CTE layer over the second side of the silicon substrate, the second high CTE layer having a CTE greater than the CTE of silicon;removing the second high CTE layer; andafter removing the second high CTE layer, forming a III-V family layer over the buffer layer, the III-V family layer having a CTE greater than the CTE of the buffer layer.2. The method of claim 1 , wherein:the forming the high CTE layer is carried out in a manner so that the first high CTE layer includes a material selected from the group consisting of: silicon nitride, doped glass, and silicon carbide; andthe forming the III-V family layer is carried out in a manner so that the III-V family layer includes a gallium nitride material.3. The method of claim 1 , ...

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Номер записи: 94
28-08-2014 дата публикации

REDUCING WAFER DISTORTION THROUGH A HIGH CTE LAYER

Номер: US20140242768A1
Автор: Chen Chi-Ming, Hwang Ho-Yung David, Tsai Chia-Shiung, Yu Chung-Yi
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon (111) surface. The method includes forming a high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate. The high CTE layer has a CTE greater than the CTE of silicon. The method includes forming a buffer layer over the second side of the silicon substrate. The buffer layer has a CTE greater than the CTE of silicon. The method includes forming a III-V family layer over the buffer layer. The III-V family layer has a CTE greater than the CTE of the buffer layer. 1. A method of fabricating a semiconductor device , comprising:providing a silicon substrate having opposite first and second sides, at least one of the first and second sides including a silicon (111) surface;forming a first high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate, the first high CTE layer having a CTE greater than a CTE of silicon;forming a buffer layer over the second side of the silicon substrate, the buffer layer having a CTE greater than the CTE of silicon;forming a second high CTE layer over the second side of the silicon substrate, the second high CTE layer having a CTE greater than the CTE of silicon;removing the second high CTE layer; andafter removing the second high CTE layer, forming a III-V family layer over the buffer layer, the III-V family layer having a CTE greater than the CTE of the buffer layer.2. The method of claim 1 , wherein:the forming the high CTE layer is carried out in a manner so that the first high CTE layer includes a material selected from the group consisting of: silicon nitride, doped glass, and silicon carbide; andthe forming the III-V family layer is carried out in a manner so that the III-V family layer includes a gallium nitride material.3. The method of claim 1 , wherein the ...

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Номер записи: 95
14-06-2018 дата публикации

HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) DEVICE STRUCTURE

Номер: US20180166565A1
Автор: Chen Chi-Ming, Chen Kuei-Ming, Yu Chung-Yi
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A high electron mobility transistor (HEMT) device structure is provided. The HEMT device structure includes a channel layer formed over a substrate and an active layer formed over the channel layer. The HEMT device structure also includes a gate structure formed over the active layer, and the gate structure includes: a p-doped gallium nitride (p-GaN) layer or a p-doped aluminum gallium nitride (p-GaN) layer formed over the active layer, and a portion of the p-GaN layer or p-AlGaN layer has a stepwise or gradient doping concentration. The HEMT device structure also includes a gate electrode over the p-GaN layer or p-AlGaN layer. 1. A high electron mobility transistor (HEMT) device structure , comprising:a channel layer formed over a substrate;an active layer formed over the channel layer; and 'a p-doped gallium nitride (p-GaN) layer or a p-doped aluminum gallium nitride (p-AlGaN) layer formed over the active layer, wherein a portion of the p-GaN layer or a portion of the p-AlGaN layer has a stepwise or gradient doping concentration, and the other portion of the p-GaN layer or the p-AlGaN layer has a constant concentration, and the constant concentration is higher than the gradient doping concentration; and a gate electrode over the p-GaN layer or the p-AlGaN layer.', 'a gate structure formed over the active layer, wherein the gate structure comprises2. The high electron mobility transistor (HEMT) device structure as claimed in claim 1 , wherein the gate structure further comprises:a n-doped gallium nitride (n-GaN) layer between the p-GaN layer or the p-AlGaN layer and the gate electrode.3. (canceled)4. The high electron mobility transistor (HEMT) device structure as claimed in claim 1 , wherein the gradient doping concentration is gradually decreased from a bottom surface of the p-GaN layer to a top surface of the p-GaN layer claim 1 , or a bottom surface of the p-AlGaN layer to a top surface of the p-AlGaN layer.5. The high electron mobility transistor (HEMT) device ...

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Номер записи: 96
21-06-2018 дата публикации

MULTI-FUNCTION RULER

Номер: US20180172415A1
Автор: Chang Heng, CHU CHI-MING, Wang Yu-Lin
Принадлежит:

A multi-function ruler is provided with a rectangular, transparent body; at least one opening through a top and an underside of the body; and at least one row of a plurality of equally spaced markings printed along one side of the body. The at least one opening includes at least one directional sign, at least one curve, and at least one figure. 1. A ruler comprising:a transparent body;at least one opening through a top and an underside of the body; andat least one row of a plurality of equally spaced markings printed along one side of the body.2. The ruler of claim 1 , wherein the body is rectangular.3. The ruler of claim 1 , wherein the at least one opening includes at least one directional sign claim 1 , at least one curve claim 1 , and at least one figure. The invention relates to rulers and more particularly to a multi-function ruler, in addition to drawing a straight line, being capable of drawing different directional signs, curves and figures.Conventionally, an architect may use a plurality of different rulers to draw straight lines, curves, figures, etc. in work. This is inconvenient and may consume time.However, there is no single ruler capable of drawing different directional signs, curves and figures commercially available.Thus, the need for improvement still exists.It is therefore one object of the invention to provide a ruler comprising a transparent body; at least one opening through a top and an underside of the body; and at least one row of a plurality of equally spaced markings printed along one side of the body.Preferably, the body is rectangular.Preferably, the at least one opening includes at least one directional sign, at least one curve, and at least one figure.The invention has the following advantages: An individual may use the ruler to draw straight lines, different curves, and different figures on a paper. The individual may clearly see the opening being pointed by the pen and what is being drawn by the pen through the transparent body. ...

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Номер записи: 97
23-06-2016 дата публикации

Platinum(ii) complexes for oled applications

Номер: US20160181551A1
Автор: Chi Chung Kwok, Chi Fai Kui, Chi Ming Che
Принадлежит: Versitech Ltd

The current invention relates to novel platinum(II) based organometallic materials. These materials show high emission quantum efficiencies and low self-quenching constant. Also provided are high efficiency, green to orange emitting organic light-emitting diode (OLED) that are fabricated using platinum(II) based organometallic materials as the light-emitting material. The organometallic materials of the invention are soluble in common solvents; therefore, solution process methods such as spin coating and printing can be used for device fabrication. The devices fabricated from these materials show low efficiency roll-off.

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Номер записи: 98
02-07-2015 дата публикации

WIRELESS CHARGER HAVING MOVEABLE TRANSIMITTER COIL

Номер: US20150188356A1
Автор: CHEN CHENG-PANG, Chen Chi-Ming, Ren Wei, Zhou Feng
Принадлежит:

A wireless charger used for charging a portable electronic device with a receiver coil includes a wireless charging body, a transmitter coil, and a shaft. The charging body has a front body to support the portable electronic device and a rear body coordinated with the front body to form a receiving cavity for receiving transmitter coil. The rear body defines a track for the shaft disposing therein and moving the transmitter coil to align with the receiver coil. The wireless charger could align with receiver coils of different portable electronic devices. 1. A wireless charger used for charging a portable electronic device with a receiver coil , comprising:a wireless charging body having a front body to support said portable electronic device and a rear body coordinated with the front body to form a receiving cavity, said rear body defining a track;a transmitter coil received in the receiving cavity; anda shaft disposed within the track and connected with the transmitter coil, said shaft being moveable to align the transmitter coil with the receiver coil.2. The wireless charger claimed in claim 1 , wherein said rear body has an inner face and an outer face claim 1 , said track extend through the rear body along a direction perpendicular to the outer face claim 1 , and said track has a plurality of serrated structures for mating with the shaft.3. The wireless charger claimed in claim 2 , further including a moving tray connected between the transmitter coil and the shaft.4. The wireless charger claimed in claim 3 , wherein said transmitter coil has a planar magnetic core and a plurality of spiral coils retained thereon claim 3 , said planar magnetic core is retained to the moving tray claim 3 , and said shaft is engaged with the moving tray.5. The wireless charger claimed in claim 4 , wherein said shaft includes a disk-shaped main body claim 4 , a grip portion extending backwardly from the main body claim 4 , and a mating block extending forwardly from the main body ...

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Номер записи: 99
08-07-2021 дата публикации

Mouse

Номер: US20210208703A1
Автор: Chi-Ming Tseng
Принадлежит: Cheng Uei Precision Industry Co Ltd

A mouse includes a lower shell, an upper shell covered on the lower shell, a circuit board and a pressing button. The upper shell is spaced from the lower shell to form an accommodating space between the lower shell and the upper shell. The upper shell has at least one elastic arm. The circuit board fastened in the accommodating space is equipped with at least one electronic switch corresponding to the at least one elastic arm. The at least one electronic switch has a touching element. The pressing button is covered on the upper shell. The pressing button has at least one touching board which protrudes downward to form at least one pressing block. The at least one elastic arm is received in the at least one pressing block. The at least one pressing block abuts against the touching element.

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Номер записи: 100