COOLING STRUCTURE FOR ELECTRONIC BOARDS

A cooling structure for large electronic boards with closely-spaced heterogeneous die and packages is disclosed. The assembly includes a frame having a plurality of openings. The assembly further includes a cold plate mounted to the frame. The cold plate includes at least one inlet and at least one outlet and fluid channels in communication with the at least one inlet and the at least one outlet. The assembly further includes a heat sink mounted within each of the plurality of openings which in combination with sidewalls of the openings of the frame and the cold plate form individual compartments each of which are in fluid communication with the fluid channels. 1. A manifold assembly , comprising:a frame assembly having a plurality of sealed compartments each comprising a single heat sink registered to an underlying chip and/or package mounted on an electronic board;a fluid channel within the frame assembly; andan inlet and an outlet associated with each of the sealed compartments and in fluid communication with the fluid channel, the inlet and the outlet directing coolant over the single heat sink of each of the sealed compartments.2. The manifold assembly of claim 1 , wherein the frame assembly includes:a plurality of openings in a frame; anda cold plate assembly sealed to sidewalls of the openings of the bottom plate,fluid channels in the cold plate which includes the inlet and outlet for each of the sealed compartments.3. The manifold assembly of claim 2 , wherein the heat sink is mounted within each of the plurality of openings of the frame and in combination with sidewalls of the openings of the frame and the cold plate assembly form individual compartments each of which is in fluid communication with the fluid channels.4. The manifold assembly of claim 2 , wherein the cold plate assembly includes grooves structured to accommodate the sidewalls of the plurality of openings of the frame for mounting of the frame to the cold plate.5. The manifold assembly of ...

MULTICHIP ELECTRONIC PACKAGES AND METHODS OF MANUFACTURE

A multi-chip electronic package and methods of manufacture are provided. The method includes contacting pistons of a lid with respective ones of chips on a chip carrier. The method further includes separating the lid and the chip carrier and placing at least one seal shim on one of the lid and chip carrier. The at least one seal shim has a thickness that results in a gap between the pistons with the respective ones of the chips on the chip carrier. The method further includes dispensing thermal interface material within the gap and in contact with the chips. The method further includes sealing the lid to the chip carrier with the at least one seal shim between the lid and the chip carrier. 1. A method , comprising:contacting pistons of a lid with respective ones of chips on a chip carrier;separating the lid and the chip carrier and placing at least one seal shim on one of the lid and chip carrier, the at least one seal shim having a thickness that results in a gap between the pistons with the respective ones of the chips on the chip carrier;dispensing thermal interface material within the gap and in contact with the chips; andsealing the lid to the chip carrier with the at least one seal shim between the lid and the chip carrier.2. The method of claim 1 , further comprising aligning the pistons of the lid in registration with chips on the chip carrier.3. The method of claim 1 , further comprising planarizing the pistons with a surface of the lid and fixing the pistons to the lid.4. The method of claim 3 , wherein the fixing the pistons to the lid includes cooling solder such that the solder bonds the pistons to the lid.5. The method of claim 4 , wherein the contacting comprising placing the lid and chip carrier in a reflow furnace and heating the solder to release the pistons from the lid.6. The method of claim 1 , further comprising sealing the at least one seal shim to the one of the lid and chip carrier with a sealant.7. The method of claim 1 , further comprising ...

MULTICHIP ELECTRONIC PACKAGES AND METHODS OF MANUFACTURE

A multi-chip electronic package and methods of manufacture are provided. The multi-chip package includes a plurality of chips mounted on a chip carrier. The multi-chip package further includes a lid mounted on the chip carrier using a bonding material or compression seal, and at least one single piston extending from the lid. Each piston covers an entirety of multiple chips of the plurality of chips. 1. A multi-chip package comprising:a plurality of chips mounted on a chip carrier;a lid mounted on the chip carrier using a bonding material or seal; andat least one single piston extending from the lid, each of which cover an entire surface of multiple chips of the plurality of chips.2. The multi-chip package of claim 1 , wherein the lid encapsulates the plurality of chips mounted on the chip carrier.3. The multi-chip package of claim 1 , wherein the at least one single piston covers at least two chips mounted on the chip carrier.4. The multi-chip package of claim 1 , wherein the chip carrier is a ceramic claim 1 , silicon or inorganic chip carrier.5. The multi-chip package of claim 1 , wherein the chip carrier is a polymer-based or organic chip carrier.6. The multi-chip package of claim 1 , further comprising a thermally-conducting material provided between the at least one single piston and the respective multiple chips which are covered by the at least one single piston.7. The multi-chip package of claim 1 , wherein the at least one single piston is planar with a surface of the lid.8. The multi-chip package of claim 1 , wherein the multiple chips have a spacing therebetween of about 1 millimeter to about 2 millimeters.9. The multi-chip package of claim 1 , wherein the at least one single piston is fixed to the lid.10. The multi-chip package of claim 1 , wherein edges of each of the at least one single piston overlap edges of the multiple chips.11. A structure comprising:a lid encapsulating at least two chips mounted on a chip carrier;a single piston of a lid ...

MULTICHIP ELECTRONIC PACKAGES AND METHODS OF MANUFACTURE

A multi-chip electronic package and methods of manufacture are provided. The method comprises adjusting a piston position of one or more pistons with respect to one or more chips on a chip carrier. The adjusting comprises placing a chip shim on the chips and placing a seal shim between a lid and the chip carrier. The seal shim is thicker than the chip shim. The adjusting further comprise lowering the lid until the pistons contact the chip shim. The method further comprises separating the lid and the chip carrier and removing the chip shim and the seal shim. The method further comprises dispensing thermal interface material on the chips and lowering the lid until a gap filled with the thermal interface material is about a particle size of the thermal interface material. The method further comprises sealing the lid to the chip carrier with sealant. 1. A method , comprising: 'placing a chip shim on the one or more chips on the chip carrier;', 'adjusting a piston position of one or more pistons with respect to one or more chips on a chip carrier, the adjusting comprising 'lowering the lid until the one or more pistons contact the chip shim;', 'placing a seal shim between a lid and the chip carrier, the seal shim being thicker than the chip shim;'} 'fixing the one or more pistons to the lid in the displaced position;', 'displacing the one or more pistons and lid individually until full surface contact with both the chip shim and the seal shim is established;'}separating the lid and the chip carrier;removing the chip shim and the seal shim;dispensing thermal interface material on the one or more chips and lowering the lid until a gap filled with the thermal interface material between the one or more chips and the one or more pistons is about a particle size of the thermal interface material; andsealing the lid to the chip carrier with sealant between the lid and the chip carrier.2. The method of claim 1 , further comprising aligning the one or more pistons of the lid in ...

DETERMINING THERMAL INTERFACE MATERIAL (TIM) THICKNESS CHANGE

An apparatus for determining a thickness change of thermal interface material (TIM) disposed between first and second elements is provided. The apparatus includes a first part movable with the first element in a movement direction along which the TIM thickness is to be determined, a second part movable with the second element in the movement direction and a sensor to measure a distance between the first and second parts in the movement direction, the measured distance being related to the TIM thickness change. 1. An apparatus for determining a thickness change of thermal interface material (TIM) disposed between first and second elements , the apparatus comprising:a first part movable with the first element in a movement direction along which the TIM thickness change is to be determined;a second part movable with the second element in the movement direction; anda sensor to measure a distance between the first and second parts in the movement direction, the measured distance being related to the TIM thickness.2. The apparatus according to claim 1 , wherein the first element comprises a lid and the second element comprises a processor.3. The apparatus according to claim 1 , wherein the first part is affixed to the first element.4. The apparatus according to claim 3 , wherein the first part is recessed from a plane of a surface of the first element.5. The apparatus according to claim 1 , further comprising an elastic element interposed between the first and second parts to urge the second part to contact the second element.6. The apparatus according to claim 5 , wherein the elastic element comprises a spring.7. The apparatus according to claim 1 , wherein the second part comprises a pin oriented to extend in the movement direction.8. The apparatus according to claim 7 , further comprising a bushing disposed within the first element through which the pin extends.9. The apparatus according to claim 1 , wherein the sensor comprises a capacitive sensor.10. The apparatus ...

ELECTRONIC DEVICE CONSOLE WITH NATURAL DRAFT COOLING

An electronic device console includes a console body that houses a chip package, and a duct extending from the console body. An interior volume of the duct is in fluid communication with an interior volume of the console body. A first vent is at a distal end of the duct. A second vent is in a wall of the console body. The console may be oriented in a first orientation and a second orientation. The duct functions as a chimney for natural convection cooling of the chip package when the console is oriented in the first orientation. The console body functions as a chimney for natural convection cooling of the chip package when the console is oriented in the second orientation. 1. An electronic device console , comprising:a console body that houses a chip package;a duct extending from the console body, wherein an interior volume of the duct is in fluid communication with an interior volume of the console body;a first vent at a distal end of the duct; anda second vent in a wall of the console body;wherein the console is structured and arranged to be oriented in a first orientation and a second orientation;the duct functions as a chimney for natural convection cooling of the chip package when the console is oriented in the first orientation; andthe console body functions as a chimney for natural convection cooling of the chip package when the console is oriented in the second orientation.2. The console of claim 1 , wherein the console is devoid of a fan.3. The console of claim 1 , wherein a length of the duct is greater than a width of the duct.4. The console of claim 1 , wherein:the first vent is an outlet and the second vent is an inlet in the first orientation; andthe first vent is an inlet and the second vent is an outlet in the second orientation.5. The console of claim 1 , wherein:the first vent is vertically aligned with the chip package in the first orientation; andthe second vent is vertically aligned with the chip package in the second orientation.6. The console ...

MULTICHIP ELECTRONIC PACKAGES AND METHODS OF MANUFACTURE

A multi-chip electronic package and methods of manufacture are provided. The method includes adjusting a piston position of one or more pistons with respect to one or more chips on a chip carrier. The adjusting includes placing a chip shim on the chips and placing a seal shim between a lid and the chip carrier. The seal shim is thicker than the chip shim. The adjusting further includes lowering the lid until the pistons contact the chip shim. The method further includes separating the lid and the chip carrier and removing the chip shim and the seal shim. The method further includes dispensing thermal interface material on the chips and lowering the lid until a gap filled with the thermal interface material is about a particle size of the thermal interface material. The method further includes sealing the lid to the chip carrier with sealant. 1. A method , comprising: placing a chip shim on the one or more chips on the chip carrier;', 'placing a seal shim between a lid and the chip carrier, the seal shim being thicker than the chip shim;', 'lowering the lid until the lid contacts the seal shim and the one or more pistons contact the chip shim;', 'fixing the one or more pistons to the lid in the lowered position; and', 'removing the chip shim and the seal shim;, 'adjusting a piston position of one or more pistons with respect to one or more chips on a chip carrier, the adjusting comprisingdispensing thermal interface material on the one or more chips and lowering the lid until a gap filled with the thermal interface material between the one or more chips and the one or more pistons is about a particle size of the thermal interface material; andsealing the lid to the chip carrier with sealant.2. The method of claim 1 , further comprising aligning the one or more pistons of the lid in registration with respective one or more chips on the chip carrier.3. The method of claim 1 , further comprising planarizing the one or more pistons with a surface of the lid and fixing ...

MULTICHIP ELECTRONIC PACKAGES AND METHODS OF MANUFACTURE

A multi-chip electronic package and methods of manufacture are provided. The multi-chip package includes a plurality of chips mounted on a chip carrier. The multi-chip package further includes a lid mounted on the chip carrier using a bonding material or compression seal, and at least one single piston extending from the lid. Each piston covers an entirety of multiple chips of the plurality of chips. 1. A method comprising:mounting a plurality of chips on a chip carrier;positioning a lid over the chip carrier;placing at least one single piston in a hole in the lid, such that the at least one piston is aligned with the plurality of chips, the at least one single piston having a continuous surface on a single plane;providing a thermal interface material (TIM) along an entirety of a length of the continuous surface of the at least one single piston; andmounting the lid on the chip carrier using a bonding material or seal.2. The method of claim 1 , further comprising planarizing an upper surface of the at least one single piston with an upper surface of the lid.3. The method of claim 1 , wherein the aligning the at least one single piston with the plurality of chips comprises overlapping edges of the plurality of chips with the continuous surface of the at least one single piston.4. The method of claim 1 , further comprising fixing the at least one single piston to the lid with material deposited between the lid and the at least one single piston.5. The method of claim 4 , wherein the material that fixes the at least one single piston to the lid comprises one of adhesive claim 4 , epoxy claim 4 , and solder.6. The method of claim 4 , further comprising attaching the lid to the chip carrier with an adhesive or sealant.7. The method of claim 6 , wherein the fixing the at least one single piston to the lid is by one of adhesive claim 6 , epoxy and solder.8. The method of claim 1 , wherein the aligning the at least one single piston with the plurality of chips comprises ...

MULTICHIP MODULE WITH STIFFING FRAME AND ASSOCIATED COVERS

A multichip module includes a carrier, a stiffening frame, a plurality of semiconductor chips, and a plurality of covers. The carrier has a top surface and a bottom surface configured to be electrically connected to a motherboard. The stiffening frame includes a plurality of openings that accept the plurality of semiconductor chips and may be attached to the top surface of the carrier with an adhesive that absorbs dimensional changes between the stiffening frame and the carrier. The semiconductor chips are concentrically arranged within the plurality of openings of the stiffening frame and the plurality of covers are attached to the stiffening frame so as to enclose the plurality of openings. 1. A method comprising:attaching a stiffening frame to a carrier with a compliant adhesive that absorbs thermally induced dimensional variations between the stiffening frame and the carrier, the stiffening frame comprising a plurality of openings configured to accept a plurality of semiconductor chips;electronically coupling the plurality of semiconductor chips to the carrier, each semiconductor chip being concentrically arranged within a particular opening, and;attaching a plurality of covers to the stiffening frame to enclose the plurality of openings.2. The method of wherein at least a first cover is in thermal contact with a first semiconductor chip.3. The method of further comprising:attaching a thermal interface material barrier to the stiffening frame perimeter.4. The method of wherein each cover comprises a top surface and wherein the top surface of a first cover is coplanar with the top surface of a second cover.5. The method of wherein each cover comprises a top surface and wherein the top surface of a first cover is non-planar with the top surface of a second cover.6. The method of wherein each cover comprises a top surface claim 1 , wherein the stiffening frame comprises a top surface claim 1 , and wherein the top surface of a first cover is coplanar with the top ...

SEMICONDUCTOR WAFER HAVING TRENCHES WITH VARIED DIMENSIONS FOR MULTI-CHIP MODULES

A semiconductor wafer includes a first substrate and a first etch stop layer formed on the first substrate. The etch stop layer has an opening. The semiconductor wafer further includes a second substrate and a second etch stop layer formed on the second substrate. The first substrate is bonded on top of the second substrate such that the first etch stop layer is positioned between the first substrate and the second substrate. A trench is formed in the opening. 1. A semiconductor wafer comprising:a first substrate;a first etch stop layer formed on the first substrate, wherein the etch stop layer comprises an opening;a second substrate;a second etch stop layer formed on the second substrate, wherein the first substrate is bonded on top of the second substrate such that the first etch stop layer is positioned between the first substrate and the second substrate; anda trench formed in the opening.2. The semiconductor wafer according to claim 1 , wherein the first substrate comprises silicone.3. The semiconductor wafer according to claim 1 , wherein the second substrate comprises a silicon-on-insulator (SOI) structure.4. The semiconductor wafer according to claim 1 , wherein the first etch stop layer comprises a material selected from the group consisting of an oxide claim 1 , nitride or oxynitride.5. The semiconductor wafer according to claim 1 , wherein the second etch stop layer comprises a material selected from the group consisting of an oxide claim 1 , nitride or oxynitride.6. The semiconductor wafer according to further comprising a planarizing layer.7. The semiconductor wafer according to claim 6 , wherein the planarizing layer comprises an acrylic polymer.8. The semiconductor wafer according to further comprising a bonding layer.9. The semiconductor wafer according to claim 8 , wherein the bonding layer comprises a metal.10. The semiconductor wafer according to further comprising a micro-cooler structure.11. A method of fabricating a semiconductor wafer claim 1 ...

LAMINATED STIFFENER TO CONTROL THE WARPAGE OF ELECTRONIC CHIP CARRIERS

A technique relates to an electronic package. A substrate is configured to receive a chip. A stiffener is attached to the substrate. The stiffener includes a core material with a first material formed on opposing sides of the core material. 1. An electronic package comprising:a substrate configured to receive a chip; anda stiffener attached to the substrate, the stiffener comprising a core material with a first material formed on opposing sides of the core material, wherein a coefficient of thermal expansion (CTE) of the stiffener and the substrate matches through a predefined range of temperatures.2. The electronic package of claim 1 , wherein the core material comprises at least one material in the substrate.3. The electronic package of claim 1 , wherein the first material is copper.4. The electronic package of claim 1 , wherein a second material is formed on opposing sides of the core material.5. The electronic package of claim 4 , wherein the second material is a dielectric material.6. The electronic package of claim 4 , wherein vias are formed through the second material.7. The electronic package of claim 6 , wherein the vias are filled with the first material.8. The electronic package of claim 1 , wherein the CTE of the stiffener and the substrate positively correlates through the predefined range of temperatures.9. The electronic package of claim 6 , wherein the vias are of different shapes.10. The electronic package of claim 9 , wherein the different shapes of the vias comprise one or more of a first geometric shape claim 9 , a second geometric shape claim 9 , and a third geometric shape.11. The electronic package of claim 1 , wherein one or both sides of the core material comprise a stack of copper layers and dielectric layers in any order of arrangement.12. The electronic package of claim 11 , wherein the copper layers are of a variable thickness and the dielectric layers are of a variable thickness.13. The electronic package of claim 12 , wherein the CTE ...

ELECTRONIC DEVICE CONSOLE WITH NATURAL DRAFT COOLING

An electronic device console includes a console body that houses a chip package, and a duct extending from the console body. An interior volume of the duct is in fluid communication with an interior volume of the console body. A first vent is at a distal end of the duct. A second vent is in a wall of the console body. The console may be oriented in a first orientation and a second orientation. The duct functions as a chimney for natural convection cooling of the chip package when the console is oriented in the first orientation. The console body functions as a chimney for natural convection cooling of the chip package when the console is oriented in the second orientation.

Multiple chip bridge connector

The present invention includes a bridge connector with one or more semiconductor layers in a bridge connector shape. The shape has one or more edges, one or more bridge connector contacts on a surface of the shape, and one or more bridge connectors. The bridge connectors run through one or more of the semiconductor layers and connect two or more of the bridge connector contacts. The bridge connector contacts are with a tolerance distance from one of the edges. In some embodiments the bridge connector is a central bridge connector that connects two or more chips disposed on the substrate of a multi-chip module (MCM). The chips have chip contacts that are on an interior corner of the chip. The interior corners face one another. The central bridge connector overlaps the interior corners so that each of one or more of the bridge contacts is in electrical contact with each of one or more of the chip contacts. In some embodiments, overlap is minimized to permit more access to the surface of the chips. Arrays of MCMs and methods of making bridge connects are disclosed. Bridge connector shapes include: rectangular, window pane, plus-shaped, circular shaped, and polygonal-shaped.

ELECTRONIC DEVICE CONSOLE WITH NATURAL DRAFT COOLING

An electronic device console includes a console body that houses a chip package, and a duct extending from the console body. An interior volume of the duct is in fluid communication with an interior volume of the console body. A first vent is at a distal end of the duct. A second vent is in a wall of the console body. The console may be oriented in a first orientation and a second orientation. The duct functions as a chimney for natural convection cooling of the chip package when the console is oriented in the first orientation. The console body functions as a chimney for natural convection cooling of the chip package when the console is oriented in the second orientation. 1. An electronic device console , comprising:a console body that houses a chip package;a duct extending from the console body;a first vent at a distal end of the duct; anda second vent in a wall of the console body,wherein the electronic device console is structured and arranged to be oriented in a first orientation and a second orientation, andthe electronic device comprises a slide mechanism positioned at a top orientation of the console body such that a proximate end of the duct is moveable into the console body through the slide mechanism that allows translational movement of the duct relative to the console body when the electronic device console is oriented in the first orientation, and the slide mechanism allows a portion of the duct to be moved within the console body.2. The electronic device console of claim 1 , wherein the electronic device console is devoid of a fan.3. The electronic device console of claim 1 , wherein a length of the duct is greater than a width of the duct.4. The electronic device console of claim 1 , wherein:the first vent is an outlet and the second vent is an inlet in the first orientation; andthe first vent is an inlet and the second vent is an outlet in the second orientation.5. The electronic device console of claim 1 , wherein:the first vent is vertically ...

Adjustable heat sink fin spacing

A heat sink includes a heat sink base/riser, a first fin, and a second fin. The spacing between the base/riser and the first fin and the second fin, restively, may be adjusted by rotating a threaded rod. The threaded rod includes a first threaded knurl that is engaged with the first fin and a second threaded knurl that is engaged with the second fin. The thread pitch of the first threaded knurl and the second threaded knurl may differ. For example, the pitch of the first threaded knurl may be smaller than the pitch of the second threaded knurl if the first fin is located nearest the heat sink base/riser relative to the second fin. The spacing of the heat sink fins may be adjusted based upon the current operating conditions of the electronic device to maintain an optimal temperature of a heat generating device during device operation.

Semiconductor Microcooler

A semiconductor microcooler is fabricated by forming fins in a semiconductor substrate and forming a metal layer upon the fins. A stacked microcooler may be formed by stacking a plurality of semiconductor microcoolers. The microcoolers may be positioned such that the fins of each microcooler are vertically aligned. The microcoolers may include an inlet passage to accept coolant and an outlet passage to expel the coolant. One or more microcoolers may be thermally connected to an electronic device heat generating device, such as an integrated circuit (IC) chip, or the like. Heat from the electronic device heat generating device may transfer to the one or more microcoolers. A flow of cooled liquid may be introduced through the passages and heat from the one or more microcoolers may transfer to the liquid coolant. 1. A method comprising:forming a first semiconductor microcooler by removing portions of a first bulk silicon substrate to form a plurality of first silicon fins and a plurality of first fin trenches, wherein each first fin trench separates adjacent first silicon fins, forming a first copper layer upon sidewalls of each of the plurality of first silicon fins, by forming a first bonding layer upon a respective upper surface of each of the first plurality of silicon fins, by forming a first access passage within the first semiconductor microcooler by removing a portion of a first silicon fin and a portion of the bulk silicon substrate adjacent to the portion of the first silicon fin, and forming a first fin trench filler within each of the plurality of first fin trenches and within the first access passage;forming a second semiconductor microcooler by removing portions of a second bulk silicon substrate to form a plurality of second silicon fins and a plurality of second fin trenches, wherein each second fin trench separates adjacent second silicon fins, forming a second copper layer upon sidewalls of each of the plurality of second silicon fins, by forming a ...

Semiconductor Microcooler

A semiconductor microcooler is fabricated by forming fins in a semiconductor substrate and forming a metal layer upon the fins. A stacked microcooler may be formed by stacking a plurality of semiconductor microcoolers. The microcoolers may be positioned such that the fins of each microcooler are aligned. One or more microcoolers may be thermally connected to a surface of a coolant conduit that is thermally connected to an electronic device heat generating device, such as an integrated circuit (IC) chip, or the like. Heat from the electronic device heat generating device may transfer to the one or more microcoolers. A flow of cooled liquid may be introduced through the conduit and heat from the one or more microcoolers may transfer to the liquid coolant.

LID ATTACH OPTIMIZATION TO LIMIT ELECTRONIC PACKAGE WARPAGE

An electronic package includes a carrier and a semiconductor chip. In a first aspect an interleaved seal band includes a pattern of a first type of seal band material and a second type of seal band material. 1. A electronic package comprising:a carrier comprising a top surface and a bottom surface;a semiconductor chip electrically connected to the top surface;a interleaved seal band connecting the carrier and the lid perimeter; anda lid thermally connected to a top surface of the semiconductor chip and thermally connected with the interleaved seal band.2. The electronic package of claim 1 , wherein the interleaved seal band comprises a patterned epoxy material upon the carrier about the perimeter of the semiconductor chip.3. The electronic package of claim 1 , wherein the interleaved seal band further comprises a patterned elastomeric material upon the carrier about the perimeter of the semiconductor chip.4. The electronic package of claim 3 , wherein the patterned epoxy material is interleaved with the patterned elastomeric material.5. The electronic package of claim 4 , wherein the patterned epoxy material is located at corners of the interleaved seal band.6. The electronic package of claim 5 , wherein a top surface of the epoxy material is coplanar with a top surface of the elastomeric material.7. The electronic package of claim 5 , wherein a top surface of the epoxy material is recessed from a top surface of the elastomeric material.8. The electronic package of claim 1 , wherein the interleaved seal band fills a gap between the carrier and an underside of the lid.9. The electronic package of claim 5 , wherein the patterned epoxy material is further located at the semiconductor chip bisection points of the interleaved seal band.10. The electronic package of claim 1 , wherein the interleaved seal band comprises a high thermally compliant material upon the carrier about the perimeter of the semiconductor chip interleaved with a low thermally compliant material upon ...

LID ATTACH OPTIMIZATION TO LIMIT ELECTRONIC PACKAGE WARPAGE

In yet another aspect the electronic package further includes a frame concentric with the chip. The lid is attached to the frame with a solder, epoxy or elastomer and placed on the chip with a thermal interface material. The seal band material is dispensed on the chip carrier and the frame is then moved towards the chip carrier allowing a minimum seal band thickness. 1. A electronic package comprising:a carrier comprising a top surface and a bottom surface;a frame comprising an opening upon the carrier, the frame comprising a first frame side and second frame side, the first frame side comprising a top surface coplanar with a top surface of a lid and the second frame side comprising a top surface below the top surface of the lid;a semiconductor chip electrically connected to the top surface within and concentric with the opening;the lid thermally connected to a top surface of the semiconductor chip; andjoin material that connects the lid and the frame.2. The electronic package of claim 1 , wherein the join material contacts a sidewall of the first frame side and a first sidewall of the lid.3. The electronic package of claim 1 , wherein the join material contacts a sidewall and the top surface of the second frame side and a second sidewall of the lid.4. The electronic package of claim 1 , wherein the first sidewall of the lid opposes the second sidewall of the lid.5. The electronic package of claim 1 , wherein the join material is solder.6. The electronic package of claim 1 , wherein the join material is epoxy.7. The electronic package of claim 1 , wherein the join material is elastomeric.8. The electronic package of claim 3 , wherein a top surface of the join material that contacts the top surface of the second frame side is coplanar with the top surface of the lid. Embodiments of the present invention generally relate to electronic devices and more specifically to lid attach techniques to limit warpage within an electronic device package.An electronic package may ...

Integrated Circuit Chip Carrier with In-Plane Thermal Conductance Layer

An integrated circuit (IC) chip carrier includes an IC chip electrically connected to an IC chip carrier by a plurality of chip-carrier contacts, a cover thermally connected the IC chip upper surface, and an in-plane thermal conductance (ITC) layer upon the IC chip carrier between the IC chip carrier and the IC chip. The ITC layer includes an extension tab connected to a vertical side surface of the cover. Heat is transferred vertically from the IC chip to the cover. Heat is also transferred vertically from the IC chip to the ITC layer. Heat is also transferred within the ITC layer through the ITC layer basal plane(s). The ITC layer basal plane(s) are positioned horizontally where the ITC layer is between the IC chip and the IC chip carrier. The ITC layer basal planes are positioned vertically where the extension tab contacts the vertical side surface of the cover. 1. An integrated circuit (IC) chip carrier comprising:an IC chip electrically connected to an IC chip carrier by a plurality of chip-carrier contacts;a cover thermally connected the IC chip upper surface; andan in-plane thermal conductance (ITC) layer upon the IC chip carrier between the IC chip carrier and the IC chip, the ITC layer comprising an extension tab connected to a vertical side surface of the cover.2. The carrier of claim 1 , wherein the ITC layer comprises a plurality of openings therethrough claim 1 , each of the plurality of openings aligned with one of the plurality of chip-carrier contacts.3. The carrier of claim 1 , wherein the ITC layer comprises an opening therethrough claim 1 , the opening aligned around the circumference of the plurality of chip-carrier contacts.4. The carrier of claim 1 , wherein the ITC layer is an anisotropic material that has first thermal conductivity through its basal plane and a second thermal conductivity through its plane orthogonal to the basal plane claim 1 , wherein the second thermal conductivity is lower than the first thermal conductivity.5. The ...

COOLING STRUCTURE FOR ELECTRONIC BOARDS

A cooling structure for large electronic boards with closely-spaced heterogeneous die and packages is disclosed. The assembly includes a frame having a plurality of openings. The assembly further includes a cold plate mounted to the frame. The cold plate includes at least one inlet and at least one outlet and fluid channels in communication with the at least one inlet and the at least one outlet. The assembly further includes a heat sink mounted within each of the plurality of openings which in combination with sidewalls of the openings of the frame and the cold plate form individual compartments each of which are in fluid communication with the fluid channels. 1. A manifold assembly , comprising:a frame assembly having a plurality of sealed compartments each comprising a single heat sink registered to an underlying chip and/or package mounted on an electronic board;a fluid channel within the frame assembly; andan inlet and an outlet associated with each of the sealed compartments and in fluid communication with the fluid channel, a plurality of openings in a frame; and', 'a cold plate assembly sealed to sidewalls of openings of a bottom plate,', 'the bottom plate having a top side and a bottom side, and', 'the bottom side having a plurality of grooves which accommodate sidewalls of the openings of the frame., 'wherein the frame assembly includes2. The manifold assembly of claim 1 , wherein the inlet and the outlet direct coolant over the single heat sink of each of the sealed compartments.3. The manifold assembly of claim 1 , wherein the cold plate assembly includes fluid channels for the inlet and outlet for each of the sealed compartments.4. The manifold assembly of claim 1 , wherein the heat sink includes fins which are one of cuboidal claim 1 , cylindrical pin fins claim 1 , channels that are parallel and trapezoidal.5. The manifold assembly of claim 1 , wherein the heat sink in each of the plurality of openings is registered and spans over at least one ...

MULTICHIP MODULE WITH STIFFENING FRAME AND ASSOCIATED COVERS

A multichip module includes a carrier, a stiffening frame, a plurality of semiconductor chips, and a plurality of covers. The carrier has a top surface and a bottom surface configured to be electrically connected to a motherboard. The stiffening frame includes a plurality of openings that accept the plurality of semiconductor chips and may be attached to the top surface of the carrier with an adhesive that absorbs dimensional changes between the stiffening frame and the carrier. The semiconductor chips are concentrically arranged within the plurality of openings of the stiffening frame and the plurality of covers are attached to the stiffening frame so as to enclose the plurality of openings. 1. A multichip module comprising: 'a top surface and a bottom surface configured to be electrically connected to a motherboard;', 'a carrier comprising 'a plurality of openings that accept the plurality of semiconductor chips;', 'a stiffening frame attached to the top surface with an compliant adhesive that absorbs thermally induced dimensional variations between the stiffening frame and the carrier, the stiffening frame comprisinga plurality of semiconductor chips electrically connected to the top surface and concentrically arranged within the plurality of openings, and;a plurality of covers attached to the stiffening frame that enclose the plurality of openings.2. The multichip module of wherein at least a first cover is in thermal contact with a first semiconductor chip.3. The multichip module of wherein the stiffening frame further comprises:a thermal interface material barrier upon a top surface of the stiffening frame perimeter.4. The multichip module of wherein each cover comprises a top surface and wherein the top surface of a first cover is coplanar with the top surface of a second cover.5. The multichip module of wherein each cover comprises a top surface and wherein the top surface of a first cover is non-planar with the top surface of a second cover.6. The multichip ...

Adjustable heat sink fin spacing

A heat sink includes a first fin and a second fin. The spacing between the first fin and the second fin may be adjusted by a threaded rod. The threaded rod includes a first portion that is engaged with the first fin and a second portion that is engaged with the second fin. The thread pitch of the first portion and the second portion may differ. For example, the pitch of a first internal thread of the first fin may be smaller than the pitch of a second internal thread of the second fin. The spacing of the heat sink fins may be adjusted based upon the current operating conditions of the electronic device to maintain an optimal temperature of a heat generating device during device operation.

ELECTRONIC PACKAGE COVER HAVING UNDERSIDE RIB

An electronic package lid which includes one or more underside ribs. The ribs have a major length and a minor width and are generally aligned to be parallel with a diagonal or normal bisector of the processing device. The underside rib generally stiffens the cover such that an upper surface of the cover is more apt to stay flat. As such, cover warpage and, therefore, the peeling of the TIM1 and delamination of underfill due to the physical or dimensional expansion of the processing device and/or a carrier may be reduced. As a result, the surface area dedicated for the seal material upon the carrier surface may be reduced, thereby increasing the available surface area upon the carrier for additional electronic components to be placed in close proximity to the processing device. 1. A electronic package comprising:a processing device electrically connected to a carrier, the processing device comprising a diagonal bisector that travels through a center of the processing device and at least one corner of the processing device;a seal band upon the carrier; anda cover having a perimeter bottom surface connected to the carrier via the seal band, the cover comprising an underside rib having a major length and minor width, wherein the underside rib is positioned upon the cover such that the major length is parallel with the diagonal bisector and an inner end surface of the underside rib contacts a corner of the processing device, wherein the perimeter bottom surface of the cover and an underside rib surface are coplanar, and wherein the inner end surface is orthogonal to the underside rib surface.2. The electronic package of claim 1 , wherein the underside rib surface and the perimeter bottom surface are integral and coplanar.3. The electronic package of claim 1 , wherein the processing device is electrically connected to the carrier.4. The electronic package of claim 1 , further comprising underfill material between the processing device and the carrier.5. The electronic ...

ELECTRONIC PACKAGE COVER HAVING UNDERSIDE RIB

An electronic package lid which includes one or more underside ribs. The ribs have a major length and a minor width and are generally aligned to be parallel with a diagonal or normal bisector of the processing device. The underside rib generally stiffens the cover such that an upper surface of the cover is more apt to stay flat. As such, cover warpage and, therefore, the peeling of the TIM1 and delamination of underfill due to the physical or dimensional expansion of the processing device and/or a carrier may be reduced. As a result, the surface area dedicated for the seal material upon the carrier surface may be reduced, thereby increasing the available surface area upon the carrier for additional electronic components to be placed in close proximity to the processing device. 1. A electronic package comprising:a processing device electrically connected to a carrier, the processing device comprising a normal bisector along a center of the processing device and midpoint of an edge of a sidewall of the processing device;a seal band upon the carrier; anda cover having a perimeter bottom surface connected to the carrier via the seal band, the cover comprising an underside rib having a major length and minor width, wherein the underside rib is positioned upon the cover such that the major length is parallel with the normal bisector and an inner end surface of the underside rib contacts the sidewall of the processing device, wherein the perimeter bottom surface of the cover and an underside rib surface are coplanar, and wherein the inner end surface is orthogonal to the underside rib surface.2. The electronic package of claim 1 , wherein the underside rib surface and the perimeter bottom surface are integral and coplanar.3. An electronic package fabrication method comprising:positioning a cover comprising an underside rib against a carrier such that a major length of the underside rib is parallel with a normal bisector of a processing device electrically connected to the ...

HYBRID TIMs FOR ELECTRONIC PACKAGE COOLING

Structural combinations of TIMs and methods of combining these TIMs in semiconductor packages are disclosed. An embodiment forms the structures by selectively metallizing a backside of a semiconductor chip (chip) on chip hot spots, placing a higher performance thermal interface material (TIM) on the metallized hot spots, selectively metalizing an underside of a lid in one or more metalized lid locations, and assembling a lid over the backside of the chip to create an assembly so that metalized lid locations are in contact with the higher performance TIMs. A lower performance TIM fills the region surrounding the higher performance TIM on the underside of the lid enclosing the chips. Disclosed are methods of disposing both solid and dispensable TIMs, curing and not curing the thermal interface, and structures to keep the TIMs in place while assembly the package and compressing dispensable TIMs. Alternative method steps are disclosed, such as: injecting the lower performance TIM through injection holes in a pre-assembled assembly, using solid preform TIMs with cutouts, and using high performance TIM structures that have collapsible rails to prevent lower performance TIM from spilling onto the surface of the higher performance TIM to permit good/bonding. 1. A method of forming a thermal interface comprising the steps of:selectively metallizing a backside of a semiconductor chip (chip) to form one or more metallized layers on one or more hot spot regions of the chip, a connection side of the chip electrically and physically connected to a chip carrier by one or more electrical connections;placing a higher performance thermal interface material (TIM) on the metallized layers;selectively metalizing an underside of a lid in one or more metalized lid locations, each of the metalized lid locations corresponding to one of the high-performance TIMs, the lid having one or more feet protruding from the underside of the lid to create a chip region on the underside of the lid; ...

Semiconductor Microcooler

A stacked semiconductor microcooler includes a first microcooler and a second microcooler. The microcoolers may be positioned such that the fins of each microcooler are vertically aligned. The microcoolers may include an inlet passage to accept coolant and an outlet passage to expel the coolant. One or more microcoolers may be thermally connected to an electronic device heat generating device, such as an integrated circuit (IC) chip, or the like. Heat from the electronic device heat generating device may transfer to the one or more microcoolers. A flow of cooled liquid may be introduced through the passages and heat from the one or more microcoolers may transfer to the liquid coolant. 1. A heat transfer method comprising:causing a flow of liquid coolant through a plurality of fin trenches of a stacked semiconductor microcooler, the stacked semiconductor microcooler comprising:a first semiconductor microcooler comprising a plurality of first silicon fins and a plurality of first fin trenches, wherein each first fin trench separates adjacent first silicon fins, a first copper layer upon sidewalls of each of the plurality of first silicon fins, a first bonding layer upon a respective upper surface of each of the first plurality of silicon fins, and a first access passage within the first semiconductor microcooler; anda second semiconductor microcooler comprising a plurality of second silicon fins and a plurality of second fin trenches, wherein each second fin trench separates adjacent second silicon fins, a second copper layer upon sidewalls of each of the plurality of second silicon fins, and a second bonding layer upon a respective upper surface of each of the second plurality of silicon fins;wherein the first bonding layer is bonded to the second bonding layer;wherein the first access passage allows coolant within one or more first fin trenches to pass through the first semiconductor microcooler to one or more second fin trenches of the second semiconductor ...

LAMINATED CIRCUITRY COOLING FOR INTER-CHIP BRIDGES

The present invention includes embodiments of a semiconductor package designed to transfer heat from one or more bridges within the package to ambient external to the package in addition to conducting the heat through any semiconductor chips encapsulated within the package. A laminated substrate has one or more horizontal layer heat conduction paths and one or more vertical substrate heat conduction paths. The vertical substrate heat conduction paths collect heat from one or more of the horizontal layer heat conduction paths, and eventually conduct the heat out of the semiconductor package, e.g. into a lid or heat sink. 2. A package claim 1 , as in claim 1 , where one or more of the horizontal layers is a plane of material with high heat conductivity.3. A package claim 1 , as in claim 1 , where one or more of the vertical substrate heat conduction paths is made of vias that are either vertically stacked or offset vertically.4. A package claim 1 , as in claim 1 , where one or more of the horizontal layers is one or more conductive lines of material with high heat conductivity.5. A package claim 1 , as in claim 1 , where two or more of the horizontal layers have different cross-sectional areas.6. A package claim 5 , as in claim 5 , where the cross-sectional areas are determined by an amount of heat conducted through them.7. A package claim 5 , as in claim 5 , where the conductive lines are metal lines made of Copper (Cu).8. A semiconductor package comprising:two or more semiconductor chips (chips), each chip having one or more external electrical connections;one or more active bridges, the active bridge electrically connecting at least one of the electrical connections on a first chip to an electrical connection on a second chip, the active bridge producing heat while the chips and bridge are operating;a laminated substrate, the laminated substrate having a surface, one or more horizontal layers with low heat conductivity, and one or more horizontal layer heat ...

Multi Integrated Circuit Chip Carrier Package

A multi integrated circuit (IC) chip package includes multiple IC chips, a carrier, and a lid. The IC chips may be connected to the carrier. Alternatively, each IC chip may be connected to an interposer and multiple interposers may be connected to the carrier. The carrier may be positioned against a carrier deck. The lid may be positioned relative to carrier by aligning one or more alignment features within the lid with one or more respective alignment features of the carrier deck. A compression fixture cover may contact the lid and exert a force toward the carrier deck, the lid be loaded against respective IC chips, and the lid may be loaded against the carrier. While under compression, thermal interface material between respective the lid and respective IC chips and seal band material between the lid and the carrier may be cured. 1. An electronic device fabrication method comprising:positioning a multiple IC chip carrier against a carrier deck that comprises a plurality of first alignment features;aligning a lid, comprising a plurality of second alignment features, with the carrier deck by engaging the first alignment features with the second alignment features;connecting the lid to each IC chip of the multiple IC chip carrier; andremoving the multiple IC chip carrier from the carrier deck.2. The method of claim 1 , further comprising:connecting the lid to the multiple IC chip carrier3. The method of claim 2 , further comprising:applying a seal band material upon the multiple IC chip carrier around a circumference of each IC chip or applying a seal band material upon an underside surface of the lid.4. The method of claim 2 , further comprising:applying a thermal interface material upon an upper surface of each IC chip of the multiple IC chip carrier.5. The method of claim 2 , further comprising:applying a thermal interface material upon an underside surface of the lid.6. The method of claim 2 , further comprising:curing a seal band that exists between the lid and ...

Integrated Circuit Chip Carrier with In-Plane Thermal Conductance Layer

An integrated circuit (IC) chip carrier includes an IC chip electrically connected to an IC chip carrier by a plurality of chip-carrier contacts, a cover thermally connected the IC chip upper surface, and an in-plane thermal conductance (ITC) layer upon the IC chip carrier between the IC chip carrier and the IC chip. The ITC layer includes an extension tab connected to a vertical side surface of the cover. Heat is transferred vertically from the IC chip to the cover. Heat is also transferred vertically from the IC chip to the ITC layer. Heat is also transferred within the ITC layer through the ITC layer basal plane(s). The ITC layer basal plane(s) are positioned horizontally where the ITC layer is between the IC chip and the IC chip carrier. The ITC layer basal planes are positioned vertically where the extension tab contacts the vertical side surface of the cover. 1. An integrated circuit (IC) chip carrier comprising:an IC chip electrically connected to an IC chip carrier by a plurality of chip-carrier contacts;a cover thermally connected the IC chip upper surface; andan in-plane thermal conductance (ITC) layer upon the IC chip carrier between the IC chip carrier and the IC chip.2. The carrier of claim 1 , wherein the ITC layer comprises a plurality of openings therethrough claim 1 , each of the plurality of openings aligned with one of the plurality of chip-carrier contacts.3. The carrier of claim 1 , wherein the ITC layer comprises an opening therethrough claim 1 , the opening aligned around the circumference of the plurality of chip-carrier contacts.4. The carrier of claim 1 , wherein the ITC layer is an anisotropic material that has a first thermal conductivity through its basal plane and a second thermal conductivity through its plane orthogonal to the basal plane claim 1 , wherein the second thermal conductivity is lower than the first thermal conductivity.5. The carrier of claim 1 , wherein the ITC layer is a Graphite ITC layer.6. The carrier of claim 1 , ...

ELECTRONIC PACKAGE WITH TAPERED PEDESTAL

An electrical package may comprise a first substrate with a first substrate surface, and a microprocessor chip connected to the first substrate surface. The microprocessor chip may comprise a first chip surface that electrically connects to the first substrate surface, and a second chip surface located opposite the first chip surface. The electrical package may comprise a heat spreader assembly that comprises a lid section and a contact surface thermally connected to the second-chip surface. The electrical package may also comprise a pedestal between the contact surface and the lid section. The pedestal may comprise a first end that is located near the contact surface and a second end that is located near the lid section. The second end may be wider than the first end. 1. An electrical package comprising:a first substrate with a first substrate surface; a first chip surface that electrically connects to the first substrate surface; and', 'a second chip surface located opposite the first chip surface; and, 'at least one microprocessor chip connected to the first substrate surface, the microprocessor chip comprising a lid section;', 'a contact surface thermally connected to the second chip surface;', a first end that is connected to the contact surface; and', 'a second end that is connected to the lid section, wherein the pedestal is wider at the second end than at the first end., 'a pedestal between the contact surface and the lid section, the pedestal comprising], 'a heat-spreader assembly, the heat spreader assembly comprising2. The electrical package of claim 1 , further comprising a stiffener claim 1 , the stiffener comprising:a complementary stiffener surface that complements a shape of the pedestal, wherein the shape of the pedestal is defined by the first end of the pedestal and second end of the pedestal; anda lower stiffener surface.3. The electrical package of claim 2 , wherein the stiffener further comprises a top stiffener surface claim 2 , located ...

Direct bonded heterogeneous integration packaging structures

Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.

Circuit substrate with mixed pitch wiring

In some examples, an electronic package and methods for forming the electronic package are described. The electronic package can be formed by disposing an interposer on a surface of a substrate having a first pitch wiring density. The interposer can have a second pitch wiring density different from the first pitch wiring density. A layer of non-conductive film can be situated between the interposer and the surface of the substrate. A planarization process can be performed on a surface of the substrate. A solder resist patterning can be performed on the planarized surface the substrate. A solder reflow and coining process can be performed to form a layer of solder bumps on top of the planarized surface of the substrate. The interposer can provide bridge connection between at least two die disposed above the substrate. Solder bumps under the interposer electrically connect the substrate and the interposer.

COOLING STRUCTURE FOR ELECTRONIC BOARDS

A cooling structure for large electronic boards with closely-spaced heterogeneous die and packages is disclosed. The assembly includes a frame having a plurality of openings. The assembly further includes a cold plate mounted to the frame. The cold plate includes at least one inlet and at least one outlet and fluid channels in communication with the at least one inlet and the at least one outlet. The assembly further includes a heat sink mounted within each of the plurality of openings which in combination with sidewalls of the openings of the frame and the cold plate form individual compartments each of which are in fluid communication with the fluid channels. 1. An assembly , comprising:a frame having a plurality of openings;a cold plate mounted to the frame, the cold plate comprising at least one inlet and at least one outlet and fluid channels in communication with the at least one inlet and the at least one outlet; anda heat sink mounted within each of the plurality of openings which in combination with sidewalls of the openings of the frame and the cold plate form individual compartments each of which are in fluid communication with the fluid channels.2. The assembly of claim 1 , wherein:the fluid channels comprise an in input fluid channel and an output fluid channel;the input fluid channel is in fluid communication with each individual compartment through an input port communicating to each of the individual compartments; andthe output fluid channel is in fluid communication each individual compartment through an output port communicating to each of the individual compartments.3. The assembly of claim 2 , wherein each individual compartment is a sealed compartment.4. The assembly of claim 2 , wherein the cold plate includes grooves which are structured to accommodate sidewalls of the plurality of openings of the frame for mounting of the frame to the cold plate.5. The assembly of claim 4 , further comprising an o-ring within the grooves.6. The assembly of ...

LID ATTACH OPTIMIZATION TO LIMIT ELECTRONIC PACKAGE WARPAGE

An electronic package includes a carrier and a semiconductor chip. In a first aspect a lid is attached to the chip and subsequently the gap between the lid and the carrier is filled by a seal band that includes seal band material and a plurality of shim members. In another aspect, an interleaved seal band includes a pattern of a first type of seal band material and a second type of seal band material. In another aspect, the lid includes a plurality of surfaces at different topographies to reduce the thickness of the seal band between the topographic lid and the carrier. In yet another aspect the electronic package further includes a frame concentric with the chip. The lid is attached to the frame with a solder, epoxy or elastomer and placed on the chip with a thermal interface material. The seal band material is dispensed on the chip carrier and the frame is then moved towards the chip carrier allowing a minimum seal band thickness. 1. A method to fabricate an electronic package comprising:electronically connecting a semiconductor chip to a carrier;forming a gap between a perimeter bottom surface of a lid and the carrier as a result of thermally connecting the lid to the semiconductor chip;subsequent to thermally connecting the lid to the semiconductor chip, forming a first seal band upon the carrier concentric with the semiconductor chip in the gap between the perimeter bottom surface of the lid and the carrier; andsubsequent to forming the first seal band, inserting a plurality of shim members upon the first seal band in the gap between the perimeter bottom surface of the lid and the carrier.25.-. (canceled)6. The method of claim 1 , further comprising:applying a second seal band upon the plurality of shim members filling the gap between the perimeter bottom surface of the lid and the carrier.7. The method of claim 1 , wherein the seal-band material is an elastomeric material.820.-. (canceled)21. A method to fabricate an electronic package comprising: ...

LID ATTACH OPTIMIZATION TO LIMIT ELECTRONIC PACKAGE WARPAGE

An electronic package includes a carrier and a semiconductor chip. In a first aspect a lid is attached to the chip and subsequently the gap between the lid and the carrier is filled by a seal band that includes seal band material and a plurality of shim members. In another aspect, an interleaved seal band includes a pattern of a first type of seal band material and a second type of seal band material. In another aspect, the lid includes a plurality of surfaces at different topographies to reduce the thickness of the seal band between the topographic lid and the carrier. In yet another aspect the electronic package further includes a frame concentric with the chip. The lid is attached to the frame with a solder, epoxy or elastomer and placed on the chip with a thermal interface material. The seal band material is dispensed on the chip carrier and the frame is then moved towards the chip carrier allowing a minimum seal band thickness. 1. A electronic package comprising:a carrier comprising a top surface and a bottom surface;a semiconductor chip electrically connected to the top surface;a lid thermally connected to a top surface of the semiconductor chip, and;a seal band connected to the carrier and the lid perimeter and that surrounds two metal shim members, the seal band comprising a first bead of thermally compliant seal-band material connected to the top surface of the carrier, connected to respective lower sidewall surface portions of the two metal shim members, and connected to respective bottom surfaces of the two metal shim members and a second bead of thermally compliant seal-band material connected to the lid perimeter, connected to respective upper sidewall surface portions of the two metal shim members, and connected to respective top surfaces of the two metal shim members.25.-. (canceled)6. The electronic package of claim 1 , wherein the seal-band fills a gap between the carrier and an underside of the lid.7. The electronic package of claim 1 , wherein the ...

Semiconductor Microcooler

A stacked semiconductor microcooler includes a first and second semiconductor microcooler. Each mircocooler includes silicon fins extending from a silicon substrate. A metal layer may be formed upon the fins. The microcoolers may be positioned such that the fins of each microcooler are aligned. One or more microcoolers may be thermally connected to a surface of a coolant conduit that is thermally connected to an electronic device heat generating device, such as an integrated circuit (IC) chip, or the like. Heat from the electronic device heat generating device may transfer to the one or more microcoolers. A flow of cooled liquid may be introduced through the conduit and heat from the one or more microcoolers may transfer to the liquid coolant.

Cooling and power delivery for a wafer level computing board

A computing device includes a wafer having multiple layers, the wafer including a top layer and sublayers disposed below it, the sublayers including one or more memory devices. The computing device also includes two or more shaped retainer elements shaped to mate with and at least partially surround at least the top of the wafer and in electrical contact with one or more chips disposed on a top of the top layer and a holding device that mates with the retainer elements to provide at least power to the retaining elements. So arranged, the wafer may be cooled.

HEAT SPREADING LAYER WITH HIGH THERMAL CONDUCTIVITY

Embodiments of the invention comprise a homogeneous heat spreading cap element in chip packages to facilitate better heat spreading and dissipation. The heat spreading cap comprises a single high-K graphite layer supported by a copper frame for increased stability and reduced thermal warpage during handling and operation while minimizing thermal penalty by reducing the amount of material having a relatively low heat conductivity that is needed in conventional heat spreading caps. 1. A cooling system for a semiconductor package comprising:a heat spreading layer partially encased in a supporting frame, the heat spreading layer including a perimeter, the supporting frame being configured to encase the perimeter and an adjacent portion of the heat spreading layer, defining centrally exposed top and bottom portions of the heat spreading layer; anda heat generating element thermally connected to the centrally exposed bottom portion of the heat spreading layer.2. The system of claim 1 , wherein the semiconductor package is a flip chip ball grid array package claim 1 , a flip chip land grid array package claim 1 , or a flip chip pin grid array package.3. The system of claim 1 , wherein the semiconductor package is a wire bonding assembly package.4. The system of claim 3 , wherein the centrally exposed bottom portion of the heat spreading layer further comprises a centrally protruding portion connected to a central portion of a top surface of the heat generating element.5. The system of claim 1 , wherein the heat spreading layer is made from graphite.6. The system of wherein the heat spreading layer is positioned to have high thermal conductivity in a first direction being substantially perpendicular relative to the substrate claim 5 , and relatively high thermal conductivity in at least a second direction substantially parallel relative to the substrate.7. The system of claim 1 , wherein the heat spreading layer is made from pyrolytic graphite.8. The system of claim 1 , ...

Chip corner guard for chip-package interaction failure mitigation

An integrated circuit (IC) package, and a method for fabricating an IC package is described. A set of semiconductor chips, a set of corner guard structures and a chip carrier are provided. The set of semiconductor chips and the set of corner guard structure placed and bonded to a first surface of the chip carrier. The set of semiconductor chips are in electrical contact with the chip carrier. Respective corner guard structures are placed proximate to the corners of respective semiconductor chips. The coefficient of thermal expansion (CTE) of the set of corner guard structures is selected to ameliorate chip-package interaction (CPI) related failures due to differences between a CTE of the set of semiconductor chips and a CTE of the chip carrier.

Mixed Under Bump Metallurgy (UBM) Interconnect Bridge Structure

An electronic package and a method of manufacture includes a substrate having an upper surface with a trench formed in a bridge region. First pads are arranged on the upper surface of the substrate, outside of the bridge region, and a bridge is positioned in the trench. A plurality of second pads are arranged on an upper surface of the bridge. A plurality of pillars are electrically coupled to the plurality of second pads. Two or more semiconductor chips are positioned in a side-by-side proximal arrangement overlaying the bridge and the substrate. A first semiconductor chip is joined to the bridge, then a second semiconductor chip is joined to the bridge, followed by attaching the chip-bridge assembly to the substrate with the bridge positioned within the substrate trench. Each of the two or more semiconductor chips have first electrical connections including bumps, and second electrical connections including third pads. 1. An electronic package , comprising:a substrate having an upper surface with a trench formed in a bridge region;a plurality of first pads arranged on the upper surface of the substrate, outside of the bridge region;a bridge positioned in the trench;a plurality of second pads arranged on an upper surface of the bridge;a plurality of pillars, each of the pillars having a first end and a second end, the first end being electrically coupled to one of the plurality of second pads; and the upper surface of the bridge need not be aligned with the upper surface of the substrate:', 'each of the two or more semiconductor chips have a plurality of first electrical connections including bumps,', 'each of the bumps is configured to correspond to and electrically couple with one pad of the plurality of first pads outside of the bridge region,', 'each of the two or more semiconductor chips includes a plurality of second electrical connections including third pads, and', 'each one of the third pads is configured to correspond to and electrically couple with the ...

LID ATTACH OPTIMIZATION TO LIMIT ELECTRONIC PACKAGE WARPAGE

An electronic package includes a carrier and a semiconductor chip. In a first aspect, a lid is attached to the chip and subsequently the gap between the lid and the carrier is filled by a seal band that includes seal band material and a plurality of shim members. In another aspect, an interleaved seal band includes a pattern of a first type of seal band material and a second type of seal band material. In another aspect, the lid includes a plurality of surfaces at different topographies to reduce the thickness of the seal band between the topographic lid and the carrier. In yet another aspect the electronic package further includes a frame concentric with the chip. The lid is attached to the frame with a solder, epoxy or elastomer and placed on the chip with a thermal interface material. The seal band material is dispensed on the chip carrier and the frame is then moved towards the chip carrier allowing a minimum seal band thickness. 1. A method to fabricate an electronic package comprising:electronically connecting a semiconductor chip to a carrier;forming a gap between a lid and the carrier by thermally connecting the lid to the semiconductor chip;subsequent to thermally connecting the lid to the semiconductor chip, inserting a plurality of shim members upon the carrier in the gap between the lid and the carrier; andsubsequent to inserting the plurality of shim members, forming a seal band upon the plurality of shim members within the gap to connect the lid and the carrier.2. The method of claim 1 , wherein forming a seal band upon the plurality of shim members comprises:injecting the seal band upon respective upper surfaces of each of the plurality of shim members.3. The method of claim 2 , wherein forming a seal band upon the plurality of shim members comprises:injecting the seal band upon at least one side surface of each of the plurality of shim members.4. The method of claim 3 , wherein the seal band comprises an elastomeric material.5. The method of claim 3 ...

DETERMINING MAGNITUDE OF COMPRESSIVE LOADING

An apparatus for determining a magnitude of a compressive load applied to a piston including a compliant film disposed between first and second elements is provided. The apparatus includes a first part movable with the first element in a movement direction along which the magnitude of the compressive load is to be determined, a second part movable with the second element in the movement direction and a sensor to measure a distance between the first and second parts in the movement direction, the measured distance being related to a deformation of the compliant film as the compressive load is applied. 1. An apparatus for determining a magnitude of a compressive load , the apparatus comprising:a cap affixed to and movable with an upper portion of a piston in a movement direction along which the magnitude of the compressive load is to be determined;a spring disposed in contact with the cap;a pin disposed to extend through the upper portion of the piston and urged by the spring toward a lower portion of the piston, the pin being thereby movable with the lower portion of the piston in the movement direction; anda sensor to measure a distance between the cap and the pin in the movement direction, the measured distance being related to a deformation of a compliant film disposed between the upper and lower portions as the compressive load is applied.2. The apparatus according to claim 1 , wherein a plane of a surface of the cap is recessed from a corresponding plane of a surface of the upper portion of the piston.3. The apparatus according to claim 1 , further comprising a bushing disposed within the upper portion of the piston through which the pin extends.4. The apparatus according to claim 1 , wherein the sensor comprises a capacitive sensor.5. A method for determining a magnitude of a compressive load claim 1 , the method comprising:machining a through-hole in an upper portion of a piston;disposing in the through-hole a sensor assembly apparatus including a cap movable ...

LAMINATED STIFFENER TO CONTROL THE WARPAGE OF ELECTRONIC CHIP CARRIERS

A technique relates to an electronic package. A substrate is configured to receive a chip. A stiffener is attached to the substrate. The stiffener includes a core material with a first material formed on opposing sides of the core material. 1. An electronic package comprising:a substrate configured to receive a chip; anda stiffener attached to the substrate, the stiffener comprising a core material with a first material formed on opposing sides of the core material, wherein a coefficient of thermal expansion (CTE) of the stiffener and the substrate matches through a predefined range of temperatures.2. The electronic package of claim 1 , wherein the core material comprises at least one material in the substrate.3. The electronic package of claim 1 , wherein the first material is copper.4. The electronic package of claim 1 , wherein a second material is formed on opposing sides of the core material.5. The electronic package of claim 4 , wherein the second material is a dielectric material.6. The electronic package of claim 4 , wherein vias are formed through the second material claim 4 , the vias being filled with the first material.7. The electronic package of claim 1 , wherein the CTE of the stiffener and the substrate positively correlates through the predefined range of temperatures.8. A method of forming an electronic package claim 1 , the method comprising:providing a substrate configured to receive a chip, the substrate comprising a laminate stack; andattaching a stiffener to the substrate, the stiffener comprising a core material with a first material formed on opposing sides of the core material, wherein a coefficient of thermal expansion (CTE) of the stiffener and the substrate matches through range of temperatures, the core material comprising a core laminate stack matching the laminate stack of the substrate.9. (canceled)10. The method of claim 8 , wherein the first material is copper.11. The method of claim 8 , wherein a second material is formed on ...

ADJUSTABLE HEAT SINK FIN SPACING

A heat sink includes a heat sink base, a first fin, and a second fin. The spacing between the base and the first fin and the second fin, restively, may be adjusted by rotating a threaded rod. The threaded rod includes a first threaded knurl that is engaged with the first fin and a second threaded knurl that is engaged with the second fin. The thread pitch of the first threaded knurl and the second threaded knurl may differ. For example, the pitch of the first threaded knurl may be smaller than the pitch of the second threaded knurl if the first fin is located nearest the heat sink base relative to the second fin. The spacing of the heat sink fins may be adjusted based upon the current operating conditions of the electronic device to maintain an optimal temperature of a heat generating device during device operation. 1. A heat sink comprising:a heat sink base comprising an underside and a topside;a first heat sink fin comprising a first threaded opening;a second heat sink fin comprising a second threaded opening, the first heat sink fin located nearest the heat sink base relative to the second heat sink fin; anda threaded rod comprising a first threaded knurl comprising first threads of a first thread pitch that engage with threads of the first threaded opening and a second threaded knurl comprising second threads of a second thread pitch that engage with threads of the second threaded opening.2. The heat sink of claim 1 , further comprising a motor that rotates the threaded rod about an axis orthogonal to the topside of the heat sink base.3. The heat sink of claim 2 , wherein upon the rotation of the threaded rod claim 2 , the first fin is displaced against the first threaded knurl by a first dimension along the axis and the second fin is displaced against the second threaded knurl by a second dimension along the axis.4. The heat sink of claim 3 , wherein the first thread pitch is smaller than the second thread pitch and wherein the first dimension is smaller than ...

DIRECT BONDED HETEROGENEOUS INTEGRATION PACKAGING STRUCTURES

Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate. 1. An integrated circuit packaging structure free of an interposer layer , the integrated circuit packaging structure comprising:a packaging substrate comprising first and second opposing surfaces, and a trench provided in the first opposing surface, wherein the first opposing surface defining the trench is free to electrical connections;a bridge disposed in the trench; andat least two chips in a side by side arrangement overlying the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement, the at least two chips comprising a plurality of electric connections coupled to corresponding electrical connections on the bridge and on the packaging substrate, wherein each of the at least two chips are supported completely by the corresponding electrical connections and an underfill material.2. The integrated circuit packaging structure of claim 1 , further comprising a lid and a thermal interface material overlaying the chips.3. The integrated circuit packaging structure of claim 1 , further comprising an underfill material between the plurality of electrical connections coupled to the corresponding electrical ...

THREE-DIMENSIONAL MICROELECTRONIC PACKAGE WITH EMBEDDED COOLING CHANNELS

The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.

OPTIMIZED WEIGHT HEAT SPREADER FOR AN ELECTRONIC PACKAGE

A heat spreader is disclosed with regions where material is absent to reduce the mass/weight of the heat spreader without substantially reducing the temperature of the semiconductor chip and without substantially affecting the warpage and mechanical stress/strain in the electronic package. 2. A heat spreader claim 1 , as in claim 1 , wherein the central top surface and central bottom surface are flat.3. A heat spreader claim 1 , as in claim 1 , wherein the thickness decreases linearly.4. A heat spreader claim 1 , as in claim 1 , wherein the thickness decreases convexly.5. A heat spreader claim 1 , as in claim 1 , wherein the thickness decreases concavely.6. A heat spreader claim 1 , as in claim 1 , wherein a semiconductor chip is placed within the space created and a chip top surface of the chip is connected to the central bottom surface of the heat spreader such that heat generated by the chip is transported into the heat spreader though a thermal interface material.7. A heat spreader claim 6 , as in claim 6 , wherein the central bottom surface overlaps the chip top surface.8. A heat spreader claim 1 , as in claim 1 , wherein the outer top periphery steps down from the top surface.9. A heat spreader claim 1 , as in claim 1 , wherein the outer top periphery has a vertical projection that partially overlaps the transition bottom region.11. A system claim 10 , as in claim 10 , where the lip is connected to the carrier surface by a seal band adhesive.12. A system claim 10 , as in claim 10 , where the semiconductor chip is thermally connected to the central bottom surface by imposing a heat conductive sealer between the chip top surface and the central bottom surface.13. A system claim 10 , as in claim 10 , further comprising a heat sink thermally connected to the central top surface by interposing a heat conductive sealer between the heat sink and the central top surface.14. A method of designing a heat spreader comprising the steps of:selecting a base case heat ...

COOLING STRUCTURE FOR ELECTRONIC BOARDS

A cooling structure for large electronic boards with closely-spaced heterogeneous die and packages is disclosed. The assembly includes a frame having a plurality of openings. The assembly further includes a cold plate mounted to the frame. The cold plate includes at least one inlet and at least one outlet and fluid channels in communication with the at least one inlet and the at least one outlet. The assembly further includes a heat sink mounted within each of the plurality of openings which in combination with sidewalls of the openings of the frame and the cold plate form individual compartments each of which are in fluid communication with the fluid channels. 1. A manifold assembly , comprising:a frame assembly having a plurality of sealed compartments each comprising a single heat sink registered to an underlying chip and/or package mounted on an electronic board;a fluid channel within the frame assembly; andan inlet and an outlet associated with each of the sealed compartments and in fluid communication with the fluid channel, the inlet and the outlet directing coolant over the single heat sink of each of the sealed compartments, a plurality of openings in a frame; and', 'a cold plate assembly sealed to sidewalls of the openings of a bottom plate,', 'fluid channels in the cold plate which includes the inlet and outlet for each of the sealed compartments, and, 'wherein the frame assembly includeswherein the heat sink includes fins which are one of cuboidal, cylindrical pin fins, channels that are parallel and trapezoidal.2. The manifold assembly of claim 1 , wherein the heat sink is provided in each of the plurality of openings attached to the sidewalls of the openings.3. The manifold assembly of claim 2 , wherein the heat sink in each of the plurality of openings is registered and spans over at least one underlying chip or package mounted on an electronic board and mounted thereon by a thermal interface material (TIM).4. A manifold assembly claim 2 , comprising: ...

Cooling structure for electronic boards

A cooling structure for large electronic boards with closely-spaced heterogeneous die and packages is disclosed. The assembly includes a frame having a plurality of openings. The assembly further includes a cold plate mounted to the frame. The cold plate includes at least one inlet and at least one outlet and fluid channels in communication with the at least one inlet and the at least one outlet. The assembly further includes a heat sink mounted within each of the plurality of openings which in combination with sidewalls of the openings of the frame and the cold plate form individual compartments each of which are in fluid communication with the fluid channels.

Heat spreading layer with high thermal conductivity

Embodiments of the invention comprise a homogeneous heat spreading cap element in chip packages to facilitate better heat spreading and dissipation. The heat spreading cap comprises a single high-K graphite layer supported by a copper frame for increased stability and reduced thermal warpage during handling and operation while minimizing thermal penalty by reducing the amount of material having a relatively low heat conductivity that is needed in conventional heat spreading caps.

HEAT SPREADING LAYER WITH HIGH THERMAL CONDUCTIVITY

Embodiments of the invention comprise a homogeneous heat spreading cap element in chip packages to facilitate better heat spreading and dissipation. The heat spreading cap comprises a single high-K graphite layer supported by a copper frame for increased stability and reduced thermal warpage during handling and operation while minimizing thermal penalty by reducing the amount of material having a relatively low heat conductivity that is needed in conventional heat spreading caps. 1. A cooling system for a semiconductor package comprising:a heat spreading layer partially encased in a supporting frame, the heat spreading layer including a perimeter, the supporting frame being configured to encase the perimeter and an adjacent portion of the heat spreading layer, defining centrally exposed top and bottom portions of the heat spreading layer; anda heat generating element thermally connected to the centrally exposed bottom portion of the heat spreading layer.212-. (canceled)13. The system of claim 1 , wherein the supporting frame is made from a metal.1419-. (canceled)20. The system of claim 1 , wherein a top surface and/or a bottom surface of the heat spreading layer is chamfered.2125-. (canceled) This invention relates generally to the field of controlling thermal conduction in computer chip packaging, and more specifically to a heat spreading cap structure having high thermal conductivity.Innovations in semiconductor fabrication and packaging technologies have enabled development of high performance, densely integrated semiconductor chip modules. The downscaling of chip geometries and the increase in operating speeds lead to increased power densities, resulting in more heat generation per unit area. The increased power density poses practical limitations to the level of integration density and performance that may be achieved. The ability to implement chip modules with higher densities and higher performance is limited primarily by the ability to effectively cool the ...

Heat spreading layer with high thermal conductivity

Embodiments of the invention comprise a homogeneous heat spreading cap element in chip packages to facilitate better heat spreading and dissipation. The heat spreading cap comprises a single high-K graphite layer supported by a copper frame for increased stability and reduced thermal warpage during handling and operation while minimizing thermal penalty by reducing the amount of material having a relatively low heat conductivity that is needed in conventional heat spreading caps.

HEAT SPREADING LAYER WITH HIGH THERMAL CONDUCTIVITY

Embodiments of the invention comprise a homogeneous heat spreading cap element in chip packages to facilitate better heat spreading and dissipation. The heat spreading cap comprises a single high-K graphite layer supported by a copper frame for increased stability and reduced thermal warpage during handling and operation while minimizing thermal penalty by reducing the amount of material having a relatively low heat conductivity that is needed in conventional heat spreading caps. 1. A cooling system for a semiconductor package comprising:a heat spreading layer partially encased in a supporting frame, the heat spreading layer including a perimeter, the supporting frame being configured to encase the perimeter and an adjacent portion of the heat spreading layer, defining centrally exposed top and bottom portions of the heat spreading layer; anda heat generating element thermally connected to the centrally exposed bottom portion of the heat spreading layer.221-. (canceled)22. A semiconductor package , comprising:a substrate;a chip electrically connected to the substrate;a thermal module having a heat spreading layer partially encased in a supporting frame, the heat spreading layer including a perimeter, the supporting frame being configured to encase the perimeter and an adjacent portion of the heat spreading layer, defining centrally exposed top and bottom portions of the heat spreading layer, wherein the chip is thermally connected to the centrally exposed bottom portion of the heat spreading layer; anda circuit board electrically connected to the substrate and the chip.2325-. (canceled) This invention relates generally to the field of controlling thermal conduction in computer chip packaging, and more specifically to a heat spreading cap structure having high thermal conductivity.Innovations in semiconductor fabrication and packaging technologies have enabled development of high performance, densely integrated semiconductor chip modules. The downscaling of chip ...

Heat spreading layer with high thermal conductivity

Embodiments of the invention comprise a homogeneous heat spreading cap element in chip packages to facilitate better heat spreading and dissipation. The heat spreading cap comprises a single high-K graphite layer supported by a copper frame for increased stability and reduced thermal warpage during handling and operation while minimizing thermal penalty by reducing the amount of material having a relatively low heat conductivity that is needed in conventional heat spreading caps.

Heat spreading layer with high thermal conductivity

Embodiments of the invention comprise a homogeneous heat spreading cap element in chip packages to facilitate better heat spreading and dissipation. The heat spreading cap comprises a single high-K graphite layer supported by a copper frame for increased stability and reduced thermal warpage during handling and operation while minimizing thermal penalty by reducing the amount of material having a relatively low heat conductivity that is needed in conventional heat spreading caps.

ADJUSTABLE HEAT SINK FIN SPACING

A heat sink includes a first fin and a second fin. The spacing between the first fin and the second fin may be adjusted by a threaded rod. The threaded rod may include a first portion that is engaged with the first fin and a second portion that is engaged with the second fin. The thread pitch of the first portion and the second portion may differ. For example, the pitch of a first internal thread of the first fin may be smaller than the pitch of a second internal thread of the second fin. The spacing of the heat sink fins may be adjusted based upon the current operating conditions of the electronic device to maintain an optimal temperature of a heat generating device during device operation. 1. A heat sink comprising:a first heat sink fin comprising a first internal thread;a second heat sink fin comprising a second internal thread of a different thread pitch relative to the first internal thread; anda threaded rod comprising: a first portion comprising a first external thread that engages with the first internal thread; and a second portion comprising a second external thread that engages with the second internal thread.2. The heat sink of claim 1 , further comprising a motor that rotates the threaded rod.3. The heat sink of claim 2 , wherein upon the rotation of the threaded rod claim 2 , the first fin is displaced against the first portion by a first dimension and the second fin is displaced against the second portion by a second dimension.4. The heat sink of claim 1 , wherein the pitch of the first internal thread is smaller than the pitch of the second internal thread.5. The heat sink of claim 1 , wherein rotation of the first heat sink fin is fixed relative to rotation of the second heat sink fin.6. The heat sink of claim 1 , further comprising:a first fin temperature sensing device that measures temperature of the first heat sink fin.7. The heat sink of claim 6 , further comprising:a second fin temperature sensing device that measures temperature of the second ...

ADJUSTABLE HEAT SINK FIN SPACING

A heat sink includes a threaded rod. The spacing between a first fin and a second fin of the heat sink may be adjusted by the threaded rod. The threaded rod includes a first portion and a second portion. The first portion may engage with the first fin and a second portion may engage with the second fin. The thread pitch of the first portion and the second portion may differ. For example, the pitch of a first knurl of the threaded rod may be smaller than the pitch of a second threaded knurl of the threaded rod. The spacing of the heat sink fins may be adjusted based upon the current operating conditions of the electronic device to maintain an optimal temperature of a heat generating device during device operation. 1. A heat sink comprising: a first portion comprising a first external thread; and', 'a second portion comprising a second external thread of different pitch than the first external thread., 'a threaded rod comprising2. The heat sink of claim 1 , further comprising a motor that rotates the threaded rod.3. The heat sink of claim 1 , wherein the pitch of the first external thread is smaller than the pitch of the second external thread.4. The heat sink of claim 1 , wherein the first portion and the second portion share a same axis of rotation.5. The heat sink of claim 4 , wherein the first portion further comprises one or more protrusions.6. The heat sink of claim 4 , wherein the second portion comprises one or more receptacles configured to accept the one or more protrusions.7. The heat sink of claim 1 , wherein the pitch of the first portion is configured to be the same as a first internally threaded hole of a first heat sink fin of the heat sink.8. The heat sink of claim 7 , wherein the pitch of the second portion is configured to be the same as a second internally threaded hole of a second heat sink fin of the heat sink.9. The heat sink of claim 1 , wherein first external thread is configured to engage with a first internally threaded hole of a first heat ...

MICRO-FLUIDIC CHANNELS HAVING VARIOUS CRITICAL DIMENSIONS

Embodiments of the present invention are directed to microchannels having varied critical dimensions for efficient cooling of semiconductor integrated circuit chip packages. In a non-limiting embodiment of the invention, a patterning stack is formed over a substrate. The patterning stack includes a hard mask, an etch transfer layer on the hard mask, and a photoresist on the etch transfer layer. A manifold trench is formed in a first region of the substrate and is recessed below a surface of the etch transfer layer. A microchannel trench is formed in a second region of the substrate to expose the surface of the etch transfer layer. The manifold trench and the microchannel trench are recessed such that the manifold trench extends into the hard mask and the microchannel trench extends into the etch transfer layer. A manifold and a microchannel are formed in the substrate by pattern transfer. 1. A method for forming a semiconductor device , the method comprising:forming a patterning stack over a substrate, the patterning stack comprising a hard mask, an etch transfer layer on the hard mask, and a photoresist on the etch transfer layer;forming a manifold trench in a first region of the substrate, the manifold trench recessed below a surface of the etch transfer layer;forming a microchannel trench in a second region of the substrate, the microchannel trench exposing the surface of the etch transfer layer;recessing the manifold trench and the microchannel trench such that the manifold trench extends into the hard mask and the microchannel trench extends into the etch transfer layer; andforming a manifold and a microchannel in the substrate.2. The method of claim 1 , wherein forming the manifold and the microchannel comprises a pattern transfer of the manifold trench and the microchannel trench into the substrate.3. The method of claim 1 , wherein the manifold trench and the microchannel trench are recessed concurrently during a same etch process.4. The method of further ...

Electronic package with tapered pedestal

An electrical package may comprise a first substrate with a first substrate surface, and a microprocessor chip connected to the first substrate surface. The microprocessor chip may comprise a first chip surface that electrically connects to the first substrate surface, and a second chip surface located opposite the first chip surface. The electrical package may comprise a heat spreader assembly that comprises a lid section and a contact surface thermally connected to the second-chip surface. The electrical package may also comprise a pedestal between the contact surface and the lid section. The pedestal may comprise a first end that is located near the contact surface and a second end that is located near the lid section. The second end may be wider than the first end.

Reliability enhancement of metal thermal interface

A frontside of a chip is bonded to a top surface of a chip carrier. Seal material is dispensed at a periphery of the top surface of the chip carrier. A solder TIM having a first side and a second side is provided. The first side of the TIM contacts a backside of the chip. A reflow is performed to melt the TIM. The second side of the TIM is bonded to a lid. The seal material is cured. The lid is attached to the top surface of the chip carrier. Backfill material is injected into a space between the top surface of the chip carrier and the lid. The backfill material abuts sides of the TIM. The backfill material is cured. TIM solder cracking and associated thermal degradation are mitigated.

Method of forming an electronic package

A technique relates to an electronic package. A substrate is configured to receive a chip. A stiffener is attached to the substrate. The stiffener includes a core material with a first material formed on opposing sides of the core material.

Chip package having chip extension and method

A chip package including a chip extension for containing thermal interface material (TIM) and improves chip cooling, and a related method, are disclosed. In particular, the chip package includes a chip, a cooling structure coupled to the chip via a TIM, and a chip extension may be thermally coupled to an outer edge of the chip. A TIM placed between the chip and the cooling structure is contained during thermal cycling by the chip extension such that void formation at the edge of the chip, which can move between the chip and cooling structure, is suppressed. The chip extension also improves lateral heat dissipation by providing a greater thermal contact area between the cooling structure and the chip and, if needed, the substrate at a much lower cost than using larger die with lower production unit output from a wafer.

Multichip module with stiffening frame and associated covers

A multichip module includes a carrier, a stiffening frame, a plurality of semiconductor chips, and a plurality of covers. The carrier has a top surface and a bottom surface configured to be electrically connected to a motherboard. The stiffening frame includes a plurality of openings that accept the plurality of semiconductor chips and may be attached to the top surface of the carrier with an adhesive that absorbs dimensional changes between the stiffening frame and the carrier. The semiconductor chips are concentrically arranged within the plurality of openings of the stiffening frame and the plurality of covers are attached to the stiffening frame so as to enclose the plurality of openings.

Optimized thermally conductive plate and attachment method for enhanced thermal performance and reliability of flip chip organic packages

Disclosed are thermally conductive plates. Each plate is configured such that a uniform adhesive-filled gap may be achieved between the plate and a heat generating structure when the plate is bonded to the heat generating structure and subjected to a temperature within a predetermined temperature range that causes the heat generating structure to warp. Additionally, this disclosure presents the associated methods of forming the plates and of bonding the plates to a heat generating structure. In one embodiment the plate is curved and modeled to match the curved surface of a heat generating structure within the predetermined temperature range. In another embodiment the plate is a multi-layer conductive structure that is configured to undergo the same warpage under a thermal load as the heat generating structure. Thus, when the plate is bonded with the heat generating structure it is able to achieve and maintain a uniform adhesive-filled gap at any temperature.

Three-dimensional microelectronic package with embedded cooling channels

The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.

Copper microcooler structure and fabrication

Techniques that facilitate a copper microcooler structure are provided. In one example, a device includes a first copper microcooler structure and a second copper microcooler structure. The first copper microcooler structure includes a first copper plate and a first set of copper channels attached to the first copper plate. The second copper microcooler structure includes a second copper plate and a second set of copper channels attached to the second copper plate. A surface of the second copper plate associated with the second copper microcooler structure is bonded to one or more surfaces of the first set of copper channels associated with the first copper microcooler structure via a fusion bond.

Chip package assembly using chip heat to cure and verify

Methods of assembling a chip package are disclosed that employ heat from test pattern operation of the chip to cure a thermal interface material. The methods may also simultaneously verify thermal performance of the package using the heat from test pattern operation. Further, the heat may be used to cure the sealing material and/or underfill material, where they are used.

Cooling structure for electronic boards

A cooling structure for large electronic boards with closely-spaced heterogeneous die and packages is disclosed. The assembly includes a frame having a plurality of openings. The assembly further includes a cold plate mounted to the frame. The cold plate includes at least one inlet and at least one outlet and fluid channels in communication with the at least one inlet and the at least one outlet. The assembly further includes a heat sink mounted within each of the plurality of openings which in combination with sidewalls of the openings of the frame and the cold plate form individual compartments each of which are in fluid communication with the fluid channels.

Mechanical barrier element for improved thermal reliability of electronic components

Embodiments of the invention are generally related to packaging of integrated circuit devices, and more specifically to the placement of thermal paste for cooling an integrated circuit device during operation. A barrier element may be placed along at least one side of an integrated circuit chip. The barrier element may contain thermal paste pumped out during expansion and contraction of the package components to areas near the chip. The barrier element may also form a reservoir to replenish thermal paste that is lost during thermal pumping of the paste.

Adjustable heat sink fin spacing

A heat sink includes a heat sink base, a first fin, and a second fin. The spacing between the base and the first fin and the second fin, restively, may be adjusted by rotating a threaded rod. The threaded rod includes a first threaded knurl that is engaged with the first fin and a second threaded knurl that is engaged with the second fin. The thread pitch of the first threaded knurl and the second threaded knurl may differ. For example, the pitch of the first threaded knurl may be smaller than the pitch of the second threaded knurl if the first fin is located nearest the heat sink base relative to the second fin. The spacing of the heat sink fins may be adjusted based upon the current operating conditions of the electronic device to maintain an optimal temperature of a heat generating device during device operation.

Multi-chip package structures formed with interconnect bridge devices and chip packages with discrete redistribution layers

Techniques are provided for constructing multi-chip package structures. For example, a multi-chip package structure includes a package substrate, an interconnect bridge device, a first chip package, and a second chip package. The first chip package includes a first redistribution layer structure, and a first integrated circuit chip connected to the first redistribution layer structure. The first redistribution layer structure is connected to the interconnect bridge device and to the package substrate. The second chip package includes a second redistribution layer structure, and a second integrated circuit chip connected to the second redistribution layer structure. The second redistribution layer structure is connected to the interconnect bridge device and to the package substrate. The interconnect bridge device includes wiring to provide package-to-package connections between the first and second chip packages.

Electronic package with varying interconnects

A flip chip device and methods for fabrication are provided. An interconnect layer for a device include a plurality of solder bumps arranged within the interconnect layer. A first subset of the plurality of solder bumps has a first cross-sectional area, where the first subset is arranged along a first position at a first edge of the interconnect layer. A second subset of the plurality of solder bumps has a second cross-sectional area, where the second subset is arranged at a second position of the interconnect layer. A third subset of the plurality of solder bumps is arranged between the first position and the second position, where the third subset has a plurality of cross-sectional areas.

Fatigue failure resistant eletronic package

A chip package comprises a chip having a first temperature sensor. The first temperature sensor is configured to measure a first temperature of the chip in a localized area around the first temperature sensor. The chip package also includes a chip carrier coupled to the chip via a plurality of solder connections. The chip carrier includes a second temperature sensor vertically aligned with the first temperature sensor. The second temperature sensor is configured to measure a second temperature of the chip carrier in a localized area around the second temperature sensor. The chip carrier further includes a localized heater element located near the second temperature sensor and configured to generate heat in response to a detected difference based on comparison of the first temperature and the second temperature such that the detected difference is adjusted in the localized area around the first temperature sensor.

Electrical-optical bridge chip and integrated circuit packaging structure

A bridge chip of an IC packaging structure includes E/O and O/E converters and a first wiring pattern interconnecting the converters to host chips and a second wiring pattern electrically connected to the host chips. An optical interface outputs the optical signals from a backside surface of the bridge chip. The optical interface receives optical signals through the backside surface. Electrical through links connected to the second wiring pattern output electrical signals generated by the host chips through the backside surface of the bridge chip. The packaging structure includes substrate with a trench provided in the top surface of the substrate and the bridge chip disposed in the trench. The host chips are directly connected to the top surface of the bridge chip and the top surface of the substrate. Optical signals are output from the packaging structure through an opening in the bottom surface of the substrate.

Electronic package structure with offset stacked chips and top and bottom side cooling lid

An electronic structure includes offset three-dimensional stacked chips; and a two-piece lid structure configured to extract heat from the bottom and top of the stacked chips.

Direct bonded heterogeneous integration silicon bridge

A direct bonded heterogeneous integration (DBHi) device includes a substrate including a trench formed in a top surface of the substrate. The DBHi device further includes a first chip coupled to the substrate on a first side of the trench by a plurality of first interconnects. The DBHi device further includes a second chip coupled to the substrate on a second side of the trench by a plurality of second interconnects. The second side of the trench is arranged opposite the first side of the trench. The DBHi device further includes a bridge coupled to the first chip and to the second chip by a plurality of third interconnects such that the bridge is suspended in the trench. The DBHi device further includes a non-conductive paste material surrounding the plurality of third interconnects to further couple the bridge to the first chip and to the second chip.

Rehealable and reworkable polymer for electronic packaging

A composition, process, and device are disclosed. The composition includes a polymer formed by reacting an epoxy compound with an amine curing agent. The epoxy compound comprises a Diels-Alder dimer and an ester moiety. The process includes providing a polymer formed by reacting the epoxy compound with the amine curing agent. The device includes a material that includes the polymer.

Electronic device console with natural draft cooling

An electronic device console includes a console body that houses a chip package, and a duct extending from the console body. An interior volume of the duct is in fluid communication with an interior volume of the console body. A first vent is at a distal end of the duct. A second vent is in a wall of the console body. The console may be oriented in a first orientation and a second orientation. The duct functions as a chimney for natural convection cooling of the chip package when the console is oriented in the first orientation. The console body functions as a chimney for natural convection cooling of the chip package when the console is oriented in the second orientation.

Architecture and device using optical element and computer chip for optical signal transmission

A device and associated method include using an optical element (OE) for electrical and optical communications on the device. A substrate includes a wiring layer with an optically transparent path which allows optical signals to pass therethrough. An optical coupling layer is coupled to the wiring layer, and the optical coupling layer includes at least one micro-lens for focusing or collimating the optical signals through the transparent path. An OE is coupled to the wiring layer, and the OE is positioned in optical alignment with the optically transparent path for communicating optical signals. One or more semiconductor chips can be communicatively coupled to an OE for controlling the OE.

Fatigue failure resistant eletronic package

A chip package 100 comprises a chip 102 having a first temperature sensor 108 configured to measure a first temperature of the chip in a localized area around the first temperature sensor. The chip package also includes a chip carrier 104 coupled to the chip via a plurality of solder connections 106. The chip carrier includes a second temperature sensor 112 vertically aligned with the first temperature sensor. The second temperature sensor is configured to measure a second temperature of the chip carrier in a localized area around the second temperature sensor. The chip carrier further includes a localized heater element 114 located near the second temperature sensor and configured to generate heat in response to a detected difference of the temperatures at the first and second temperature sensors.

チップパッケージ、電子デバイスおよび方法（疲労破損耐久性電子パッケージ）

【課題】温度により誘発される応力を低減するチップパッケージを提供する。【解決手段】チップパッケージ１００は、チップ温度センサ１０８を有するチップ１０２を備える。チップ温度センサは、チップ温度センサ周りの局所的領域におけるチップの温度を測定する。チップパッケージは、複数の相互接続１０６を介してチップに結合されるチップキャリア１０４も含む。チップキャリアは、チップ温度センサと縦方向に整列されたキャリア温度センサ１１２を含む。キャリア温度センサは、キャリア温度センサ周りの局所的領域におけるチップキャリアの温度を測定する。チップキャリアはさらに、キャリア温度センサの近くに配置され、且つ、チップの温度とチップキャリアの温度との比較に基づき検出された差に応答して熱を生成する局所的加熱要素１１４を含む。局所的加熱要素は、検出された差を、チップ温度センサの周りの局所的領域で調整する。【選択図】図１Ａ

Gegenüber einer ermüdungs-fehlfunktion beständigeelektronische packung

Eine Chip-Packung weist einen Chip mit einem ersten Temperatursensor auf. Der erste Temperatursensor ist so konfiguriert, dass er eine erste Temperatur des Chips in einem lokalisierten Gebiet um den ersten Temperatursensor herum misst. Die Chip-Packung weist außerdem einen Chip-Träger auf, der über eine Mehrzahl von Lot-Verbindungen mit dem Chip gekoppelt ist. Der Chip-Träger weist einen zweiten Temperatursensor auf, der in Bezug auf den ersten Temperatursensor vertikal ausgerichtet ist. Der zweite Temperatursensor ist so konfiguriert, dass er eine zweite Temperatur des Chip-Trägers in einem lokalisierten Gebiet um den zweiten Temperatursensor herum misst. Der Chip-Träger weist des Weiteren ein lokalisiertes Heizelement auf, das sich in der Nähe des zweiten Temperatursensors befindet und so konfiguriert ist, dass es in Reaktion auf einen detektierten Unterschied auf Grundlage des Vergleichs der ersten Temperatur und der zweiten Temperatur Wärme erzeugt, so dass der detektierte Unterschied in dem lokalisierten Gebiet um den ersten Temperatursensor herum eingestellt wird.

Double patterned microcooler having alternating fin widths

A microcooler device and formation thereof. The microcooler device includes: a first set of fins having a first fin width; a second set of fins having a second fin width, wherein the first set of fins alternate between the second set of fins; and a set of channels located between the first set of fins and the second set of fins.

Enhanced thermal management of 3-d stacked die packaging

A die stack package is provided and includes a substrate, a stack of computing components, at least one thermal plate, which is thermally communicative with the stack and a lid supported on the substrate to surround the stack and the at least one thermal plate to thereby define a first heat transfer path extending from one of the computing components to the lid via the at least one thermal plate and a fin coupled to a surface of the lid and the at least one thermal plate, and a second heat transfer path extending from the one of the computing components to the lid surface without passing through the at least one thermal plate.

Verbesserte Kühlung von Gehäusen für dreidimensional gestapelte Chips

Gehäuse (200) für Chip-Stapel, aufweisend:ein Substrat (210);einen Stapel von Datenverarbeitungskomponenten gleicher Größe und Form (231);eine Mehrzahl von Kühlplatten (220), die jeweils thermisch mit dem Stapel verbunden sind; undeinen Deckel (250), der auf dem Substrat angebracht ist, um den Stapel und die Mehrzahl von Kühlplatten (220) zu umschließen, um dadurch bereitzustellen:eine Mehrzahl von ersten Wärmeübertragungspfaden, die sich jeweils von einer der Datenverarbeitungskomponenten bis zu dem Deckel über eine entsprechende der Mehrzahl von Kühlplatten (220) und einer Mehrzahl von einzelnen Rippen (2501) erstrecken, die jeweils mit einer Oberfläche (2500) des Deckels und einer entsprechenden der Mehrzahl der Kühlplatten verbunden ist, undeinen zweiten Wärmeübertragungspfad, der sich von einer der Datenverarbeitungskomponenten bis zu der Deckeloberfläche erstreckt, ohne durch eine der Mehrzahl der Rippen (2501) zu verlaufen.

Multichip electronic packages and methods of manufacture

A multi-chip electronic package and methods of manufacture are provided. The multi-chip package includes a plurality of chips mounted on a chip carrier. The multi-chip package further includes a lid mounted on the chip carrier using a bonding material or compression seal, and at least one single piston extending from the lid. Each piston covers an entirety of multiple chips of the plurality of chips.

Enhanced thermal management of 3-D stacked die packaging

Thermal expansion matched chip module with integrated liquid cooling

A chip and cooler assembly includes an active or passive interposer that has a front side and a back side. Integrated circuit chips are mounted onto the back side of the interposer. Each of the chips has a front side that is attached to the interposer and a back side that faces away from the interposer. Gaps separate the chips. The assembly also includes a frame that is fitted into the gaps between the chips. The frame is CTE-matched to the chips. The frame and the chips define a back side surface. A cooler module is attached to the back side surface. The cooler module is CTE-matched to the chips. The cooler module includes a microchannel cooler that is disposed directly against the back sides of the chips and a manifold that is attached to the microchannel cooler opposite the chips. The manifold is CTE-matched to the microchannel cooler.

Thermal expansion matched chip module with integrated liquid cooling

A chip and cooler assembly includes an active or passive interposer (114) that has a front side and a back side. Integrated circuit chips (102, 112) are mounted onto the back side of the interposer (114). Each of the chips (102, 112) has a front side that is attached to the interposer (114) and a back side that faces away from the interposer (114). Gaps (108) separate the chips (102, 112). The assembly also includes a frame (300) that is fitted into the gaps (108) between the chips (102, 112). The frame (300) is CTE-matched to the chips (102, 112). The frame (300) and the chips (102, 112) define a back side surface. A cooler module (200) is attached to the back side surface. The cooler module (200) is CTE-matched to the chips (102, 112). The cooler module (200) includes a microchannel cooler (202) that is disposed directly against the back sides of the chips and a manifold (204, 206) that is attached to the microchannel cooler (202) opposite the chips (102, 112). The manifold (204, 206) is CTE-matched to the microchannel cooler (202).