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27-06-2013 дата публикации

MULTIPROCESSOR SYSTEM AND SYNCHRONOUS ENGINE DEVICE THEREOF

Номер: US20130166879A1
Автор: An Xuejun, Cao Zheng, Chen Fei, Sun Ninghui, Wang Kai
Принадлежит:

The invention discloses a multiprocessor System and synchronous engine device thereof. the synchronous engine includes: a plurality of storage queues, wherein one of the queues stores all synchronization primitives from one of the processors; a plurality of scheduling modules, selecting the synchronization primitives for execution from the plurality of storage queues and then according to the type of the synchronization primitive transmitting the selected synchronization primitives to corresponding processing modules for processing, scheduling modules corresponding in a one-to-one relationship with the storage queues; a plurality of processing modules, receiving the transmitted synchronization primitives to execute different functions; a virtual synchronous memory structure module, using small memory space and mapping main memory spaces of all processors into a synchronization memory structure to realize the function of all synchronization primitives through a control logic; a main memory port, communicating with virtual synchronous memory structure module to read and write the main memory of all processors, and initiate an interrupt request to processors; a configuration register, storing various configuration information required by processing modules. 1. A synchronous engine device of multiprocessor , characterized in that the synchronous engine device includes:a plurality of storage queues, being configured to receive synchronization primitives transmitted by a plurality of processors, wherein one of the queues stores all synchronization primitives from one of the processors;a plurality of scheduling modules, being configured to select the synchronization primitives for execution from the plurality of storage queues and then according to the type of the synchronization primitive transmitting the selected synchronization primitives to corresponding processing modules for processing, the scheduling modules corresponding in a one-to-one relationship with the ...

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Номер записи: 1
25-05-2017 дата публикации

Many-core processor system integrated with network router, and integration method and implementation method thereof

Номер: US20170147528A1
Автор: En SHAO, Ninghui Sun, Peiheng ZHANG, QIANG LI, Xiaobing LIU, Xiaoli Liu, Xuejun An, ZHENG Cao
Принадлежит: Institute of Computing Technology of CAS

The present invention discloses a method for integrating a many-core processor system with a network router. The method comprises a subnet division step used for dividing an on-chip network into network requests in multiple subnet balance chips, and a network interface device deployment step used for deploying at least one network interface device in a subnet in a distributed mode in order to guarantee optimization of the connectivity between the deployed network interface device and the processor cores in the subnets and to implement rapid data exchange of the on-chip network or the inter-chip network. The present invention also discloses a many-core processor system integrated with a network router. The system comprises a network router used for network interfacing and data exchange, and comprising multiple network interface devices embedded into the on-chip network in a distributed mode.

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Номер записи: 2
09-08-2016 дата публикации

Multiprocessor system and synchronous engine device thereof

Номер: US09411778B2
Автор: Fei Chen, Kai Wang, Ninghui Sun, Xuejun An, ZHENG Cao
Принадлежит: Institute of Computing Technology of CAS

The invention discloses a multiprocessor System and synchronous engine device thereof. the synchronous engine includes: a plurality of storage queues, wherein one of the queues stores all synchronization primitives from one of the processors; a plurality of scheduling modules, selecting the synchronization primitives for execution from the plurality of storage queues and then according to the type of the synchronization primitive transmitting the selected synchronization primitives to corresponding processing modules for processing, scheduling modules corresponding in a one-to-one relationship with the storage queues; a plurality of processing modules, receiving the transmitted synchronization primitives to execute different functions; a virtual synchronous memory structure module, using small memory space and mapping main memory spaces of all processors into a synchronization memory structure to realize the function of all synchronization primitives through a control logic; a main memory port, communicating with virtual synchronous memory structure module to read and write the main memory of all processors, and initiate an interrupt request to processors; a configuration register, storing various configuration information required by processing modules.

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Номер записи: 3