Einheit mit einem extrem langen Kanal innerhalb einer VFET-Bauart

Ausführungsformen sind auf Verfahren und resultierende Strukturen für einen vertikalen Feldeffekttransistor (VFET) mit einem extrem langen Kanal ausgerichtet. Ein Paar von Halbleiter-Fins ist auf einem Substrat ausgebildet. Eine Halbleitersäule ist zwischen den Halbleiter-Fins auf dem Substrat ausgebildet. Ein Bereich, der sich unter sämtlichen der Halbleiter-Fins und unter einem Teil der Halbleitersäule erstreckt, ist dotiert. Ein leitfähiges Gate ist über einem Kanalbereich der Halbleiter-Fins und der Halbleitersäule ausgebildet. Eine Oberfläche der Halbleitersäule dient als ein erweiterter Kanalbereich, wenn das Gate aktiv ist.

TRANSISTOR GATE HAVING TAPERED SEGMENTS POSITIONED ABOVE THE FIN CHANNEL

Embodiments of the invention are directed to a method that includes forming a fin over a major surface of a substrate. The fin includes an active fin region having a top fin surface and a fin sidewall. The top fin surface is substantially parallel with respect to the major surface, and the fin sidewall is substantially perpendicular with respect to the major surface. A gate is formed over and around a central portion of the fin, the gate having a bottom gate region and a top gate region. The bottom gate region is substantially below the top fin surface and includes a bottom gate region sidewall that is substantially parallel with respect to the fin sidewall. The top gate region is substantially above the top fin surface and includes a top gate region sidewall that is at an angle with respect to the major surface. 1. A method of forming an integrated circuit (IC) structure , the method comprising:forming a fin over a major surface of a substrate;wherein the fin comprises an active fin region having a top fin surface and a fin sidewall;wherein the top fin surface is substantially parallel with respect to the major surface of the substrate;wherein the fin sidewall is substantially perpendicular with respect to the major surface of the substrate;forming a gate over and around a central portion of the fin, the gate having a bottom gate region and a top gate region;wherein the bottom gate region is substantially below the top fin surface and includes a bottom gate region sidewall that is substantially parallel with respect to the fin sidewall and substantially perpendicular with respect to the major surface of the substrate; andwherein the top gate region is substantially above the top fin surface and includes a top gate region sidewall that is substantially non-parallel with respect to the fin sidewall and substantially non-parallel with respect to the major surface of the substrate.2. The method of claim 1 , wherein forming the gate comprises:forming a gate trench over ...

Supply Chain Disruption Advisor

In an approach to generating advice for supply chain disruptions, one or more computer processors receive a query associated with a supply chain disruption. The one or more computer processors retrieve data corresponding to the supply chain disruption. Based on the retrieve data, the one or more computer processors determine one or more solutions to the supply chain disruption. The one or more computer processors display the one or more determined solutions. The one or more computer processors receive a selection of one of the one or more determined solutions. The one or more computer processors detect one or more patterns associated with the selected solution. 1. A method comprising:receiving, by one or more computer processors, a query associated with a supply chain disruption;retrieving, by the one or more computer processors, data corresponding to the supply chain disruption;based on the retrieved data, determining, by the one or more computer processors, one or more solutions to the supply chain disruption;displaying, by the one or more computer processors, the one or more determined solutions;receiving, by the one or more computer processors, a selection of one of the one or more determined solutions; anddetecting, by the one or more computer processors, one or more patterns associated with the selected solution.2. The method of claim 1 , further comprising claim 1 , receiving claim 1 , by the one or more computer processors claim 1 , training data claim 1 , wherein the training data includes one or more pre-defined rules associated with determining the one or more solutions to the supply chain disruption claim 1 , wherein determining the one or more solutions to the supply chain disruption is based on the retrieved data and on the one or more pre-defined rules.3. The method of claim 2 , wherein the training data is selected from the group consisting of: supply chain transactional data claim 2 , a product bill of materials claim 2 , a current stock claim 2 , ...

Semiconductor device with reduced contact resistance

An interconnect structure and methods of forming the interconnect structure an interconnect dielectric including at least one contact landing within the interconnect dielectric and/or underlying the interconnect dielectric. The structure and methods include roughening an exposed surface of at least one contact landing to increase the surface area of a conductive metal subsequently disposed in a contact feature and in direct contact with the roughened surface of the least one contact landing.

VERTICALLY ALIGNED NANOWIRE CHANNELS WITH SOURCE/DRAIN INTERCONNECTS FOR NANOSHEET TRANSISTORS

A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of semiconductor material layers and metal gate material layers. The nano-sheet semiconductor structure further comprises a source region and a drain region. A first plurality of epitaxially grown interconnects contacts the source region and the semiconductor layers in the alternating stack. A second plurality of epitaxially grown interconnects contacts the drain region and the semiconductor layers in the alternating stack. The method includes removing a portion of alternating semiconductor layers and metal gate material layers. A first plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the source region. A second plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the drain region. 18-. (canceled)9. A semiconductor structure comprising at least:a substrate;at least one alternating stack of semiconductor material layers and metal gate material layers disposed on the substrate;a metal gate disposed on and in contact with the alternating stack of semiconductor material layers and metal gate material layers;a source region;a drain region;a first plurality of epitaxially grown interconnects, wherein each epitaxially grown interconnect in the first plurality of epitaxially grown interconnects contacts the source region and one semiconductor layer in the alternating stack, wherein the first plurality of epitaxially grown interconnects forms an air pocket between each metal gate material layer in the alternating stack and the source region; anda second plurality of epitaxially grown interconnects, wherein each epitaxially grown interconnect in the second plurality of epitaxially grown interconnects contacts the drain region and one semiconductor layer in the alternating stack, wherein the second plurality of ...

VERTICALLY ALIGNED NANOWIRE CHANNELS WITH SOURCE/DRAIN INTERCONNECTS FOR NANOSHEET TRANSISTORS

A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of semiconductor material layers and metal gate material layers. The nano-sheet semiconductor structure further comprises a source region and a drain region. A first plurality of epitaxially grown interconnects contacts the source region and the semiconductor layers in the alternating stack. A second plurality of epitaxially grown interconnects contacts the drain region and the semiconductor layers in the alternating stack. The method includes removing a portion of alternating semiconductor layers and metal gate material layers. A first plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the source region. A second plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the drain region. 1. A semiconductor structure comprising at least:a substrate;at least one alternating stack of semiconductor material layers and metal gate material layers disposed on the substrate;a metal gate disposed on and in contact with the alternating stack of semiconductor material layers and metal gate material layers;a source region;a drain region;a first plurality of epitaxially grown interconnects, wherein each epitaxially grown interconnect in the first plurality of epitaxially grown interconnects contacts the source region and one semiconductor layer in the alternating stack; anda second plurality of epitaxially grown interconnects, wherein each epitaxially grown interconnect in the second plurality of epitaxially grown interconnects contacts the drain region and one semiconductor layer in the alternating stack.2. The semiconductor structure of claim 1 , wherein a thickness of each semiconductor layer in the alternating stack is between 3 nm and 60 nm.3. The semiconductor structure of claim 1 , wherein the first plurality of ...

Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors

A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of semiconductor material layers and metal gate material layers. The nano-sheet semiconductor structure further comprises a source region and a drain region. A first plurality of epitaxially grown interconnects contacts the source region and the semiconductor layers in the alternating stack. A second plurality of epitaxially grown interconnects contacts the drain region and the semiconductor layers in the alternating stack. The method includes removing a portion of alternating semiconductor layers and metal gate material layers. A first plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the source region. A second plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the drain region.

FABRICATION OF FIN FIELD EFFECT TRANSISTORS FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICES INCLUDING SEPARATE N-TYPE AND P-TYPE SOURCE/DRAINS USING A SINGLE SPACER DEPOSITION

A method of forming a complementary metal oxide semiconductor (CMOS) device on a substrate, including forming a plurality of vertical fins on the substrate, forming a first set of source/drain projections on the first subset of vertical fins, forming a second set of source/drain projections on the second subset of vertical fins, where the second set of source/drain projections is a different oxidizable material from the oxidizable material of the first set of source/drain projections, converting a portion of each of the second set of source/drain projections and a portion of each of the first set of source/drain projections to an oxide, removing the converted oxide portion of the first set of source/drain projections to form a source/drain seed mandrel, and removing a portion of the converted oxide portion of the second set of source/drain projections to form a dummy post. 1. A method of forming a complementary metal oxide semiconductor (CMOS) device on a substrate , comprising:forming a plurality of vertical fins on the substrate, where a first subset of vertical fins includes one or more vertical fins and a second subset of vertical fins includes one or more vertical fins;forming a first set of source/drain projections on the first subset of vertical fins;forming a second set of source/drain projections on the second subset of vertical fins, where the second set of source/drain projections is a different oxidizable material from the oxidizable material of the first set of source/drain projections;converting a portion of each of the second set of source/drain projections and a portion of each of the first set of source/drain projections to an oxide;removing the converted oxide portion of the first set of source/drain projections to form a source/drain seed mandrel; andremoving a portion of the converted oxide portion of the second set of source/drain projections to form a dummy post.2. The method of claim 1 , wherein the first set of source/drain projections is ...

FABRICATION OF FIN FIELD EFFECT TRANSISTORS FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICES INCLUDING SEPARATE N-TYPE AND P-TYPE SOURCE/DRAINS USING A SINGLE SPACER DEPOSITION

A method of forming a complementary metal oxide semiconductor (CMOS) device on a substrate, including forming a plurality of vertical fins on the substrate, forming a first set of source/drain projections on the first subset of vertical fins, forming a second set of source/drain projections on the second subset of vertical fins, where the second set of source/drain projections is a different oxidizable material from the oxidizable material of the first set of source/drain projections, converting a portion of each of the second set of source/drain projections and a portion of each of the first set of source/drain projections to an oxide, removing the converted oxide portion of the first set of source/drain projections to form a source/drain seed mandrel, and removing a portion of the converted oxide portion of the second set of source/drain projections to form a dummy post. 1. A complementary metal oxide semiconductor (CMOS) device , comprising:an arrangement of a plurality of vertical fins on a substrate, wherein the plurality of vertical fins are made of a semiconductor material;a first set of source/drain bases on a first subset of vertical fins, wherein the first set of source/drain bases is an oxidizable material;a second set of source/drain base on a second subset of vertical fins, wherein the second set of source/drain bases is a different oxidizable material than the oxidizable material of the first set of source/drain bases; andsource/drains on each of the first set of source/drain bases and source/drains on each of the second set of source/drain bases.2. The complementary metal oxide semiconductor (CMOS) device of claim 1 , wherein the substrate is silicon-germanium claim 1 , and the germanium concentration of the silicon-germanium substrate is in the range of about 10 at. % germanium to about 30% at. % germanium.3. The complementary metal oxide semiconductor (CMOS) device of claim 1 , wherein the first set of source/drain bases is single crystal silicon ...

SEMICONDUCTOR DEVICE WITH REDUCED CONTACT RESISTANCE

An interconnect structure and methods of forming the interconnect structure an interconnect dielectric including at least one contact landing within the interconnect dielectric and/or underlying the interconnect dielectric. The structure and methods include roughening an exposed surface of at least one contact landing to increase the surface area of a conductive metal subsequently disposed in a contact feature and in direct contact with the roughened surface of the least one contact landing. 1. A method of fabricating an interconnect structure , the method comprising:forming one or more openings in an interconnect dielectric, wherein the one or more openings expose at least one contact landing;performing an oxidative gas cluster ion beam process to the at least one contact landing, wherein oxidative gas cluster ion beam process forms an irregular oxide layer on an exposed surface of the at least one contact landing;performing a cleaning process to selectively remove the irregular oxide layer from the exposed surface of the at least one contact landing to form an irregular surface on the at least one contact landing, wherein the irregular surface has a surface roughness of 1 nanometer to 10 nanometers;filling the one or more openings with a conductive metal, wherein the conductive metal directly contacts the irregular surface on the at least one contact landing.2. The method of claim 1 , wherein the gas cluster ion beam process utilizes a reactive gas comprising oxygen and/or an oxygen containing gas.3. The method of claim 1 , wherein the reactive gas further includes an inert gas.4. The method of claim 1 , wherein the cleaning process comprises exposing the substrate to a wet etchant for a period of time effective to remove the oxide layer.5. The method of claim 1 , wherein the wherein the interconnect dielectric comprises SiO claim 1 , silsesquixoanes claim 1 , carbon doped oxides that include atoms of Si claim 1 , C claim 1 , O and H claim 1 , thermosetting ...

NANOSHEET CHANNEL-TO-SOURCE AND DRAIN ISOLATION

A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate. 1. A structure used to fabricate a nanosheet semiconductor device , the structure comprising:a substrate;two or more sets of silicon layers formed above the substrate, wherein each of the two or more sets of silicon layers is parallel to others of the two or more sets of silicon layers in a first direction and each of the two or more sets of silicon layers includes gaps between the silicon layers of the respective set of silicon layers; anda dielectric material configured to anchor each of the two or more sets of silicon layers at a first end and a second end along a second direction, which is perpendicular to the first direction.2. The structure according to claim 1 , wherein the dielectric material is silicon nitride.3. The structure according to claim 1 , wherein the dielectric material is between the silicon layers of each of the two or more sets of silicon layers and between adjacent ones of the two or more sets of silicon layers.4. The structure according to claim 1 , further comprising an oxide in the gaps between the silicon layers of each of the two or more sets of silicon layers.5. ...

ELECTRICALLY CONDUCTIVE INTERCONNECT INCLUDING VIA HAVING INCREASED CONTACT SURFACE AREA

An interconnect structure includes a first dielectric layer and a second dielectric layer each extending along a first axis to define a height and a second axis opposite the first axis to define a length. A capping layer is interposed between the first dielectric layer and the second dielectric layer. At least one electrically conductive feature is embedded in at least one of the first dielectric layer and the second dielectric layer. At least one electrically conductive via extends through the second dielectric layer and the capping layer. The via has an end that contacts the conductive feature. The end includes a flange having at least one portion extending laterally along the first axis to define a contact area between the via and the at least one conductive feature. 1. An interconnect structure , comprising:a first dielectric layer and a second dielectric layer each extending along a first axis to define a height and a second axis opposite the first axis to define a length;a capping layer interposed between the first dielectric layer and the second dielectric layer;at least one electrically conductive feature formed in at least one of the first dielectric layer and the second dielectric layer; andat least one electrically conductive via extending through the second dielectric layer and the capping layer, and having an end that contacts the at least one electrically conductive feature, the end including a contact flange having at least one portion extending laterally along the second axis to define a contact area between the via and the at least one conductive feature.2. The interconnect structure of claim 1 , wherein the contact flange extends laterally away from the via and beyond the second dielectric layer.3. The interconnect structure of claim 2 , wherein the contact flange is interposed between the first dielectric layer and the second dielectric layer.4. The interconnect structure of claim 3 , wherein the contact flange is formed in only the contact area ...

SYSTEM AND METHOD FOR MEASURING GEOMETRIC CHANGE IN A SUBTERRANEAN STRUCTURE

A system for measuring geometric change in a subterranean structure. The system includes an apparatus communicably couplable to a computing system. The apparatus is couplable to a mobile platform and includes a sensor configured to acquire data representative of a geometry of the subterranean structure and/or a camera configured to capture images of an interior of the subterranean structure, and a processing circuit. The computing system includes at least one processor, a 3D generator module configured to generate a digital three-dimensional model of the subterranean structure, an anchor module configured to define a plurality of digital anchors associated with the subterranean structure; a movement determination module configured to determine a movement of at least one of the digital anchors, and a movement classification module configured to determine a type of movement within the subterranean structure based on the determined movement of the at least one of the digital anchors. 1. A system for measuring geometric change in a subterranean structure , the system comprising: [ a sensor configured to acquire data representative of a geometry of the subterranean structure; and', 'a camera configured to capture images of an interior of the subterranean structure; and, 'at least one of the following, the sensor; and', 'the camera; and, 'a processing circuit communicably couplable to at least one of the following], 'an apparatus couplable to a mobile platform, wherein the apparatus comprises at least one processor;', 'a 3D generator module communicably couplable to the at least one processor, wherein the 3D generator module is configured to generate a digital three-dimensional model of the subterranean structure;', 'an anchor module communicably couplable to the at least one processor, wherein the anchor module is configured to define a plurality of digital anchors associated with the subterranean structure;', 'a movement determination module communicably couplable to ...

EPITAXIALLY GROWN QUANTUM WELL FINFETS FOR ENHANCED PFET PERFORMANCE

A method of forming a quantum well having a conformal epitaxial well on a {100} crystallographic orientated fin. The method may include: forming fins in a {100} crystallographic oriented substrate; forming a conformal well on the fins using epitaxial growth; and forming a conformal barrier on the conformal well using epitaxial growth. 1. A method comprising:forming a pad layer on a {100} crystallographic oriented substrate;forming a mandrel on the pad layer, wherein the pad layer is an oxide layer on a nitride layer;forming spacers on sidewalls of the mandrel, wherein the spacers are silicon nitride;forming a spacer pattern by removing the mandrel from in-between the spacers;transferring the spacer pattern into the oxide layer using the nitride layer as an etch stop;transferring the spacer pattern into the nitride layer and simultaneously removing the spacers from above the oxide layer;forming fins in the substrate by transferring the spacer pattern in the nitride layer into the substrate;forming a recessed oxide fill on the substrate and in-between the fins, a top surface of the recessed oxide fill is below a top surface of the fins;forming a conformal well on the fins using epitaxial growth; andforming a conformal barrier on the conformal well using epitaxial growth, wherein the conformal well is in-between the fins and the conformal barrier, the conformal well has a lower band-gap than the conformal barrier and the fins.2. The method of claim 1 , wherein a dual processing chamber is used to grow both the conformal well and the conformal barrier.3. (canceled)4. The method of claim 1 , wherein the fins each have a thickness of 8 nm.5. (canceled)6. The method of claim 1 , wherein the mandrel is amorphous silicon.7. The method of claim 3 , wherein the oxide layer is undoped silicon glass.8. The method of claim 3 , wherein the nitride layer is silicon nitride.9. The method of claim 1 , further comprising:forming an isolation region surrounding a set of fins, the ...

EPITAXIALLY GROWN QUANTUM WELL FINFETS FOR ENHANCED PFET PERFORMANCE

A finFET with a quantum well having a conformal epitaxial well on a {100} crystallographic orientated fin. The structure may include a fin having a {100} crystallographic orientation; a conformal well covering the fin; and a conformal barrier covering the conformal well. 1. A structure comprising:a fin having a {100} crystallographic orientation;a conformal well covering the fin; anda conformal barrier covering the conformal well.2. The structure of claim 1 , wherein the fin has a thickness of 8 nm.3. The structure of claim 1 , wherein the conformal well has a thickness of 1.5 nm and the conformal barrier has a thickness of 2 nm.4. The structure of claim 1 , wherein the conformal well and the conformal barrier are above a recessed oxide fill claim 1 , the recessed oxide fill electrically isolates a bottom portion of the fin from adjoining components claim 1 , the bottom portion of the fin is below the conformal well and the conformal barrier claim 1 , a top surface of the recessed oxide fill is below a top surface of the fin.5. The structure of claim 1 , wherein the band-gap of the conformal well is less than the band-gap of the fin and less than the band-gap of the conformal barrier. The present invention generally relates to fin field effect transistors (finFET's) in a {100} crystallographic oriented silicon substrate, and more particularly to a finFET with a quantum well having a conformal epitaxial well on a fin in the {100} crystallographic orientation to increase pFET (hole) mobility while having a negligible impact on nFET (electron) mobility.In each new generation of semiconductor technology, transistor current decreases due to gate width reduction, mobility degradation of minority carriers and reduction of supply voltage. Reduced transistor current results in deterioration of circuit stability and reduces the speed of circuit operation thereby causing degradation in performance. One of the key parameters determining the mobility of minority carriers is the ...

MARGIN FOR FIN CUT USING SELF-ALIGNED TRIPLE PATTERNING

A method for fabricating a semiconductor structure. The method includes forming a plurality of mandrel structures. A plurality of first spacers is formed on sidewalls of the mandrel structures. A plurality of second spacers is formed on sidewalls of the first spacers. The plurality of first spacers is removed selective to the plurality of second spacers and mandrel structures. A cut mask is formed over a first set of second spacers in the plurality of second spacers and a first set of mandrel structures in the plurality of mandrel structures. A second set of second spacers in the plurality of spacers and a second set of mandrel structures in the plurality of mandrel structures remain exposed. One of the second set of mandrel structures and the second set of second spacers is removed selective to the second set of second spacers and the second set of mandrel structures, respectively. 1. A method of forming a semiconductor structure comprising:forming a plurality of mandrel structures;forming a plurality of first spacers on sidewalls of the plurality of mandrel structures;forming a plurality of second spacers on sidewalls of the plurality of first spacers;removing the plurality of first spacers selective to the plurality of second spacers and the plurality of mandrel structures;forming a cut mask over a first set of second spacers in the plurality of second spacers and a first set of mandrel structures in the plurality of mandrel structures, wherein a second set of second spacers in the plurality of second spacers and a second set of mandrel structures in the plurality of mandrel structures remain exposed; andremoving the second set of mandrel structures selective to the second set of second spacers.2. The method of claim 1 , wherein removing the plurality of first spacers disposes each mandrel structure in the plurality of mandrel structures between a pair of second spacers in the plurality of second spacers.3. The method of claim 1 , wherein each second spacer in ...

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE

A semiconductor device including a fin structure including a recess, a first gate formed in the recess of the fin structure, and a second gate formed outside the fin structure.

VERTICAL TUNNELING FIELD EFFECT TRANSISTOR WITH DUAL LINER BOTTOM SPACER

Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having a dual liner bottom spacer. In a non-limiting embodiment of the invention, a first liner is formed on a top surface of a source or drain (S/D) region and sidewalls of a semiconductor fin. Portions of a spacer are removed to expose a first region and a second region of the first liner. The first region of the first liner is directly on the S/D region and the second region is over the semiconductor fin. A second liner is formed on the first liner. A first portion of the second liner is formed by selectively depositing dielectric material on the exposed first region and exposed second region of the first liner. The first liner and the second liner collectively define the dual liner bottom spacer. 1. A method for forming a semiconductor device , the method comprising:forming a first liner on a top surface of a source or drain (S/D) region and sidewalls of a semiconductor fin;removing portions of a spacer to expose a first region and a second region of the first liner, wherein the first region is directly on the S/D region and the second region is over the semiconductor fin; andforming a second liner on the first liner, a first portion of the second liner formed by selectively depositing dielectric material on the exposed first region and exposed second region of the first liner.2. The method of claim 1 , wherein forming the first liner comprises conformally depositing dielectric material over the top surface of the S/D region and sidewalls of the semiconductor fin.3. The method of claim 1 , wherein a second portion of the second liner is formed by depositing additional dielectric material on the first portion of the second liner after removing the spacer.4. The method of claim 3 , wherein the additional dielectric material is conformally deposited such that the second liner comprises a first thickness over the S/ ...

ELECTRICALLY CONDUCTIVE INTERCONNECT INCLUDING VIA HAVING INCREASED CONTACT SURFACE AREA

An interconnect structure includes a first dielectric layer and a second dielectric layer each extending along a first axis to define a height and a second axis opposite the first axis to define a length. A capping layer is interposed between the first dielectric layer and the second dielectric layer. At least one electrically conductive feature is embedded in at least one of the first dielectric layer and the second dielectric layer. At least one electrically conductive via extends through the second dielectric layer and the capping layer. The via has an end that contacts the conductive feature. The end includes a flange having at least one portion extending laterally along the first axis to define a contact area between the via and the at least one conductive feature. 1. An interconnect structure , comprising:a first dielectric layer and a second dielectric layer each extending along a first axis to define a height and a second axis opposite the first axis to define a length;a capping layer interposed between the first dielectric layer and the second dielectric layer;at least one electrically conductive feature formed in at least one of the first dielectric layer and the second dielectric layer; andat least one electrically conductive via extending through the second dielectric layer and the capping layer, and having an end that contacts the at least one electrically conductive feature, the end including a flange having at least one portion extending laterally along the second axis to define a contact area between the via and the at least one conductive feature.2. The interconnect structure of claim 1 , wherein the flange extends laterally away from the via and beyond the second dielectric layer.3. The interconnect structure of claim 2 , wherein a portion of the contact area is aligned beneath the second dielectric layer.4. The interconnect structure of claim 2 , wherein the contact flange is interposed between the first dielectric layer and the second dielectric ...

Method and structure for enabling high aspect ratio sacrificial gates

Sacrificial gate structures having an aspect ratio of greater than 5:1 are formed on a substrate. In some embodiments, each sacrificial gate structure straddles a portion of a semiconductor fin that is present on the substrate. An anchoring element is formed orthogonal to each sacrificial gate structure rendering the sacrificial gate structures mechanically stable. After formation of a planarization dielectric layer, each anchoring element can be removed and thereafter each sacrificial gate structure can be replaced with a functional gate structure.

GAS TURBINE HAVING FUEL GAS MONITORING SYSTEM

A gas turbine and a method for operating a gas turbine having a fuel gas monitoring system are presented. The fuel gas monitoring system may provide a measurement of a parameter of a fuel gas in real time. An operation of a gas turbine may be optimized to adapt variation in hydrocarbon content of a fuel gas from the measurement. The fuel gas monitoring system may provide an optical, flow through, online monitoring of fuel gas composition. 1. A gas turbine comprising:a compressor that is configured to compress air;a combustor located downstream of the compressor that is configured to receive the compressed air;a fuel gas supply line connected to the combustor that is configured to supply fuel gas to the combustor, wherein the fuel gas and the compressed air are mixed and combusted in the combustor to generate working gas;a turbine located downstream of the combustor that is configured to expend the working gas to generate power output;a fuel gas monitoring system that is configured to provide a measurement of a parameter of the fuel gas in real time, wherein the fuel gas monitoring system comprises an inlet and an outlet, wherein a fuel gas sample flows into the fuel gas monitoring system through the inlet, wherein the fuel gas sample is discharged from the fuel gas monitoring system through the outlet; anda control system that is configured to adjust an operating parameter of the gas turbine based on the measurement of the parameter of the fuel gas.2. The gas turbine as claimed in claim 1 , wherein the fuel gas monitoring system comprises an optical system.3. The gas turbine as claimed in claim 1 , wherein the fuel gas monitoring system is configured to provide an online measurement of the parameter of the fuel gas.4. The gas turbine as claimed in claim 1 , wherein the fuel gas sample is discharged from the fuel gas monitoring system into the fuel gas supply line.5. The gas turbine as claimed in claim 1 , further comprising an upstream pressure regulating device ...

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE

A semiconductor device includes a fin structure including a cylindrical shape, an inner gate formed inside the fin structure, and an outer gate formed outside the fin structure and connected to the inner gate. 1. A semiconductor device comprising:a fin structure comprising a cylindrical shape and including a recess formed in an upper surface of the fin structure;an inner gate formed inside the fin structure;an outer gate formed outside the fin structure; anda conductor formed in the recess and connecting the inner and outer gates.2. The semiconductor device of claim 1 , wherein the cylindrical shape of the fin structure comprises a circular cylindrical shape claim 1 , and the conductor comprises a conductive bar extending radially across the fin structure from an inner surface of the fin structure to an outer surface of the fin structure.3. The semiconductor device of claim 2 , wherein the conductive bar comprises a first end connected to an outer surface of the inner gate and a second end connected to an inner surface of the outer gate.4. The semiconductor device of claim 2 , wherein the conductive bar comprises a substantially rectangular cross-sectional shape.5. The semiconductor device of claim 2 , wherein a diameter of the inner surface of the fin structure is in a range from 10 nm to 30 nm claim 2 , and a diameter of the outer surface of the fin structure is in a range from 30 nm to 50 nm.6. The semiconductor device of claim 2 , further comprising:an inner gate insulating layer formed between the inner gate and the inner surface of the fin structure.7. The semiconductor device of claim 2 , further comprising:an outer gate insulating layer formed between the outer gate and the outer surface of the fin structure.8. The semiconductor device of claim 2 , wherein a width of the fin structure between the inner surface and the outer surface is in a range from 5 nm to 15 nm.9. The semiconductor device of claim 1 , wherein the recess comprises a first recess portion ...

AIR GAP SPACER FOR METAL GATES

A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure. 1. A method for forming a transistor device comprising:forming a trench adjacent to at least one gate structure to expose a surface of one of a source region and a drain region;forming a sacrificial spacer on sidewalls of the trench, wherein the sacrificial spacer has a base width greater than an upper surface width;forming a contact in the trench on at least one of the source region and the drain region;removing the sacrificial spacer; andforming a dielectric material layer on sidewalls of the metal contact and a gate structure exposed by removing the sacrificial spacer, wherein portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structures.2. The method of claim 1 , wherein said forming the trench comprises:forming an interlayer dielectric layer′forming said trench in said interlayer dielectric layer exposing sidewall spacers on adjacent gate structures of said at least one gate structure;recessing said sidewall spacers to provide remnant spacer portions; andrecessing a vertical portion of a gate dielectric of said adjacent gate structures.3. The method of ...

ENABLING LARGE FEATURE ALIGNMENT MARKS WITH SIDEWALL IMAGE TRANSFER PATTERNING

In an embodiment, this disclosure relates to a method of creating an alignment feature within a sidewall image transfer process by the addition of a block mask. The presence of the alignment feature would enable better overlay and alignment for subsequent lithographic stacks. 1. An integrated circuit component comprising:a gate electrode layer; anda hard mask layer on the gate electrode layer;wherein the hard mask layer is patterned with an alignment feature and a sidewall feature comprising a critical dimension;wherein a width of the alignment feature is greater than the critical dimension; andwherein the critical dimension is less than or equal to about 100 nanometers.2. The integrated circuit component of claim 1 , wherein the sidewall feature has a width of 5 to 100 nanometers.3. The integrated circuit component of claim 1 , wherein the sidewall feature has a width of 10 to 100 nanometers.4. The integrated circuit component of claim 1 , wherein the sidewall feature has a width of 10 to 40 nanometers.5. The integrated circuit component of claim 1 , wherein the alignment feature has a width of greater than or equal to 1 micrometer.6. The integrated circuit component of claim 1 , wherein the alignment feature has a width of greater than or equal to 25 nanometers.7. The integrated circuit component of claim 1 , wherein the alignment feature has a width of 25 to 100 nanometers.8. The integrated circuit component of claim 1 , wherein the hard layer mask comprisesa memory layer located on top of the gate electrode layer,an oxide layer located on top of the memory layer, anda hard mask planarization layer located on top of the oxide layer.9. The integrated circuit component of claim 8 , wherein the memory layer comprises a dielectric material comprising an oxide claim 8 , an oxide precursor claim 8 , or a nitride.10. The integrated circuit component of claim 8 , wherein the memory layer comprises a silicon nitride.11. The integrated circuit component of claim 8 , ...

SYSTEM AND METHOD FOR MEASURING GEOMETRIC CHANGE IN A SUBTERRANEAN STRUCTURE

A system. The system includes an apparatus and a computing system. The apparatus is couplable to a mobile platform and includes a sensing device and/or a camera. The computing system includes an anchor module configured to define a plurality of virtual anchors associated with a subterranean structure; a movement determination module configured to determine a movement of at least one of the virtual anchors, and a movement classification module configured to determine a type of subterranean structure movement based on the determined movement of the at least one of the virtual anchors. The type of subterranean structure movement comprises convergence, subsidence, movement along a fault line, cross-sectional movement, longitudinal movement and/or hidden movement. 1. A system , comprising: a sensing device; and', 'a camera, wherein the apparatus is couplable to a mobile platform; and, 'an apparatus comprising at least one of the following an anchor module configured to define a plurality of virtual anchors associated with a subterranean structure;', 'a movement determination module configured to determine a movement of at least one of the virtual anchors; and', convergence;', 'subsidence;', 'movement along a fault line;', 'cross-sectional movement;', 'longitudinal movement; and', 'hidden movement., 'a movement classification module configured to determine a type of subterranean structure movement based on the determined movement of the at least one of the virtual anchors, wherein the type of subterranean structure movement comprises at least one of the following], 'a computing system communicably couplable to the apparatus, wherein the computing system comprises2. The system of claim 1 , wherein the subterranean structure comprises one of the following:a mine;a tunnel;a cave;a bunker; anda conduit.3. The system of claim 1 , wherein the sensing device comprises one of the following:a laser rangefinder;a radar module;an ultrasonic ranging module; anda sonar module.4. The ...

FIN PATTERNS WITH VARYING SPACING WITHOUT FIN CUT

Methods of forming semiconductor fins include forming first spacers on a first sidewall of each of a plurality of mandrels using a directional deposition process. A finless region is masked by forming a mask on a second sidewall of one or more of the plurality of mandrels. Second spacers are formed on a second sidewall of unmasked mandrels using a directional deposition process. The finless region is unmasked and each of the plurality of mandrels is etched away. Fins are formed from a substrate using the first and second spacers as a mask, such that no fins are formed in the finless region. 1. A method of forming semiconductor fins , comprising:forming first spacers on a first sidewall of each of a plurality of mandrels using a directional deposition process;masking a finless region by forming a mask on a second sidewall of one or more of the plurality of mandrels;forming second spacers on a second sidewall of unmasked mandrels using a directional deposition process;unmasking the finless region;etching away each of the plurality of mandrels; andforming fins from a substrate using the first and second spacers as a mask, such that no fins are formed in the finless region.2. The method of claim 1 , wherein no fin is removed after formation of the fins.3. The method of claim 1 , wherein masking the finless region further comprises forming the mask to directly contact a first spacer on an adjacent mandrel.4. The method of claim 1 , wherein the substrate comprises a nitride pad layer that is directly on a semiconductor layer.5. The method of claim 4 , wherein the nitride pad layer includes silicon nitride.6. The method of claim 1 , wherein the oxygen gas cluster ion beam includes an angled deposition process.7. The method of claim 1 , wherein unmasking the finless region includes unmasking the second sidewall of the one or more of the plurality of mandrels.8. The method of claim 1 , further comprising patterning a mandrel material using a hard mask to form the plurality ...

FIN PATTERNS WITH VARYING SPACING WITHOUT FIN CUT

Methods of forming semiconductor fins include forming first spacers on a first sidewall of each of multiple mandrels using an angled deposition process. A second sidewall of one or more of the mandrels is masked in a finless region. Second spacers are formed on a second sidewall of all unmasked mandrels. Semiconductor fins are formed from a substrate using the first and second spacers as a pattern mask. 1. A method of forming semiconductor fins , comprising:forming first spacers on a first sidewall of each of a plurality of mandrels using an angled deposition process;masking a second sidewall of one or more of the plurality of mandrels in a finless region;forming second spacers on a second sidewall of all unmasked mandrels;forming said semiconductor fins from a substrate using the first and second spacers as a pattern mask.2. The method of claim 1 , wherein forming the first spacers on the first sidewalls comprises oxidizing the first sidewalls using a gas cluster ion beam.3. The method of claim 2 , wherein the mandrels comprise amorphous silicon and the gas cluster ion beam comprises oxygen.4. The method of claim 2 , wherein the gas cluster ion beam has an angle relative to the substrate under the mandrels between about 10° and about 80°.5. The method of claim 1 , wherein forming the second spacers on the second sidewalls comprising oxidizing the second sidewalls using a gas cluster ion beam.6. The method of claim 1 , wherein forming the second spacers on the second sidewalls comprises an isotropic process.7. The method of claim 1 , further comprising anisotropically etching spacer material from horizontal surfaces of the mandrels after unmasking the second sidewall of the one or more of the plurality of mandrels.8. The method of claim 1 , wherein forming the semiconductor fins comprises forming no semiconductor fins in a region that was masked.9. The method of claim 1 , wherein no semiconductor fin is removed after formation of the semiconductor fins.10. The ...

FORMING STACKED NANOWIRE SEMICONDUCTOR DEVICE

A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire. 1. A method for forming a nanowire semiconductor device , the method comprising:forming a nanowire stack comprising a first nanowire and a second nanowire arranged on the first nanowire;forming a sacrificial gate over the nanowire stack;forming a sacrificial spacer adjacent to the sacrificial gate;removing an exposed portion of the first nanowire while leaving at least a portion of the first nanowire intact to form a first cavity partially defined by the sacrificial spacer, the first nanowire, and the second nanowire;removing the sacrificial spacer;depositing a layer of spacer material adjacent to the sacrificial gate and in the first cavity;removing a portion of the layer of spacer material to form a spacer adjacent to the sacrificial gate and the first nanowire;removing exposed portions of the second nanowire;removing a portion of the second nanowire to form a second cavity, the second cavity partially defined by the spacer and the second nanowire; andepitaxially growing a source/drain region in the second cavity from exposed portions of the second nanowire.2. The method of claim 1 , further comprising:forming an inter-level dielectric layer over portions of the source/drain region;removing the sacrificial gate to partially expose a channel region of the second nanowire.3. The method of claim 2 , further comprising removing the first nanowire.4. The method of claim 3 , further comprising forming a gate stack over and around the second nanowire.5. The method of claim 1 , wherein the forming the sacrificial spacer comprises:depositing a layer of spacer material along sidewalls of the sacrificial gate; andetching to form the ...

METHOD AND STRUCTURE FOR ENABLING CONTROLLED SPACER RIE

A method and structure to enable reliable dielectric spacer endpoint detection by utilizing a sacrificial spacer fin are provided. The sacrificial spacer fin that is employed has a same pitch as the pitch of each semiconductor fin and the same height as the dielectric spacers on the sidewalls of each semiconductor fin. Exposed portions of the sacrificial spacer fin are removed simultaneously during a dielectric spacer reactive ion etch (RIE). The presence of the sacrificial spacer fin improves the endpoint detection of the spacer RIE and increases the endpoint signal intensity. 1. A semiconductor structure comprising:a plurality of semiconductor fins extending upwards from a surface of a substrate;a plurality of sacrificial spacer fin portions extending upwards from another surface of said substrate;a gate structure straddling over each semiconductor fin and each sacrificial spacer fin portion; anda gate spacer surrounding said gate structure, wherein each sacrificial spacer fin portion is located entirely beneath a portion of said gate structure and a portion of said gate spacer.2. The semiconductor structure of claim 1 , wherein said gate structure is a sacrificial gate structure.3. The semiconductor structure of claim 1 , wherein said gate structure is a functional gate structure.4. The semiconductor structure of claim 1 , wherein said substrate is an insulator layer.5. The semiconductor structure of claim 1 , wherein said gate spacer and each sacrificial spacer fin portion comprise a same dielectric material.6. The semiconductor structure of claim 5 , wherein said same dielectric material is silicon nitride.7. The semiconductor structure of claim 1 , wherein said semiconductor fins are present in a FinFET device region claim 1 , while each sacrificial spacer fin portion is present in a Kerf region.8. The semiconductor structure of claim 2 , wherein a portion of a protective dielectric liner is positioned between a bottommost surface of said sacrificial gate ...

VERTICALLY ALIGNED NANOWIRE CHANNELS WITH SOURCE/DRAIN INTERCONNECTS FOR NANOSHEET TRANSISTORS

A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of semiconductor material layers and metal gate material layers. The nano-sheet semiconductor structure further comprises a source region and a drain region. A first plurality of epitaxially grown interconnects contacts the source region and the semiconductor layers in the alternating stack. A second plurality of epitaxially grown interconnects contacts the drain region and the semiconductor layers in the alternating stack. The method includes removing a portion of alternating semiconductor layers and metal gate material layers. A first plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the source region. A second plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the drain region. 1. A method for forming a semiconductor structure , the method comprising:forming a structure comprising at least an alternating stack of semiconductor layers and metal gate material layers formed on a substrate, a metal gate formed on and in contact with a top layer of the alternating stack, a source region and a drain region in contact with the alternating stack, and dielectric layers formed on and in contact with a top surface of the source and drain regions, respectively;removing a portion of the semiconductor layers and metal gate material layers, wherein the removing forms trenches exposing at least sidewalls of the source and drain regions;forming a first plurality of interconnects between and in contact with the semiconductor layers and the source region; andforming a second plurality of interconnects between and in contact with the semiconductor layers and the drain region.2. The method of claim 1 , further comprising:prior to removing the portion of the semiconductor layers and metal gate material layers, etching ...

Forming stacked nanowire semiconductor device

A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire.

METHOD AND STRUCTURE FOR ENABLING HIGH ASPECT RATIO SACRIFICIAL GATES

Sacrificial gate structures having an aspect ratio of greater than 5:1 are formed on a substrate. In some embodiments, each sacrificial gate structure straddles a portion of a semiconductor fin that is present on the substrate. An anchoring element is formed orthogonal to each sacrificial gate structure rendering the sacrificial gate structures mechanically stable. After formation of a planarization dielectric layer, each anchoring element can be removed and thereafter each sacrificial gate structure can be replaced with a functional gate structure. 1. A method of forming a semiconductor structure comprising:forming a sacrificial gate stack over a surface of a substrate;providing a plurality of hard mask structures on a topmost surface of said sacrificial gate stack;forming an anchoring element disposed over segments of each hard mask structure; andpatterning said sacrificial gate stack into a plurality of sacrificial gate structures utilizing said plurality of hard mask structures and said anchoring element as an etch mask.2. The method of claim 1 , further comprising forming a dielectric spacer comprising a first dielectric material on sidewalls of said anchoring element claim 1 , each of said hard mask structures and each of said sacrificial gate structures.3. The method claim 2 , further comprising forming a planarization dielectric layer laterally surrounding each of said sacrificial gate structures claim 2 , wherein said planarization dielectric layer has a topmost surface that is coplanar with a topmost surface of each of said sacrificial gate structures.4. The method of claim 3 , further comprising removing each hard mask structure prior to said forming said planarization dielectric layer to expose a sacrificial gate cap portion of each sacrificial gate structure claim 3 , wherein end segments of each sacrificial gate cap portion are connected to a sacrificial gate cap anchoring portion.5. The method of claim 1 , wherein said forming said anchoring element ...

MARGIN FOR FIN CUT USING SELF-ALIGNED TRIPLE PATTERNING

A method for fabricating a semiconductor structure. The method includes forming a plurality of mandrel structures. A plurality of first spacers is formed on sidewalls of the mandrel structures. A plurality of second spacers is formed on sidewalls of the first spacers. The plurality of first spacers is removed selective to the plurality of second spacers and mandrel structures. A cut mask is formed over a first set of second spacers of the plurality of second spacers and a first set of mandrel structures of the plurality of mandrel structures. A second set of second spacers of the plurality of spacers and a second set of mandrel structures of the plurality of mandrel structures remain exposed. One of the second set of mandrel structures and the second set of second spacers is removed selective to the second set of second spacers and the second set of mandrel structures, respectively. 1. A method of forming a semiconductor structure comprising:forming a plurality of mandrel structures;forming a plurality of first spacers on sidewalls of the plurality of mandrel structures;forming a plurality of second spacers on sidewalls of the plurality of first spacers; andremoving the plurality of first spacers selective to the plurality of second spacers and the plurality of mandrel structures.2. The method of claim 1 , wherein removing the plurality of first spacers disposes each mandrel of the plurality of mandrel structures between a pair of second spacers of the plurality of second spacers.3. The method of claim 1 , wherein each second spacer of the plurality of second spacers comprises a material different from a material of each mandrel structure of the plurality of mandrel structures.4. The method of claim 1 , wherein forming the plurality of mandrel structures comprises:forming a planarization layer on and in contact with a mandrel layer;forming an anti-reflective coating on and in contact with the planarization layer;forming a photoresist layer on and in contact with the ...

SINGLE SPACER FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR PROCESS FLOW

A method of forming a semiconductor device that includes forming a high-k dielectric fin liner on the first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region, and forming a gate structure including a low-k dielectric gate sidewall spacer on the channel region of the first and second plurality of fin structures. A first epitaxial semiconductor material on the first plurality of fin structures from which the high-k dielectric fin liner has been removed. The first epitaxial semiconductor material is then oxidized, and a remaining portion of the high-k dielectric fin liner is removed. A second epitaxial semiconductor material is formed on the second plurality of fin structures. 1. A method of forming a fin structure comprising:forming a high-k dielectric fin liner on at least one of a first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region;forming a low-k dielectric spacer on a channel region of said at least one of the first and second plurality of fin structures;forming a first epitaxial semiconductor material on one for said first and second plurality of fin structures from which the high-k dielectric fin liner is removed, wherein a remaining portion of the high-k dielectric fin liner remains on a second of said first and second plurality of fin structures;oxidizing the first epitaxial semiconductor material;removing a remaining portion of the high-k dielectric fin liner; andforming a second epitaxial semiconductor material on said second of said first and second plurality of fin structures.2. The method of claim 1 , wherein said forming the high-k dielectric fin liner on at least one of the first plurality of fin structures in the first device region and a second plurality of fin structures in the second device region comprises:forming a material layer of high-k dielectric on the first and second plurality of fin structures; ...

SINGLE SPACER FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR PROCESS FLOW

A method of forming a semiconductor device that includes forming a high-k dielectric fin liner on the first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region, and forming a gate structure including a low-k dielectric gate sidewall spacer on the channel region of the first and second plurality of fin structures. A first epitaxial semiconductor material on the first plurality of fin structures from which the high-k dielectric fin liner has been removed. The first epitaxial semiconductor material is then oxidized, and a remaining portion of the high-k dielectric fin liner is removed. A second epitaxial semiconductor material is formed on the second plurality of fin structures. 1. A semiconductor device comprising:p-type FinFETs in a first device region and n-type FinFETs in a second device region of a substrate;a gate structure present on a channel portion for each of the fin structures for each of the p-type and n-type FinFETs;gate sidewall spacers of a low-k dielectric material present on the gate structures for each of the n-type FinFETs and the p-type FinFETs, wherein the gate sidewall spacers for each of the n-type and p-type FinFETs have substantially a same width; andsource and drain epitaxial semiconductor material on the fin structures for each of the p-type FinFETs and the n-type FinFETs, wherein an oxide surface liner is present on exterior surfaces of the source and drain epitaxial semiconductor material of the p-type FinFETs that is not present on exterior surfaces of the source and drain epitaxial semiconductor material of the n-type FinFETs.2. The semiconductor device of claim 1 , wherein the gate sidewall spacers for the n-type finFETs comprise a high-k dielectric fin liner material present at an interface of the gate sidewall spacers claim 1 , and the fin structures.3. The semiconductor device of claim 1 , wherein the low-k dielectric material of the gate sidewall spacers is SiOCN.4. ...

AIR GAP SPACER FOR METAL GATES

A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure. 1. A method for forming an air gap in a semiconductor structure comprising:forming a sacrificial spacer that abuts a first structure;forming a second structure that abuts the sacrificial spacer;removing the sacrificial spacer; andforming a first conformal dielectric layer on opposing sidewalls of the second structure and the first structure, wherein the first conformal dielectric layer is present around a perimeter of an air gap and portions of the single conformal dielectric material layer contact one another to enclose the air gap.2. The method of claim 1 , wherein the first structure is a first electrically conductive structure.3. The method of claim 2 , wherein the first electrically conductive structure is a gate structure.4. The method of claim 1 , wherein the sacrificial spacer is formed in a trench.5. The method of claim 4 , wherein forming the trench comprises:forming an interlayer dielectric layer around the first structure;etching the interlayer dielectric layer to expose a sidewall spacer that abuts the first structure; andrecessing the sidewall spacer to define a depth of the trench.6. The method of claim 5 , wherein forming the sacrificial spacer ...

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE

A semiconductor device includes a fin structure having a circular cylindrical shape, and including a first recess formed on a first side of the fin structure and a second recess formed on a second side of the fin structure opposite the first side, an inner gate formed inside the fin structure, and an inner gate insulating layer formed between the inner gate and an inner surface of the fin structure. 1. A semiconductor device comprising: a first recess formed on a first side of the fin structure; and', 'a second recess formed on a second side of the fin structure opposite the first side;, 'a fin structure comprising a circular cylindrical shape, and includingan inner gate formed inside the fin structure, and an inner gate insulating layer formed between the inner gate and an inner surface of the fin structure;an outer gate formed outside the fin structure, and an outer gate insulating layer formed between the outer gate and an outer surface of the fin structure; andfirst and second conductive bars formed in the first and second recesses, respectively, each of the first and second conductive bars connecting the inner and outer gates, a height of the first and second conductive bars being substantially equal to the depth of the recess, such that an upper surface of the first and second conductive bars is substantially co-planar with an upper surface of the fin structure, and each of the first and second conductive bars comprising a first end connected to an outer surface of the inner gate and a second end connected to an inner surface of the outer gate.2. A semiconductor device comprising:a fin structure;an inner gate formed inside the fin structure;an outer gate formed outside the fin structure and connected to the inner gate; anda conductor connecting the inner and outer gates.3. The semiconductor device of claim 2 , wherein the conductor is formed in an upper surface of the fin structure.4. The semiconductor device of claim 3 , wherein the fin structure includes a ...

Semiconductor device and method of forming the semiconductor device

A semiconductor device includes a fin structure including a cylindrical shape, an inner gate formed inside the fin structure, and an outer gate formed outside the fin structure and connected to the inner gate.

NANOSHEET CHANNEL-TO-SOURCE AND DRAIN ISOLATION

A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate. 1. (canceled)2. A method of fabricating a semiconductor device , the method comprising:providing first and second nanosheet fins, wherein each of the first nanosheet fin and the second nanosheet fin comprises at least two first layers and at least two second layers disposed on a substrate, wherein the at least two first layers are arranged alternatingly with the at least two second layers, wherein the first and second nanosheet fins are adjacent and in-line, and wherein the first and second nanosheet fins are separated by a trench filled with a trench-dielectric;depositing a dummy gate-dielectric layer over the first and second nanosheet fins and the trench-dielectric;forming a dummy gate stack and sidewall spacers over a portion of the first nanosheet fin;etching the first nanosheet fin using the dummy gate stack and sidewall spacers as an etch-mask to expose sidewalls of the at least two first layers and the at least two second layers,recessing the sidewalls of the at least two second layers with respect to sidewalls of the at least two first layers to form divots;filling the divots to form ...

AIR GAP SPACER FOR METAL GATES

A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure. 1. A method for forming a transistor device comprising:forming a sacrificial spacer having a base width greater than an upper surface width that is abutting a gate structure;forming a contact abutting the sacrificial spacer on at least one of a source region and a drain region;removing the sacrificial spacer; andforming a dielectric material layer on sidewalls of the contact and the gate structure, wherein portions of the conformally dielectric material layer contact one another to form an air gap.2. The method of claim 1 , wherein the sacrificial spacer is formed in a trench claim 1 , and forming the trench comprises:forming an interlayer dielectric layer;forming said trench in said interlayer dielectric layer exposing sidewall spacers on adjacent gate structures of said at least one gate structure;recessing said sidewall spacers to provide remnant spacer portions; andrecessing a vertical portion of a gate dielectric of said adjacent gate structures.3. The method of claim 2 , wherein recessing said vertical portion of said gate dielectric of said adjacent gate structures recesses are formed between a remaining portion of the gate structure and at least one of ...

UNDER-CHANNEL GATE TRANSISTORS

Transistors and methods of forming the same include forming a semiconductor fin from a first material on dielectric layer. Material is etched away from the dielectric layer directly underneath a channel region of the semiconductor fin, with the semiconductor fin still being supported by the dielectric layer in a source and drain region. A gate stack is formed around the channel region of the semiconductor fin, with a portion of the gate stack underneath the semiconductor fin being larger than a portion of the gate stack above the semiconductor fin. 1. A method for forming a transistor , comprising:anisotropically etching a stacked semiconductor layer and dielectric layer to form a semiconductor fin from a first material on a dielectric fin;etching away material from the dielectric layer directly underneath a channel region of the semiconductor fin, with the semiconductor fin still being supported by the dielectric layer in a source and drain region and with a continuous remnant of the dielectric layer remaining underneath the semiconductor fin;forming a gate stack around the channel region of the semiconductor fin, with a portion of the gate stack underneath the semiconductor fin having a vertical thickness greater than a vertical thickness of a portion of the gate stack above the semiconductor fin.2. The method of claim 1 , further comprising forming a dummy gate fin over the semiconductor fin claim 1 , the dummy gate fin having a long dimension that is perpendicular to a long dimension of the semiconductor fin.3. The method of claim 2 , further comprising forming dielectric sidewalls on the dummy gate fin.4. The method of claim 3 , further comprising etching away the dummy gate fin after forming the dielectric sidewalls to expose the channel region of the semiconductor fin.5. The method of claim 4 , wherein etching away material from the dielectric layer is performed after etching away the dummy gate.6. The method of claim 3 , further comprising forming source and ...

DUMMY GATE FORMATION USING SPACER PULL DOWN HARDMASK

Forming a dummy gate on a semiconductor device is disclosed. A first sacrificial layer is formed on a fin, and a second sacrificial layer is formed on the first sacrificial layer. A first hardmask layer is formed on the second sacrificial layer, and a second hardmask layer is formed on the first hardmask layer and patterned. The first hardmask layer is laterally recessed in a lateral direction under the second hardmask layer. The first and second sacrificial layers are etched to a corresponding width of the first hardmask layer. A spacer layer is formed on the fin, the first sacrificial layer, second sacrificial layer, the first hardmask layer and the second hardmask layer. The spacer layer is etched until it remains on a sidewall of the first sacrificial layer, the second sacrificial layer and the first hardmask layer, wherein the first and second sacrificial layers form the dummy gate. 1. A dummy gate of a semiconductor device , the semiconductor device comprising:a first sacrificial layer on a fin, a second sacrificial layer on the first sacrificial layer, a first hardmask layer on the second sacrificial layer, and a second hardmask layer on the first hardmask layer, wherein the first hardmask layer has been laterally recessed under the second hardmask layer, wherein the first sacrificial layer and the second sacrificial layer correspond to the first hardmask layer having been laterally recessed; anda spacer layer formed on the first sacrificial layer, the second sacrificial layer, and the first hardmask layer, wherein the spacer layer is below the second hardmask layer such that a top of the spacer layer is at a boundary of the first hardmask layer and the second hardmask layer, wherein the first sacrificial layer and the second sacrificial layer form the dummy gate.2. The semiconductor device of claim 1 , wherein a width of the first hardmask layer and the dummy gate is about equal.3. The semiconductor device of claim 1 , wherein a combined width of the spacer ...

TECHNIQUES FOR MIGRATION PATHS

Exemplary embodiments described herein relate to a destination path for use with multiple different types of VMs, and techniques for using the destination path to convert, copy, or move data objects stored in one type of VM to another type of VM. The destination path represents a standardized (canonical) way to refer to VM objects from a proprietary VM. A destination location may be specified using the canonical destination path, and the location may be converted into a hypervisor-specific destination location. A source data object may be copied or moved to the destination location using a hypervisor-agnostic path. 1. A system comprising:a computer readable storage medium to store instructions to migrate data from a source virtual machine (VM) managed by a first type of hypervisor to a destination VM managed by a second type of hypervisor different from the first type; and a command interface module to receive an identification of the destination virtual machine and a destination path, the destination path provided to the command interface module in a format that is independent of a path format of the first type of hypervisor and independent of a path format of the second type of hypervisor; and', "a conversion module to migrate the data from the source VM to a location managed by the destination VM's hypervisor, the location corresponding to the received destination path."], 'a processor configured to execute the instructions to provide2. The system of claim 1 , wherein the conversion module is configured to migrate the data by issuing a hypervisor-agnostic conversion command.3. The system of claim 1 , wherein the conversion module is configured to migrate the data via a hypervisor-agnostic data object.4. The system of claim 1 , wherein the data is stored in a hypervisor-agnostic format and exposed to a client according to a hypervisor-specific format.5. The system of claim 1 , wherein the processor is further configured to provide a storage mapping module claim 1 ...

FIN PATTERNS WITH VARYING SPACING WITHOUT FIN CUT

Methods of forming semiconductor fins include forming first spacers on a first sidewall of each of a plurality of mandrels using an angled deposition process. A second sidewall of one or more of the plurality of mandrels is masked. Second spacers are formed on a second sidewall of all unmasked mandrels. The second sidewall of the one or more of the plurality of mandrels is unmasked. The mandrels are etched away. Fins are formed from a substrate using the first and second spacers as a mask. 1. A method of forming semiconductor fins , comprising:forming first spacers on a first sidewall of each of a plurality of mandrels using an angled deposition process;masking a second sidewall of one or more of the plurality of mandrels;forming second spacers on a second sidewall of all unmasked mandrels;unmasking the second sidewall of the one or more of the plurality of mandrels;etching away the mandrels; andforming fins from a substrate using the first and second spacers as a mask.2. The method of claim 1 , wherein forming the first spacers on the first sidewalls comprises oxidizing the first sidewalls using a gas cluster ion beam.3. The method of claim 2 , wherein the mandrels comprise amorphous silicon and the gas cluster ion beam comprises oxygen.4. The method of claim 2 , wherein the gas cluster ion beam has an angle relative to a substrate under the mandrels between about 10° and about 80°.5. The method of claim 1 , wherein forming the second spacers on the second sidewalls comprising oxidizing the second sidewalls using a gas cluster ion beam.6. The method of claim 1 , wherein forming the second spacers on the second sidewalls comprises an isotropic process.7. The method of claim 1 , further comprising anisotropically etching spacer material from horizontal surfaces of the mandrels after unmasking the second sidewall of the one or more of the plurality of mandrels.8. The method of claim 1 , wherein forming the fins comprises forming no fins in a region that was masked.9. ...

FIN PATTERNS WITH VARYING SPACING WITHOUT FIN CUT

Methods of forming semiconductor fins include forming first spacers on a first sidewall of each of a plurality of mandrels using an angled deposition process. A second sidewall of one or more of the plurality of mandrels is masked. Second spacers are formed on a second sidewall of all unmasked mandrels. The second sidewall of the one or more of the plurality of mandrels is unmasked. The mandrels are etched away. Fins are formed from a substrate using the first and second spacers as a mask. 1. A method of forming semiconductor fins , comprising:forming first spacers on a first sidewall of each of a plurality of amorphous silicon mandrels using an oxygen gas cluster ion beam;masking a finless region by forming a mask directly on a second sidewall of one or more of the plurality of mandrels;forming second spacers on a second sidewall of all unmasked mandrels using an oxygen gas cluster ion beam;unmasking the finless region;anisotropically etching spacer material from horizontal surfaces of the mandrels after unmasking the finless region;etching away the mandrels; andforming fins from a substrate using the first and second spacers as a mask, such that no fins are formed in the finless region.2. The method of claim 1 , wherein forming the second spacers on the second sidewalls comprises an isotropic process.3. The method of claim 1 , wherein no fin is removed after formation of the fins.4. The method of claim 1 , wherein masking the finless region further comprises forming the mask to directly contact a first spacer on an adjacent mandrel.5. The method of claim 1 , wherein the substrate comprises a nitride pad layer that is directly on a semiconductor layer.6. The method of claim 5 , wherein the nitride pad layer includes silicon nitride.7. The method of claim 1 , wherein the oxygen gas cluster ion beam has an angle relative to a substrate under the mandrels between about 10° and about 80°.8. The method of claim 1 , wherein the oxygen gas cluster ion beam includes an ...

FIN PATTERNS WITH VARYING SPACING WITHOUT FIN CUT

Methods of forming semiconductor fins include forming first spacers on a first sidewall of each of a plurality of mandrels using an angled deposition process. A second sidewall of one or more of the plurality of mandrels is masked. Second spacers are formed on a second sidewall of all unmasked mandrels. The second sidewall of the one or more of the plurality of mandrels is unmasked. The mandrels are etched away. Fins are formed from a substrate using the first and second spacers as a mask. 1. A method of forming semiconductor fins , comprising:forming first spacers on a first sidewall of each of a plurality of amorphous silicon mandrels using an oxygen gas cluster ion beam that is angled between about 10° and about 80°;masking a finless region by forming a mask directly on a second sidewall of one or more of the plurality of mandrels;isotropically forming second spacers on a second sidewall of all unmasked mandrels using an oxygen gas cluster ion beam;unmasking the finless region;anisotropically etching spacer material from horizontal surfaces of the mandrels after unmasking the finless region;etching away the mandrels; andforming fins from a substrate, comprising a nitride pad layer directly on a semiconductor layer, using the first and second spacers as a mask, such that no fins are formed in the finless region.2. The method of claim 1 , wherein masking the finless region further comprises forming the mask to directly contact a first spacer on an adjacent mandrel.3. The method of claim 1 , wherein no fin is removed after formation of the fins.4. The method of claim 1 , wherein the nitride pad layer includes silicon nitride.5. The method of claim 1 , wherein the oxygen gas cluster ion beam includes an angled deposition process.6. The method of claim 1 , wherein unmasking the finless region includes unmasking the second sidewall of the one or more of the plurality of mandrels.7. The method of claim 1 , further comprising patterning a mandrel material using a hard ...

FORMING STACKED NANOWIRE SEMICONDUCTOR DEVICE

A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire. 1. A method for forming a nanowire semiconductor device , the method comprising:forming a nanowire stack comprising a first nanowire and a second nanowire arranged on the first nanowire;forming a sacrificial gate over the nanowire stack;forming a sacrificial spacer adjacent to the sacrificial gate;removing one or more portions of the first nanowire to form a first cavity;removing the sacrificial spacer;depositing a layer of spacer material adjacent to the sacrificial gate and in the first cavity;removing a portion of the layer of spacer material to form a spacer adjacent to the sacrificial gate and the first nanowire;removing one or more portions of the second nanowire to form a second cavity; andepitaxially growing a source/drain region in the second cavity from the one or more portions of the second nanowire.2. The method of claim 1 , further comprising:forming an inter-level dielectric layer over portions of the source/drain region;removing the sacrificial gate to partially expose a channel region of the second nanowire.3. The method of claim 2 , further comprising removing the first nanowire.4. The method of claim 3 , further comprising forming a gate stack over and around the first nanowire.5. The method of claim 1 , wherein the first cavity is partially defined by the sacrificial spacer claim 1 , the first nanowire claim 1 , and the second nanowire claim 1 , wherein the second cavity is partially defined by the spacer and the second nanowire.6. The method of claim 1 , wherein the forming the sacrificial spacer comprises:depositing a layer of spacer material along sidewalls of the sacrificial gate; andetching to form the ...

SUPER LONG CHANNEL DEVICE WITHIN VFET ARCHITECTURE

Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active. 114.-. (canceled)15. A semiconductor device , comprising:a pair of semiconductor fins formed on a substrate;a semiconductor pillar formed between the semiconductor fins on the substrate;a bottom doped region that extends under all of the semiconductor fins and under part of the semiconductor pillar; anda conductive gate formed over a channel region of the semiconductor fins and the semiconductor pillar.16. The semiconductor device of further comprising a thick oxide layer formed between the conductive gate and the semiconductor fins.17. The semiconductor device of claim 15 , wherein the semiconductor pillar is recessed below a surface of the semiconductor fins.18. The semiconductor device of further comprising a bottom spacer between the conductive gate and the bottom doped region.19. The semiconductor device of further comprising a top spacer on the conductive gate.2022.-. (canceled)23. A semiconductor device claim 15 , comprising:a first semiconductor fin formed on a substrate;a second semiconductor fin formed on the substrate and adjacent to the first semiconductor fin;a semiconductor pillar formed between the first and second semiconductor fins;a bottom doped region that extends under all of the semiconductor fins and under part of the semiconductor pillar; anda shared conductive gate formed over a channel region of the first and second semiconductor fins and the semiconductor pillar ...

SUPER LONG CHANNEL DEVICE WITHIN VFET ARCHITECTURE

Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active. 1. A method for forming a semiconductor device , the method comprising:forming a pair of semiconductor fins on a substrate;forming a semiconductor pillar between the semiconductor fins on the substrate;forming a bottom doped region that extends under all of the semiconductor fins and under part of the semiconductor pillar; andforming a conductive gate over a channel region of the semiconductor fins and the semiconductor pillar.2. The method of further comprising doping the semiconductor pillar.3. The method of further comprising forming a thick oxide layer between the conductive gate and the semiconductor fins and the semiconductor pillar.4. The method of further comprising recessing the semiconductor pillar below a surface of the semiconductor fins.5. The method of further comprising forming a bottom spacer between the conductive gate and the bottom doped region.6. The method of further comprising forming a top spacer on the conductive gate.7. The method of further comprising forming top doped regions on exposed surfaces of the semiconductor fins.8. The method of further comprising forming a conductive contact on the top doped regions.9. The method of further comprising forming a gate contact on the conductive gate and over the semiconductor pillar.10. The method of claim 1 , wherein a thickness of the semiconductor pillar is larger than a thickness of the semiconductor fins.11. A ...

AIR GAP SPACER FOR METAL GATES

A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure. 1. A transistor device comprising:contacts formed on source and drain regions and spaced from gate structures, wherein the contacts have a first width proximate to the source and drain regions that tapers to a larger second width in a direction away from the source and drain regions; anda dielectric layer present on at least sidewalls of the contacts and sidewall of the gate structures, the dielectric layer having a pinched off region that seals air gaps between the contacts and the gate structures.2. The device of further comprising an interlayer dielectric material positioned around at least a portion of the gate structures.3. The device of claim 1 , wherein the device is fin-type field effect transistor (FinFET) further comprising fin structures having a channel region that the gate structures are present on claim 1 , wherein the source region is present on a source region portion of the fin structure and the drain region is present on a drain region portion of the fin structure.4. The device of claim 1 , further comprising spacer remnants located adjacent to at least one of the source region and the drain region.5. The device of claim 1 , further comprising a ...

SUPER LONG CHANNEL DEVICE WITHIN VFET ARCHITECTURE

Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active. 1. A method of operating a semiconductor device , the method comprising: a first semiconductor fin adjacent to a second semiconductor fin on a substrate;', 'a semiconductor pillar formed between the first and second semiconductor fins on the substrate;', 'a conductive gate formed over a channel region of the first and second semiconductor fins and the semiconductor pillar;', 'a source region formed on a surface of the first semiconductor fin; and', 'a drain region formed on a surface of the second semiconductor fin; and, 'providing a semiconductor device comprisingpassing a current from the source region to the drain region through the semiconductor pillar, the current passing across a top portion of the semiconductor pillar from a first sidewall of the semiconductor pillar to a second sidewall of the semiconductor pillar.2. The method of claim 1 , wherein the semiconductor pillar is recessed below a surface of the first and second semiconductor fins.3. The method of claim 1 , wherein the semiconductor device further comprises a common gate contact formed on the conductive gate and over the semiconductor pillar.4. The method of claim 1 , wherein a thickness of the semiconductor pillar is larger than a thickness of the first and second semiconductor fins.5. The method of further comprising doping the semiconductor pillar.6. The method of further comprising forming a thick oxide layer ...

METHOD AND STRUCTURE FOR ENABLING CONTROLLED SPACER RIE

A method and structure to enable reliable dielectric spacer endpoint detection by utilizing a sacrificial spacer fin are provided. The sacrificial spacer fin that is employed has a same pitch as the pitch of each semiconductor fin and the same height as the dielectric spacers on the sidewalls of each semiconductor fin. Exposed portions of the sacrificial spacer fin are removed simultaneously during a dielectric spacer reactive ion etch (RIE). The presence of the sacrificial spacer fin improves the endpoint detection of the spacer RIE and increases the endpoint signal intensity. 1. A method of forming a semiconductor structure , said method comprising:providing a plurality of semiconductor fins extending upwards from a surface of a substrate, and a plurality of sacrificial spacer fins extending upwards from another surface of said substrate;forming a sacrificial gate structure straddling over a portion of each semiconductor fin and each sacrificial spacer fin;forming a dielectric spacer material surrounding said sacrificial gate structure, wherein said dielectric spacer material and each sacrificial spacer fin comprise a same dielectric material; andperforming a spacer reactive ion etch to said dielectric spacer material to provide a dielectric spacer on sidewall surfaces of said sacrificial gate structure, wherein during said spacer reactive ion etch exposed portions of each sacrificial spacer fin are removed, while maintaining a portion of each sacrificial spacer fin beneath said dielectric spacer and said sacrificial gate structure.2. The method of claim 1 , wherein each of said plurality of semiconductor fins has a height and width that is the same as each sacrificial spacer fin.3. The method of claim 1 , wherein said providing said plurality of semiconductor fins comprises:forming a first set of semiconductor fins on said surface of said substrate and a set second of semiconductor fins on said another surface of said substrate; andreplacing each semiconductor ...

FABRICATION OF FIN FIELD EFFECT TRANSISTORS FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICES INCLUDING SEPARATE N-TYPE AND P-TYPE SOURCE/DRAINS USING A SINGLE SPACER DEPOSITION

A method of forming a complementary metal oxide semiconductor (CMOS) device on a substrate, including forming a plurality of vertical fins on the substrate, forming a first set of source/drain projections on the first subset of vertical fins, forming a second set of source/drain projections on the second subset of vertical fins, where the second set of source/drain projections is a different oxidizable material from the oxidizable material of the first set of source/drain projections, converting a portion of each of the second set of source/drain projections and a portion of each of the first set of source/drain projections to an oxide, removing the converted oxide portion of the first set of source/drain projections to form a source/drain seed mandrel, and removing a portion of the converted oxide portion of the second set of source/drain projections to form a dummy post. 1. A method of forming a complementary metal oxide semiconductor (CMOS) device on a substrate , comprising:forming a first set of source/drain projections of a first oxidizable material on a first subset of vertical fins including one or more vertical fins;forming a second set of source/drain projections of a second oxidizable material on a second subset of vertical fins including one or more vertical fins, wherein the second oxidizable material is different from the first oxidizable material;converting a portion of each of the second set of source/drain projections and a portion of each of the first set of source/drain projections to an oxide;removing the converted oxide portion of the first set of source/drain projections to form a source/drain seed mandrel; andremoving a portion of the converted oxide portion of the second set of source/drain projections to form a dummy post.2. The method of claim 1 , wherein the first set of source/drain projections is silicon claim 1 , and the second set of source/drain projections is silicon-germanium.3. The method of claim 2 , wherein the substrate is ...

METHOD AND STRUCTURE FOR ENABLING HIGH ASPECT RATIO SACRIFICIAL GATES

Sacrificial gate structures having an aspect ratio of greater than 5:1 are formed on a substrate. In some embodiments, each sacrificial gate structure straddles a portion of a semiconductor fin that is present on the substrate. An anchoring element is formed orthogonal to each sacrificial gate structure rendering the sacrificial gate structures mechanically stable. After formation of a planarization dielectric layer, each anchoring element can be removed and thereafter each sacrificial gate structure can be replaced with a functional gate structure. 1. A method of forming a semiconductor structure comprising:forming a sacrificial gate stack over a surface of a substrate;providing a plurality of hard mask structures on a topmost surface of said sacrificial gate stack, wherein an anchoring element is disposed over segments of each hard mask structure; andpatterning said sacrificial gate stack into a plurality of sacrificial gate structures utilizing said plurality of hard mask structures and said anchoring element as an etch mask.2. The method of claim 1 , further comprising forming a dielectric spacer comprising a first dielectric material on sidewalls of said anchoring element claim 1 , each of said hard mask structures and each of said sacrificial gate structures.3. The method claim 2 , further comprising forming a planarization dielectric layer laterally surrounding each of said sacrificial gate structures claim 2 , wherein said planarization dielectric layer has a topmost surface that is coplanar with a topmost surface of each of said sacrificial gate structures.4. The method of claim 3 , further comprising removing each hard mask structure prior to said forming said planarization dielectric layer to expose a sacrificial gate cap portion of each sacrificial gate structure claim 3 , wherein end segments of each sacrificial gate cap portion are connected to a sacrificial gate cap anchoring portion.5. The method of claim 4 , further comprising removing each ...

METHOD AND STRUCTURE FOR ENABLING HIGH ASPECT RATIO SACRIFICIAL GATES

Sacrificial gate structures having an aspect ratio of greater than 5:1 are formed on a substrate. In some embodiments, each sacrificial gate structure straddles a portion of a semiconductor fin that is present on the substrate. An anchoring element is formed orthogonal to each sacrificial gate structure rendering the sacrificial gate structures mechanically stable. After formation of a planarization dielectric layer, each anchoring element can be removed and thereafter each sacrificial gate structure can be replaced with a functional gate structure. 1. A semiconductor structure comprising:a plurality of functional gate structures located on a surface of a substrate;a dielectric spacer comprising a first dielectric material located on sidewalls of each functional gate structure of said plurality of functional gate structures; anda second dielectric material located on end portions of each functional gate structure, wherein said second dielectric material comprises a different dielectric material than said first dielectric material of said dielectric spacer and wherein said second dielectric material is located orthogonal to said dielectric spacer and each functional gate structure.2. The semiconductor structure of claim 1 , wherein said substrate comprises an insulator layer and wherein at least one semiconductor fin is present on said insulator claim 1 , and wherein each functional gate straddles a portion of said at least one semiconductor fin and said dielectric spacer straddles another portion of said at least one semiconductor fin.3. The semiconductor structure of claim 1 , wherein said dielectric spacer comprises a low k dielectric material.4. The semiconductor structure of claim 2 , further comprising epitaxial semiconductor material portions located on still other portions of said at least one semiconductor fin and on each side of the functional gate structure claim 2 , wherein said epitaxial semiconductor material portions are doped with an n-type dopant.5. ...

METHOD TO FORM DUAL CHANNEL SEMICONDUCTOR MATERIAL FINS

A silicon fin precursor is formed in an nFET device region and a fin stack comprising alternating material portions, and from bottom to top, of silicon and a silicon germanium alloy is formed in a pFET device region. A thermal anneal is then used to convert the fin stack into a silicon germanium alloy fin precursor. A thermal oxidation process follows that converts the silicon fin precursor into a silicon fin and the silicon germanium alloy fin precursor into a silicon germanium alloy fin. Functional gate structures can be formed straddling over each of the various fins. 1. A semiconductor structure comprising:a silicon fin located directly on a first portion of a substrate; anda silicon germanium alloy fin located directly on a silicon pedestal structure that is present directly on a second portion of said substrate, wherein said silicon fin and said silicon germanium alloy fin have a same width and topmost surfaces that are coplanar with each other.2. The semiconductor structure of claim 1 , further comprising a local isolation structure located on exposed surfaces of said substrate and at a footprint of said silicon fin and said silicon germanium alloy fin claim 1 , wherein upper sidewall surfaces and a topmost surface of said silicon fin and said silicon germanium alloy fin are exposed.3. The semiconductor structure of claim 2 , further comprising a first functional gate structure straddling over said silicon fin claim 2 , and a second functional gate structure straddling over said silicon germanium alloy fin.4. The semiconductor structure of claim 3 , wherein each of said first functional gate structure and said second functional gate structure comprises a gate dielectric portion and a gate conductor portion claim 3 , said gate conductor portion is located over said gate dielectric portion.5. The semiconductor structure of claim 1 , wherein said substrate comprises silicon.6. The semiconductor structure of claim 1 , wherein said silicon fin is present in an ...

CYCLIC ETCH PROCESS TO REMOVE DUMMY GATE OXIDE LAYER FOR FIN FIELD EFFECT TRANSISTOR FABRICATION

Methods are provided to implement a cyclic etch process to remove oxide layers for semiconductor device fabrication. For example, a method comprises performing a cyclic etch process to incrementally etch an oxide layer, wherein the cyclic etch process comprises sequentially performing at least two instances of an etch cycle. The etch cycle comprises performing an etch process to partially etch a portion of the oxide layer using an etch chemistry and environment which is configured to etch down the oxide layer at an etch rate of about 25 angstroms/minute or less, and performing a thermal treatment to remove by-products of the etch process. The cyclic etch process can be implemented as part of a replacement metal gate process to remove a dummy gate oxide layer of a dummy gate structure as part of, e.g., a FinFET semiconductor fabrication process flow. 1. A method for fabricating a semiconductor device , comprising: performing an etch process to partially etch a portion of the oxide layer using an etch chemistry and environment which is configured to etch down the oxide layer at an etch rate of about 25 angstroms/minute or less, wherein the etch chemistry and environment comprises a reaction gas and a carrier gas, wherein the reaction gas is flowed into a chamber for the etch process at a flow rate of about 30 sccm (standard cubic centimeter per minute) to about 50 sccm, and wherein the carrier gas is flowed into the chamber at a flow rate of about 100 sccm to about 1000 sccm and wherein the chamber is maintained at a pressure of about 30 mTorr to about 50 mTorr; and', 'performing a thermal treatment to remove by-products of the etch process., 'performing a cyclic etch process to incrementally etch an oxide layer, wherein the cyclic etch process comprises sequentially performing, at least two instances of an etch cycle, wherein the etch cycle comprises2. The method of claim 1 , wherein a ratio of the carrier gas to reaction gas is about 20:1 or greater.3. (canceled)4. ...

METHOD AND STRUCTURE TO ENABLE DUAL CHANNEL FIN CRITICAL DIMENSION CONTROL

A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a substrate having a {100} crystallographic surface orientation, forming a second semiconductor layer on the substrate, patterning the first semiconductor layer and the second semiconductor layer into a first plurality of fins and a second plurality of fins, respectively, wherein the first and second plurality of fins extend vertically with respect to the substrate, covering the first plurality of fins and a portion of the substrate corresponding to the first plurality of fins, and epitaxially growing semiconductor layers on exposed portions of the second plurality of fins and on exposed portions of the substrate, wherein the epitaxially grown semiconductor layers on the exposed portions of the second plurality of fins increase a critical dimension of each of the second plurality of fins. 1. A semiconductor device , comprising:a substrate having a {100} crystallographic surface orientation;a first plurality of fins comprising a first semiconductor material; and the first and second plurality of fins extend vertically with respect to the substrate;', 'the second plurality of fins each comprise a conformal semiconductor layer on lateral sides thereof; and', 'the first plurality of fins has the same or substantially the same lateral critical dimension as the second plurality of fins combined with the conformal semiconductor layer on the lateral sides thereof., 'a second plurality of fins comprising a second semiconductor material different from the first semiconductor material, wherein2. The semiconductor layer according to claim 1 , wherein the conformal semiconductor layer extends onto the substrate adjacent each of the second plurality of fins.3. The semiconductor layer according to claim 1 , wherein a thickness of the conformal semiconductor layer on the lateral sides of a given fin of the second plurality of fins is the same or substantially the same as a difference ...

VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR WITH PRECISE GATE LENGTH DEFINITION

Techniques relate to a gate stack for a semiconductor device. A vertical fin is formed on a substrate. The vertical fin has an upper portion and a bottom portion. The upper portion of the vertical fin has a recessed portion on sides of the upper portion. A gate stack is formed in the recessed portion of the upper portion of the vertical fin. 110.-. (canceled)11. A method of forming a gate stack for a semiconductor device , the method comprising:forming a vertical fin on a substrate, the vertical fin having an upper portion and a bottom portion, wherein the upper portion of the vertical fin has a recessed portion on sides of the upper portion; andforming the gate stack in the recessed portion of the upper portion of the vertical fin, such that the gate stack is on the sides of the upper portion but not above the upper portion of the vertical fin.12. The method of claim 11 , further comprising forming a bottom spacer on top of the substrate and on the bottom portion of the vertical fin.13. The method of claim 11 , wherein a first hard mask layer is formed on top of the vertical fin claim 11 , such that the gate stack is covered by the first hard mask layer.14. The method of claim 13 , wherein a second hard mask layer is formed on top of the first hard mask layer.15. The method of claim 14 , wherein a combined width of the upper portion of the vertical fin and the gate stack are about a same as a width of the second hard mask layer.16. The method of claim 13 , wherein the first hard mask layer has a width about a same as the upper portion of the vertical fin.17. The method of claim 14 , wherein the first and second hard mask layers are different materials.18. The method of claim 14 , wherein a spacer layer is formed on the vertical fin claim 14 , the gate stack claim 14 , the first hard mask layer claim 14 , and a second hard mask layer.19. The method of claim 14 , wherein the first hard mask layer includes an oxide material claim 14 , and the second hard mask layer ...

Vertical transport field effect transistor with precise gate length definition

Techniques relate to a gate stack for a semiconductor device. A vertical fin is formed on a substrate. The vertical fin has an upper portion and a bottom portion. The upper portion of the vertical fin has a recessed portion on sides of the upper portion. A gate stack is formed in the recessed portion of the upper portion of the vertical fin.

NANOSHEET CHANNEL-TO-SOURCE AND DRAIN ISOLATION

A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate. 1. A structure used to fabricate a nanosheet semiconductor device , the structure comprising:a substrate;a set of silicon layers formed above the substrate, wherein the silicon layers of the set of silicon layers are parallel to each other and include gaps between adjacent ones of the silicon layers of the set of silicon layers, wherein each of the gaps defines a region that is parallel to the silicon layers of the set of silicon layers and extends from a first end to a second end of each of the adjacent ones of the silicon layers of the set of silicon layers; andan inner spacer at the first end and at the second end of each of the gaps between the adjacent ones of the silicon layers of the set of silicon layers.2. The structure according to claim 1 , wherein the inner spacer includes silicon nitride (SiN).3. The structure according to claim 1 , wherein the inner spacer is a low-k spacer.4. The structure according to claim 3 , wherein the low-k spacer includes silicon boron carbon nitride (SiBCN).5. The structure according to claim 3 , wherein the low-k spacer includes silicon oxycarbonitride ...

Sub-Fin Removal for SOI Like Isolation with Uniform Active Fin Height

Sub-fin removal techniques for SOI like isolation in finFET devices are provided. In one aspect, a method for forming a finFET device includes: etching partial fins in a substrate, wherein the partial fins include top portions of fins of the finFET device; forming a bi-layer spacer on the top portions of the fins; complete etching of the fins in the substrate to form bottom portions of the fins of the finFET device; depositing an insulator between the fins; recessing the insulator enough to expose a region of the fins not covered by the bi-layer spacer; removing the exposed region of the fins to create a gap between the top and bottom portions of the fins; filling the gap with additional insulator. A method for forming a finFET device is also provided where placement of the fin spacer occurs after (rather than before) insulator deposition. A finFET device is also provided. 1. A method of forming a fin field effect transistor (finFET) device , the method comprising:forming a patterned fin hardmask on a substrate;etching fins in the substrate using the patterned fin hardmask;depositing an insulator between the fins;recessing the insulator enough to expose top portions of the fins;depositing a spacer onto the exposed top portions of the fins;further recessing the insulator enough to expose a region of bottom portions of the fins not covered by the spacer;removing the exposed region of the bottom portions of the fins to create a gap between the top and bottom portions of the fins;filling the gap with additional insulator;forming a gate over a portion of the fins that serves as a channel region of the finFET device;forming gate spacers on opposite sides of the gate; andforming source and drain regions on opposite sides of the gate, offset by the gate spacers.2. The method of claim 1 , wherein the substrate is a bulk semiconductor substrate.3. The method of claim 2 , wherein the bulk semiconductor substrate comprises a material selected from the group consisting of: ...

TECHNIQUES FOR MIGRATION PATHS

Exemplary embodiments described herein relate to a destination path for use with multiple different types of VMs, and techniques for using the destination path to convert, copy, or move data objects stored in one type of VM to another type of VM. The destination path represents a standardized (canonical) way to refer to VM objects from a proprietary VM. A destination location may be specified using the canonical destination path, and the location may be converted into a hypervisor-specific destination location. A source data object may be copied or moved to the destination location using a hypervisor-agnostic path. 1. A method , comprising:generating a snapshot of a volume accessible to a source virtual machine managed by a source hypervisor;modifying a header of a first virtual disk of the source virtual machine to be compatible with a destination virtual machine to create a modified header; andcreating a second virtual disk for the destination virtual machine to comprise the modified header and a pointer to content of the first virtual disk within the snapshot of a volume, wherein a destination file path is modified to be in a format compatible with the destination virtual machine and a destination hypervisor based upon configuration information identified by querying a storage mapping using the destination file path.2. The method of claim 1 , comprising:identifying the configuration information by querying the storage mapping using the destination file path to obtain a translation of the destination file path to a destination hypervisor specific destination location utilized by the destination hypervisor.3. The method of claim 2 , comprising:modifying the destination file path based upon the destination hypervisor specific destination location.4. The method of claim 1 , comprising:updating the storage mapping in real-time based upon detected changes to storage locations assigned to the destination virtual machine.5. The method of claim 1 , wherein the destination ...

Novel method of synthesising ivabradine and the salts thereof for addition to a pharmaceutically acceptable acid

Method of synthesising ivabradine of formula (I), the salts thereof for addition to a pharmaceutically acceptable acid and the hydrates thereof. The crystalline form a of ivabradine hydrochloride is also described, as are drugs comprising same.

LIQUID ORAL FORMULATION OF BUMETANIDE

The invention relates to a liquid oral formulation of bumetanide for the treatment of autism, more particularly for the improvement of the Autism Spectrum Disorder (ASD) core symptoms, tuberous sclerosis complex, fragile X syndrome, Rett syndrome, Down syndrome, cancer and particularly gliomas, spinal cord lesions, chronic pain, brain trauma, cerebrovascular infarcts, various types of epilepsies, and also acute lung injury such as pneumonias or Severe Acute Respiratory Disease due to Coronavirus-2 (SARS-CoV-2). Said formulation is especially designed for paediatric populations. The invention relates also to a posology for the administration of said liquid oral formulation. 1. A liquid oral formulation for use in the treatment of a patient in need thereof consisting of:an amount of 0.5 mg/ml of bumetanide;an effective amount of an antimicrobial preservative or a combination of antimicrobial preservatives;a buffering agent or a combination of buffering agents;a sweetening agent; andwater.2. The formulation of wherein the antimicrobial preservative is selected from sodium benzoate claim 1 , sorbate claim 1 , salt of edetate claim 1 , benzaldionium chloride and paraben claim 1 , salts thereof or a combination thereof.3. The formulation of claim 1 , wherein the antimicrobial preservative is selected from alkyl paraben salts claim 1 , and preferably a combination of alkyl paraben salts.4. The formulation of wherein the combination of antimicrobial preservative compounds consists in sodium methyl paraben combined with sodium propyl paraben.5. The formulation of claim 1 , wherein the buffering agent is selected from carbonates claim 1 , citrates claim 1 , gluconates claim 1 , lactates claim 1 , phosphates or tartrates claim 1 , or a combination thereof.6. The formulation of claim 5 , wherein the buffering agent is a combination of sodium dihydrogen phosphate dihydrate and disodium phosphate.7. The formulation of claim 1 , wherein the sweetening agent is selected from ...

CRYSTALLINE BETA FORM OF IVABRADINE HYDROCHLORIDE, PROCESS FOR PREPARING THE SAME, AND PHARMACEUTICAL COMPOSITIONS CONTAINING THE SAME

CRYSTALLINE FORM 6 OF IVABRADINE HYDROCHLORIDE, PROCESS FOR PREPARING THE SAME, AND PHARMACEUTICAL COMPOSITIONS CONTAINING THE SAME

NEW PROCESS FOR THE SYNTHESIS OF AGOMELATIN

New synthesis process and new crystalline form for agomelatine, and pharmaceutical compositions containing it

Procédé de synthèse industrielle et forme cristalline II du composé de formule (I) (voir formule I)

IVABRADINE HYDROCHLORIDE BETA D-CRYSTALLINE FORM, PROCESS FOR PREPARING THE SAME, AND PHARMACEUTICAL COMPOSITIONS CONTAINING THE SAME

NOVEL PROCESS FOR THE SYNTHESIS OF IVABRADINE AND ITS SALTS OF ADDITION TO A PHARMACEUTICALLY ACCEPTABLE ACID

CRYSTALLINE GAMMA D FORM OF IVABRADINE HYDROCHLORIDE, PROCESS FOR PREPARING THE SAME, AND PHARMACEUTICAL COMPOSITIONS CONTAINING THE SAME

CRYSTALLINE BETA FORM OF IVABRADINE HYDROCHLORIDE, ITS PREPARATION PROCEDURE, AND PHARMACEUTICAL COMPOSITIONS CONTAINING IT

SE REFIERE A UNA FORMA CRISTALINA BETA DEL CLORHIDRATO DE IVABRADINA CARACTERIZADA POR PARAMETROS DEFINIDOS DE DIAGRAMA DE DIFRACCION X SOBRE POLVO MEDIDO EN DIFRACTOMETRO PANALYTICAL X'PERT PRO CON UN DETECTOR X'CELERATOR. SE REFIERE TAMBIEN A UN PROCEDIMIENTO DE PREPARACION QUE COMPRENDE: A) CALENTAR UNA MEZCLA DE CLORHIDRATO DE IVABRADINA, ISOPROPANOL Y AGUA HASTA DISOLUCIO COMPLETA; B) ENFRIAR PROGRESIVAMENTE HASTA CRISTALIZACION COMPLETA; Y A UNA COMPOSICION FARMACEUTICA SIENDO UTILES COMO BRADICARDIZANTES REFERS TO A BETA CRYSTALLINE FORM OF IVABRADINE HYDROCHLORIDE CHARACTERIZED BY DEFINED PARAMETERS OF X DIFRACTION DIAGRAM ON POWDER MEASURED BY PANALYTICAL X'PERT PRO DIFRACTOMETER WITH AN X'CELERATOR DETECTOR. IT ALSO REFERS TO A PREPARATION PROCEDURE WHICH INCLUDES: A) HEATING A MIXTURE OF IVABRADINE HYDROCHLORIDE, ISOPROPANOL AND WATER TO COMPLETE SOLUTION; B) COOL PROGRESSIVELY UNTIL COMPLETE CRYSTALIZATION; AND A PHARMACEUTICAL COMPOSITION BEING USEFUL AS BRADICARDIZERS

RECTIFIER FOR AN AIRCRAFT TURBOMACHINE, AN AIRCRAFT TURBOMACHINE EQUIPPED WITH SUCH A RECTIFIER.

L’invention concerne un redresseur (10) pour une turbomachine d’aéronef, ce redresseur (10) comportant deux viroles (20, 30) annulaires coaxiales, respectivement interne (20) et externe (30), reliées ensemble par des aubes (11) qui sont chacune pleine et venue de matière avec les viroles (20, 30), la virole externe (30) comportant une surface annulaire externe (31) reliée à au moins un crochet (32) de fixation du redresseur (10), et la virole interne (20) comportant une surface annulaire interne (21) reliée à un support (22) d’un revêtement abradable, caractérisé en ce qu’au moins une desdites surfaces interne (21) et externe (31) comporte des évidements (42’’, 43’’) qui sont situés au droit des aubes (11) et qui sont configurés de façon à ce que les aubes (11) soient reliées à la virole (20, 30) correspondante. L’invention concerne également une turbomachine d’aéronef, comportant au moins un redresseur (10) tel que décrit précédemment. Figure pour l'abrégé : Figure 2 The invention relates to a rectifier (10) for an aircraft turbomachine, this rectifier (10) comprising two coaxial annular shrouds (20, 30), respectively internal (20) and external (30), connected together by vanes (11 ) which are each solid and integral with the ferrules (20, 30), the outer ferrule (30) comprising an outer annular surface (31) connected to at least one hook (32) for fixing the rectifier (10), and the inner shroud (20) comprising an inner annular surface (21) connected to a support (22) of an abradable coating, characterized in that at least one of the said inner (21) and outer (31) surfaces comprises recesses ( 42'', 43'') which are located in line with the vanes (11) and which are configured so that the vanes (11) are connected to the corresponding shroud (20, 30). The invention also relates to an aircraft turbine engine, comprising at least one rectifier (10) as described above. Figure for abstract: Figure 2

TRACTABLE AND / OR AUTONOMOUS HYBRID TRAILER, ALL-TERRAIN AND AMPHIBIOUS FOR MOVING A CARGO IN A DRIVE ZONE AND / OR IN A NON-DRIVE ZONE

La présente invention concerne une remorque hybride (100) comprenant une structure porteuse (10) sur laquelle sont montés un essieu arrière (20) comprenant une paire de roues arrière (21) escamotables; un système de chenilles (30) motorisées rétractable ; et des moyens de commande (50) de l’essieu arrière (20) et du système de chenilles (30) autorisant le passage d’une configuration de route vers une configuration autonome (C2), ou inversement dans laquelle : - en configuration de route, les roues arrière (21) sont en contact avec le sol et le système de chenilles (30) est rétracté pour un déplacement en zone carrossable par un véhicule tracteur, et - en configuration autonome (C2), ledit système de chenilles (30) est en contact avec le sol et les roues arrière (21) sont escamotées pour un déplacement autonome en zone non carrossable par ledit système de chenilles (30). Figure d’abrégé : figure 3 The present invention relates to a hybrid trailer (100) comprising a carrying structure (10) on which are mounted a rear axle (20) comprising a pair of retractable rear wheels (21); a retractable motorized track system (30); and control means (50) of the rear axle (20) and of the track system (30) allowing the passage from a road configuration to an autonomous configuration (C2), or vice versa in which: - in the configuration of road, the rear wheels (21) are in contact with the ground and the track system (30) is retracted for movement in a drivable area by a towing vehicle, and - in autonomous configuration (C2), said track system (30) ) is in contact with the ground and the rear wheels (21) are retracted for autonomous movement in a non-drivable zone by said track system (30). Abstract figure: Figure 3

CRYSTALLINE GAMMA D FORM OF IVABRADINE HYDROCHLORIDE, PROCESS FOR PREPARING THE SAME, AND PHARMACEUTICAL COMPOSITIONS CONTAINING THE SAME

caractérisée par son diagramme de diffraction X sur poudre. Médicaments. characterized by its powder X-ray diffraction pattern. Drugs.

NOVEL PROCESS FOR THE SYNTHESIS OF IVABRADINE AND ITS SALTS OF ADDITION TO A PHARMACEUTICALLY ACCEPTABLE ACID

Procédé de synthèse de l'ivabradine de formule (I) :et de ses sels d'addition à un acide pharmaceutiquement acceptable. Process for the synthesis of ivabradine of formula (I): and of its addition salts with a pharmaceutically acceptable acid.

NEW PROCESS FOR THE SYNTHESIS OF AGOMELATIN

Procédé de synthèse industrielle du composé de formule (I) Process for the industrial synthesis of the compound of formula (I)

Device for launching and / or raising a boat and vehicle comprising such a device

La présente invention concerne un dispositif de mise à l’eau et/ou de remontée (100) d’une embarcation (300) comprenant un bras articulé (10) monté en liaison pivot sur une structure porteuse (20) et autorisant le passage d’une position de repos dans laquelle ledit bras (10) est sensiblement rabattu vers une position d’arrimage dans laquelle ledit bras (10) est sensiblement en équerre par rapport à ladite structure porteuse (20), ou inversement, l’extrémité distale dudit bras (10) présente un axe d’arrimage (12) sensiblement parallèle à l’axe de pivotement (11) dudit bras (10) et apte à venir coopérer, lors du pivotement de la position de repos à la position d’arrimage, avec un système d’accroche (30) solidaire de la coque (301) de l’embarcation (300) pour permettre l’arrimage de ladite embarcation (300). Figure d’abrégé : figure 8 The present invention relates to a device for launching and / or raising (100) a boat (300) comprising an articulated arm (10) pivotally mounted on a supporting structure (20) and allowing the passage of 'a rest position in which said arm (10) is substantially folded back towards a stowed position in which said arm (10) is substantially at right angles to said supporting structure (20), or vice versa, the distal end of said arm (10) has a lashing axis (12) substantially parallel to the pivot axis (11) of said arm (10) and able to cooperate, during pivoting from the rest position to the stowed position, with an attachment system (30) integral with the hull (301) of the boat (300) to allow the stowage of said boat (300). Abstract figure: Figure 8

HYBRID TRACTABLE AND / OR AUTONOMOUS, ALL-TERRAIN AND AMPHIBIOUS TRAILER FOR MOVING A CARGO IN A DRIVING ZONE AND / OR IN A NON-DRIVING ZONE

La présente invention concerne une remorque hybride (100) comprenant une structure porteuse (10) sur laquelle sont montés un essieu arrière (20) comprenant une paire de roues arrière (21) escamotables; un système de chenilles (30) motorisées rétractable ; et des moyens de commande (50) de l’essieu arrière (20) et du système de chenilles (30) autorisant le passage d’une configuration de route vers une configuration autonome (C2), ou inversement dans laquelle : - en configuration de route, les roues arrière (21) sont en contact avec le sol et le système de chenilles (30) est rétracté pour un déplacement en zone carrossable par un véhicule tracteur, et - en configuration autonome (C2), ledit système de chenilles (30) est en contact avec le sol et les roues arrière (21) sont escamotées pour un déplacement autonome en zone non carrossable par ledit système de chenilles (30). Figure d’abrégé : figure 3 The present invention relates to a hybrid trailer (100) comprising a supporting structure (10) on which are mounted a rear axle (20) comprising a pair of retractable rear wheels (21); a retractable motorized track system (30); and control means (50) of the rear axle (20) and of the track system (30) allowing the passage from a road configuration to an autonomous configuration (C2), or vice versa in which: - in the configuration of road, the rear wheels (21) are in contact with the ground and the track system (30) is retracted for movement in a drivable area by a towing vehicle, and - in autonomous configuration (C2), said track system (30) ) is in contact with the ground and the rear wheels (21) are retracted for autonomous movement in a non-drivable zone by said track system (30). Abstract figure: Figure 3

Novel perindopril salt and pharmaceutical compositions containing same

The invention relates to a novel perindopril salt and pharmaceutical compositions containing same. The invention is used for medicaments.

βd-crystalline form of ivabradine hydrochloride, a process for its preparation and pharmaceutical compositions containing it

A βd-Crystalline form of ivabradine hydrochloride of formula (I): characterized by its powder X-ray diffraction data. Medicinal products containing the same which are useful as bradycardics.

IVABRADINE HYDROCHLORIDE BETA D-CRYSTALLINE FORM, PROCESS FOR PREPARING THE SAME, AND PHARMACEUTICAL COMPOSITIONS CONTAINING THE SAME

caractérisée par son diagramme de diffraction X sur poudre. Médicaments. characterized by its powder X-ray diffraction pattern. Drugs.

NEW PROCESS FOR SYNTHESIS OF IVABRADINE AND ITS ADDITIONAL SALTS WITH A PHARMACEUTICALLY ACCEPTABLE ACID

NOUVEAU PROCEDE DE SYNTHESE DE L'IVABRADINE ET DE SES SELS D'ADDITION A UN ACIDE PHARMACEUTIQUEMENT ACCEPTABLE Procédé de synthèse de l'ivabradine de formule (I): de ses sels d'addition à un acide pharmaceutiquement acceptable et de ses hydrates. Forme cristalline a du chlorhydrate de l'ivabradine. Médicaments. NEW PROCESS FOR THE SYNTHESIS OF IVABRADINE AND ITS SALTS OF ADDITION TO A PHARMACEUTICALLY ACCEPTABLE ACID Process for the synthesis of ivabradine of formula (I): its addition salts with a pharmaceutically acceptable acid and its hydrates. Crystalline form has ivabradine hydrochloride. Drugs.

BETA CRYSTALINE FORM OF IVABRADINE CHLORHYDRATE, ITS PREPARATION PROCEDURE AND PHARMACEUTICAL COMPOSITIONS CONTAINING IT

Forma crsitalina Bd del clorihidrato de ivabradina segun la formula (I) de la presente solicitud, caracterizada por el digrama de difraccion X sobre polvo siguiente, medido en un difractometro PANalytical X'Per Pro con un detector X'Celerator, y expresado en terminos de posicion de linea (angulo de Bragg 2 theta, expresado en grados); altura de linea (expresado en cuentas), superficie de linea (expresado en cuentas x grados); anchura a media altura de las lineas ("FWHM, expresada en grados) y distancia interreticular d (expresadqa en A).

New process for the synthesis and new crystalline form of agomelatine and pharmaceutical compositions containing it

New Process For The Synthesis And New Crystalline Form Of Agomelatine And Pharmaceutical Compositions Containing It Abstract The invention relates to a process for the industrial synthesis and new crystalline form of the compound of formula (1): NHCOMe MeO (I) Medicaments comprising the new crystalline form of the compound of formula (1) and its use in therapy are also disclosed.

Gamma d-crystalline form of ivabradine hydrochloride, a process for its preparation and pharmaceutical compositions containing it

A γd-Crystalline form of ivabradine hydrochloride of formula (I): characterised by its powder X-ray diffraction data. Medicinal products containing the same which are useful as bradycardics.

Crystalline form gamma-d of the chlorohydrate of ivabradine, process for its preparation and pharmaceutical compositions containing it

Kristalni oblik γd ivabradin hidroklorida formule (I):naznačen time, daje određen sljedećim dijagramom difrakcije X-zraka na prašku, izmjereno difraktometrom PANalytical X'Pert Pro s detektorom X'Celerator, izraženo u kategorijama položaja zrake (Braggov kut 2 theta, izražen u stupnjevima), visine zrake (izraženo zbrojem), površine zrake (izraženo zbrojem pomnoženo sa stupnjevima), širine zrake na polovici visine ("FWHM", izraženo u stupnjevima) i interplanarne udaljenosti d (izraženo u A): Crystalline form γd of ivabradine hydrochloride of formula (I): characterized by the following powder X-ray diffraction pattern, measured by a PANalytical X'Pert Pro diffractometer with an X'Celerator detector, expressed in beam position categories, expressed in Bragg angle 2 theta, expressed in degrees), beam heights (expressed as a sum), beam surfaces (expressed as a sum multiplied by degrees), beam widths at half height ("FWHM", expressed in degrees) and interplanar distances d (expressed in A):

New process for synthesizing ivrabradine and its pharmaceutically acceptable acid addition salts

Procédé de synthèse de l'ivabradine de formule (I): de ses sels d'addition à un acide phanmaceutiquement acceptable et de ses hydrates. Forme cristalline a du chlorhydrate de l'ivabradine.

Puzzle with polycubes of distributed and low complexity for building cube and other shapes

An assembly puzzle comprising different polycubes that can be arranged to form a cube comprising sixty-four unit cubes. Included in the puzzle are polycubes of a sufficiently distributed complexity to allow meaningful hints to be given without actually providing a solution. Furthermore, the polycubes can be arranged in different configurations to build a wide variety of shapes other than a cube.

Salt of perindopril and pharmaceutical preparations containing it. Drugs.

Super long channel device within VFET architecture

Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.

Method and structure for enabling controlled spacer RIE

A method and structure to enable reliable dielectric spacer endpoint detection by utilizing a sacrificial spacer fin are provided. The sacrificial spacer fin that is employed has a same pitch as the pitch of each semiconductor fin and the same height as the dielectric spacers on the sidewalls of each semiconductor fin. Exposed portions of the sacrificial spacer fin are removed simultaneously during a dielectric spacer reactive ion etch (RIE). The presence of the sacrificial spacer fin improves the endpoint detection of the spacer RIE and increases the endpoint signal intensity.

A-CRYSTAL FORM OF RANELIC STRONTIUM, METHOD OF PREPARATION AND PHARMACEUTICAL COMPOSITIONS CONTAINING IT

α-κρυσταλλική μορφή του ρανελικού στροντίου του τύπου (Ι): α-crystalline form of the strontium ranelike of formula (I):

$g(d)d crystalline form of ivabradine hydrochloride, preparation method thereof and pharmaceutical compositions containing same

The invention relates to the δd crystalline form of ivabradine hydrochloride having general formula (I), which is characterised by its X-ray diffraction pattern on powder. The invention is suitable for medicaments.

Alpha crystalline form of strontium ranelate, process for its preparation, and pharmaceutical compositions containing it.

Single spacer for complementary metal oxide semiconductor process flow

A method of forming a semiconductor device that includes forming a high-k dielectric fin liner on the first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region, and forming a gate structure including a low-k dielectric gate sidewall spacer on the channel region of the first and second plurality of fin structures. A first epitaxial semiconductor material on the first plurality of fin structures from which the high-k dielectric fin liner has been removed. The first epitaxial semiconductor material is then oxidized, and a remaining portion of the high-k dielectric fin liner is removed. A second epitaxial semiconductor material is formed on the second plurality of fin structures.

Shoe and process of making the same

IVABRADINE SYNTHESIS PROCEDURE AND ITS ADDITION SALTS OF A PHARMACEUTICALLY ACCEPTABLE ACID.

Procedimiento de síntesis de ivabradina, de fórmula (I): (Ver fórmula) o 3-{3-[{[(7S)-3, 4-dimetoxibiciclo[4.2.0]octa-1, 3, 5-trien-7-il]metil}(metil) amino]propil}-7, 8-dimetoxi-1, 3, 4, 5-tetrahidro-2H-3-benzazepin-2-ona, de sus sales de adición de un ácido farmacéuticamente aceptable y de sus hidratos, caracterizado porque se somete el compuesto de fórmula (V): (Ver fórmula) donde R1 y R2, idénticos o diferentes, representan cada uno un grupo alcoxi(C1-C8) lineal o ramificado, o bien forman, junto con el átomo de carbono que los porta, un ciclo 1, 3-dioxano, 1, 3-dioxolano o 1, 3-dioxepano, a una reacción de hidrogenación catalítica, y luego porque el compuesto de fórmula (VI) así obtenido: (Ver fórmula) donde R1 y R2 son como se han definido anteriormente, se somete a reacción con el compuesto de fórmula (VII): (Ver fórmula) donde HX representa un ácido farmacéuticamente aceptable, en presencia de hidrógeno y de un catalizador, para conducir directamente, después de filtración del catalizador y separación, a la sal de adición de ivabradina con el ácido HX, que se somete eventualmente, cuando se desea acceder a la ivabradina libre, a la acción de una base. Method of synthesis of ivabradine, of formula (I): (See formula) or 3- {3 - [{[(7S) -3, 4-dimethoxybicyclo [4.2.0] octa-1, 3, 5-trien-7 -yl] methyl} (methyl) amino] propyl} -7,8-dimethoxy-1,3,4,5-tetrahydro-2H-3-benzazepin-2-one, of its addition salts of a pharmaceutically acceptable acid and of its hydrates, characterized in that the compound of formula (V) is subjected: (See formula) where R1 and R2, identical or different, each represent a linear or branched (C1-C8) alkoxy group, or they form, together with the carbon atom that carries them, a 1,3-dioxane, 1,3-dioxolane or 1,3-dioxepane cycle, to a catalytic hydrogenation reaction, and then because the compound of formula (VI) thus obtained: (See formula) where R1 and R2 are as defined above, it is reacted with the compound of formula (VII): (See formula) ...

Supply chain disruption advisor

In an approach to generating advice for supply chain disruptions, one or more computer processors receive a query associated with a supply chain disruption. The one or more computer processors retrieve data corresponding to the supply chain disruption. Based on the retrieve data, the one or more computer processors determine one or more solutions to the supply chain disruption. The one or more computer processors display the one or more determined solutions. The one or more computer processors receive a selection of one of the one or more determined solutions. The one or more computer processors detect one or more patterns associated with the selected solution.

Bd crystalline form of ivabradine chlorhydrate, process for the preparation thereof and pharmaceutical compounds containing it

Forme cristalline .beta.d du chlorhydrate de l'ivabradine de formule (I ): (voir formule I), HC1~ caractérisée par son diagramme de diffraction X sur poudre.