CELLULAR MODEM PROCESSING

A cellular mobile station including a modem processor and memory. The memory includes instructions for the modem processor to perform layer processor operations, layer processor operations, and layer processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol. In one example, the mobile station includes different levels of memory to provide different deterministic access times 146-. (canceled)47. An integrated circuit for a cellular mobile station , the cellular mobile station communicating as per a cellular communication protocol , the integrated circuit comprising:{'b': 1', '2', '3, 'a cellular modem processor, the cellular modem processor to execute instructions to perform a layer processor operations of the cellular communication protocol, instructions to perform a layer processor operation of the cellular communication protocol, and instructions to perform a layer processor operation of the cellular communication protocol when the integrated circuit is operational; and'}a second processor;at least one memory;wherein the second processor performs untrusted processor operations, wherein untrusted processor operations are not performed by the cellular modem processor.48. The integrated circuit of wherein processor operations which have not been validated to be nonmalicious are not performed by the cellular modem processor.49. The integrated circuit of wherein processor operations which have not been validated to be nonmalicious are performed by the second processor.50. The integrated circuit of wherein the second processor does not perform modem processor operations.51. The integrated circuit of wherein the second processor does not perform modem processor operations.52. The integrated circuit of wherein the second processor does not perform modem processor operations.5312. The integrated circuit of wherein the cellular modem ...

Method and System for Phase Compensation in Multi-Path Communication Device

A method and apparatus for a radio base station () aligns IQ data blocks for transmission over multiple radio frequency (RF) signal paths () between a base station controller () and a plurality of antennas () at the base station by determining a path delay () for each RF signal path, and then transmitting IQ data blocks from JESD 204 transmit interfaces (-) over each RF signal path ahead of a first predetermined time slot by an advance time period equaling the path delay for each RF signal path, thereby aligning IQ data block signaling to the first predetermined time slot at the antennas. 1. A method for operating a base station comprising a plurality of communication signal paths over a plurality of transceiver front ends to a plurality of antennas at the base station , comprising:obtaining a plurality of path delay values for the plurality of communication signal paths; andfor each of the plurality of communication signal paths, transmitting one or more data blocks onto said communication signal path ahead of a first predetermined time slot by an advance time period compensating for the path delay value for said communication signal path, thereby aligning data block signaling over said communication signal path to the first predetermined time slot.2. The method of claim 1 , where obtaining the plurality of path delay values comprises:measuring a path delay value for each of the plurality of communication signal paths in the field, orretrieving a factory-calibrated path delay value for each of the plurality of communication signal paths.3. The method of claim 1 , where transmitting one or more data blocks comprises:generating a first phase alignment pulse signal for a first communication signal path in advance of the first predetermined time slot by a first advance time period; andproviding the first phase alignment pulse signal to a serial interface for the first communication signal path to trigger transmission of the one or more data blocks over the first ...

Method and System for Automatically Controlling the Insertion of Control Word in CPRI Daisy Chain Configuration

A method and apparatus automatically controls the insertion of information flow data over a shared CPRI link () by providing a hardware control mechanism (-) at a local radio base station subsystem () connected in a CPRI daisy chain configuration between a downstream RE device () and an upstream REC device () for determining whether the control word being transmitted is sourced from a downstream device (e.g., forwarded data from a downstream RE device) or from the local device. 1. A method for operating a local base station subsystem connected between first and second base station subsystems over first and second common interface links in a daisy chain configuration , comprising:programming one or more mask update registers to store an update bitmap with a plurality of insert control values having either a first or second value, where the plurality of insert control values correspond to one or more predetermined words in a corresponding plurality of basic frames;switching into a radio data frame for transmission to the second base station subsystem one or more inserted words from system memory of the local base station subsystem for each insert control value from the update bitmap having the first value by inserting at least a first inserted word into a first basic frame corresponding to a first insert control value having the first value.2. The method of claim 1 , where programming one or more mask update registers occurs during configuration of the first and second common interface links.3. The method of claim 1 , where the first and second common interface links respectively comprise first and second Common Public Radio Interface (CPRI) serial interface links.4. The method of claim 1 , where programming one or more mask update registers comprises programming 8×32-bit mask update registers to store the update bitmap with 256 insert control values claim 1 , where each of the 256 insert control values correspond uniquely to a control word in one of the plurality of ...

Method and System for Low Power Transmission and Data Alignment

A method and apparatus automatically maintains a JESD204 serial data link () as active by using an idle signal () and multiplexer selection circuit () to selectively switch signal data samples () and dummy samples () onto a serial interface input to a JESD module () for serialization into a plurality of symbols for transmission over the JESD204 serial data link () in response to a transmit clock signal () so that serialized symbols generated from signal data samples are transmitted when there are signal data samples available, and serialized symbols generated from dummy samples are transmitted when there are no signal data samples available. 1. A method for operating a first base station subsystem , comprising:generating signal data samples for transmission over a first high speed serial data link;generating dummy samples for transmission over the first high speed serial data link;switching the signal data samples and dummy samples onto a serial interface input in response to an idle condition having first and second values such that any available signal data samples are switched onto the serial interface input when the idle condition is of a first state, and dummy samples are switched onto the serial interface input when the idle condition is of a second state;serializing samples from the serial interface input into a plurality of symbols for transmission over the first high speed serial data link; andtransmitting the plurality of symbols over the first high speed serial data link, wherein the first high speed serial data link is maintained as active by transmitting serialized symbols generated from dummy samples when there are no signal data samples available.2. The method of claim 1 , further comprising generating an idle clock signal having first and second values in response to the idle condition having first and second values.3. The method of claim 1 , where the first high speed serial data link is a JESD204-compliant serial interface link.4. The method of ...

PROGRAMMABLE DIRECT MEMORY ACCESS CHANNELS

A storage location of a device that can be configured to act as a master in a particular security mode, such as a Direct Memory Access (DMA) having one or more channels, can be programmed to indicate a security indicator to be provided when configured to operate as a master device.

Programmable direct memory access channels

A storage location of a device that can be configured to act as a master in a particular security mode, such as a Direct Memory Access (DMA) having one or more channels, can be programmed to indicate a security indicator to be provided when configured to operate as a master device.

Data processing system having a serial data controller

A data processing system (30) includes two processors (70, 80) and a serial data controller (36) for selectively multiplexing serial data signals between one or more of a plurality of serial data devices (40, 42, 44, 46, 74, 76, 82) The serial data controller (36) includes one or more host ports (50, 52, 54) and one or more peripheral ports (56, 58, 60, 62) coupled together through a switching matrix (64). A control circuit (66) and a plurality of control registers (68) are used to configure and control a serial data path created between two or more ports including clock and frame synchronization timing of the data path.

Method and apparatus for selecting cache ways available for replacement

In a multi-way cache, a method for selecting N ways available for replacement includes providing a plurality of rulesets (102, 108) where each one of the plurality of rulesets specifies N ways in the cache that are available for replacement (where N is equal to or greater than zero). The method further includes receiving an access address, and using at least a portion of the access address to select one of the plurality of rulesets. The selected one of the plurality of rulesets (110) may then be used to select N ways in that cache that are available for replacement. One embodiment uses the high order bits of the access address (40) to select a ruleset. An alternate embodiment uses at least a portion of the access address and a ruleset selector control register to select the ruleset. Yet another embodiment uses the access address and address range comparators to select the ruleset.

Data processor with development support features

Timer channel with multiple timer reference features

Method and system for automatically controlling the insertion of control word in CPRI daisy chain configuration

A method and apparatus automatically controls the insertion of information flow data over a shared CPRI link ( 561 ) by providing a hardware control mechanism ( 504 - 509 ) at a local radio base station subsystem ( 501 ) connected in a CPRI daisy chain configuration between a downstream RE device ( 570 ) and an upstream REC device ( 560 ) for determining whether the control word being transmitted is sourced from a downstream device (e.g., forwarded data from a downstream RE device) or from the local device.

Data processing system having a serial data controller

A data processing system (30) includes two processors (70, 80) and a serial data controller (36) for selectively multiplexing serial data signals between one or more of a plurality of serial data devices (40, 42, 44, 46, 74, 76, 82) The serial data controller (36) includes one or more host ports (50, 52, 54) and one or more peripheral ports (56, 58, 60, 62) coupled together through a switching matrix (64). A control circuit (66) and a plurality of control registers (68) are used to configure and control a serial data path created between two or more ports including clock and frame synchronization timing of the data path.

Cellular modem processing

A cellular mobile station (101) including a modem processor (127) and memory (129). The memory includes instructions for the modem processor to perform layer 1 processor operations, layer 2 processor operations, and layer 3 processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol. In one example, the mobile station includes different levels of memory to provide different deterministic access times.

Integrated circuit power management for reducing leakage current in circuit arrays and method therefor

Authenticated debug access for field returns

Authenticated debug access for field returns

Under the direction of a first party, an integrated circuit (IC) device (202) is configured to temporarily enable access to a debug interface (216) of the IC device (202) via authentication of the first party by a challenge/response process using a key (321, 322) of the IC device (202) and a challenge value (324) generated at the IC device (202). The first party then may conduct a software evaluation of the IC device (202) via the debug interface (216). In response to failing to identify an issue with the IC device (202) from the software evaluation, the first party can permanently enable open access to the debug interface (216) while authenticated and provide the IC device (202) to a second party. Under the direction of the second party, a hardware evaluation of the IC device (202) is conducted via the debug interface (216) that was permanently opened by the first party.

Authenticated debug access for field returns

Authenticated debug access for field returns

Under the direction of a first party, an integrated circuit (IC) device (202) is configured to temporarily enable access to a debug interface (216) of the IC device (202) via authentication of the first party by a challenge/response process using a key (321, 322) of the IC device (202) and a challenge value (324) generated at the IC device (202). The first party then may conduct a software evaluation of the IC device (202) via the debug interface (216). In response to failing to identify an issue with the IC device (202) from the software evaluation, the first party can permanently enable open access to the debug interface (216) while authenticated and provide the IC device (202) to a second party. Under the direction of the second party, a hardware evaluation of the IC device (202) is conducted via the debug interface (216) that was permanently opened by the first party.

Method and apparatus for entering a low power mode

A method and apparatus for entering a low power mode is provided. In one embodiment, data processing system (10) has power control circuitry (52) which may be used to control power usage in data processing system (10). Power mode select circuitry (84) may be used to select a power mode. Depending upon the power mode selected, power control circuitry (52) may use a cascaded approach to selecting which portions of data processing system (10) will be powered down, and thus how deeply data processing system (10) will be powered down.

Method and system for exchanging data

The invention concerns a method (300) and system for exchanging data in a multi-core architecture having at least one shared memory. The method can include the steps of requesting (312) data in a first format from a predetermined range of addresses in the shared memory in which the data is shared between different processors, storing (316) the requested data in a cache to be retrieved by a format converter and identifying (320) to the format converter a data type for the data. The method can also include the step of, with the format converter, translating (322) based on predetermined rules the data to a second format that is native to a processor that will process the data.

Method and system for employing adaptive event codes

The invention concerns a method (500) for employing adaptive event codes. The method includes the steps of generating (512) at least one adaptive event code in which the adaptive event code corresponds to a preexisting event code, storing (514) the adaptive event code in at least one table (154, 156), running (516) the table in which the adaptive event codes are at least initially disabled and enabling (522) the adaptive event code in response to a system event in which the preexisting event code that corresponds to the enabled adaptive event code is executed (526). The method can further include the step of ignoring (518) the adaptive event codes during the running step when the adaptive event codes are disabled.

Verfahren und system zur verwendung adaptiver ereigniscodes

Method and system for employing adaptive event codes

The invention concerns a method (500) for employing adaptive event codes. The method includes the steps of generating (512) at least one adaptive event code in which the adaptive event code corresponds to a preexisting event code, storing (514) the adaptive event code in at least one table (154, 156), running (516) the table in which the adaptive event codes are at least initially disabled and enabling (522) the adaptive event code in response to a system event in which the preexisting event code that corresponds to the enabled adaptive event code is executed (526). The method can further include the step of ignoring (518) the adaptive event codes during the running step when the adaptive event codes are disabled.

Method and system for employing adaptive event codes

The invention concerns a method (500) for employing adaptive event codes. The method includes the steps of generating (512) at least one adaptive event code in which the adaptive event code corresponds to a preexisting event code, storing (514) the adaptive event code in at least one table (154, 156), running (516) the table in which the adaptive event codes are at least initially disabled and enabling (522) the adaptive event code in response to a system event in which the preexisting event code that corresponds to the enabled adaptive event code is executed (526). The method can further include the step of ignoring (518) the adaptive event codes during the running step when the adaptive event codes are disabled.

Method and system for employing adaptive event codes

The invention concerns a method (500) for employing adaptive event codes. The method includes the steps of generating (512) at least one adaptive event code in which the adaptive event code corresponds to a preexisting event code, storing (514) the adaptive event code in at least one table (154, 156), running (516) the table in which the adaptive event codes are at least initially disabled and enabling (522) the adaptive event code in response to a system event in which the preexisting event code that corresponds to the enabled adaptive event code is executed (526). The method can further include the step of ignoring (518) the adaptive event codes during the running step when the adaptive event codes are disabled.

Method and system for exchanging data

The invention concerns a method (300) and system for exchanging data in a multi-core architecture having at least one shared memory. The method can include the steps of requesting (312) data in a first format from a predetermined range of addresses in the shared memory in which the data is shared between different processors, storing (316) the requested data in a cache to be retrieved by a format converter and identifying (320) to the format converter a data type for the data. The method can also include the step of, with the format converter, translating (322) based on predetermined rules the data to a second format that is native to a processor that will process the data.

Cellular modem processing

A cellular mobile station (101) including a modem processor (127) and memory (129). The memory includes instructions for the modem processor to perform layer 1 processor operations, layer 2 processor operations, and layer 3 processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol. In one example, the mobile station includes different levels of memory to provide different deterministic access times.

Programmable direct memory access channels

A storage location of a device that can be configured to act as a master in a particular security mode, such as a Direct Memory Access (DMA) having one or more channels, can be programmed to indicate a security indicator to be provided when configured to operate as a master device.