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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 14419. Отображено 100.
05-03-2018 дата публикации

Стенд для измерения работы выхода электрона с поверхности металлических тел

Номер: RU0000177659U1
Автор: Александр Гургенович Сукиязов, Борис Игоревич Митрин, Владимир Борисович Зеленцов, Сергей Михайлович Айзикович
Принадлежит: федеральное государственное бюджетное образовательное учреждение высшего образования "Донской государственный технический университет" (ДГТУ)

Полезная модель относится к измерительной технике и может быть использована как для контроля технологического процесса поверхностной отделочно-упрочняющей обработки, а также при проведении лабораторных работ в учебном процессе. Сущность полезной модели заключается в том, что стенд измерения работы выхода электрона с поверхности металлических тел содержит магнитный вибратор выполнен виде стального П-образного упругого элемента жестко связанного с нижней параллельной стороной на основании из немагнитного материала, внутри упомянутого упругого элемента со стороны основания укреплен один полюс электромагнита возбуждения с обмоткой соединенной с генератором прямоугольных импульсов и сердечником параллельным перекладине П-образного упругого элемента, а его другой полюс образует зазор с верхней параллельной стороной упругого элемента, кроме того, снаружи верхней параллельной стороны упругого элемента в ее продолжении укреплен один конец легкой пластиковой балки с ребрами жесткости, на другом конце которого укреплен измерительный зонд, при этом частота генератора прямоугольных импульсов кратна собственной частоте колебания пластиковой балки с измерительным зондом. Технический результат - упрощение процесса изготовления и упрощение конструкции устройства. 3 ил. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 177 659 U1 (51) МПК H01L 21/00 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК H01L 21/00 (2006.01) (21)(22) Заявка: 2017139300, 13.11.2017 (24) Дата начала отсчета срока действия патента: Дата регистрации: 05.03.2018 (45) Опубликовано: 05.03.2018 Бюл. № 7 1 7 7 6 5 9 R U (56) Список документов, цитированных в отчете о поиске: SU 1494732 A1, 07.01.1991. SU 731337 A1, 30.04.1980. RU 89709 U1, 10.12.2009. JPH 05133979 A, 28.05.1993. (54) СТЕНД ДЛЯ ИЗМЕРЕНИЯ РАБОТЫ ВЫХОДА ЭЛЕКТРОНА С ПОВЕРХНОСТИ МЕТАЛЛИЧЕСКИХ ТЕЛ (57) Реферат: Полезная модель относится к измерительной генератором прямоугольных импульсов и технике и ...

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Номер записи: 1
26-01-2012 дата публикации

Real-time monitoring of retaining ring thickness and lifetime

Номер: US20120021671A1
Автор: Adam H. Zhong, Eric S. Rondum, Garlen C. Leung, Gopalakrishna B. Prabhu, Gregory E. Menk, Peter McReynolds, Thomas H. Osterheld
Принадлежит: Applied Materials Inc

A method and apparatus for monitoring the condition of a surface of a retaining ring disposed on a carrier head in a polishing module is described. In one embodiment, a method for monitoring at least one surface of a retaining ring coupled to a carrier head is provided. The method includes moving the carrier head adjacent a sensor device disposed in a polishing module, transmitting energy from the sensor device toward the retaining ring, receiving energy reflected from the retaining ring, and determining a condition of the retaining ring based on the received energy.

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Номер записи: 2
08-03-2012 дата публикации

Substrate processing method and system

Номер: US20120055401A1
Автор: Shigeki Tozawa
Принадлежит: Tokyo Electron Ltd

A substrate processing method includes a first step of subjecting a target substrate to a gas process within an atmosphere containing a fluorine-containing process gas, thereby forming a fluorine-containing reaction product on a surface of the target substrate. The method further includes a second step of subjecting the target substrate treated by the gas process to a heating process and a gas process within an atmosphere containing a reactive gas that reacts with fluorine.

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Номер записи: 3
29-03-2012 дата публикации

Methods for discretized processing and process sequence integration of regions of a substrate

Номер: US20120074096A1
Автор: Alexander Gorer, David E. Lazovsky, Thomas R. Boussie, Tony P. Chiang
Принадлежит: Individual

The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.

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Номер записи: 4
29-03-2012 дата публикации

Electrolytic gold or gold palladium surface finish application in coreless substrate processing

Номер: US20120077054A1
Автор: Charavanakumara Gurumurthy, Tao Wu
Принадлежит: Intel Corp

Electronic assemblies including coreless substrates having a surface finish, and their manufacture, are described. One method includes electrolytically plating a first copper layer on a metal core in an opening in a patterned photoresist layer. A gold layer is electrolytically plated on the first copper layer in the opening. An electrolytically plated palladium layer is formed on the gold layer. A second copper layer is electrolytically plated on the palladium layer. After the electrolytically plating the second copper layer, the metal core and the first copper layer are removed, wherein a coreless substrate remains. Other embodiments are described and claimed.

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Номер записи: 5
12-04-2012 дата публикации

Rolling bearing assembly with rotation sensing means, electric machine provided with such an assembly and fork lift truck comprising such an electric machine

Номер: US20120086313A1
Автор: Francois Niarfeix, Gertjan Van Amerongen
Принадлежит: SKF AB

This rolling bearing assembly ( 2 ) comprises a rolling bearing ( 4 ) with an inner ring ( 8 ), an outer ring ( 6 ) and several rolling bodies ( 10 ) between the inner and outer rings, at least one sensor ( 30 ) adapted to detect a rotation parameter of a first ring ( 8 ) with respect to a second ring ( 6 ) of the rolling bearing and a support member ( 40 ) holding the sensor ( 30 ) in position with respect to the rolling bearing ( 4 ). The support member ( 40 ) holds the sensor ( 30 ) in a position such that at least one connecting pin ( 34, 36, 38 ) of the sensor ( 30 ) extends in a volume ( 46 ) defined by the support member ( 40 ) and adapted to accommodate an electrical connector ( 100 ).

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Номер записи: 6
26-04-2012 дата публикации

Semiconductor device with reduced junction leakage and an associated method of forming such a semiconductor device

Номер: US20120098042A1
Автор: Ahmet S. Ozcan, Bin Yang, Christian Lavoie, Ming Cai, Zhen Zhang
Принадлежит: Globalfoundries Inc, International Business Machines Corp

Disclosed is a semiconductor device having a p-n junction with reduced junction leakage in the presence of metal silicide defects that extend to the junction and a method of forming the device. Specifically, a semiconductor layer having a p-n junction is formed. A metal silicide layer is formed on the semiconductor layer and a dopant is implanted into the metal silicide layer. An anneal process is performed causing the dopant to migrate toward the metal silicide-semiconductor layer interface such that the peak concentration of the dopant will be within a portion of the metal silicide layer bordering the metal silicide-semiconductor layer interface and encompassing the defects. As a result, the silicide to silicon contact is effectively engineered to increase the Schottky barrier height at the defect, which in turn drastically reduces any leakage that would otherwise occur, when the p-n junction is in reverse polarity.

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Номер записи: 7
03-05-2012 дата публикации

Methods Of Forming Doped Regions In Semiconductor Substrates

Номер: US20120108042A1
Автор: Allen Mcteer, Jennifer Lequn Liu, SHU QIN, Yongjun Jeff Hu
Принадлежит: Micron Technology Inc

Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant.

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Номер записи: 8
14-06-2012 дата публикации

Organic light emitting display device and manufacturing method for the same

Номер: US20120146032A1
Автор: Chun-Gi You, Joon-hoo Choi, June-Woo Lee
Принадлежит: Samsung Mobile Display Co Ltd

An organic light emitting display device includes a substrate, a thin film transistor formed on the substrate and including an active layer, a gate electrode including a gate lower electrode and a gate upper electrode, a source electrode, and a drain electrode, an organic light emitting device electrically connected to the thin film transistor, wherein a pixel electrode formed of the same material as at least a part of the gate electrode in the same layer, an intermediate layer including a light emitting layer, and an opposed electrode arranged to face the pixel electrode are sequentially deposited.

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Номер записи: 9
05-07-2012 дата публикации

Substrate bonding method and semiconductor device

Номер: US20120168954A1
Автор: Toshihiro Seko
Принадлежит: Stanley Electric Co Ltd

A first Sn absorption layer is formed on a principal surface of a first substrate, the first Sn absorption layer being made of metal absorbing Sn from AuSn alloy and lowering a relative proportion of Sn in the AuSn alloy. A second Sn absorption layer is formed on a principal surface of a second substrate, the second Sn absorption layer being made of metal absorbing Sn from AuSn alloy and lowering a relative proportion of Sn in the AuSn alloy. A solder layer made of AuSn alloy is formed at least on one Sn absorption layer of the first and second Sn absorption layers. The first and second substrates are bonded together by melting the solder layer in a state that the first and second substrates are in contact with each other, with the principal surfaces of the first and second substrates facing each other.

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Номер записи: 10
19-07-2012 дата публикации

Method for mems device fabrication and device formed

Номер: US20120181638A1
Автор: Joseph Damian Gordon Lacey, Mickael Renault, Thomas L. Maguire, Vikram Joshi
Принадлежит: Cavendish Kinetics Inc

The present invention generally relates to methods for producing MEMS or NEMS devices and the devices themselves. A thin layer of a material having a lower recombination coefficient as compared to the cantilever structure may be deposited over the cantilever structure, the RF electrode and the pull-off electrode. The thin layer permits the etching gas introduced to the cavity to decrease the overall etchant recombination rate within the cavity and thus, increase the etching rate of the sacrificial material within the cavity. The etchant itself may be introduced through an opening in the encapsulating layer that is linearly aligned with the anchor portion of the cantilever structure so that the topmost layer of sacrificial material is etched first. Thereafter, sealing material may seal the cavity and extend into the cavity all the way to the anchor portion to provide additional strength to the anchor portion.

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Номер записи: 11
19-07-2012 дата публикации

Tool performance by linking spectroscopic information with tool operational parameters and material measurement information

Номер: US20120185813A1
Автор: Kenji Sugishima, Sanjeev Kaushal, Sukesh Janubhai Patel
Принадлежит: Tokyo Electron Ltd

System(s) and method(s) are provided for adjustment and analysis of performance of a tool through integration of tool operational data and spectroscopic data related to the tool. Such integration results in consolidated data that enable, in part, learning at least one relationship amongst selected portions of the consolidated data. Learning is performed autonomously without human intervention. Adjustment of performance of the tool relies at least in part on a learned relationship and includes generation of process recipe parameter(s) that can adjust a manufacturing process in order to produce a satisfactory tool performance in response to implementation of the manufacturing process. A process recipe parameter can be generated by solving an inverse problem based on the learned relationship. Analysis of performance of the tool can include assessment of synthetic performance scenarios, identification of spectroscopic condition(s) that affect performance, and extraction of endpoints based at least on time dependence spectroscopic data.

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Номер записи: 12
26-07-2012 дата публикации

Hybrid Silicon Wafer

Номер: US20120187409A1
Автор: Hiroshi Takamura, Ryo Suzuki
Принадлежит: JX Nippon Mining and Metals Corp

A hybrid silicon wafer which is a silicon wafer having a structure wherein monocrystalline silicon is embedded in polycrystalline silicon that is prepared by the unidirectional solidification/melting method. The longitudinal plane of crystal grains of the polycrystalline portion prepared by the unidirectional solidification/melting method is used as the wafer plane, and the monocrystalline silicon is embedded so that the longitudinal direction of the crystal grains of the polycrystalline portion forms an angle of 120° to 150° relative to the cleaved surface of the monocrystalline silicon. Thus provided is a hybrid silicon wafer comprising the functions of both a polycrystalline silicon wafer and a monocrystalline wafer.

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Номер записи: 13
02-08-2012 дата публикации

Drive Current Increase in Field Effect Transistors by Asymmetric Concentration Profile of Alloy Species of a Channel Semiconductor Alloy

Номер: US20120193708A1
Автор: Jan Hoentschel, Stefan Flachowsky, Steven Langdon, Thilo Scheiper
Принадлежит: Globalfoundries Inc

When forming sophisticated transistors, the channel region may be provided such that the gradient of the band gap energy of the channel material may result in superior charge carrier velocity. For example, a gradient in concentration of germanium, carbon and the like may be implemented along the channel length direction, thereby obtaining higher transistor performance.

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Номер записи: 14
02-08-2012 дата публикации

Wafer dicing press and method and semiconductor wafer dicing system including the same

Номер: US20120196426A1
Автор: Won-Chul Lim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

In a wafer dicing press for reducing time and cost for wafer dicing and for evenly applying a dicing pressure to a whole wafer, a wafer dicing press includes a support unit supporting a first side of a wafer; and a pressurization device applying a pressure, by dispersing the pressure, to a second side of the wafer so that a laser-scribed layer of the wafer operates as a division starting point. Accordingly, the wafer dicing press reduces laser radiation and pressure-application times for dividing a wafer into semiconductor devices. This increased efficiency is achieved without increasing the likelihood of damaging the wafer.

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Номер записи: 15
04-10-2012 дата публикации

Semiconductor device and method for forming the same

Номер: US20120252186A1
Автор: Young Man Cho
Принадлежит: Hynix Semiconductor Inc

A semiconductor device includes a semiconductor substrate including an active area defined by an device isolation region, a buried gate formed on both side walls of a trench formed in the semiconductor substrate, and a storage node contact which is buried between the buried gates, and is connected to the active region of a middle portion of the trench and the device isolation region.

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Номер записи: 16
15-11-2012 дата публикации

Method for fabricating semiconductor power device

Номер: US20120289037A1
Автор: Shou-Yi Hsu, Yi-Lin Sun, Yung-Fa Lin
Принадлежит: Anpec Electronics Corp

A method for fabricating a semiconductor power device includes the following steps. First, a substrate having at least a semiconductor layer and a pad layer thereon is provided. At least a trench is etched into the pad layer and the semiconductor layer. Then, a dopant source layer is deposited in the trench and on the pad layer followed by thermally driving in dopants of the dopant source layer into the semiconductor layer. A polishing process is performed to remove the dopant source layer from a surface of the pad layer and a thermal oxidation process is performed to eliminate micro-scratches formed during the polishing process. Finally, the pad layer is removed to expose the semiconductor layer.

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Номер записи: 17
24-01-2013 дата публикации

Methods for post dopant implant purge treatment

Номер: US20130023112A1
Автор: Kartik Santhanam
Принадлежит: Applied Materials Inc

Methods for processing substrates are provided herein. In some embodiments, a method of processing a substrate may include implanting a substrate with a dopant in a first vacuum chamber; transferring the substrate to a second vacuum chamber at a first pressure below atmospheric; providing an inert gas to the second vacuum chamber to raise the pressure to a second pressure; pumping down the second vacuum chamber to a third pressure below the second pressure; and providing the inert gas to the second vacuum chamber to raise the pressure to a fourth pressure above the third pressure.

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Номер записи: 18
31-01-2013 дата публикации

Method of fabricating semiconductor device including calibrating process conditions and configurations by monitoring processes

Номер: US20130029434A1
Автор: Jang-Sun Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of fabricating a semiconductor device includes performing a first period of operation and a second period of operation at first equipment and second equipment. The first period of operation includes performing a first patterning process at each of the first equipment and the second equipment, generating first inspection data of the first equipment and first inspection data of the second equipment, generating first differential data of the second equipment including differentials of the first inspection data of the first equipment and the first inspection data of the second equipment, and calibrating a configuration of the second equipment with reference to the first differential data of the second equipment.

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Номер записи: 19
31-01-2013 дата публикации

Plasma etching method, control program and computer storage medium

Номер: US20130029493A1
Автор: Masahiro Ogasawara, Sungtae Lee
Принадлежит: Individual

A plasma etching method, for plasma-etching a target substrate including at least a film to be etched, an organic film to become a mask of the to-be-etched film, and a Si-containing film which are stacked in order from bottom, includes the first organic film etching step, the treatment step and the second organic film etching step when the organic film is etched to form a mask pattern of the to-be-etched film. In the first organic film etching step, a portion of the organic film is etched. In the treatment step, the Si-containing film and the organic film are exposed to plasma of a rare gas after the first organic film etching step. In the second organic film etching step, the remaining portion of the organic film is etched after the treatment step.

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Номер записи: 20
14-03-2013 дата публикации

Recessed Access Device for a Memory

Номер: US20130062678A1
Автор: Jigish D. Trivedi, Kevin G. Duesman, Kurt D. Beigel
Принадлежит: Micron Technology Inc

Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.

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Номер записи: 21
25-04-2013 дата публикации

Architectural construct having a plurality of implementations

Номер: US20130101808A1
Автор: Roy Edward McAlister
Принадлежит: McAlister Technologies LLC

An architectural construct is a synthetic material that includes a matrix characterization of different crystals. An architectural construct can be configured as a solid mass or as parallel layers that can be on a nano-, micro-, and macro-scale. Its configuration can determine its behavior and functionality under a variety of conditions. Implementations of an architectural construct can include its use as a substrate, sacrificial construct, carrier, filter, sensor, additive, and catalyst for other molecules, compounds, and substances, or may also include a means to store energy and generate power.

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Номер записи: 22
02-05-2013 дата публикации

TEMPERATURE-COMPENSATED MICROMECHANICAL RESONATOR

Номер: US20130106246A1
Автор: Peczalski Adam, Raieszadeh Mina, Thakar Vikram Atul, WU Zhengzheng
Принадлежит: THE REGENTS OF THE UNIVERSITY OF MICHIGAN

A micromechanical resonator is passively compensated to reduce the value of the temperature coefficient of frequency (TCF). The resonator may be part of a MEMS device and includes temperature compensating material encapsulated within the resonator between a resonator body and a capping layer. The compensating material has a TCE that is opposite to that of the resonator body material. One material has a positive TCE and the other material has a negative TCE. The compensating material can be located at or near high strain regions of the resonator to help minimize the amount of compensating material necessary to bring the TCF of the resonator close to zero. The compensating material can also be located in trenches formed only partially through the resonator body, thus allowing the resonator to be released from a substrate using wet release methods without etching away any of the compensating material. 1. A micro-electromechanical (MEMS) device , comprising:a resonator body formed from a material that has a temperature coefficient of elasticity (TCE) that is one of positive or negative;a capping layer overlying and coupled with the resonator body; andone or more passive temperature compensating elements, each compensating element being encapsulated in the device between the resonator body material and the capping layer and being formed from a material having a TCE that is the other one of positive or negative.2. A MEMS device as defined in claim 1 , further comprising:a transducer coupled with the resonator body.3. A MEMS device as defined in claim 2 , wherein the transducer comprises the capping layer.4. A MEMS device as defined in claim 1 , wherein each temperature compensating element is in contact with the capping layer on one side and in contact with the resonator body material on the other sides.5. A MEMS device as defined in claim 1 , wherein the resonator body material is single-crystal silicon and at least one of the temperature compensating elements comprises ...

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Номер записи: 23
09-05-2013 дата публикации

SEMICONDUCTOR COMPONENT

Номер: US20130113087A1
Автор: HILLE Frank, Pfirsch Frank, Ruething Holger, Schulze Hans-Joachim, Willmeroth Armin
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A semiconductor component is disclosed. One embodiment provides a semiconductor body having a cell region with at least one zone of a first conduction type and at least one zone of a second conduction type in a rear side. A drift zone of the first conduction type in the cell region is provided. The drift zone contains at least one region through which charge carriers flow in an operating mode of the semiconductor component in one polarity and charge carriers do not flow in an operating mode of the semiconductor component in an opposite polarity. 1. A semiconductor component comprising:a semiconductor body having a cell region, with at least one zone of a first conduction type and at least one zone of a second conduction type in a rear side and contains a drift zone of the first conduction type in the cell region;wherein the rear side contains both at least one region having zones of the first and of the second conduction type and at least one further region of the second conduction type which has, as partial area, at least one circular area having a diameter of at least four times a thickness of the drift zone and which contains no zones of the first conduction type.2. The semiconductor component of claim 1 , comprising wherein a doping concentration in the at least one zone of the first conduction type is increased in comparison with a doping concentration of the drift zone.3. The semiconductor component of claim 1 , comprising wherein in the at least one zone of the first conduction type claim 1 , a doping concentration is achieved by using a doping dose of between 1015 l/cm2 and 1016 l/cm2.4. The semiconductor component of claim 1 , comprising wherein a laterally delimited further zone of the second conduction type is arranged directly in front of the at least one zone of the first conduction type.5. The semiconductor component of claim 1 , comprising wherein a field punch-through at the at least one further zone makes it possible to prevent a chopping of a ...

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Номер записи: 24
23-05-2013 дата публикации

Method for fabricating vertical channel type nonvolatile memory device

Номер: US20130130454A1
Автор: Ki-hong Lee, Kwon Hong, Moon-Sig Joo, Sun-Hwan Hwang
Принадлежит: SK hynix Inc

A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers alternately over a substrate; etching the interlayer insulating layers and the gate electrode conductive layers to form a channel trench exposing the substrate; forming an undoped first channel layer over the resulting structure including the channel trench; doping the first channel layer with impurities through a plasma doping process; and filling the channel trench with a second channel layer.

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Номер записи: 25
06-06-2013 дата публикации

Contactor and semiconductor test apparatus comprising the same

Номер: US20130141129A1
Автор: Tae-Youn LIM
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Provided is a test contactor for testing a semiconductor device which includes a cylinder, a piston which is configured to reciprocate between a first position and a second position according to a change in pressure in the cylinder, and a pressing part which is configured to change its location according to the reciprocating motion of the piston. The pressing part is configured to be in contact with the semiconductor device when the piston is located at the first position, and the pressing part is configured not to be in contact with the semiconductor device when the piston is located at the second position.

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Номер записи: 26
06-06-2013 дата публикации

HEAT TREATMENT METHOD OF SEMICONDUCTOR WAFERS, MANUFACTURING METHOD OF SOLAR BATTERY, AND HEAT TREATMENT DEVICE

Номер: US20130143348A1
Автор: Nishimura Kunihiko, OTA Narihito
Принадлежит:

A heat treatment method of the present invention includes mounting a plurality of semiconductor wafers upright on a treatment boat in parallel to each other, inserting the treatment boat in a space above an injector located in a tube to be oriented to plane surfaces of the semiconductor wafers in parallel to an extending direction of the tube, and heating the tube while continuously supplying source gas into the tube through openings of the injector. 1. A heat treatment method of semiconductor wafers , whereinthe method uses a heat-resistant tube extending in a horizontal direction as a process chamber;a gas pipe is installed in an inner lower portion of the tube; anda treatment boat is placed in the tube, wherein the treatment boat includes a pair of first shield plates that shields entire side surfaces of a plurality of semiconductor wafers mounted on the treatment boat in parallel to each other; the heat treatment method comprising:heating the tube while supplying source gas into the tube, thereby performing heat treatment to the semiconductor wafers mounted on the treatment boat;mounting the semiconductor wafers upright in parallel to each other on the treatment boat;inserting the treatment boat into a space above the gas pipe in the tube to be oriented to plane surfaces of the semiconductor wafers in parallel to an extending direction of the tube; andcontinuously supplying the source gas into the tube from an opening of the gas pipe and heating the tube.2. The heat treatment method of semiconductor wafers according to claim 1 , wherein the source gas is continuously flowed into the treatment boat from below the treatment boat and is continuously flowed to an upper side of the treatment boat.3. The heat treatment method of semiconductor wafers according to claim 2 , whereina discharge pipe is placed inside of the tube at an upper portion thereof, andthe source gas flowed to the upper side of the treatment boat is continuously discharged from an opening of the ...

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Номер записи: 27
20-06-2013 дата публикации

Apparatus and Method for Thermal Interfacing

Номер: US20130154748A1
Автор: Beale Gary, Mcerlean Eamon
Принадлежит: EMBLATION LIMITED

An apparatus () for use as an amplifier has a transistor () for providing signal amplification, a heat pipe or circulated fluid heat sink () and a thermal interface device () for providing mechanical and thermal connection between the transistor () and the heat sink (). In use, to facilitate efficient transfer of heat/thermal energy from the transistor () to the heat sink (), the plate () is provided between the heat sink () and the transistor (). The plate () connects the heat sink () to the transistor () and provides a thermal conduit therebetween. 1. An apparatus for use as an amplifier comprising:a radio frequency or microwave transistor for providing signal amplification;at least one circuit board to provide input signals to and/or receive signals from the transistor; anda thermal interface device configured to facilitate mechanical and thermal connection between the transistor and a heat pipe heat sink or circulating fluid heat sink.2. The apparatus according to claim 1 , wherein the heat sink comprises a microprocessor heat sink.3. The apparatus of claim 1 , wherein the transistor comprises a power transistor that has an output power in the range 1 W to 10 claim 1 ,000 W claim 1 , optionally in the range 1 W to 1000 W claim 1 , further optionally in the range 20 W to 200 W.4. The apparatus of claim 1 , wherein the transistor has an output power per unit surface area in the range 1 W/cmto 100 W/cm claim 1 , optionally in the range 80 W/cmto 100 W/cm.5. The apparatus of claim 1 , wherein at least one of:the interface device is configured to be directly coupled to the transistor;the interface device is directly coupled to the transistor to provide two thermal junctions between the transistor and the heat sink.6. (canceled)7. The apparatus of claim 1 , wherein the interface device is configured to be indirectly coupled to the transistor.8. The apparatus of claim 1 , further comprising a septum between the transistor and the interface device.9. The apparatus of ...

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Номер записи: 28
20-06-2013 дата публикации

Electrostatic Discharge Protection Device and Method

Номер: US20130157430A1
Автор: Feng Yao-Wu, LEE Jian-Hsing, Sheu Ming-Song
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

Embodiments of the invention relate to an electrostatic discharge (ESD) device and method for forming an ESD device. An embodiment is an ESD protection device comprising a p well disposed in a substrate, an n well disposed in the substrate, a high voltage n well (HVNW) disposed between the p well and the n well in the substrate, a source n+ region disposed in the p well, and a plurality of drain n+ regions disposed in the n well. 1. A method of forming a semiconductor device , the method comprising:forming a p well in a semiconductor substrate;forming a high voltage n well in the semiconductor substrate;forming a deep n well in the high voltage n well; andforming n+ regions in the deep n well.2. The method of claim 1 , wherein forming n+ regions in the deep n well comprises:forming a resist layer over the semiconductor substrate such that the resist layer has a plurality of openings over the deep n well; andimplanting n type impurities into the deep n well.3. The method of claim 1 , further comprising forming a contact electrically coupled to each n+ region.4. The method of claim 3 , wherein the forming the contact to each n+ region comprises:forming a dielectric layer over the substrate;patterning a hardmask over the dielectric layer such that an area of the dielectric layer above each n+ region is exposed;etching the dielectric layer; anddepositing conductive material on the substrate.5. The method of claim 1 , further comprising:forming a p+ region in the p well; andforming a gate structure on the semiconductor substrate.6. A method of forming a semiconductor device claim 1 , the method comprising:forming a drain region, the drain region having dopants of a first conductivity type;forming a plurality of highly doped regions in the drain region, the plurality of highly doped regions having a higher concentration of dopants of the first conductivity type than the drain region; andforming a plurality of contacts, wherein at least two of the plurality of contacts are ...

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Номер записи: 29
27-06-2013 дата публикации

HEAT-TREATMENT FURNACE

Номер: US20130161313A1
Автор: MURAKAMI Takashi, Otsuka Hiroyuki, Watabe Takenori
Принадлежит: SHIN-ETSU CHEMICAL CO., LTD.

The disclosed heat-treatment furnace, used in a semiconductor-substrate heat-treatment step, is characterized by the provision of a cylindrical core, both ends of which have openings sized so as to allow insertion and removal of semiconductor substrates. This reduces standby time between batches during consecutive semiconductor heat treatment, thereby improving productivity. Furthermore, the use of a simple cylindrical shape for the structure of the core reduces the frequency at which gas-introduction pipe sections fail, thereby decreasing the running cost of the heat-treatment process. 1. A heat-treatment furnace for use in the heat treatment of semiconductor substrates , comprising a cylindrical core tube which is provided at opposite ends with openings having a sufficient size to allow semiconductor substrates to be moved into and out of the core tube.2. The heat-treatment furnace of claim 1 , further comprising lids each of which is detachably mounted to the core tube to block the opening to substantially seal the core tube.3. The heat-treatment furnace of claim 1 , further comprising thin gas inlet conduits penetrating through the lids for introducing gas into the core tube.4. The heat-treatment furnace of claim 1 , further comprising thin gas inlet conduits disposed near opposite ends of the core tube for introducing gas into the core tube.5. The heat-treatment furnace of claim 1 , further comprising a thin gas inlet conduit disposed near the longitudinal center of the core tube for introducing gas into the core tube.6. The heat-treatment furnace of claim 1 , wherein the opening in the core tube has an inner diameter which is at least 95% of the inner diameter of the core tube at the center.7. The heat-treatment furnace of claim 1 , further comprising at least one boat station disposed outside the core tube and in proximity to the opening in the core tube claim 1 , the boat station carrying a boat having semiconductor substrates rested thereon on standby.8. ...

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Номер записи: 30
11-07-2013 дата публикации

Method of Impurity Introduction and Controlled Surface Removal

Номер: US20130178051A1
Автор: Tzu-Yin Chiu
Принадлежит: Individual

A method of introducing dopants into a semiconductor wafer includes implanting the dopants into a region below a surface of the semiconductor wafer using an ion beam to form a first implanted layer. The dopants when activated causing a conductivity of the implanted layer to be either of N-type or P-type. The first implanted layer is characterized by a peak dopant concentration at a first depth below the surface of the semiconductor wafer. The method also includes removing a layer from the semiconductor wafer surface, wherein said layer includes a portion of said dopants.

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Номер записи: 31
25-07-2013 дата публикации

Light-emitting dies incorporating wavelength-conversion materials and related methods

Номер: US20130187174A1
Автор: Michael A. Tischler
Принадлежит: Individual

In accordance with certain embodiments, semiconductor dies are embedded within polymeric binder to form, e.g., freestanding white light-emitting dies and/or composite wafers containing multiple light-emitting dies embedded in a single volume of binder.

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Номер записи: 32
25-07-2013 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20130189832A1
Автор: HORIE Mitsuo, MASADA Atsuya
Принадлежит: Panasonic Corporation

A semiconductor device including a semiconductor substrate having a first conductive type layer; a first diffusion region which has the first conductive type and is formed in the first conductive type layer; a second diffusion region which has a second conductive type and an area larger than an area of the first diffusion region and overlaps the first diffusion region; and a PN junction formed at an interface between the first and the second diffusion regions. The second diffusion region includes a ring shaped structure or a guard ring includes an inverted region which has the second conductive type. According to such a configuration, it is possible to provide a semiconductor device having the required Zener characteristics with good controllability. 17-. (canceled)8. A manufacturing method of a semiconductor device comprising;preparing a semiconductor substrate having a first conductive type layer;doping a first conductive type impurity into the first conductive type layer so as to &Inn a first diffusion region; anddoping a second type impurity into the first conductive type layer so as to form a second diffusion region which has an area larger than an area of the first region and overlaps the first diffusion region,wherein a part of the first diffusion region is inverted from the first conductive type to the second conductive type by doping the second type impurity so as to form a PN junction.9. The manufacturing method of the semiconductor device according to claim 8 , wherein the first conductive type layer is formed by epitaxial growth.10. The manufacturing method of the semiconductor device according to claim 9 , comprising:forming an insulator layer prior to doping the first conductive type impurity, the insulator layer including an opening which corresponds to the second diffusion region.11. The manufacturing method of the semiconductor device according to claim 10 , wherein the first conductive impurity is doped by using a resist mask claim 10 , the resist ...

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Номер записи: 33
01-08-2013 дата публикации

DEVICE FOR PROTECTING AN INTEGRATED CIRCUIT AGAINST BACK SIDE ATTACKS

Номер: US20130193437A1
Автор: Larosa Francesco, Lisart Mathieu, Sarafianos Alexandre, Soude Thierry
Принадлежит: STMICROELECTRONICS (ROUSSET) SAS

An integrated circuit including: a semiconductor substrate of a first conductivity type having at least one well of a second conductivity type laterally delimited, on two opposite walls, by regions of the first conductivity type, defined at its surface; at least one region of the second conductivity type which extends in the semiconductor substrate under the well; and a system for detecting a variation of the substrate resistance between each association of two adjacent regions of the first conductivity type. 1. An integrated circuit comprising:a semiconductor substrate of a first conductivity type having a surface;a first well of a second conductivity type formed in the substrate and having first and second sides;first and second regions of the first conductivity type defined at the surface of the substrate and respectively delimiting the first and second sides of the first well;a region of the second conductivity type which extends in the semiconductor substrate under said first well; anda detector configured to detect a variation of a resistance of the substrate between the first and second regions of the first conductivity type.2. The circuit of claim 1 , wherein the detector comprises:a voltage generator circuit configured to generate a first potential difference between said first and second regions and cause a current to flow between said first and second regions; anda comparison circuit configured to compare the current between said first and second regions and a threshold.3. The circuit of claim 2 , comprising:a second well of the second conductivity type formed in the substrate and having first and second sides;a third region of the first conductivity type, the second and third regions respectively delimiting the first and second sides of the second well, and the generator being configured to apply a second potential difference between the second region and the third region.4. The circuit of claim 3 , wherein the first potential difference and the second ...

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Номер записи: 34
15-08-2013 дата публикации

Humidity detection sensor and a method for manufacturing the same

Номер: US20130207673A1
Автор: Atsushi Tondokoro, Satoshi Waga, Shinya Yokoyama, Sumihito Morita, Takashi Sato
Принадлежит: Alps Electric Co Ltd

A humidity detection sensor includes a lower electrode provided on a board, an upper electrode provided so as to face the lower electrode, a humidity sensing film which is formed at least between the lower electrode and the upper electrode and whose dielectric constant changes in response to humidity, and a protective film provided so as to cover the upper electrode. Each of the upper electrode and the protective film has an opening through which the humidity sensing film is partially exposed to the outside. In the opening, the humidity sensing film is provided so as to reach at least a position higher than the position of the lower surface of the protective film.

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Номер записи: 35
19-09-2013 дата публикации

DIODES WITH A DOG BONE OR CAP-SHAPED JUNCTION PROFILE TO ENHANCE ESD PERFORMANCE, AND OTHER SUBSTRUCTURES, INTEGRATED CIRCUITS AND PROCESSES OF MANUFACTURE AND TESTING

Номер: US20130244411A1
Автор: CHUANG Ming-Yeh
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

An integrated circuit structure includes a semiconductor doped area (NWell) having a first conductivity type, and a layer (PSD) that overlies a portion of said doped area (NWell) and has a doping of an opposite second type of conductivity that is opposite from the first conductivity type of said doped area (NWell), and said layer (PSD) having a corner in cross-section, and the doping of said doped area (NWell) forming a junction beneath said layer (PSD) with the doping of said doped area (NWell) diluted in a vicinity below the corner of said layer (PSD). Other integrated circuits, substructures, devices, processes of manufacturing, and processes of testing are also disclosed. 1. A process of making an integrated circuit , comprising:forming a first-conductivity-type region in an opposite-type substrate; andproviding an approximately cap-shaped structure having such opposite-type overlying and at least partially laterally bounding said first-type region so that an impressed electric field where said structure overlies said first-type region is at least as great in magnitude as an impressed electric field where said structure laterally bounds said first-type region.2. The process of the providing of the approximately cap-shaped structure includes implanting a layer that overlies a portion of said first-type region and has a doping of an opposite second type of conductivity that is opposite from the first conductivity type of said first-type region.3. The process of wherein said implanted layer has a corner in cross-section claim 2 , and the doping of said first-type region forms a junction beneath said implanted layer and the doping of said first-type region is diluted in a vicinity near a periphery of said approximately cap-shaped structure.4. The process of further comprising forming an epitaxial region of such opposite-type prior to forming said first-type region claim 2 , the forming said first-type region leaving the epitaxial region approximately indented into ...

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Номер записи: 36
26-09-2013 дата публикации

Methods, structures and devices for increasing memory density

Номер: US20130248800A1
Автор: John K. Zahurak, Sanh D. Tang
Принадлежит: Micron Technology Inc

Non-volatile memory devices comprising a memory string including a plurality of vertically superimposed diodes. Each of the diodes may be arranged at different locations along a length of the electrode and may be spaced apart from adjacent diodes by a dielectric material. The electrode may electrically couple the diodes of the memory strings to one another and to another memory device, such as, a MOSFET device. Methods of forming the non-volatile memory devices as well as intermediate structures are also disclosed.

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Номер записи: 37
26-09-2013 дата публикации

Reducing Source/Drain Resistance of III-V Based Transistors

Номер: US20130248929A1
Автор: KO Chih-Hsin, Wann Clement Hsingjen
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

An integrated circuit structure includes a substrate; a channel layer over the substrate, wherein the channel layer is formed of a first III-V compound semiconductor material; a highly doped semiconductor layer over the channel layer; a gate dielectric penetrating through and contacting a sidewall of the highly doped semiconductor layer; and a gate electrode on a bottom portion of the gate dielectric. The gate dielectric includes a sidewall portion on a sidewall of the gate electrode. 1. A device comprising:a channel layer over a substrate, wherein the channel layer is formed of a first III-V compound semiconductor material comprising group III and group V elements;a top barrier over the channel layer, a bandgap of the top barrier greater than a bandgap of the channel layer;a doped semiconductor layer over the top barrier;a gate dielectric extending through the doped semiconductor layer; anda gate electrode on a bottom portion of the gate dielectric, wherein the gate dielectric comprises a sidewall portion on a sidewall of the gate electrode.2. The device of further comprising a bottom barrier over the substrate claim 1 , and wherein forming the channel layer comprises forming the channel layer over the bottom barrier.3. The device of claim 2 , wherein a bandgap of the bottom barrier is greater than a bandgap of the channel layer.4. The device of claim 1 , wherein the gate dielectric is in contact with a sidewall of the doped semiconductor layer.5. The device of claim 4 , wherein a bottom surface of a bottom portion of the gate dielectric is substantially even with a bottom surface of the doped semiconductor layer.6. The device of claim 1 , wherein the doped semiconductor layer is doped with an impurity having a concentration greater than about 1×10/cm.7. The device of claim 6 , wherein the doped semiconductor layer comprises a second III-V compound semiconductor material claim 6 , and wherein the impurity is selected from the group consisting essentially of Si ...

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Номер записи: 38
26-09-2013 дата публикации

Vapor deposition shadow mask system for backplane and display screen with any size and method thereof

Номер: US20130251907A1
Автор: Chongguang Pan
Принадлежит: Individual

The present invention discloses a vapor deposition shadow mask system for backplane and display screen of any size and a method thereof. The system includes at least one vacuum chamber, a substrate and a transmission device. The vacuum chambers accommodate ‘M’ set of shadow mask plates and deposition sources therein. The substrate includes ‘M’ number of elementary units, each of which being partitioned into ‘N’ number of regions. The transmission device is utilized to shift the substrate or the shadow mask plate along a path of the vacuum chamber such that the ‘M’ set of shadow mask plates are corresponded to the different regions of the ‘M’ number of elementary units in ‘N’ number of periods. The ‘M’ is a natural number greater than or equal to one, and the ‘N’ is a natural number greater than or equal to two.

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Номер записи: 39
26-09-2013 дата публикации

METHOD FOR FABRICATING SCHOTTKY DEVICE

Номер: US20130252408A1
Автор: Chang Chia-Hao, Hsu Shou-Yi, Lin Yung-Fa, Wu Meng-Wei
Принадлежит: ANPEC ELECTRONICS CORPORATION

A method for fabricating a Schottky device includes the following sequences. First, a substrate with a first conductivity type is provided and an epitaxial layer with the first conductivity type is grown on the substrate. Then, a patterned dielectric layer is formed on the epitaxial layer, and a metal silicide layer is formed on a surface of the epitaxial layer. A dopant source layer with a second conductivity type is formed on the metal silicide layer, followed by applying a thermal drive-in process to diffuse the dopants inside the dopant source layer into the epitaxial layer. Finally, a conductive layer is formed on the metal silicide layer. 1. A fabricating method of a Schottky device , comprising:providing a substrate having a first conductivity type;forming an epitaxial layer on the substrate, wherein the epitaxial layer has the first conductivity type;forming a patterned dielectric layer on the epitaxial layer;forming a guard ring of a second conductivity type in the epitaxial layer;forming a silicide layer on a surface of the epitaxial layer, wherein the silicide layer covers the guard ring;forming a dopant source layer on the silicide layer, wherein the dopant source layer has a plurality of dopants with the second conductivity type;performing a thermal drive-in process to diffuse the dopants from the dopant source layer into the epitaxial layer through the silicide layer, thereby forming a doped region of the second conductivity type; andforming a conductive layer on the silicide layer.2. The fabricating method of the Schottky device according to claim 1 , wherein the surface of the epitaxial layer comprises at least a lattice defect structure.3. The fabricating method of the Schottky device according to claim 2 , wherein the lattice defect structure comprises seam defects claim 2 , void defects claim 2 , or lattice dislocations.4. The fabricating method of the Schottky device according to claim 2 , wherein the doped region encompasses the lattice defect ...

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Номер записи: 40
03-10-2013 дата публикации

PHONONIC STRUCTURES AND RELATED DEVICES AND METHODS

Номер: US20130255738A1
Автор: Heath James R., Mitrovic Slobodan, Yu Jen-Kan
Принадлежит: California Institute of Technology

Phononic structures, devices related to phononic structures, and methods related to fabrication of the phononic structures are described. The phononic structure can include a sheet of material, where the sheet of material can include a plurality of regions. Adjacent regions in the sheet of material can have dissimilar phononic patterns. 1. A phononic structure , comprising:a sheet of a first material, the sheet comprising a plurality of regions, wherein adjacent regions have dissimilar phononic patterns.2. The phononic structure according to claim 1 , wherein adjacent regions have dissimilar phonon energy band structures.3. The phononic structure according to claim 1 , wherein each region has a length more than twice a phonon mean free path of the first material.4. The phononic structure according to claim 1 , wherein the plurality of regions comprises at least a first region and a second region adjacent the first region claim 1 , the first region comprising holes in the first material and the second region comprising the first material devoid of holes.5. The phononic structure according to claim 4 , wherein the holes are filled with a second material.6. The phononic structure according to claim 1 , wherein the plurality of regions comprises at least a first region and a second region adjacent the first region claim 1 , the first region comprising holes with a first value for a characteristic and the second region comprising holes with a second value for the same characteristic.7. The phononic structure according to claim 6 , wherein the characteristic is selected from the group consisting of hole size claim 6 , pitch between holes claim 6 , wall-to-wall distance between holes claim 6 , and hole shape.8. The phononic structure according to claim 6 , wherein the holes in one or both of the first and second regions are filled with a second material.9. The phononic structure according to claim 6 , wherein the holes in the first region are filled with a second material ...

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Номер записи: 41
17-10-2013 дата публикации

Semiconductor Device with Integrated Breakdown Protection

Номер: US20130270606A1
Автор: Hubert M. Bode, Patrice M. Parris, Richard J. De Souza, Weize Chen
Принадлежит: FREESCALE SEMICONDUCTOR INC

A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. The device isolating region and the body region are spaced from one another to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path.

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Номер записи: 42
24-10-2013 дата публикации

METHOD FOR FORMING A DOPANT PROFILE

Номер: US20130280898A1
Автор: Blendin Gabriele, Horzel Joerg, Lachowicz Agata, Schum Berthold
Принадлежит: SCHOTT SOLAR AG

A method is provided for forming a dopant profile based on a surface of a wafer-like semiconductor component with phosphorus as a dopant. The method includes the steps of applying a phosphorus dopant source onto the surface, forming a first dopant profile with the dopant source that is present on the surface, removing the dopant source, and forming a second dopant profile that has a greater depth in comparison to the first dopant profile. In order to form an optimized dopant profile, the dopant source is removed after forming the first dopant profile, and precipitates that are crystallized selectively on or in the surface from the precipitates SiPand SiPOare removed. 119-. (canceled)20. A method for forming a dopant profile proceeding from a surface of a plate-shaped or wafer-shaped silicon-based semiconductor device with phosphorus as a dopant , comprising:applying a phosphorus dopant source onto the surface;forming a first dopant profile with the phosphorus dopant source present on the surface;{'sub': x', 'y', 'x', 'y', 'z, 'removing the phosphorus dopant source and precipitates present on the surface, the precipitates being selected from the group consisting of SiP, SiPO, and combinations thereof; and'}forming a second dopant profile having greater depth in comparison to the first dopant profile.21. The method according to claim 20 , wherein claim 20 , after removal of the phosphorus dopant source and the precipitates present on the surface claim 20 , the method further comprises removing electrically inactive phosphorus and free phosphorus.22. The method according to claim 20 , wherein claim 20 , after forming the first dopant profile and removing the phosphorus dopant source claim 20 , the method further comprises applying an etch-resistant mask on the surface claim 20 , the mask having a geometry that corresponds to that of a metallizing to be applied on the surface.23. The method according to claim 20 , wherein the step of forming the first dopant profile ...

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Номер записи: 43
31-10-2013 дата публикации

SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20130285070A1
Автор: Kawai Jun, SUGIURA Kazuhiko, Tokura Norihito
Принадлежит:

In a manufacturing method of a silicon carbide semiconductor device, a semiconductor substrate made of single crystal silicon carbide is prepared. At a portion of the semiconductor substrate where a first electrode is to be formed, a metal thin film made of electrode material including an impurity is formed. After the metal thin film is formed, the first electrode including a metal reaction layer in which the impurity is introduced is formed by irradiating the metal thin film with a laser light. 1. A manufacturing method of a silicon carbide semiconductor device including a semiconductor substrate that has a main surface and a rear surface being an opposite surface of the main surface and is made of single crystal silicon carbide and a first electrode that forms an ohmic junction with the semiconductor substrate , comprising:preparing the semiconductor substrate;forming a metal thin film that is made of electrode material including an impurity, at a portion of the semiconductor substrate where the first electrode is to be formed; andforming the first electrode that includes a metal reaction layer in which the impurity is introduced, by irradiating the metal thin film with a laser light after forming the metal thin film, thereby concurrently diffusing a metal atom that forms the metal thin film and the impurity that is included in the metal thin film, and forming the metal reaction layer in which the metal atom reacts with at least one of carbon or silicon that forms the semiconductor substrate.2. A manufacturing method of a silicon carbide semiconductor device including a semiconductor substrate that has a main surface and a rear surface being an opposite surface of the main surface and is made of single crystal silicon carbide and a first electrode that forms an ohmic junction with the semiconductor substrate , comprising:preparing the semiconductor substrate;stacking an impurity layer that is made of silicon carbide including an impurity and a metal layer that is ...

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Номер записи: 44
31-10-2013 дата публикации

Methods of Forming Doped Regions in Semiconductor Substrates

Номер: US20130288466A1
Автор: Allen Mcteer, Lequn Jennifer Liu, SHU QIN, Yongjun Jeff Hu
Принадлежит: Micron Technology Inc

Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant.

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Номер записи: 45
14-11-2013 дата публикации

HEAVILY DOPED SEMICONDUCTOR NANOPARTICLES

Номер: US20130299772A1
Автор: Banin Uri, Cohen Guy, Millo Oded, Mocatta David, Rabani Eran
Принадлежит:

Herein, provided are heavily doped colloidal semiconductor nanocrystals and a process for introducing an impurity to semiconductor nanoparticles, providing control of band gap, Fermi energy and presence of charge carriers. The method is demonstrated using InAs colloidal nanocrystals, which are initially undoped, and are metal-doped (Cu, Ag, Au) by adding a metal salt solution. 164-. (canceled)65. A nanoparticle comprising a semiconductor material , the semiconductor material being doped with at least two atoms of a dopant material , wherein said atoms of the dopant material are heterovalent to atoms of the material , said at least two atoms of a dopant material being dispersed within said material.66. A nanoparticle according to claim 65 , wherein said at least two atoms of a dopant material altering the density of states of said material.67. The nanoparticle according to claim 65 , wherein the nanoparticle being of a semiconductor material.68. The nanoparticle according to claim 65 , being free of dopant domains.69. The nanoparticle according to claim 65 , being on average in the range of 1 nm to 500 nm in length or diameter claim 65 , 1 nm to 50 nm in length or diameter claim 65 , or 1 nm to 20 nm in length or diameter.70. The nanoparticle according to claim 65 , wherein the semiconductor material is selected from the group of elements consisting of Group I-VII claim 65 , Group II-VI claim 65 , Group III-V claim 65 , Group IV-VI claim 65 , Group and Group IV semiconductors and combinations thereof.71. The nanoparticle according to claim 70 , wherein the semiconductor material is a Group I-VII material being selected from the group consisting of CuCl claim 70 , CuBr claim 70 , CuI claim 70 , AgCl claim 70 , AgBr claim 70 , and AgI claim 70 , or the semiconductor material is a Group II-VI material selected from the group consisting of CdSe claim 70 , CdS claim 70 , CdTe claim 70 , ZnSe claim 70 , ZnS claim 70 , ZnTe claim 70 , HgS claim 70 , HgSe claim 70 , HgTe ...

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Номер записи: 46
14-11-2013 дата публикации

Method for mems device fabrication and device formed

Номер: US20130299926A1
Автор: Joseph Damian Gordon Lacey, Mickael Renault, Thomas L. Maguire, Vikram Joshi
Принадлежит: Cavendish Kinetics Inc

The present invention generally relates to methods for producing MEMS or NEMS devices and the devices themselves. A thin layer of a material having a lower recombination coefficient as compared to the cantilever structure may be deposited over the cantilever structure, the RF electrode and the pull-off electrode. The thin layer permits the etching gas introduced to the cavity to decrease the overall etchant recombination rate within the cavity and thus, increase the etching rate of the sacrificial material within the cavity. The etchant itself may be introduced through an opening in the encapsulating layer that is linearly aligned with the anchor portion of the cantilever structure so that the topmost layer of sacrificial material is etched first. Thereafter, sealing material may seal the cavity and extend into the cavity all the way to the anchor portion to provide additional strength to the anchor portion.

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Номер записи: 47
28-11-2013 дата публикации

PROCESS FOR FORMING A PLANAR DIODE USING ONE MASK

Номер: US20130313684A1
Автор: Chen Max, Chiang Warren, Lu Kevin, Wang Benson
Принадлежит: VISHAY GENERAL SEMICONDUCTOR LLC

A planar diode and method of making the same employing only one mask. The diode is formed by coating a substrate with an oxide, removing a central portion of the oxide to define a window through which dopants are diffused. The substrate is given a Ni/Au plating to provide ohmic contact surfaces, and the oxide on the periphery of the window is coated with a polyimide passivating agent overlying the P/N junction. 1. A diode comprising:(a) a substrate of a first conductivity type and a doped region of a second conductivity type defining a P/N junction therebetween;(b) nickel plating on the underside of the substrate and along a central portion of a top side of the substrate overlying the doped region of the second conductivity type;(c) an oxide coating on the peripheral portion of the top side of the substrate adjacent the central portion; and(d) a coating of a passivating material along the oxide on the top side of the substrate, the passivating material extending partially over the P/N junction.2. The diode of claim 1 , wherein said first conductivity type has N-type conductivity and said second conductivity type has P-type conductivity.3. The diode of claim 1 , wherein said doped region is doped with boron.4. The diode of claim 1 , wherein the passivating material is polyimide.5. A diode comprising:(a) a substrate of a first conductivity type and a doped region of a second conductivity type;(b) metal plating on the underside of the substrate and along a central portion of the top side of the substrate which corresponds to the doped region of the second conductivity type; and(c) a coating of a passivating material on top of the oxide on the top side of the substrate, the passivating material extending partially over the doped region.6. The diode of claim 5 , wherein said first conductivity type is N-type conductivity and said second conductivity type is P-type conductivity.7. The diode of claim 5 , wherein said doped region is doped with boron.8. The diode of claim 5 ...

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Номер записи: 48
12-12-2013 дата публикации

Method of semiconductor film stabilization

Номер: US20130330911A1
Автор: Errol Antonio C. Sanchez, Yi-Chiau Huang, Yihwan Kim
Принадлежит: Individual

Embodiments of the invention generally relate to methods for forming silicon-germanium-tin alloy epitaxial layers, germanium-tin alloy epitaxial layers, and germanium epitaxial layers that may be doped with boron, phosphorus, arsenic, or other n-type or p-type dopants. The methods generally include positioning a substrate in a processing chamber. A germanium precursor gas is then introduced into the chamber concurrently with a stressor precursor gas, such as a tin precursor gas, to form an epitaxial layer. The flow of the germanium gas is then halted, and an etchant gas is introduced into the chamber. An etch back is then performed while in the presence of the stressor precursor gas used in the formation of the epitaxial film. The flow of the etchant gas is then stopped, and the cycle may then be repeated. In addition to or as an alternative to the etch back process, an annealing processing may be performed.

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Номер записи: 49
26-12-2013 дата публикации

Method for obtaining data of substrate processing apparatus and sensor substrate

Номер: US20130346018A1
Автор: Hikaru AKADA
Принадлежит: Tokyo Electron Ltd

According to an embodiment of the present invention, a data obtainment method for obtaining data on gas flow directions in a plurality of measurement regions in a surface of a substrate loaded onto a loading unit of a substrate processing apparatus is provided. The method includes loading a sensor substrate onto the loading unit in a first direction, and changing the first direction into a second direction. Further, it is obtained a vector data of a gas flow in a first straight direction and a vector data of a gas flow in a second straight direction from each first sensor of the sensor substrate loaded in the first and second directions. Also, the method includes calculating a gas flow direction at each starting point in the first and second measurement regions by combining the vector data.

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Номер записи: 50
02-01-2014 дата публикации

Systems and methods for processing thin films

Номер: US20140001164A1
Автор: James S. Im
Принадлежит: Columbia University of New York

Methods and systems for processing a thin film are disclosed. Thin films are loaded onto two different loading fixtures, laser beam pulses are split into first and second laser beam pulses, the thin film loaded on one loading fixture is irradiated with the first laser beam pulses to induce crystallization while the thin film loaded on the other loading fixture is irradiated with the second laser beam pulses. At least a portion of the thin film loaded on the first and second loading fixtures is irradiated. The laser source system includes first and second laser sources and an integrator that combines the laser beam pulses to form combined laser beam pulses. The methods and system further utilize additional loading fixtures for processing additional thin film samples. The irradiation of additional thin film samples can be performed while thin film samples are being loaded onto the remaining loading fixtures.

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Номер записи: 51
16-01-2014 дата публикации

TOUCH SCREEN PANELS AND METHODS OF FABRICATING THE SAME

Номер: US20140015771A1
Автор: CHEONG Woo-Seok, Kim Kyung Hyun, Park Rae-Man, SHIN Jaeheon
Принадлежит: Electronics and Telecommunications Research Institute

Provided are touch screen panels with improved transmittance and methods of fabricating the same. the method may include preparing a substrate including a cell region and an interconnection region provided around the cell region, sequentially forming a first buffer layer and a second buffer layer on the substrate, the second buffer layer having a refractive index less than that of the first buffer layer, and forming a transparent electrode on the second buffer layer. The second buffer layer is formed of a SiOC material. 1. A method of fabricating a touch screen panel , comprising:preparing a substrate including a cell region and an interconnection region provided around the cell region;sequentially forming a first buffer layer and a second buffer layer on the substrate, the second buffer layer having a refractive index less than that of the first buffer layer; andforming a transparent electrode on the second buffer layer,wherein the second buffer layer is formed of a SiOC material.2. The method of claim 1 , wherein the forming of the second buffer layer comprises performing a reactive sputtering process using a SiC material as a target claim 1 , under an oxygen partial pressure condition of 1% to 40%.3. The method of claim 1 , wherein the transparent electrode comprises an indium tin oxide (ITO) layer.4. The method of claim 3 , wherein the transparent electrode has a thickness of 10 nm to 100 nm.5. The method of claim 1 , wherein the first buffer layer comprises a material of TiO claim 1 , NbO claim 1 , ZrO claim 1 , TaO claim 1 , or HfO.6. The method of claim 1 , wherein the first buffer layer has a thickness of 3 nm to 100 nm.7. The method of claim 1 , wherein the first buffer layer has a refractive index of 1.6 to 2.7.8. The method of claim 1 , wherein the second buffer layer has a thickness of 5 nm to 100 nm.9. The method of claim 1 , wherein the second buffer layer has a refractive index of 1.4 to 1.48.10. The method of claim 1 , wherein the first buffer layer ...

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Номер записи: 52
30-01-2014 дата публикации

METHOD OF FABRICATING A DEVICE WITH A CONCENTRATION GRADIENT AND THE CORRESPONDING DEVICE

Номер: US20140027886A1
Автор: Bensahel Daniel-Camille, Morand Yves
Принадлежит: STMICROELECTRONICS (CROLLES 2) SAS

A semiconductive device is fabricated by forming, within a semiconductive substrate, at least one continuous region formed of a material having a non-uniform composition in a direction substantially perpendicular to the thickness of the substrate. 1. A method , comprising:forming a trench in a layer of a first material;filling the trench with an alloy material comprising a combination the first material and a second material, the second material being present in the alloy material with a heavier concentration than the first material;performing heat drive-in to stimulate lateral diffusion of the second material from the alloy material filling the trench and into the first material in the layer within which the trench is formed so as to form a non-uniform composition in a direction substantially perpendicular to a depth of the trench.2. The method of further comprising etching a top surface of the deposited layers which fill the trench.3. The method of wherein the etching forms a top surface having one of a convex and concave profile.4. The method of claim 1 , wherein the first material is silicon and the second material is germanium.5. A method for fabricating a semiconductive device with a concentration gradient claim 1 , the method comprising:forming a cavity in a protective layer and a silicon layer above an etch stop layer and a substrate of the semiconductive device;filling of the cavity with an alloy; andperforming a drive-in diffusion to form, in a portion of the silicon layer adjacent to the cavity, a gradient of a material from the alloy extending in a direction substantially perpendicular to the thickness of the semiconductive device.6. The method of claim 5 , wherein the material from the alloy is germanium.7. The method of claim 6 , wherein the gradient is a varying ratio of silicon to germanium as a function of distance from the cavity.8. The method of claim 5 , wherein the etch stop layer lies horizontally on top of the substrate and the silicon layer ...

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Номер записи: 53
30-01-2014 дата публикации

METHOD OF DIFFUSING IMPURITY-DIFFUSING COMPONENT AND METHOD OF MANUFACTURING SOLAR CELL

Номер: US20140030839A1
Автор: Kamizono Takashi, Morita Toshiro, Takahashi Motoki
Принадлежит: TOKYO OHKA KOGYO CO., LTD.

A method of diffusing an impurity-diffusing component including forming a first diffusing agent layer containing a first conductivity type impurity-diffusing component on the surface of a semiconductor substrate; calcining the first diffusing agent layer; forming a second diffusing agent layer containing a second conductivity type impurity-diffusing component on the surface of the semiconductor substrate excluding the region where the first diffusing agent layer is formed; and heating the semiconductor substrate at a temperature higher than the calcination temperature to diffuse the first and second conductivity type impurity-diffusing components to the semiconductor substrate. 1. A method of diffusing an impurity-diffusing component comprising:forming a first diffusing agent layer containing a first conductivity-type impurity diffusing component on the surface of a semiconductor substrate;calcining the first diffusing agent layer;forming a second diffusing agent layer containing a second conductivity-type impurity diffusing component on the surface of the semiconductor substrate excluding a region where the first diffusing agent layer is formed; andheating the semiconductor substrate at a temperature higher than a calcination temperature to diffuse the first conductivity-type impurity diffusing component and the second conductivity-type impurity diffusing component into the semiconductor substrate.2. The method of diffusing an impurity-diffusing component according to claim 1 , wherein the first conductivity type is boron claim 1 , and the second conductivity type is phosphorus.3. The method of diffusing an impurity-diffusing component according to claim 1 , wherein the first diffusing agent layer and the second diffusing agent layer are formed on the same surface of the semiconductor substrate.4. The method of diffusing an impurity-diffusing component according to claim 1 , wherein claim 1 , in the calcining claim 1 , the first diffusing agent layer is heated at a ...

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Номер записи: 54
30-01-2014 дата публикации

METHOD OF VAPOR-DIFFUSING IMPURITIES

Номер: US20140030879A1
Автор: FURUSAWA Yoshikazu, Okada Mitsuhiro, TAKAHASHI Kazuya
Принадлежит: TOKYO ELECTRON LIMITED

A method of vapor-diffusing impurities into a diffusion region of a target substrate to be processed using a dummy substrate is provided. The method includes loading the target substrate and the dummy substrate in a substrate loading jig, accommodating the substrate loading jig loaded with the target substrate and the dummy substrate in a processing chamber of a processing apparatus, and vapor-diffusing impurities into the diffusion region of the target substrate in the processing chamber having the accommodated substrate loading jig. The vapor-diffused impurities are boron, an outer surface of the dummy substrate includes a material having properties not allowing boron adsorption. 1. A method of vapor-diffusing impurities into a diffusion region of a target substrate to be processed using a dummy substrate , comprising:loading the target substrate and the dummy substrate in a substrate loading jig;accommodating the substrate loading jig loaded with the target substrate and the dummy substrate in a processing chamber of a processing apparatus; andvapor-diffusing impurities into the diffusion region of the target substrate in the processing chamber having the accommodated substrate loading jig,wherein, when the vapor-diffused impurities are boron, an outer surface of the dummy substrate includes a material having properties not allowing boron adsorption.2. The method of claim 1 , wherein the loading claim 1 , the accommodating claim 1 , and the vapor-diffusing are performed on the target substrate and the dummy substrate in a batch processing unit claim 1 , and in a subsequent batch processing unit claim 1 , the loading claim 1 , the accommodating claim 1 , and the vapor-diffusing are performed on a subsequent target substrate and the dummy substrate from the batch processing unit.3. The method of claim 1 , wherein after vapor-diffusing the impurities claim 1 , an oxygen gas purge is performed.4. The method of claim 1 , wherein after vapor-diffusing the impurities ...

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Номер записи: 55
06-02-2014 дата публикации

Memory Devices Comprising Word Line Structures, At Least One Select Gate Structure, and a Plurality Of Doped Regions

Номер: US20140035021A1
Автор: ARITOME Seiichi, Larsen Chris, Li Di, Moradi Behnam, Prall Kirk D.
Принадлежит: MICRON TECHNOLOGY, INC.

Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures. 136-. (canceled)37. A memory device , comprising:a plurality of word line structures and at least one select gate structure positioned above a semiconducting substrate, the word line structures individually comprising gate insulation over the semiconducting substrate, a floating gate over the gate insulation, inter-gate insulation over the floating gate, and a control gate over the inter-gate insulation; anda plurality of doped regions formed in said substrate adjacent said word line structures and said at least one select gate structure, wherein said doped regions between said word line structures have a shallower depth than said doped region adjacent said at least one select gate structure.38. (canceled)39. The device of claim 37 , wherein said doped regions between said word line structures comprise halogen ions.40. (canceled)41. (canceled)42. The device of claim 37 , wherein said doped regions between said word line structures have a depth that is approximately 30-60% of a depth of said doped region adjacent said at least one select gate structure.43. The memory device of comprising halogen atoms in the floating gate.44. The memory device of comprising halogen atoms in the semiconducting substrate beneath the gate insulation.45. The memory ...

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Номер записи: 56
13-02-2014 дата публикации

Composite substrate and method of manufacturing the same

Номер: US20140042598A1
Автор: Masanobu Kitada, Motokazu Ogawa, Yoshiyuki Kawaguchi
Принадлежит: Kyocera Corp

A composite substrate which includes a silicon layer having less lattice defects is provided. A composite substrate includes an insulating substrate and a functional layer of which one main surface is bonded to an upper surface of the substrate. A dopant concentration of the functional layer decreases from the other main surface toward the substrate side in a thickness direction of the functional layer.

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Номер записи: 57
06-03-2014 дата публикации

Substrate processing apparatus

Номер: US20140060423A1
Автор: Hitoshi Nakai, Yasuhiko Ohashi
Принадлежит: Dainippon Screen Manufacturing Co Ltd

A substrate processing apparatus includes a chamber, a substrate holding part, a substrate rotating mechanism, a liquid receiving part, and an upper nozzle. The chamber includes a chamber body and a chamber cover, and the chamber cover is moved up and down. While the chamber cover is in contact with the chamber body, a small sealed space is formed and some processings involving pressure reduction or pressurization are performed. When the chamber cover is moved up, an annular opening is formed between the chamber cover and the chamber body. On an outer side relative to the annular opening, positioned are a first cup part and a second cup part. A processing liquid spattering from a substrate is received by the first cup part or the second cup part. In the substrate processing apparatus, it is possible to perform various processings in the small chamber.

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Номер записи: 58
06-03-2014 дата публикации

Jfet having width defined by trench isolation

Номер: US20140062524A1
Автор: Binghua Hu, Pinghai Hao, Sameer Pendharkar
Принадлежит: Texas Instruments Inc

A junction field-effect transistor (JFET) includes a substrate having a first-type semiconductor surface including a topside surface, and a top gate of a second-type formed in the semiconductor surface. A first-type drain and a first-type source are formed on opposing sides of the top gate. A first deep trench isolation region has an inner first trench wall and an outer first trench wall surrounding the top gate, the drain and the source, and extends vertically to a deep trench depth from the topside surface. A second-type sinker formed in semiconductor surface extends laterally outside the outer first trench wall. The sinker extends vertically from the topside surface to a second-type deep portion which is both below the deep trench depth and laterally inside the inner first trench wall to provide a bottom gate.

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Номер записи: 59
06-03-2014 дата публикации

TOUCH SCREENS AND METHODS OF MANUFACTURING THE SAME

Номер: US20140062906A1
Автор: Park Rae-Man
Принадлежит: Electronics and Telecommunications Research Institute

Disclosed are touch screens and methods of manufacturing the same. The touch screen may include a substrate, a first electrode extending in a first direction on the substrate, an interlayer insulating layer disposed on the first electrode, and a second electrode disposed on the interlayer insulating layer and extending in a second direction crossing the first direction. The interlayer insulating layer may have quantum dots that induce a change of a capacitance between the first electrode and the second electrode by a visible light incident on the substrate. 1. A touch screen comprising:a substrate;a first electrode extending in a first direction on the substrate;an interlayer insulating layer disposed on the first electrode; anda second electrode disposed on the interlayer insulating layer and extending in a second direction crossing the first direction,wherein the interlayer insulating layer has quantum dots that induce a change of a capacitance between the first electrode and the second electrode by a visible light incident on the substrate.2. The touch screen of claim 1 , wherein the quantum dots include silicon nano particles.3. The touch screen of claim 2 , wherein each of the silicon nano particles has a particle size within a range of about 2 nm to about 7 nm.4. The touch screen of claim 2 , wherein a number density of the silicon nano particles in the interlayer insulating layer has a range of about 1×10ea/cmto about 1×10ea/cm.5. The touch screen of claim 1 , wherein the interlayer insulating layer includes a silicon oxide layer or a silicon nitride layer.6. The touch screen of claim 1 , wherein the first electrode and a second electrode include a transparent metal.7. The touch screen of claim 6 , wherein the transparent metal includes indium-tin oxide (ITO) and/or indium-zinc oxide (IZO).8. The touch screen of claim 1 , wherein the second electrode comprises:separation electrodes spaced apart from each other in the second direction on the substrate, the ...

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Номер записи: 60
13-03-2014 дата публикации

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Номер: US20140070369A1
Автор: KITAMURA Shoji
Принадлежит: FUJI ELECTRIC CO., LTD.

A simplified manufacturing process stably produces a semiconductor device with high electrical characteristics, wherein platinum acts as an acceptor. Plasma treatment damages the surface of an oxide film formed on a ntype drift layer deposited on an n type semiconductor substrate. The oxide film is patterned to have tapered ends. Two proton irradiations are carried out on the ntype drift layer with the oxide film as a mask to form a point defect region in the vicinity of the surface of the ntype drift layer. Silica paste containing 1% by weight platinum is applied to an exposed region of the ntype drift layer surface not covered with the oxide film. Heat treatment inverts the vicinity of the surface of the ntype drift layer to p-type by platinum atoms which are acceptors. A p-type inversion enhancement region forms a p-type anode region. 1. A semiconductor device manufacturing method , comprising:a point defect introduction step of introducing point defects into a surface of a first conductivity type semiconductor layer at a point defect density higher than the point defect density in the semiconductor layer in a state of thermal equilibrium to produce a point defect region;a transition metal introduction step of introducing a transition metal into the point defect region; andan activation step of using heat treatment to advance the electrical activation of the transition metal in the point defect region.2. A semiconductor device manufacturing method , comprising:a transition metal introduction step of introducing a transition metal into a surface of a first conductivity type semiconductor layer;an activation step of using heat treatment to electrically activate the transition metal;a point defect introduction step of introducing point defects into the region into which the transition metal has been introduced at a point defect density higher than the point defect density in the semiconductor layer in a state of thermal equilibrium; anda reactivation step of using ...

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Номер записи: 61
27-03-2014 дата публикации

WELDED BELLOWS FOR SEMICONDUCTOR MANUFACTURING DEVICE

Номер: US20140082906A1
Автор: Inoue Masahiko, Ochiai Hiroyuki, TAKAHASHI Hidekazu
Принадлежит:

An accordion-structured welded bellows for a semiconductor-manufacturing device is characterized in that a plurality of annular bellows plates having curved surfaces in a radial direction are connected in an alternating fashion on the outside-diameter side and the inside-diameter side, wherein the annular bellows plates have a processing-side bellows plate and a non-processing-side bellows plate, a gas layer is interposed between the two bellows plates, the processing-side bellows plate is configured as a thick plate, and the non-processing-side bellows plate is configured as a thin plate. The welded bellows is less likely to be damaged by foreign matter and to be able to use the non-processing-side bellows plate to compensate for any damage to the processing-side bellows plate. 1. An accordion-structured welded bellows for a semiconductor-manufacturing device in which a plurality of annular bellows plates having curved surfaces in a radial direction are connected in an alternating fashion on the outside-diameter side and the inside-diameter side , characterized in that:the annular bellows plates have a processing-side bellows plate and a non-processing-side bellows plate;a gas layer is interposed between the two bellows plates;the processing-side bellows plate is configured as a thick plate; andthe non-processing-side bellows plate is configured as a thin plate.2. The welded bellows for a semiconductor-manufacturing device according to claim 1 , characterized in that:the processing side is a vacuum; andthe non-processing side is the atmosphere.3. The welded bellows for a semiconductor-manufacturing device according to claim 1 , characterized in being used for sealing a gate valve with which an opening in a vacuum processing chamber used in a manufacturing step of a semiconductor-manufacturing device can be opened and closed in an airtight manner.4. The welded bellows for a semiconductor-manufacturing device according to claim 1 , characterized in being actuated by ...

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Номер записи: 62
27-03-2014 дата публикации

METHOD FOR FORMING PATTERNED DOPING REGIONS

Номер: US20140087549A1
Автор: Lin Tzer-Shen, SUN Wen-Ching, Wang Tai-Jui, Yu Sheng-Min
Принадлежит: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

A method for forming doping regions is disclosed, including providing a substrate, forming a first-type doping material on the substrate and forming a second-type doping material on the substrate, wherein the first-type doping material is separated from the second-type doping material by a gap; forming a covering layer to cover the substrate, the first-type doping material and the second-type doping material; and performing a thermal diffusion process to diffuse the first-type doping material and the second-type doping material into the substrate. 1. A method for forming doping regions , comprising:providing a substrate;forming a first-type doping material on the substrate;forming a second-type doping material on the substrate, wherein the first-type doping material is separated from the second-type doping material by a gap;forming a covering layer to cover the substrate, the first-type doping material, and the second-type doping material; andperforming a thermal diffusion process to diffuse the first-type doping material and the second-type doping material into the substrate.3. The method for forming doping regions as claimed in claim 2 , wherein the first-type doping material is n-type doping material or p-type doping material claim 2 , the second-type doping material is p-type doping material or n-type doping material claim 2 , and the first-type doping material and the second-type doping material have reverse conductivity type.4. The method for forming doping regions as claimed in claim 3 , wherein the p-type doping material is a boride claim 3 , aluminide or gallide claim 3 , and the n-type doping material is a phosphide claim 3 , arsenide or telluride.5. The method for forming doping regions as claimed in claim 1 , wherein the covering layer is SiNor AlO.6. The method for forming doping regions as claimed in claim 1 , wherein the step of forming the covering layer comprises spray coating claim 1 , spin coating claim 1 , screen printing claim 1 , plasma ...

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Номер записи: 63
03-04-2014 дата публикации

PLASMA DOPING APPARATUS, PLASMA DOPING METHOD, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20140094024A1
Автор: Horigome Masahiro, KOBAYASHI Yuuki, Oka Masahiro, Ueda Hirokazu
Принадлежит: TOKYO ELECTRON LIMITED

Disclosed is a plasma doping apparatus including a processing chamber, a substrate holding unit, a plasma generating mechanism, a pressure control mechanism, a bias power supply mechanism, and a control unit. The control unit controls the pressure within the processing chamber to be a first pressure and controls the bias power to be supplied to the holding unit is to be a first bias power for a first plasma process. The control unit also controls the pressure within the processing chamber to be a second pressure which is higher than the first pressure, and controls the bias power to be supplied to the holding unit to be a second bias power which is lower than the first bias power for a second plasma process. 1. A plasma doping apparatus comprising:a processing chamber configured to accommodate a substrate to be processed so that the substrate is implanted with a dopant;a gas supply unit configured to supply a doping gas and an inert gas for plasma excitation into the processing chamber;a holding unit disposed within the processing chamber and configured to hold the substrate thereon;a plasma generating mechanism configured to generate a plasma within the processing chamber by using a microwave;a pressure control mechanism configured to control a pressure within the processing chamber;a bias power supply mechanism configured to supply an AC bias power to the holding unit; anda control unit configured to control the plasma doping apparatus,wherein the control unit controls the pressure control mechanism so as to set the pressure within the processing chamber to be a first pressure, and controls the bias power supply mechanism so as to set the bias power to be supplied to the holding unit to be a first bias power, so that a first plasma processing is performed on the substrate by the plasma generated by the plasma generating mechanism, and after the first plasma processing, the control unit controls the pressure control mechanism so as to set the pressure within the ...

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Номер записи: 64
10-04-2014 дата публикации

Integrated diode array and corresponding manufacturing method

Номер: US20140097511A1
Автор: Gregor Schuermann, Hubert Benzel
Принадлежит: ROBERT BOSCH GMBH

An integrated diode array and a corresponding manufacturing method are provided. The integrated diode array includes a substrate having an upper side, and a plurality of blocks of several diodes, which are positioned in a planar manner and are suspended at the substrate above a cavity situated below them in the substrate. The blocks are separated from one another by respective gaps, and within a specific block, the individual diodes are electrically insulated from one another by first STI trenches situated between them.

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Номер записи: 65
01-01-2015 дата публикации

Systems and methods for processing thin films

Номер: US20150004808A1
Автор: James S. Im
Принадлежит: Columbia University of New York

The present disclosure is directed to methods and systems for processing a thin film samples. In an exemplary method, semiconductor thin films are loaded onto two different loading fixtures, laser beam pulses generated by a laser source system are split into first laser beam pulses and second laser beam pulses, the thin film loaded on one loading fixture is irradiated with the first laser beam pulses to induce crystallization while the thin film loaded on the other loading fixture is irradiated with the second laser beam pulses. In a preferred embodiment, at least a portion of the thin film that is loaded on the first loading fixture is irradiated while at least a portion of the thin film that is loaded on the second loading fixture is also being irradiated. In an exemplary embodiment, the laser source system includes first and second laser sources and an integrator that combines the laser beam pulses generated by the first and second laser sources to form combined laser beam pulses. In certain exemplary embodiments, the methods and system further utilize additional loading fixtures for processing additional thin film samples. In such methods and systems, the irradiation of thin film samples loaded on some of the loading fixtures can be performed while thin film samples are being loaded onto the remaining loading fixtures. In certain exemplary methods and systems, the crystallization processing of the semiconductor thin film samples can consist of a sequential lateral solidification (SLS) process.

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Номер записи: 66
04-01-2018 дата публикации

CONDUCTIVE TEST PROBE

Номер: US20180003738A1
Автор: Russell Wayne
Принадлежит: Power Probe TEK, LLC

A conductive probe may include a probe body for communicating with a circuit tester or a jumper. The probe body may be formed of metal and may have a free end. A probe tip may be mounted to the end of the probe body. The probe tip may be formed of thorium-tungsten. The probe tip may be configured for contacting a circuit node. 120.-. (canceled)21. A conductive probe , comprising:a probe body comprised of a conductor;a probe tip coupled with the probe body; anda probe plug configured to couple the probe body with a circuit tester or a jumper.22. The conductive probe of claim 21 , wherein the probe body is configured to conduct an electrical current between the probe plug and the probe tip mounted to an end of probe body.23. The conductive probe of claim 21 , wherein the probe body includes portions that are enclosed in an insulating layer so as to prevent unintended electrical shorting to a test environment.24. The conductive probe of claim 21 , wherein the probe tip is configured to provide a low contact resistance with a circuit node and minimize the electrical resistance of the conductive probe.25. The conductive probe of claim 21 , wherein the circuit tester is comprised of a multi-meter electrical circuit tester or other electrical test equipment that may be used to diagnose or repair an electrical circuit.26. The conductive probe of claim 21 , wherein the probe plug is configured to electrically mate with a circuit tester jack of the circuit tester.27. The conductive probe of claim 26 , wherein the probe plug is configured to slidably couple with the circuit tester jack.28. The conductive probe of claim 26 , wherein the probe plug is configured to threadably couple with the circuit tester jack.29. The conductive probe of claim 21 , wherein the probe tip is comprised of a buried end configured to be coupled with a socket disposed in the probe body and a narrowed end configured for contacting a circuit node to be measured.30. The conductive probe of claim 29 , ...

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Номер записи: 67
02-01-2020 дата публикации

Semiconductor Device and Method

Номер: US20200006533A1
Автор: Chen Jung-Jen, Chen Kei-Wei, Jeng Pei-Ren, Li Chii-Horng, Tsai Ji-Yin, Yeo Yee-Chia
Принадлежит:

In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack. 1. A device comprising:a substrate;a first semiconductor region extending from the substrate, the first semiconductor region comprising silicon;a second semiconductor region on the first semiconductor region, the second semiconductor region comprising silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration;a gate stack on the second semiconductor region; andsource and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.2. The device of claim 1 , wherein edge portions of the first semiconductor region have a third germanium concentration claim 1 , a center portion of the first semiconductor region having a fourth germanium concentration less than the third germanium concentration.3. The device of claim 1 , wherein the gate stack comprises:a gate dielectric extending along the edge portions of the second semiconductor region and along a top surface of the second semiconductor region; anda gate electrode on the gate dielectric.4. The device of claim 1 , wherein the first semiconductor region has a first width claim 1 , the second semiconductor region has a ...

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Номер записи: 68
03-01-2019 дата публикации

Laterally Diffused Metal Oxide Semiconductor with Gate Poly Contact within Source Window

Номер: US20190006514A1
Автор: MATHUR Guru, Pendharkar Sameer
Принадлежит:

An integrated circuit includes a power transistor having at least one transistor finger that lies within a semiconductor material substrate. Each transistor finger has a source region stripe and a substantially parallel drain region stripe. A gate structure lies between the source region stripe and the drain region stripe and has a plurality of fingers that extend over the source region stripe. Contacts are formed that connect to the fingers of the gate structure over thick oxide islands in the source region stripes. A conductive gate runner is connected to the contacts of the gate layer structure over the thick oxide islands in the source region stripe. 1. A method for fabricating a power transistor in an integrated circuit , the method comprising:diffusing a source region stripe into an epitaxial layer of a semiconductor substrate, and a drain region stripe into the epitaxial layer such that a channel region stripe is located substantially parallel to and between the source region stripe and the drain region stripe;growing thick oxide islands that overlie the source region stripe;forming contacts connected to a gate structure over the thick oxide islands; andforming a conductive gate runner that connects to the contacts of the gate structure over the plurality of thick oxide islands.2. The method of claim 1 , further including diffusing into the substrate a first well having a first conductivity type into which the source region stripe is diffused claim 1 , and diffusing into the substrate a second well having a second conductivity type into which the drain region stripe is diffused.3. The method of claim 2 , in which the power transistor is a laterally diffused metal oxide semiconductor device and in which the second well forms a drift region.4. The method of claim 1 , in which the gate structure comprises polysilicon.5. The method of claim 1 , wherein the at least one transistor finger has a linear topology.6. The method of claim 1 , wherein the conductive gate ...

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Номер записи: 69
08-01-2015 дата публикации

BRIDGE RECTIFIER AND METHOD FOR SAME

Номер: US20150008564A1
Автор: TSENG CHING-CHIU
Принадлежит:

A bridge rectifier including a common P-type diode, a common N-type diode, two first metal layers, two pairs of second metal layers, two AC inputs and two DC outputs. The P-type diode includes a common P-type doping region, a pair of first N-type substrate regions and a pair of P-type doping regions. The N-type diode includes a common N-type doping region, a pair of second N-type substrate regions and a pair of N-type doping regions. The first metal layers connect to the common N-type doping region and the common P-type doping region. The second metal layers connect to the P-type doping region and the N-type doping region. Two AC inputs connect to one of the second metal layers of the P-type diode and one of the second metal layers of the N-type diode respectively. Two DC inputs connect to the first metal layers respectively. 1. A bridge rectifier comprising:a common P-type diode comprising a common P-type doping region, a pair of first N-type substrate regions and a pair of N-type doping regions, the first N-type substrate regions positioned between the common P-type doping region and the N-type doping regions;a common N-type diode comprising a common N-type doping region, a pair of second N-type substrate regions and a pair of P-type doping regions, the second N-type substrate regions positioned between the common N-type doping region and the P-type doping regions;two first metal layers connected to the common N-type doping region and the common P-type doping region respectively;two pairs of second metal layers connected to the pair of N-type doping regions and the pair of P-type doping regions respectively;two AC inputs connecting to one of the second metal layers of the common N-type diode and one of the second metal layers of the common P-type diode; andtwo DC outputs connecting to two first metal layers respectively.2. The bridge rectifier of claim 1 , wherein the common P-type diode and the common N-type diode each has a trench claim 1 , wherein the trench of ...

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Номер записи: 70
08-01-2015 дата публикации

Method for Forming Biochips and Biochips With Non-Organic Landings for Improved Thermal Budget

Номер: US20150011021A1
Автор: Chang Allen Timothy, CHANG Yi-Hsien, Chen Ching-Ray, Cheng Chun-Ren, Cheng Chun-Wen, Chu Chia-Hua, Liu Yi-Shao
Принадлежит:

The present disclosure provides biochips and methods of fabricating biochips. The method includes combining three portions: a transparent substrate, a first substrate with microfluidic channels therein, and a second substrate. Through-holes for inlet and outlet are formed in the transparent substrate or the second substrate. Various non-organic landings with support medium for bio-materials to attach are formed on the first substrate and the second substrate before they are combined. In other embodiments, the microfluidic channel is formed of an adhesion layer between a transparent substrate and a second substrate with landings on the substrates. 1. A method of manufacturing a biochip , comprising:providing a transparent substrate;forming a patterned passivating layer on the transparent substrate;forming a patterned adhesion layer on the transparent substrate;providing a second substrate having a plurality of landings; and,bonding the transparent substrate to the second substrate via the patterned adhesion layer.2. The method of claim 1 , further comprising:forming a plurality of through-holes in the transparent substrate.3. The method of claim 1 , further comprising:flowing an adhesion material through microfluidic channels, wherein the adhesion material adheres to the landings;flowing a support media material through microfluidic channels, wherein the support media material adheres to the adhesion material on the landings; andflowing bio-materials through microfluidic channels having the patterned adhesion layer as sidewalls, wherein the bio-materials adhere on the landings and wherein the bio-materials adhere to the support media material on the landings.4. The method of claim 1 , wherein the landings overlay exposed portion of the transparent substrate.5. The method of claim 1 , wherein the forming the patterned adhesion layer comprises depositing and patterning a plurality of adhesion material layers.6. The method of claim 1 , wherein the step of forming a ...

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Номер записи: 71
11-01-2018 дата публикации

SYSTEMS AND METHODS FOR SORTING IMAGE ACQUISITION SETTINGS FOR PATTERN STITCHING AND DECODING USING MULTIPLE CAPTURED IMAGES

Номер: US20180012052A1
Автор: Borovszki Jozsef, Negro James A., ROBLES Robb, Vekony David, Wang Xianju, Webster Steven G., Ye Xiangyun
Принадлежит:

Systems and methods are described for acquiring and decoding a plurality of images. First images are acquired and then processed to attempt to decode a symbol. Contributions of the first images to the decoding attempt are identified. An updated acquisition-settings order is determined based at least partly upon the contributions of the first images to the decoding attempt. Second images are acquired or processed based at least partly upon the updated acquisition-settings order. 1. A system for decoding a symbol using images of the symbol , the system comprising:an imaging device configured to acquire multiple images, each of the acquired images including a respective symbol data region; receive a first plurality of images for a first read cycle of the system, the first plurality of images being acquired by the imaging device in a first acquisition order using respective acquisition settings, the first plurality of images including first and second images that are acquired, respectively, using first and second acquisition settings determined according to an initial acquisition-settings order;', generating a synthetic model of the symbol, the synthetic model being a model of a plurality of known features of the symbol;', 'comparing the synthetic model of the symbol with at least the first and second images;', 'converting a first symbol data region of the first image into a first binary matrix and converting a second symbol data region of the second image into a second binary matrix; and', 'at least partly combining the first binary matrix with the second binary matrix to generate a combined binary matrix, the combined binary matrix being a decodable representation of the symbol;, 'execute a data stitching algorithm including, 'attempt to decode the symbol based at least partly upon the combined binary matrix; and', 'receive a second plurality of images for a second read cycle of the system, the second plurality of images being acquired by the imaging device in a ...

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Номер записи: 72
09-01-2020 дата публикации

INSULATING INDUCTOR CONDUCTORS WITH AIR GAP USING ENERGY EVAPORATION MATERIAL (EEM)

Номер: US20200013551A1
Автор: SINGH Jagar, Singh Sunil K.
Принадлежит: GLOBALFOUNDRIES INC.

A first layer on a substrate includes an insulator material portion adjacent an energy-reactive material portion. The energy-reactive material portion evaporates upon application of energy during manufacturing. Processing patterns the first layer to include recesses extending to the substrate in at least the energy-reactive material portion. The recesses are filled with a conductor material, and a porous material layer is formed on the first layer and on the conductor material. Energy is applied to the porous material layer to: cause the energy to pass through the porous material layer and reach the energy-reactive material portion; cause the energy-reactive material portion to evaporate; and fully remove the energy-reactive material portion from an area between the substrate and the porous material layer, and this leaves a void between the substrate and the porous material layer and adjacent to the conductor material. 1. An integrated circuit structure comprising:a substrate;a first layer on the substrate; anda porous material layer on the first layer, first electrical conductors comprising an inductor structure;', 'a void adjacent to the first electrical conductors of the inductor structure; and', 'an insulator material portion bordering the inductor structure,, 'wherein the first layer includeswherein the insulator material portion includes second electrical conductors comprising electrical connectors separate from the inductor structure, andwherein the void extends between the substrate and the porous material layer.2. The integrated circuit structure according to claim 1 , wherein the porous material layer has pores capable of allowing ultraviolet light to pass through.3. The integrated circuit structure according to claim 1 , wherein the porous material layer has pores capable of allowing an evaporated energy-reactive material portion to pass through.4. The integrated circuit structure according to claim 1 , further comprising an insulator layer on the porous ...

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Номер записи: 73
18-01-2018 дата публикации

Methods for creating a semiconductor wafer having profiled doping and wafers and solar cell components having a profiled field, such as drift and back surface

Номер: US20180019365A1
Автор: Adam M Lorenz, G.D. Stephen Hudelson, Kernan D Brian, Ralf Jonczyk, Richard L. Wallace
Принадлежит: 1366 TECHNOLOGIES INC

A semiconductor wafer forms on a mold containing a dopant. The dopant dopes a melt region adjacent the mold. There, dopant concentration is higher than in the melt bulk. A wafer starts solidifying. Dopant diffuses poorly in solid semiconductor. After a wafer starts solidifying, dopant can not enter the melt. Afterwards, the concentration of dopant in the melt adjacent the wafer surface is less than what was present where the wafer began to form. New wafer regions grow from a melt region whose dopant concentration lessens over time. This establishes a dopant gradient in the wafer, with higher concentration adjacent the mold. The gradient can be tailored. A gradient gives rise to a field that can function as a drift or back surface field. Solar collectors can have open grid conductors and better optical reflectors on the back surface, made possible by the intrinsic back surface field.

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Номер записи: 74
22-01-2015 дата публикации

BACKSCATTERING FOR LOCALIZED ANNEALING

Номер: US20150021746A1
Автор: Theodore Nirmal David
Принадлежит: Freescale Semiconductor, Inc.

A method of fabricating an electronic apparatus includes forming an active layer over a wafer, forming a backscatter layer over the wafer, and directing radiation toward the wafer to anneal the active layer. The backscatter layer is not transparent to the radiation, more reflective than absorptive of the radiation, and positioned such that the backscatter layer inhibits exposure of the wafer to the radiation apart from the active layer. 1. A method of fabricating an electronic apparatus , the method comprising:forming an active layer over a wafer;forming a backscatter layer over the wafer; anddirecting radiation toward the wafer to anneal the active layer;wherein the backscatter layer is not transparent to the radiation, is more reflective than absorptive of the radiation, and is positioned such that the backscatter layer inhibits exposure of the wafer to the radiation apart from the active layer.2. The method of claim 1 , wherein forming the backscatter layer is implemented before forming the active layer such that the backscatter layer is disposed between the active layer and a substrate of the wafer.3. The method of claim 2 , wherein an intermediate active layer is disposed between the backscatter layer and the substrate such that the backscatter layer minimizes an extent to which the radiation reaches the intermediate active layer.4. The method of claim 1 , wherein:the wafer comprises a substrate transparent to the radiation such that the radiation passes through the substrate to reach the active layer; andforming the active layer is implemented before forming the backscatter layer such that the active layer is disposed between the backscatter layer and the substrate.5. The method of claim 4 , further comprising removing the backscatter layer.6. The method of claim 1 , further comprising:forming an intermediate active layer on a substrate of the wafer; anddirecting further radiation toward the wafer to anneal the intermediate active layer; forming the ...

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Номер записи: 75
17-01-2019 дата публикации

POWER MINIMIZING CONTROLLER FOR A STAGE ASSEMBLY

Номер: US20190020257A1
Автор: Binnard Michael B., Hemati Neyram
Принадлежит:

A method for moving a stage includes coupling a stage mover to the stage, and directing current to the stage mover with a control system. The stage mover includes a magnet array and a conductor array positioned adjacent to the magnet array. The conductor array includes a first layer of coils and a second layer of coils, with the first layer of coils being closer to the magnet array than the second layer of coils. The control system directs current to the first layer of coils and the second layer of coils independently. Further, the control system directs more current to the first layer of coils than the second layer of coils during a movement step to reduce the power consumption. 120-. (canceled)21. A method for moving a workpiece a movement step , the method comprising the steps of:coupling a stage mover to the workpiece, the stage mover including (i) a magnet array including a plurality of magnets that are positioned substantially adjacent to one another; and (ii) a conductor array positioned adjacent to the magnet array, the conductor array including a first layer of conductors and a second layer of conductors that is adjacent to the first layer of conductors, wherein the first layer of conductors is closer to the magnet array than the second layer of conductors, wherein the magnet array is positioned on one side of the conductor array, and wherein a first force constant of the first layer of conductors is larger than a second force constant of the second layer of conductors; anddirecting current to the first layer of conductors and the second layer of conductors independently with a control system, wherein the control system simultaneously directs a first current to the first layer of conductors and a second current to the second layer of conductors, and wherein the first current is greater than the second current during the movement step.22. The method of wherein the first layer of conductors is positioned in a stronger magnetic field than the second layer of ...

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Номер записи: 76
17-04-2014 дата публикации

BACK CONTACT SOLAR CELLS WITH EFFECTIVE AND EFFICIENT DESIGNS AND CORRESPONDING PATTERNING PROCESSES

Номер: US20140106551A1
Автор: Hieslmair Henry, PAKALA Neeraj, Srinivasan Uma, ZHOU Xin
Принадлежит: NanoGram Corporation

Laser based processes are used alone or in combination to effectively process doped domains for semiconductors and/or current harvesting structures. For example, dopants can be driven into a silicon/germanium semiconductor layer from a bare silicon/germanium surface using a laser beam. Deep contacts have been found to be effective for producing efficient solar cells. Dielectric layers can be effectively patterned to provide for selected contact between the current collectors and the doped domains along the semiconductor surface. Rapid processing approaches are suitable for efficient production processes. 1. A method for doping a semiconductor along a selected pattern , the method comprising:pulsing an energy beam at a first plurality of selected locations along a surface to drive a first dopant from a first dopant source into a semiconductor layer at the first plurality of selected locations to form a first doped domain comprising a stripe having a ratio of the average length that is at least about a factor of 10 greater than the average width.2. The method of wherein the first dopant source comprises doped silicon particles comprising the first dopant and wherein the pulsing the energy beam comprises driving the first dopant from the doped silicon particles into the semiconductor layer.3. The method of wherein the first dopant source comprises doped silicon particles having a first dopant concentration of from about 1×10atoms per cubic centimeter to about 5×10atoms per cubic centimeter.4. The method of wherein the first dopant source is selected from the group consisting of As claim 1 , Sb claim 1 , P claim 1 , or combinations thereof.5. The method of wherein the first dopant is selected from the group consisting of B claim 1 , Al claim 1 , Ga claim 1 , In or combinations thereof.6. The method of wherein the energy beam comprises a light beam having a wavelength from about 600 nm to about 5 microns and wherein the pulses have an energy density from about 0.25 J/ ...

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Номер записи: 77
28-01-2016 дата публикации

Shielded sockets for microprocessors and fabrication thereof by overmolding and plating

Номер: US20160028203A1
Автор: Gaurav Chawla, Joshua D. Heppner
Принадлежит: Individual

Shielded sockets for microprocessors and fabrication of shielded sockets by overmolding and plating techniques are described. In an example, a socket for a packaged semiconductor device includes a plastic housing having walls surrounding a cavity. A plurality of contact strips is disposed in the cavity and supported by one or more of the walls of the plastic housing. Each of the plurality of contact strips includes a plurality of contacts. Each of the plurality of contacts includes a vertical region overmolded with plastic, a contact portion, and a J-lead portion. The plastic is coated with a metal layer.

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Номер записи: 78
25-01-2018 дата публикации

Transistor with contacted deep well region

Номер: US20180026115A1
Автор: George IMTHURN
Принадлежит: Silanna Asia Pte Ltd

Various methods and devices that involve body contacted transistors are disclosed. An exemplary method comprises forming a gate on a planar surface of a semiconductor wafer. The gate covers a channel of a first conductivity type that is opposite to a second conductivity type. The method also comprises implanting a body dose of dopants on a source side of the gate using the gate to mask the body dose of dopants. The body dose of dopants spreads underneath the channel to form a deep well. The body dose of dopants has the first conductivity type. The method also comprises implanting, subsequent to implanting the body dose of dopants, a source dose of dopants on the source side of the gate to form a source. The method also comprises forming a source contact that is in contact with the deep well at the planar surface of the semiconductor wafer.

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Номер записи: 79
29-01-2015 дата публикации

Flexible composite, production thereof and use thereof

Номер: US20150029681A1
Автор: Anil K. SAXENA, Bjoern Borup, Helmut Mack, Philipp Albert
Принадлежит: Evonik Industries AG

A flexible composite comprising a plastic foil, having an upper and a lower surface, and at least one dielectric barrier layer against gases and liquids which is applied directly to at least one of the surfaces by plasma-enhanced thermal vapor deposition and comprises an inorganic vapor-depositable material, is provided. The flexible composite can be used for constructing flexible circuits or displays and has a high barrier effect with regard to oxygen and/or water vapor.

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Номер записи: 80
02-02-2017 дата публикации

Semiconductor device and a method of manufacturing the same

Номер: US20170033052A1
Автор: Masami Koketsu, Toshiaki Sawada
Принадлежит: Renesas Electronics Corp

To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P 1 a is formed in the same layer as that of a second layer wiring and the pattern P 1 b is formed in the same layer as that of a first layer wiring. Further, the pattern P 2 is formed in the same layer as that of a gate electrode, and the pattern P 3 is formed in the same layer as that of an element isolation region.

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Номер записи: 81
02-02-2017 дата публикации

Detecting heater failure in a group of electric heaters in a process equipment heating system

Номер: US20170034874A1
Автор: Brent Haslett, Brett Trevor Lawrence, Budd Edward Faulkner, Craig Richard Charles Turner, Mark Kollin Romeo, Matthew Demian Klepp, Nicholas Daniel Hutton, Peter George Stammers
Принадлежит: Edwards Vacuum LLC

A process equipment heating system has a group of electric heaters and a heater checking system. The heater checking system is configured to determine a resistance value R 1 for the group of electric heaters, compare the resistance value R 1 with a reference resistance value R R and judge a fault condition if the resistance value R 1 differs from the reference resistance value R R by more than a predetermined amount.

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Номер записи: 82
01-05-2014 дата публикации

INORGANIC PHOSPHATE CONTAINING DOPING COMPOSITIONS

Номер: US20140120705A1
Автор: Rogojina Elena
Принадлежит:

A composition for doping semiconductor materials, such as silicon, may contain a) a solvent and a) an inorganic salt of a phosphor containing acid dispersed in the solvent. Also disclosed are doping methods using such composition as well as methods of making the doping composition. 1. A semiconductor doping method comprising:(A) obtaining a substrate comprising a semiconductor material and(B) contacting at least a portion of a surface of the substrate with an effective amount of a doping composition comprising a) a solvent and b) an inorganic salt of a phosphor containing acid dispersed in said solvent.2. The method of claim 1 , wherein the substrate comprises silicon.3. The method of claim 1 , wherein the phosphor containing acid is an orthophosphoric acid.4. The method of claim 1 , wherein the phosphor containing acid is a metaphosphoric acid.5. The method of claim 1 , wherein the phosphor containing acid is a pyrophosphoric acid.6. The method of claim 1 , wherein the salt is a metal salt of the phosphor containing acid.7. The method of claim 1 , wherein the salt is an acid salt of the phosphor containing acid.8. The method of claim 1 , wherein the salt is selected from the group consisting of Al(HPO) claim 1 , Al(PO) claim 1 , Ca(PO) claim 1 , CaHPO claim 1 , Ca(HPO) claim 1 , CaPO claim 1 , MgHPO claim 1 , Mg(PO) claim 1 , Zr(HPO) claim 1 , NaPOand combinations thereof.9. The method of claim 1 , wherein the doping composition is a non-Newtonian fluid.10. The method of claim 1 , wherein the doping composition does not comprise a phosphor-containing acid or a phosphorous oxide.11. The method of claim 1 , wherein the solvent is an organic solvent.12. The method of claim 1 , wherein the solvent is selected from the group consisting of alcohols claim 1 , aldehydes claim 1 , ketones claim 1 , carboxylic acids claim 1 , esters claim 1 , amines claim 1 , organosiloxanes claim 1 , halogenated hydrocarbons claim 1 , hydrocarbons and combinations thereof.13. The method of ...

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Номер записи: 83
12-02-2015 дата публикации

Helium Management Control System

Номер: US20150040596A1
Автор: Allen J. Bartlett, Bruce R. Andeen, Gary S. Ash, Joseph Chopy, Jr., Paul E. Dresens, Y. Roberto Than
Принадлежит: Brooks Automation Inc

A helium management control system for controlling the helium refrigerant supply from a common manifold supplies cryogenic refrigerators with an appropriate helium supply. The system employs sensors to monitor and regulate the overall refrigerant supply. An appropriate supply of helium is distributed to each cryopump. If the total refrigeration supply exceeds the demand, or consumption, excess refrigerant is directed to cryogenic refrigerators which can utilize the excess helium to complete a current cooling function more quickly. If the total refrigeration demand exceeds the total refrigeration supply, the refrigerant supply to some or all of the cryogenic refrigerators will be reduced accordingly so that detrimental or slowing effects are minimized based upon the current cooling function.

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Номер записи: 84
12-02-2015 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20150041892A1
Автор: Hebert Francois, KIM Kwangil, Kim Youngbae, KIM Youngju, MOON Jinwoo, OH Intaek, Sun I-Shan
Принадлежит: MAGNACHIP SEMICONDUCTOR, LTD.

There are provided a semiconductor device and a method of manufacturing the same. The semiconductor device includes a source region disposed apart from a drain region, a first body region surrounding the source region, a deep well region disposed below the drain region, and a second body region disposed below the first body region. A bottom surface of the second body region is not coplanar with a bottom surface of the deep well region, and the first body region has a different conductivity type from the second body region. 1. A semiconductor device comprising:a source region disposed apart from a drain region;a first body region surrounding the source region;a deep well region disposed below the drain region; anda second body region disposed below the first body region,wherein a bottom surface of the second body region is not coplanar with a bottom surface of the deep well region; andthe first body region has a different conductivity type from the second body region.2. The semiconductor device according to claim 1 , wherein the source region and the drain region are disposed in a substrate.3. The semiconductor device according to claim 1 , wherein the second body region has a shallower depth than the deep well region.4. The semiconductor device according to claim 1 , wherein the deep well region has an impurity concentration that is different from an impurity concentration of the second body region.5. The semiconductor device according to claim 1 , wherein the second body region has an impurity concentration that is lower than an impurity concentration of the deep well region.6. The semiconductor device according to claim 1 , wherein at least one dip is disposed at the bottom surface of the second body region.7. A semiconductor device comprising:a body region disposed in a substrate and surrounding a source region; anda deep well region disposed in the substrate and surrounding the body region and a drain region,wherein a depth of a portion of the deep well region ...

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Номер записи: 85
12-02-2015 дата публикации

Semiconductor Device with Cell Trench Structures and Contacts and Method of Manufacturing a Semiconductor Device

Номер: US20150041962A1
Автор: Cotorogea Maria, Griebl Erich, Haghofer Andreas, Itani Haybat, Laven Johannes Georg, Schulze Hans-Joachim
Принадлежит:

First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width. 1. A method of manufacturing a semiconductor device , the method comprising:providing first and second cell trench structures extending from a first surface into a semiconductor portion, wherein the first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures;providing a capping layer covering the first surface;patterning the capping layer to form an opening having a minimum width larger than a thickness of the first insulator layer, the opening exposing a first vertical section of the first insulator layer at the first surface;removing an exposed portion of the first insulator layer to form a recess between the semiconductor mesa and the first buried electrode; andproviding a contact structure in the recess and the opening.2. The method of claim 1 , further comprising forming claim 1 , in the semiconductor mesa claim 1 , a source zone of a first conductivity type along the first surface and a body zone ...

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Номер записи: 86
12-02-2015 дата публикации

Power Semiconductor Device and Method

Номер: US20150041965A1
Автор: Hirler Franz, Mauder Anton, Schulze Hans-Joachim
Принадлежит:

A power semiconductor device includes a semiconductor body having a first side, a second side opposite the first side and an outer rim. The semiconductor body includes an active region, an edge termination region arranged between the active region and the outer rim, a first doping region in the active region and connected to a first electrode arranged on the first side, a second doping region in the active region and the edge termination region and connected to a second electrode arranged on the second side, a drift region between the first doping region and the second doping region, the drift region including a first portion adjacent to the first side and a second portion arranged between the first portion and the second doping region, and an insulating region arranged in the edge termination region between the second doping region and the first portion of the drift region. 1. A power semiconductor device , comprising: a first doping region in the active region and connected to a first electrode arranged on the first side of the semiconductor body;', 'a second doping region in the active region and the edge termination region and connected to a second electrode arranged on the second side of the semiconductor body;', 'a drift region between the first doping region and the second doping region, the drift region comprising a first portion adjacent to the first side of the semiconductor body and a second portion arranged between the first portion and the second doping region; and', 'an insulating region arranged in the edge termination region between the second doping region and the first portion of the drift region., 'a semiconductor body having a first side, a second side opposite the first side and an outer rim, the semiconductor body comprising an active region and an edge termination region arranged between the active region and the outer rim, the semiconductor body further comprising2. The power semiconductor device of claim 1 , wherein the insulating region ...

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Номер записи: 87
06-02-2020 дата публикации

Test Key Design to Enable X-Ray Scatterometry Measurement

Номер: US20200037979A1
Автор: Ferng Shyh-Shin, Huang Chung-Li, Lin Yi-Hung, Wang Chungwei
Принадлежит:

A method includes forming a test key. The formation of the test key includes forming a first plurality of semiconductor strips, and cutting the first plurality of semiconductor strips into an array of a second plurality semiconductor strips, with each row of the array being formed from one strip in the first plurality of semiconductor strips, forming isolation regions in recesses between the second plurality of semiconductor strips, and recessing the isolation regions. The top portions of the second plurality of semiconductor strips protrude higher than the isolation regions form semiconductor fins, which form a fin array. An X-ray beam is projected on the test key. A diffraction pattern is obtained from scattered X-ray beam scattered from the test key. 1. A method comprising: forming a first plurality of semiconductor strips;', 'forming isolation regions between the first plurality of semiconductor strips; and', 'recessing the isolation regions, wherein top portions of the first plurality of semiconductor strips protrude higher than the isolation regions to form semiconductor fins;, 'forming a test key comprisingprojecting an X-ray beam on the test key, wherein the X-ray beam has a spot size, and the test key is larger than the spot size; andobtaining a diffraction pattern from scattered X-ray beam scattered from the test key.2. The method of claim 1 , wherein the first plurality of semiconductor strips form an array claim 1 , with a portion of the array covered by the spot size comprising a plurality of rows and columns of the first plurality of semiconductor strips.3. The method of claim 1 , wherein the forming the test key further comprises:forming a second plurality of semiconductor strips; andcutting the second plurality of semiconductor strips into the first plurality of semiconductor strips, with each of the second plurality of semiconductor strips being cut into multiple semiconductor strips.4. The method of claim 1 , wherein the first plurality of ...

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Номер записи: 88
07-02-2019 дата публикации

PRODUCTION OF ROUNDED SALT PARTICLES

Номер: US20190039911A1
Автор: FLORES-PUJOL Alberto J., Schuessler David J.
Принадлежит:

The present disclosure generally relates to methods of preparing spherical salt particles for industrial, medical, and other uses. The methods can include combining the angular salt particles with a quantity of finishing media, for example, into a receptacle. Thereafter, the angular salt particles and the finishing media can be moved or agitated until the angular salt particles have a desired sphericity. 1. A method for producing rounded salt particles from angular salt particles , the method comprising combining the angular salt particles with a quantity of finishing media in a receptacle , and moving or agitating the angular salt particles and the finishing media until the angular salt particles have a sphericity of greater than about 0.75.2. The method of claim 1 , wherein the angular salt particles have a particle size in the range of about 100 to about 1200 μm.3. The method of claim 1 , wherein the angular salt particles are selected from the group consisting of sodium chloride claim 1 , potassium chloride claim 1 , calcium carbonate claim 1 , lithium chloride claim 1 , magnesium chloride claim 1 , calcium chloride claim 1 , ammonium chloride claim 1 , sodium iodide claim 1 , potassium iodide claim 1 , lithium iodide claim 1 , magnesium iodide claim 1 , calcium iodide claim 1 , ammonium iodide claim 1 , sodium bromide claim 1 , potassium bromide claim 1 , lithium bromide claim 1 , magnesium bromide claim 1 , calcium bromide claim 1 , ammonium bromide claim 1 , sodium carbonate claim 1 , potassium carbonate claim 1 , lithium carbonate claim 1 , magnesium carbonate claim 1 , ammonium carbonate claim 1 , sodium bicarbonate claim 1 , potassium bicarbonate claim 1 , lithium bicarbonate claim 1 , ammonium bicarbonate claim 1 , sodium nitrate claim 1 , potassium nitrate claim 1 , lithium nitrate claim 1 , magnesium nitrate claim 1 , calcium nitrate claim 1 , ammonium nitrate claim 1 , sodium acetate claim 1 , potassium acetate claim 1 , lithium acetate claim 1 , ...

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Номер записи: 89
08-02-2018 дата публикации

FINFET BASED DRIVER CIRCUIT

Номер: US20180041212A1
Автор: AGATA YASUHIRO, KOIKE TSUYOSHI, YAMAGAMI Yoshinobu
Принадлежит:

Disclosed herein is a driver circuit including a first group of transistors provided between first and second nodes and including n of the transistor(s) where n is equal to or greater than one, and a second group of transistors provided in parallel with the first group of transistors and including m of the transistor(s) where m is equal to or greater than one and not equal to n, the m transistors being connected together in series. The n-channel transistor in the first group and at least one of the two n-channel transistors in the second group have their gate connected to an input node. 119-. (canceled)20. A semiconductor integrated circuit connected to an input node and first and second nodes , wherein:the semiconductor integrated circuit has a plurality of transistors, each of which has a first channel conductivity type and which are configured as fin transistors having the same gate length and the same gate width, a first group of transistor(s) provided between the first and second nodes and including n transistor(s) where n is an integer equal to or greater than one, the n transistor(s) being connected together in series; and', 'a second group of transistor(s) provided between the first and second nodes in parallel with the first group of transistor(s) and including m transistor(s) where m is an integer equal to or greater than one and not equal to n, the m transistor(s) being connected together in series, and, 'the plurality of transistors comprisesall of the n transistor(s) in the first group of transistor(s) and all of the m transistor(s) in the second group of transistor(s) have their gate connected to the input node.21. The semiconductor integrated circuit of claim 20 , wherein the plurality of transistors further comprises:a third group of transistor(s) provided in parallel with the first group of transistor(s) between the first and second nodes and including n transistor(s) connected together in series.22. The semiconductor integrated circuit of claim 21 ...

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Номер записи: 90
19-02-2015 дата публикации

Controlling the melt front of thin film applications

Номер: US20150047781A1
Автор: John A. Ott, Stephen W. Bedell
Принадлежит: International Business Machines Corp

Systems and methods for bonding include selectively heating an initial location of a sample to melt a bonding layer at an interface between a first layer and a second layer of the sample. The heating is propagated in a direction away from the initial location such that a melt front of the bonding layer is translated across the interface to provide a void free bond between the first layer and the second layer.

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Номер записи: 91
15-02-2018 дата публикации

LITHIUM TANTALATE SINGLE CRYSTAL SUBSTRATE, BONDED SUBSTRATE, MANUFACTURING METHOD OF THE BONDED SUBSTRATE, AND SURFACE ACOUSTIC WAVE DEVICE USING THE BONDED SUBSTRATE

Номер: US20180048283A1
Автор: ABE Jun, Kato Koji, KUWABARA Yoshinori, Nagata Kazutoshi, TANNO Masayuki
Принадлежит: SHIN-ETSU CHEMICAL CO., LTD.

The lithium tantalate single crystal substrate is a rotated Y-cut LiTaOsingle crystal substrate having a crystal orientation of 36° Y-49° Y cut characterized in that: the substrate is diffused with Li from its surface into its depth such that it has a Li concentration profile showing a difference in the Li concentration between the substrate surface and the depth of the substrate; and the substrate is treated with single polarization treatment so that the Li concentration is substantially uniform from the substrate surface to a depth which is equivalent to 5-15 times the wavelength of either a surface acoustic wave or a leaky surface acoustic wave propagating in the LiTaOsubstrate surface. 1. A method of manufacturing a bonded substrate , comprising:{'sub': '3', "bonding a base substrate to a LiTaOsingle crystal substrate which has a concentration profile wherein Li concentration is different between a substrate surface and an inner part of the substrate and wherein Li concentration is substantially uniform in a region ranging from at least one of the substrate's surfaces to a depth; and"}{'sub': '3', 'removing a LiTaOsurface layer opposite the bonding face in a manner such that at least part of said region where the Li concentration is substantially uniform is left.'}2. A method of manufacturing a bonded substrate , comprising:{'sub': '3', "bonding a base substrate to a LiTaOsingle crystal substrate which has a concentration profile wherein Li concentration is different between a substrate surface and an inner part of the substrate and wherein Li concentration is substantially uniform in a region ranging from at least one of the substrate's surfaces to a depth and"}{'sub': '3', 'removing a LiTaOsurface layer opposite the bonding face in a manner such that only said region where the Li concentration is substantially uniform is left.'}3. The method of manufacturing a bonded substrate as claimed in claim 2 , wherein that region in which the Li concentration is ...

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Номер записи: 92
22-02-2018 дата публикации

SIGNAL RELAY BOARD FOR POWER SEMICONDUCTOR MODULES

Номер: US20180053654A1
Автор: KUBOUCHI Motoyoshi, Makino Ryohei, TAKAHASHI Kiyoshi
Принадлежит: FUJI ELECTRIC CO., LTD.

Signal relay board for power semiconductor modules enabling electrical connection between power semiconductor modules and a drive unit driving same. A first wire layer, a second wire layer, a third wire layer, and a fourth wire layer of a multiphase wire portion are assigned with a first control wire layer serving as a path to provide a control signal to a first semiconductor device of the modules, a first ground wire layer serving as a path to provide a ground potential to a low potential side terminal of the first semiconductor device of the semiconductor modules, a second control wire layer serving as a path to provide a control signal to a second semiconductor device of the modules, and a second ground wire layer serving as a path to provide a ground potential to the second semiconductor device of the modules. 1. A signal relay board for power semiconductor modules configured to provide connection between a plurality of power semiconductor modules which houses a first semiconductor device and a second semiconductor device connected in series and a drive unit which drives the first semiconductor device and the second semiconductor device , the signal relay board for power semiconductor modules comprising:a multiphase wire portion in which a first wire layer, a second wire layer, a third wire layer, and a fourth wire layer are stacked in this order, wherein the first wire layer, the second wire layer, the third wire layer, and the fourth wire layer are respectively assigned with a first control wire layer which serves as a path to provide a control signal to the first semiconductor device of the plurality of power semiconductor modules, a first ground wire layer which serves as a path to provide a ground potential to a low potential side terminal of the first semiconductor device of the plurality of power semiconductor modules, a second control wire layer which serves as a path to provide a control signal to the second semiconductor device of the plurality of ...

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Номер записи: 93
05-03-2015 дата публикации

Semiconductor device having silicide on gate sidewalls in isolation regions

Номер: US20150061039A1
Автор: Hoon Lim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Provided are a semiconductor device and a method of fabricating the same. According to the semiconductor device, a silicide layer is formed on at least a part of both sidewalls of a gate pattern on a device isolation layer, thereby reducing resistance of the gate pattern. This makes an operation speed of the device rapid. According to the method of the semiconductor device, a sidewall spacer pattern is formed on at least a part of both sidewalls of the gate pattern in following salicide process by entirely or partially removing remaining portions of the sidewall spacer except for portions which are used as an ion implantation mask to form source/drain regions. This can reduce resistance of the gate pattern, thereby fabricating a semiconductor device with a rapid operation speed.

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Номер записи: 94
03-03-2016 дата публикации

Pressure sensor including deformable pressure vessel(s)

Номер: US20160061679A1
Автор: Charles W. Blackmer, Kristin J. Lynch, Scott G. Adams
Принадлежит: Kionix Inc

Techniques are described herein that perform pressure sensing using pressure sensor(s) that include deformable pressure vessel(s). A pressure vessel is an object that has a cross section that defines a void. A deformable pressure vessel is a pressure vessel that has at least one curved portion that is configured to structurally deform (e.g., bend, shear, elongate, etc.) based on a pressure difference between a cavity pressure in a cavity in which at least a portion of the pressure vessel is suspended and a vessel pressure in the pressure vessel.

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Номер записи: 95
22-05-2014 дата публикации

HYBRID TRANSFORMER STRUCTURE ON SEMICONDUCTOR DEVICES

Номер: US20140138792A1
Автор: Kim Jonghae, Lan Je-Hsiung, Lo Chi Shun, Velez Mario Francisco
Принадлежит: QUALCOMM INCORPORATED

Several novel features pertain to a hybrid transformer formed within a semiconductor die having multiple layers. The hybrid transformer includes a first set of windings positioned on a first layer of the die. The first layer is positioned above a substrate of the die. The first set of windings includes a first port and a second port. The first set of windings is arranged to operate as a first inductor. The hybrid transformer includes a second set of windings positioned on a second layer of the die. The second layer is positioned above the substrate. The second set of windings includes a third port, a fourth port and a fifth port. The second set of windings is arranged to operate as a second inductor and a third inductor. The first set of windings and the second set of windings are arranged to operate as a vertical coupling hybrid transformer. 1. A hybrid transformer formed within a semiconductor die having multiple layers , the hybrid transformer comprising:a first set of windings positioned on at least a first layer of the semiconductor die, the first layer positioned above a substrate of the semiconductor die, the first set of windings includes a first port and a second port, the first set of windings arranged to operate as a first inductor; anda second set of windings positioned on at least a second layer of the semiconductor die, the second layer positioned above the substrate, the second set of windings includes a third port, a fourth port and a fifth port, the second set of windings arranged to operate as a second inductor and a third inductor, wherein the semiconductor die includes a third layer and a fourth layer, the first set of windings being positioned on the first layer and on the third layer, the second set of windings being positioned on the second layer and on the fourth layer, and wherein the first set of windings and the second set of windings are arranged to operate as a vertical coupling hybrid transformer.2. The hybrid transformer of claim 1 , ...

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Номер записи: 96
22-05-2014 дата публикации

Strain relaxation using metal materials and related structures

Номер: US20140138796A1
Автор: Christiaan J. Werkhoven
Принадлежит: Soitec SA

Methods of fabricating semiconductor structures include forming a plurality of openings extending through a semiconductor material and at least partially through a metal material and deforming the metal material to relax a remaining portion of the semiconductor material. The metal material may be deformed by exposing the metal material to a temperature sufficient to alter (i.e., increase) its ductility. The metal material may be formed from one or more of hafnium, zirconium, yttrium, and a metallic glass. Another semiconductor material may be deposited over the remaining portions of the semiconductor material, and a portion of the metal material may be removed from between each of the remaining portions of the semiconductor material. Semiconductor structures may be formed using such methods.

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Номер записи: 97
08-03-2018 дата публикации

PECVD PROCESS

Номер: US20180066364A1
Автор: AYOUB Mohamad A., Balasubramanian Ganesh, BANSAL Amit Kumar, BUDIARTO Edward, Chen Jian J., Egan Todd, HAN Xinhai, Jiang Zhijun, Kim Bok Hoen, LEE Jeongmin, Lee Terrance Y., Nowak Thomas, Ogata Masaki, PANASYUK Dmitriy, PARK Heung Lak, Rajagopalan Nagarajan, REILLY Patrick, Rocha-Alvarez Juan Carlos, Sankarakrishnan Ramprakash, SHAIKH Shahid, STARIK Sergey, TSIANG Michael Wenyoung, ZHOU Jianhua
Принадлежит:

A method of processing a substrate according to a PECVD process is described. Temperature profile of the substrate is adjusted to change deposition rate profile across the substrate. Plasma density profile is adjusted to change deposition rate profile across the substrate. Chamber surfaces exposed to the plasma are heated to improve plasma density uniformity and reduce formation of low quality deposits on chamber surfaces. In situ metrology may be used to monitor progress of a deposition process and trigger control actions involving substrate temperature profile, plasma density profile, pressure, temperature, and flow of reactants. 1. A method , comprising:disposing a substrate on a substrate support in a chamber;establishing a temperature profile in the substrate;controlling a temperature of a face plate of the chamber, wherein the face plate faces the substrate support, and wherein a processing region is between the face plate and the substrate support;flowing a precursor gas mixture into the chamber;forming a plasma in the chamber;adjusting a density profile of the plasma; andforming a layer of uniform thickness on the substrate.2. The method of claim 1 , wherein the layer is of uniform composition.3. The method of claim 1 , wherein controlling the temperature of the face plate promotes temperature uniformity in the processing region.4. The method of claim 1 , wherein flowing the precursor gas mixture comprises providing the precursor gas mixture to the processing region through the face plate.5. The method of claim 1 , wherein adjusting the density profile of the plasma comprises biasing an electrode coupled to at least one of:a side wall of the chamber, andthe substrate support.6. The method of claim 1 , further comprising:flowing a second precursor gas mixture into the chamber; andforming a second layer of uniform thickness to form a stack.7. The method of claim 6 , wherein a structure of the stack is substantially planar claim 6 , laminar claim 6 , and ...

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Номер записи: 98
17-03-2022 дата публикации

Leak detection apparatus and method and wafer electroplating method

Номер: US20220084855A1
Автор: Dongjin Kim
Принадлежит: Changxin Memory Technologies Inc

A leak detection apparatus and method and a wafer electroplating method are provided. An air tightness state of a reaction chamber in a wafer electroplating device is detected in advance before a wafer electroplating process is performed, namely whether leak occurs at the reaction chamber is judged by inputting a detection gas to the reaction chamber and detecting a gas pressure value of the detection gas, and whether to perform the wafer electroplating process is determined according to a judgment result.

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Номер записи: 99
08-03-2018 дата публикации

Diamond Semiconductor System and Method

Номер: US20180068853A1
Автор: Khan Adam
Принадлежит:

Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The system may include a diamond material having n-type donor atoms and a diamond lattice, wherein 0.16% of the donor atoms contribute conduction electrons with mobility greater than 770 cm2/Vs to the diamond lattice at 100 kPa and 300K. The method of fabricating diamond semiconductors may include the steps of selecting a diamond material having a diamond lattice; introducing a minimal amount of acceptor dopant atoms to the diamond lattice to create ion tracks; introducing substitutional dopant atoms to the diamond lattice through the ion tracks; and annealing the diamond lattice. 1. (canceled)2. (canceled)3. (canceled)4. (canceled)5. A method of fabricating diamond semiconductors , the method including the steps of:selecting a diamond material having a diamond lattice, forming a diamond layer on a silicon dioxide layer;introducing acceptor dopant atoms to the diamond lattice to create pathways;introducing substitutional dopant atoms to the diamond lattice through the pathways; andannealing the diamond lattice to remove the pathways;{'sup': 22', '3, 'wherein the introduction of the acceptor dopant atoms does not create a critical density of more than 10/cmof vacancies in the diamond layer.'}6. The method of claim 5 , wherein the diamond material is intrinsic diamond.7. The method of claim 5 , wherein the acceptor dopant atoms are introduced at 293 to 298 degrees Kelvin.8. The method of claim 5 , wherein the acceptor dopant claim 5 , atoms are boron.9. The method of claim 5 , wherein the amount of acceptor dopant atoms is between 5×10/cmand 5×10/cm.10. The method of claim 5 , wherein the substitutional dopant atoms are introduced at or below 78 degrees Kelvin.11. The method of claim 5 , wherein the substitutional dopant atoms are introduced at less than 500 keV.12. The method of claim 5 , wherein the substitutional dopant atoms are introduced at less than 140 keV and at a ...

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Номер записи: 100