ИСТОЧНИК ОПОРНОГО НАПРЯЖЕНИЯ С КАЛИБРОВКОЙ ВЫХОДНОГО НАПРЯЖЕНИЯ

Полезная модель относится к области электротехники. Техническим результатом полезной модели является создание источника опорного напряжения с калибровкой выходного напряжения с улучшенными эксплуатационными характеристиками, а именно со стабильным выходным напряжением Vout после калибровки и автоматическим процессом подстройки регулируемых элементов, за счет наличия схемы смещения базы биполярных транзисторов BJT1 и BJT2, состоящей из блока управления температурным коэффициентом (CTK - Control block temperature coefficient), осуществляющим преобразование цифрового кода в температурный коэффициент выходного тока, и нагрузочного резистора Rt, подключенного между эмиттером и коллектором биполярных транзисторов BJT1 и BJT2, а также за счет наличия источника тока, управляемого напряжением (OTA_TR - Operational Transconductance Amplifier) с подстройкой смещения, выполняемой блоком управления напряжением смещения CVOS (Control block offset voltage), входящим в состав источника тока, управляемого ...

ИСТОЧНИК ОПОРНОГО НАПРЯЖЕНИЯ

Использование: в микроэлектронике. Сущность изобретения: устройство содержит три p-канальных 2, 3, 5 и три n-канальных МОП-транзистора 1, 4, 6. Выходное напряжение V1 формируется на транзисторе 2 в диодном включении относительно шины 8 отрицательного напряжения. Аналогичное выходное напряжение V2 формируется на транзисторе 4. Оно стабилизировано относительно шины 7 положительного напряжения. По сравнению с прототипом температурная стабильность выходного напряжения повышена в 5 раз. 1 з.п. ф-лы, 1 ил.

ИСТОЧНИК ПОСТОЯННОГО ТОКА С ЭЛЕКТРОННО-СТИРАЕМОЙ ПРОГРАММИРУЕМОЙ ПОСТОЯННОЙ ЯЧЕЙКОЙ ПАМЯТИ (EEPROM)

... 1. Источник постоянного тока с полевым МОП-транзистором, вывод стока (D) которого соединен с первым выводом источника тока и вывод истока (S) и вывод управляющего затвора (SG) которого соединены со вторым выводом источника тока, отличающийся тем, что между управляющим затвором (SG) и каналом (K) полевого транзистора расположен плавающий затвор (FG) с зарядом носителя заряда типа, противоположного типу канала полевого транзистора. 2. Источник постоянного тока по п. 1, отличающийся тем, что полевой транзистор для нанесения заряда на плавающий затвор является соединяемым с высоковольтным источником и отделяемым от подлежащей питанию нагрузки. 3. Источник постоянного тока по п.1 или 2, отличающийся тем, что между выводом истока полевого транзистора и вторым выводом источника тока включен резистор.

Источник опорного напряжения

Изобретение относится к электротехнике и может найти применение в устр-вах вторичного электропитания радиоэлектронной аппаратуры. Цель изобретения - повышение температурной стабильности выходного напряжения и нагрузочной способности. Устр-во содержит первый 1 и второй 2 МОП-транзисторы одного типл проводимости, третий 3 и четвертый 4 МОП-транзисторы нротивоположного гяпа проводимости , резистор 5, а также дополни- тельньп пятый МОП-транзист 1ры 8, про водимость которого аналогична первому и второму. Цель достигается за счет протекания одинаковых токов через транзисторы, а также введения дополнительного транзистора, осуществляющего регулирование выходного напряжения. 1 ил. С 3 (/) ...

Spannungsreferenzschaltung

Integrierte Schaltung mit einer Einheit zur Regelung einer Belastung mit einem induktiven Charakter

Halbleiteranordnung und Schaltung, geeignet für die Verwendung in intelligenten Leistungsschaltern

REGULATED SUBSTRATE VOLTAGE GENERATOR

Spannungsgenerator

Ein Spannungsgeneratorschaltkreis kann so strukturiert sein, dass er eine Ausgangsspannung mit einem im Wesentlichen flachen Temperaturkoeffizienten durch Verwenden einer Schaltkreisschleife mit Transistoren und einem Widerstand derart angeordnet bereitstellt, dass im Betrieb ein Strom durch den Widerstand einen vorzeichenbehafteten Temperaturkoeffizienten hat. Das Stromverhalten kann durch einen Ausgangstransistor gesteuert werden, der mit einem anderen Transistor gekoppelt ist, der mit der Schaltkreisschleife gekoppelt ist, wobei dieser andere Transistor so bemessen ist, dass im Betrieb eine Spannung dieses anderen Transistors einen vorzeichenbehafteten Temperaturkoeffizienten hat, der in Bezug auf das Vorzeichen entgegengesetzt zu dem vorzeichenbehafteten Temperaturkoeffizienten des Stroms durch den Widerstand ist. Ausführungsformen eines Spannungsgeneratorschaltkreises können auch zusätzliche Komponenten aufweisen, um eine Ausgangsspannung zu trimmen, eine bedingungslose Stabilität ...

Impulssignalgenerator und Redundanzauswahlsignalgenerator.

Referenzspannungsgenerator für dynamischen Specher mit wahlfreien Zugriff

Leistungshalbleiter mit Strombegrenzung

STROMQUELLE MIT NIEDRIGEM TEMPERATURKOEFFIZIENT.

Interne Spannungsgeneratorschaltung

... ndash; einem Spannungsteiler (140), der dafür ausgelegt ist, einen Pegel einer internen Spannung (IVC) zu teilen, sodass eine geteilte interne Spannung (DIV_IVC) erzeugt wird; einem Komparator (610), der mit einer externen Spannung (EXT_VDD) als einer Eingangsspannung und mit der internen Spannung (IVC) als einer weiteren Eingangsspannung verbunden und dafür ausgelegt ist, die geteilte interne Spannung (DIV_IVC) mit einer Referenzspannung (VREF) zu vergleichen und ein Vergleichsausgangssignal (DA_OUT) zu erzeugen und an einem Ausgang bereitzustellen sowie an einem Knoten (A) die höhere der beiden Eingangsspannungen bereitzustellen und zur Bereitstellung eines hohen Spannungspegels des Vergleichsausgangssignals (DA_OUT) abhängig vom Vergleich der geteilten internen Spannung (DIV_IVC) mit der Referenzspannung (VREF) den Ausgang mit diesem Knoten (A) zu verbinden, und einem Treiber (620), der das Vergleichsausgangssignal (DA_OUT) des Komparators (610) empfängt und dafür ausgelegt ist, die ...

KOMPENSATIONSNETZWERK FÜR ABSCHNÜRSPANNUNGSSENSITIVE SCHALTUNGEN

Current-controlled current switch stage for digital circuit

The current switch stage (or current-controlled current node logic circuit) has at least one low impedance transimpedance stage (1). The latter includes an input (3) connected to the current switching stage, and converts an input signal to the current switching stage into an input voltage. The transimpedance stage provides an intermediate voltage at its output. A high impedance transconductance stage is connected after the transimpedance stage. The transconductance stage is connected to the output of the current switch stage, and converts the intermediate voltage to an output current, which is accessible at the output (4) of the current switching stage.

Schaltungsanordnung zum Erzeugen eines Widerstandsverhaltens mit einstellbarem positiven Temperaturkoeffizienten, sowie Verwendung dieser Schaltungsanordnung

Constant voltage supply system - uses MOS devices coupled in stabilising chain for high performance

A highly accurate and stable voltage supply is provided using MOS devices for digital circuit applications. The first stabilising stage consists of an MOSFET in series with a resistor (R1) and coupled to the supply voltage (VD). Further stabilising stages are provided with an MOSFET (T3) controlled by the output of the first stage (V1) over a second transistor (T2). The two transistors (T2, T3) are complimentary. Additional stabilising stages (T4, T5), (T6, T7) provide the level of performance required.

Ladungspumpenschaltung, insbesondere für eine elektrische Phasenregelschleife

Ladungspumpenschaltung, insbesondere für eine Phasenregelschleife, aufweisend a) eine von ein em ersten digitalen Ansteuersignal (UP) schaltbare Stromquelleneinheit, welche bei Aktivierung durch das erste Ansteuersignal (UP) einen Strom definierter Stärke an einen Ausgang (CPout) der Ladungspumpenschaltung liefert, b) wobei die Stromquelleneinheit eine ersten einstellbare Konstantstromquelle (MPout, MPL) umfasst, welche im Strompfad vom positiveren Potential (VDD) der Versorgungsspannung der Ladungspumpenschaltung zum Ausgang (CPout) der Ladungspumpenschaltung liegt und so eingestellt ist, dass bei geschlossenem Strompfad der Strom definierter Stärke zum Ausgang (CPout) fließt, und c) wobei die Stromquelleneinheit einen ersten steuerbaren elektronischen Schalter (S2B) umfasst, welcher im Strompfad vom positiveren Potential (VDD) der Versorgungsspannung zum Ausgang (CPout) angeordnet ist und diesen abhängig vom ersten Ansteuersignal (UP) schaltet; d) eine von einem zweiten digitalen Ansteuersignal ...

SEMICONDUCTOR STRUCTURE HAVING A VOLTAGE LEVEL SHIFTER

Power supply device

CIRCUIT FOR GENERATING INTERNAL SUPPLY VOLTAGE

Negative voltage drive circuit

Circuit for generating reference voltage and reference current

Circuitry and semiconductor devices which can be implemented in gallium arsenide technology for generating a substantially constant reference voltage and for generating a substantially constant reference current are described. JFET transistors 80, 88 are connected in series and connected to the gate of JFET 96 in series with JFET 100. A variable resistor 98 and JFET 106 are coupled to a load 108. Transistors 80, 88 generate a constant voltage at mode B. Variable resistor 98 is constructed using a network of resistors connected by laser programmable fuses, allowing a desired overall resistance to be chosen.

Voltage-controlled current-circuit

A current-controlling circuit for producing either a constant current, independent of supply potential or a current which decreases with increasing supply potential and vice-versa. Three devices 12, 13, 14 are connected together at a point such that the current in the first device 12 and the current in the third device 14 form the current in the second device 13. The current flowing in first device 12 is a mirror of the current flowing in device 11. When the supply potential increases, the increase in current in the first device 12 at least equals the increase in current in the second device 13, so that the current in the third device 14 does not increase. If the current in the third device 14 decreases with increasing supply potential, it may be mirrored into subsequent devices 15,16 which may then pass a constant current. The circuit may include an amplifying current mirror 30, 31, 32, 33 so that any change in current flowing in the first device 12 is an amplified version of the change ...

Voltage reference circuit

A STABILIZED LOW DROPOUT VOLTAGE REGULATOR CIRCUIT

SEMICONDUCTOR TEMPRATURE DETECTING CIRCUIT.

A semiconductor temperature detecting circuit is provided having a plurality of pairs of a MOS transistor for supplying current and a polycrystalline silicon resistor connected in series thereto. Each such pair is connected in between a first and a second power supply line. The voltage across the terminals of each polycrystalline silicon resistor is converted to a digital logic value and the combination of all such digital outputs represents the detected temperature. Each current supply transistor has its gate electrode connected to a common circuit which sets the current supply. The current setting circuit includes two p-channel MOS transistors and two n-channel MOS transistors. Each p-channel transistor in the current setting circuit has a current electrode connected to one power supply line and another current electrode connected to a current electrode of a corresponding n-channel transistor. Each n-channel transistor has its other current electrode connected to the other power supply ...

Source voltage control circuit

There is provided a source voltage control circuit including a reference voltage generating circuit (70) with a negative feedback circuit, a source voltage level sensing circuit (90) for increasing the internal source voltage when the external voltage exceeds a given voltage, a first differential amplifying circuit (11) for active operation and a second differential amplifying circuit (130) for stand-by operation. whereby a stable internal source voltage (122) is produced and the slope of the internal source voltage is readily adjusted when the external source voltage exceeds the given value. The first differential amplifying circuit (110) receives the reference voltage and the internal source voltage, controlled by a first control signal and the output of the source voltage level sensing circuit (90). The second differential amplifying circuit (130) receives the reference voltage and the internal source voltage, controlled by a second control signal. ...

Circuit and method for regulating a voltage

Voltage reference circuit

The circuit is capable of providing threhold voltages with different temperature coefficients and includes two base-collector cross-coupled transistors Q 1 , Q 2 , one of which Q 2 has a K 1 times larger emitter area. Each transistor carries current from sources Q5, Q6 which are operated as current mirrors of reference transistor Q3. Q6 has K2 times the emitter area of Q3 and Q5. The drive current to Q2 is thus K2 times that to Q1. As the base of Q3 is connected to the collector of Q2, V1 and V2 are equal. The circuit arrangement is such that the reference voltages VREF1 and VREF2 are weighted sums of the respective transistor VBE and the difference between the two VBEs. Thus by choosing K1, K2, R1, R2 AND R3, the reference levels can be set to desired values. Since the temperature dependency of the VBE term is selected to be positive and that of the differential term to be negative, any desired temperature characteristic can be achieved. Similar embodiments using MOSFET transistors are ...

Output voltage controlling circuit in a negative charge pump

Voltage comparitors

A voltage comparitor or level detector comprises a differential amplifier the input terminals of which are formed by the gates of two IGFET's Q1, Q2 which have different threshold voltages due to the use of differently doped semiconductor material for their gate electrodes. This structure provides a stable input offset for the amplifier which is used as a reference. The input voltage and a reference level are applied to the input terminals and the output of the amplifier is determined by the difference between the input p.d. and the input offset. The values of the source currents I1, I2 may be adjusted to provide temperature compensation. In an alternative arrangement the input transistors Q1, Q2 are arranged in a common source configuration with constant current drain supplies. The arrangement may be used as a battery voltage level detector by applying the battery voltage (via a potential divider) to one input and a fixed level (e.g. VDD or VSS) to the other input. Circuits incorporating ...

Reference voltage generating circuit

A bandgap reference voltage source with high power supply rejection ratio

A bandgap reference voltage source comprises a band-gap core circuit, a pre-regulator circuit, a switch circuit and a start-up circuit. The start-up circuit, after being powered on, provides an initial bias current for the operational amplifier in the bandgap core circuit. The pre-regulator circuit provides a pre-regulated voltage for the bandgap reference core. A comparator judges the output state of the bandgap core circuit and selects, using a switch circuit, either the bandgap core circuit output VBG or the power supply partial voltage as the reference voltage of the pre-regulator circuit. Use of the pre regulator may increase the power supply rejection ratio of the bandgap reference voltage source.

VOLTAGE SOURCES

SEMICONDUCTOR DEVICE

REFERENCE VOLTAGE GENERATING CIRCUIT

DIFFERENITAL CURRENT SOURCE CIRCUIT USED IN DAC OF CURRENTDRIVING TYPE

Pulsed DC/DC voltage converter having little ripple in the input or output current

The invention relates to an apparatus for pulsed conversion of a DC voltage 4 to a load voltage which can be predetermined, is supported by a capacitor 8 and occurs between the terminals 5 and 6. The converter structure is formed by connecting an inductance 10, which is arranged on the input or output side, a centre inductance 12, electronic switching apparatuses 14 and 15 and a coupling capacitance 20. The arrangement of the switching elements according to the invention results in the voltage which occurs across the coupling capacitance always being equal to the sum of the input and output voltage of the converter in the steady state, so that (ideally) no difference voltage occurs across the inductance 10 irrespective of the switching state of the electronic switching apparatuses 14 and 15, and the converter system therefore has very little ripple in the input or output current. ...

SEMICONDUCTOR ARRANGEMENT.

CLOCKED DC VOLTAGE DC STATIC CONVERTER WITH SMALL RIPPLES OF THE INITIALLY OR OUTPUT CURRENT

SWITCHED POWER SOURCE.

SOURCE OF REFERENCE ON AN INTEGRATED FET COMPONENT AS WELL AS PROCEDURE FOR THE ENTERPRISE OF THE SOURCE OF REFERENCE.

PRE-LOADING CIRCUIT TO PRODUCTION OF SEVERAL PRE-LOADING

VOLTAGE CLAMPING CIRCUIT

Low power regenerative feedback device and method

Compensation network for pinch off sensitive circuits

REFERENCE VOLTAGE GENERATOR DEVICE

VOLTAGE CLAMPING CIRCUIT

CMOS VOLTAGE DIVIDER CIRCUITS

CMOS VOLTAGE DIVIDER CIRCUITS A CMOS fractional reference source or voltage divider circuit includes a string (chain) of CMOS pairs of transistors connected with their source-drain circuits in series and with ends of the string being connected across an input power (voltage) supply. The P-channel transistors are all matched to one another in a one to one ratio, the N-channel transistors are all similarly matched to one another. Output terminals are connected at the nodes between pairs of transistors. Accurate tracking of the voltage of the power supply is achieved by connecting each gate of the chain in a manner to insure the same source-to-gate voltage on each transistor of the pair. In the preferred form, the string comprises two pairs of CMOS transistors and the voltage appearing at the output terminal thereof is equal to one half of the voltage of the power supply.

CONSTANT CURRENT SUPPLY

CONSTANT CURRENT SUPPLY A first field-effect transistorized constant current supply provides a first relatively constant output current. A second field-effect transistorized constant current supply is cascaded with, and driven by, said first current to provide a more highly regulated second constant output current. The system is self-starting and latch free. The second output current may be employed to drive a current mirror with a plurality of output current paths.

SELF-REGULATING DRIVING CIRCUIT FOR LIGHT EMITTING DIODES

SELF-REGULATING DRIVING CIRCUIT FOR LIGHT-EMITTING DIODES A self-regulating circuit is disclosed for driving a load, such as an arithmetical calculator display using light-emitting diodes, directly from a single MOS calculator chip. A strobe driver, which may be a field effect transistor switch, has its gate electrode connected to a regulated supply of dc voltage, its drain electrode connected to a supply of voltage subject to variation, and its source electrode connected at a common point to one terminal of each of the light-emitting diodes of the display in order that the light-emitting diodes may be driven thereby. A second field effect transistor switch is also provided and has the conduction path thereof connected between the other terminal of a respective light-emitting diode and a reference potential, e.g. ground, to selectively complete a current path including the respective light-emitting diode. Hence, a light-emitting diode may be illuminated at a particular time and according ...

PROGRAMMABLE REFERENCE VOLTAGE GENERATOR FOR A READ ONLY MEMORY

INTEGRATED MOSFET RESISTANCE AND OSCILLATOR FREQUENCY CONTROL AND TRIM METHODS AND APPARATUS

BIAS VOLTAGE DISTRIBUTION SYSTEM

The present invention describes a bias potential distribution system which provides bias potentials to MOS devices while ensuring the devices' operating conditions remain constant over temperature, process, and power supply fluctuations. Further, bias potentials are generated at one main location within the logic circuit and then distributed throughout the logic circuit to all of the MOS devices or to bias voltage conversion circuits.

A METHOD AND DEVICE FOR TEMPERATURE DEPENDENT CURRENT GENERATION

Most temperature related reference generations are in the voltage domain, which means that reference voltages rather than reference currents are generated. In some applications such as driving laser diodes, currents are needed rather than voltages. In the present invention, as an alternative, the references are designed in the current domain, wherei n the operation philosophy can be said to be inverse to the operation philosophy of the prior art. The temperature dependence of the currents are known and the currents (1, 2) will be processed by linear and/or non linear operation to generate currents (3) with predetermin ed temperature coefficients. The advantages of the invention can be outlined as more straightforward, scaling and summation (subtraction) are much easier and simpler in the current domain than in the voltage domain.

DEVICE FOR COMPENSATING PROCESS AND OPERATING PARAMETER VARIATIONS IN CMOS INTEGRATED CIRCUITS

A device is provided for compensating process and operating parameters variations in a CMOS integrated circuit. The device comprises means for generating a first and a second compensation signals which depend on quality indexes of the fabrication process of the P and N transistors of the integrated circuit and on the operating temperature, and which are capable of compensating deviations of the controlled quantity from the desired value, due to the deviation of the quality indexes and temperature, respectively, from a typical value which would originate the desired value for the output parameter. The compensating device also can be implemented in the form of CMOS integrated circuit, preferably jointly with the device to be subjected to compensation.

CIRCUIT INTEGRE A SEMI-CONDUCTEUR CONSTITUANT UN CIRCUIT DETECTEUR DE TENSION.

BATTERIEGETRIEBENES ELEKTRONISCHES ZEITMESSGERAET.

Circuit arrangement for stabilising the feed voltage for at least one electronic circuit

SWITCHING CONFIGURATION IN INTEGRATED CMOS TECHNOLOGY FOR THE REGULATION OF THE SUPPLY VOLTAGE FOR A LOAD.

REFERENCE-VOLTAGE SOURCE MADE IN THE FORM OF AN INTEGRATED CIRCUIT WITH MOS TRANSISTORS.

TENSION MULTIPLICATION CIRCUIT.

REFERENCE-VOLTAGE SOURCE.

BATTERY-DRIVEN ELECTRONIC HOROLOGE.

INTEGRATED CIRCUIT HAS SEMICONDUCTOR CONSTITUTING A CIRCUIT TENSION DETECTOR.

Electronic reference-voltage generator circuit, voltage detector device employing this circuit

The circuit comprises two transistors (32, 33) including drains and sources (21-24) and isolated gates (34, 35) respectively having dopings suitable for setting up a threshold-voltage difference between these two transistors. The reference-voltage source thus obtained can easily be produced as an integrated circuit. The circuit is advantageously used in a battery-voltage detector device in an electronic watch. ...

Low power consumption electronic circuit

ELECTRONIC TIMEPIECE

REFERENCE TENSION PRODUCER.

Semiconductor device

REFERENCE TENSION PRODUCER.

REFERENCE TENSION PRODUCER.

VOLTAGE REGULATOR.

A method of generating a current substantially independent of the temperature and a device for carrying out said method.

Il est décrit un procédé ainsi qu'un dispositif de génération d'un courant (11) sensiblement indépendant en température. Pour produire ce courant (I1), on utilise un circuit générateur de courant conventionnel comportant un amplificateur opérationnel (11) commandant un transistor (12) ayant l'une (12a) de ses électrodes de courant (12a, 12b) connectée à une résistance (13) ainsi qu'à une borne d'entrée (11b) de l'amplificateur opérationnel (11).Selon l'invention, on applique une tension d'entrée (Vin) stable en température sur l'autre borne d'entrée (11a) de l'amplificateur opérationnel (11), et on agence ce dernier pour qu'il présente une tension d'offset (Vos(T)) entre ses bornes d'entrées (11a, 11b) ayant une dépendance en température, cette tension d'offset (Vos(T)) ainsi que la tension d'entrée (Vin) étant ajustées pour compenser la dépendance en température de la résistance (13) de telle sorte que le courant généré (I1) est sensiblement indépendant de la température.Selon l'invention ...

Reference voltage element

Resistorless bias current generation circuit

Low voltage following open loop voltage adjusting circuit

Reference voltage generating circuit and method, display drive circuit and display apparatus

Reference voltage generating circuit and internal voltage generating circuit for controlling internal voltage level

REFERENCE CURRENT GENERATING CIRCUIT

GENERATOR STABILIZES SUPPLY OF TENSION OF THRESHOLD OF TRANSISTOR MOS

Circuit for generating an internal voltage corresponding to an external voltage applied to a semiconductor chip

... a) circuit générateur de tension interne correspondant à une tension externe appliquée à une puce à semi-conducteur b) circuit générateur de tension interne caractérisé en ce qu'il comprend: un circuit de détection de tension externe (100) destiné à détecter la tension externe de manière à amener la tension interne au niveau de la tension externe appliquée lorsque cette tension externe dépasse une valeur donnée; un circuit de commande de pilote (200) branché entre le premier amplificateur différentiel (100A) et le circuit pilote de sortie pour commander le branchement électrique entre le signal de sortie du premier amplificateur différentiel et la borne de commande du circuit pilote (50) en réponse au signal de sortie du circuit de détection de tension externe (100).

GENERATOR OF TENSION OF REFERS AND MEASURING CIRCUIT OF the TENSION OF THRESHOLD Of a TRANSISTOR MOS, APPLICABLE THIS GENERATOR OF TENSION OF REFERS

CURRENT SOURCE

CIRCUIT REGULATEUR DE LA TENSION DE POLARISATION DU SUBSTRAT D'UN CIRCUIT INTEGRE A TRANSISTORS A EFFET DE CHAMP

CE CIRCUIT REGULATEUR COMPREND UN INVERSEUR FORME DE DEUX TRANSISTORS A APPAUVRISSEMENT T3, T4. L'ENTREE DE L'INVERSEUR 5, C'EST-A-DIRE L'ELECTRODE DE GRILLE DU TRANSISTOR ACTIF T3, EST RACCORDEE DIRECTEMENT AU SUBSTRAT DU CIRCUIT INTEGRE ET LA SORTIE 6 DE L'INVERSEUR EST RACCORDEE A LA BORNE DE COMMANDE DE L'OSCILLATEUR QUI ALIMENTE LE GENERATEUR DE CHARGES RACCORDE AU SUBSTRAT. LE FONCTIONNEMENT DE L'OSCILLATEUR EST INHIBE QUAND LA TENSION DU SUBSTRAT DEPASSE UN NIVEAU PREDEFINI.

Circuit de conversion de tension d'alimentation pour une mémoire à semiconducteurs à densité élevée

L'invention concerne la technologie des mémoires à semiconducteurs. Un circuit de conversion de tension d'alimentation pour une mémoire comprend notamment un générateur de tension de référence 40, un circuit d'alimentation de circuits périphériques 20P et un circuit d'alimentation de circuits de réseau 20A, qui alimentent respectivement les circuits périphériques et les circuits de réseau de la mémoire. Chaque circuit d'alimentation comprend un diviseur qui produit une tension proportionnelle à la tension d'alimentation interne, un élément d'alimentation principal 22M et un élément d'alimentation secondaire 22S. Application aux mémoires à très haut niveau d'intégration.

DIVISEUR DE TENSION MOS

DIVISEUR DE TENSION MOS SIMPLE COMPORTANT TROIS TRANSISTORS MOS A ENRICHISSEMENT, A SAVOIR UN TRANSISTOR DE CHARGE 10 ET DEUX TRANSISTORS DE COMMANDE 12, 14, CES DEUX DERNIERS FORMANT UNE COMBINAISON PARALLELE A LAQUELLE EST CONNECTE LEDIT TRANSISTOR DE CHARGE. LA GRILLE DE L'UN DES TRANSISTORS DE COMMANDE 14 EST CONNECTEE A LA BORNE DE SORTIE 18, ALORS QUE LES DEUX AUTRES GRILLES SONT BRANCHEES SUR LA TENSION D'ALIMENTATION. LES TROIS TRANSISTORS ONT LEUR SUBSTRAT EN COMMUN. PAR LE CHOIX ADEQUAT DE LA SEULE GEOMETRIE DE TRANSISTOR, LA TENSION APPLIQUEE A LA BORNE DE SORTIE PEUT ETRE RENDUE INDEPENDANTE DES VARIATIONS DE LA TENSION DE SEUIL ET DES FLUCTUATIONS DE TEMPERATURE EN PRESENCE DE TENSIONS DE SORTIE SUPERIEURES A UNE TENSION DE SEUIL ET INFERIEURES A LA MOITIE DE LA TENSION D'ALIMENTATION. DE PLUS, LE RAPPORT ENTRE LES TENSIONS DE SORTIE ET LES TENSIONS D'ALIMENTATION RESTE CONSTANT. APPLICATION: MEMOIRES A ACCES ALEATOIRE.

POWER SOURCE CONSTANT INTEGREE HAS FIELD-EFFECT TRANSISTORS HAS DOOR ISOLEE

VOLTAGE GENERATOR CIRCUITRY ELECTRICALLY PROGRAMMABLE INTERNAL SUPPLY.

CURRENT GENERATOR STABILIZED INDIVIDUAL FEEDING, ESPECIALLY FOR MOS INTEGRATED CIRCUIT

DEVICE HAS SEMICONDUCTOR

Circuit en vue d'engendrer une tension de reference en utilisant un circuit de charge et de decharge

Circuit en vue d'engendrer une tension de reference comportant des premiers moyens 10, 20 en vue d'abaisser la polarisation d'entree au-dessous d'une tension appliquee exterieurement et de reduire tout d'abord la variation du niveau de tension due a la tension appliquee, des seconds moyens 40, 50 pour faire circuler un courant selon la sortie desdits premiers moyens pour detecter l'etat de la tension appliquee et engendrer la tension de reference augmentee de la chute de tension produite a travers la resistance selon ladite circulation de courant vers la borne de sortie de ladite tension de reference lorsqu'une tension constante fixe est appliquee, et des troisiemes moyens 70 en vue de charger et de decharger une partie du courant appliquee selon la variation de tension appliquee desdits seconds moyens.

A METHOD FOR PRODUCING A SIGNAL LIMITS IN TIME

SOURCE OF TENSION OF LOW IMPEDANCE

Receiver circuit with high input voltage protection

An integrated circuit 2 includes a receiver circuit 4 for receiving an input signal PAD and converting this to an output signal OUT. Conduction path circuitry 14 couples an input 10 to a first node 16 . Buffer circuitry 18 is coupled between the first node 16 and an output 12 carrying the output signal Out. The conduction path circuitry comprises a first PMOS transistor 24 and a second PMOS transistor 26 connected between the input 10 and the first node 16 . A first NMOS transistor 28 is connected between the input 10 and the first node 16 . The gate of the second PMOS transistor 26 is coupled to the output 12 to directly receive the output signal and thereby achieve rapid cut off of the charging of the node 16 when the input voltage rises beyond a certain level which switches the buffer circuitry 18.

Semiconductor chip

The present invention provides a semiconductor chip which is insusceptible to noise and whose consumption current is small. In a semiconductor chip, an internal power supply voltage for an internal circuit block is generated by a regulator having small current drive capability and a regulator having large current drive capability. A voltage buffer is provided between a reference voltage generating circuit and the regulator having large current drive capability. In a low-speed operation mode, the voltage buffer and the regulator having large current drive capability are made inactive. Therefore, noise in reference voltage is suppressed, and consumption current can be reduced.

High-voltage tolerant voltage regulator

Circuits and methodologies related to high-voltage tolerant regulators are disclosed. In some implementations, a voltage regulator can be configured to be capable of being in a regulating state and a bypass state. In the regulating state, an input voltage greater than a selected value can be regulated so as to yield a desired output voltage such as a substantially constant voltage. In the bypass state, an input voltage at or less than the selected value can be regulated so as to yield an output voltage that substantially tracks the input voltage. Such a capability of switching between two modes can provide advantageous features such as reducing the likelihood of damage in a powered circuit due to high input voltage, and extending the operating duration of a power source such as a rechargeable battery. Also disclosed are examples of how the foregoing features can be implemented in different products and methods of operation and fabrication.

Constant current circuit and semiconductor integrated circuit

In a constant current circuit, a drain terminal is connected to an output terminal of a current, and a gate voltage operable in a saturation region is applied to a source-grounded transistor. An increase current generating circuit generates an increase current equivalent to an increase of a current due to a channel length modulation effect of the transistor. A current mirror circuit generates a current having the same value as that of the increase current generated by the increase current generating circuit and supplies the generated current to the drain terminal of the transistor.

Reference voltage generation circuit and method

A reference voltage generation circuit includes: a bandgap reference circuit, generating a plurality of initial currents with different temperature coefficients; a base voltage generation circuit, combining the initial current into a combined current, and converting the combined current into one or more base voltages; a bias current source circuit, generating one or more bias currents based on at least one of the initial currents; and one or more regulating output circuit, each converting a respective one of the one or more bias currents into an increment voltage and adding the increment voltage to the base voltage to generate a respective output voltage. Each output voltage may have its respective temperature coefficient.

Multi-voltage regulator

Disclosed herein is a multi-voltage regulator. The multi-voltage regulator includes an error amplifier amplifying a difference voltage between a predetermined reference voltage and a received feedback voltage; a first voltage adjusting part connected to an output terminal of the error amplifier, the first voltage adjusting part regulating a level of a voltage at a power input terminal to output the regulated voltage to a first output terminal; a second voltage adjusting part connected to the output terminal of the error amplifier, the second voltage adjusting part regulating the level of the voltage at the power input terminal to output the regulated voltage to a second output terminal; and a voltage detector detecting a voltage according to a voltage at the first output terminal and a voltage at the second output terminal to supply the detected voltage as the feedback voltage.

Constant-voltage circuit and semiconductor device thereof

A reference-voltage generating circuit of an embodiment includes a first FET; a second FET; a first resistor in which one end is connected to a power supply while the other end is connected to a drain of the first FET; and a second resistor that is connected between the drain and a gate of the first FET, wherein a gate and a source of the second FET are connected, a drain of the second FET is connected to the gate of the first FET, the drain of the first FET outputs a reference voltage, and the source of the first FET and the source of the second FET are connected to a ground or another circuit.

Internal power supply voltage generation circuit

Provided is an internal power supply voltage generation circuit, with which a through current that flows during the operation of a logic circuit can be prevented from being excessive due to fluctuations in threshold voltage of a P-type transistor and an N-type transistor forming the logic circuit, and current consumption can be suppressed. Provided is an internal power supply voltage generation circuit for generating an internal power supply voltage at an internal power supply terminal and supplying the internal power supply voltage to a logic circuit, the internal power supply voltage generation circuit including a transistor having a source follower configuration for outputting a voltage applied to a gate thereof. A value of the internal power supply voltage is given based on the sum of an absolute value of a threshold voltage of an N-type transistor and an absolute value of a threshold voltage of a P-type transistor.

Method of generating multiple current sources from a single reference resistor

A differential voltage controlled current source generating one or more output currents is based upon a single external resistor. The differential voltage controlled current source may generate an output current that is proportional to a received differential voltage and a bias current with the use of a single external resistor. The technique may be used to generate multiple accurate and process independent current sources. The current sources may be a zero temperature coefficient (ZTC) current, a proportional to absolute temperature (PTAT) current, or an inversely proportional to absolute temperature (NTAT) current. The output of the current sources may be inversely proportional to the resistance of the external resistor.

Semiconductor integrated circuit

A semiconductor integrated circuit includes constant current circuit, starter circuit and power supply start-up circuit. In the constant current circuit, first current mirror circuit includes first and second transistors, and second current mirror circuit includes third and fourth transistors that are connected to first and second nodes. In the starter circuit, a potential of first node controls sixth transistor, seventh transistor is connected to third node, gate electrode of the seventh transistor is at ground potential, a capacitance element is connected to fourth node, and a potential of fourth node controls fifth transistor, which supplies start-up current to the constant current circuit via second node. In the power supply start-up circuit, source electrode of eighth transistor is fixed at power supply voltage, gate electrode is at ground potential, and drain electrode supplies power to the other circuits.

CONSTANT CURRENT CIRCUIT AND LIGHT EMITTING DIODE DRIVING DEVICE USING THE SAME

A constant current circuit includes a first transistor, a second transistor having the gate and the source connected to the gate and the source of the first transistor, and having the drain connected to a load, a voltage adjustment circuit section that controls the drain voltage of the first transistor, a constant current generation circuit section that supplies a constant current to the first transistor, and a detection circuit section that determines whether at least one of the first transistor and the second transistor is unable to output a current proportional to the first constant current while at least one of the first transistor and the second transistor operates in the linear region, by performing a voltage comparison between a voltage at a connecting section between the voltage adjustment circuit section and the constant current generation circuit section and a predetermined reference voltage. 1. A constant current circuit that generates a predetermined constant current and supplies the predetermined constant current to a load , the constant current circuit comprising:a first transistor composed of a MOS transistor that flows a current in accordance with a control signal input to the gate of the first transistor;a second transistor composed of a MOS transistor having a same conductivity type as that of the first transistor, the gate and the source of the second transistor corresponding to and being connected to the gate and the source, respectively, of the first transistor, the drain of the second transistor being connected to the load, the second transistor supplying a current to the load, the current being in accordance with the control signal input to the gate of the second transistor;a voltage adjustment circuit section that controls the drain voltage of the first transistor in accordance with the drain voltage of the second transistor;a constant current generation circuit section that is composed of a first current source that supplies a predetermined ...

Current source circuit with high order temperature compensation and current source system thereof

A current source circuit with high order temperature compensation, includes a reference voltage terminal, a first power module, a second power module, a control module, a current source output module and a bias current source module. The control module includes a first field-effect tube (FET), a second FET, and a third FET. The bias current source module includes a first bias current source and a second bias current source. The current source output module includes a fourth FET, a fifth FET, and an output terminal. The first power module includes a first comparator, a sixth FET, a first resistor and a second resistor. The second power module includes a second comparator, a seventh FET, a third resistor, and a fourth resistor. A current source system with high order temperature compensation is further provided.

Constant current circuit and voltage reference circuit

Provided is a constant current circuit in which an enhancement N-channel transistor can operate in a weak-inversion state even at high temperatures. A constant current circuit includes a current mirror circuit, a constant-current generation block circuit, and an off-leak circuit, wherein the off-leak circuit is constituted by a first enhancement N-channel transistor having a gate and a source connected to an earth terminal and a drain connected to an output of the constant current circuit. This suppresses an increase in a gate-to-source voltage of the enhancement N-channel transistor which generates a constant current, thereby maintaining its operation in a weak-inversion state.

Reference voltage generation circuit and internal volatage generation circuit using the same

A reference voltage generation circuit configured to generate a reference voltage level that is compensated for based on an internal temperature change, where the reference voltage level is adjusted based on a resistance value controlled in response to a control signal.

Low power current comparator for switched mode regulator

A current comparator comprising a first NMOS transistor having a drain coupled to V DD , a source and a gate. A first PMOS transistor having a source coupled to the source of the first NMOS transistor to form an input, a drain coupled to V SS and a gate coupled to the gate of the first NMOS transistor. A second NMOS transistor having a drain coupled to V DD , a source and a gate coupled to the input. A first bias current source having an input coupled to the source of the second NMOS transistor and an output. A second bias current source having an input coupled to the drain of the first NMOS transistor and an output coupled to the gate of the first NMOS transistor. A third NMOS transistor having a drain coupled to the gate of the first NMOS transistor to form an output, a source and a gate.

DC-DC CONVERTER

A DC-DC converter includes a main reactor interposed in a main energization path extending from a DC voltage input terminal to a DC voltage output terminal, a first main switching element interposed into the main energization path so as to be on-off controlled so that current flowing across the main reactor is intermitted, a second main switching element forming a discharge loop discharging electrical energy stored in the main reactor to the DC voltage output terminal side, an auxiliary reactor interposed between the first main switching element and the main reactor in the main energization path, an auxiliary switching element discharging electrical energy via the main reactor to the DC voltage output terminal side, the electrical energy being stored in the auxiliary and main reactors, and diodes connected in reverse parallel with the first and second main switching elements and the auxiliary switching elements respectively. 1. A DC-DC converter comprising:a main reactor interposed in a main energization path extending from a DC voltage input terminal to a DC voltage output terminal;a first main switching element which is interposed in the main energization path so as to be on-off controlled so that current flowing across the main reactor is intermitted;a second main switching element forming a discharge loop which discharges electrical energy stored in the main reactor to the DC voltage output terminal side;an auxiliary reactor interposed between the first main switching element and the main reactor in the main energization path;an auxiliary switching element which discharges electrical energy via the main reactor to the DC voltage output terminal side, the electrical energy being stored in the auxiliary and main reactors; anda plurality of diodes connected in reverse parallel with the first and second main switching elements and the auxiliary switching elements respectively.2. The DC-DC converter according to claim 1 , wherein the auxiliary reactor has inductance ...

IMPEDANCE TRANSFORMATION WITH TRANSISTOR CIRCUITS

In one implementation, an apparatus may include a first negative channel metal oxide semiconductor (NMOS) transistor circuit coupled to a first voltage source, a second NMOS transistor circuit coupled to the first voltage source, the second NMOS transistor circuit having a smaller channel width to channel length ratio than the first NMOS transistor circuit, a first positive channel metal oxide semiconductor (PMOS) transistor circuit coupled to a second voltage source and coupled to the second NMOS transistor circuit, and a second PMOS transistor circuit coupled to the second voltage source, the second PMOS transistor circuit having a larger channel width to channel length ratio than the first PMOS transistor circuit. 1. An apparatus comprising:a first transistor circuit having a first overdrive voltage, wherein the first overdrive voltage is defined by a gate-source voltage of the first transistor circuit minus a threshold voltage of the first transistor circuit,a second transistor circuit having a second overdrive voltage, wherein the second overdrive voltage is defined by a gate-source voltage of the second transistor circuit minus a threshold voltage of the second transistor circuit, and wherein a source of the second transistor circuit and a source of the first transistor circuit are coupled to a same electrostatic potential,wherein the gate-source voltage of the first transistor circuit is defined by at least one reference current and whereby the gate-source voltage of the second transistor circuit is defined by a gate-source voltage and a voltage drop provided by a voltage source.2. The apparatus of claim 1 , wherein the voltage source comprises an impedance element and a current source.3. The apparatus of claim 2 , wherein the impedance element includes one or more resistors.4. The apparatus of claim 3 , wherein the impedance element is coupled to the same electrostatic potential.5. The apparatus of claim 1 , wherein the gate source voltage of the first ...

Voltage reference circuit with temperature compensation

A voltage reference circuit with temperature compensation includes a power supply, a first reference voltage supply, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a resistor connected to the second NMOS source and ground. The voltage reference circuit also includes a second reference voltage supply, a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor with a drain connected to the source of the fourth NMOS transistor, a source connected to the ground, and a gate connected to the first reference voltage output.

Apparatus and method for outputting signal

There is provided an apparatus for outputting a signal, including: a reference signal generating unit outputting a first temperature coefficient signal having a positive temperature coefficient and a second temperature coefficient signal having a negative temperature coefficient; and an output unit outputting an output signal having a plurality of temperature coefficients, based on the first temperature coefficient signal and the second temperature coefficient signal.

REFERENCE-VOLTAGE CIRCUIT

Provided is a reference voltage circuit capable of adjusting an arbitrary output voltage to have arbitrary temperature characteristics. The reference voltage circuit includes: a reference current generating circuit configured to convert a difference between forward voltages of a plurality of PN junction elements into current to generate a first current; a current generating circuit configured to use the first current generated by the reference current generating circuit to generate a second current; and a voltage generating circuit including a first resistive element and a second resistive element, the first resistive element being configured to generate a first voltage having positive temperature characteristics when the first current flows through the first resistive element, the second resistive element being configured to generate a second voltage having negative temperature characteristics when the first current and the second current flow through the second resistive element. The reference voltage circuit outputs a reference voltage obtained by adding the first voltage to the second voltage.

Driver having low power consumption and method thereof

A driver having low power consumption includes a first input terminal, a second input terminal, an output terminal, a power supply terminal, a ground terminal, a driving circuit, an adjusting circuit connected to the driving circuit and a biasing circuit which is connected to the driving circuit and the adjusting circuit. A method for accomplishing low power consumption of a driver is also provided. The method accomplishes an object of low power consumption by dynamically adjusting a driving current of a driver according to a difference between inputted differential signals. 1. (canceled)2. A driver having low power consumption , comprising a first input terminal , a second input terminal , an output terminal , a power supply terminal , a ground terminal , a driving circuit which is connected to said first input terminal , said second input terminal , said output terminal , said power supply terminal and said ground terminal , an adjusting circuit which is connected to said driving circuit , said power supply terminal and said ground terminal , and a biasing circuit which is connected to said driving circuit , said adjusting circuit , said power supply terminal and said ground terminal;wherein said driving circuit comprises a first FET connected to said first input terminal, a second FET connected to said second input terminal, a third FET which is connected to said first FET and said second FET, a fourth FET connected to said first FET, a fifth FET connected to said second FET, a sixth FET connected to said fourth FET, a seventh FET connected to said fifth FET, an eighth FET connected to said sixth FET and a ninth FET connected to said seventh FET; said adjusting circuit comprise a tenth FET connected to said sixth FET, an eleventh FET connected to said tenth FET, a twelfth FET connected to said tenth FET, a first current source connected to said tenth FET, a thirteenth FET connected to said eleventh FET, and a second current source connected to said eleventh FET; ...

POWER SUPPLY CIRCUIT AND A METHOD OF CONTROLLING THE SAME

A power supply circuit, its generating and control methods are presented, relating to smart wearable devices. The power supply circuit comprises a Bandgap voltage reference, a real-time detection and control circuit, and a substitute voltage source. The real-time detection and control circuit is connected to the Bandgap voltage reference and the substitute voltage source, and adjusts an output voltage of the substitute voltage source to match an output voltage of the Bandgap voltage reference. After these output voltages are equal, the output voltage of the power supply circuit is provided by the substitute voltage source, and the Bandgap voltage reference can be disconnected from the circuit. This circuit can lower the power consumption of the Bandgap voltage reference without affecting the stability of the voltage output. 1. A power supply circuit , comprising:a Bandgap voltage reference;a real-time detection and control circuit; anda substitute voltage source, wherein the real-time detection and control circuit is connected to the substitute voltage source and the Bandgap voltage reference, and adjusts an output voltage of the substitute voltage source based on an output voltage of the Bandgap voltage reference, when these two output voltages are equal, the substitute voltage source replaces the Bandgap voltage reference to provide an output voltage of the power supply circuit.2. The circuit of claim 1 , wherein adjusting an output voltage of the substitute voltage source based on an output voltage of the Bandgap voltage reference comprises:connecting an output node of the Bandgap voltage reference to an output node of the substitute voltage source;adjusting the output voltage of the substitute voltage source based on a current between the output node of the substitute voltage source and the output node of the Bandgap voltage reference, when the current between these two output nodes is zero, the output node of the Bandgap voltage reference is disconnected from ...

POWER CONVERTER FOR FUEL CELL AND METHOD FOR CONTROLLING THE SAME

A power converter for a fuel cell is provided. The power converter includes a boost converter connected to the fuel cell and configured to control a load voltage at a predetermined magnitude in a normal operation mode and to induce an output response by applying a predetermined perturbation current to the fuel cell in a diagnosis mode, and a digital signal processor configured to extract an impedance parameter by detecting the output response of the fuel cell in the diagnosis mode, and predict a lifespan of the fuel cell according to the impedance parameter. The normal operation mode is configured to supply a voltage in response to a change of a load and the diagnosis mode is configured to predict the lifespan of the fuel cell. 1. A power converter for a fuel cell , the power converter comprising:a boost converter connected to the fuel cell and configured to control a load voltage at a predetermined magnitude in a normal operation mode and to induce an output response by applying a predetermined perturbation current to the fuel cell in a diagnosis mode, wherein the normal operation mode is configured to supply a voltage in response to a change of a load and the diagnosis mode is configured to predict the lifespan of the fuel cell; anda digital signal processor configured to extract an impedance parameter by detecting the output response of the fuel cell in the diagnosis mode, and predict a lifespan of the fuel cell according to the impedance parameter.2. The power converter of claim 1 , wherein the power converter further comprises an auxiliary energy storage device connected between the boost converter and the load claim 1 , configured to be charged by power from the fuel cell and to discharge power from the auxiliary energy storage device to the load in addition to the power from the fuel cell.3. The power converter of claim 2 , wherein the power converter further comprises a bidirectional converter connected to the auxiliary energy storage device claim 2 , and ...

CURRENT GENERATING CIRCUITS CAPABLE OF GENERATING CURRENTS WITH DIFFERENT TEMPERATURE COEFFICIENTS AND FLEXIBLY ADJUSTING SLOPE OF THE TEMPERATURE COEFFICIENT

A current generating circuit includes a first circuit subunit, a second circuit subunit and a third circuit subunit. The first circuit subunit is configured to generate a first current having a first temperature coefficient. The first temperature coefficient is a negative temperature coefficient. The second circuit subunit is configured to generate a second current having a second temperature coefficient. The second temperature coefficient is a positive temperature coefficient. The third circuit subunit is configured to generate a third current having a third temperature coefficient according to a difference between the first current and the second current. An absolute value of a slope of the third temperature coefficient is greater than that of the first temperature coefficient or that of the second temperature coefficient. 1. A current generating circuit , comprising:a first circuit subunit, configured to generate a first current having a first temperature coefficient, wherein the first temperature coefficient is a negative temperature coefficient;a second circuit subunit, configured to generate a second current having a second temperature coefficient, wherein the second temperature coefficient is a positive temperature coefficient; anda third circuit subunit, configured to generate a third current having a third temperature coefficient according to a difference between the first current and the second current, wherein an absolute value of a slope of the third temperature coefficient is greater than an absolute value of a slope of the first temperature coefficient or an absolute value of a slope of the second temperature coefficient.2. The current generating circuit as claimed in claim 1 , wherein the first current is a sum of the third current and the second current claim 1 , and wherein the third temperature coefficient is a negative temperature coefficient claim 1 , the absolute value of the slope of the third temperature coefficient is greater than the ...

Sample-and-Hold Circuit

A sample-and-hold circuit, which includes a hold capacitor at its output terminal and at least one intermediate capacitor, intermittently receives an input voltage, and a first value of a switch enable signal causes the sample-and-hold circuit to sample the input voltage and to charge the at least one intermediate capacitor and the hold capacitor to the input voltage, and when it is not receiving the input voltage, a second value of the switch enable signal causes the sample-and-hold circuit to hold, at its output terminal, the input voltage until the hold capacitor discharges, which starts to discharge only after the at least one intermediate capacitor has substantially discharged. 1. A sample-and-hold circuit comprising:a switch enable terminal for receiving a switch enable signal;an input terminal for intermittently receiving an input voltage;a first transistor having one conducting terminal coupled to the input terminal, having another conducting terminal coupled to a node and having a control terminal coupled to the switch enable terminal;an intermediate capacitor coupled between the node and a ground terminal;a second transistor having one conducting terminal coupled to the node, having another conducting terminal coupled to an output terminal and having a control terminal coupled to the switch enable terminal; anda hold capacitor coupled between the output terminal and the ground terminal,wherein, when the input terminal is receiving the input voltage, a first value of the switch enable signal causes the sample-and-hold circuit to sample the input voltage and to charge the intermediate capacitor and the hold capacitor to the sampled input voltage,wherein, when the input terminal is not receiving the input voltage, a second value of the switch enable signal causes the sample-and-hold circuit to hold, at the output terminal, the sampled input voltage until the hold capacitor discharges, andwherein the charge on the intermediate capacitor delays discharging of ...

VOLTAGE REFERENCE CIRCUIT, VOLTAGE DETECTOR AND VOLTAGE DETECTOR SYSTEM

A voltage detector () for monitoring an input signal and outputting a detection signal at an output when a voltage of the input signal meets a first threshold having: an input configured for receiving the input signal; a voltage reference circuit for receiving an input voltage and producing a reference voltage having a maximum value independent of the input voltage; and a trigger configured to compare the input signal and the reference voltage and to output a detection signal to the output when the voltage of the input signal reaches the first threshold. The voltage reference circuit comprises a reset input connected to either the input or the output and is configured to reduce the reference voltage when a predetermined reset signal is received. The voltage reference circuit may include: an input for receiving the input voltage; a first current controlling element (), such as a diode, which allows current to flow as an increasing, non-linear function of voltage at least within a first range of voltages; a second current controlling element (), such as a transistor, which allows current to flow as an increasing, non-linear function of voltage at least with a second range of voltages; and an output at which the output reference voltage is produced. The first current controlling element and the second current controlling element are connected in series between the input and a common reference, with the second current controlling element between the first current controlling element and a common reference, the output comprises a node between the two current controlling elements, the first and second range of voltages overlap and the second current controlling element is configured to vary the function by which it allows current to flow in dependence on the input voltage. 26-. (canceled)7. A voltage reference circuit according to wherein the second current controlling element has a control terminal connected to the input.8. A voltage reference circuit according to ...

LOW VOLTAGE DRIVE CIRCUIT WITH VARIABLE OSCILLATING FREQUENCIES AND METHODS FOR USE THEREWITH

A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; generating a first oscillation at a first frequency; generating a second oscillation at the first frequency; and outputting the first oscillation or the second oscillation on a bit-by-bit basis in accordance with the transmit digital data to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analog outbound data, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit drives an analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus in a first frequency range and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus in a second frequency range. 1. A low voltage drive circuit (LVDC) comprises: generating a DC component that has a magnitude between magnitudes of power supply rails of the transmit digital to analog circuit; and', 'generating, via an output limited digital to analog converter, a first oscillation at a first frequency; generating a second oscillation at second frequency, wherein magnitude of the first and second oscillations is limited to a range that is less than a difference between the magnitudes of power supply rails; and outputting the first oscillation or the second oscillation on a bit-by-bit basis in accordance with the transmit digital data to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analog outbound data;, 'a transmit digital to analog circuit configured to convert transmit digital data into analog outbound data bya receive analog to digital circuit configured to convert analog inbound data into received digital data; ...

Controllable Temperature Coefficient Bias Circuit

A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit. A Current Digital to Analog Converter (IDAC) scales the output of the VWT and provides the scaled output to an amplifier bias input. 1. A controllable temperature coefficient bias circuit comprising a variable with temperature circuit having:(a) a reference circuit having an output and a control port; and(b) a current control circuit including a first current control element having a first temperature coefficient coupled to the control port of the reference circuit and a parallel second current control element having a second temperature coefficient, different from the first temperature coefficient, coupled to the control port of the reference circuit.2. The invention of claim 1 , wherein the first temperature coefficient and the second temperature coefficient are of opposite polarity.3. The invention of claim 1 , wherein a resistance of the first current control element with respect to a resistance of the second current control element is set to a selected ratio to ...

CANCELLATION OF DYNAMIC OFFSET IN MOS RESISTORS

A circuit utilizes a MOS device in a triode mode of operation and includes a biasing circuit and a MOS device. The MOS device has a drain, a source, and a gate terminal, and is coupled to the biasing circuit. The source terminal, drain terminal, and gate terminal each has a potential and the drain and the source terminals have a resistance. The biasing circuit couples the drain and source terminals of the MOS device to the gate terminal of the MOS device. The biasing circuit couples a DC potential to the gate terminal to adjust the resistance between the source and drain terminals of the MOS device. The resistance between the source and drain terminals is a non-linear function of voltage potentials at the source and drain terminals. The biasing circuit reduces the non-linearity of the resistance between the drain and source terminals by modulating the potential at the gate terminal by a combination of source and drain terminal potentials. 1. A circuit operable to use a MOS device in a triode mode of operation comprising ,a biasing circuit; anda MOS device having a drain terminal, a source terminal, and a gate terminal, and being coupled to the biasing circuit, the source terminal having associated therewith a potential, the drain terminal having associated therewith a potential, and the gate terminal having associated therewith a potential, the drain and the source terminals having associated there between a resistance, wherein the biasing circuit couples the drain and source terminals of the MOS device to the gate terminal of the MOS device, and further wherein the biasing circuit couples a DC potential to the gate terminal of the MOS device to adjust the resistance between the source and drain terminals of the MOS device, wherein the resistance between the source and drain terminals is a non-linear function of voltage potentials at the source and drain terminals, the biasing circuit being operable to reduce the non-linearity of the resistance between the drain and ...

REFERENCE VOLTAGE CIRCUIT

Provided is a reference voltage circuit including a Zener diode having a cathode connected to a current source via a first node, and an anode connected to a ground point; a first resistor having one end connected to the first node; a second resistor having one end connected to another end of the first resistor; a first diode having an anode connected to another end of the second resistor via a second node, and a cathode connected to the ground point; and a current control circuit configured to generate a control current corresponding to an anode voltage of the first diode so that the current source supplies a reference current corresponding to the control current to the first diode. 1. A reference voltage circuit , comprising:a Zener diode having a cathode connected to a current source via a first node, and an anode connected to a ground point;a first resistor having one end connected to the first node;a second resistor having one end connected to another end of the first resistor;a first diode having an anode connected to another end of the second resistor via a second node, and a cathode connected to the ground point; anda current control circuit configured to generate a control current corresponding to an anode voltage of the first diode so that the current source supplies a reference current corresponding to the control current to the first diode.2. The reference voltage circuit according to claim 1 ,wherein the current source comprises a first current mirror circuit configured to receive the control current as an input current and supply the reference current as an output current, andwherein the current control circuit comprises a V/I conversion element configured to convert the anode voltage into the control current.3. The reference voltage circuit according to claim 2 , wherein the current control circuit comprises:a first error amplifier circuit having a non-inverting input terminal connected to the second node, and an inverting input terminal connected to ...

DISPLAY DEVICE AND REFERENCE VOLTAGE GENERATION METHOD

The present application discloses a display device and a reference voltage generation method. The display device includes a display area, a fan-out area, and a reference voltage generation circuit formed in the fan-out area. The reference voltage generation circuit includes a multi-voltage conversion module configured to: input a first direct current voltage and a second direct current voltage, and output multiple third direct current voltages having different voltage values; a latch module, configured to: input multiple latch signals and gating signals, and output corresponding switch control signals according to the input multiple latch signals and gating signals; a gating switch matrix, having a plurality of switch branches for controlling output of the multiple third direct current voltages, configured to turn on corresponding switch branches according to the switch control signals when the switch control signals are received, to output the third direct current voltages having corresponding voltage values. 1. A display device , comprising:a display area,a fan-out area, anda reference voltage generation circuit formed in the fan-out area,wherein the reference voltage generation circuit comprises:a multi-voltage conversion module, configured to: input a first direct current voltage and a second direct current voltage, and output multiple third direct current voltages having different voltage values;a latch module, configured to: input multiple latch signals and gating signals, and output corresponding switch control signals according to the input multiple latch signals and gating signals; anda gating switch matrix, having a plurality of switch branches for controlling output of the multiple third direct current voltages, configured to: turn on corresponding switch branches according to the switch control signals when the switch control signals are received, so as to output the third direct current voltages having corresponding voltage values.2. The display device ...

PASSING HIGH VOLTAGE INPUTS USING A CONTROLLED FLOATING PASS GATE

An input receiver includes a first pass transistor coupled between an input pad and an internal receiver node. The first pass transistor includes a controlled floating gate capacitively coupled to the input pad. A source follower transistor couples between the internal receiver node and a power supply. A gate for the source follower transistor couples to the input pad. 1. A circuit , comprising:a non-native first pass transistor coupled between an input pad and an input receiver node, wherein the non-native first pass transistor includes a floating gate coupled to a power supply through a pair of diodes; anda source follower transistor having its gate coupled to the input pad, a first drain/source terminal coupled to the input receiver node, and a second drain/source terminal coupled to the power supply.2. The circuit of claim 1 , wherein the pair of diodes comprises:a first diode-connected transistor coupled between the floating gate and the power supply; anda second diode-connected transistor coupled between the floating gate and the power supply, wherein the first diode-connected transistor is configured to have its cathode coupled to the floating gate and the second diode-connected transistor is configured to have its anode coupled to the floating gate.3. The circuit of claim 1 , further comprising a non-native second pass transistor coupled between the input pad and the input receiver node claim 1 , wherein a gate for the non-native second pass transistor is coupled to the power supply.4. The circuit of claim 2 , wherein the first diode-connected transistor and the second diode-connected transistor comprise diode-connected NMOS transistors.5. The circuit of claim 2 , wherein the first diode-connected transistor and the second diode-connected transistor comprise diode-connected PMOS transistors.6. The circuit of claim 1 , wherein the pair of diodes comprises a diode-connected transistor and a parasitic body diode for the diode-connected transistor.7. The circuit ...

OPTICAL SENSOR DEVICE AND VOLTAGE REGULATOR APPARATUS WITH IMPROVED NOISE REJECTION CAPABILITY

A voltage regulator apparatus with a rejection capability for high frequency power noise includes a low dropout linear regulator and a noise rejection circuit. The low dropout linear regulator has at least one operational amplifier which is powered by a power source, and the low dropout linear regulator is configured for receiving and regulating an input voltage signal to provide an output voltage signal for a load. The noise rejection circuit is coupled between the power source and the low dropout linear regulator, and is configured for providing a power noise rejection capability upon a high frequency part of a power signal of the power source to generate the power signal with less high frequency noise to the at least one operational amplifier. 1. A voltage regulator apparatus with a rejection capability for high frequency power noise , comprising:a low dropout linear regulator having at least one operational amplifier which is powered by a power source, the low dropout linear regulator being configured for receiving and regulating an input voltage signal to provide an output voltage signal for a load; anda noise rejection circuit, coupled between the power source and the low dropout linear regulator, configured for providing a power noise rejection capability upon a high frequency part of a power signal of the power source to generate the power signal with less high frequency noise to the at least one operational amplifier; a transistor used as a noise rejection element, having a first terminal connected to the power source, a second terminal connected to a power input of the at least one operational amplifier, and a control terminal connected to a voltage bias signal;', 'a resistor, having a first terminal connected to the power source and a second terminal connected to the control terminal of the transistor; and', 'a capacitor, having a first terminal connected to the control terminal of the transistor and a second terminal connected to a ground level;', ' ...

BIAS GENERATION AND DISTRIBUTION FOR A LARGE ARRAY OF SENSORS

In certain aspects, a bias generation circuit comprises a bias voltage generator. The bias voltage generator has a main NMOS transistor having a drain and a gate of the main NMOS transistor both coupled to a first terminal, a main resistor having a first main resistor terminal and a second main resistor terminal, wherein the first main resistor terminal couples to a source of the main NMOS transistor; and a main PMOS transistor having a source of the main PMOS transistor coupled to the second main resistor terminal and a drain and a gate of the main PMOS transistor both coupled to a second terminal, wherein the second terminal couples to a main ground. The bias generation circuit further comprises an array of sensors coupled to the first terminal and the second terminal. 1. A bias generation circuit , comprising:a main bias voltage generator coupled to a main bias current and configured to generate a first bias voltage at a first terminal and a second bias voltage at a second terminal through a main NMOS transistor, a main resistor, and a main PMOS transistor serially coupled, wherein the first bias voltage is higher than the second bias voltage; andan array of sensors, wherein each sensor of the array of sensors comprises a local bias replica coupled to the first terminal and the second terminal and is configured to generate a local bias current through a local NMOS transistor, a local resistor, and local PMOS transistor serially coupled, and wherein the first terminal couples to a gate of the main NMOS transistor and a gate of the local NMOS transistor, the second terminal couples to a gate of the main PMOS transistor and a gate of the local PMOS transistor.2. The bias generation circuit of further comprising a main current mirror coupled to the main bias voltage generator and configured to generate the main bias current.3. The bias generation circuit of claim 1 , wherein the local bias current of each sensor of the array of sensors is coupled to a sensing circuit ...

Power supply voltage detector circuit

A power supply voltage detector circuit includes a control signal terminal, switch circuit, first voltage detector circuit, and second voltage detector circuit. The first voltage detector circuit has a first input connected to a power supply terminal and a first output connected to the control signal input of the switch circuit. The first voltage detector circuit outputs a first-ON signal to a control signal input of the switch circuit when the power supply voltage is greater than or equal to the first threshold. The second voltage detector circuit has a second input connected to a power supply output of the switch circuit and second output connectable to a load circuit. The second voltage detector circuit outputs a second-ON signal to the control signal terminal to activate the load circuit when the voltage at the second input is greater than or equal to the second threshold.

VOLTAGE GENERATING CIRCUIT

A voltage generating circuit includes a voltage control circuit that includes an output section and a reference voltage terminal to which a reference voltage is supplied, and outputs a voltage to the output section which is controlled so as to be equal to a voltage of the reference voltage terminal, a first voltage dividing MOS transistor having a first end connected to the output section, and a second voltage dividing MOS transistor having a first end connected to a second end of the first voltage dividing MOS transistor. The voltage generating circuit further includes an auxiliary circuit having a set terminal to which an enable signal is supplied. In response to the enable signal, the auxiliary circuit outputs a first target voltage to the first end of the first voltage dividing MOS transistor and outputs a second target voltage to the first end of the second voltage dividing MOS transistor. 1. A voltage generating circuit comprising:a voltage control circuit that includes an output section and a reference voltage terminal to which a reference voltage is supplied, and outputs a voltage to the output section, the output voltage being controlled so as to be equal to a voltage of the reference voltage terminal;at least two voltage dividing MOS transistors connected in series including a first voltage dividing MOS transistor having a first end connected to the output section and a second voltage dividing MOS transistor having a first end connected to a second end of the first voltage dividing MOS transistor;an auxiliary circuit that includes a set terminal to which an enable signal is supplied, and in response to the enable signal, outputs a first target voltage to the first end of the first voltage dividing MOS transistor and outputs a second target voltage to the first end of the second voltage dividing MOS transistor; andan output circuit including an output terminal and configured to output the output voltage to the output terminal, based on a voltage that is ...

Devices, Systems and Method for Providing Adaptive Output Power by a Power Converter to an Adaptive Device

Embodiments of devices, systems, and methods for controlling the output voltages and currents of a power converter as requested by an adaptive device are described. In one embodiment, a power converter includes a primary controller, a secondary controller, and an opto-coupler configured to communicate a communication request, including a load request, by a secondary controller to a primary controller in a feedback signal. A method may include the operations of: executing a request cycle, by extending an “ON” state for a secondary switch, detecting a slope change in a scaled primary voltage signal, entering a communication-ready mode, converting a load request into communication information communicated in a feedback signal using an opto-coupler, decoding the communication information, and adjusting at least one of a reference voltage for output current and a reference voltage. 1. A power converter , comprising: a first coil located on a primary side of the transformer;', 'a second coil located on a secondary side of the transformer; and', 'wherein the first coil is electrically coupled to a power source;', 'wherein the second coil is electrically coupled to and configured to provide an output current and an output voltage to an adaptive device;', 'wherein the primary side is electrically isolated from the secondary side;, 'a transformer, comprisinga primary controller, electrically coupled to the first coil, configured to control the operating status of the first coil;a secondary controller, electrically coupled to the second coil; and 'wherein the opto-coupler is configured to communicate, during a request cycle, a communication request in a feedback signal generated by the secondary controller;', 'an opto-coupler comprising a send side electrically coupled to the secondary controller and a receive side electrically coupled to the primary controller;'}wherein the communication request represents a load request received from the adaptive device; andwherein, during ...

SEMICONDUCTOR CIRCUIT

A semiconductor circuit according to embodiments includes a circuit that includes the current source and generates the output voltage, and a voltage filter constituted by a depression-type NMOS transistor, the depression-type NMOS transistor having a source connected to a power supply side of the circuit, a gate that is grounded, and a drain to which a power supply voltage is applied. Thereby, a voltage on the power supply side of the circuit that has the current source and generates an output voltage is fixed regardless of an influence of a power supply fluctuation and suppresses a change in circuit characteristics. 1. A semiconductor circuit comprising:at least one circuit that includes a current source and generates an output voltage; andat least one voltage filter constituted by a depression-type NMOS transistor, the depression-type NMOS transistor having a source connected to a power supply side of the circuit, a gate that is grounded, and a drain to which a power supply voltage is applied.2. The semiconductor circuit according to claim 1 , whereinthe circuit is constituted by an NMOS transistor.3. The semiconductor circuit according to claim 1 , whereinthe circuit is an amplifying circuit, a buffer circuit, or a constant voltage circuit.4. The semiconductor circuit according to claim 1 , wherein the at least one circuit comprises a plurality of circuits and the at least one voltage filter comprises a plurality of voltage filters.5. The semiconductor circuit according to claim 1 , wherein the at least one circuit comprises a plurality of circuits claim 1 , andthe source of the depression-type NMOS transistor is commonly connected to the power supply side of each of the plurality of circuits.6. A semiconductor circuit comprising:a first NMOS transistor having a source that is grounded, and a drain that is connected to an output terminal, operates in a saturation region, and constitutes a current source;a second NMOS transistor having a source connected to the ...

METHODS AND SYSTEMS OF OPERATING BUCK-BOOST CONVERTERS

Operating buck-boost converters. At least some of the example embodiments are methods including: producing an output voltage and an output current from the buck-boost converter; sensing a feedback parameter by a sensor disposed between an inductor of the buck-boost converter and a load; generating an error signal based on the feedback parameter; running the buck-boost converter in a buck-only mode, the buck-only mode operating at a switching frequency and during periods of time when the error signal is within a first range of values; and changing to a buck-boost mode when the error signal is in a second range of values, the buck-boost mode operating at the switching frequency; and transitioning to a boost-only mode when the error signal is in a third range of values, the boost-only mode operating at the switching frequency. 1. A method of operating a buck-boost converter , comprising:producing an output voltage and an output current from the buck-boost converter;sensing a feedback parameter by a current sensor disposed between an inductor of the buck-boost converter and a load, the current sensor senses magnitude of current to the load;generating an error signal based on the feedback parameter;running the buck-boost converter in a buck-only mode, the buck-only mode operating at a switching frequency having a first phase during periods of time when the error signal is within a first range of values; andchanging to a buck-boost mode when the error signal is in a second range of values, the buck-boost mode operating at the switching frequency; andtransitioning to a boost-only mode when the error signal is in a third range of values, the boost-only mode operating at the switching frequency having a second phase different than the first phase.2. The method of wherein running the buck-boost converter in the buck-only mode further comprises masking a boost clock signal when the error signal is within the first range of values.3. The method of wherein masking the boost ...

BAND-GAP REFERENCE CIRCUIT BASED ON TEMPERATURE COMPENSATION

A band-gap reference circuit includes a proportioned current generating circuit, a startup circuit, a current mirror circuit, a high-order temperature compensation generating circuit and a reference generating circuit. The proportioned current generating circuit is configured to generate a current in direct proportion to the absolute temperature. The startup circuit is configured to start up the proportioned current generating circuit when the startup circuit is power on. The current mirror circuit is configured to reproduce a current which is the same as the current in direct proportion to the absolute temperature. The high-order temperature compensation generating circuit is configured to generate a compensation current of high-order temperature coefficient. The reference generating circuit is configured to add the voltage which is generated by the proportioned current generating circuit to a voltage of negative temperature coefficient according to a certain proportion, and output a reference voltage of zero temperature coefficient. 1. A band-gap reference circuit based on temperature compensation , the circuit comprising:a proportioned current generating circuit configured to generate a current in direct proportion to the absolute temperature;a startup circuit configured to start up the proportioned current generating circuit when the startup circuit is power on;a current mirror circuit configured to reproduce a current which is the same as the current in direct proportion to the absolute temperature;a high-order temperature compensation generating circuit configured to generate a compensation current of high-order temperature coefficient; anda reference generating circuit configured to add the voltage which is generated by the proportioned current generating circuit to a voltage of negative temperature coefficient according to a certain proportion, and output a reference voltage of zero temperature coefficient.2. The band-gap reference circuit based on ...

SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

There is a need to provide a semiconductor device, a semiconductor system, and a semiconductor device manufacturing method capable of accurately monitoring a minimum operating voltage for a monitoring-targeted circuit. A monitor portion of a semiconductor system according to one embodiment includes a voltage monitor and a delay monitor. The voltage monitor is driven by power-supply voltage SVCC different from power-supply voltage VDD supplied to an internal circuit as a monitoring-targeted circuit and monitors power-supply voltage VDD. The delay monitor is driven by power-supply voltage VDD and monitors signal propagation time for a critical path in the internal circuit. The delay monitor is configured so that a largest on-resistance of on-resistances for a plurality of transistors configuring the delay monitor is smaller than a largest on-resistance of on-resistances for a plurality of transistors configuring the internal circuit. 1. A semiconductor device comprising:a voltage monitor that is driven by a second power-supply voltage different from a first power-supply voltage supplied to a monitoring-targeted circuit and monitors the first power-supply voltage; anda delay monitor that is driven by the first power-supply voltage and monitors signal propagation time for a critical path in the monitoring-targeted circuit,wherein the delay monitor is configured so that a largest on-resistance of on-resistances for a plurality of transistors configuring the delay monitor is smaller than a largest on-resistance of on-resistances for a plurality of transistors configuring the monitoring-targeted circuit.2. The semiconductor device according to claim 1 ,wherein the delay monitor is configured so that a largest threshold voltage of threshold voltages for the transistors configuring the delay monitor is smaller than a largest threshold voltage of threshold voltages for the transistors configuring the monitoring-targeted circuit.3. The semiconductor device according to claim 1 ...

SUPPLY VOLTAGE REGULATOR

A circuit comprising a NMOS having a gate coupled to a first node and a source terminal coupled to a second node, a second NMOS having a gate coupled to the second node and a source terminal coupled to an output node, a PMOS having a gate coupled to a third node, a drain terminal coupled to a fourth node, and a source terminal coupled to a fifth node, and a second PMOS having a gate coupled to the fourth node, a drain terminal coupled to the output node, and a source terminal coupled to the fifth node. The circuit also includes a voltage protection sub-circuit coupled to the first node, a fast turn-off sub-circuit coupled to the output node, a fast turn-on sub-circuit coupled to the third and fourth nodes, and a node initialization sub-circuit coupled to the first, second, and fourth nodes and the fast turn-on sub-circuit. 1. A circuit comprising: a first n-type metal oxide semiconductor field effect transistor (MOSFET) (NMOS) having a gate terminal coupled to a first node, a drain terminal, and a source terminal coupled to a second node;', 'a second NMOS having a gate terminal coupled to the second node, a drain terminal, and a source terminal coupled to an output node;', 'a first p-type MOSFET (PMOS) having a gate terminal coupled to a third node, a drain terminal coupled to a fourth node, and a source terminal coupled to a fifth node; and', 'a second PMOS having a gate terminal coupled to the fourth node, a drain terminal coupled to the output node, and a source terminal coupled to the fifth node: and, 'a control sub-circuit havinga fast turn-off sub-circuit coupled to the output node, and configured to turn off at least a portion of the control sub-circuit more rapidly than in the absence of the fast turn-off sub-circuit.2. The circuit of claim 1 , wherein the fast turn-off sub-circuit is configured to couple the gate terminal of the second PMOS to a voltage supply to bypass a bias current turn off of the second PMOS and rapidly turn off the second PMOS when an ...

Rf square-law circuit

A circuit includes a first transistor that conducts a first current responsive to a DC bias voltage and an RF signal. A second transistor conducts a second current responsive to the DC bias voltage. The first current and the second current are mirrored through a pair of current mirrors coupled together through a low-pass filter to filter the envelope of the RF signal.

Bandgap reference voltage generator

Disclosed is a bandgap reference voltage generator insensitive to changes of process, voltage, and temperature. A bandgap reference voltage generator may detect current having characteristic of CTAT and current having characteristic of PTAT which flow in a current compensation part included in an amplification part, and provide body voltage to one of two input transistors included in the amplification part in response to ratio of the two currents when the ratio is different from the preconfigured reference value. Thus, characteristics according to changes of parameters of elements and change of offset of the amplification part due to changes of PVT may be enhanced, and a characteristic of power supply rejection ratio (PSRR) may be enhanced.

Body Biasing for RF Switch Optimization

Switches comprising a number of transistors in series achieve improved performance through biasing the bodies of the transistors to lower the stack resistance in the ON mode and optionally to also lower the stack capacitance in the OFF mode. These switches find use in RF applications such as phase shifters, step attenuators, and in antenna switches, for example. In some embodiments, a bias network is used to alternatingly provide a positive bias voltage or a negative bias voltage to the bodies of the transistors. 1. A switch comprising:a plurality of transistors arranged in series, each transistor of the plurality of transistors including a source, a drain, a channel disposed therebetween, and a gate to control the channel;a first bias network configured to bias the gates of the plurality of transistors; anda second bias network configured to bias the channels of the plurality of transistors.2. The switch of wherein the second bias network includes a resistor for each transistor of the plurality of transistors claim 1 , wherein the resistors are arranged in series claim 1 , wherein each resistor has a proximal end and a distal end claim 1 , wherein each distal end of each resistor is associated with a node claim 1 , and wherein each said node biases the channel of the corresponding transistor.3. The switch of wherein the second bias network includes a first diode claim 1 , the first diode being forward biased.4. The switch of wherein the second bias network further includes second and third diodes in series with the first diode claim 3 , the second and third diodes also being forward biased.5. The switch of further comprising a second diode arranged in parallel to the first diode claim 3 , the second diode being reverse biased.6. The switch of further comprising a DC control configured to supply a variable bias voltage claim 1 , wherein the first and second bias networks are configured to both receive the same variable bias voltage from the DC control.7. The switch ...

Piecewise correction of errors over temperature without using on-chip temperature sensor/comparators

A temperature dependent correction circuit includes a first supply source, a second supply source, a rectifying circuit, and a reference. The first supply source is configured to supply a first signal that varies with temperature along a first constant or continuously variable slope. The second supply source is configured to supply a second signal that varies with temperature along a second constant or continuously variable slope. The rectifying circuit is configured to receive the first and second signal, rectify the first signal to produce a first rectified signal, and add the first rectified signal to the second signal to produce a correction signal. The reference is configured to receive the correction signal.

VOLTAGE SENSITIVE CURRENT CIRCUIT

Aspects of the invention include a first voltage sensitive circuit including first transistors, the first transistors being coupled together so as to be operatively coupled to a first current source. A second voltage sensitive circuit includes second transistors, the second transistors being coupled together so as to be operatively coupled to a second current source, the first voltage sensitive circuit being coupled to the second voltage sensitive circuit to form a delay chain, the first and second current sources being responsive to changes in voltage of a power supply according to a voltage reference. A voltage sensitive current reference module is coupled to the first and second current sources and configured to supply the voltage reference to the first and second current sources, the voltage sensitive current reference module being responsive to changes in the voltage of the power supply. 1. A circuit comprising:a first voltage sensitive circuit comprising first transistors, the first transistors being coupled together so as to be operatively coupled to a first current source;a second voltage sensitive circuit comprising second transistors, the second transistors being coupled together so as to be operatively coupled to a second current source, the first voltage sensitive circuit being coupled to the second voltage sensitive circuit to form a delay chain, the first and second current sources being responsive to changes in voltage of a power supply according to a voltage reference; anda voltage sensitive current reference module coupled to the first and second current sources and configured to supply the voltage reference to the first and second current sources, the voltage sensitive current reference module being responsive to changes in the voltage of the power supply.2. The circuit of claim 1 , wherein each of the first transistors is an n-type field effect transistor (NFET).3. The circuit of claim 1 , wherein each of the second transistors is an NFET.4. The ...

LOW VOLTAGE DRIVE CIRCUIT WITH VARIABLE FREQUENCY CHARACTERISTICS AND METHODS FOR USE THEREWITH

A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; a first plurality of oscillations, wherein each oscillation of the first plurality of oscillations has first unique oscillation characteristics; selecting one of the first plurality of oscillations in accordance with a first portion of the transmit digital data to produce a first selected oscillation; generating a second plurality of oscillations, wherein each oscillation of the second plurality of oscillations has second unique oscillation characteristics; selecting one of the second plurality of oscillations in accordance with a second portion of the transmit digital data to produce a second selected oscillation, and outputting the first selected oscillation and the second selected oscillation on an n-bit-by-n-bit basis to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analog outbound data. A drive sense circuit drives an analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus in a first frequency range and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus in a second frequency range. 1. A low voltage drive circuit (LVDC) comprises: generating a DC component that has a magnitude between magnitudes of power supply rails of the transmit digital to analog circuit; and', 'generating, via an output limited digital to analog converter, a first plurality of oscillations, wherein each oscillation of the first plurality of oscillations has first unique oscillation characteristics; selecting one of the first plurality of oscillations in accordance with a first portion of the transmit digital data to produce a first selected oscillation; generating a second plurality of oscillations, ...

SEMICONDUCTOR DEVICE WITH REFERENCE VOLTAGE CIRCUIT

Provided is a semiconductor device with a reference voltage circuit including an enhancement type transistor having P-type polycrystalline silicon as a first gate electrode, and a depletion type transistor having N-type polycrystalline silicon as a second gate electrode, in which the enhancement type transistor has an impermeable film that is locally provided to cover the first gate electrode via an interlayer insulating film disposed on the first gate electrode, and a nitride film that has an opening portion which is provided larger than the first gate electrode and smaller than the impermeable film, and is provided to cover a periphery of the impermeable film, and the depletion type transistor has a nitride film that is directly provided on an interlayer insulating film disposed on the second gate electrode and covers the depletion type transistor without a gap.

Multi-bit digitally controlled accurate current source circuit

This invention provides a multi-bit digitally controlled accurate current source circuit including a reference current detection unit, a voltage buffer unit, a digital logic control unit, a switch array unit, and a current source array unit. The reference current detection unit generates a first bias voltage according to a reference current; the voltage buffer unit receives the first bias voltage, and generate a buffer voltage accordingly; the digital logic control unit receives the buffer voltage, and generate a digital control signal accordingly; the switch array unit receives the digital control signal, and generate on-off signals accordingly; and the current source array unit receives and responds to the on-off signals so as to control turn-on and turn-off of the current sources in the current source array unit. In this invention, by adding only one voltage buffer, a cascode current source if formed, and an area saving accurate current source is realized. 1. A multi-bit digitally controlled accurate current source circuit , comprising:a reference current detection unit, coupled with a reference current source and configured to generate a first bias voltage according to a reference current of the reference current source;a voltage buffer unit, coupled with the reference current detection unit and configured to receive the first bias voltage of the reference current detection unit and to generate a buffer voltage according to the first bias voltage at the same time;a digital logic control unit, coupled with the voltage buffer unit and configured to receive the buffer voltage of the voltage buffer unit and to generate a digital control signal according to the buffer voltage at the same time;a switch array unit, coupled with the digital logic control unit and configured to receive the digital control signal of the digital logic control unit and to generate an on-off signal controlling a current source array unit according to the digital control signal at the same ...

CONSTANT CURRENT CIRCUIT

The constant current circuit includes a constant current generation circuit, a start-up detection circuit configured to detect start-up of the constant current generation circuit, and a clamp circuit configured to output a start-up voltage to the constant current generation circuit. The start-up voltage output from the clamp circuit is a voltage close to gate voltages that are higher than gate voltages of transistors that form a current mirror circuit of the constant current generation circuit, in a state where the constant current generation circuit is operating. 1. A constant current circuit comprising: a resistor connected to a ground terminal;', 'a first current mirror circuit connected to the ground terminal and the resistor, the first current mirror circuit containing a plurality of transistors; and', 'a second current mirror circuit connected between a power supply terminal supplying a power supply voltage and the first current mirror circuit; and, 'a constant current generation circuit includinga start-up detection circuit configured to detect start-up of the constant current generation circuit, and transmit a detection signal;a clamp circuit configured to apply a start-up voltage to the constant current generation circuit, the start-up voltage being a voltage close to the gate voltages of the plurality of transistors in the first current mirror circuit in a state where the constant current generation circuit operates, the start-up voltage being higher than the gate voltages of the plurality of transistors; anda power supply start-up detection circuit configured to detect whether the power supply voltage is applied to the power supply terminal, start up the clamp circuit by detecting the power supply voltage applied to the power supply terminal, receive the detection signal from the start-up detection circuit, and stop the clamp circuit by receiving the detection signal.2. The constant current circuit according to claim 1 , wherein the start-up detection ...

Dynamic Battery Voltage Restriction for Hazardous Environments

A method for dynamic limiting of battery voltage includes determining that a voltage delivered by a battery exceeds a predefined maximum safe voltage for operation of a portable electronic device in a hazardous environment and, in response, enabling a voltage restriction circuit in a supply line between the battery and the portable electronic device to reduce the voltage delivered by the battery below the maximum safe voltage, and supplying electrical power to the portable electronic device at the reduced voltage. Enabling the voltage restriction circuit may include deactivating a MOSFET switch that includes a forward biased body diode to allow the body diode to provide a fixed voltage drop. The method also includes determining that the voltage delivered by the battery no longer exceeds the maximum safe voltage and, in response, disabling the first voltage restriction circuit by activating the MOSFET, thus allowing the body diode to be bypassed. 1. A method for providing on-demand reduction of battery output voltage , comprising:determining, prior to supplying electrical power from a battery to a portable electronic device, that a voltage delivered by the battery exceeds a predefined maximum safe voltage for operation of the portable electronic device in a hazardous environment; enabling a first voltage restriction circuit in a supply line between the battery and the portable electronic device to reduce the voltage delivered by the battery below the maximum safe voltage; and', 'supplying electrical power to the portable electronic device at the reduced voltage;, 'in response to determining that the voltage delivered by the battery exceeds the maximum safe voltagedetermining, subsequent to enabling the first voltage restriction circuit, that the voltage delivered by the battery no longer exceeds the maximum safe voltage; and 'disabling the first voltage restriction circuit.', 'in response to determining that the voltage delivered by the battery no longer exceeds the ...

MULTI-CHANNEL PULSE CURRENT GENERATOR WITH CHARGING

A multi-channel current pulse generator for driving a plurality of loads with unique positive terminals and a shared negative terminal. The pulse generator comprises a pulse control transistor and, for each load, a load capacitor and a charging control transistor. The pulse control transistor allows or blocks current pulses through the loads and has a drain terminal connected to the shared negative terminal, a source terminal connected to ground, and a gate terminal for receiving a load driver control signal. The load capacitors are discharged by current pulses through the corresponding loads. The charging control transistors allow or block charging currents for the corresponding load capacitors. The pulse control transistor is preferably an enhancement mode GaN FET and is chosen to withstand current pulses through a maximum number of loads to be driven simultaneously. 1. A multi-channel current pulse generator for driving a plurality of loads with unique positive terminals and a shared negative terminal , comprising:a pulse control transistor for allowing or blocking current pulses through the plurality of loads based on a load driver control signal and having a drain terminal connected to the shared negative terminal, a source terminal connected to ground, and a gate terminal for receiving the load driver control signal; and a load capacitor configured to be charged by a charging circuit and discharged by providing a current pulse to the respective load; and', 'a charging control transistor for allowing or blocking a charging current to the load capacitor from the charging circuit based on a charging control signal., 'for each load of the plurality of loads2. The multi-channel current pulse generator of claim 1 , wherein the pulse control transistor comprises a gallium nitride (GaN) field effect transistor (FET).3. The multi-channel current pulse generator of claim 2 , wherein the pulse control transistor comprises an enhancement mode GaN FET.4. The multi-channel ...

Reference voltage generator

Provided is a reference voltage generator having flat temperature characteristics. The reference voltage generator includes a resistor ( 3 ) surrounding a periphery of a depletion MOS transistor ( 1 ) of a first conductivity type which is connected so as to function as a current source for causing a constant current to flow, and an enhancement MOS transistor ( 2 ) of the first conductivity type diode-connected thereto, and also includes a current source capable of being trimmed with high precision under a preset temperature environment and a diode connected in series to the current source. The reference voltage generator can operate under a given preset temperature environment because a voltage consumed in the resistor becomes approximately constant in accordance with a signal output from the diode.

OUTPUT BUFFERS

An output buffer is provided. The output buffer is coupled to a first voltage source providing a first supply voltage and used for generating an output signal at an output terminal according to an input signal. The output buffer includes first and second transistors and a self-bias circuit. The first and second transistors are cascaded between the output terminal and a reference voltage. The self-bias circuit is coupled to the output terminal and the control electrode of the first transistor. When the output buffer does not receive the first supply voltage, the self-bias circuit provides a first bias voltage to the control electrode of the first transistor according to the output signal to decrease voltage differences between the control electrode and the input and output electrodes of the first transistor to be lower than a predetermined voltage. 1. An output buffer , coupled to a first voltage source providing a first supply voltage , for generating an output signal at an output terminal according to an input signal , comprising:a first transistor having a control electrode, an input electrode coupled to the output terminal, and an output electrode;a second transistor having a control electrode, an input electrode coupled to the output electrode of the first transistor, and an output electrode coupled to a reference voltage; anda self-bias circuit coupled to the output terminal and the control electrode of the first transistor,wherein when the output buffer does not receive the first supply voltage, the self-bias circuit provides a first bias voltage at the control electrode of the first transistor according to the output signal to decrease voltage differences between the control electrode and the input and output electrodes of the first transistor to be lower than a predetermined voltage.2. The output buffer as claimed in claim 1 , wherein the self-bias circuit comprises a plurality of first diodes cascaded between the output terminal and the control electrode of ...

BANDGAP REFERENCE CIRCUIT AND METHOD OF USING THE SAME

A bandgap reference circuit and method of using the same are provided. The bandgap reference circuit includes a startup component; an output component; and a bandgap core component coupled there-between. The bandgap core component includes a reference point having a voltage associated with an output signal of the output component. A controller is configured for controlling the bandgap core component and the output component to switch between a low power consumption mode and a normal operation mode based on the voltage at the reference point. When the bandgap core component and the output component operate in the normal operation mode, the bandgap reference circuit outputs a stable voltage and has a first power consumption. When the bandgap core component and the output component operate in the low power consumption mode, the bandgap reference circuit has a second power consumption less than the first power consumption. 1. A bandgap reference circuit , comprising:a startup component;an output component;a bandgap core component coupled between the startup component and the output component, wherein the bandgap core component includes a reference point, and a voltage at the reference point is associated with an output signal of the output component; anda controller configured for controlling the bandgap core component and the output component to switch between a low power consumption mode and a normal operation mode based on the voltage at the reference point; when the bandgap core component and the output component operate in the normal operation mode, the bandgap reference circuit outputs a stable voltage and has a first power consumption, and', 'when the bandgap core component and the output component operate in the low power consumption mode, the bandgap reference circuit has a second power consumption less than the first power consumption., 'wherein2. The bandgap reference circuit of claim 1 , wherein the controller is further configured for:when the bandgap core ...

Methods for fabricating an integrated circuit with a voltage regulator

Methods for fabricating an integrated circuit with a voltage regulator are provided. In some implementations, a method includes forming a primary regulator on a semiconductor substrate, including fabricating a switch, fabricating an amplifier for controlling the switch, and fabricating a voltage generator for biasing the amplifier to operate the primary regulator in a bypass mode or in a regulating mode. The method further includes forming an input terminal and an output terminal of the primary regulator on the semiconductor substrate, forming a secondary regulator on the substrate, forming an input terminal and an output terminal of the secondary regulator on the semiconductor substrate, and forming an electrical connection between the output terminal of the primary regulator and the input terminal of the secondary regulator.

Power-on reset circuit

A Power-on Reset circuit is described. The Power-on Reset is formed by two comparators and a latch circuit. The Power-on Reset circuit will de-assert the reset state once the supply voltage reaches a first reference point and re-assert the reset state once the supply voltage drops below a second reference point. The Power-on Reset circuit disclosed further includes circuits to initialize properly and to ensure the regulator voltage and the bandgap voltages are stable and above the ground level voltage.

REFERENCE VOLTAGES

A voltage reference circuit comprises a voltage-controlled current source; a first reference metal-oxide-semiconductor field-effect transistor having a first threshold voltage; a second reference metal-oxide-semiconductor field-effect transistor having a second threshold voltage, wherein the second threshold voltage is different to the first threshold voltage; a current mirror; and a load. The voltage-controlled current source is arranged to generate a first current proportional to a difference between the first and second threshold voltages, and the current mirror is arranged to generate a second current that is a scaled version of the first current through the load so as to produce a reference voltage. 1. A voltage reference circuit comprising:a voltage-controlled current source;a first reference metal-oxide-semiconductor field-effect transistor having a first threshold voltage;a second reference metal-oxide-semiconductor field-effect transistor having a second threshold voltage, said second threshold voltage being different to said first threshold voltage;a current mirror; anda load,wherein the voltage-controlled current source is arranged to generate a first current proportional to a difference between said first and second threshold voltages, and the current mirror is arranged to generate a second current that is a scaled version of the first current through the load so as to produce a reference voltage.2. The voltage reference circuit as claimed in claim 1 , wherein the voltage-controlled current source is an operational transconductance amplifier.3. The voltage reference circuit as claimed in claim 1 , wherein said first threshold voltage is greater than said second threshold voltage.4. The voltage reference circuit as claimed in claim 3 , wherein the first threshold voltage is between 300 mV and 800 mV.5. The voltage reference circuit as claimed in claim 3 , wherein the second threshold voltage is between 200 mV and 700 mV.6. The voltage reference circuit as ...

REFERENCE VOLTAGE CIRCUIT AND POWER-ON RESET CIRCUIT

A reference voltage circuit includes a first output terminal from which a first reference voltage is supplied; a first MOS transistor of a depletion type, the first MOS transistor containing a drain connected to a power supply terminal, a gate connected to a ground terminal, and a source; a first voltage drop circuit including a first end connected to the source of the first MOS transistor and a second end connected to the first output terminal; and a second MOS transistor of a depletion type, the second MOS transistor containing a drain connected to the first output terminal, a gate connected to the ground terminal, and a source connected to the ground terminal. 1. A reference voltage circuit , comprising:a first output terminal from which a first reference voltage is supplied;a first MOS transistor of a depletion type, the first MOS transistor containing a drain connected to a power supply terminal, a gate connected to a ground terminal, and a source;a first voltage drop circuit including a first end connected to the source of the first MOS transistor and a second end connected to the first output terminal; anda second MOS transistor of a depletion type, the second MOS transistor containing a drain connected to the first output terminal, a gate connected to the ground terminal, and a source connected to the ground terminal.2. The reference voltage circuit according to claim 1 , wherein the first voltage drop circuit is configured by a third MOS transistor of a depletion type claim 1 , the third MOS transistor containing a gate connected to the source of the first MOS transistor claim 1 , a drain connected to the source of the first MOS transistor and the gate of the third MOS transistor claim 1 , and a source connected to the first output terminal.3. The reference voltage circuit according to claim 1 , further comprising:a second output terminal from which a second reference voltage is supplied;a fourth MOS transistor of a depletion type, the fourth MOS transistor ...

POWER VOLTAGE GENERATING CIRCUIT AND DISPLAY APPARATUS INCLUDING THE SAME

A power voltage generating circuit includes an input part, a clock determining part and a plurality of switches. The input part receives a plurality of clock signals and generates a plurality of peak signals corresponding to rising edges of the plurality of clock signals. The clock determining part determines a normal mode and an abnormal mode based on a number of the plurality of peak signals. The switches blocks outputs of the plurality of clock signals in the abnormal mode. 1. A power voltage generating circuit comprising:an input part which receives a plurality of clock signals and generates a plurality of peak signals corresponding to rising edges of the plurality of clock signals;a clock determining part which determines a normal mode and an abnormal mode based on a number of the plurality of peak signals; anda plurality of switches which blocks outputs of the plurality of clock signals in the abnormal mode.2. The power voltage generating circuit of claim 1 , wherein the input part comprises:an input diode which receives a clock signal of the plurality of clock signals; andan input capacitor connected to the input diode in series.3. The power voltage generating circuit of claim 2 , wherein the clock determining part comprises:a peak detecting part which detects the plurality of peak signals;a mode determining signal generating part which generates a mode determining signal in response to the plurality of peak signals; anda comparing part which compares the mode determining signal and a mode reference voltage to generate a mode signal.4. The power voltage generating circuit of claim 3 , wherein the peak detecting part comprises an operation amplifier including a first input terminal connected to the input capacitor claim 3 , a second input terminal connected to a first power source and an output terminal claim 3 , andwherein the peak detecting part amplifies the plurality of peak signals to generate a plurality of second peak signals.5. The power voltage ...

CURRENT SOURCE AND DIGITAL TO ANALOG CONVERTER

The present disclosure relates to the technical field of semiconductors, and discloses a current source and a digital to analog convertor. The current source includes a current output circuit and an impedance gain circuit which is configured to increase output impedance of the current output circuit. The current output circuit includes a first PMOS transistor and a second PMOS transistor. The impedance gain circuit includes a first end, a second end, a third end which is connected to a supply voltage, and a fourth end which is connected to the ground. A source electrode of the first PMOS transistor is connected to the supply voltage, a drain electrode of the first PMOS transistor is connected to a source electrode of the second PMOS transistor and the first end of the impedance gain circuit, and a gate electrode of the first PMOS transistor is controlled by a first bias voltage. A gate electrode of the second PMOS transistor is connected to the second end of the impedance gain circuit, and a drain electrode of the second PMOS transistor serves as an output end of the current source. 1. A current source , comprising:a current output circuit, comprising:a first PMOS transistor; anda second PMOS transistor;an impedance gain circuit, configured to increase output impedance of the current output circuit, the impedance gain circuit comprising:a first end;a second end;a third end which is connected to a supply voltage; anda fourth end which is connected to a ground;wherein a source electrode of the first PMOS transistor is connected to the supply voltage, a drain electrode of the first PMOS transistor is connected to a source electrode of the second PMOS transistor and the first end of the impedance gain circuit, and a gate electrode of the first PMOS transistor is controlled by a first bias voltage; andwherein a gate electrode of the second PMOS transistor is connected to the second end of the impedance gain circuit, and a drain electrode of the second PMOS transistor ...

Circuit for generating reference voltage

Provided is a circuit for generating a reference voltage. The circuit includes a band gap circuit generating a first current having a size that increases in proportion to an absolute temperature and a second current having a size that decreases in proportion to the absolute temperature, and outputting a reference voltage based on the first current and the second current; a mirroring circuit mirroring a sum of the first current and the second current and outputting a mirroring voltage that is in proportion to the sum of the first current and the second current; and a start-up circuit receiving the mirroring voltage from the mirroring circuit and providing a driving current for generating the first current or the second current to the band gap circuit until a time when the first current starts to be generated in the band gap circuit.

FEEDBACK CIRCUIT FOR REGULATION LOOPS

In some examples, a device includes an amplifier circuit configured to receive a reference voltage signal at a first input, receive a feedback signal at a second input, and generate an output signal based on the reference voltage signal and the feedback signal. In some examples, the device also includes a feedback circuit including a soft-shaper circuit that is electrically connected to the second input of the amplifier circuit. In some examples, the feedback circuit is configured to sense a voltage step in the reference voltage signal, generate a voltage step across the soft-shaper circuit approximately equal to the voltage step in the reference voltage signal in response to sensing the voltage step in the reference voltage signal, and ramp a voltage level across the soft-shaper circuit to zero after generating the voltage step across the soft-shaper circuit. 1. A device comprising: receive a reference voltage signal at the first input of the amplifier circuit;', 'receive a feedback signal at the second input of the amplifier circuit; and', 'generate an output signal based on the reference voltage signal and the feedback signal; and, 'an amplifier circuit including a first input and a second input, wherein the amplifier circuit is configured to sense a voltage step in the reference voltage signal;', 'generate a voltage step across the soft-shaper circuit approximately equal to the voltage step in the reference voltage signal in response to sensing the voltage step in the reference voltage signal; and', 'ramp a voltage level across the soft-shaper circuit to zero after generating the voltage step across the soft-shaper circuit., 'a feedback circuit including a soft-shaper circuit that is electrically connected to the second input of the amplifier circuit, wherein the feedback circuit is configured to2. The device of claim 1 , wherein the feedback circuit is configured to ramp the voltage level across the soft-shaper circuit by at least causing the voltage level ...

VOLTAGE GENERATOR WITH MULTIPLE VOLTAGE VS. TEMPERATURE SLOPE DOMAINS

An electronic circuit is disclosed. The electronic circuit includes a reference voltage generator, which includes a first candidate circuit configured to generate a first candidate reference voltage, a second candidate circuit configured to generate a second candidate reference voltage, and a selector circuit configured to select one of the first and second candidate reference voltages. The reference voltage generator also includes a third circuit configured to generate a power supply voltage based on the selected candidate reference voltage. 1. An electronic circuit , comprising: a first candidate circuit configured to generate a first candidate reference voltage,', 'a second candidate circuit configured to generate a second candidate reference voltage, and', 'a selector circuit configured to select one of the first and second candidate reference voltages; and, 'a reference voltage generator, comprisinga third circuit configured to generate a power supply voltage based on the selected candidate reference voltage.2. The electronic circuit of claim 1 , wherein the first candidate circuit is configured to cause the first candidate reference voltage to change by an first amount in response to changing a temperature from a first temperature value to a second temperature value claim 1 , wherein the second candidate circuit is configured to cause the second candidate reference voltage to change by an second amount in response to changing the temperature from the first temperature value to the second temperature value claim 1 , and wherein the first amount is greater than the second amount.3. The electronic circuit of claim 2 , wherein the second amount is substantially zero.4. The electronic circuit of claim 2 , wherein claim 2 , at temperatures which are greater than a crossover temperature claim 2 , the first candidate reference voltage is greater than the second candidate reference voltage claim 2 , wherein claim 2 , at temperatures which are less than the crossover ...

HIGH PERFORMANCE I2C TRANSMITTER AND BUS SUPPLY INDEPENDENT RECEIVER, SUPPORTING LARGE SUPPLY VOLTAGE VARIATIONS

One or more embodiments are directed to inter-integrated circuit (I2C) transmitters, receivers, and devices that utilize a stable reference voltage for driving a pre-driver of the transmitter and for driving a first input stage of the receiver. One embodiment is directed to a device A device that includes an inter-integrated circuit (I2C) transmitter and an I2C receiver. The I2C transmitter includes a driver coupled to an I2C data line, and a pre-driver coupled to a variable first supply voltage, a second supply voltage, and a reference voltage. The pre-driver is configured to output a control signal to a control terminal of the driver. The I2C receiver includes a first stage coupled to the I2C data line, the variable first supply voltage, the second supply voltage, and the reference voltage. 1. An inter-integrated circuit (I2C) transmitter , comprising:an input terminal;an output terminal coupled to an I2C data line;a first supply voltage terminal coupled to a variable first supply voltage;a second supply voltage terminal coupled to a second supply voltage;a reference voltage terminal coupled to a reference voltage;a driver coupled to the output terminal; anda pre-driver coupled to the variable first supply voltage, the second supply voltage, and the reference voltage, the pre-driver configured to output a control signal to a control terminal of the driver based at least in part on an input signal at the input terminal, the control signal having a voltage level of one of the second supply voltage and the reference voltage.2. The I2C transmitter of wherein the driver includes an NMOS transistor connected in an open-drain configuration.3. The I2C transmitter of claim 1 , further comprising a multiplexer and level shifter coupled between the input terminal and the pre-driver claim 1 , the multiplexer and level shifter are coupled to the variable first supply voltage and to the second supply voltage.4. The I2C transmitter of wherein the pre-driver includes an inverter ...

Reference voltage generator

A reference voltage generator includes a mirroring circuit generating a first sub-voltage and a second sub-voltage that are constant, a first voltage generator including a first switch generating a first voltage based on the first sub-voltage, and a second voltage generator including a second switch generating a second voltage that is lower than the first voltage based on the second sub-voltage, wherein the second switch has a threshold voltage that is lower than the first switch to keep a voltage difference between the first voltage and the second voltage as a first reference voltage.

CMOS SUBTHRESHOLD REFERENCE CIRCUIT WITH LOW POWER CONSUMPTION AND LOW TEMPERATURE DRIFT

A resistorless CMOS low power voltage reference circuit is provided. The start-up circuit is used to prevent the circuit to stay in the zero state and stop working when the circuit gets out of the zero state. The self-biased Vgenerating circuit generate the voltage Vwhich has positive temperature coefficient. The square-law current generating circuit generates a square-law current which is proportional to μTthrough the V. Finally, the reference voltage Vis obtained by introducing the square-law current into the reference voltage output circuit. The reference voltage Vof this application can realize approximative zero temperature coefficient in the temperature range of −40° C. 100° C. This application improves temperature characteristic which may be poorer due to temperature nonlinearity of carrier mobility based on the traditional subthreshold reference. This application can reduce the power consumption from μW level to nW level and realize low power consumption. 1. A CMOS subthreshold reference circuit with low power consumption and low temperature drift , comprisinga start-up circuit;{'sub': 'PTAT', 'a self-biased Vgenerating circuit;'}a square-law current generating circuit; anda reference voltage output circuit,wherein{'sub': 'PTAT', 'an output terminal of the start-up circuit is connected to an input terminal of the self-biased Vgenerating circuit,'}{'sub': 'PTAT', 'the square-law current generating circuit is connected between the self-biased Vgenerating circuit and the reference voltage output circuit,'}{'sub': 'PTAT', 'the self-biased Vgenerating circuit provides the positive temperature coefficient voltage to generate a square-law current, and'}the square-law current is introduced into the reference voltage output circuit to obtain a reference voltage.2. The CMOS subthreshold reference circuit with low power consumption and low temperature drift according to claim 1 , whereinthe start-up circuit comprises a first NMOS transistor, a second NMOS transistor, a ...

Voltage Generator, a Method of Generating a Voltage and a Power-Up Reset Circuit

A voltage generator is provided which is reliable, self starting and only requires a few components. The voltage generator comprises a first stage that provides a current to a second stage. The first stage has a temperature coefficient of one sign, such as positive, and the second stage has an opposing temperature coefficient, e.g. negative. The responses are summed such that the overall temperature coefficient is reduced. 1. A voltage generator comprising first and second coupled stages , wherein the first stage has a voltage versus temperature characteristic which is opposite to a voltage versus temperature characteristic of the second stage , and in which the first stage comprises a first transistor having a gate , a drain and a source , and a first resistive element , wherein a first node of the first resistive element is connected to the source of the first transistor , a second node of the first resistive element is connected to the gate of the first transistor , and the first transistor is configured to pass a current when its gate voltage is approximately the same as its source voltage.2. A voltage generator as claimed in claim 1 , in which the second stage comprises a second transistor having a gate claim 1 , a drain and a source claim 1 , and wherein the gate of the second transistor is connected to the drain of the second transistor.3. A voltage generator as claimed in claim 2 , in which the second transistor is an enhancement mode transistor having a threshold voltage greater than 0V.4. A voltage generator as claimed in claim 1 , in which the first transistor is a native device or a depletion mode transistor.5. A voltage generator as claimed in claim 2 , in which the second stage further comprises a second resistor in series with the drain of the second transistor.6. A voltage generator as claimed in claim 1 , further comprising a cascode transistor in series between the first transistor and a supply rail for the first transistor.7. A voltage generator ...

HV MOS Leakage Compensation for Ultralow Current Operation

Various disclosed leakage compensation apparatus and methods enable HV MOS transistors to be employed for ultralow current operation. One illustrative embodiment is a backup energy block that includes: a pair of input terminals that couple to a backup energy source; an anti-series switch that supplies power from the pair of input terminals to a voltage regulator (when closed) and isolates power from the pair of input terminals to the voltage regulator (when open); a control current source; and an HV MOS control transistor that selectively couples the control current source to a control signal line to open and close the anti-series switch; and a compensation current source coupled to the control signal line to provide a compensation current matched to a parasitic leakage current from the control transistor. The compensation current source includes an HV MOS compensation transistor matched to the control transistor. 1. A control device with ultralow current requirements , the device comprising:a control signal line;a control current source;a high-voltage metal-oxide-semiconductor (“HV MOS”) control transistor that selectively couples the control current source to the control signal line, the control transistor further coupling a parasitic leakage current to the control signal line; anda compensation current source coupled to the control signal line to provide a compensation current, the compensation current source including an HV MOS compensation transistor that matches the compensation current to the parasitic leakage current.2. The control device of claim 1 , wherein the compensation transistor has a gate and a floating source shorted to the gate.3. The control device of claim 2 ,wherein the compensation transistor has a drain coupled to a drain of a second compensation transistor having a gate and a floating source shorted to the gate of the second compensation transistor,wherein the control transistor has a drain coupled to a drain of an additional transistor ...

APPARATUSES AND METHODS FOR PROVIDING BIAS SIGNALS ACCORDING TO OPERATION MODES AS SUPPLY VOLTAGES VARY IN A SEMICONDUCTOR DEVICE

Apparatuses and methods for providing bias signals in a semiconductor device are described. An example apparatus includes a power supply configured to provide a supply voltage and further includes a bias circuit coupled to the power supply to produce a bias current. The bias circuit is configured to decrease the bias current as the supply voltage increases from a first value to a second value. The bias circuit continues to decrease the bias current as the supply voltage further increases from the second value in a first operation mode. The bias circuit also prevents the bias current from decreasing against a further increase of the supply voltage from the second value in a second operation mode. 1. An apparatus , comprising:a power supply line configured to provide a supply voltage; and decrease the bias current as the supply voltage increases from a first value to a second value,', 'continue to decrease the bias current as the supply voltage further increases from the second value in a first operation mode, and', 'prevent the bias current from decreasing against a further increase of the supply voltage from the second value in a second operation mode., 'a bias circuit coupled to the power supply line to produce a bias current, the bias circuit configured to2. The apparatus of wherein the bias circuit is configured to increase the bias current as the supply voltage further increases from the second value in the second mode.3. The apparatus of claim 1 , further comprising:an additional power supply line configured to provide an additional supply voltage;first and second nodes;a first transistor coupled between the power supply line and the first node;a second transistor coupled between the first and second nodes;an impedance element coupled between the second node and the additional power supply line; anda third transistor coupled between the first and second nodes in parallel to the second transistor, the third transistor configured to be in an off state in the ...

POWER SUPPLY SYSTEM

A power supply system for an electronic device includes a first interface, a first switch, and a second switch. When the electronic device is not connected to the first interface, the switch circuit receives a first voltage level switch control signal based upon output of the first interface, the first switch turns on and outputs a second voltage level power control signal to the second switch, the second switch turns off and does not provide power to the electronic device via the first interface. When the electronic device is connected to the first interface, the switch circuit receives a second voltage level switch control signal based upon output of the first interface, the first switch turns off and outputs a first voltage level power control signal to the second switch, the second switch turns on and provides power supply to the electronic device via the first interface. 1. A power supply system comprising:a first interface configured to connect with an electronic device;a switch circuit comprising a first switch; anda power supply circuit comprising a second switch and configured to provide power supply to the electronic device via the first interface;wherein when the electronic device is not connected to the first interface, the switch circuit receives a first voltage level switch control signal based upon output of the first interface, the first switch turns on and outputs a second voltage level power control signal to the second switch, the second switch turns off and does not provide power supply to the electronic device via the first interface; andwherein when the electronic device is connected to the first interface, the switch circuit receives a second voltage level switch control signal based upon output of the first interface, the first switch turns off and outputs a first voltage level power control signal to the second switch, the second switch turns on and provides power supply to the electronic device via the first interface.2. The power supply ...

POWER SUPPLY SWITCHING CIRCUIT

Disclosed is a power supply switching circuit comprising: a first switch pair for selectively connecting a first power supply node to an output node, a second switch pair for selectively connecting a second power supply node to the output node; and a switch control circuit. The switch control circuit is operable such that a first switch of each of the first switch pair and the second switch pair is controlled by a respective first control signal and a second switch of each of the first switch pair and the second switch pair is controlled by a respective second control signal, so as to connect no more than one of the first power supply node or the second power supply node to the output node at any one time. 131-. (canceled)32. A power supply switching circuit comprising:a first switch pair for selectively connecting a first power supply node to an output node;a second switch pair for selectively connecting a second power supply node to the output node; anda switch control circuit configured such that a first switch of each of the first switch pair and the second switch pair is controlled by a respective first control signal and configured such that a second switch of each of the first switch pair and the second switch pair is controlled by a respective second control signal, such that one of the first power supply node and the second power supply node is connected to the output node at any one time.33. A power supply switching circuit as claimed in claim 32 , wherein the first switch and the second switch are connected in series claim 32 , such that claim 32 , in each of the first switch pair and the second switch pair claim 32 , an intrinsic body diode of the first switch and an intrinsic body diode of the second switch are oppositely connected.34. A power supply switching circuit as claimed in claim 32 , wherein the second control signal for the second switch of at least one of the first switch pair or the second switch pair receives is powered via the output node. ...

CURRENT GENERATION CIRCUIT

A current generation circuit includes: a current source circuit including a first transistor and a first resistor, and configured to output a first current based on a source voltage or a drain voltage of the first transistor and a resistance of the first resistor; a current control circuit including a voltage input terminal, a second transistor and a third transistor, and configured to output a second current based on a source voltage of the second transistor and a resistance of the third transistor; and an impedance circuit including a second resistor formed of a same resistive body as the first resistor and a fourth transistor diode-connected to the second resistor, and configured to generate a control voltage at the voltage input terminal by the first current and the second current, wherein the current generation circuit is configured to output a current based on the second current. 1. A current generation circuit comprising:a current source circuit comprising a first transistor having a gate to which a first bias voltage is supplied, and a first resistor connected to a source or drain of the first transistor, and configured to output a first current based on a source voltage or a drain voltage of the first transistor and a resistance of the first resistor;a current control circuit comprising a voltage input terminal, a second transistor having a gate to which a second bias voltage is supplied, and a third transistor connected to a source of the second transistor and having a gate to which a voltage of the voltage input terminal is supplied, the current control circuit being configured to output a second current based on a source voltage of the second transistor and a resistance of the third transistor; andan impedance circuit comprising a second resistor formed of a same resistive body as the first resistor, and a fourth transistor connected in series with the second resistor and having a gate and a drain being short-circuited, the impedance circuit being ...

INTEGRATED CIRCUITS HAVING CASCODE TRANSISTOR

An integrated circuit includes a first circuit. The first circuit includes a first transistor having a first dopant type. The first circuit further includes a first cascode transistor having the first dopant type, wherein the first cascode transistor connected in series with the first transistor. The first circuit further includes a second transistor having a second dopant type opposite to the first dopant type, wherein the second transistor is connected in series with the first transistor. The first circuit includes a second cascode transistor having the second dopant type, wherein the second cascode transistor is connected in series with the second transistor. The integrated circuit further includes a first bias circuit configured to adjust a threshold voltage of at least one of the first cascode transistor or the second cascode transistor. 2. The integrated circuit of claim 1 , further comprising a second bias circuit configured to adjust a threshold voltage of the second cascode transistor claim 1 , wherein the first bias circuit is configured to adjust the threshold voltage of the first cascode transistor.3. The integrated circuit of claim 1 , wherein the first bias circuit comprises:a first bias transistor having the second dopant type;a second bias transistor having the second dopant type, wherein the second bias transistor is connected in series with the first bias transistor, and a node between the first bias transistor and the second bias transistor is connected to a bulk of the first cascode transistor.4. The integrated circuit of claim 1 , wherein a gate of the first transistor is connected to a gate of the first cascode transistor.5. The integrated circuit of claim 1 , wherein a gate of the second transistor is connected to a gate of the second cascode transistor.6. The integrated circuit of claim 1 , further comprising a resistor between the second transistor and a ground voltage claim 1 , wherein the second transistor is between the resistor and the ...

Electronic Biasing Circuit for Constant Transconductance

An electronic biasing circuit provides a DC bias voltage to a circuit to be biased. The biasing circuit has a first transistor and a second transistor. A gate of the first transistor is connected to a gate of the second transistor and supplies the DC bias voltage. A source of the first transistor is connected to a supply reference voltage. A source of the second transistor is connected to the supply reference voltage via a resistor element. The currents flowing through the first and second transistor are forced to be equal. A third transistor is connected in series with the first transistor and a fourth transistor is connected in series with the second transistor. Currents flowing through the third and fourth transistors are forced to be equal.

Reference voltage generator and related method

A reference voltage generator may include the following elements: a first power supply terminal configured to receive a first power supply voltage; a second power supply terminal configured to receive a second power supply voltage; a reference voltage output node configured to provide a reference voltage; a first switch electrically connected between the first power supply terminal and the reference voltage output node; a second switch electrically connected between the second power supply terminal and the reference voltage output node; a first positive feedback module electrically connected to both the reference voltage output node and the first switch and configured to provide a first feedback voltage to the first switch; and a second positive feedback module electrically connected to both the reference voltage output node and the second switch and configured to provide a second feedback voltage to the second switch.

REFERENCE VOLTAGE CIRCUIT

A reference voltage circuit is provided, which includes bandgap reference circuit, bias current generator, first capacitor, second capacitor, comparator and control logic circuit. In the active mode of the control logic circuit, the control logic circuit controls the bandgap reference circuit to deliver bandgap reference voltage. The comparator transmits first comparison signal to control logic circuit when the first and second capacitors are charged to the bandgap reference voltage. The control logic circuit enters low power mode and controls the bandgap reference circuit to stop delivering the bandgap reference voltage. If the comparator detects the potential difference between the first capacitor and second capacitor exceeds the threshold value, the control logic circuit returns to active mode according to the second comparison signal transmitted form the comparator. 1. A reference voltage circuit , comprising:a bandgap reference circuit delivering a bandgap reference voltage and connected to a first switch and a second switch;a bias current generator connected to the bandgap reference circuit;a first capacitor connected between the first switch and a ground terminal;a second capacitor connected between the second switch and another ground terminal;a comparator having a first input terminal and a second input terminal respectively connected to the first capacitor and the second capacitor to compare a potential difference between the first capacitor and the second capacitor, wherein the bias current generator is connected to a power supply terminal of the comparator; anda control logic circuit connected between the comparator and the first switch and connected between the second switch and the bandgap reference circuit,wherein, in an active mode of the control logic circuit, the control logic circuit controls the first switch and the second switch to turn on, and controls the bandgap reference circuit to deliver the bandgap reference voltage to charge the first ...

SIGNAL RECEIVER, RELATED METHOD, AND RELATED ELECTRONIC DEVICE

A signal receiver may include the following elements: a first transmission gate connected to an signal input terminal and receiving a first reference voltage; a enable switch connected to a first power supply terminal and receiving a first enable signal; a p-channel transistor connected to the enable switch and the first transmission gate; a first protection switch connected to the p-channel transistor and receiving the first reference voltage; a second transmission gate connected to the signal input terminal and receiving a second reference voltage; an n-channel transistor connected to a second power supply terminal, an signal output terminal, and the second transmission gate; a second protection switch connected to the signal output terminal, the n-channel transistor, and the first protection switch and receiving the second reference voltage; and a pull-down transistor connected to the second power supply terminal, the n-channel transistor, and the output terminal and receiving a second enable signal. 1. A signal receiver comprising:a signal input terminal, which is configured to receive an input signal;a first power supply terminal, which is configured to receive a first power supply voltage;a second power supply terminal, which is configured to receive a second power supply voltage;a signal output terminal, which is configured to output an output signal;a first transmission gate, wherein a first terminal of the first transmission gate is electrically connected to the signal input terminal, and wherein a control electrode of the first transmission gate is configured to receive a first copy of a first reference voltage;an enable switch, wherein a first terminal of the enable switch is electrically connected to the first power supply terminal, and wherein a control electrode of the enable switch is configured to receive a first enable signal;a first p-channel transistor, wherein a first terminal of the first p-channel transistor is electrically connected to a ...

Cascoded semiconductor devices

The invention provides a cascode transistor circuit with a depletion mode transistor and a switching device. A gate bias circuit is connected between the gate of the depletion mode transistor and the low power line. The gate bias circuit is adapted to compensate the forward voltage of a diode function of the switching device. The depletion mode transistor and the gate bias circuit are formed as part of an integrated circuit.

Method for providing a voltage reference at a present operating temperature in a circuit

A method for providing a voltage reference at a present operating temperature in a circuit is provided. The circuit comprises a first MOS transistor having a first threshold voltage; and a second MOS transistor having a second threshold voltage different from the first threshold voltage is provided. Temperature insensitivity is obtained by compensating the difference between the first threshold voltage and the second threshold voltage with a parameter representative of the present operating temperature

FLIPPED GATE VOLTAGE REFERENCE AND METHOD OF USING

A voltage reference includes a flipped gate transistor configured to receive a first current. The voltage reference further includes a first transistor configured to receive a second current, the first transistor having a first leakage current, wherein the first transistor is connected with the flipped gate transistor in a Vgs subtractive arrangement. The voltage reference further includes an output node configured to output a reference voltage, the output node connected to the first transistor. The voltage reference further includes a second transistor connected to the output node, the second transistor having a second leakage current, wherein the first leakage current is substantially equal to the second leakage current. 1. A voltage reference comprising:a flipped gate transistor configured to receive a first current;a first transistor configured to receive a second current, the first transistor having a first leakage current, wherein the first transistor is connected with the flipped gate transistor in a Vgs subtractive arrangement;an output node configured to output a reference voltage, the output node connected to the first transistor; anda second transistor connected to the output node, the second transistor having a second leakage current, wherein the first leakage current is substantially equal to the second leakage current.2. The voltage reference of claim 1 , wherein a size of the flipped gate transistor is less than a size of the first transistor.3. The voltage reference of claim 1 , wherein a size of the first transistor is a first integer multiple of a transistor unit size claim 1 , and a size of the flipped gate transistor is a second integer multiple of the transistor unit size.4. The voltage reference of claim 1 , wherein the first current is greater than the second current.5. The voltage reference of claim 1 , wherein the flipped gate transistor is an n-type metal oxide semiconductor (NMOS) transistor claim 1 , the first transistor is an NMOS ...

Circuit starting method, control circuit and voltage reference circuit

A circuit starting method, a control circuit and a voltage reference circuit are provided. The control circuit includes an operational amplifier circuit and a comparison control circuit, wherein the operational amplifier circuit is arranged to establish an input reference voltage (VREF_INT) and an output reference voltage (VREF_OUT) by means of an operational amplifier (EA) and an external capacitor (C); and the comparison control circuit is arranged to, when the input reference voltage (VREF_INT) and the output reference voltage (VREF_OUT) are consistent, execute a toggle operation and output an enable signal (VREF_OK) to the operational amplifier (EA) so as to shut down the operational amplifier (EA).

Semiconductor integrated circuitry

The present invention relates to semiconductor integrated circuitry, and in particular to such circuitry where one or a plurality of similar or identical operating units are each operable to carry out an operation dependent on a reference signal. One example of such an operating unit is a sub-ADC unit of analogue-to-digital converter (ADC) circuitry, which employs one or more such sub-ADC units to convert samples of an input analogue signal into representation digital values. Where there are a plurality of sub-ADC units, they may each convert samples of an input analogue signal into representative digital values. They may also operate in a time-interleaved manner so that their conversion rate (from sample to digital value) can be lower than the overall sample rate by a factor of the number of sub-ADC units.

DIFFERENTIAL REFERENCE VOLTAGE BUFFER

The present disclosure provides a differential reference voltage buffer, including: a buffer stage, including at least a first transistor and a second transistor; a control circuit, connected with the buffer stage and forming a negative feedback structure for generating a differential reference voltage; a current compensation circuit for compensating a resistive load current of the control circuit; and a drive stage for generating an output differential reference voltage. The differential reference voltage is generated according to an external input reference voltage and a common mode input voltage. The common mode voltage can be set separately, so that the flexibility is high. The current generated by a resistive network in the control circuit is compensated by the current compensation circuit, so that the current of a follow device in the buffer stage is not influenced by the control circuit, thereby generating a differential reference voltage with high accuracy output. 1. A differential reference voltage buffer , comprising:a buffer stage, comprising at least a first transistor and a second transistor;a control circuit, connected with the buffer stage to form a negative feedback structure for generating a differential reference voltage; the control circuit comprises at least a first operational amplifier, a first resistor, a second resistor, and a common mode feedback circuit; the first operational amplifier includes two input ends, a first input end of the first operational amplifier is connected with a source of the first transistor and the common mode feedback circuit through the first resistor, and a second input end of the first operational amplifier is connected with a source of the second transistor and the common mode feedback circuit through the second resistor;a current compensation circuit, to compensate for a resistive load current of the control circuit; anda drive stage, to generate an output differential reference voltage.2. The differential ...

REFERENCE VOLTAGE GENERATING CIRCUIT AND DISPLAY DEVICE

Disclosed are a reference voltage generating circuit and a display device. The reference voltage generating circuit includes a timing control circuit, a digital-to-analog conversion circuit, an operational amplifier circuit, a drive circuit, a switch control circuit, a first switch circuit, and a second switch circuit. The switch control circuit generates a control signal according to a frame start signal and a clock signal provided by the timing control circuit, and outputs the control signal to the first switch circuit and the second switch circuit to control the channels inside the first switch circuit and the second switch circuit to be turned on sequentially, such that an analog voltage signal output by the digital-to-analog conversion circuit can be output to the drive circuit through the first switch circuit, the operational amplifier circuit and the second switch circuit, to provide a reference voltage signal for the drive circuit. 1. A reference voltage generating circuit , comprising:a timing control circuit;a digital-to-analog conversion circuit, provided with n voltage signal output terminals, and for providing an analog voltage signal;an operational amplifier circuit;a drive circuit;a switch control circuit, provided with a first signal input terminal, n second signal input terminals, n first signal output terminals and n second signal output terminals, wherein the first signal input terminal of the switch control circuit is connected to a frame signal output terminal of the timing control circuit, the n second signal input terminals of the switch control circuit are all connected to a clock signal output terminal of the timing control circuit; upon receiving a frame start signal output by the frame signal output terminal of the timing control circuit, and receiving a clock signal output by the clock signal output terminal of the timing control circuit, the switch control circuit is for outputting a high-level control signal from one of the n first ...

All-CMOS, Low-voltage, Wide-temperature Range, Voltage Reference Circuit

A CMOS voltage reference is disclosed. The CMOS voltage reference may include a PTAT current bias circuit including a start-up circuit, a core module implementing high order non-linear curvature compensation and an output stage supplying the reference voltage. The CMOS voltage reference may include a PTAT current bias circuit having a start-up and a CTAT feedback loop and a PTAT feedback loop and a compensating circuit summing the current from the CTAT feedback loop and the PTAT feedback loop.

FLIPPED GATE CURRENT REFERENCE

A current reference which includes a tracking voltage generator including a flipped gate transistor, a first transistor connected with the flipped gate transistor in a Vgs subtractive arrangement, an output node providing a tracking voltage which has a positive or negative temperature dependency based on the flipped gate transistor and the first transistor, and a second transistor connected to the output node; an amplifier to receive the tracking voltage and output an amplified signal; a control transistor to receive the amplified signal; a control resistor connected in series with the control transistor; and a current mirror to receive and mirror a reference current to at least one external device, the current mirror including mirroring pairs having a corresponding mirroring resistor coupled in series with a corresponding mirroring transistor, the mirroring resistor of at least one of the mirroring pairs having a serpentine structure. 1. A current reference comprising: a flipped gate transistor;', 'a first transistor connected with the flipped gate transistor in a Vgs subtractive arrangement;', 'an output node configured to output a tracking voltage which has a positive or negative temperature dependency based on the flipped gate transistor and the first transistor; and', 'a second transistor connected to the output node;, 'a tracking voltage generator, the tracking voltage generator includingan amplifier configured to receive the tracking voltage and to output an amplified signal;a control transistor configured to receive the amplified signal;a control resistor connected in series with the control transistor; anda current mirror configured to receive a reference current based on a conductivity of the control transistor, wherein the current mirror is further configured to mirror the reference current to at least one external device, the current mirror including mirroring pairs, each mirroring pair including a corresponding mirroring resistor coupled in series with ...

METHODS AND APPARATUS FOR DRIVER CALIBRATION

Various embodiments of the present technology may comprise methods and apparatus for driver calibration. The methods and apparatus may comprise various circuits and/or systems to minimize an offset output current (e.g., a drive current) due to an offset voltage in an operational amplifier. The methods and apparatus may comprise a current comparator circuit and a replica circuit that operate in conjunction with each other to monitor the drive current and provide a feedback signal, which is then used to adjust the drive current and improve the accuracy of the drive current. 1. A circuit , comprising: a first node having a first voltage; and', 'a second node having a second voltage;, 'a current comparator circuit comprising a first terminal responsive to the second voltage; and', 'a second terminal connected to a reference voltage; and, 'a driver comprising a third terminal connected to the first node;', 'a fourth terminal connected to the second terminal of the driver; and', 'a fifth terminal connected to the first terminal of the driver., 'a replica circuit comprising2. The circuit according to claim 1 , wherein the replica circuit generates a replica current that is proportional to the drive current3. The circuit according to claim 1 , wherein the current comparator circuit comprises a first transistor and a second transistor connected in series with each other.4. The circuit according to claim 3 , wherein the first node is located between the first transistor and the second transistor.5. The circuit according to claim 3 , wherein the second node is located between the second transistor and the third transistor.6. The circuit according to claim 1 , wherein the current comparator circuit generates a comparator output voltage at the second node.7. The circuit according to claim 1 , wherein the replica circuit comprises a transistor and the third terminal is a drain terminal claim 1 , the fourth terminal is a source terminal claim 1 , and the fifth terminal is a gate ...

SWITCH CONTROL CIRCUIT AND SWITCH CIRCUIT

A switch control circuit includes a plurality of first voltage generation circuits that generate a plurality of second control signals by level-shifting a plurality of first control signals using a reference voltage. A plurality of cut-off circuits controlling whether or not to supply the reference voltage to a corresponding one of the plurality of first voltage generation circuits. A control circuit is configured to control the cut-off circuits in such a manner that the reference voltage supplied to at least one first voltage generation circuit is cut off to the other first voltage generation circuits after a state of the first control signal supplied to the at least one first generation circuit is changed. In some embodiments, the reference voltage to the other first generation circuits is cut-off for a predetermined time period. 1. A switch control circuit , comprising:a plurality of first voltage generation circuits configured to generate a plurality of second control signals by level-shifting a plurality of first control signals using a reference voltage;a plurality of cut-off circuits configured to connect and disconnect the reference voltage to or from a corresponding one of the plurality of first voltage generation circuits; anda control circuit configured to control the plurality of cut-off circuits such that at least one first voltage generation circuit in the plurality of first voltage generation circuits is disconnected from the reference voltage when a state of a first control signal of at least one other first voltage generation circuit in the plurality of first voltage generation circuits changes.2. The switch control circuit according to claim 1 , wherein the at least one first voltage generation circuit is disconnected from the reference voltage for a predetermined time period when the state of the first control signal of the at least one other first voltage generation circuit changes.3. The switch control circuit according to claim 1 , further ...

CONSTANT VOLTAGE GENERATING CIRCUIT

A constant voltage generating circuit includes an ED-type reference voltage supply that generates a predetermined constant voltage by using a first transistor of depletion-type and a second transistor of enhancement-type that are connected in series between a power supply terminal and a ground terminal, and a third transistor a source of which is connected to an output terminal for the constant voltage, a drain of which is connected to the power supply terminal or the ground terminal, and a gate of which is connected to a connection node between the first transistor and the second transistor. 1. A constant voltage generating circuit comprising:a first transistor that is an N-channel depletion type transistor of which a drain is connected to a power supply terminal and of which a source and a gate are commonly connected;a second transistor that is an N-channel enhancement type transistor of which a drain is connected to the source and the gate of the first transistor, of which a source is connected to a ground terminal, and of which a gate is connected to an output terminal for a constant voltage; anda third transistor of which a source is connected to the output terminal for the constant voltage, of which a drain is connected to the power supply terminal or the ground terminal, and of which a gate is connected to the gate of the first transistor to form a common gate.2. The constant voltage generating circuit according to claim 1 , further comprising:a first resistor that is connected between the output terminal for the constant voltage and the gate of the second transistor; anda second resistor that is connected between the ground terminal and the gate of the second transistor.3. The constant voltage generating circuit according to claim 1 , wherein the third transistor is equipped with a greater current supplying ability than the first transistor and the second transistor.4. The constant voltage generating circuit according to claim 1 , wherein the third ...

CONFIGURABLE OFFSET COMPENSATION DEVICE

An offset compensation device includes a first bias module and a second bias module. The first bias module includes a plurality of first current control circuits and a plurality of second current control circuits coupled in parallel. Each of the first current control circuits generates a first reference current, and each of the second current control circuits generates a second reference current. The second bias module includes a plurality of third current control circuits and a plurality of fourth current control circuits coupled in parallel. Each of the third current control circuits generates a third reference current, and each of the fourth current control circuits generates a fourth reference current. The second reference current is greater than the first reference current, and the fourth reference current is greater than the third reference current. 1. An offset compensation device comprising: a plurality of first current control circuits each configured to generate a first reference current; and', 'a plurality of second current control circuits each configured to generate a second reference current; and, 'a first bias module coupled to a first bias node and comprising a plurality of third current control circuits each configured to generate a third reference current; and', 'a plurality of fourth current control circuits each configured to generate a fourth reference current;, 'a second bias module coupled to a second bias node and comprisingwherein:the plurality of first current control circuits and the plurality of second current control circuits are coupled in parallel and coupled to the first bias node;the plurality of third current control circuits and the plurality of fourth current control circuits are coupled in parallel and coupled to the second bias node; andthe second reference current is greater than the first reference current, and the fourth reference current is greater than the third reference current.2. The offset compensation device of claim 1 ...

SWITCHED CAPACITOR BIASING CIRCUIT

Bias circuit and a bias generator circuit comprising such a bias circuit. The bias circuit () comprises a switched capacitor resistor circuitry (C, C, M-M), and an operational amplifier (M-M, M) with an input differential transistor pair (M, M). The bias circuit further comprises additional source follower transistors (M, M) associated with the first and second input differential transistors (M, M). The bias generator circuit has a PMOS switched capacitor reference circuit () and a NMOS switched capacitor reference circuit () and a transconductor reference cell (). The transconductor reference cell () is a replica of a basic reference cell used in a further circuit. 1. Biasing generator circuit comprising:a PMOS switched capacitor reference circuit and a NMOS switched capacitor reference circuit, of which respective outputs are connected to a combiner element, and a transconductor reference cell receiving an output of the combiner element,wherein the transconductor reference cell is a replica of a basic reference cell used in a further circuit, andthe biasing generator circuit is arranged to provide a bias output to the further circuit.2. Biasing generator circuit according to claim 1 , wherein the transconductor reference cell comprises a PMOS transistor and a NMOS transistor claim 1 , wherein the PMOS transistor has a gain factor Kand the NMOS transistor has a gain factor K claim 1 , wherein K=K.3. Biasing generator circuit according to claim 1 , further comprising a low-drop out (LDO) regulator circuit connected to an output of the transconductor reference cell.4. Biasing generator circuit according to claim 1 , wherein the further circuit is a continuous time gm-C filter circuit.5. Biasing generator circuit according to claim 1 , wherein the further circuit is a ring oscillator circuit.6. Biasing generator circuit according to claim 2 , further comprising a low-drop out (LDO) regulator circuit connected to an output of the transconductor reference cell.7. ...

POWER SUPPLY CONTROL DEVICE

A power supply control device includes a switch disposed in a first current path of a current flowing from a battery. A first comparator compares a voltage value of a current input end of the switch to which the current is inputted with a voltage threshold. When the voltage value of the current input end is less than the voltage threshold, a drive circuit turns off the switch. The battery supplies, via a second current path, power to a starter that starts an engine of a vehicle. The voltage threshold is less than the voltage value of the current input end of the switch in the case where the battery supplies the power to the starter. 1. A power supply control device , comprising:a switch disposed in a first current path of a current flowing from a direct-current (DC) power source;a comparison unit configured to compare a voltage value of a current input end of the switch to which the current is inputted with a voltage threshold; anda switching unit configured to turn off the switch when the comparison unit indicates that the voltage value of the current input end is less than the voltage threshold,wherein the DC power source is configured to supply, via a second current path, power to a starter that starts an engine of a vehicle, andthe voltage threshold is less than the voltage value of the current input end in a case where the DC power source supplies the power to the starter.2. The power supply control device according to claim 1 , comprising:a capacitor having one end connected to the current input end of the switch;a resistance having one end connected to the other end of the capacitor; anda DC voltage source having a negative terminal connected to a connection node between the capacitor and the resistance,wherein the voltage threshold is a voltage value of a positive terminal of the DC voltage source, andthe switching unit is configured to turn off the switch when the comparison unit indicates continuously for at least a predetermined period that the voltage ...

Reference voltage circuit and semiconductor device

A reference voltage circuit includes a first MOS transistor pair having a first MOS transistor of an enhancement type having a gate and a drain connected to each other, and a second MOS transistor of a depletion type having a gate connected to a source of the first MOS transistor, a source connected to the drain of the first MOS transistor, and a drain connected to an output terminal; and a second MOS transistor pair having a third MOS transistor of an enhancement type having a gate and a drain connected to the output terminal and a source connected to the source of the second MOS transistor, and a fourth MOS transistor of a depletion type having a gate connected to the source of the third MOS transistor and a source connected to the output terminal. All the MOS transistors operate in a weak inversion region.

SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM, AND CONTROL SYSTEM

A semiconductor device includes: a drive transistor controlling current supply to a load; a current detector unit detecting a current of a sense transistor through which a current proportional to the current flowing through the drive transistor flows; a controller unit generating a pulse signal with a duty ratio corresponding to the detection result of the current detector unit; a voltage monitor monitoring whether a voltage of an external output terminal reaches a battery voltage; and a pre-driver performing charge and discharge to a control terminal of the drive transistor based on the pulse signal. The pre-driver performs the charge and discharge to the control terminal of the drive transistor at a first speed, when the voltage of the external output terminal reaches the battery voltage, and at a speed faster than the first speed, when the voltage of the external output terminal reaches the battery voltage. 2. The semiconductor device according to claim 1 , further comprising:a current detector unit that includes the first sense transistor; anda controller unit to generate the first pulse signal corresponding to a value of the current detected by the current detector unit.3. The semiconductor device according to claim 2 ,wherein the pre-driver comprises:a first switching unit to control the charge and discharge to the control terminal of the first drive transistor based on the first pulse signal; anda second switching unit to control the charge and discharge to the control terminal of the first drive transistor based on the first pulse signal in cooperation with the first switching unit, when the voltage of the external output terminal has reached the prescribed voltage.4. The semiconductor device according to claim 3 ,wherein the second switching unit performs the charge and discharge to the control terminal of the first drive transistor at a charge and discharge speed faster than the charge and discharge speed in the first switching unit.5. The semiconductor ...

FLIPPED GATE CURRENT REFERENCE AND METHOD OF USING

A tracking voltage generator, the latter including: a first transistor having a first leakage current and which is coupled with the flipped gate transistor so that a difference between a gate-source voltage (Vgs) of a flipped gate transistor and the first transistor is approximately equal to a bandgap voltage of a semiconductor material from which the tracking voltage generator is formed; an output node providing a tracking voltage which has a positive or negative temperature dependency based on the flipped gate transistor and the first transistor; and a second transistor connected to the output node and which has a second leakage current. A current reference includes: the tracking voltage generator; an amplifier to receive the tracking voltage and output an amplified signal; a control transistor to receive the amplified signal and conduct a reference current therethrough; and a control resistor connected in series with the control transistor. 1. A current reference comprising: a flipped gate transistor;', 'a first transistor, the first transistor having a first leakage current, wherein the first transistor is coupled with the flipped gate transistor in an arrangement wherein a difference between a gate-source voltage (Vgs) of the flipped gate transistor and the first transistor is approximately equal to a bandgap voltage of a semiconductor material from which the tracking voltage generator is formed;', 'an output node configured to output a tracking voltage, the tracking voltage having a positive or negative temperature dependency based on the flipped gate transistor and the first transistor; and', 'a second transistor connected to the output node, the second transistor having a second leakage current;, 'a tracking voltage generator, the tracking voltage generator comprisingan amplifier configured to receive the tracking voltage and to output an amplified signal;a control transistor configured to receive the amplified signal and to conduct a reference current ...

MOS CAPACITORS FLOW TYPE DEVICES AND METHODS OF FORMING THE SAME

A capacitor structure is described. The capacitor structure includes a substrate; a source/drain region formed in the substrate to form an active area, the active area having an active area width; and at least two gates formed above the substrate. The at least two gates having a gate width. The gate width is configured to be less than the active area width. And, the at least two gates are formed such that the source/drain region is between the two gates to form at least one channel between the two gates. 1. A capacitor structure comprising:a substrate;a source/drain region formed in said substrate to form an active area, said active area having an active area width; andat least two gates formed above said substrate, said at least two gates having a gate width, said gate width configured to be less than said active area width, said at least two gates formed such that said source/drain region is between said two gates to form at least one channel between said two gates.2. The capacitor structure of claim 1 , wherein said substrate is an silicon-on-insulator substrate.3. The capacitor structure of claim 1 , wherein said plurality of source/drain regions claim 1 , said first plurality of gates claim 1 , and said second plurality of gates are interconnected to form one or more pairs of capacitors connected in an anti-series configuration.4. The capacitor structure of claim 1 , wherein said plurality of source/drain regions claim 1 , said first plurality of gates claim 1 , and said second plurality of gates are interconnected to form a variable capacitor cell of a variable capacitor array.5. The capacitor structure of claim 4 , wherein the variable capacitor cell is part of an integrated circuit.6. The capacitor structure of claim 1 , wherein said plurality of source/drain regions claim 1 , said first plurality of gates claim 1 , and said second plurality of gates are interconnected to form a plurality of variable capacitor cells of a variable capacitor array.7. A method ...

MOS CAPACITORS FOR VARIABLE CAPACITOR ARRAYS AND METHODS OF FORMING THE SAME

A capacitor structure is described. The capacitor structure includes a substrate, a plurality of source/drain regions formed in the substrate, and a plurality of gates formed above the substrate. The plurality of gates formed above the substrate such that each of the plurality of gates is formed between each pair of source/drain regions of the plurality of source/drain regions to form a channel between each pair of source/drain regions. 1. A capacitor structure comprising:a substrate;a plurality of source/drain regions formed in said substrate; anda plurality of gates formed above said substrate such that each of said plurality of gates is formed between each pair of source/drain regions of said plurality of source/drain regions to form a channel between said each pair of source/drain regions.2. The capacitor structure of claim 1 , wherein said substrate is an silicon-on-insulator substrate.3. The capacitor structure of claim 1 , wherein said plurality of source/drain regions and said plurality of gates are interconnected to form one or more pairs of capacitors connected in an anti-series configuration.4. The capacitor structure of claim 1 , wherein said plurality of source/drain regions and said plurality of gates are interconnected to form a variable capacitor cell of a variable capacitor array.5. The capacitor structure of claim 4 , wherein the variable capacitor cell is part of an integrated circuit.6. The capacitor structure of claim 1 , wherein said plurality of source/drain regions and said plurality of gates are interconnected to form a plurality of variable capacitor cells of a variable capacitor array.7. A method to form a plurality of capacitors comprising:forming a plurality of source/drain regions in a substrate; andforming a plurality of gates above said substrate such that each of said plurality of gates is formed between each pair of source/drain regions of said plurality of source/drain regions to form a channel between said each pair of source/ ...

MOS CAPACITORS WITH HEAD-TO-HEAD FINGERS AND METHODS OF FORMING THE SAME

A capacitor structure is described. The capacitor structure includes a substrate, a plurality of source/drain regions, a first plurality gates, and a second plurality of gates. The plurality of source/drain regions is formed in the substrate. The first and second plurality of gates is formed above the substrate. Each gate of the first and second plurality of gates has a gate width. The gate widths are configured to be less than an active area width and each gate of the first and second plurality of gates is formed between a pair of the source/drain regions of the plurality of source/drain regions. And, each gate of the first plurality of gates is configured to be in line with a corresponding gate of the second plurality of gates to form a head-to-head gate configuration. 1. A capacitor structure comprising:a substrate;a plurality of source/drain regions formed in said substrate to form an active area, the active area having an active area width;a first plurality of gates formed above said substrate, each gate of said first plurality of gates having a first gate width, said first gate width configured to be less than said active area width, each gate of said first plurality of gates formed between a pair of source/drain regions of said plurality of source/drain regions; anda second plurality of gates formed above said substrate, each gate of said second plurality of gates having a second gate width, the second gate width configured to be less than said active area width, each gate of said second plurality of gates formed between a pair of source/drain regions of said plurality of source drain regions such that each gate of said first plurality of gates is configured to be in line with a corresponding gate of said second plurality of gates to form a head-to-head gate configuration.2. The capacitor structure of claim 1 , wherein said substrate is an silicon-on-insulator substrate.3. The capacitor structure of claim 1 , wherein said plurality of source/drain regions ...