МЕХАНИЗМ ОБРАБОТКИ ПРЕРЫВАНИЙ В КОМПЬЮТЕРНЫХ СИСТЕМАХ, ПОДДЕРЖИВАЮЩИХ ОДНОВРЕМЕННОЕ ИСПОЛНЕНИЕ МНОЖЕСТВА ПОТОКОВ

... 1. Процессор, содержащий первый блок обработки прерываний для предписывания первому логическому процессору выполнить подпрограмму обработки прерываний в ответ на прерывание; второй блок обработки прерываний для предписывания второму логическому процессору выполнить подпрограмму обработки прерываний в ответ на прерывание; и регистр заявок на прерывания для хранения значения, которое показывает, должны ли первый и второй логические процессоры обрабатывать прерывание. 2. Процессор по п.1, в котором первый и второй логические процессоры считывают значение из регистра заявок на прерывания под управлением подпрограммы обработки прерываний. 3. Процессор по п.2, в котором первый логический процессор обрабатывает прерывание, если он первым считывает регистр заявок на прерывания. 4. Процессор по п.2, в котором второй логический процессор завершает подпрограмму обработки прерываний, если первый логический процессор обрабатывает прерывание. 5. Процессор по п.4, в котором второй логический процессор ...

СПОСОБ ДОСТАВКИ ПРЕРЫВАНИЙ В ДРАЙВЕРЫ ПОЛЬЗОВАТЕЛЬСКОГО РЕЖИМА

... 1. Способ независимой от устройства обработки прерываний, содержащий этапы, на которых: ! регистрируют драйвер устройства в операционной системе; ! предоставляют независимую от устройства службу прерывания как службу ядра; ! предоставляют интерфейс, который вызывается упомянутым драйвером, чтобы активировать прерывание; ! выполняют общую процедуру службы прерывания при получении упомянутого прерывания; и ! обрабатывают упомянутое прерывание посредством упомянутого драйвера устройства. ! 2. Способ по п.1, дополнительно содержащий этапы, на которых: ! маскируют упомянутое прерывание в процессоре до выполнения упомянутой процедуры службы прерывания; ! блокируют упомянутое прерывание на более низком уровне чем уровень упомянутого процессора, чтобы предотвратить ситуацию, когда упомянутое прерывание достигает упомянутого процессора; ! демаскируют упомянутое прерывание в упомянутом процессоре; и ! активируют упомянутое прерывание на упомянутом более низком уровне, чем уровень упомянутого процессора ...

Устройство для обмена данными между процессором и периферийными устройствами

УСТРОЙСТВО ДЛЯ ОБМЕНА ДАННЫМИ МЕВДУ ПРОЦЕССОРОМ И ПЕРИФЕРИЙ- . НЫМИ УСТРОЙСТВАМИ, содержащее генератор синхроимпульсов, память команд , адресньй выход процессора соединён с адресным входом памяти команд , информационные выходы которой соединены с информационной шиной процессора, первый выход генератора синхроимпульсов соединен с входом синхронизации процессора , о тличающее ся тем,, что, с целью упрощения устройства за счет сокращения линий связи, введены память данных,таймер,буферный регистр , элемент ИЛИ,два элемента НЕ,элемент , два элемента И-НЕ, причем выход буферного регистра является адресным выходом устройства , информационные входы - выходы памяти данных и таймера соединены с информационной шиной процессора , выход первого элемента НЕ является выходом записи устройства , вход первого элемента НЕ соединен с входом записи таймера, входом разрешения записи памяти данных и с выходом управления записью процессора, выход управления чтением которого соединен с входом чтения таймера, адресные ...

Устройство для сопряжения двух вычислительных машин

Изобретение относится к вычислительной технике и может быть ис - пользовано в вычислительных комплексах , иостроенных на базе специалР зи- рованной вычислительной системы. Целью изобретения является повьаиеиие достоверности за счет устранения влияния импульсных помех. Устройство содержит регистр 1 сдвига, два регистра 8 и 9, две группы 2 и 3 элементов И, счетчик 5 импульсов, одновибратор 6, тактовый генератор 26, счетчик 25, элемент ИЛИ 7, элемент И 4. 2 ил. to CD СП 4 Фиг.1 ...

Устройство для сопряжения процессора с устройствами ввода-вывода

Изобретение относится к области вычислительной техники и может быть использовано в вычислительных системах обработки и подготовки данных. для согласования интерфейсов устройств ввода-вывода и процессора, имеющих различный набор сигналов .и протокол обмена информацией. Целью изобретения является расширение класса сопрягаемых устройств за счет увеличения длины формируемых последова-- тельностей управляющих сигналов и по- вьппение помехозащищенности при работе в режиме опроса. Устройство содержит у.зел при- мопередачи, дешифратор команд, узел синхронизации, учел формирования прерываний, узел обработки кода обратной связи, регистр инструкции , входной и выходной информационные регистры, входной и выходной управляющие регистры. 2 з.п. ф-лы, 7 ил. Р.

Устройство для сопряжения ЭВМ с общей магистралью

Изобретение относится к вычислительной технике и может быть использовано в многомашинных или многопроцессорных вычислительных системах с магистральной структурой обмена информацией. Целью изобретения является сокращение аппаратурных затрат. Устройство содержит два пpиe,o- передатчика, приемник, два передатчика, дешифратор адреса, регистр команд, регистр адреса приемника, регистр состояния, регистр данных источника, регистр данных при емника, регистр адреса, блок прерывания, блок захвата магистрали, три триггера, два элемента И, группу элементов И, два элемента НЕ, элемент сравнения. 5 ил.

Устройство для сопряжения периферийных устройств с ЭВМ

Изобретение относится к вычислительной технике, в частности к устройствам для передачи информации между центральным процессором и устройствами ввода-вывода, и может быть использовано в автоматизированных системах управления и системах сбора данных. Целью изобретения является сокращение аппаратурных затрат. Устройство содержит два блока 1, 2 приемопередатчиков , блок 3 обмена, шифратор 4 адреса, блок 5 прерывания, шифратор 6 вектора прерывания, блок |7 коммутации. 1 з.п. ф-лы, 4 ил.

Verfahren und Vorrichtung zur Verarbeitung von Ein-/Ausgabeanforderungen von mehreren Host-Rechnern

Vefahren und Vorrichtung zur Ein-/Ausgabeanforderungsverarbeitung mit einer Mehrzahl von Kanalbussen

ANWENDUNGS-SOFTWARE FÜR HARDWARE-UNTERBRECHUNGEN.

Mikroprogrammablaufsteuerung.

SCHALTUNGSANORDNUNG ZUR STEUERUNG DER BIDIREKTIONALEN DATENUEBERTRAGUNG ZWISCHEN EINER RECHNEREINHEIT UND UEBER EIN-/AUSGABEEINHEITEN ANGESCHLOSSENEN UEBERTRAGUNGSLEITUNGEN.

Bidirectional transmission of data between a data processor (RE) and input/output units (EE,AE) is made using buffer memory modules (ZP1,ZP2). A bit serial transmission of 4,096Mbit/sec uses one buffer (SP1) that receives a word structure entry and is transported by reading the other memory. Both memories are coupled to the processor data bus (ADB) and to the input/output units over PCM lines. The memories have a capacity for storing 12 sixteen bit data words. Entries and outputs from the buffer memories are controlled by threshold logic units (SL1,SL2) coupled to the address bus and to an interrupt control stage ((RL) connected to the processor. The threshold units control the capacity of the memory.

VORRICHTUNG UND VERFAHREN ZUR UMSCHALTUNG ZWISCHEN PROZESSEN

Erzeugung von einer logischen APIC-ID mit Cluster ID und Intra-Cluster ID

Beansprucht ist Folgendes: Vorrichtung, die Folgendes umfasst: Erzeugungslogik für eine logische Interruptidentifikationsnummer zum: Empfangen physikalischer Prozessoridentifikationsnummern; und Erzeugen logischer Prozessoridentifikationsnummern unter Verwendung der physikalischen Prozessoridentifikationsnummern, wobei jede der logischen Prozessoridentifikationsnummern einer der physikalischen Prozessoridentifikationsnummer entspricht, und wobei die logische Prozessoridentifikationsnummern jeweils eine Prozessorclusteridentifikationsnummer und eine Intra-Cluster-Identifikationsnummer aufweisen, und wobei die Prozessorclusteridentifikationsnummern jeweils so gebildet sind, dass sie eine Gruppe von Bits aus der entsprechenden physikalischen Prozessoridentifikationsnummer aufweisen, die in der Position verschoben ist, und die Intra-Cluster-Identifikationsnummern in Reaktion auf Werte von anderen der Bits gebildet sind, die der physikalischen Prozessoridentifikationsnummer entsprechen.

VERFAHREN UND ANORDNUNG ZUR UEBERWACHTEN UEBERGABE VON STEUERSIGNALEN AN SCHNITTSTELLEN DIGITALER SYSTEME

MEHRRECHNERSYSTEM

Verfahren zur Erzeugung von Unterbrechungsbefehlen in einem Mikroprozessorsystem und bezügliches Prioritätsunterbrechungssteuerungsgerät

Vorrichtung zum Behandeln von Interruptereignissen, mit der pegel-sensitive bzw. level-sensitive Interruptanforderungen in flankengetriggerten Interruptnachrichten umgesetzt werden

Vorrichtung zum Behandeln von Interruptereignissen mit: einer Interrupteingangseinheit (210) zum Empfangen level-sensitiver Interruptanforderungen und zum Erzeugen von Anforderungserkennungssignalen daraus, wobei jedes Anforderungserkennungssignal anzeigt, dass eine level-sensitive Interruptanforderung empfangen wurde; einer Flankenerfassungseinheit (220), die mit der Interrupteingangseinheit (210) verbunden ist, um die Anforderungserkennungssignale zu empfangen und um Startsignale für flankengetriggerte Interruptnachrichten auf der Grundlage der empfangenen Anforderungserkennungssignale zu erzeugen; und einer Interruptbeendigungserfassungseinheit (200) zum Empfangen von Abschlusssignalen, die jeweils anzeigen, dass eine Interruptroutine (110), die sich auf eine durch eine vorhergehende level-sensitive Interruptanforderung ausgelöste flankengetriggerte Interruptnachricht bezieht, abgeschlossen ist, wobei die Interruptbeendigungserfassungseinheit (200) die Interrupteingangseinheit (210) ...

DATA PORT

COMPUTER SYSTEM WITH MODE CONVERSION OF COMPUTER COMMANDS

PCI to ISA interrupt protocol converter and selection mechanism

PLURAL PROCESSOR SYSTEMS HAVING SHARED RESOURCES

A co-processor is connectable to a main system data bus to run software unknown to the main processor. The main processor can concurrently run other software and maintains priority over shared I/O facilities by providing trapping logic incorporated in a random access memory and dynamically loadable by the master processor which contains data related to the current useability by the co-processor of a shared I/O device. Additional logic is associated with the co-processor to manage interrupts between the co-processor and the system bus.

Programmable multi-processor interrupt controller system with a processor integrated local interrupt controller

PURPOSE: To deal with the problem of optimum dynamic and static interruption service in a multiprocessor system. CONSTITUTION: A multiprocessor programmable interruption controller system is provided with an I/O interruption controller for receiving an interruption request from an I/O sub-system, plural processor interruption controllers which are related with the specified processor and distribute received interruptions and an interruption controller bus 103 for mainly transmitting the interruption requests between the interruption controllers by using a standard message format and an arbitration protocol and for arbitrating a bus and priority.

Control of access to a shared resource in a data processing apparatus

A data processing apparatus comprises a plurality of processors operable to perform respective data processing operations requiring access to the shared resource, and a path interconnecting the plurality of processors. An access control mechanism is operable to control access to the shared resource by the plurality of processors, each processor being operable to enter a power saving mode if access to the shared resource is locked. Further, each processor is operable, when that processor has access to the shared resource, to issue a notification on the path when access to the shared resource is no longer required by that processor. A processor in the power saving mode is arranged, upon receipt of that notification, to exit the power saving mode and to seek access to the shared resource.

Method and apparatus for sharing an interrupt between disk drive interfaces

An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry that masks an interrupt signal coming from the parallel storage device interface if no storage device is coupled to the parallel storage device interface. The masking of the parallel storage device interface interrupt of no storage device is coupled to the parallel storage device interface allows the controller for the serial storage device interface to share the interrupt traditionally assigned to the parallel storage device interface.

Interrupt processing device

Hot plug device

Mechanism for interrupt handling in computer systems that support concurrent execution of multiple threads

Method and apparatus for avoiding race condition with edge-triggered interrupts

Providing multiple virtual device controllers by redirecting an interrupt from a physical device controller

Processor, which stores interrupt enable flags in a location used for other functions

When a processor is interrupted, it stores its interrupt enable flags l in a location C which is used to store other values at other times. At the end of the interrupt, the interrupt enable flags are restored. When not in an interrupt, the location may be used to store a carry or overflow flag. Both the location and the interrupt flags may be stored in the same processor status register 134-1. The flags may be copied to the location in a single clock cycle. The interrupt enable flags may also be pushed onto the stack when the processor is interrupted.

Method of and circuit arrangement for supplying interrupt request signals

A circuit arrangement for supplying interrupt requests signals from a peripheral unit to a central processing unit of a computer system over a common control line, without a priority scheme. A blocking circuit is provided such that the first interrupt signal on the common control line blocks any further interrupt signals on that line until the interrupt has been processed. Since no further interrupts are possible, the interrupt acknowledged signal from the central processing unit need not contain the address of the external unit having requested the interrupt nor need there be provided a circuit to process the interrupt acknowledge signal in the peripheral unit. An interrupt signal present on the common interrupt line blocks generation of subsequent interrupt signals from reaching the common interrupt line by a combination of the two interrupting switches together with a delay after the first switch. The station generating the first interrupt signal contains the means for blocking the reception ...

Microcomputer with interrupt packets

A GENERAL EXPENDITURE FOR INPUT AND EQUIVALENT PROCEDURE FOR THE SUPPORT OF EXISTING INTERRUPTIONS

ETHERNET ADDRESSING OVER PHYSICAL POSITION FOR MASSIF PARALLEL OF SYSTEMS

EXPENDITURE FOR EVENT FOR PROCESSORS

PROCEDURE AND DEVICE FOR THE INTERRUPT DISTRIBUTION IN A MULTIPROCESSOR SYSTEM

Verfahren zum Schutz vor Unterbrechung einer festgelegten Befehlssequenz eines Prozesses durch einen anderen Prozess in einer Datenverarbeitungsanlage

Die Erfindung betrifft ein Verfahren zum Schutz vor Unterbrechung einer festgelegten Befehlssequenz eines Prozesses durch einen anderen Prozess in einer Datenverarbeitungsanlage, wobei die Prozesse auf mindestens einem Prozessor ablaufen. Um eine atomare Abarbeitung von Prozessen unter Verhinderung einer Prioritätsumkehr zu ermöglichen, ist vorgesehen,-dass ein erster Prozess (EOS-Task1) am Beginn seiner Ausführung der festgelegten Befehlssequenz beim Betriebssystemkern (EOS-Kernel) wegen einer Sperre (EOS-Lock) des Prozessors für andere Prozesse anfragt, diese Sperre vom Betriebssystemkern gewährt wird, sofern kein anderer Prozess diese Sperre bereits eingeschaltet hat, und die Sperre zugunsten des ersten Prozesses (EOS-Task1) vom Betriebssystem so lange aufrecht erhalten wird, bis der erste Prozess am Ende seiner Ausführung der festgelegten Befehlssequenz die Sperre wieder aufhebt, und-dass ein zweiter Prozess (E0S-Task2), der während einer Sperre des Prozessors zugunsten eines ersten ...

MICROPROCESSOR INTERRUPTION SYSTEM.

COMPUTER SYSTEM WITH CONVERSION OF MODE OF PROCESSOR INSTRUCTIONS.

DATA PROCESSING SYSTEM WITH ANORDUNG FOR THE IDENTIFICATION OF EXTERNAL INTERRUPTS DELIVERING UNITS.

ARRANGEMENT WITH FUNCTIONAL UNITS PLUG-IN

SOFTWARE-CONFIGURABLE TECHNOLOGY FOR THE PRIORISIEREN OF INTERRUPTIONS IN A ON A MICROPROCESSOR WERE BASED SYSTEM

A GENERAL EXPENDITURE FOR INPUT, MINUTES AND AN EQUIVALENT PROCEDURE FOR THE CONVERSION OF THE FLOW CONTROL

INTERRUPTION OPERATION IN A DATA PROCESSING SYSTEM

DEVICE AND PROCEDURE FOR THE INTERRUPTION PROCESSING OF PERIPHERAL DEVICES

CIRCUIT FOR SELECTING INTERRUPT REQUESTS IN RISC MICROPROCESSORS

VECTORED INTERRUPTS IN C.R.T. DISPLAY

Interruption circuit operable at a high speed

Adapter unit having a handle grip for a personal digital assistant

NODE FOR SERVICING INTERRUPT REQUEST MESSAGES ON A PENDED BUS

A device with host indication combination

SYSTEM AND METHOD FOR PROVIDING A REAL-TIME PROGRAMMABLE INTERFACE TO A GENERAL-PURPOSE NON-REAL-TIME COMPUTING SYSTEM

A system and method providing read-time external signals to and from a gaming application executing within a platform independent programming environment on a computing system. The system comprises an input packet queue located within a block of system RAM coupled to a main system bus, a main processing module coupled to the main system bus, and an intelligent I/O interface module coupled to the main system bus for generating an input signal data packet in response to a change in state of one or more external signals. The intelligent I/O interface module comprises a control processor, an plurality of external signal interfaces, and a dual-port RAM. The control processor generates and stores the input signal data packet within the dual-port RAM before asserting an interrupt signal to the main processing module. Finally, the interrupt signal causes the main processing module to transfer the input signal data packet from the dual-port RAM to the input packet queue. The main procesing system ...

I/O PRIORITY RESOLVER

VECTORED INTERRUPTS IN A CATHODE RAY TUBE DISPLAY

DISCRETE CONTROLLER

HIGH SPEED DATA TRANSFER FOR A PERIPHERAL CONTROLLER

COMMUNICATION MULTIPLEXER HAVING DUAL MICROPROCESSORS

METHOD AND APPARATUS FOR TRANSFERRING INTERRUPTS FROM A PERIPHERAL DEVICE TO A HOST COMPUTER SYSTEM

Apparatus for transferring interrupts form a peripheral device to a host computer system is described. The apparatus comprises a buffer for storing indications of interrupts generated by the peripheral device. In response to a preset condition being met, a controller generates a control data block having a payload portion, moves the contents of the buffer to the payload poriton of the control data block, and sends the control data block to the host computer system.

CONVERTING A MESSAGE SIGNALED INTERRUPTION INTO AN I/O ADAPTER EVENT NOTIFICATION

One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications. Each I/O adapter event notification includes the setting of one or more specific indicators in system memory and an interruption request, the first of which results in a pending I/O adapter interruption request. While a request for an I/O adapter interruption is pending, subsequent message signaled interruption requests are converted to I/O adapter event notifications, but do not result in additional requests for I/O adapter interruptions.

VIRTUAL COMPUTER SYSTEM HAVING IMPROVED INPUT/OUTPUT INTERRUPT CONTROL

A virtual computer system includes a plurality of virtual machines running in a central processing unit with time shared, an input/output unit generating an input/output interrupt request, and a specific instruction generating part for generating a specific instruction indicating a priority to one of the virtual machines which is running. The system further includes a decision part for determining whether the input/output interrupt request addressed to one of the virtual machines has a priority equal to that indicated by the specific instruction and for generating an interrupt accepting signal when the decision result is affirmative. Moreover, the system includes a monitor part for transferring a right to use the central processing unit from the one of the virtual machines which is running to the one of the virtual machines which is addressed by the input/output interrupt request when the interrupt accepting signal from the decision part is supplied to the monitor part.

APPARATUS AND METHOD FOR IMPROVING THE COMMUNICATION EFFICIENCY BETWEEN A HOST PROCESSOR AND PERIPHERAL DEVICES CONNECTED BY AN SCSI BUS

Apparatus and method for increasing efficiency of command execution from a host processor over an SCSI bus. Arbitration, selection and message out functions of SCSI protocol are implemented using a background arbitration state machine. Additional protocol functions are implemented in a foreground state machine. When the host processor issues a command for access to the SCSI bus, the background state machine can be programmed before the foreground machine completes the protocol function for a previous command. Thus, the background state machine is ready to arbitrate for access to the bus at the very next bus free condition.

MULTIPLE INTERRUPT HANDLING METHOD AND APPARATUS

A method and an apparatus for handling interrupt requests generated by a plurality of interrupt sources (2A, 2N) for a processor. The method includes ste ps of scanning interrupt registering means (8) for determining a current interrupt request to be sent to the processor among interrupt requests having respective interrupt flags inputted in said interrupt registering means, and steps involvin g the processor for execution of an interrupt processing program according to the result of a comparison of a scanned interrupt flag with a predetermined flag val ue, characterised in that it includes a step of latching a flag corresponding to a f irst occurring interrupt request from a source in a group of sources into interrupt latch registering means (7) for further processing and for blocking further interrupt requests from at least the same source in the same group from having a flag latched before processor controlled resetting.

Verfahren und Anordnung zur Fehlererkennung und Fehlerkorrektur für Datenblocks aus binär verschlüsselten Zeichen

Verfahren zum Empfangen und Senden von in Form von Polaritätswechseln auftretenden Informationen

CONTROL EQUIPMENT WITH A MICROPROCESSOR.

SWITCHING CONFIGURATION TO THE INPUT OF CONTROL INSTRUCTIONS INTO A MICROCOMPUTER SYSTEM.

MULTIPROCESSOR PLANT.

PROCEDURE FOR THE TASK CHANGE-OVER AFTER AN INTERRUPT REQUEST IN A PROCESSOR SYSTEM.

Scalable system interrupt structure for a multiprocessing system

Virtual-interrupt-mode interface and method for virtualizing an interrupt mode

Embodiments of the present invention are directed to methods for virtualizing interrupt modes on behalf of interrupt-generating devices, including I/O-device controllers, so that newer interrupt-generating devices that lack older interrupt modes can be used in systems that continue to rely on older interrupt modes. In one embodiment of the present invention, a PCIe switch or PCIe-based host bridge is modified, or a new component introduced, to provide an interrupt-mode virtualizing function, or virtual interrupt-mode interface, that provides a virtual interrupt mode on behalf of interrupt-generating devices, such as I/O-device controllers, to operating systems, BIOS layers, and other components that communicate with the I/O-device controllers.

优化的可扩展网络交换机

... 在一种包括按照m多维配置的多个节点的大规模并行计算系统中，每个节点包括计算设备，一种用于将分组路由到它们的目的节点的方法被提供，该方法包括生成包含从下行流节点导出的信息的2m个压缩位向量(115、154)中的至少之一。一种多级仲裁过程(116、155)，其中在该压缩向量中所存储的下行流信息，诸如链路状态信息和下行流缓冲器(130、140)的充满度，被用于确定用于传送分组的优选方向和虚拟信道。优选方向范围被编码并且虚拟信道通过检查该多个压缩位向量(115、154)来加以选择。这一动态路由方法消除了路由表的必要性，因此就增强了交换机的可扩展性。 ...

System and method for transmitting interrupt messages through a parallel communication bus

Package

FPGA-based (Field Programmable Gate Array) extended multi-serial port device and data receiving-transmitting method thereof

Interrupt controller using small handware to flexibly dual with multiple interrupt treatment

COMMUNICATION INTERFACE STIRRUP

DEVICE AND METHOD FOR PROCESSING AN INTERRUPT REQUEST IN A DATA PROCESSING SYSTEM OPERATING IN VIRTUAL MACHINE.

PROCEDE ET MONTAGE DE CIRCUIT POUR FOURNIR DES SIGNAUX DE DEMANDE D'INTERRUPTION

DANS UN PROCEDE DESTINE A DES UNITES EXTERNES D'UN CALCULATEUR POUR LA FOURNITURE DE SIGNAUX DE DEMANDE D'INTERRUPTION SANS PRIORITES PAR L'INTERMEDIAIRE D'UNE LIGNE DE COMMANDE COMMUNE A L'UNITE CENTRALE DU CALCULATEUR, LE SIGNAL DE DEMANDE D'INTERRUPTION D'UNE UNITE EXTERNE EMPECHE LA FOURNITURE D'UN SIGNAL DE DEMANDE D'INTERRUPTION PAR LES AUTRES UNITES EXTERNES.

SYSTEM OF DATA PROCESSING HAS DEVICE Of INTERCONNECTION OF MULTIPLE PROCESSORS

PROCESS Of OPTIMIZATION Of ACCESS REPORT, DURING the RESUMPTION Of EXECUTION Of an APPLICATION, IN a MICROPROCESSOR INCLUDING/UNDERSTANDING SEVERAL LOGICAL HEARTS AND COMPUTER PROGRAM IMPLEMENTING SUCH a PROCESS

APPARATUS Of ARBITRATION FOR TREATMENT Of ASYNCHRONOUS INTERRUPTIONS

I/O DEVICE ATTACHMENT FOR A COMPUTER

PROGRAMME-CONTROLLED DATA PROCESSING SYSTEMS

Async. signal transmission system for data processor - provides bidirectional dialogue by amplitude variation of single signal from each peripheral

Exit and input circuit for calculator

COMPUTER FOR PREFERABLY PROCESSING AN INTERRUPT OF A DEVICE CONNECTED TO A PCI BUS, CONCERNED WITH INCREASING THE PROCESSING SPEED OF THE ENTIRE SYSTEM BY PREFERABLY HANDLING INTERRUPT REQUEST SIGNALS OF DEVICES LOCATED ON THE PCI BUS

PURPOSE: A computer for preferably processing an interrupt of a device connected to a PCI bus is provided to give a priority to an interrupt of a device connected to a PCI bus, rather than an interrupt of a device connected to an ISA(Industry Standard Architecture) bus, thereby increasing a data processing speed of a computer system. CONSTITUTION: An ISA device(13) includes input/output devices(9,10) and ISA slots(11). An ISA bridge controller(7) includes the first programmable interrupt controller(8) for receiving interrupt request signals(IRQ1,IRQ(3:15)) outputted from the ISA device(13) and outputting the first interrupt signal(INTR1) according to priorities of each ISA device(13). A PCI device(14) includes input/output devices(4,5) and PCI slots(6). A PCI bridge controller(2) is embedded with the second programmable interrupt controller(3) for receiving the first interrupt signal(INTR1) and interrupt request signals(INTA#,B#,C#,D#), giving a priority to an interrupt of the device(14 ...

FAULT ISOLATION THROUGH NO-OVERHEAD LINK LEVEL CRC

A NOVEL MASSIVELY PARALLEL SUPERCOMPUTER

GLOBAL INTERRUPT AND BARRIER NETWORKS

APPARATUS AND METHOD FOR SUPPORTING CREATION OF IMAGE FOR PORTABLE TERMINAL

컴퓨터 시스템 인터럽트 핸들링

... 본 발명은 상기 가속 처리 디바이스(APD)를 사용하여 큐에서 복수의 작업을 인큐잉하는 단계, 유저 레벨 인터럽트를 생성하는 단계, 및 중앙 처리 유닛(CPU) 쓰레드와 연관된 인터럽트 핸들러를 사용하여 상기 큐에 있는 복수의 작업을 상기 CPU에 전송하는 단계를 포함하는, 작업을 처리할 것을 CPU에 요청하는 APD를 위한 시스템, 방법, 및 제조 물품에 관한 것이다.

DMA controller with interrupt control processor

METHOD AND APPARATUS FOR AVOIDING RACE CONDITION WITH EDGE-TRIGGERED INTERRUPTS

Flexible interrupt controller that includes an interrupt force register

TESTER AND INFORMATION PROCESSING SYSTEM

APPARATUS AND A METHOD FOR REPLYING TO AN EXTERNAL INTERFACE HOST TO CONTROL THE INTERFACE POWER IN A SYSTEM ON A CHIP, PARTICULARLY FOR CONTROLLING THE ELECTRIC POWER OF AN INTERFACE POWER AREA

PURPOSE: An apparatus and a method for replying to an external interface host to control the interface power in a system on a chip are provided to reduce the leakage current and power consumption for an interface power area. CONSTITUTION: An interface power area in a chip is connected to an external interface host(210) and performs communication to enable an interface operation. When the communication with the external interface host is not performed, a power controller(201) cuts down the electric power of the interface power region. If the external interface host requests the connection In a state that the electric power of the interface power area is blocked, an interface control unit(203) transmits the response signal to the connection request of the external interface host until the interface power region is activated. COPYRIGHT KIPO 2010 ...

Query sampling information instruction

A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss.

Technique for communicating interrupts in a computer system

A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APlC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).

Computing device and serial communication method of the computing device

A serial communication method is applied in a computing device to communicate serially with any external serial device. The computing device includes a baseboard management controller (BMC) and an operating system (OS). The BMC includes at least one physical serial port. The method generates a virtual serial port for the OS by emulating serial port functionality of the physical serial port. When the BMC is initializing the physical serial port and a serial device is connected to the physical serial port, an interrupt handler is activated to handle an interrupt triggered to the BMC by the serial device. The interrupt handler is deactivated when the physical serial port has been initialized by the BMC.

Method, apparatus or software for processing exceptions produced by an application program

A method, apparatus and software is disclosed in which original exceptions issued by an application program are encoded as substitute exceptions with associated metadata identifying the original exception so as to enable to enable a first application program receiving the exception but not arranged to process the original exception to process the substitute exception and to enable a second application program receiving the exception and arranged to process the original exception to extract and process that original exception.

Selectively enabling a host transfer interrupt

Embodiments of the invention are directed to systems and methods for reducing the number of interrupts on a controller for a non-volatile storage device to improve data transfer performance of the storage system. The embodiments described herein selectively enable an interrupt generated by host transfer hardware for a host command. The interrupt can be enabled or disabled by considering the command type, availability of interface resources to accept additional host transfers, and the command size. Embodiments described herein are useful for host interfaces implementing a tagging scheme for host transfers with a limited range of identification tags.

System and methods for protecting users from malicious content

A method, system and device for allowing the secure collection of sensitive information is provided. The device includes a display, and a user interface capable of receiving at least one user-generated interrupt in response to a stimulus generated in response to content received by the device, wherein the action taken upon receiving the user-generated interrupt depends on a classification of the content, the classification identifying the content as trusted or not trusted. The method includes detecting a request for sensitive information in content, determining if an interrupt is generated, determining if the content is trusted, allowing the collection of the sensitive information if the interrupt is generated and the content is trusted, and performing an alternative action if the interrupt is generated and the content is not trusted. The method may include instructions stored on a computer readable medium.

Host device suspending communication link to client device based on client device notification

A communication link between a host device and a client device can be suspended based on a suspend request or notification provided by the client device. The suspend request can be transmitted by a client device to a host device if the client device determines that suspension is appropriate, and can be sent in response to receiving a polling request from the host device. After receiving a suspend request, the host device can initiate an operation to suspend the communication link between the devices.

Method and apparatus for managing operating systems in embedded system

A method for managing operating systems in an embedded system to solve the problem of performance loss and high product complexity caused by the running of multiple operating systems on a single CPU is provided. The embedded system includes at least two operating systems. The method includes: receiving an interrupt instruction; saving a state of a currently running operating system; and switching the currently running operating system to a target operating system corresponding to the interrupt instruction.

Delivering Interrupts Directly To A Virtual Processor

Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.

System and method for high-performance, low-power data center interconnect fabric with broadcast or multicast addressing

A system and method are provided that support a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology. The system may use a segmented MAC architecture which may have a method of re-purposing MAC IP addresses for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch.

Source Core Interrupt Steering

An embodiment of the invention includes (i) receiving a core identifier that corresponds with a processor source core; (ii) receiving an input/output request, produced from the source core, that is associated with the core identifier; (iii) and directing an interrupt, which corresponds to the request, to the source core based on the core identifier. Other embodiments are described herein. 1. At least one machine readable medium comprising instructions that when executed on a computing device cause the computing device to perform a method comprising:receiving a core identifier that corresponds with a source core that is included in a processor;receiving an input/output request, produced and originating from the source core, that is associated with the core identifier;storing the core identifier in a memory coupled to the processor;directing an interrupt, which corresponds to the request, to the source core based on the core identifier;wherein the processor is coupled to an additional core and the request includes the core identifier.2. The at least one medium of claim 1 , the method comprising directing the interrupt to the source core claim 1 , but not the additional core claim 1 , based on the core identifier.3. The at least one medium of claim 2 , the method comprising directing a message-signaled interrupt message to the source core based on the core identifier.4. The at least one medium of claim 1 , the method comprising determining a message-signaled interrupt address based on the core identifier.5. The at least one medium of claim 1 , the method comprising storing the core identifier in the memory before directing the interrupt to the source core.6. At least one machine readable medium comprising instructions that when executed on a computing device cause the computing device to perform a method comprising:receiving an input/output request, produced and originating from a source core, which includes a message-signaled interrupt (MSI) message that corresponds ...

Method for Enabling Sequential, Non-Blocking Processing of Statements in Concurrent Tasks in a Control Device

A method for enabling sequential, non-blocking processing of statements in concurrent tasks in a control device having an operating system capable of multi-tasking, in particular a programmable logic controller, is disclosed. At least one operating system call, which causes the operating system to interrupt the particular task according to an instruction output by the statement in favor of another task, is associated with at least one statement. 1. A method for enabling sequential , non-blocking processing of statements in concurrent tasks in a control device having an operating system capable of multitasking , comprising:associating at least one statement with at least one operating system call, andcausing the operating system to interrupt the respective task according to an instruction output by the at least one statement in favor of another task.2. The method as claimed in claim 1 , further comprising using the method in a programmable logic controller or a motion controller.3. The method as claimed in claim 1 , further comprising:suspending the interrupted task during a processing time of the instruction, andreactivating the interrupted task after the end of the processing time.4. The method as claimed in claim 3 , wherein the suspending step and/or the reactivating step is effected using a semaphore and/or a test function.5. The method as claimed in claim 1 , wherein the method is implemented for a programming language according to IEC/EN 61131-3.6. The method as claimed in claim 1 , in which the at least one statement is associated with further operating system calls which cause the operating system to write an output image and/or to read an input image.7. The method as claimed in claim 1 , wherein operating system calls are associated with the at least one statement in the form of a structure encapsulating statements and operating system calls.8. The method as claimed in claim 7 , in which the encapsulating structure also comprises a test function and/or a ...

INTERRUPTION FACILITY FOR ADJUNCT PROCESSOR QUEUES

Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queue. In order for the queue to take advantage of the interruption capability, it is enabled for interruptions. 1. A method for making a computer program product for facilitating processing of queues of a processing environment , the method comprising:first assembling instructions for causing a computer to determine that a queue of the processing environment has transitioned from a no replies pending state to a reply pending state, wherein the queue is indirectly accessible to user programs, and wherein the no replies pending state is a state in which the queue is empty, and the reply pending state is a state in which the queue is not empty, and storing the first assembling instructions on a tangible computer storage medium;second assembling instructions for causing a computer to enable the queue for interruption, the enabling comprising employing a process adjunct processor queue (PQAP) instruction to enable the queue for interruption, wherein the PQAP instruction employs general registers 0, 1 and 2 for input, and general register 1 for output, and storing the second assembling instructions on a tangible computer storage medium; andthird assembling instructions for causing a computer to initiate, by a processor, an interrupt for the queue, wherein the initiating is based on enabling the queue and determining that the queue has transitioned from the no replies pending state to the reply pending state, wherein the interrupt is initiated based on the queue transitioning from an empty state to a non-empty state, and the interrupt is not initiated based on the queue not transitioning from the empty state to the non-empty state, and storing the third assembling instructions on a tangible computer storage medium. ...

System and Method for High-Performance, Low-Power Data Center Interconnect Fabric

A system and method are provided that support a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology. The system may use a segmented MAC architecture which may have a method of re-purposing MAC IP addresses for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch.

Host-Based Messaging Framework for PCIE Device Management

A method of routing data in an information handling system can include receiving a notification from a management controller at a basic input/output system (BIOS) that includes a system management interrupt (SMI) handler. The a notification can indicate that the management controller has a data packet bound for a peripheral component interconnect express input/output (PCIe I/O) device coupled to a secondary processor. The method can include generating a system management interrupt at the information handling system via the BIOS SMI handler in response to the notification. The method can also include retrieving the data packet from the management controller via the BIOS SMI handler and sending a payload associated with the data packet from the BIOS SMI handler to the PCIe I/O device.

EMULATION OF AN INPUT/OUTPUT ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER

Embodiments of systems, apparatuses, and methods for emulating an input/output Advanced Programmable Interrupt Controller are disclosed. In one embodiment, an apparatus includes a first interrupt controller having a first programming model, and emulation logic to emulate a second interrupt controller having a second programming model that is different from the first programming model, The emulation logic is also to mask one of a plurality of interrupt requests to the first interrupt controller for each of the plurality of interrupt requests handled by the emulation logic. 1. An apparatus co p sing:a first intern controller having a first programming model; andemulation logic to emulate a second interrupt controller having a second programming model different from the first programming model, and to mask one of a plurality of interrupt requests to the first interrupt controller for each of the plurality of interrupt requests handled by the emulation logic.2. The apparatus of claim 1 , wherein the second interrupt controller is an input/output Advanced Programmable Interrupt Controller.3. The apparatus of claim 1 , wherein he first interrupt controller includes a plurality of mask indicators claim 1 , and the emulation logic is to mask one of the plurality of interrupt requests to the first interrupt controller using one of the plurality of mask indicators.4. The apparatus of claim 1 , further comprising a random access memory to store information corresponding to contents of the register set of the second interrupt controller.5. The apparatus of claim 4 , further comprising a decoder to decode transactions intended for the second interrupt controller.6. The apparatus of claim 5 , further comprising redirection logic to redirect transactions intended for the second interrupt controller to the random access memory.7. The apparatus of claim 1 , further comprising messaging logic to construct an interrupt message for each of the plurality of interrupts handled by the ...

DELEGATING A POLL OPERATION TO ANOTHER DEVICE

In one embodiment, the present invention includes a method for handling a registration message received from a host processor, where the registration message delegates a poll operation with respect to a device from the host processor to another component. Information from the message may be stored in a poll table, and the component may send a read request to poll the device and report a result of the poll to the host processor based on a state of the device. Other embodiments are described and claimed. 1. An apparatus comprising:a core to generate a registration message to delegate a poll operation to an input/output (IO) interconnect;the IO interconnect coupled to the core, the IO interconnect to include a poll table having a plurality of entries each having a first address field to store a first address to be received in a registration message and a destination address field to store a destination address in a system memory to be received in the registration message; andat least one device coupled to the IO interconnect to perform an operation for an application to be executed on the core and to include at least one status register, the IO interconnect including a poll delegation logic to poll the at least one status register responsive to information in a poll table entry, and to issue a write transaction to the destination address if a polled value of the at least one status register differs from an initial value of the at least one status register.2. The apparatus of claim 1 , wherein each of the plurality of entries includes an initial value field to store an initial value associated with the first address received in the registration message.3. The apparatus of claim 1 , wherein the poll delegation logic is to issue a read request to the at least one device at a predetermined interval to perform the poll.4. The apparatus of claim 3 , wherein the poll delegation logic is to perform a comparison between data received from the at least one device responsive to ...

MULTICORE PROCESSOR SYSTEM, COMPUTER PRODUCT, ASSIGNING METHOD, AND CONTROL METHOD

A multicore processor system includes core configured to detect a process assignment instruction; acquire a remaining time obtained by subtracting a processing time of interrupt processing assigned to an arbitrary core of a multicore processor from a period that is from a calling time of the interrupt processing to an execution time limit of the interrupt processing, upon detecting the process assignment instruction; judge if the remaining time acquired at the acquiring is greater than or equal to a processing time of processing defined to limit an interrupt in the process; and assign the process to the arbitrary core, upon judging that the remaining time is greater than or equal to the processing time of the processing defined to limit an interrupt in the process. 1. A multicore processor system comprising core configured to:detect a process assignment instruction;acquire a remaining time obtained by subtracting a processing time of interrupt processing assigned to an arbitrary core of a multicore processor from a period that is from a calling time of the interrupt processing to an execution time limit of the interrupt processing, upon detecting the process assignment instruction;judge if the remaining time acquired at the acquiring is greater than or equal to a processing time of processing defined to limit an interrupt in the process; andassign the process to the arbitrary core, upon judging that the remaining time is greater than or equal to the processing time of the processing defined to limit an interrupt in the process.2. A multicore processor system comprising a core configured to:add an execution time of given interrupt processing and an execution time of interrupt processing assigned to an arbitrary core of a multicore processor;judge whether the arbitrary core can meet an execution time limit from a time of calling of the given interrupt processing and an execution time limit from a time of calling of the assigned interrupt processing, based on a sum ...

INTERRUPT CONTROL METHOD AND MULTICORE PROCESSOR SYSTEM

In an interrupt control method of a multicore processor system including cores, a cache coherency mechanism, and a device, a first core detecting an interrupt signal from the device writes into an area prescribing an interrupt flag in the cache memory of the first core, first data indicating detection of the interrupt signal, and notifies the other cores of an execution request for interrupt processing corresponding to the interrupt signal, consequent to the cache coherency mechanism establishing coherency among at least cache memories of the other cores when the first data is written; and a second core different from the first core, maintaining the first data written as the interrupt flag, and notified of the execution request executes the interrupt processing, and writes over the area prescribing the interrupt flag written in the cache memory of the second core, with second data indicating no-detection of the interrupt signal. 1. An interrupt control method of a multicore processor system comprising a plurality of cores , a cache coherency mechanism establishing coherency among cache memories of the cores other than an arbitrary core when data is written into a cache memory of the arbitrary core , and a device , wherein first-writing into an area prescribing an interrupt flag in the cache memory of the first core, first data indicating detection of the interrupt signal, and', 'notifying the cores, other than the first core, of an execution request for interrupt processing corresponding to the interrupt signal, consequent to the cache coherency mechanism establishing coherency among at least the cache memories of the cores other than the first core when the first data is written at the first-writing; and, 'a first core that is among the cores and detects an interrupt signal from the device executes'} the interrupt processing, and', 'second-writing over the area prescribing the interrupt flag written in the cache memory of the second core, with second data ...

NETWORK ADAPTOR OPTIMIZATION AND INTERRUPT REDUCTION

A method and system are disclosed for network adaptor optimization and interrupt reduction. The method may also build an outbound buffer list based on outgoing data and add the outgoing data to an outbound buffer queue. Furthermore, the method may set a buffer state from an empty state to a primed state to indicate that the outgoing data is prepared for transmitting and signal a network adaptor with a notification signal. 1. A method for network adaptor optimization and interrupt reduction , the method comprising:building an outbound buffer list based on outgoing data, the outgoing data comprising data to be transmitted to a network;adding the outgoing data to an outbound buffer queue;setting a buffer state from an empty state to a primed state to indicate that the outgoing data is prepared for transmitting; andsignaling a network adaptor with a notification signal, the network adaptor configured to process the outbound buffer queue and transmit the outgoing data to the network in response to the notification signal, the network adaptor configured to set the buffer state to a polling state indicating that the network adaptor is polling for additional outgoing data, the network adaptor configured to poll for additional outgoing data for a predetermined time interval.2. The method of claim 1 , further comprising releasing the outgoing data in the outbound buffer queue such that the outbound buffer queue may accept additional outgoing data.3. The method of claim 1 , further comprising detecting that the network adaptor is polling based on the polling state and refraining from signaling the network adaptor with an additional notification signal claim 1 , the network adaptor configured to directly process the outbound buffer queue and directly transmit the additional outgoing data to the network.4. The method of claim 1 , wherein the buffer state comprises a Queued Direct I/O (QDIO) Storage-List-State Block (SLSB).5. The method of claim 1 , wherein the outbound buffer ...

Interrupt Moderation

A technique for interrupt moderation allows coalescing interrupts from a device into groups to be processed as a batch by a host processor. Receive and send completions may be processed differently. When the host is interrupted for receive completions, it may check for send completions, reducing the need for interrupts related to send completions. Timers and a counter allow coalescing interrupts into a single interrupt that can be used to signal the host to process multiple completions. The technique is suitable for both dedicated interrupt line and message-signaled interrupts.

Semiconductor data processing device, time-triggered communication system, and communication system

The variation of the timing of starting interrupt processing in response to a timer interrupt request is reduced regardless of the condition of processing of other interrupts. A semiconductor data processing device incorporated in each of plural electronic control devices coupled to a network for time-triggered communication system is provided with a central processing unit, a communication control circuit and an interrupt control circuit. The communication control circuit has a local time timer for use in time-triggered communication and issues, based on time counting by the local time timer, a timer interrupt request for time-triggered communication. When a timer interrupt request for time-triggered communication is received, the interrupt control circuit performs control to cause the central processing unit to delay, by a predetermined reservation time, starting the interrupt processing to be performed in response to the timer interrupt request.

System and method for Automatic Hardware Interrupt Handling

A processing system is provided consisting of an interrupt pin, multiple registers, a stack pointer, and an automatic interrupt system. The multiple registers store a number of processor states values. When the system detects an interrupt on the interrupt pin the system prepares to enter an exception mode where the automatic interrupt system causes an interrupt vector to be fetched, the stack pointer to be updated, and the processor state values to be read in parallel from the registers and stored in memory locations based on the updated stack pointer, prior to the execution of an interrupt service routine. A method for automatic hardware interrupt handling is also presented. 1. A method of interrupt handling , comprising:determining a privilege level associated with a first interrupt;updating a first stack pointer register with a value copied from a first fixed register,storing a value associated with the first interrupt in a first memory address at a location identified by the first stack pointer register, anddisallowing access to the first fixed register from a process operating at a second privilege level, wherein the second privilege level is lower than the privilege level of the first interrupt.2. The method of claim 1 , further comprising:determining a privilege level of a second interrupt;updating a second stack pointer register with a value copied from a third stack pointer register associated with an interrupted process operating at a third privilege level, wherein the third privilege level is equal to the privilege level of the second interrupt;modifying the value in the second stack pointer register, andstoring a value associated with the second interrupt in a second memory address at a location identified by the second stack pointer register. This application is a divisional of U.S. application Ser. No. 12/847,772, filed Jul. 30, 2010, (now allowed), which is incorporated by reference herein in its entirety.1. Field of InventionEmbodiments of the ...

BUS CONTROL DEVICE AND BUS CONTROL METHOD

A bus control device includes a storing unit that stores therein a threshold related to bus width of a bus that is a transfer path for data, a comparing unit that compares, when the bus width is reduced, the reduced bus width with the threshold stored in the storing unit, and a selecting unit that selects, on the basis of the result of the comparison performed by the comparing unit, an interrupt operation performed on a processor that performs a process related to a reduction of the bus width. 1. A bus control device comprising:a storing unit that stores therein a threshold related to bus width of a bus that is a transfer path for data;a comparing unit that compares, when the bus width is reduced, the reduced bus width with the threshold stored in the storing unit; anda selecting unit that selects, on the basis of the result of the comparison performed by the comparing unit, an interrupt operation performed on a processor that performs a process related to a reduction of the bus width.2. The bus control device according to claim 1 , wherein the selecting unit selects claim 1 , on the basis of the result of the comparison performed by the comparing unit claim 1 , whether to generate an interrupt in the processor.3. The bus control device according to claim 1 , wherein the selecting unit selects claim 1 , on the basis of the result of the comparison performed by the comparing unit claim 1 , a priority of an interrupt performed on the processor.4. The bus control device according to claim 1 , whereinthe storing unit stores therein multiple thresholds,the comparing unit compares the reduced bus width with each of the multiple thresholds stored in the storing unit, andthe selecting unit selects, on the basis of the result of the comparison performed by the comparing unit, the presence or absence of an interrupt performed on the processor and a priority of an interrupt.5. The bus control device according to claim 1 , wherein the storing unit stores therein claim 1 , in ...

INFORMATION PROCESSING APPARATUS AND RECORDING APPARATUS USING THE SAME

A memory control unit is connected to a first bus and a second bus and that controls writing and reading of data to a memory; a control unit controls the information processing apparatus; a first circuit device is connected to the first bus and outputs a data write request to the memory control unit and a notification signal; a second circuit device is connected to the first bus and outputs a data read request to the memory control unit in accordance with the notification signal and an interrupt signal to the control unit in response to the data read request; and a third circuit device is connected to the second bus and outputs a data read request stored in the memory to the memory control unit in accordance with an instruction from the control unit which has received an interrupt signal. 1. An information processing apparatus including a memory control unit that is connected to a first bus and a second bus and that controls writing of data to a memory and reading of data from the memory , the information processing apparatus comprising:a control unit that controls the information processing apparatus;a first circuit device that is connected to the first bus and that outputs a data write request to the memory control unit and outputs a notification signal;a second circuit device that is connected to the first bus and that outputs a data read request to the memory control unit in accordance with the notification signal and outputs an interrupt signal to the control unit in accordance with a response to the data read request; anda third circuit device that is connected to the second bus and that outputs a data read request stored in the memory to the memory control unit in accordance with an instruction from the control unit to which the interrupt signal has been input.2. The information processing apparatus according to claim 1 , further comprising a fourth circuit device that is connected to the first bus and that outputs a data write request to the memory control ...

INTERRUPT CAUSE MANAGEMENT DEVICE AND INTERRUPT PROCESSING SYSTEM

A peripheral device sends an interrupt generation notification to a bus bridge. The bus bridge receives the interrupt generation notification, transfers the received interrupt generation notification to a CPU, reads an interrupt cause from the peripheral device that has sent the interrupt generation notification, and writes to a memory the interrupt cause that has been read. Upon receiving the interrupt generation notification, the CPU reads the interrupt cause from the memory which allows fast access, and begins interrupt processing corresponding to the interrupt cause. Interrupt processing time up to commencement of the interrupt processing can be reduced. 14-. (canceled)5. An interrupt cause management device comprising:an interrupt generation notification receiving unit that receives an interrupt generation notification sent from a device;an interrupt cause reading unit that, when the interrupt generation notification is received by the interrupt generation notification receiving unit, reads an interrupt cause from the device that has sent the interrupt generation notification;an interrupt cause writing unit that writes the interrupt cause read by the interrupt cause reading unit to a memory device to be accessed by a processor device that processes the interrupt generation notification; andan interrupt generation notification sending unit that sends to the processor device the interrupt generation notification received by the interrupt generation notification receiving unit,wherein under a condition that an amount of read time required for the processor device to read the interrupt cause written in the memory device is shorter than an amount of time required for the processor device to read the interrupt cause from the device that has sent the interrupt generation notification,the interrupt cause writing unit writes to the memory device the interrupt cause read by the interrupt cause reading unit before a timing when the processor device, upon receiving the ...

Increasing Turbo Mode Residency Of A Processor

In one embodiment, the present invention includes a method for accessing a task stored in an entry of a task queue that identifies the task and a first core of a processor on which the task has been scheduled, reassigning the task to a coldest idle core of the processor, and sending the task to the coldest idle core and maintaining the processor in a turbo mode. Other embodiments are described and claimed. 1. A processor comprising:a plurality of cores each to execute instructions, each of the plurality of cores including at least one front end unit, at least one execution unit and at least one cache memory;a mapping table including a plurality of entries each to store a mapping of an advanced programmable interrupt controller (APIC) identifier (ID) to a core of the plurality of cores; anda power control unit (PCU) coupled to the plurality of cores and the mapping table and to access a task queue including a plurality of entries each to store a task identifier for a task and a corresponding identifier for a core on which the task is scheduled, wherein the PCU is to reassign a first task obtained from the task queue from a first core to a second core.2. The processor of claim 1 , wherein the PCU is to reassign the first task based at least in part on a temperature of the first and second cores.3. The processor of claim 2 , wherein the PCU is to reassign the first task when the second core is cooler than the first core.4. The processor of claim 1 , wherein the PCU is to reassign the first task in a manner that is not visible to an operating system.5. The processor of claim 1 , further comprising a plurality of thermal sensors each associated with one of the plurality of cores claim 1 , wherein each of the plurality of thermal sensors is to communicate temperature information to the PCU.6. The processor of claim 1 , wherein the second core includes an APIC register to store the APIC ID corresponding to the second core claim 1 , wherein the second core is to access the ...

INTERRUPT SIGNAL ACCEPTING APPARATUS AND COMPUTER APPARATUS

An interrupt signal accepting apparatus manages two OSs, relates devices sharing the same interrupt number respectively with an OS caused to perform an interrupt processing and an interrupt priority unique to a device, and manages an interrupt number priority conversion table showing the relation between the interrupt number and the interrupt priority. Each device continuously outputs an interrupt request having the same interrupt number until the interrupt processing is completed. An interrupt controller converts the interrupt number into the interrupt priority in accordance with the interrupt number priority conversion table when there is an interrupt signal from the devices. An interrupt signal control section causes a running OS to perform the interrupt processing to change the interrupt priority in the interrupt number priority conversion table when the converted interrupt priority matches an interrupt priority related to the running OS, and stops the running OS and starts the other OS when the interrupt priorities do not match. 1. An interrupt signal accepting apparatus , managing operations of at least two operating systems (OSs) and accepting interrupt signals from a plurality of devices , wherein an interrupt number notified by an interrupt signal and an OS caused to process the interrupt signal as a specified OS are specified to each of the plurality of devices , the interrupt signal accepting apparatus comprising:an OS unique value information storing section that stores OS unique value information to relate each of at least two number sharing devices which share the same interrupt number, to the specified OS of each number sharing device, a unique value which is unique to each number sharing device, and a shared interrupt number which is shared by the at least two number sharing devices;a conversion value information storing section that stores conversion value information to specify a unique value selected from among at least two unique values related ...

INTERRUPT HANDLING SYSTEMS AND METHODS FOR PCIE BRIDGES WITH MULTIPLE BUSES

A bridge includes buses, a memory, a component module, an interface and an interrupt module. The component module transfers data between a host control module and a network device via the memory and the buses. The interface is connected between the memory and the network device and transmits status information to the memory via one of the buses. The status information indicates completion of a last data transfer between the network device and the host control module. An interrupt module, subsequent to the status information being transmitted to the memory, detects a first interrupt generated by the network device, and transmits an interrupt message to the component module via the memory and the one of the buses. The component module then generates a second interrupt detectable by the host control module. The second interrupt indicates completion of data transfer between the network device and the host control module. 1. A bridge comprising:a plurality of buses;a memory;a component module configured to transfer data between a host control module and a network device via the memory and the plurality of buses;an interface connected between the memory and the network device and configured to transmit status information to the memory via one of the plurality of buses, wherein the status information indicates completion of a last data transfer between the network device and the host control module; andan interrupt module configured to, subsequent to the status information being transmitted to the memory, detect a first interrupt generated by the network device, and transmit an interrupt message to the component module via the memory and the one of the plurality of buses,wherein the component module is configured to, based on the interrupt message, generate a second interrupt detectable by the interrupt module, and wherein the second interrupt indicates completion of data transfer between the network device and the host control module.2. The bridge of claim 1 , wherein:the ...

MULTI-THREAD PROCESSOR AND ITS INTERRUPT PROCESSING METHOD

A multi-thread processor includes a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that manages in what order a plurality of hardware threads are processed with a pre-established schedule, and an interrupt controller that receives an input interrupt request signal and assigns the interrupt request to an associated hardware thread, wherein the interrupt controller comprises a register in which information is stored for each channel of an interrupt request signal, and the information includes information regarding to which one or more than one of the plurality of hardware threads the interrupt request signal is associated. 1. A multi-thread processor comprising:a plurality of hardware threads each of which generates an independent instruction flow;a thread scheduler that manages in what order the plurality of hardware threads are processed with a pre-established schedule; andan interrupt controller that receives an interrupt request and assigns the interrupt request to one certain hardware thread to be managed by the thread scheduler.2. The multi-thread processor according to claim 1 , wherein the interrupt controller comprises a register in which information of an interrupt request signal including the interrupt request is stored claim 1 , and the information of the interrupt request signal comprises information regarding to which one hardware thread the interrupt request is associated.3. The multi-thread processor according to claim 1 , wherein the interrupt controller comprises a register in which information is stored for each channel of an interrupt request signal including the interrupt request claim 1 , and the information comprises information regarding to which one or more of the plurality of hardware threads the interrupt request signal is associated claim 1 , andwherein in the register for each channel of an interrupt request signal, information about a relation between any one of the plurality of ...

PROGRAMMABLE EVENT DRIVEN YIELD MECHANISM WHICH MAY ACTIVATE OTHER THREADS

Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors. 1execution resources to execute a plurality of instructions;a monitor to detect a low progress indicating condition of said execution resources, said monitor to selectively disrupt processing of at least one program by transferring to a handler in response to detecting said low progress indicating condition.. An apparatus comprising: This application is a continuation of application Ser. No. 10/982,261, filed Nov. 5, 2004, which is a divisional of application Ser. No. 10/370,251, filed Feb. 19, 2003, which issued as U.S. Pat. No. 7,487,502 on Feb. 3, 2009, which are hereby incorporated by reference.1. FieldThe present disclosure pertains to the field of processing apparatuses and systems that process sequences of instructions or the like, as well as certain instruction sequences to program such apparatuses and/or systems. Some embodiments relate to monitoring and/or responding to conditions or events within execution resources of such processing apparatuses.2. Description of Related ArtVarious mechanism are presently used to change the flow of control (i.e., the processing path or instruction sequence being followed) in a processing system. For example, a jump instruction in a program sequence explicitly and precisely causes a jump to a new ...

POSTING INTERRUPTS TO VIRTUAL PROCESSORS

Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure. 1. An apparatus comprising: look-up logic to look up an entry associated with an interrupt request to a virtual processor in a first data structure; and posting logic to post the interrupt request in a second data structure specified by first information in the first data structure.2. The apparatus of claim 1 , wherein the first information includes the address of the second data structure.3. The apparatus of claim 1 , wherein the posting logic is also to generate a notify event to a physical processor claim 1 , the notify event to indicate that an interrupt request is posted for the virtual processor.4. The apparatus of claim 1 , wherein the second data structure is to include a plurality of posted-interrupt request indicators claim 1 , each of the plurality of posted-interrupt request indicators corresponding to one of a plurality of virtual interrupt vectors associated with the virtual processor.5. The apparatus of claim 3 , wherein the second data structure is to include an identifier of the physical processor.6. The apparatus of claim 3 , wherein the notify event is an interrupt request to the physical processor.7. The apparatus of claim 6 , wherein the second data structure is to include a physical interrupt vector to be included in an interrupt message to the physical processor.8. The apparatus of claim 3 , wherein the posting logic is to use second information from the second data structure to determine whether to generate the notify event.9. The apparatus of claim 8 , wherein the second information includes an indication of whether a ...

Input capture peripheral with gating logic

A microcontroller has an input capture peripheral, wherein the input capture peripheral is configured to store timer values of an associated timer in a memory and wherein the input capture peripheral has a gating input which controls whether an input capture function is activated.

Microcontroller with Context Switch

A microprocessor or microcontroller device may have a central processing unit (CPU), a data memory coupled with the CPU, wherein the data memory is divided into a plurality of memory banks, wherein a bank select register determines which memory bank is currently coupled with the CPU. Furthermore, a first and second set of special function registers are provided, wherein upon occurrence of a context switch either the first or the second set of special function register are selected as active context registers for the CPU and the respective other set of special function registers are selected as inactive context registers, wherein at least some of the registers of the active context registers are memory mapped to more than two memory banks of the data memory and wherein all registers of the inactive context registers are memory mapped to at least one memory location within the data memory. 1. A microprocessor or microcontroller device comprising:a central processing unit (CPU);a data memory coupled with the CPU, wherein the data memory is divided into a plurality of memory banks, wherein a bank select register determines which memory bank is currently coupled with the CPU; anda first set of special function registers and a second set of special function registers, wherein upon occurrence of a context switch either the first or the second set of special function register are selected as active context registers for the CPU and the respective other set of special function registers are selected as inactive context registers, wherein at least some of the registers of the active context registers are memory mapped to more than two memory banks of said data memory and wherein all registers of the inactive context registers are memory mapped to at least one memory location within the data memory.2. The device according to claim 1 , wherein all registers of the inactive context registers are memory mapped to only one memory bank of said plurality of memory banks.3. The ...

Interrupt Virtualization

In an embodiment, a device interrupt manager may be configured to receive an interrupt from a device that is assigned to a guest. The device interrupt manager may be configured to transmit an operation targeted to a memory location in a system memory to record the interrupt for a virtual processor within the guest, wherein the interrupt is to be delivered to the targeted virtual processor. In an embodiment, a virtual machine manager may be configured to detect that an interrupt has been recorded by the device interrupt manager for a virtual processor that is not currently executing. The virtual machine manager may be configured to schedule the virtual processor for execution on a hardware processor, or may prioritize the virtual processor for scheduling, in response to the interrupt. 1. A computer readable storage medium storing a plurality of instructions which , when executed on a computer:read a first memory location in a memory system, wherein the first memory location stores a log of events detected in the computer, wherein the log of events is updated by a hardware device interrupt manager in the computer responsive to the hardware device interrupt manager recording an interrupt in a second memory location in the memory system, wherein the second memory location is assigned to store interrupt data corresponding to a virtual processor in a virtual machine executing on the computer, wherein the hardware device interrupt manager is configured to receive the interrupt and to determine that the interrupt is targeted at the virtual processor, and wherein the interrupt is sourced by a device that is assigned to the virtual machine; andschedule the virtual processor for execution on a hardware processor in the computer responsive to detecting that the interrupt has been recorded for the virtual processor as indicated in the log of events, wherein the virtual processor is scheduled in order to service the interrupt.2. The computer readable storage medium as recited in ...

METHOD TO EMULATE MESSAGE SIGNALED INTERRUPTS WITH MULTIPLE INTERRUPT VECTORS

Methods to emulate a message signaled interrupt (MSI) with multiple interrupt vectors are described herein. An embodiment of the invention includes a memory decoder to monitor a predetermined memory location allocated to a device and to generate an emulated message signaled interrupt (MSI) signal in response to a posted write transaction to the predetermined memory location initiated from the device, and an interrupt controller, in response to the emulated MSI signal from the memory decoder, to invoke processing of a plurality of interrupts based on a plurality of interrupt vectors retrieved from the predetermined memory location, without receiving an actual MSI interrupt request from the device. 1. A processor , comprising:a memory decoder to monitor a predetermined memory location allocated to a device and to generate an emulated message signaled interrupt (MSI) signal in response to a posted write transaction to the predetermined memory location initiated from the device; andan interrupt controller, in response to the emulated MSI signal from the memory decoder, to invoke processing of a plurality of interrupts based on a plurality of interrupt vectors retrieved from the predetermined memory location, without receiving an actual MSI interrupt request from the device.2. The processor of claim 1 , further comprising one or more execution units to execute one or more interrupt service routines (ISRs) associated with the device to service the MSI interrupts using interrupt data retrieved from the predetermined memory location claim 1 , without having to access the device via an input output (IO) transaction.3. The processor of claim 1 , wherein the emulated MSI signal is generated based on the posted write transaction from the predetermined memory location other than a system defined address for the MSI.4. The processor of claim 1 , wherein the memory location is allocated from one of a cache memory associated with the execution unit and a system memory during ...

ACCESS DEVICE, COMMUNICATION DEVICE, COMMUNICATION SYSTEM, AND DATA ACCESS METHOD

The access device comprises a memory and a device controller configured to send and receive a data control right between the data recording device and a central controller provided in a host device. When having received a request to interrupt transfer of data from the central controller while data is being transferred from the data recording device, the device controller releases the data control right from the data recording device, and has the data recording device determine whether or not mismatching has occurred in file system management information for data stored in the memory. The device controller then returns the data control right to the data recoding device when it is determined that mismatching has occurred in the file system management information. The data recording device releases the data control right after eliminating the mismatching in the file system management information according to the returned data control right. 1. An access device provided in a host device and configured to control reading or writing of data from or to a memory , in a communication system including a data recording device and the host device that are wirelessly connected to each other , the access device comprising:the memory configured to store data; anda device controller configured to send and receive a data control right between the data recording device and a central controller provided in the host device, the data control right being an exclusive right to execute the reading or the writing of data that is managed by a file system provided in the memory;wherein the device controller is configured to:when having received a request to interrupt transfer of data from the central controller provided in the host device while data is being transferred from the data recording device after the data control right has been granted to the data recording device, release the data control right from the data recording device, and have the data recording device determine whether or ...

MICROCOMPUTER

A rewriting area of a flash ROM stores a main program, which includes a user vector with respect to each of interrupt factors that are different from each other in respect of types. The user vector with respect to a subject interrupt factor indicates an address, which stores an interrupt processing program that is executed when the subject interrupt factor arises. This user vector is stored in a predetermined address dedicated for the subject interrupt factor. The predetermined address of the user vector is enabled to be specified by an interrupt vector or interrupt changeover program, both of which are stored in a non-rewriting area of the flash ROM. Even when an address of the interrupt processing program is changed, the changed address is enabled to be indicated by using the user vector. 1. A microcomputer comprising:a CPU that executes selectively (i) a main program and (ii) an onboard rewriting program that executes an onboard rewriting of the main program; anda nonvolatile memory that includes (i) a rewriting permitted area where data are enabled to be rewritten and (ii) a rewriting forbidden area where data are forbidden from being rewritten,the rewriting permitted area storing the main program,the rewriting forbidden area storing the onboard rewriting program,the rewriting forbidden area further storing an interrupt vector with respect to each of a plurality of interrupt factors, the interrupt factors being different from each other,the interrupt vector indicating an address of a branch destination when each of the plurality of interrupt factors arises,the microcomputer further comprising:a change section that uses the address indicated by the interrupt vector and changes a CPU-accessed address, which is an address accessed by the CPU, into either an address within the main program or an address within the onboard rewriting program according to the main program or the onboard rewriting program, whichever is executed,wherein:the main program includes a user ...

Interrupt coalescing for outstanding input/output completions

In a computer system, a method of controls interrupts which correspond to input/output (I/O) processing. For each delivery of an I/O completion interrupt, the method provides a recordation of a delivery time; identifies I/O completions for which deliveries of corresponding I/O completion interrupts involve deliveries of inter-processor interrupts; and for each of the identified I/O completions, accesses the recordation of the most recent delivery time to determine whether a selected period of time has elapsed since a last delivery of an inter-processor interrupt. As a response to a determination that the selected period has elapsed, an inter-processor interrupt is delivers. As a response to a determination that less than the duration of the selected period has elapsed, the method refrains from delivering an inter-processor interrupt.

Method, System, and Apparatus for Dynamic Reconfiguration of Resources

A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware. 12-. (canceled)3. An apparatus comprising:input/output (“I/O”) logic coupled to a point-to-point interconnect capable of coupling caching agents and home agents, the I/O logic including a physical layer to receive an operation based on an interrupt generated in response to an insertion of a resource into a computing system, wherein, in response to the physical layer receiving the operation, the I/O logic to enter a state where no protocol transactions are generated, and wherein during state routing, tables associated with the resource are updated without rebooting an operating system (“OS”) of the computing system.4. The apparatus of claim 3 , wherein if multiple resources are added to multiple OS partitions claim 3 , multiple interrupts are sent to the multiple OS partitions.5. The apparatus of claim 3 , wherein the caching agents and the home agents are coupled to a network fabric adhered to layered protocol scheme and used for transporting messages from one protocol to another protocol claim 3 , wherein the network fabric includes one or more of a link layer claim 3 , a physical layer claim 3 , a protocol layer claim 3 , a routing layer claim 3 , and a transport layer.6. The apparatus of claim 3 , wherein the resource comprises a processor node claim 3 , a memory-only node claim 3 , or an ...

Providing real-time interrupts over ethernet

In one embodiment, a method includes sending a request to one or more distributed fabric protocol (DFP) system members in order to retrieve one or more events from the one or more DFP system members, wherein the one or more events are received as data encapsulated in a packet(s), receiving one or more acknowledgements to the request from the one or more DFP system members at a local network switch of the DFP system master, upon receipt of the at least one packet: decoding the at least one packet to retrieve details of the one or more events using a dedicated processor of the DFP system master, creating and sending a message signaled interrupt (MSI) comprising the details of the one or more events to a local processor of the DFP system master using the dedicated processor, and reading the MSI using the local processor of the DFP system master.

INTERRUPT RETURN INSTRUCTION WITH EMBEDDED INTERRUPT SERVICE FUNCTIONALITY

An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an interrupt handling instruction. Storage circuitry to hold different sets of micro-ops where each set of micro-ops is to handle a different interrupt. First logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for. Second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt. 1. An instruction pipeline implemented on a semiconductor chip , comprising: a) storage circuitry to hold different sets of micro-ops, each set of micro-ops to handle a different interrupt;', 'b) first logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for;', 'c) second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt., 'an execution unit having the following to execute an interrupt handling instruction2. The instruction pipeline of wherein said storage circuitry is a ROM.3. The instruction pipeline of wherein said execution unit further includes look up table circuitry claim 1 , said look up table circuitry to provide a pointer to one of said sets in said storage circuitry in response to a problem code for said interrupt being presented to said look-up table circuitry.4. The instruction pipeline of wherein said look up table circuitry includes a ROM.5. The instruction pipeline of wherein said look up table circuitry is coupled to a register claim 3 , said register to store said problem code.6. The instruction pipeline of wherein further comprising a register to store a return pointer address.7. The instruction pipeline of wherein said register is coupled to said second logic circuitry.8. An instruction pipeline implemented on a semiconductor chip claim 6 , comprising: a) storage ...

SELF CLOCKING INTERRUPT GENERATION IN A NETWORK INTERFACE CARD

A network interface card may issue interrupts to a host in which the determination of when to issue an interrupt to the host may be based on the incoming packet rate. In one implementation, an interrupt controller of the network interface card may issue interrupts to that informs a host of the arrival of packets. The interrupt controller may issue the interrupts in response to arrival of a predetermined number of packets, where the interrupt controller re-calculates the predetermined number based on an arrival rate of the incoming packets. 123-. (canceled)24. A method comprising: [ the value being based on an initial number, a number of interrupts generated during another period of time, and a threshold number of interrupts,', 'the other period of time occurring prior to the first period of time, and, 'applying a function to a value to produce a result,'}, 'using the produced result to determine the number;, 'the number being used to generate an interrupt and being determined based on, 'determining, by a device, a number associated with a first quantity of packets to receive during a first period of time,'}receiving, by the device, the first quantity of packets during the first period of time; 'the second number being different than the number;', 'updating, by the device and based on the received first quantity of packets, the number to a second number,'} 'the second period of time being subsequent to the first period of time;', 'receiving, by the device, a second quantity of packets during a second period of time,'}updating, by the device, the second number based on a relationship between the received second quantity of packets and the second number; andissuing, by the device, the interrupt based on the updated second number.25. The method of claim 24 , further comprising:identifying one or more parameters associated with a rate of issuing the interrupt, 'issuing the interrupt based on the one or more parameters.', 'where, when issuing the interrupt, the method ...

Computer system

There is a need to provide a computer system capable of preventing a failure from propagating and recovering from the failure. VCPU# 0 through VCPU# 2 each operate different OS's. VCPU# 0 operates a management OS that manages the other OS's. When notified of bus error occurrence, a virtual CPU execution portion 201 operates only VCPU# 0 regardless of an execution sequence stored in schedule register A. VCPU# 0 reinitializes a bus where an error occurred.

INFORMATION PROCESSING SYSTEM, IMAGE FORMING APPARATUS, CONTROL METHOD, AND RECORDING MEDIUM

A flow service server group manages a job consisting of multiple tasks generated according to a user request, and a task server acquires a task included in the aforementioned managed job if a processing standby status exists, and carries out specific task processing. The task server notifies the flow service server group at a fixed interval that task processing is in progress. The flow service server group then issues a command to the task server that has not completed task processing within a prescribed time to suspend the task processing, and issues a command to a task server capable of task processing that is identical to the task processing to alternatively execute the task processing. 1. An information processing system comprising:a job management unit configured to manage a job consisting of multiple tasks that is generated in accordance with a user request; andmultiple back-end units configured to acquire tasks from the job management unit if a processing standby status exists, and carry out specific task processing,wherein the back-end units periodically notify the job management unit that task processing is in progress, andwherein the job management unit issues a command to suspend task processing to the back-end unit that has not completed the task processing within a prescribed time, and issues a command for alternative execution of task processing to a back-end unit capable of task processing that is identical to the task processing.2. The information processing system according to claim 1 , wherein the job management unit changes a timing at which a command is issued to suspend the task processing and a command is issued to alternatively execute the task processing according to a task processing time that corresponds to a task processing content.3. The information processing system according to claim 1 , wherein the back-end unit in processing standby status issues task request at fixed time interval to the job management unit to inquire whether or not ...

Facilitating transaction completion subsequent to repeated aborts of the transaction

Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.

PROGRAM EVENT RECORDING WITHIN A TRANSACTIONAL ENVIRONMENT

A transaction is initiated within a computing environment, and based on detecting a program event recording event, an interrupt is presented for the transaction. Subsequent to the interrupt, one or more controls are set to inhibit presentation of another interrupt based on detecting another PER event. Thereafter, the transaction is re-executed and PER events detected during execution of the transaction are ignored. 1. A method of controlling transactional execution in a computing environment , the method comprising:initiating, by a processor, a transaction within a computing environment, the transaction effectively delaying committing transactional stores to main memory until completion of a selected transaction, and wherein presentation of interrupts for the transaction is managed by one or more controls, the one or more controls having state associated therewith;presenting an interrupt for the transaction based on detecting a program event recording (PER) event and the state having a first value, PER being defined as presenting an interrupt based on detecting a PER event, the interrupt causing an address to be saved of a next transaction instruction to be executed; andsuppressing PER event detection for the transaction based on the state having a second value.2. The method of claim 1 , further comprising re-executing the transaction based on the interrupt claim 1 , and wherein the state has the second value indicating suppression of PER event detection claim 1 , wherein presentation of another interrupt based on another PER event is prevented.3. The method of claim 2 , wherein the another PER event is a same event as the PER event or a different event than the PER event.4. The method of claim 1 , wherein the one or more controls comprise an event suppression control to specify a suppression of selected PER events claim 1 , and a transaction end event control to trigger an event based on the selected transaction ending.5. The method of claim 4 , wherein the ...

SYSTEMS AND METHODS FOR ADVANCED INTERRUPT SCHEDULING AND PRIORITY PROCESSING IN A STORAGE SYSTEM ENVIRONMENT

Methods and systems for advanced interrupt processing and scheduling are provided. The system comprises a memory operable to store interrupt priorities, an interface, and a processor operable to acquire incoming interrupts and to handle the incoming interrupts according to the interrupt priorities. The processor is also operable to receive interrupt processing criteria from the interface (sent, for example, from a device not directly coupled with the system), and to modify the interrupt priorities of the memory based upon the interrupt processing criteria without losing incoming processing requests for the system. Additionally, the processor is operable to process the incoming interrupts according to the modified interrupt priorities responsive to modifying the interrupt priorities. 1. A storage controller , comprising:a program memory that stores instructions for operating the storage controller;an interrupt memory that stores interrupt priorities for the storage controller; anda processor coupled to the program memory and the interrupt memory, the processor being operable to acquire interrupts as inputs, and to process the interrupts according to the interrupt priorities;wherein the processor is further operable to receive data sent by a device external to the storage controller, and to modify the interrupt priorities based upon the data without losing incoming processing requests for the storage controller,wherein the processor is further operable to handle the incoming interrupts according to the modified set of interrupt priorities.2. The storage controller of claim 1 , wherein:the interrupt memory comprises registers of a Programmable Interrupt Controller (PIC) coupled with the processor and coupled with a plurality of interrupt sources,wherein the PIC is operable to multiplex signals from the plurality of interrupt sources according to the interrupt priorities stored in the interrupt memory to generate an interrupt signal applied to the processor.3. The ...

Managing interrupts

A process for managing interrupts, which may be performed using electronic circuitry, includes: receiving interrupts bound for a processing device, where the interrupts are received from hardware devices that are configured to communicate with the processing device; generating data containing information corresponding to the interrupts; and sending the data to the processing device.

TASK SCHEDULING METHOD AND MULTI-CORE SYSTEM

A task scheduling method is executed by a multi-core system and includes reading from a profile memory, first information concerning operation of a first task in a single core system; calculating second information concerning operation of a second task in the multi-core system, based on the first information; and setting based on the second information, an operating environment of a core that executes the second task. 1. A task scheduling method executed by a multi-core system , the task scheduling comprising:reading from a profile memory, first information concerning operation of a first task in a single core system;calculating second information concerning operation of a second task in the multi-core system, based on the first information; andsetting based on the second information, an operating environment of a core that executes the second task.2. The task scheduling method according to claim 1 , whereinthe first information includes an operating frequency of a core, a bus or a memory, or a time slice, or latency information of a core, a bus or a memory.3. The task scheduling method according to claim 1 , whereinthe calculating includes calculating the second information based also on operating performance of the multi-core system.4. The task scheduling method according to claim 1 , whereinthe second information includes any one among an operating frequency and a source voltage of the core.5. The task scheduling method according to claim 1 , whereinthe setting includes setting an interrupt permitting mode that permits interrupts when the first task is executed.6. The task scheduling method according to claim 5 , comprisingsuspending any one among the first task and the second task, based on setting of the interrupt permitting mode.7. The task scheduling method according to claim 1 , whereinthe setting include setting based on the first information, the operating environment of a core that executes the first task.8. The task scheduling method according to claim 1 ...

PROCESSOR CORE AND MULTI-CORE PROCESSOR SYSTEM

In one embodiment of the present invention, processor comprising a plurality of processor cores for processing an instruction-execution sequence is provided. Signal path that is able to communicate an inter-core interrupt signal fint is connected to at least two processor cores A and B. Each core of the at least two cores has an inter-core interrupt count setting register (ICSR) and a FIFO counter . Inter-core interrupt synchronization function, inter-core interrupt generation function, and FIFO counter updating function are implemented to the every core. In embodiments of the present invention, a core and a method therefor are also provided. 1. A processor comprising:a plurality of processor cores for processing a sequence of instruction-execution processes, the sequence including inter-process communications (IPCs), anda signal path that is connected to at least two processor cores of the plurality of processor cores and is able to communicate an inter-core interrupt signal fint, an inter-core interrupt count setting register (ICSR) for storing a FIFO depth value, wherein the FIFO depth value indicates a number of entries in a first-in first-out (FIFO) buffer that is used for IPCs between a process in a present processor core and a process in a different processor core and sets an upper limit for a range in the instruction-execution sequence, the range including the IPCs under execution, and', 'a FIFO counter for storing a value for indicating a number of entries currently used in the FIFO buffer, and, 'wherein every processor core of the at least two processor cores has'} inter-core interrupt synchronization function that carries out IPCs between a present processor core and a different processor core, based on at least any of: an inter-core interrupt signal fint received from the different processor core of the at least two processor cores, a value in the FIFO counter, and a value in the ICSR,', 'inter-core interrupt generation function that issues and sends an ...

DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS

Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system 1. A method comprisingreceiving an interrupt;restoring saved state information to a first processor in response to the interrupt;changing at least one clock frequency and at least one operating voltage of the first processor in response to receiving the interrupt;saving state information corresponding to a second processor in response to the interrupt, wherein the first and second processors are asymmetric with respect to each other having different instruction set architectures (ISAs).2. The method of claim 1 , wherein the at least one clock frequency and at least one operating voltage of the first processor is to enable the first processor to be operational.3. The method of claim 2 , further comprising changing at least one clock frequency and at least one operating voltage corresponding to the second processor in response to the interrupt.4. The method of claim 3 , wherein the at least one clock frequency and at least one operating voltage corresponding to the second processor is to enable the second processor to be non-operational.5. The method of claim 4 , wherein at least one interrupt corresponds to the first processor and at least one interrupt corresponds to the second processor.6. The method of claim 1 , wherein the second processor has an x86 ISA claim 1 , such that a program using x86 instructions needs to be translated into instructions of a different ISA corresponding to the first processor.7. The method of claim 6 , wherein the x86 instructions are to be translated into instructions of the different ISA corresponding to the first processor by a software binary translation shell. This application is a Divisional, which claims benefit under 35 USC §120 of application Ser. No. 12/220,092, ...

RESOURCE MANAGEMENT IN A MULTICORE ARCHITECTURE

A resource management and task allocation controller for installation in a multicore processor having a plurality of interconnected processor elements providing resources for processing executable transactions, at least one of said elements being a master processing unit, the controller being adapted to communicate, when installed, with each of the processor elements including the master processing unit, and comprising control logic for allocating executable transactions within the multicore processor to particular processor elements in accordance with pre-defined allocation parameters. 1. A method of handling an external interrupt in a multicore processor comprising a plurality of processor elements , the method comprising:configuring an interrupt service thread in an initial queue of the multicore processor, the initial queue comprising threads awaiting the occurrence of an event for execution;receiving an external interrupt from outside the multicore processor at a controller of the multicore processor; andallocating the interrupt service thread to one of the plurality of processor elements in response to the received external interrupt by moving the interrupt service thread from the initial queue to a dispatch queue of the allocated processor element.2. The method of claim 1 , wherein the initial queue is a pending queue and wherein allocating the interrupt service thread to one of the plurality of processor elements comprises generating a synchronization primitive at the controller of the multicore processor.3. The method of claim 1 , wherein the initial queue is a timer queue claim 1 , wherein the interrupt service thread is configured in response to the received external interrupt claim 1 , and wherein allocating the interrupt service thread to one of the plurality of processor elements occurs at a specified time after configuring the interrupt service thread.4. The method of claim 1 , further comprising:configuring a second thread in the initial queue of the ...

LOW PIN COUNT CONTROLLER

Described herein is a system having a multi-host low pin count (LPC) controller () configured to facilitate sharing of common peripheral devices by multiple hosts () of a multi-host computing system (). In one implementation, the multi-host LPC controller () interfaces with the hosts () via an ON-chip bus or an LPC-IN-chip bus. Further, the multi-host LPC controller () includes a LPC-IN controller () and a microcontroller () to moderate among requests generated by the hosts (). The requests can be target accesses, DMA accesses, and BM accesses. Also, the multi-host LPC controller () is configured to operate in a software mode and an auto mode. Based on the mode the multi-host LPC controller () is operating in, the requests generated by the various hosts are moderated. 1100. A Low Pin Count (LPC) controller () comprising:{'b': 130', '110', '110, 'an LPC-IN unit () configured to receive one or more target access requests for accessing a LPC device coupled to a multi-host computing system (), from at least one host of the multi-host computing system ();'}{'b': '160', 'claim-text': [{'b': '100', 'generate an interrupt for each of the one or more target access requests, based on an operational mode of the LPC controller ();'}, {'b': '100', 'analyze the one or more target access requests based on an operational mode of the LPC controller () on generation of the interrupt;'}], 'a LPC-IN controller () configured to,'}{'b': '155', 'claim-text': arbitrate the one or more target access requests on receiving the interrupt based on the analysis; and', 'provide access to the LPC device based in part on the arbitration and a sharing mechanism supported by the LPC device., 'a microcontroller () configured to'}2100100110110110. The LPC controller () as claimed in claim 1 , wherein the operational mode of the LPC controller () is at least one of a software mode claim 1 , wherein access is provided to at least one host of the multi-host computing system () based on the arbitration ...

ADAPTIVE INTERRUPT MODERATION

Generally, this disclosure relates to adaptive interrupt moderation. A method may include determining, by a host device, a number of connections between the host device and one or more link partners based, at least in part, on a connection identifier associated with each connection; determining, by the host device, a new interrupt rate based at least in part on a number of connections; updating, by the host device, an interrupt moderation timer with a value related to the new interrupt rate; and configuring the interrupt moderation timer to allow interrupts to occur at the new interrupt rate. 1. A method comprising:determining, by a host device, a number of connections between the host device and one or more link partners based on, at least in part, a connection identifier associated with each connection;determining, by the host device, a new interrupt rate based at least in part on a number of connections;updating, by the host device, an interrupt moderation timer with a value related to the new interrupt rate, and;configuring the interrupt moderation timer to allow interrupts to occur at the new interrupt rate.2. The method of claim 1 , further comprising generating claim 1 , by the host device claim 1 , the connection identifier associated with each connection based on claim 1 , at least in part claim 1 , a received packet.3. The method of claim 1 , further comprising determining claim 1 , by the host device claim 1 , a number of packets received during an interrupt moderation interval claim 1 , wherein the new interrupt rate is determined based on claim 1 , at least in part claim 1 , the number of packets received.4. The method of claim 1 , further comprising determining claim 1 , by the host device claim 1 , an average packet size of packets received during an interrupt moderation interval claim 1 , the average packet size corresponding to a sum of sizes of packet payloads divided by a number of packets received claim 1 , wherein the new interrupt rate is ...

METHOD AND PROGRAM FOR SELECTIVE SUSPENSION OF USB DEVICE

A method provides device selective suspension feature when the operating system does not allow certain device drivers to perform device selective suspension. Two driver stacks are provided in the kernel space for the device. The first driver stack includes a virtual bus, a PDO (physical device object) created by the virtual bus, and a driver for the device (e.g. NDIS driver); the second stack includes a device driver stack (e.g. USB generic driver) and a function driver that performs device selective suspension by sending power IRPs to the device driver stack. By using a virtual bus and PDOs created by the virtual bus in the first driver stack, the driver above the PDO can be any one of many types of drivers (NDIS driver being one example). The virtual bus forwards IRPs from the first driver stack to the second driver stack. 1. A method for controlling a device coupled to a host computer , comprising:providing a first driver stack in a kernel space of an operating system (OS) of the host computer, wherein the first driver stack comprises a virtual bus, a physical device object created by and coupled to the virtual bus, and a first device driver coupled to the physical device object, to interact with user applications in a user space of the OS; andproviding a second driver stack in the kernel space of the OS, wherein the second driver stack comprises a function driver and a second device driver for the device, to interact with the device, wherein the function driver is coupled to the first driver stack and the second device driver is coupled to the function driver, wherein the second driver stack forwards data from the virtual bus of the first driver stack to the device, and wherein the function driver issues a command to the second device driver to selectively suspend the device, andwherein the first driver stack and the second driver stack are distinct, and the first device driver and the function driver are distinct.2. The method of claim 1 , wherein when the ...

Interrupt Priority Management Using Partition-Based Priority Blocking Processor Registers

A method and circuit for a data processing system ( 20 ) provide a processor-based partitioned priority blocking mechanism by storing priority levels and associated partition information in special purpose registers ( 27 - 29 ) located at the processor core ( 26 ) to enable quick and efficient interrupt priority blocking on a partition basis.

PROCESSOR, INFORMATION PROCESSING APPARATUS, AND INTERRUPT CONTROL METHOD

An input/output interface unit includes a plurality of ports connected to different external units, and adds predetermined identification information unique to each of the ports to an interrupt request received from each of the external units via the ports. An interrupt control unit stores information on the interrupt request received by the input/output interface unit in a vector storage unit based on the identification information. Each of cores executes a process corresponding to the interrupt request stored in the vector storage unit based on the identification information. 1. A processor comprising:an input/output interface unit that includes a plurality of ports each being connected to a different external unit, and that adds predetermined identification information unique to each of the ports to an interrupt request received from each of the external units via the ports;an interrupt control unit that stores information on the interrupt request received by the input/output interface unit in a register based on the identification information; anda process executing unit that executes a process corresponding to the interrupt request stored in the register based on the identification information.2. The processor according to claim 1 , further comprising a plurality of the process executing units claim 1 , whereinthe interrupt control unit stores information on the interrupt request in a register corresponding to a process executing unit designated by the received interrupt request, and sends a notice of the interrupt request to the process executing unit corresponding to the register according to a priority order contained in the identification information of the interrupt request stored in the register, andthe process executing unit sequentially performs processes corresponding to the interrupt requests notified by the interrupt control unit.3. The processor according to claim 1 , wherein when a process by another interrupt control circuit is designated by the ...

Data processing system and data processor

One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.

Information processing apparatus, information processing method, computer-readable recording medium having stored therein program

A first computing device includes a data transmission processing unit transmitting data to be transferred to another computing device to a first storage area among the plurality of storage areas, and an interrupt generating unit generating an interrupt corresponding to transmission of data by the data transmission processing unit with respect to a transmission destination of the data together with identification information specifying the storage area, and a second computing device includes an interrupt processing unit specifying from which computing device the interrupt is requested based on the identification information received together with the interrupt when receiving the interrupt, and a data receiving unit reading out data from the first storage area corresponding to the computing device specified by the interrupt processing unit among the plurality of storage areas to efficiently communicate among computing devices in an information processing apparatus including a plurality of computing devices.

Method for implementing secure data channel between processor and devices

Apparatuses, systems, and methods are directed to securely store, transfer, and/or process data especially sensitive data sent from input devices to processors. In one embodiment, sensitive data may be packaged with at least one interrupt vector to provide a single posted write transaction initiated by an input device. The single posted write transaction may then be directly sent to a predetermined memory block allocated from a processor. In response to the single posted write transaction, a memory decoder associated with the processor may generate an emulated message signaled interrupt (MSI) signal to invoke an interrupt handler or an interrupt service routine (ISR) to service the emulated MSI using interrupt data, including the sensitive data, retrieved from the predetermined memory block. Once the sensitive data are processed by the processor, they may be removed from the processor before the processor exits the interrupt handler.

ARCHITECTURE AND METHOD FOR MANAGING INTERRUPTS IN A VIRTUALIZED ENVIRONMENT

A method may comprise identifying a signal indicating real-time mode operation for a guest operating system (OS) and directly routing an interrupt for a first processor to the guest OS while the guest OS is running without causing a transition from execution by the guest OS to execution by a host system. Other embodiments are disclosed and claimed. 1. A computer implemented method , comprising:identifying a signal indicating real-time mode operation for a guest operating system (OS); anddirectly routing an interrupt for a first processor to the guest OS while the guest OS is running without causing a transition from execution by the guest OS to execution by a host system.2. The computer implemented method of claim 1 , comprising claim 1 , in response to the signal claim 1 , clearing a bit in a virtual machine control structure (VMCS) that indicates an external interrupt is to generate a virtual machine (VM) exit wherein a transition from execution by the guest OS to execution by a host system occurs.3. The computer implemented method of claim 1 , comprising pinning the guest OS to the first processor during real-time operation of the guest OS.4. The computer implemented method of claim 1 , comprising disabling the guest OS from performing a virtual machine (VM) exit operation when the guest OS executes an HLT instruction.5. The computer implemented method of claim 1 , comprising instructing a bootstrap processor to forward an interrupt generated by a hard drive as an inter-processor-interrupt (IPI) to the guest OS.6. The computer implemented method of claim 1 , comprising setting a direct translation structure for interrupts to be forwarded to the guest OS.7. The computer implemented method of claim 1 , comprising translating the interrupts into an interrupt format of the guest operating system.8. The computer implemented method of claim 1 , comprising programming a virtual advanced programmable interrupt controller (APIC) coupled to the first processor to prevent a ...

METHOD AND AN APPARATUS FOR COHERENCY CONTROL

The subject matter discloses a method for data coherency; the method comprising receiving an interrupt request for interrupting a CPU; wherein the interrupt request is from one of a plurality of modules; wherein the interrupt request notifying a writing instruction of a first data by the one of the plurality of modules to a shared memory; and wherein the shared memory is accessible to the plurality of modules through a shared bus; suspending the interrupt request; validating a completion of an execution of the writing instruction; wherein the validating is performed after the suspending; and resuming the interrupt request after the completion of the execution of the writing is validated, whereby to notify a to the CPU about the completion of the execution of the writing instruction. 1. A method for data coherency; the method comprising:receiving by a coherency control module (CCM), an interrupt request for interrupting a central processing unit (CPU), wherein the CPU is coupled to the CCM; wherein the interrupt request is from one of a plurality of modules; wherein the interrupt request is for notifying of a writing instruction of a first data by the one of the plurality of modules to a shared memory; and wherein the shared memory is accessible to the plurality of modules through a shared bus;suspending, by the CCM, the interrupt request by preventing the CPU from receiving the interrupt request;validating, by the CCM, a completion of execution of the writing instruction; andresuming the interrupt request by sending the interrupt request to the CPU.2. The method of claim 1 , wherein the validating is performed after the suspending.3. The method of claim 1 , wherein the resuming is performed after the completion of execution of the writing is validated.4. The method of claim 1 , wherein the resuming is performed for notifying the CPU about the completion of execution of the writing instruction.5. The method of claim 1 , wherein the validating further comprises ...

Enhanced I/O Performance in a Multi-Processor System Via Interrupt Affinity Schemes

Disclosed herein is a method for improving Input/Output (I/O) performance in a host system having multiple CPUs. Under this method, various interrupt affinity schemes are provided, which associate multiple processors, interrupts, and I/O channels for sending the interrupts, thereby allowing the interrupts to be almost evenly loaded among the multiple I/O channels and processors. Also, data locality (“warm cache”) can be achieved through the interrupt affinity schemes that associate each interrupt to its source processor, namely, the processor originating the I/O request that results in the interrupt. 130-. (canceled)31. A system for controlling interrupt processing , the system comprising:an adapter operable to generate an interrupt, wherein the interrupt is communicated over a channel selected from a plurality of channels and the interrupt is processed by a processor selected from a plurality of processors,wherein the processor is selected according to a first mapping and the channel is selected according to a second mapping, andwherein the second mapping comprises an association between the interrupt and the channel and the second mapping is adaptable based on a usage of one or more processors of the plurality of processors.3251-. (canceled)52. The system of claim 31 , wherein the adapter comprises a network adapter that is operable to communicate with a Storage Area Network (SAN) over a number of communication links claim 31 , the communication links comprising one or both of: Fibre Channel links and Ethernet links.53. The system of claim 31 , wherein the system comprises:a plurality of Local Advanced Programmable Interrupt Controllers (LAPICs), each LAPIC of the plurality of LAPICs is associated with a processor of the plurality of processors, wherein a LAPIC of the plurality of LAPICs is operable to assist with processing an interrupt; anda plurality of caches, each cache of the plurality of caches is associated with a LAPIC of the plurality of LAPICs, wherein ...

Allocation of flow control credits for high performance devices

Methods and apparatus relating to allocation of flow control credits for high performance devices are described. In some embodiments, controls and/or configuration structures may be provided for the OS (Operating System) or VMM (Virtual Machine Manager) to indicate possible processor affinity (e.g., of a device driver for a given PCIe device) to the platform components (in a platform dependent fashion, for example). Using this data, the platform components could configure the RC (Root Complex) ports and/or intermediate components (such as switches, bridges, etc.) to pre-allocate buffers for the links coupling the PCIe device to the RC ports or intermediate components. Other embodiments are also disclosed and claimed.

Application management of a processor performance monitor

A method for an operating system (OS) enabling an application direct control of a performance monitoring unit (PMU) including enabling the PMU to notify the application when a PMU exception occurs without interrupting the OS by controllably encoding a redirect field in an OS accessible control register, and enabling the application to reinitialize the PMU after the PMU exception.

COMMUNICATION DEVICE, COMMUNICATION METHOD AND COMPUTER-READABLE RECORDING MEDIUM

There is provided a communication device which communicates with a target communication device, including: a communication controller, a general-purpose processing unit, a data transfer processing unit and a starting unit. The general-purpose processing unit communicates with the target communication device via the communication controller. The data transfer processing unit receives data from the target communication device via the communication controller. The starting unit starts up the data transfer processing unit. The general-purpose processing unit receives a data transfer start request from the target communication device. The starting unit starts up the data transfer processing unit when the general-purpose processing unit receives the data transfer start request. The general-purpose processing unit or the data transfer processing unit notifies a data transfer start response to the target communication device after the data transfer processing unit is started up. 1. A communication device which communicates with a target communication device , comprising:a communication controller;a general-purpose processing unit configured to communicate with the target communication device via the communication controller;a data transfer processing unit configured to receive data from the target communication device via the communication controller; anda starting unit configured to start up the data transfer processing unit,wherein the general-purpose processing unit receives a data transfer start request from the target communication device,the starting unit starts up the data transfer processing unit when the general-purpose processing unit receives the data transfer start request, andthe general-purpose processing unit or the data transfer processing unit notifies a data transfer start response to the target communication device after the data transfer processing unit is started up.2. The communication device according to claim 1 , further comprising:a mode management ...

SYSTEM FOR ELECTRICALLY CONNECTING CABIN EQUIPMENT OF AN AIRCRAFT TO A CONTROL SYSTEM AND TO AT LEAST ONE ELECTRICAL POWER SUPPLY SOURCE OF THE AIRCRAFT

A system for electrically connecting a piece of cabin equipment of an aircraft to a control system and to at least one electrical power supply source of the aircraft. The connection system comprises a host interface module to which the control system and the at least one electrical power supply source are connected. The host interface module ensures the conversion of data signals originating from the control system and a transfer of voltages of the at least one power supply source to power supply/data signals that conform to a given protocol. An interface module integrated in the cabin equipment ensures the conversion of the power supply/data signals conforming to the given protocol to data signals for controlling at least one electrical service element of the cabin equipment and the transfer of the voltages of the at least one power supply source to the at least one electrical service element. 1. A system for electrically connecting a piece of cabin equipment of an aircraft to a control system and to at least one electrical power supply source of the aircraft , the connection system comprising:a host interface module to which the control system and the at least one electrical power supply source are connected, the host interface module configured to ensure a conversion of data signals originating from the control system and a transfer of voltages from the at least one power supply source to power supply/data signals that conform to a given protocol, the power supply/data signals being provided at terminals of a host connector;an equipment interface module integrated in the cabin equipment, the interface module being connected to an equipment connector and to at least one electrical service element of the cabin equipment, the equipment interface module ensuring a conversion of the power supply/data signals conforming to the given protocol that are present on the equipment connector to control data signals for controlling the at least one electrical service element ...

EXCEPTION HANDLING IN MICROPROCESSOR SYSTEMS

A microprocessor system () includes a host processor (),a graphics processing unit (GPU) () that includes a number of processing cores (), and an exception handler. When a thread that is executing on a processing core () encounters an exception in its instruction sequence, the thread is redirected to the exception handler. However, the exception event is also communicated to a task manager () of the GPU The task manager () then broadcasts a cause exception message to each processing core (). Each processing core then identifies the threads that it is currently executing that the cause exception message relates to, and redirects those threads to the exception handler. In this way, an exception caused by a single thread is broadcast to all threads within a task. 1. A microprocessor system comprising:one or more processing cores, each core operable to execute plural execution threads in parallel;a task manager operable to issue tasks to the processing cores for processing; andan exception handler operable to handle threads that encounter exceptions during their execution;wherein:at least one of the processing cores is configured to, when a thread it is executing encounters an exception or wishes to generate an exception, trigger an exception event to the task manager;the task manager is configured to, when it receives an indication of an exception event from a processing core, broadcast a cause exception message to at least one of the processing cores; andthe processing cores are configured to, when they receive a broadcast cause exception message from the task manager, identify any threads that the core is currently executing that the cause exception message applies to, and to redirect any such identified threads to the exception handler for handling.2. The system of claim 1 , wherein the processing cores are graphics processing cores.3. The system of claim 1 , further comprising a host processor that is operable to indicate tasks to be performed to the task manager ...

Computer System

A problem to be solved by the present invention is, in a computer system, to reduce processing delay from wait times which occur in timer access. According to the present invention, using either a CPU core (hereinafter “processing core”) other than a CPU core which executes an application, or a DMA device, a latest timer value is always transferred from a timer device to a primary storage device. The processing core reads the transferred value upon the primary storage device instead of accessing a register of the timer device, thereby avoiding a wait which occurs when directly reading the timer value of the timer device. The transfer of the value is carried out asynchronously from the processing of the processing core, thus obviating the need for the processing core to wait for the completion of the transfer. Accordingly, it is also unnecessary for the processing core to process an interrupt or a notification from another CPU core or the DMA device. 1. A computer system comprising a first processing unit , a second processing unit , a primary storage device , and a timer device , whereinthe timer device stores in the timer device timestamp information and includes a timestamp register accessible from the second processing unit,the primary storage device includes a timestamp transfer buffer that stores in the primary storage device the timestamp information that the second processing unit read from the timestamp register of the timer device,the first processing unit reads the timestamp information from the timestamp transfer buffer, andthe second processing unit stores the timestamp information in the timestamp transfer buffer at a different timing from the first processing unit reading the timestamp information.2. The computer system according to claim 1 , whereinthe primary storage device comprises a counter area that stores therein count information, and the first processing unit updates the count information upon reading the timestamp information of the timestamp ...

INTEGRATED CIRCUIT DEVICE INCLUDING WAKE-UP CONTROL CIRCUIT AND ELECTRONIC DEVICE INCLUDING THE SAME

An integrated circuit device is provided. The integrated circuit device may include a central processing unit (CPU) configured to operate in one of a plurality of modes and a wake-up control circuit configured to control the CPU. The wake-up control circuit may include a clock generator configured to generate an internal clock signal, a multiplexer configured to select a signal from among an external signal and the internal clock signal and to provide the CPU with the selected signal as an operating clock signal, and a controller configured to control the CPU and the clock generator based on the external signal. 1. An integrated circuit device comprising:a central processing unit (CPU) configured to operate in one of a plurality of modes; and a clock generator configured to generate an internal clock signal,', 'a multiplexer configured to select a signal from among an external signal and the internal clock signal and to provide the CPU with the selected signal as an operating clock signal, and', 'a controller configured to control the CPU and the clock generator based on the external signal., 'a wake-up control circuit configured to control the CPU, the wake-up control circuit comprising2. The integrated circuit device of claim 1 , wherein the controller is configured to function as a finite state machine (FSM) and count edges of the external signal.3. The integrated circuit device of claim 1 , wherein the controller is configured to count edges of the external signal and generate a clock enable signal to activate the clock generator when a count value of the controller reaches a first reference value claim 1 , andwherein the clock generator is configured to generate the internal clock signal based on the clock enable signal and output the internal clock signal to the multiplexer.4. The integrated circuit device of claim 3 , wherein the controller is further configured to output a wake-up signal to the CPU when the count value of the controller reaches a second ...

TECHNIQUES FOR HYBRID COMPUTER THREAD CREATION AND MANAGEMENT

A technique for operating a computer system to support an application, a first application server environment, and a second application server environment includes intercepting a work request relating to the application issued to the first application server environment prior to execution of the work request. A thread adapted for execution in the first application server environment is created. A context is attached to the thread that non-disruptively modifies the thread into a hybrid thread that is additionally suitable for execution in the second application server environment. The hybrid thread is returned to the first application server environment. 1. A method of operating a computer system to support an application , a first application server environment , and a second application server environment , the method comprising:intercepting, by a request interceptor component executing on the computer system, a work request relating to the application issued to the first application server environment prior to execution of the work request;responsive to the request interceptor component, creating, using the computer system, a thread adapted for execution in the first application server environment by an executor component;responsive to the executor component, attaching to the thread, by a thread dispatcher component executing on the computer system, a context to non-disruptively modify the thread into a hybrid thread that is additionally suitable for execution in the second application server environment; andresponsive to the thread dispatcher component, returning the hybrid thread to the first application server environment by a catcher component executing on the computer system.2. The method of claim 1 , wherein the context comprises transactional control data of one of the application server environments claim 1 , security control data of one of the application server environments claim 1 , monitoring control data of one of the application server environments ...

OPTIMIZING SOFTWARE-DIRECTED INSTRUCTION REPLICATION FOR GPU ERROR DETECTION

A thread execution method in a processor includes executing original instructions of a first thread in a first execution lane of the processor, and interleaving execution of duplicated instructions of the first thread with execution of original instructions of a second thread in a second execution lane of the processor. 1. A thread execution method comprising:executing original instructions of a first thread in a first execution lane of a processor; andinterleaving execution of duplicated instructions of the first thread with execution of original instructions of a second thread in a second execution lane of the processor.2. The thread execution method of claim 1 , further comprising:interleaving execution of duplicated instructions of a third thread with execution of the original instructions of the first thread in the first execution lane of the processor.3. The thread execution method of claim 1 , further comprising:performing an integrity verification on results of the execution of the original instructions of the first thread and results of the execution of the duplicated instructions of the first thread.4. The thread execution method of claim 3 , further comprising: moving execution of the original instructions of the first thread to a different execution lane than the first execution lane of the processor;', 'moving execution of the duplicate instructions of the first thread to a different execution lane than the second execution lane of the processor; and', 'duplicating and executing the original instructions of the first thread on a third or more execution lanes of the processor., 'on condition that the verification instructions detect an execution error, performing one or more of5. The thread execution method of claim 3 , wherein the integrity verification is triggered by reaching an exit point of the first thread.6. The thread execution method of claim 1 , further comprising claim 1 , for each of threads i claim 1 , where i=1 to N (N≥2):{'sup': 'th', ' ...

APPARATUS AND METHOD FOR CONFIGURING SETS OF INTERRUPTS

An apparatus and method are described for efficiently processing and reassigning interrupts. For example, one embodiment of an apparatus comprises: a plurality of cores; and an interrupt controller to group interrupts into a plurality of interrupt domains, each interrupt domain to have a set of one or more interrupts assigned thereto and to map the interrupts in the set to one or more of the plurality of cores. 1a plurality of cores; andan interrupt controller to group interrupts into a plurality of interrupt domains, each interrupt domain to have a set of one or more interrupts assigned thereto and to map the interrupts in the set to one or more of the plurality of cores.. An apparatus comprising: This application is a continuation of U.S. application Ser. No. 14/861,618, filed Sep. 22, 2015, which claims priority under 35 U.S.C. § 119 to Indian Patent Application No. 4721/CHE/2014, filed Jan. 6, 2015, entitled, “Apparatus And Method For Configuring Sets Of Interrupts” which claims the benefit of Indian Provisional Patent Application No. 4721/CHE/2014, filed Sep. 26, 2014, entitled, “Apparatus And Method For Configuring Sets Of Interrupts” all of which is herein incorporated by reference.Embodiments of the invention relate generally to the field of computer systems. More particularly, the embodiments of the invention relate to an apparatus and method for programming sets of interrupts.In computing systems, an interrupt is a signal generated by hardware or software indicating an event that needs immediate attention from the processor (i.e., requiring an interruption of the current thread the processor is executing). The processor responds by suspending its current execution thread, saving the state (so that it can re-start execution where it left off), and executing a function referred to as an interrupt handler to service the event. The interruption is temporary; after the interrupt handler completes, the processor resumes execution of the thread.Hardware ...

MONITORING PERFORMANCE OF A PROCESSOR USING RELOADABLE PERFORMANCE COUNTERS

In accordance with embodiments disclosed herein, there is provided systems and methods for monitoring performance of a processor to manage events. A processor includes a first performance counter to increment upon occurrence of a first type of event in the processor and a second performance counter to increment upon occurrence of a second type of event in the processor. The processor is to reset the second performance counter in response to the first performance counter reaching a first limit. 1. A processor comprising:a first performance counter to increment upon occurrence of a first type of event in the processor; anda second performance counter to increment upon occurrence of a second type of event in the processor, wherein the processor is to reset the second performance counter in response to the first performance counter reaching a first limit.2. The processor of claim 1 , wherein the processor is to generate a record in response to the second performance counter reaching a second limit.3. The processor of claim 2 , wherein the record defines a state of the processor at a time of generation of the record.4. The processor of claim 1 , wherein the processor is to generate an interrupt in response to the second performance counter reaching a second limit.5. The processor of claim 1 , wherein the processor is to monitor performance of the processor based on the second performance counter reaching a second limit.6. The processor of claim 1 , wherein the processor is to perform event based sampling based on the second performance counter reaching a second limit.7. The processor of claim 1 , wherein the processor is to determine that the processor is operating at an unexpected rate based on the second performance counter reaching a second limit.8. A method comprising:incrementing a first value in a first performance counter upon occurrence of a first type of event in a processor;incrementing a second value in a second performance counter upon occurrence of a second ...

CENTRALIZED SCHEDULING SYSTEM USING EVENT LOOP FOR OPERATING AUTONOMOUS DRIVING VEHICLES

An event queue is maintained to store IO events generated from a number of sensors and timer events generated for a number of autonomous driving modules. For each of the events pending in the event queue, in response to determining that the event is an IO event, the data associated with the IO event is stored in a data structure associated with the sensor in a global store. In response to determining that the event is a timer event, a worker thread associated with the timer event is launched. The worker thread executes one of the autonomous driving modules triggered or initiated the timer event. Input data is retrieved from the global store and provided to the worker thread to allow the worker thread to process the input data. 1. A computer-implemented method for operating an autonomous driving vehicle , the method comprising:maintaining an event queue to store input and output (IO) events generated from a plurality of sensors and timer events generated for a plurality of autonomous driving modules; and in response to determining that the event is an IO event, storing data associated with the IO event in a global store, and', launching a worker thread associated with the timer event, the worker thread executing one of the autonomous driving modules triggering the timer event, and', 'providing input data retrieved from the global store to the worker thread to allow the worker thread to process the input data., 'in response to determining that the event is a timer event,'}], 'for each of the events stored in the event queue, iteratively performing'}2. The method of claim 1 , wherein executing a worker thread associated with one of the autonomous driving modules comprises:identifying a first autonomous driving module based on a first timer event; andlaunching a first worker thread to executing the first autonomous driving module.3. The method of claim 2 , further comprising:identifying first input data stored in the global store that is associated with the first timer ...

Scheduling Method, PCIe Switch and Electronic System Using the Same

The present invention provides a scheduling method for a peripheral component interconnect express (PCIe) switch of an electronic system. The PCIe switch is utilized for handling input/output requests of a host of the electronic system. The scheduling method includes the PCIe switch determining a scheduling sequence of message signal interrupts (MSIs) and read/write requests corresponding to the input/output requests according to amount of the message signal interrupts corresponding to the input/output requests; and the PCIe switch handling the message signal interrupts and the read/write requests according to the scheduling sequence. 1. A scheduling method for a peripheral component interconnect express (PCIe) switch of an electronic system , the PCIe switch is utilized for handling input/output requests of a host of the electronic system , the scheduling method comprising:the PCIe switch determining a scheduling sequence of message signal interrupts (MSIs) and read/write requests corresponding to the input/output requests according to an amount of the MSIs corresponding to the input/output requests; andthe PCIe switch handling the MSIs and the read/write requests according to the scheduling sequence.2. The scheduling method of claim 1 , wherein the scheduling sequence is determined based on an amount of data transmission claim 1 , an amount of the input/output requests or an application environment of the host.3. The scheduling method of claim 1 , wherein once the PCIe switch schedules each of a first number of the MSIs claim 1 , the PCIe switch schedules a second number of the read/write requests.4. The scheduling method of claim 3 , wherein the first number and the second number are determined based on an amount of data transmission claim 3 , an amount of the input/output requests or an application environment of the host.5. The scheduling method of claim 3 , wherein when the amount of the MSIs is smaller than the first number claim 3 , the PCIe switch schedules ...

Programmable Adapter Between Slow Peripherals and Network On-Chip Interfaces

A method and system for adapting communication between a low-speed interface and a high-speed interface is disclosed. The method includes retrieving configuration instructions in response to a power-up of a microcontroller, where the configuration instructions associated with a low-speed communication protocol. The method includes sending the configuration instructions to a low-speed interface module causing the low-speed interface module to configure an interface of the low-speed interface module based on the configuration instructions. The method includes receiving, by the interface of the low-speed interface module, data associated with the low-speed communication protocol. The method includes retrieving, by the microcontroller, mapping instructions associated with a high-speed communication protocol. The method also includes sending, by the microcontroller, the mapping instructions to the low-speed interface module, causing the low-speed interface module to convert the data associated with the low-speed communication protocol to data associated with the high-speed communication protocol. 1. A method for adapting communication between a low-speed interface and a high-speed interface , the method comprising:retrieving, by a microcontroller and via a memory bus, configuration instructions in response to a power-up of the microcontroller, the configuration instructions associated with a low-speed communication protocol;sending, by the microcontroller and via an address/data bus, the configuration instructions to a low-speed interface module causing the low-speed interface module to configure an interface of the low-speed interface module based on the configuration instructions;entering, by the microcontroller, a low-power mode;receiving, by the interface of the low-speed interface module, data associated with the low-speed communication protocol;changing, by the low-speed interface module and in response to receiving the data, a state of an interrupt signal causing ...

Method, Apparatus And System For Dynamic Control Of Clock Signaling On A Bus

In an embodiment, a host controller includes a clock control circuit to cause the host controller to communicate a clock signal on a clock line of an interconnect, the clock control circuit to receive an indication that a first device is to send information to the host controller and to dynamically release control of the clock line of the interconnect to enable the first device to drive a second clock signal onto the clock line of the interconnect for communication with the information. Other embodiments are described and claimed. 1. An apparatus comprising:a host controller to couple to an interconnect to which a plurality of devices may be coupled, the host controller including a clock control circuit to cause the host controller to communicate a clock signal on a clock line of the interconnect, the clock control circuit to receive an indication that a first device of the plurality of devices is to send information to the host controller and to dynamically release control of the clock line of the interconnect to enable the first device to drive a second clock signal onto the clock line of the interconnect for communication with the information, wherein the first device is a clock source capable device.2. The apparatus of claim 1 , wherein the host controller is to release the control of the clock line in response to an in-band interrupt from the first device claim 1 , the first device comprising a slave device.3. The apparatus of claim 1 , further comprising a configuration storage to store configuration information for the plurality of devices claim 1 , the configuration information to indicate whether each of the plurality of devices is a clock source capable device.4. The apparatus of claim 3 , wherein the host controller is to send a configuration request and the first device is to provide the configuration information of the first device in response thereto.5. The apparatus of claim 3 , wherein the configuration storage includes an entry for the first device ...

DUAL-DRIVER INTERFACE

A network interface device capable of communication with a data processing system supporting an operating system and at least one application, the network interface device supporting communication with the operating system by means of: two or more data channels, each data channel being individually addressable by the network interface device and being capable of carrying application-level data between the network interface device and the data processing device; and a control channel individually addressable by the network interface device and capable of carrying control data between the network interface device, the control data defining commands and the network interface being responsive to at least one command sent over the control channel to establish at least one additional data channel. 1. A network interface device capable of communication with a data processing system supporting an operating system and at least one application , the network interface device supporting communication with the operating system by means of:a first driver configured to transfer data between the network interface device and the data processing device, the first driver having a first event queue;a second driver configured to transfer data between the network interface device and the data processing device, the second driver having a second event queue; and provide data to each driver independently by placing an event data block on the event queue associated with the respective driver; and', 'request execution of the driver by raising an interrupt., 'the network interface device configured to2. The network interface device of wherein the transfer of data between the network interface and the data processing device by the first driver is independent of the transfer of data between the network interface device and the data processing apparatus by the second stack.3. The network interface device of wherein the first and second drivers are vertically separate.4. The network interface ...

CONTROL DEVICE AND IMAGE FORMING APPARATUS

A control device includes an apparatus controller that is connected to at least one apparatus and includes a first memory which stores data for controlling the driving of the apparatus and data indicating a state of the apparatus and a reading and transmitting unit which reads each data item stored in the first memory and transmits the read data, a main controller that includes a central processing unit, a second memory, and a writing unit which writes the data transmitted from the apparatus controller to the second memory, and a full-duplex serial bus that connects the main controller and the apparatus controller. The reading and transmitting unit and the writing unit operate such that each data item stored in the first memory is read, transmitted, and stored in the second memory in a cycle equal to or less than a count cycle of a system timer. 1. A control device comprising:a first controller that is connected to at least one apparatus and includes a first memory that stores data for controlling the driving of the at least one apparatus and data indicating a state of the at least one apparatus;a second controller that is connected to a bus of a central processing unit and includes a second memory to which data is copied from the first memory; anda full-duplex serial bus that connects the first controller and the second controller,wherein the second controller reads the data which is copied in the second memory and supplies the data which is read from the second memory to the central processing unit when the second controller receives a read request from the central processing unit.2. The control device according to claim 1 ,the first controller further including:a reading and transmitting unit which reads each data item stored in the first memory and transmits the read data, 'a writing unit which writes the data transmitted from the first controller to the second memory,', 'the second controller further includingwherein the reading and transmitting unit and the ...

Mechanism for Dual Active Detection Link Monitoring in Virtual Switching System with Hardware Accelerated Fast Hello

Methods and systems are disclosed. Methods and systems include enabling MacSec in a frontside stacking environment. The method includes: creating a prepended frame descriptor to a packet; and placing SecTag control information in the prepended frame descriptor. Further methods and systems include enabling Pause and OAM in a frontside stacking environment. The method includes: identifying a size of a packet; and if the size of a packet is less than or equal to 64 bytes, examining the packet for a Pause or an OAM frame format. 1. A method of enabling MacSec in a frontside stacking environment , comprising:creating a prepended frame descriptor to a packet; andplacing a SecTag in the prepended frame descriptor.2. The method of claim 1 , further comprising placing SecTag control information in the prepended frame descriptor.3. The method of claim 2 , further comprising placing the SecTag in a next six bytes following the SecTag.4. A method of enabling Pause in a frontside stacking environment claim 2 , comprising:identifying a size of a packet; andif the size of a packet is less than or equal to 64 bytes, examining the packet for a Pause frame format.5. A method of identifying OAM in a frontside stacking environment claim 2 , comprising:identifying a size of a packet; andif the size of a packet is less than or equal to 64 bytes, examining the packet for an OAM frame format.6. A method of enabling SPAN in a frontside stacking network claim 2 , comprising:receiving an incoming spanSessionMap from a frontside stack frame descriptor;generating a second spanSessionMap that encompasses a frontside stack port to a span session;logically OR'ing the incoming spanSessionMap with the second spanSessionMap to form a resultant spanSessionMap; andplacing the resultant spanSessionMap in the frontside stack frame descriptor.7. A method of operating a first switch and a second switch as respective active and standby switches connected by dual active detection (“DAD”) links claim 2 , ...

Providing State Storage in a Processor for System Management Mode

In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed. 1. A system comprising:a first processor including a first core to execute instructions and to enter a system management mode (SMM), a first indicator to indicate whether a thread executing on the first core is in a long flow operation, a second indicator to indicate whether the thread is in a system management interrupt (SMI)-inhibited state, and a storage unit, wherein upon entry to the SMM the first core is to store an active state present in a state storage of the first core into the storage unit and to store a SMM execution state into the state storage, the storage unit dedicated to storage of the active state during the SMM;a second processor including a second core to execute instructions and to enter the SMM, a first indicator to indicate whether a second thread executing on the second core is in a long flow operation, a second indicator to indicate whether the second thread is in the SMI-inhibited state, and a second storage unit, wherein upon entry to the SMM the second core is to store an active state present in a state storage of the second core into the second storage unit and to store a SMM execution state into the state storage, the second storage unit dedicated to storage of the active state during the SMM; anda dynamic random access ...

IC CARD AND IC CARD SYSTEM HAVING SUSPEND/RESUME FUNCTIONS

An IC card and an IC card system are disclosed in which command processing performance is improved by storing current state data related to a first command upon interruption of an execution cycle for the first command by a second command. Upon completion of the second command, the current state information is reloaded and execution of the first command is resumed. 1. A MultiMedia (MMC) card comprising:a flash memory for storing data related to a program command;a static random access memory (SRAM) configured to store flag values associated with an execution of the program command;an interface device configured to receive the program command, a first command and an interrupt command from a host device; anda controller configured to perform an execution of the program command in the flash memory, to halt the execution of the program command upon receiving the interrupt command, to store the flag values related to the execution of the program command at a predetermined memory location in the SRAM, to perform an execution of a first command in the flash memory upon receiving the first command, and to perform an execution of remaining portion of the program command upon again receiving the program command from the host device after completing the execution of the first command,wherein the first command has a higher priority that was determined by the host device than the program command.2. The MMC card of claim 1 , wherein the controller performs the execution of remaining portion of the program command based on the flag values.3. A storage medium comprising:at least one flash memory for storing data related to a program command;a volatile memory configured to store a state information associated with an execution of the program command; anda controller configured to perform an execution of the program command in the at least one flash memory, to halt the execution of the program command upon receiving an interrupt or a similar command from a host device, to store the ...

Power control method and electronic device supporting the same

A power control method of an electronic device is provided. The method includes receiving a power-on event in a power-off state of the electronic device and determining whether the received power-on event is a real time clock (RTC) interrupt. The method further includes determining, if the power-on event is the RTC interrupt, whether the power-off state is caused by an abnormal power-off, and performing, if the power-off state is caused by the abnormal power-off, a booting procedure.

Inter-Process Signaling Mechanism

The disclosed embodiments provide a mechanism to support implementation of semaphores or messaging signals between masters in a multi-master system, or between tasks in a single master system. A semaphore flag register contains one or more bits indicating whether resources are free or busy. The register is aliased to allow atomic read-and-clear of individual bits in the register. Masters poll the status of a resource until the resource reads as free. Alternatively, interrupts or events per master can be implemented to indicate availability of a resource. 1. A inter-process signaling system comprising:a plurality of masters;a plurality of resources shared by the plurality of masters; and a semaphore flag (SFLAG) register containing at least one bit per resource that indicates whether a resource is free or busy;', 'an SFLAG set (SFLAGSET) register for selectively setting individual bits in the SFLAG register; and', 'an SFLAG clear (SFLAGCLR) register for selectively clearing individual bits in the SFLAG register., 'an inter-process signal module coupled to the plurality of masters and the plurality of resources, the inter-process signal module including2. The system of claim 1 , wherein the bits in the SFLAG register are aliased to sequential memory locations claim 1 , so that the bits can be accessed individually by the SFLAGCLRR register.3. The system of claim 2 , wherein the SFLAGCLRR register provides atomic read-to-clear access.4. The system of claim 1 , further comprising:a plurality of semaphore mask (SMASK) registers, wherein each of the SMASK registers is associated with one of the plurality of masters and indicates which of the SFLAG register bits will produce an interrupt request for its associated master.5. The system of claim 4 , further comprising:an interrupt generator for generating an interrupt request based on contents of one of the SMASK registers and the SFLAG register.7. The system of claim 1 , further comprising:an event system coupled to the ...

USING TRANSACTIONAL EXECUTION FOR RELIABILITY AND RECOVERY OF TRANSIENT FAILURES

Autonomous recovery from a transient hardware failure by executing portions of a stream of program instructions as a transaction. A start of a transaction is created in a stream of executing program instructions. A snapshot of a system state information is saved when the transaction begins. When a predefined number of program instructions in the stream are executed, the transaction ends, and store data of the transaction is committed. A new transaction then begins. If a transient hardware failure occurs, the transaction is aborted without notifying the computer software application that initiated the stream of program instructions. The transaction is re-executed, based on the saved snapshot of the system state information. 1. A method for autonomous recovery from a transient hardware failure by executing each portion of a stream of program instructions as a transaction , the method comprising:while executing a stream of program instructions on a computer system configured to support transactional execution mode processing:creating a start of a transactional region portion of the stream of program instructions wherein the portion of the stream of program instructions in the transactional region is to be executed as a transaction in transactional execution mode; 'in response to executing a predefined number of program instructions in the transactional region portion stream of program instructions, creating, by the operating system, an end of the transactional region portion;', 'in response to starting the transactional region in transactional execution mode committing, by the operating system, store data of a transaction to memory;', 'creating a subsequent start of a transactional region portion of the stream of program instructions to be executed as a transaction in transactional execution mode;, 'in response to ending execution of the transactional region in transactional execution mode aborting, by the operating system, the transaction without notifying a computer ...

MEMORY SYSTEM WITH LATENCY DISTRIBUTION OPTIMIZATION AND AN OPERATING METHOD THEREOF

A memory system and an operating method thereof include: at least a CPU including multiple CPU cores, wherein the multiple CPU cores include reserved CPU cores and host CPU cores; at least a PCIe link coupled with the CPU, wherein the PCIe link includes at least a PCIe switch and a plurality of memory devices; and the plurality of memory devices coupled with the host CPU cores through respective workload threads and interrupt handlers, wherein the workload threads and interrupt handlers of each of the host CPU cores are configured to be optimized, the host CPU cores are isolated for the optimized workloads threads and interrupt handlers, and the workload threads and interrupt handlers are executed at the host CPU cores coupled thereto. 1at least a CPU including multiple CPU cores, wherein the multiple CPU cores include reserved CPU cores and host CPU cores;at least a PCIe link coupled with the CPU, wherein the PCIe link includes at least a PCIe switch and a plurality of memory devices; andthe plurality of memory devices coupled to the host CPU cores through respective workload threads and interrupt handlers, wherein the workload threads and interrupt handlers of each of the host CPU cores are configured to be optimized, the host CPU cores are isolated for the optimized workloads threads and interrupt handlers, and the workload threads and interrupt handlers are executed at the host CPU cores coupled thereto.. A memory system comprising: This application is a continuation of U.S. patent application Ser. No. 15/839,244 filed on Dec. 12, 2017, which claims benefits of priority of U.S. Provisional Patent Application No. 62/477,336 filed on Mar. 27, 2017. The disclosure of each of the foregoing application is incorporated herein by reference in its entirety.Exemplary embodiments of the present invention relate to an apparatus of semiconductor memory storage system, and more particularly to diagnose SSD and an operation method thereof.The computer environment paradigm has ...

MODULAR COMMUNICATION FRAMEWORK

Implementations generally relate to providing addressing in a modular system. In some implementations, a method includes detecting one or more modules connected to a bus, where the one or more modules are uninitialized. The method further includes associating the one or more modules with a status address on the bus. The method further includes polling for one or more interrupts on the status address. The method further includes assigning one or more respective dynamic addresses to the one or more modules based on the one or more interrupts. Implementations also generally relate to facilitating communication in a modular system. Implementations also generally relate to facilitating general communication in a modular system. 1. A method comprising:detecting one or more modules connected to a bus, wherein the one or more modules are uninitialized;associating the one or more modules with a status address on the bus;polling for one or more interrupts on the status address; andassigning one or more respective dynamic addresses to the one or more modules based on the one or more interrupts.2. The method of claim 1 , wherein the one or more modules are uninitialized if the one or more modules do not have dynamic addresses assigned to them.3. The method of claim 1 , wherein the status address is a globally shared address.4. The method of claim 1 , wherein the status address is a fixed address.5. The method of claim 1 , further comprising claim 1 , responsive to the polling claim 1 , receiving one or more polled interrupts from one or more of the respective modules.6. The method of claim 1 , further comprising claim 1 , responsive to the polling claim 1 , receiving one or more unique identifiers from the one or more respective modules.7. The method of claim 1 , wherein the one or more dynamic addresses are unique addresses.8. A non-transitory computer-readable storage medium carrying program instructions thereon claim 1 , the instructions when executed by one or more ...

DIRECTED INTERRUPT VIRTUALIZATION WITH FALLBACK

A processor receives an interrupt signal. The interrupt signal is received with an interrupt target ID identifying a target processor for handling the interrupt signal. The processor is a target of the interrupt signal directly. A check is made as to whether the processor is the target processor identified by the interrupt target ID. The checking includes performing a comparison of the interrupt target ID with a current interrupt target ID assigned to the processor. Based on the checking being successful, the interrupt signal is accepted for handling by the processor. 1. A computer program product for facilitating processing within a computing environment , the computer program product comprising: receiving, by a processor, an interrupt signal, the interrupt signal being received with an interrupt target ID identifying a target processor for handling the interrupt signal, the processor being a target of the interrupt signal directly;', 'checking whether the processor is the target processor identified by the interrupt target ID, the checking comprising performing a comparison of the interrupt target ID with a current interrupt target ID assigned to the processor; and', 'accepting, based on the checking being successful, the interrupt signal for handling by the processor., 'one or more computer readable storage media and program instructions collectively stored on the one or more computer readable storage media to perform a method comprising2. The computer program product of claim 1 , wherein the computing environment includes a plurality of processors assigned for usage by a guest operating system claim 1 , the plurality of processors including the processor receiving the interrupt signal claim 1 , and wherein the method further comprises broadcasting claim 1 , based on the checking being unsuccessful claim 1 , the interrupt signal to remaining processors of the plurality of processors for handling of the interrupt signal by the guest operating system.3. The ...

SYSTEM FOR LINK MANAGEMENT BETWEEN MULTIPLE COMMUNICATION CHIPS

Embodiments relate to an integrated circuit of an electronic device that coordinates activities with another integrated circuit of the electronic device. The integrated circuit includes an interface circuit and a processor circuit. The interface circuit communicates over a multi-drop bus connected to multiple electronic components. The processor circuit receives an authorization request from the integrated circuit via the interface circuit and the multi-drop bus. The received authorization request relates to authorization to perform an activity on the other integrated circuit. In response to receiving the authorization request, the processor circuit determines whether the other integrated circuit is authorized to execute the activity. In response to determining that the other integrated circuit is authorized to execute the activity, the processor circuit sends, to the other integrated circuit over a configurable direct connection, an authorization signal authorizing the other integrated circuit to execute the activity. 1. A first integrated circuit , comprising:an interface circuit configured to communicate with a second integrated circuit over a multi-drop bus in an electronic device; and receive an authorization request from a third integrated circuit over a configurable direct connection separate from the multi-drop bus, the authorization request associated with authorization to execute an activity at the third integrated circuit,', 'responsive at least in part to the received authorization request, determine whether the third integrated circuit is authorized to execute the activity, and', 'responsive to the determination, send a response signal to the third integrated circuit over the configurable direct connection., 'a processor circuit configured to2. The first integrated circuit of claim 1 , wherein the processor circuit is further configured to:perform, within a time limit, an internal arbitration to determine whether the third integrated circuit is ...

APPARATUS, METHOD, AND SYSTEM FOR EARLY DEEP SLEEP STATE EXIT OF A PROCESSING ELEMENT

An apparatus and method is described herein for providing an early wake scheme before spawning a new thread. An early wake indication may be provided an amount of time, which may include an amount of time to perform a demotion from a current power state to a lower power state that is closer to an active power state, before a new thread is to be spawned and executed on a processing element (e.g., core or thread). Upon encountering the spawn of the new thread, such as a helper thread, the processing element may further transition from the lower power state to an active power state. The new thread may be executed on the processing element without incurring the latency associated with execution of the new thread waiting for the demotion from the current power state to an active power state after the spawn of the new thread. 118.-. (canceled)19. A hardware processor comprising:a decoder to decode an instruction into a decoded instruction; and 'generate a wake indication for a second thread that is to be spawned from a first thread to cause a power control circuit to transition a processing element that is to execute the second thread from a first power state to a second power state within an amount of time to transition the processing element from the first power state to the second power state before the spawn, wherein the first power state and the second power state are lower power consumption states than an active power state.', 'an execution unit to execute the decoded instruction to20. The hardware processor of claim 19 , wherein the execution unit is to execute the decoded instruction to store the wake indication in a control register.21. The hardware processor of claim 19 , wherein the wake indication includes a processing element identifier to identify the processing element from a plurality of processing elements.22. The hardware processor of claim 19 , wherein the first thread is a main thread and the second thread is a helper thread to return data from the ...

INFORMATION-PROCESSING DEVICE, PROCESSING METHOD THEREOF, AND INPUT/OUTPUT DEVICE

An information processing device for reducing the number of times of interrupt notification for notifying completion of execution of input/output instruction and lightening a load of interrupt processing is described. The information processing device prescribes that a driver checks a completion state of a preceding input/output instruction after issuance of the input/output instruction. An issuing timing of the input/output instruction is considered to be a polling timing for checking the completion state of the preceding input/output instruction. Before the input/output device transmits interrupt notification to a CPU, the input/output device sets a timer to stand by for a prescribed time. A processing unit which resets the timer and extends the standby time by a prescribed time in a case where notification that a subsequent input/output instruction is issued arrives from a driver to the input/output device during the time is additionally provided to the input/output device. 1. An information processing device having a processor , a storage unit , and an input/output device which receives an instruction of processing from the processor ,wherein the information-processing device checks based on the instruction from the processor whether a preceding process is completed at the time of processing instruction from the processor, andwherein the input/output device includes:an interrupt notification transmission unit which transmits an interrupt signal as notification of processing completion to the processor;a standby unit which allows transmission of notification of the processing completion to the processor to be on standby for a certain time; andan extending unit which further extends the certain time when the transmission to the processor is allowed to be on standby in a chance of detecting a processing start instruction from the processor.2. The information-processing device according to claim 1 , wherein the processing start instruction from the processor is ...

AGGREGATION OF INTERRUPTS USING EVENT QUEUES

Embodiments of input/output hub unit are disclosed for aggregating interrupts received from multiple endpoint devices. The input/output hub may include an interface unit and one or more communication units. Each communication unit may be configured to receive messages from a corresponding endpoint device. The interface unit may be configured to update a first pointer within a first data structure responsive to a request from a given one of the communication units. The interface unit may be further configured to stored data in a second data structure responsive to updating the first pointer, reading a second pointer and the first pointer, and sending an interrupt responsive to a determination that the first and second pointers are equal. 1. An apparatus , comprising:a memory configured to store data associated with a plurality of queues;a plurality of root complexes, wherein each root complex of the plurality of root complexes is coupled to a respective plurality of endpoint devices; and receive a plurality of requests from the plurality of root complexes, wherein at least one request of the plurality of requests is made in response to an event associated with a particular endpoint device;', 'select a particular request of the plurality of events using an arbitration algorithm;', 'store information associated with the particular request in a first queue of the plurality of queues., 'an interface unit configured to2. The apparatus of claim 1 , wherein the interface unit is further configured to select first queue of the plurality of queues using a map.3. The apparatus of claim 2 , wherein the particular request includes a request address claim 2 , and wherein the interface unit is further configured to translate the request address to a physical address.4. The apparatus of claim 1 , wherein the particular request is associated with an Input/Output (I/O) interrupt associated with the particular endpoint device.5. The apparatus of claim 1 , wherein the arbitration ...

VIRTUAL INTERRUPT FILTER

A system for processing interrupts in a virtualized computing environment includes a virtual interrupt controller to provide virtual interrupts from peripherals to virtual machines. The system also includes a virtual interrupt filter that has an estimator circuit to provide an estimate of what proportion of interrupts from one or more of the peripherals are virtual interrupts. A determination is made as to whether the estimate satisfies a criterion; if it does, incoming interrupts are blocked. 1. A system for processing interrupts in a virtualized computing environment , the system comprising:a virtual interrupt filter comprising an estimator circuit to provide an estimate of what proportion of interrupts from one or more peripherals are virtual interrupts.2. The system of claim 1 , wherein the system further comprises a virtual interrupt controller to provide the virtual interrupts from peripherals to virtual machines.3. The system of claim 2 , wherein the virtual interrupt filter further comprises:a comparator to determine whether the estimate satisfies a criterion with respect to a threshold value and to assert an alert signal in response to determining that the estimate satisfies the criterion.4. The system of claim 3 , wherein the alert signal comprises an interrupt.5. The system of claim 3 , further comprising a memory-based log to which to divert virtual interrupts in response to assertion of the alert signal.6. The system of claim 3 , wherein virtual interrupts are to be blocked in response to assertion of the alert signal claim 3 , the system further comprising a memory-based scorecard to track vector numbers of blocked virtual interrupts.7. The system of claim 3 , further comprising a first-in-first-out (FIFO) buffer to sample a specified number of interrupts that precede assertion of the alert signal.8. The system of claim 2 , wherein the estimator circuit comprises an adaptive adder circuit claim 2 , the adaptive adder circuit comprising:a signal input ...

MICROCOMPUTER

To detect an abnormality in an interrupt control system without completely depending on dualization of a circuit, without the need to create a test pattern for a built-in self-test by spending time, and without considerably increasing an amount of power consumption. A test interrupt request is generated periodically using a timer or the like in an interrupt signal system from an interrupt controller to a central processing unit, the state of an interrupt request flag within the interrupt controller is checked in an interrupt processing routine, and in the case where it is detected that the same interrupt request flag is kept in a set state twice or more in succession, it is supposed that there is a high possibility that a failure has occurred in the interrupt signal system and it is considered that there is an abnormality. 1. A microcomputer comprising:a central processing unit; andan interrupt controller,wherein the central processing unit considers that there is an abnormality by referring to an interrupt request flag held by the interrupt controller in response to a predetermined test interrupt request generated periodically at predetermined intervals and by determining that the same interrupt request flag is in a set state a plurality of times in succession by the reference made by a plurality of the test interrupt requests.2. The microcomputer according to claim 1 ,wherein the interrupt controller includes a first interrupt controller to which the test interrupt request is given and a second interrupt controller having an interrupt request flag to be referred to by processing of the central processing unit in response to the test interrupt request.3. The microcomputer according to claim 2 ,wherein a test interrupt request generation circuit configured to generate the test interrupt request is dualized, andwherein the first interrupt controller further has a determination circuit configured to individually perform reception control of each of test interrupt ...

CONTROLLING OPERATIONS ACCORDING TO ANOTHER SYSTEM'S ARCHITECTURE

An I/O device operating according to a native computer architecture is accessed by a primary computer system operating according to a primary computer architecture. An application program of the primary computer system requests an I/O operation to access the I/O device. To facilitate this access, an application program interface formed of primary instructions for execution by the primary processor processes the I/O operation to provide an I/O request and to receive an interrupt in response to completion of the access. A thread is formed of primary instructions for execution by the primary processor for receiving the interrupt from the application program interface. A subsystem operates in response to the I/O request to access the I/O device and to provide the interrupt. 1. A computer program product for facilitating access to input/output (I/O) devices of a computing environment , the computer program product comprising: processing, by an application program interface executing on a processor of a first computer system operating according to a first system architecture, an I/O operation requested by an application of the first computer system to access an I/O device operating according to a second system architecture, the second system architecture different from the first system architecture, wherein the first system architecture has a first machine instruction set different from a second machine instruction set of the second system architecture, said processing providing an I/O request, and wherein the application program interface executing on the processor of the first computer system operating according to the first system architecture includes one or more library functions to implement functionality of one or more I/O instructions of the second system architecture to provide access to the I/O device; and', 'obtaining, by the application program interface, an interrupt for the I/O device accessed based on the I/O request, the interrupt to indicate completion of ...

MANAGING OVER-INITIATIVE THIN INTERRUPTS

A method, system, and computer program product identify extraneous input/output interrupts for a queued input/output device architecture. At least one interrupt is determined to have been generated for at least one queue in a plurality of queues of a queued input/output device architecture. The interrupt is identified as an extraneous interrupt in response to the determining one of that the queue is associated with at least one reply message waiting to be dequeued for a previously processed interrupt, and that the queue fails to include at least one pending reply for a previously received unprocessed interrupt. 1. A method for identifying extraneous input/output interrupts for a queued input/output device architecture , the method comprising:determining, with a processor, that at least one interrupt has been generated for at least one queue in a plurality of queues of a queued input/output device architecture;determining a queue state associated with the queue; andidentifying that the at least one interrupt is an extraneous interrupt based on the queue state associated with the queue.2. The method of claim 1 , wherein the identifying comprises at least one of:determining that the queue state indicates that one of that the queue is associated with at least one reply message waiting to be dequeued for a previously processed interrupt; anddetermining that the queue state indicates that the queue fails to comprise at least one pending reply message for a previously received non-processed interrupt.3. The method of claim 1 , further comprising:setting a global lock for the at least one interrupt, wherein the global lock prevents interrupt handlers other than an interrupt handler associated with the at least one interrupt from processing the interrupt.4. The method of claim 1 , further comprising:updating an extraneous interrupt counter in response to identifying the at least one interrupt as being an extraneous interrupt.5. The method of claim 4 , further comprising: ...

METHOD AND APPARATUS FOR DETECTING AND RESOLVING BUS HANG IN A BUS CONTROLLED BY AN INTERFACE CLOCK

Systems and methods are disclosed for resolving bus hang in a computing device. An exemplary system comprises a bus operating in accordance with an interface clock, and a controller in communication with the bus. The controller comprises a finite state machine, where the finite state machine is configured to receive a clock signal from the interface clock and a command signal originating external to the controller. The controller also comprising hang detection logic configured to receive one or more signals that the finite state machine is active, monitor the interface clock, and generate an event notification in response to the interface clock turning off while the finite state machine is active. The controller further comprises a trap handler in communication with the hang detection logic, the trap handler configured to send an interrupt in response to the event notification. 1. A computer system for resolving bus hang in a computing device , the system comprising:a bus of the computing device, the bus operating in accordance with an interface clock; and a finite state machine in communication with the bus, the finite state machine configured to receive a clock signal from the interface clock and a command signal originating external to the controller,', receive one or more signals that the finite state machine is active, monitor the interface clock, and', 'generate an event notification in response to the interface clock turning off while the finite state machine is active, and, 'hang detection logic, the hang detection logic configured to, 'a trap handler in communication with the hang detection logic, the trap handler configured to send an interrupt in response to the event notification., 'a controller in communication with the bus, the controller comprising2. The system of claim 1 , wherein the event notification comprises a trap signal.3. The system of claim 1 , wherein the controller further comprises a debug register in communication with the trap handler ...

ELECTRONIC DEVICE SUPPORTING USB INTERFACE AND CONTROL METHOD FOR USB INTERFACE

An electronic device includes a housing, a display device exposed through a first part of the housing, a recess formed in a second part of the housing, a receptacle formed in the recess, a plurality of conductive contacts disposed inside the receptacle and including a first contact, a first circuit that supplies and/or receives a current of a first level or larger to and/or from the first contact when an external connector is inserted into the receptacle, a first switching device that electrically connects the first circuit with the first contact or to interrupt a connection between the first circuit and the first contact, a second circuit that detects existence of a foreign object contacting the first contact while the external connector is inserted into the receptacle and a control circuit that controls the first switching device based at least in part on information regarding the detected existence of the foreign object. 1. An electronic device comprising:a housing:a display device exposed through a first part of the housing;a recess formed in a second part of the housing;a receptacle formed in the recess;a plurality of conductive contacts disposed inside the receptacle and including a first contact;a first circuit configured to supply and/or receive a current of a first level or larger to and/or from the first contact when an external connector is inserted into the receptacle;a first switching device comprising switching circuitry configured to electrically connect the first circuit with the first contact or to interrupt an electrical connection between the first circuit and the first contact;a second circuit configured to detect existence of a foreign object contacting the first contact while the external connector is inserted into the receptacle; anda control circuit configured to control the first switching device based at least in part on information regarding the detected existence of the foreign object.2. The electronic device of claim 1 , wherein the ...