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15-08-2017 дата публикации

Генератор псевдослучайных чисел с нелинейной обратной связью

Номер: RU0000173172U1
Автор: Вера Николаевна Бубенко, Виталий Владимирович Новицкий, Дмитрий Николаевич Полюков
Принадлежит: Открытое Акционерное Общество "Пеленг"

Полезная модель относится к вычислительной технике и может быть использована в средствах обработки и защиты информации.Предложен генератор псевдослучайных чисел с нелинейной обратной связью, включающий блок управляющего сигнала, генератор тактовых импульсов, регистр сдвига, выполненный в виде серии N «m-разрядных» запоминающих регистров и блоки стохастического преобразования. Новым является то, что для формирования нелинейной обратной связи достаточно два блока стохастического преобразования, и генератор дополнительно содержит блок квазислучайной коммутации, включающий N/2 каналов логического суммирования, каждый из которых реализует одну аффинную булевую функцию. Генератор псевдослучайных чисел с нелинейной обратной связью характеризуется низкой ресурсоемкостью и позволяет генерировать гаммы, свойства которых соответствуют истинно случайному процессу с максимальным значением энтропии. 1 ил. 173172 Ц 1 ко РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ < 3х ©“ х & < < (13) Зе УЛ х& ма, эхо п РЦ ‘’ (50) МПК СОбЕ 7/58 (2006.01) (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (21)(22) Заявка: 2017101498, 17.01.2017 (24) Дата начала отсчета срока действия патента: 17.01.2017 Дата регистрации: 15.08.2017 Приоритет(ы): (30) Конвенционный приоритет: 01.02.2016 ВУ ч20160028 (45) Опубликовано: 15.08.2017 Бюл. № 23 Адрес для переписки: 220114, Респ. Беларусь, г. Минск, ул. Макаенка, 25, ОАО "Пеленг" (72) Автор(ы): Бубенко Вера Николаевна (ВУ), Полюков Дмитрий Николаевич (ВУ), Новицкий Виталий Владимирович (ВУ) (73) Патентообладатель(и): Открытое акционерное общество "Пеленг" (ВУ) (56) Список документов, цитированных в отчете о поиске: КО 2080651 С1, 27.05.1997. ЗО 1387177 А1, 07.04.1988. 5Ц 1347167 АТ, 23.10.1987. 0$ 8831216 В2, 09.09.2014. РН 11224183 А, 17.08.1999. РН 09325881 А, 16.12.1997. (54) ГЕНЕРАТОР ПСЕВДОСЛУЧАЙНЫХ ЧИСЕЛ С НЕЛИНЕЙНОЙ ОБРАТНОЙ СВЯЗЬЮ (57) Реферат: Полезная модель относится к вычислительной технике и может быть использована в ...

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Номер записи: 1
22-03-2012 дата публикации

System for establishing a cryptographic key depending on a physical system

Номер: US20120072737A1
Автор: Geert Jan Schrijen, Helena Handschuh, Pim Theo Tuyls
Принадлежит: Intrinsic ID BV

In systems for establishing a cryptographic key depending on a physical uncloneable function (PUF) it may be a problem that internal information correlated with the cryptographic key is leaked to the outside of the system via a side-channel. To mitigate this problem a cryptographic system for reproducibly establishing a cryptographic key is presented. The system comprises a physical system comprising a physical, at least partially random, configuration of components from which an initial bit-string is derived. An error corrector corrects deviations occurring in the initial bit-string. Through the use of randomization the error corrector operates on a randomized data. Information leaking through a side channel is thereby reduced. After error correction a cryptographic key may be derived from the initial bit-string.

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Номер записи: 2
05-04-2012 дата публикации

Efficient Parallel Floating Point Exception Handling In A Processor

Номер: US20120084533A1
Автор: Arnit Gradstein, Gregory Pribush, Guy Bale, Shachar Finkelstein, Thierry Pons, Zeev Sperber
Принадлежит: Individual

Methods and apparatus are disclosed for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one embodiment a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two packed partial results of a packed result for the SIMD floating point operation. A SIMD denormalization micro-operation is initiated to combine the two packed partial results and to denormalize one or more elements of the combined packed partial results to generate a packed result for the SIMD floating point operation having one or more denormal elements. Flags are set and stored with packed partial results to identify denormal elements. In one embodiment a SIMD normalization micro-operation is initiated to generate a normalized pseudo internal floating point representation prior to the SIMD floating point operation when it uses multiplication.

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Номер записи: 3
12-04-2012 дата публикации

Modulo operation method and apparatus for same

Номер: US20120089658A1
Автор: Dong Min Kim, In Tae Kang, Jung Uk Woo, Yun Ju Kwon
Принадлежит: SAMSUNG ELECTRONICS CO LTD

The present invention provides a modulo operation method. The modulo operation method, in a case where the square of a divisor N is greater than or equal to a dividend C, includes: determining the number of computation stages n satisfying 2 n <N≦2 n+1 ; performing an initialization operation by initializing a constant a to the smallest integer greater than or equal to half of N; performing a first operation by subtracting, when C is greater than or equal to N·a (product of N and a), the value of C by the value of N·a; and performing a second operation by assigning the smallest integer greater than or equal to half of a to the value of a, wherein the value of C is output as the result of modulo operation after the first operation and the second operation are repeated n times. In the first operation, when C is less than N·a, the value of C is unchanged. In the modulo operation method and apparatus of the present invention, the amount of computation in a modulo operation or division operation does not increase in linear proportion to the magnitude of the divisor N but increases in proportion to log N. As a result, the total amount of computation decreases and computation speed increases.

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Номер записи: 4
19-04-2012 дата публикации

Architecture guided optimal system precision definition algorithm for custom integrated circuit

Номер: US20120095583A1
Автор: Anand Pandurangan, Pius Ng, Satish Padmanabhan, Siva Selvaraj
Принадлежит: Individual

Systems and methods are disclosed to automatically determine an optimal number format representation for a model or code to be implemented in a custom integrated circuit (IC) by determining a ratio of dynamic range to static range in the model or code, and selecting a floating point or a fixed point number representation based on the ratio; determining the optimal number representation format based on a cost function that includes hardware area and power cost associated with a predetermined bit precision arithmetic; automatically generating a processor architecture customized to the optimal number representation format; and synthesizing the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

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Номер записи: 5
03-05-2012 дата публикации

Implementing physically unclonable function (puf) utilizing edram memory cell capacitance variation

Номер: US20120106235A1
Автор: II John Edwards Sheets, Todd Alan Christensen
Принадлежит: International Business Machines Corp

A method and embedded dynamic random access memory (EDRAM) circuit for implementing a physically unclonable function (PUF), and a design structure on which the subject circuit resides are provided. An embedded dynamic random access memory (EDRAM) circuit includes a first EDRAM memory cell including a memory cell true storage capacitor and a second EDRAM memory cell including a memory cell complement storage capacitor. The memory cell true storage capacitor and the memory cell complement storage capacitor include, for example, trench capacitors or metal insulator metal capacitors (MIM caps). A random variation of memory cell capacitance is used to implement the physically unclonable function. Each memory cell is connected to differential inputs to a sense amplifier. The first and second EDRAM memory cells are written to zero and then the first and second EDRAM memory cells are differentially sensed and the difference is amplified to consistently read the same random data.

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Номер записи: 6
24-05-2012 дата публикации

Computation of a remainder by division using pseudo-remainders

Номер: US20120131082A1
Автор: Michael Hirsch, Shmuel T. Klein, Yair Toaff
Принадлежит: International Business Machines Corp

Methods, computer systems, and computer program products for calculating a remainder by division of a sequence of bytes interpreted as a first number by a second number is provided. A pseudo-remainder by division associated with a first subsequence of the sequence of bytes is calculated. A property of this pseudo-remainder is that the first subsequence of the sequence of bytes, interpreted as a third number, and the pseudo-remainder by division have the same remainder by division when divided by the second number. A second subsequence of the sequence of bytes interpreted as the first number is appended to the pseudo-remainder, interpreted as a sequence of bytes, so as to create a sequence of bytes interpreted as a fourth number. The first number and the fourth number have the same remainder by division when divided by the second number.

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Номер записи: 7
28-06-2012 дата публикации

Performing Reciprocal Instructions With High Accuracy

Номер: US20120166509A1
Автор: Amit Gradstein, Benny Eitan, Cristina S. Anderson, Simon Rubanovich, Zeev Sperber
Принадлежит: Intel Corp

In one embodiment, the present invention includes a method for receiving a reciprocal instruction and an operand in a processor, accessing an entry of a lookup table based on a portion of the operand and the instruction, generating an encoder output based on a type of the reciprocal instruction and whether the reciprocal instruction is a legacy instruction, and selecting portions of the lookup table entry and input operand to be provided to a reciprocal logic unit based on the encoder output. Other embodiments are described and claimed.

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Номер записи: 8
19-07-2012 дата публикации

Generating a Number based on Mask and Range Constraints

Номер: US20120185522A1
Автор: Ehud Aharoni, Oded Margalit
Принадлежит: International Business Machines Corp

Generating a number based on mask and range constraints. For example, a method of generating a pseudo random number satisfying a range constraint and a mask constraint may include determining a number of possible solutions satisfying the range constraint and the mask constraint; selecting an index representing a solution of the possible solutions; and generating the pseudo random number based on the index. Other embodiments are described and claimed.

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Номер записи: 9
09-08-2012 дата публикации

Embedded opcode within an intermediate value passed between instructions

Номер: US20120204006A1
Автор: Jorn Nystad
Принадлежит: ARM LTD

A data processing system 2 is used to evaluate a data processing function by executing a sequence of program instructions including an intermediate value generating instruction Inst 0 and an intermediate value consuming instruction Inst 1 . In dependence upon one or more input operands to the evaluation, an embedded opcode within the intermediate value passed between the intermediate value generating instruction and the intermediate value consuming instruction may be set to have a value indicating that a substitute instruction should be used in place of the intermediate value consuming instruction. The instructions may be floating point instructions, such as a floating point power instruction evaluating the data processing function a b .

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Номер записи: 10
06-09-2012 дата публикации

System and Method for Testing Whether a Result is Correctly Rounded

Номер: US20120226730A1
Автор: Alexandru Fit-Florea
Принадлежит: Nvidia Corp

A computer-implemented method for executing a floating-point calculation where an exact value of an associated result cannot be expressed as a floating-point value is disclosed. The method involves: generating an estimate of the associated result and storing the estimate in memory; calculating an amount of error for the estimate; determining whether the amount of error is less than or equal to a threshold of error for the associated result; and if the amount of error is less than or equal to the threshold of error, then concluding that the estimate of the associated result is a correctly rounded result of the floating-point calculation; or if the amount of error is greater than the threshold of error, then testing whether the floating-point calculation constitutes an exception case.

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Номер записи: 11
13-09-2012 дата публикации

Apparatus for generating random number

Номер: US20120233231A1
Автор: IHOR VASYLTSOV, KARPINSKYY Bohdan
Принадлежит: SAMSUNG ELECTRONICS CO LTD

An apparatus configured to generate random numbers is provided, the apparatus having high entropy and being capable of a reduced chip size. The apparatus includes a plurality of metastable state generation units configured to generate a metastable state signal, a plurality of amplification units configured to amplify the metastable state signal, a connection signal generation unit configured to generate a first connection signal, and a first commutation unit configured to connect at least one metastable state generation unit to at least one amplification unit according to the first connection signal. For example, the number of metastable state generation units and amplification units necessary to achieve are threshold number of commutation connections can be greatly reduced as compared to conventional apparatuses for generating random numbers.

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Номер записи: 12
13-09-2012 дата публикации

System and method of bypassing unrounded results in a multiply-add pipeline unit

Номер: US20120233234A1
Автор: Christopher H. Olson, Jeffrey S. Brooks
Принадлежит: Oracle International Corp

A processing unit, system, and method for performing a multiply operation in a multiply-add pipeline. To reduce the pipeline latency, the unrounded result of a multiply-add operation is bypassed to the inputs of the multiply-add pipeline for use in a subsequent operation. If it is determined that rounding is required for the prior operation, then the rounding will occur during the subsequent operation. During the subsequent operation, a Booth encoder not utilized by the multiply operation will output a rounding correction factor as a selection input to a Booth multiplexer not utilized by the multiply operation. When the Booth multiplexer receives the rounding correction factor, the Booth multiplexer will output a rounding correction value to a carry save adder (CSA) tree, and the CSA tree will generate the correct sum from the rounding correction value and the other partial products.

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Номер записи: 13
11-10-2012 дата публикации

Pipelined divide circuit for small operand sizes

Номер: US20120259907A1
Автор: Christopher H. Olson, Jeffrey S. Brooks
Принадлежит: Oracle International Corp

A pipelined circuit for performing a divide operation on small operand sizes. The circuit includes a plurality of stages connected together in a series to perform a subtractive divide algorithm based on iterative subtractions and shifts. Each stage computes two quotient bits and outputs a partial remainder value to the next stage in the series. The first and last stages utilize a radix-4 serial architecture with edge modifications to increase efficiency. The intermediate stages utilize a radix-4 parallel architecture. The divide architecture is pipelined such that input operands can be applied to the divider on each clock cycle.

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Номер записи: 14
11-10-2012 дата публикации

Fast carry lookahead circuits

Номер: US20120259908A1
Автор: Jonathan Greene, Marcel Derevlean, Volker Hecht
Принадлежит: Individual

A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path.

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Номер записи: 15
18-10-2012 дата публикации

Montgomery multiplication circuit

Номер: US20120265794A1
Автор: Michael NIEL
Принадлежит: Inside Secure SA

A circuit for calculating a sum of products, each product having a q-bit binary operand and a k-bit binary operand, where k is a multiple of q,includes a q-input carry-save adder (CSA); a multiplexer ( 10 ) by input of the adder, having four k-bit channels respectively receiving the value 0, a first (Yi) of the k-bit operands, the second k-bit operand (M [63:0] , m i ), and the sum of the two k-bit operands, the output of a multiplexer of rank t (where t is between 0 and q−1) being taken into account by the adder with a t-bit left shift; and each multiplexer having first and second path selection inputs, the bits of a first of the q-bit operands being respectively supplied to the first selection inputs, and the bits of the second q-bit operand being respectively supplied to the second selection inputs.

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Номер записи: 16
22-11-2012 дата публикации

Bit sequence generation apparatus and bit sequence generation method

Номер: US20120293354A1
Автор: Daisuke Suzuki
Принадлежит: Mitsubishi Electric Corp

A bit sequence generation apparatus includes a glitch generating circuit that generates a glitch, a sampling circuit that samples the glitch waveform generated by the glitch generating circuit, and a glitch shape determination circuit that generates 1-bit data indicating either 1 or 0, based on the glitch waveform sampled by the sampling circuit, and generates a bit sequence composed of a plurality of generated 1-bit data. The bit sequence generation apparatus can provide a PUF circuit that is able to generate highly randomized secret information even in a device with a low degree of freedom of alignment and wiring and that does not violate the design rules.

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Номер записи: 17
27-12-2012 дата публикации

Systems and methods for large-scale randomized optimization for problems with decomposable loss functions

Номер: US20120330867A1
Автор: John Sismanis, Peter Jay Haas, Rainer Gemulla
Принадлежит: International Business Machines Corp

Systems and methods directed toward processing optimization problems using loss functions, wherein a loss function is decomposed into at least one stratum loss function, a loss is decreased for each stratum loss function to a predefined stratum loss threshold individually using gradient descent, and the overall loss is decreased to a predefined threshold for the loss function by appropriately ordering the processing of the strata and spending appropriate processing time in each stratum. Other embodiments and aspects are also described herein.

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Номер записи: 18
03-01-2013 дата публикации

Methods and apparatus for compressing partial products during a fused multiply-and-accumulate (fmac) operation on operands having a packed-single-precision format

Номер: US20130007075A1
Автор: David Oliver, Debjit Dassarma, Hanbing Liu, Scott Hilker
Принадлежит: Advanced Micro Devices Inc

The disclosed embodiments relate to methods and apparatus for accurately, efficiently and quickly executing a fused multiply-and-accumulate instruction with respect to floating-point operands that have packed-single-precision format. The disclosed embodiments can speed up computation of a high-part of a result during a fused multiply-and-accumulate operation so that cycle delay can be reduced and so that power consumption can be reduced.

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Номер записи: 19
24-01-2013 дата публикации

Method for fast calculation of the beginning of pseudo random sequences for long term evolution

Номер: US20130024489A1
Автор: Assaf Prihed, Ido Gazit, Shai Kalfon, Sharon Rosenschein
Принадлежит: LSI Corp

An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate pseudo-random sequences in response to a first m-sequence and a second m-sequence, where the first m-sequence is initialized with a pre-calculated constant and the second m-sequence is initialized based on a pre-defined initial sequence and a table of pre-calculated values indicating which components of the initial sequence participate in initializing the second m-sequence. The second circuit may be configured to store the table of pre-calculated values.

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Номер записи: 20
18-04-2013 дата публикации

BINARY HALF-ADDER USING OSCILLATORS

Номер: US20130093458A1
Автор: Borresen Jon, Lynch Stephen
Принадлежит: MANCHESTER METROPOLITAN UNIVERSITY

A binary half-adder comprising first and second oscillators, each oscillator being connected to a first input and to a second input, the second oscillator being connected to the first oscillator, wherein the first oscillator is configured to oscillate if the first input is high or the second input is high, the second oscillator is configured to oscillate if the first and the second inputs are high, and wherein the connection between the second oscillator and the first oscillator is configured to suppress oscillation of the first oscillator if the second oscillator is oscillating. 11f. A binary half-adder comprising first and second oscillators , each oscillator being connected to a first input and to a second input , the second oscillator being connected to the first oscillator , wherein the first oscillator is configured to oscillate if the first input is high or the second input is high , the second oscillator is configured to oscillate if the first and the second inputs are high , and wherein the connection between the second oscillator and the first oscillator is configured to suppress oscillation of the first oscillator the second oscillator is oscillating.2. The binary half-adder of claim 1 , wherein each oscillator is configured to tend towards a stable non-oscillating state in the absence of an external input claim 1 , and is configured to oscillate at a limit-cycle in the presence of an external input which is above a threshold.3. The binary half-adder of claim 2 , wherein at least one of the oscillators is configured to tend towards a stable non-oscillating state if the external input exceeds an upper threshold.4. The binary half-adder of any of claim 1 , wherein the first oscillator and the second oscillator are electrical circuits.5. The binary half adder of claim 4 , wherein the first oscillator and the second oscillator comprise a plurality of FETs.6. The binary half-adder of claim 4 , wherein the first oscillator and the second oscillator are Fitzhugh ...

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Номер записи: 21
18-04-2013 дата публикации

PROCESSOR AND OPERATING METHOD

Номер: US20130097214A1
Автор: Seki Katsutoshi
Принадлежит: NEC Corporation

Disclosed is a processor that is able to efficiently execute DFT operations without having part of a basic operational circuit idle even during non-DFT-operation processing. The processor () has an operational means (operation unit) () and a control means (control unit) (). The operation means () has a plurality of shift addition-and-subtraction means connected such that CORDIC (COordinate Rotation DIgital Computer) operations can be executed. The shift adding-and-subtracting means also execute shift addition-and-subtraction processing of butterfly operations that process shift addition-and-subtraction for one stage or more. The control means () instructs the operation means () to execute either CORDIC operations or butterfly operations, based on a plurality of data received from the outside. 1. A processor , comprising:an operational circuit including a plurality of shift addition-and-subtraction unit which are connected each other so as to be able to carry out CORDIC (COordinate Rotation DIgital Computer) operation and each of which carries out a shift addition-and-subtraction process in butterfly operation including the shift addition-and-subtraction process composed of one or more one stages; anda control circuit which instructs the operation circuit to carry out the CORDIC operation or the butterfly operation based on data received from an outside.2. The processor according to claim 1 , whereinin case that the control circuit instructs the operation circuit to carry out the butterfly operation, the control circuit provides the operation circuit with information which indicates a radix of the butterfly operation, andthe operation circuit further includes shift addition-and-subtraction control unit which provides the shift addition-and-subtraction unit with information which controls a combination of data, to which an addition-and-subtraction is carried out in the shift addition-and-subtraction process, based on the information indicating the radix.3. The ...

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Номер записи: 22
25-04-2013 дата публикации

SYSTEM AND METHOD FOR REDUCING RECONFIGURATION POWER USAGE

Номер: US20130099821A1
Автор: Hu Jingcao, Huang Randy R., Teig Steven, Voogel Martin
Принадлежит: TABULA, INC.

A system and method for reducing power consumption in a reconfigurable integrated circuit. Some embodiments provide placement and routing programs that reduce the number of bits to be reconfigured. Some embodiments provide placement and routing programs that increase the number of groups of circuits that do not need reconfiguration at some times. Some embodiments include circuits that selectively block reconfiguration. 163-. (canceled)64. An integrated circuit (“IC”) comprising:a group of reconfigurable circuits, each of the reconfigurable circuits for configurably performing a plurality of different operations in different reconfiguration cycles based on stored configuration data;a select driver for selecting different sets of stored configuration data in different reconfiguration cycles for the group of reconfigurable circuits, wherein the select driver comprises a clock input for receiving a clock signal, wherein the select driver selects a different set of stored configuration data in each reconfiguration cycle in which the select driver receives the clock signal; anda gating circuit for selectively blocking the signal from reaching the clock input in a set of reconfiguration cycles controlled by configuration data of the gating circuit.65. The IC of further comprising a plurality of multiplexers (MUXs) for selectively providing the different sets of configuration data to the reconfigurable circuits.66. The IC of claim 65 , wherein at least one of the plurality of MUXs comprises a set of inputs that determine which of a plurality of stored configuration data values will be provided to the reconfigurable circuit.67. The IC of claim 66 , wherein the set of inputs are communicatively coupled to the select driver.68. The IC of claim 65 , wherein the MUXs are one-hot select MUXs.69. The IC of claim 65 , wherein the select driver selects different sets of stored configuration data by activating a selected set of inputs of the MUXs claim 65 , wherein the inputs are ...

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Номер записи: 23
02-05-2013 дата публикации

Implementing screening for single fet compare of physically unclonable function (puf)

Номер: US20130106461A1
Автор: Grant P. Kesselring, James D. Strom, Joel T. Ficke
Принадлежит: International Business Machines Corp

A screening method and circuit for implementing a Physically Unclonable Function (PUF), and a design structure on which the subject circuit resides are provided. A plurality of field effect transistors (FETs) is coupled to a low-offset dynamic comparator and is respectively selected to provide a plurality of FET pairs. For each FET pair, a voltage offset to obtain a comparator output transition is identified and recorded. The recorded voltage offset for each FET pair is compared with a margin threshold value. Each FET pair having an identified voltage offset less than the margin threshold value is discarded or disabled for PUF response generation use.

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Номер записи: 24
02-05-2013 дата публикации

SYSTEMS AND METHODS EMPLOYING UNIQUE DEVICE FOR GENERATING RANDOM SIGNALS AND METERING AND ADDRESSING, E.G., UNUSUAL DEVIATIONS IN SAID RANDOM SIGNALS

Номер: US20130110895A1
Автор: Mertz Herb, Valentino John
Принадлежит: PSYLERON, INC.

According to some embodiments, a system comprises a generator of a truly random signal is connected to an input and feedback device for the purpose of providing a user with real time feedback on the random signal. The user observes a representation of the signal in the process of an external physical event for the purpose of finding a correlation between the random output and what happens during the physical event. In some examples, the system is preferably designed such the system is shielded from all classically known forces such as gravity, physical pressure, motion, electromagnetic fields, humidity, etc. and/or, such classical forces are factored out of the process as much as possible. The system is thus designed to be selectively response to signals from living creatures, in particular, humans. 1. A method of monitoring a series of true random numbers , said method composing:using a hardware device to produce an analog noise signal, to converting said analog noise signal to a true random sequence of signals, and to carry out monitoring of said true random sequence of signals for anomalies along with evaluation of said anomalies in relation to one or more time-based events or occurrences.2. The method of claim 1 , further comprising the step of monitoring said sequence of signals for deviations from true random sequences claim 1 , and for the time period of said deviations claim 1 , comparing said time period of said deviations with events during said time periods.3. The method of claim 2 , further comprising the step of correlating said deviations with interpersonal happenings.4. The method of claim 2 , further comprising the step of correlating said deviations with interpersonal happenings in real time.5. The method of claim 2 , where the output of the device is used to make business decisions.6. The method of claim 2 , where the output of the device is used to help gauge the performance of individuals.7. The method of claim 2 , where the output of the device ...

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Номер записи: 25
23-05-2013 дата публикации

Dynamic Prediction of Downhole Temperature Distributions

Номер: US20130132050A1
Автор: Bolchover Paul, Parry Andrew J., Zielinska Barbara J. A.
Принадлежит: SCHLUMBERGER TECHNOLOGY CORPORATION

Downhole temperature distributions of aspects of a drilling scenario are predicted using computer-implemented methods. The temperature distributions are predicted based on models defined as functions of sets of parameters associated with the drilling environment. Numerical solution methods are utilized to predict downhole temperature distributions, accounting for translation of the drill string. 1. A method of predicting a temperature distribution for a downhole fluid during a drilling scenario , the method comprising:defining a first model for predicting a first temperature distribution associated with a volume of a simulated downhole fluid as a function of a first set of parameters;defining a second model for predicting a temperature distribution of a simulated formation as a function of a second set of parameters;defining a drilling scenario that simulates an operation in which a depth of a downhole end of a simulated drill string changes as the drilling scenario progresses; anddetermining a first set of predicted temperature distributions predicted based on the first model and the second model, the first set of predicted temperature distributions representing temperature distributions of the volume of the simulated downhole fluid as the drilling scenario progresses.2. The method of claim 1 , further comprising:identifying a calculation domain associated with the drilling scenario; andpartitioning the calculation domain into a plurality of sub-domains, the plurality of sub-domains comprising a first downhole-fluid sub-domain, a drill-string sub-domain, a second downhole-fluid sub-domain, and a formation sub-domain.3. The method of claim 2 , wherein determining the first set of predicted temperature distributions includes applying a numerical solution method with respect to the first downhole-fluid sub-domain claim 2 , the numerical solution method comprising:defining a mesh corresponding to the first downhole-fluid sub-domain, the mesh having a plurality of mesh ...

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Номер записи: 26
23-05-2013 дата публикации

GENERATING UNIQUE RANDOM NUMBERS FOR MULTIPLE INSTANTIATIONS

Номер: US20130132453A1
Автор: Mitra Swapnajit
Принадлежит: PLX TECHNOLOGY, INC.

In a first embodiment of the present invention, a method for generating a random number for an instance of a hardware description language definition is provided, the method comprising: generating a unique signature for the instance; applying a message digest generation process on the unique signature to arrive at a message digest having a fixed length; and applying a random number generation process on the message digest. 1. A method for generating a random number for an instance of a hardware description language definition , the method comprising:generating a unique signature for each instance of the hardware description language definition;applying a message digest generation process on the unique signature to arrive at a message digest having a fixed length for each unique signature; and 'wherein each calling of a hardware description language simulation module description results in the generation of a random number without interaction with any other instance of the hardware description language definition.', 'applying a random number generation process on the message digests;'}2. The method of claim 1 , wherein the generating includes:determining a path for the instance; andconverting the path to a unique signature.3. The method of claim 2 , wherein the converting the path includesconverting a path name corresponding to each node in the path to a numerical code; andconcatenating the numerical codes corresponding to each node in the path together to form a unique signature.4. The method of claim 3 , wherein the numerical code is extended American Standard Code for Information Interchange (ASCII) code.5. The method of claim 1 , further comprising:generating a composite unique signature based upon the generated unique signature and the current time.6. The method of claim 5 , wherein the generated composite unique signature is also based upon a user-specified seed.7. The method of claim 6 , wherein the generating a composite unique signature includes ...

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Номер записи: 27
20-06-2013 дата публикации

Verifying speculative multithreading in an application

Номер: US20130159681A1
Автор: Mitchell D. Felton
Принадлежит: International Business Machines Corp

Verifying speculative multithreading in an application executing in a computing system, including: executing one or more test instructions serially thereby producing a serial result, including insuring that all data dependencies among the test instructions are satisfied; executing the test instructions speculatively in a plurality of threads thereby producing a speculative result; and determining whether a speculative multithreading error exists including: comparing the serial result to the speculative result and, if the serial result does not match the speculative result, determining that a speculative multithreading error exists.

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Номер записи: 28
27-06-2013 дата публикации

SIGNAL PROCESSING CIRCUIT, SIGNAL PROCESSING METHOD AND CONTROL PROGRAM RECORDING MEDIUM

Номер: US20130165063A1
Автор: Kitsunezuka Masaki
Принадлежит: NEC Corporation

In order to provide a means for solving a problem that it provides a signal processing circuit with small circuit area and low power consumption, a signal processing circuit includes the first multiplying means which multiplies the first signal including the first frequency component by the second signal including the second frequency component and thereby outputs the third signal, the second multiplying means which multiplies the first signal by the fourth signal of the second frequency whose phase is lagging equals to the first phase difference relative to the second signal and thereby outputs the fifth signal, the third multiplying means which multiplies the first signal by the sixth signal of the second frequency whose phase is lagging equals to the second phase difference relative to the second signal and thereby outputs the seventh signal, the first adding means which adds the third signal with the first weight, the fifth signal with the second weight and the seventh signal with the third weight respectively and a signal generating means which controls the first phase difference and the second phase difference based on a control signal and thereby outputs the second signal, the fourth signal and the sixth signal. 1. A signal processing circuit , comprising:a first multiplying unit that multiplies a first signal including a first frequency component by a second signal including a second frequency component and thereby outputting a third signal;a second multiplying unit that multiplies said first signal by a fourth signal of said second frequency whose phase is lagging equals to a first phase difference relative to said second signal and thereby outputting a fifth signal;a third multiplying unit that multiplies said first signal by a sixth signal of said second frequency whose phase is lagging equals to a second phase difference relative to said second signal and thereby outputting a seventh signal;a first adding unit that adds said third signal with a first ...

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Номер записи: 29
27-06-2013 дата публикации

System and Method for Implementing a Multiplication

Номер: US20130166616A1
Автор: Francky Catthoor, Praveen Raghavan, Robert Fasthuber
Принадлежит: Interuniversitair Microelektronica Centrum vzw IMEC, KU Leuven Research and Development, SAMSUNG ELECTRONICS CO LTD

The present system and method relate to a system for performing a multiplication. The system is arranged for receiving a first data value, and comprises means for calculating at run time a set of instructions for performing a multiplication using the first data value, storage means for storing the set of instructions calculated at run time, multiplication means arranged for receiving a second data value and at least one instruction from the stored set of instructions and arranged for performing multiplication of the first and the second data values using the at least one instruction.

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Номер записи: 30
04-07-2013 дата публикации

Floating-point error propagation in dataflow

Номер: US20130173682A1
Автор: Marko Radmilac
Принадлежит: Microsoft Corp

A process for propagating an error in a floating-point calculation is disclosed. A floating-point error occurring from the floating-point arithmetic calculation is trapped, and a special value is generated. Information regarding the error is stored as a payload of the special value. Program operations are resumed with the special value applied to further calculations dependent on the floating-point arithmetic calculation.

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Номер записи: 31
11-07-2013 дата публикации

Efficient Technique for Optimal Re-Use of Hardware In the Implementation of Instructions Used in Viterbi, Turbo and LPDC Decoders

Номер: US20130179484A1
Автор: Anderson Timothy D., Moharil Shriram D.
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

Low density parity check (LDPC) decoding can be mapped to a class of DSP instructions called MINST. The MINST class of instructions significantly enhance the efficiency of LDPC decoding by merging several of the functions required by LDPC decoders into a single MINST instruction. This invention is an efficient implementation of the MINST class of instructions using a configurable three input arithmetic logic unit. The carry output results of the three input arithmetic logic unit enable permit boundary decisions in a range determination required by the MINST instruction. The preferred embodiment employs 2's complement arithmetic and carry-save adder logic. This invention allows reuse of hardware required to implement MAX* functions in LDPC functions. 1. An apparatus for computing a MINST function comprising:a three input arithmetic logic unit having three inputs and an output, said three input arithmetic logic unit selectively configurable to perform the following combinations of three input operands a, b and threshold (a+b−threshold), (a+b+threshold), (a−b−threshold) and (a−b+threshold) and generate a corresponding Result and Carry at said output, where threshold is a predetermined range constant;register set having four registers connected to said output of said three input arithmetic logic unit storing four respective Carry outputs; and determine from first and second Carry outputs stored in respective registers of said register set whether a sum of a+b is within a range less than a threshold and greater than an arithmetic inverse of said threshold and generating a corresponding first output, and', 'determine from third and fourth Carry outputs stored in respective registers of said register set whether a difference of a−b is within said range less than said threshold and greater than an arithmetic inverse of said threshold and generating a corresponding second output., 'a range selection circuit having four inputs connected to corresponding registers of said ...

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Номер записи: 32
18-07-2013 дата публикации

High Accuracy Sin-Cos Wave and Frequency Generators, and Related Systems and Methods

Номер: US20130181753A1
Автор: David J. Hoyle
Принадлежит: Qualcomm Inc

High accuracy sin-cos wave and frequency generators, and related systems and methods. In non-limiting embodiments disclosed herein, the sin-cos wave generators can provide highly accurate sin-cos values for sin-cos wave generation with low hardware costs and small lookup table requirements. The embodiments disclosed herein may include a circuit to conduct an arithmetic approximation of a sin-cos curve based on a phase input. The circuit may be in communication with a point lookup table and a correction lookup table. The tables may receive the phase input and match the phase input to main sin-cos endpoints associated with the phase, and to a correction value for the phase. These values which are selected based on the phase input, may be communicated to a converter circuit where the arithmetic functions are applied to the values resulting in a sin-cos curve value.

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Номер записи: 33
25-07-2013 дата публикации

Pseudo-noise generator

Номер: US20130191427A1
Автор: Lewis Farrugia
Принадлежит: Astrium Ltd

The present invention relates to a pseudo-noise generator comprising a plurality of pseudo-random number generators and an averaging unit. The averaging unit is arranged to receive a plurality of pseudo-random numbers from the plurality of pseudo-random number generators, calculate a mean value of the plurality of pseudo-random numbers, and output said mean value as a digital pseudo-noise signal.

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Номер записи: 34
12-09-2013 дата публикации

DECIMAL ABSOLUTE VALUE ADDER

Номер: US20130238680A1
Автор: ATSUMI Hiroaki
Принадлежит: FUJITSU LIMITED

A decimal absolute value adder includes a first circuit adding two operands for a first result; a second circuit adding the two operands to 10 for a second result; a third circuit adding the two operands to 6 for a third result; a fourth circuit adding the two operands to 1 for a fourth result; a fifth circuit adding the two operands to 11 for a fifth result; a sixth circuit adding the two operands to 7 for a sixth result; and a selection circuit selecting the first, second, fourth or fifth result when adding two numbers of identical signs or adding two numbers of different signs resulting in a non-negative result, and selecting a 1's complement of the first, third, fourth or sixth result when adding two numbers of different signs resulting in a negative result. 1. A decimal absolute value adder comprises:a first arithmetic circuit that adds two operands and outputs a first arithmetic operation result;a second arithmetic circuit that adds the two operands to 10 and outputs a second arithmetic operation result;a third arithmetic circuit that adds the two operands to 6 and outputs a third arithmetic operation result;a fourth arithmetic circuit that adds the two operands to 1 and outputs a fourth arithmetic operation result;a fifth arithmetic circuit that adds the two operands to 11 and outputs a fifth arithmetic operation result;a sixth arithmetic circuit that adds the two operands to 7 and outputs a sixth arithmetic operation result; and selects any one of the first arithmetic operation result, the second arithmetic operation result, the fourth arithmetic operation result and the fifth arithmetic operation result in a case where an arithmetic operation for the two operands is an addition of numbers having identical signs or in a case where a target arithmetic operation of the two operands is an addition of two numbers having different signs and has an arithmetic operation result that is not negative,', "selects a 1's complement of any one of the first arithmetic ...

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Номер записи: 35
19-09-2013 дата публикации

SYSTEMS AND METHODS FOR WAVEFRONT ANALYSIS OVER CIRCULAR AND NONCIRCULAR PUPILS

Номер: US20130246493A1
Автор: Dai Guang-ming, Mahajan Virendra N.
Принадлежит:

Systems, methods, and software for determining a set of analytical or numerical polynomials that is orthonormal over circular or noncircular pupils are described. Closed-form orthonormal polynomials for circular, annular, hexagonal, elliptical, rectangular, and square pupils are derived. Such techniques can be applied to ray tracing as in the optical design and wavefront fitting from measurement as in the optical testing. These approaches can also be applied to wavefront reconstruction in adaptive optics. 2. The method according to claim 1 , wherein the domain Σ has the hexagon shape.3. The method according to claim 1 , wherein the domain Σ has the ellipse shape.4. The method according to claim 1 , wherein the domain Σ has the annulus shape.5. The method according to claim 1 , wherein the domain Σ has the rectangle shape.6. The method according to claim 1 , wherein the domain Σ has the square shape.8. The system according to claim 7 , wherein the domain Σ has the hexagon shape.9. The system according to claim 7 , wherein the domain Σ has the ellipse shape.10. The system according to claim 7 , wherein the domain Σ has the annulus shape.11. The system according to claim 7 , wherein the domain Σ has the rectangle shape.12. The system according to claim 7 , wherein the domain Σ has the square shape.13. The system according to claim 7 , wherein the vision treatment comprises a member selected from the group consisting of a spectacle lens shape claim 7 , an intraocular lens shape claim 7 , a contact lens shape claim 7 , a corneal ring implant shape claim 7 , a corneal inlay shape claim 7 , a corneal onlay shape claim 7 , a corneal implant shape claim 7 , or a laser treatment shape.14. A method of determining a vision treatment for a patient based on a set of orthonormal polynomials F over a domain Σ corresponding to a pupil of an eye of the patient claim 7 , the method comprising:using a processing hardware having a non-transitory tangible medium embodying machine- ...

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Номер записи: 36
26-09-2013 дата публикации

Variable Node Processing Unit

Номер: US20130254252A1
Автор: Andreev Alexander, Gribok Sergey, Izyumin Oleg
Принадлежит: LSI Corporation

A low-density parity check min-sum decoder including a variable node processing unit having N+1 inputs. A first bank of N+1 two-input adders each have an associated output, and at least one of the N+1 inputs go to more than two of the adders of the first bank. A second bank of N two-input adders has no adders in common with the first bank. At least one of the adders of the first bank provides its associated output to more than one adder of the second bank. The banks of adders are disposed in series. A sign module outputs a sign value produced from one of the inputs and an output from one of the adders of the second bank. N+1 outputs are provided, where one of the outputs is the sign value. 1. A low-density parity check min-sum decoder including a variable node processing unit comprising:N+1 inputs,a first bank of N+1 two-input adders, each having an associated output, at least one of the N+1 inputs going to more than two of the adders of the first bank,a second bank of N two-input adders, the first bank and the second bank having no adders in common,at least one of the adders of the first bank providing its associated output to more than one adder of the second bank,the banks of adders disposed in series,a sign module for outputting a sign value produced from one of the inputs and an output from one of the adders of the second bank, andN+1 outputs, where one of the outputs is the sign value.2. The decoder of claim 1 , wherein at least one of the two-input adders is a signed ripple-carry adder.3. The decoder of claim 1 , wherein at least one of the two-input adders is a signed ripple-carry adder that includes logic elements and a flip-flop interjected between two adjacent ones of the logic elements.4. The decoder of claim 1 , wherein each of the two-input adders is a signed ripple-carry adder with logic elements and a flip-flop interjected between two adjacent ones of the logic elements.5. A variable node processing unit comprising:N+1 inputs,a first bank of N+1 two- ...

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Номер записи: 37
03-10-2013 дата публикации

Systems with multiple port random number generators and methods of their operation

Номер: US20130262542A1
Автор: David G. Abdoo, Matthew W. Brocker, Steven D. Millman, Thomas E. Tkacik
Принадлежит: Individual

Methods and systems for producing random numbers include a random number generator with a first port and a second port. The first port is configured to receive a first type of random data request, and the random number generator is configured to generate first random data while the first type of request is asserted on the first port. The second port is configured to receive a second type of random data request, and the random number generator is configured to generate only a specified length of second random data in response to receiving the second type of request on the second port. An embodiment of a system also includes a data structure configured to store multiple random values, which are derived from the first random data generated by the random number generator in response to the first type of random data request.

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Номер записи: 38
03-10-2013 дата публикации

ELECTRONIC MULTIPLIER AND DIGITAL SIGNAL PROCESSOR INCLUDING THE SAME

Номер: US20130262544A1
Автор: Ahn Kyoung-Moon, Kang Ji-Su, Lee Yong-Ki, Shin Jong-Hoon, Shin Sun-Soo
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

An electronic multiplier, such as a multiplication circuit, may include a partial product generator, a Booth code encoder and an accumulator. The partial product generator may generate partial product data based on a Booth code and multiplicand data. The Booth code encoder may generate the Booth code based on multiplier data. The Booth code may include a zero-generation Booth code and a zero-avoidance Booth code. The Booth code encoder may selectively generate the zero-generation Booth code or the zero-avoidance Booth code when the partial product data correspond to a partial product of zero. The accumulator accumulates the partial product data to provide a multiplication result of the multiplicand data and the multiplier data. 1. An electronic multiplier , comprising:a partial product generator to generate partial product data based on a Booth code and multiplicand data;a Booth code encoder to generate the Booth code based on multiplier data, the Booth code including a zero-generation Booth code and a zero-avoidance Booth code, the Booth code encoder selectively generating the zero-generation Booth code or the zero-avoidance Booth code when the partial product data correspond to a partial product of zero; andan accumulator to accumulate the partial product data to provide a multiplication result of the multiplicand data and the multiplier data.2. The electronic multiplier of claim 1 , further comprising:a random number generator to generate a selection signal based on a random number,wherein the Booth code encoder is configured to randomly generate the zero-generation Booth code or a zero-avoidance Booth code in response to the selection signal.3. The electronic multiplier of claim 1 , wherein the partial product generator is configured to generate first zero-expression partial product data in response to the zero-generation Booth code and generate second zero-expression partial product data in response to the zero-avoidance Booth code claim 1 , all bits of the ...

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Номер записи: 39
03-10-2013 дата публикации

ARITHMETIC CIRCUIT AND ARITHMETIC METHOD

Номер: US20130262546A1
Автор: Kitamura Kenichi, SHINOMIYA Kensuke
Принадлежит: FUJITSU LIMITED

An arithmetic circuit includes a storage circuit configured to store a decimal floating point number in an encoded state, a detection circuit configured to detect a pattern of an arrangement of zeros from a bit pattern of the decimal floating point number by decoding the decimal floating point number stored in the storage circuit, and a leading-zero-count circuit configured to generate data indicative of a number of consecutive zeros starting from a most significant bit or from a least significant bit in a significand of the decimal floating point number in response to a detection result obtained by the detection circuit. 1. An arithmetic circuit , comprising:a storage circuit configured to store a decimal floating point number in an encoded state;a detection circuit configured to detect a pattern of an arrangement of zeros from a bit pattern of the decimal floating point number by decoding the decimal floating point number stored in the storage circuit; anda leading-zero-count circuit configured to generate data indicative of a number of consecutive zeros starting from a most significant bit or from a least significant bit in a significand of the decimal floating point number in response to a detection result obtained by the detection circuit.2. The arithmetic circuit as claimed in claim 1 , wherein the detection circuit includes:a zero detecting circuit configured to detect presence and absence of zero in each digit to output data indicative of the presence and absence of zero in each digit; anda pattern detecting circuit configured to detect the pattern of an arrangement of zeros based on the data indicative of the presence and absence of zero in each digit.3. The arithmetic circuit as claimed in claim 1 , wherein the decimal floating point number is in a DPD format specified in IEEE754-2008 claim 1 , and the detection circuit is configured to produce a bit value indicative of presence and absence of zero in each digit by performing a logical sum operation with ...

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Номер записи: 40
03-10-2013 дата публикации

ARITHMETIC CIRCUIT AND ARITHMETIC METHOD

Номер: US20130262549A1
Автор: Kitamura Kenichi
Принадлежит:

An arithmetic circuit includes a circuit to output n-th multiples of a multiplicand, a circuit to output an XOR operation result that is a result of performing an exclusive logical sum operation between the multiplicand and a result of shifting the multiplicand to left by one bit, a circuit to output a first selection signal in response to a first portion of a multiplier, a circuit to output a second selection signal in response to a second portion of the multiplier, a circuit to select, in response to the first selection signal, one of the n-th multiples of the multiplicand and the XOR operation result, a circuit to select, in response to the second selection signal, one of the n-th multiples of the multiplicand and the XOR operation result, and a circuit to output a result of adding up the first partial product and the second partial product. 1. An arithmetic circuit , comprising:a multiplicand store circuit to store a multiplicand;a multiplier store circuit to store a multiplier;an n-th-multiple calculating circuit to output n-th (no integer) multiples of the multiplicand;an intermediate XOR calculating circuit to output an XOR operation result that is a result of performing an exclusive logical sum operation between the multiplicand and a result of shifting the multiplicand to left by one bit;a first decode circuit to output a first selection signal in response to a first portion of the stored multiplier;a second decode circuit to output a second selection signal in response to a second portion of the stored multiplier;a first partial product selecting circuit to select, in response to the first selection signal, one of the n-th multiples of the multiplicand output by the n-th-multiple calculating circuit and the XOR operation result output by the intermediate XOR calculating circuit;a second partial product selecting circuit to select, in response to the second selection signal, one of the n-th multiples of the multiplicand output by the n-th-multiple ...

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Номер записи: 41
17-10-2013 дата публикации

Method for the Low Cost Operation of a Processing Machine

Номер: US20130275481A1
Автор: Koehl Alexander, Schultze Stephan
Принадлежит:

A method for low cost operation of a processing machine comprising determining a suitable processing speed, operating the processing machine at the suitable processing speed, and determining costs as a function of the processing speed. The suitable processing speed is the processing speed which leads to predetermined costs in a predetermined processing time during the operation of the processing machine. 1. A method for low cost operation of a processing machine comprising:determining a suitable processing speed, wherein the suitable processing speed is a processing speed which leads to predetermined costs in a predetermined processing time during operation of the processing machine;operating the processing machine at the suitable processing speed; anddetermining costs as a function of the processing speed.2. The method of claim 1 , wherein determining the suitable processing speed includes minimizing claim 1 , locally or globally claim 1 , a cost function dependent on the processing speed.3. The method of claim 2 , wherein the cost function is a polynomial function.4. The method of claim 3 , further comprising:determining costs for a number of different processing speeds during a measurement run or during normal operation; anddetermining coefficients of the polynomial function from measuring points.5. The method of claim 4 , further comprising:storing, in product-specific fashion, at least one of the suitable processing speed, the cost function, and the coefficients.6. The method of claim 2 , further comprising:representing the cost function dependent on the processing speed on a graph; andselecting the suitable processing speed from the graph.7. The method of claim 1 , further comprising: determining costs for a plurality of processing speeds, and', 'determining, as the suitable processing speed, a processing speed having costs closest to the predetermined costs., 'measuring the suitable processing speed by8. The method of claim 1 , wherein the processing machine ...

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Номер записи: 42
17-10-2013 дата публикации

DIVISION CIRCUIT AND MEMORY CONTROLLER

Номер: US20130275484A1
Автор: HIGETA Masanori, Nakayama Hiroshi, Osano Hidekazu, Sakamaki Hideyuki, TAKAKU Kazuya
Принадлежит:

A separation circuit separates a 32-bit dividend, (e.g., 1695) into 4-bit segments and outputs 9 separated dividends. The position of each dividend counted from the dividend having the lowest bit is i. A first output circuit concatenates at the end of a dividend, 0s of number equal to an integer multiple of 4 bits. Each calculation circuit outputs an 8-bit quotient, a numerical value created by the first output circuit divided by 3(=2−1 and n=2), and outputs from a second output circuit, a first bit sequence that is the upper 4 bits of the 8-bit quotient, and a second bit sequence in which i sets of lower 4 bits of the 8-bit quotient are arranged. A quotient addition circuit outputs, as a quotient of 1695 divided by 3, the sum of values each including the first bit sequence at upper bits and the second bit sequence at lower bits. 1. A division circuit comprising:{'sup': 'n', 'a separation circuit configured to separate a dividend into k-bit segments starting from a lowest bit of the dividend where k is integer multiple of n, and output h/k separated dividends, wherein the dividend is h-bit long that is longer than a specific divisor of 2−1 where n is an integer and n≧2;'}a first output circuit configured to output, for every separated dividend, a 2k-bit quotient that is obtained by dividing by the specific divisor a separated dividend with 0s added where the number of 0s is equal to integer multiple of k;a second output circuit configured to output, for every separated dividend, a first bit sequence that includes an upper k-bit sequence of the 2k-bit quotient, and a second bit sequence that includes i sets of lower k bits of the 2k-bit quotient, wherein a position of each separated dividend counted from a separated dividend having the lowest bit is called i where i=0 to h/k−1; anda quotient addition circuit configured to add composite sequences in each of which the first bit sequence is placed at upper bits and the second bit sequence is placed at lower bits.2. The ...

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Номер записи: 43
24-10-2013 дата публикации

Method of generating random number using nonvolatile memory in two-track scheme and apparatus for the same

Номер: US20130282781A1
Автор: Byeong-Ho Ahn, Dae-Seon PARK, Haeng-Seok KO, In-Seok Kang
Принадлежит: Electronics and Telecommunications Research Institute ETRI

A method of generating a random number using nonvolatile memory and an apparatus for the same are provided. The method of generating a random number includes reading random number state information from nonvolatile memory when power is supplied; updating the random number state of a random number generator using the random number state information and a saving entropy source, thereby producing updated random number state information; storing the updated random number state information in the nonvolatile memory; updating a random number state of the random number generator using the updated random number state information and a generating entropy source, thereby producing a generating random number state information; and producing a random number to be used in an application program using the generating random number state information and the generating entropy source.

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Номер записи: 44
24-10-2013 дата публикации

ARITHMETIC PROCESSING DEVICE AND METHODS THEREOF

Номер: US20130282784A1
Автор: Das Sarma Debjit, Hilker Scott, Oliver David S.
Принадлежит:

A device and methods are disclosed for communicating an unrounded result from one arithmetic calculation for use in a second, subsequent calculation. For example, an unrounded result of a first calculation can be forwarded to provide a multiplier, a multiplicand or an addend operand for the subsequent operation. The operand can be forwarded to the input of the same fused multiply addition module (FMAM) that supplied the result, or to another FMAM, and do so without regard to the precision of the forwarded operand, the precision of the subsequent operation, or the native precision of the FMAM. 120-. (canceled)21. A method , comprising:responsive to a first instruction, determining at a first multiply-addition module of a processor a first unrounded result based on a first operand in a register, the first unrounded result having a first precision; andcommunicating the first unrounded result to a second multiply-addition module of the processor to perform an arithmetic operation having a second precision different than the first precision.22. The method of claim 21 , further comprising:determining at the first multiply-addition module a first rounded result based on the first operand; andcommunicating the first rounded result to the second multiply-addition module.23. The method of claim 22 , further comprising:determining a second unrounded result at the second multiply-addition module based on the first unrounded result and a second operand.24. The method of claim 23 , wherein determining the second unrounded result comprises determining the second unrounded result based on the first rounded result.25. The method of claim 23 , further comprising:communicating the second unrounded result to the first multiply-addition module in response to determining the second unrounded result.26. The method of claim 23 , further comprising:communicating the second unrounded result to an input of the second multiply-addition module in response to determining the second unrounded ...

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Номер записи: 45
31-10-2013 дата публикации

Expanded Scope Incrementer

Номер: US20130290393A1
Автор: Singh Deepak K.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

An incrementor circuit and method for incrementing is provided that computes an output data word by increasing an input data word magnitude by one of several integer values. The incrementor circuit includes a mode increment signal circuit providing a designation of one of the integer values for increasing the input data word magnitude. A single constant incrementor is connected to the mode increment signal circuit and the input data word and provides an intermediate sum by selectively adding a constant to the input data word. A multiplex circuit logically combines selected input data word bit position values with the mode increment signal circuit designation forming logical bit position values and directs selected input data word bit position values, selected logical bit position values, and selected bit position values of the intermediate sum to form the output data word. 1. (canceled)2. (canceled)3. (canceled)4. (canceled)5. (canceled)6. (canceled)7. (canceled)8. (canceled)9. An incrementor circuit for computing an output data word by increasing an input data word magnitude by one of a plurality of positive integers , said incrementor circuit comprising:a mode circuit for receiving an input mode indication designating one of the plurality of positive integers for increasing the input data word magnitude and providing a mode select signal in response thereto;a first multiplex circuit connected to receive the input data word and providing binary values of selected bit positions of the input data word to a constant integer incrementor according to the mode select signal;the constant integer incrementor increasing the magnitude of received binary values of the selected bit positions of the input data word and connected to provide binary values to a second multiplex circuit; andthe second multiplex circuit including logic to receive the parallel binary values from the constant value incrementor and the input data word and including logic circuitry connected to the ...

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Номер записи: 46
31-10-2013 дата публикации

INTEGRATED CIRCUIT DEVICE AND METHOD FOR CALCULATING A PREDICATE VALUE

Номер: US20130290686A1
Автор: Barak Itzhak, Peled Yuval, Rozenberg Idan, Schupper Doron, Vaskevich Lev
Принадлежит: Freescale Semiconductor, Inc.

An integrated circuit device comprises at least one instruction processing module arranged to perform branch predication. The at least one instruction processing module comprises at least one predicate calculation module arranged to receive as an input at least one result vector for a predicate function and at least one conditional parameter value therefor and output a predicate result value from the at least one result vector based at least partly on the at least one received conditional parameter value. 1. An integrated circuit device comprising at least one instruction processing module arranged to perform branch predication , the at least one instruction processing module comprising at least one predicate calculation module arranged to:receive as an input at least one result vector for a predicate function and at least one conditional parameter value therefor; andoutput a predicate result value from the at least one result vector based at least partly on the at least one received conditional parameter value.2. The integrated circuit device of wherein the at least one predicate calculation module comprises multiplexing circuitry.3. The integrated circuit device of Of wherein the at least one result vector comprises a predicate result value for a plurality of permutations of the at least one conditional parameter value within a defined Boolean function.4. The integrated circuit device of wherein the instruction processing module further comprises at least one execution module arranged to receive at least one predicate calculation instruction comprising at least an indication of the at least one result vector.5. The integrated circuit device of claim 4 , wherein upon receipt of such an at least one predicate calculation instruction claim 4 , the at least one execution module is arranged to extract the at least an indication of the at least one result vector therefrom and provide the at least one result vector to the at least one predicate calculation module.6. The ...

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Номер записи: 47
31-10-2013 дата публикации

Cryptographic processing with random number generator checking

Номер: US20130290792A1
Автор: Frank James, Michael J. Torla, Steven D. Millman, Thomas E. Tkacik
Принадлежит: Individual

Embodiments of an electronic circuit comprise a module, such as a security module, configured to perform cryptographic processing for a predetermined security protocol that includes random number checking. The security module is controlled by a descriptor that includes instructions that cause the security module to access a generated random number, compare the generated random number to a random number stored during a previous execution of the descriptor, and generate an error signal when the generated random number and the previous execution random number are equal.

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Номер записи: 48
07-11-2013 дата публикации

FPGA-BASED HIGH-SPEED LOW-LATENCY FLOATING POINT ACCUMULATOR AND IMPLEMENTATION METHOD THEREFOR

Номер: US20130297666A1
Автор: Chen Yaowu, Yuan Longtao, Zhou Fan
Принадлежит: ZHEIJIANG UNIVERSITY

This invention discloses a FPGA based high-speed low-latency floating-point accumulation and its implementation method. Floating accumulation of this invention comprises a floating-point adder unit, numerous intermediate result buffers, an input control unit and an output control unit. The floating-point accumulation implementation method of this invention is used for gradation of the whole accumulation calculation process to ensure cross execution of accumulation calculation processes and graded storage of intermediate results of accumulation calculation at different levels; meanwhile, the operation in the mode of pure flow line can significantly improve utilization rate of internal floating-point adder, and maintain relatively low latency to output of final results of floating-point accumulation calculation. This invention is expected to improve utilization rate of floating-point adder through dynamic allocation of input data in internal floating-point adder unit, and thereby maintains higher arithmetic speed and relatively low latency while ensuring minimized consumption of logic or DSP resources as required. 1. A field-programmable gate array (FPGA) based high-speed low-latency floating accumulator , characterized in that it comprises:a floating-point adder unit used for adding operation of input floating points; the floating points include original data, intermediate result data on accumulated calculation of floating points at each level, and latency of flag bit of input floating points in synchronization with adding operation of the corresponding floating points;N intermediate result buffer units, corresponding to accumulated calculation of floating points at each level, which are used to buffer intermediate results of accumulated calculation of floating points; N refers to the number of accumulated levels;an input control unit used to receive original data and data on intermediate results of floating-point accumulation arithmetic at all levels, and set ...

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Номер записи: 49
14-11-2013 дата публикации

METHOD AND DEVICE FOR GENERATING BIG PRIME

Номер: US20130304779A1
Автор: Lu Zhou, Yu Huazhang
Принадлежит: FEITIAN TECHNOLOGIES CO., LTD.

The invention discloses a method for generating a large prime number and a system thereof. The method includes Step 1, generating a random number in size corresponding to number of digits input by a user, in which number of digits of the random number is identical to number of digits input by the user; Step 2, obtaining remainders by dividing all prime numbers in a predetermined little prime number table by a current value of the random number so as to form a remainder array; Step 3, determining whether there is a remainder 0 in the remainder array, if yes, going to Step 4; otherwise, going to Step 5; Step 4, updating the random number with a predetermined step, updating remainders in remainder array and going to Step 3; Step 5, checking for whether a current value of the random number is a prime number, if yes, going to Step 6; otherwise, going to Step 4; and Step 6, storing or outputting the current value of the random number. The solution provided by embodiments of the invention reduces primality test times, and thus saves time of generating a large prime number. 1. A method for generating a large prime number , characterized in that said method comprisesStep 1, generating a random number in size corresponding to number of digits input by a user, in which the number of digits of the random number is identical to the number of digits input by the user;Step 2, obtaining remainders by dividing all prime numbers in a predetermined little prime number table by a current value of the random number respectively, so as to form a remainder array;Step 3, determining whether any remainder is 0 in the remainder array, if yes, going to Step 4; otherwise going to Step 5;Step 4, updating the random number according to a predetermined step size, updating all remainders in the remainder array, and returning to Step 3;{'b': '5', 'Step , checking for whether the current value of the random number is a prime number, if yes, going to Step 6; otherwise, going to Step 4; and'}Step 6, ...

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Номер записи: 50
14-11-2013 дата публикации

SECURE SUM-OF-PRODUCT COMPUTATION METHOD, SECURE SUM-OF-PRODUCT COMPUTATION SYSTEM, COMPUTATION APPARATUS AND PROGRAMS THEREFOR

Номер: US20130304780A1
Автор: Chida Koji, Hamada Koki, Ikarashi Dai
Принадлежит: Nippon Telegraph and Telephone Corporation

There is provided a method that can quickly perform a secure sum-of-product computation by cooperative computation by three parties (computation apparatuses) that is easy to implement. In a secure computation method in which a party X performs a party-X random number generation step, a party-X first computation step and a party-X second computation step, a party Y performs a party-Y random number generation step, a party-Y first computation step and a party-Y second computation step, and a party Z performs a party-Z random number generation step, a party-Z first computation step and a party-Z second computation step, computation processings performed by the parties are symmetrical to each other. 14. A non-transitory computer readable medium including computer executable instructions that make a computer function as a computation apparatus according to . The present invention relates to a secure sum-of-product computation method, a secure sum-of-product computation system, a computation apparatus and programs therefor for performing data processings, particularly, a multiplication computation and a sum-of-product computation, while concealing data by secret sharing.In the field of management and operation of so-called sensitive information, such as customer information and management information, the information to be managed is increasing in variety, and the information processing technology such as cloud computing is changing, so that measures to ensure security and privacy are becoming more important. Recently, the secret sharing art has become popular to prevent leakage of information by distributing the information among plural sites. Besides, a secure functional computation (a multi-party protocol) for deriving a specified computation result without reconstructing the distributed information is also being developed for commercialization. The secret sharing art is effective as a measure to ensure security when storing information but has a risk of leakage of ...

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Номер записи: 51
05-12-2013 дата публикации

BALANCING CONSUMPTION OF RANDOM DATA

Номер: US20130325918A1
Автор: Sherwood David, Walker James William, Walton Travis
Принадлежит:

An apparatus for balancing consumption of random data, comprising an entropy manager operable to: responsive to receipt of a request for random data, monitor one or more events associated with a plurality of entities and access one or more rules; determine whether a higher level of entropy associated with the random data is required by analysing the one or more events in accordance with the one or more rules; responsive to a determination that a higher level of entropy is not required, set an entropy state associated with the entropy to a lower level of entropy and obtain random data from an entropy source having a lower level of entropy; and responsive to a determination that a higher level of entropy is required, switch an entropy state associated with the entropy to a higher level of entropy and obtain random data from an entropy source having a higher level of entropy. 1. An apparatus for balancing consumption of random data , comprising an entropy manager operable to:responsive to receipt of a request for random data, monitor one or more events associated with a plurality of entities and access one or more rules;determine whether a higher level of entropy associated with the random data is required by analysing the one or more events in accordance with the one or more rules;responsive to a determination that a higher level of entropy is not required, set an entropy state associated with the entropy to a lower level of entropy and obtain random data from an entropy source having a lower level of entropy; andresponsive to a determination that a higher level of entropy is required, switch an entropy state associated with the entropy to a higher level of entropy and obtain random data from an entropy source having a higher level of entropy.2. An apparatus as claimed in claim 1 , wherein the entropy manager is operable to monitor one or more events associated with a message connection associated with the plurality of entities.3. An apparatus as claimed in claim 2 , ...

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Номер записи: 52
19-12-2013 дата публикации

PROXY CALCULATION SYSTEM, METHOD, REQUEST DEVICE AND PROGRAM THEREOF

Номер: US20130339413A1
Автор: Kobayashi Tetsutaro, Yamamoto Go
Принадлежит: Nippon Telegraph and Telephone Corporation

Where G and H are cyclic groups, M is an integer of two or more, i=1, . . . , M, f is a homomorphic function of mapping a member xof group H to group G, Rand Rare random variables with a value in group G, ris a realized value of the random variable R, ris a realized value of the random variable R, and ais a random number of an integer of 0 or more, a random number generation unit generates random numbers a, a, . . . , a. A sampler is capable of calculating f(x)r, f(x)r, . . . , f(x)rto obtain a calculation result thereof as z, z, . . . , z, respectively. A power calculation unit calculates (z), (z), . . . , (z). An extended randomizable sampler is capable of calculating f(x×x× . . . ×x)rto obtain a calculation result zthereof. A determination unit determines whether or not (z)×(z)× . . . ×(z)=z. 1. A proxy calculation system comprising:{'sub': 1', '2', 'M, 'a random number generation unit to generate random numbers a, a, . . . , a;'}{'sub': 1', '1', '2', '2', 'M', 'M', '1', '2', 'M, 'a sampler to be capable of calculating f(x)r, f(x)r, . . . , f(x)rto obtain a calculation result thereof as z, z, . . . , z, respectively;'}{'sub': 1', '2', 'M, 'sup': a1', 'a2', 'aM, 'a power calculation unit to calculate (z), (z), . . . , (z);'}{'sub': 1', '2', 'M', '0', '0, 'sup': a1', 'a2', 'aM, 'an extended randomizable sampler to be capable of calculating f(x×x× . . . ×x)rto obtain a calculation result zthereof; and'}{'sub': 1', '2', 'M', '0, 'sup': a1', 'a2', 'aM, 'a determination unit to determine whether or not (z)×(z)× . . . ×(z)=z,'}{'sub': i', 'i', '0', 'i', 'i,', '0', '0', 'i, 'where G and H are cyclic groups, M is an integer of two or more, i=1, . . . , M, f is a homomorphic function of mapping a member xof group H to group G, Rand Rare random variables with a value in group G, ris a realized value of the random variable R, ris a realized value of the random variable R, and ais a random number of an integer of 0 or more.'}2. The proxy calculation system according to claim ...

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Номер записи: 53
19-12-2013 дата публикации

Multiply-and-accumulate operation in an implantable microcontroller

Номер: US20130339677A1
Автор: Mattias Tullberg
Принадлежит: St Jude Medical AB

The invention provides microprocessor extensions for cooperating with a sequential arithmetic-logic unit (ALU) to execute a multiply-and-accumulate operation (MAc). The ALU performs a continuous sequence of accumulation instructions synchronously with a clock signal (CLK1). Buffers (BUF1, BUF2) store input data which are fed to a combinatorial multiplier (MULT) by first buses (L 1 , L 2 ). A second bus (N 1 ) forwards the product to the ALU, where it is accumulated with previous data. Since at least the first buses operate independently of the clock signal, they do not limit the speed of the MAc operation. In particular embodiments, a finite state machine (FSM) controls the buses on the basis of triggers, e.g., signals from the multiplier and/or ALU indicating the completion of their respective instructions. The FSM may be operable in a low-power mode. The invention also relates to methods, computer programs and the use of a sequential ALU for executing MAc operations.

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Номер записи: 54
26-12-2013 дата публикации

METHOD FOR MONITORING THE OUTPUT OF A RANDOM GENERATOR

Номер: US20130346458A1
Автор: Boehl Eberhard
Принадлежит: ROBERT BOSCH GMBH

An assemblage for monitoring an output of a random generator is provided, which assemblage compares chronologically successive sample values at a sampling point with one another in order to detect a relationship of the compared sample values with one another. 1. A method for monitoring an output of a random generator , comprising:sampling chronologically successive output values at each one of at least two sampling points of the random generator; andcomparing the sampled chronologically successive output values with one another in order to detect a relationship of the sample values with one another.2. The method as recited in claim 1 , wherein the random generator includes a ring oscillator which has an odd number of inverting elements claim 1 , and wherein the sampled chronologically successive output values are stored.3. The method as recited in claim 2 , wherein an odd number of inverting elements is present in each case in the ring oscillator between at least two directly successive sampling points.4. The method as recited in claim 3 , wherein sample values at the sampling points at one point in time are compared with at least one predetermined pattern.5. The method as recited in claim 4 , wherein a first warning signal is generated upon detection of the at least one predetermined pattern in the sample values.6. The method as recited in claim 5 , wherein a second warning signal is outputted if a predetermined relationship between two sample values stored at different points in time is detected.7. The method as recited in claim 6 , wherein each occurrence of the second warning signal is counted in a counter claim 6 , and at least one action is triggered when at least one threshold value of said counter is reached claim 6 , and wherein the counter is reset when the second warning signal is not active.8. The method as recited in claim 7 , wherein the at least one action claim 7 , which is triggered when the at least one threshold value of said counter is reached ...

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Номер записи: 55
26-12-2013 дата публикации

Method for generating random numbers

Номер: US20130346459A1
Автор: Eberhard Boehl
Принадлежит: ROBERT BOSCH GMBH

A method and an assemblage for generating random numbers. In the method, at a ring oscillator that comprises an odd number of inverting elements, values are picked off at at least two sampling points, an odd number of inverting elements being present in each case between at least two directly successive sampling points.

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Номер записи: 56
26-12-2013 дата публикации

APPARATUS FOR CALCULATING A RESULT OF A SCALAR MULTIPLICATION

Номер: US20130346461A1
Автор: FISCHER Wieland
Принадлежит: INFINEON TECHNOLOGIES AG

An apparatus for calculating a result of a scalar multiplication of a reference number with a reference point on an elliptic curve comprises a point selector and a processor. The point selector is configured to select randomly or pseudo-randomly an auxiliary point on the elliptic curve. The processor is configured to calculate the result of the scalar multiplication with a double-and-always-add process using the auxiliary point. 1. An apparatus for calculating a result of a scalar multiplication of a reference number with a reference point on an elliptic curve , comprising:a point selector configured to select randomly or pseudo-randomly an auxiliary point on the elliptic curve; anda processor configured to calculate the result of the scalar multiplication with a double-and-always-add process using the auxiliary point.2. The apparatus according to claim 1 , wherein the point selector is configured to select the auxiliary point independent from the reference point or wherein the auxiliary point is selected based on a mixing function applied to the reference point.3. The apparatus according to claim 1 , wherein the processor is configured to calculate the result of the scalar multiplication in a way which is immune against save error attacks.4. The apparatus according to claim 1 , wherein the processor is configured to calculate the result of the scalar multiplication without using a dummy operation.5. The apparatus according to claim 1 , wherein the processor is configured to calculate the result of the scalar multiplication based on a loop claim 1 , which claim 1 , per execution claim 1 , operates on an intermediate point claim 1 , and configured to set the intermediate point equal to the auxiliary point prior to a first execution of the loop claim 1 , wherein the loop is executed N-times claim 1 , wherein N is a number of bits comprised by the reference number in a binary representation.6. The apparatus according to claim 5 , wherein the processor is configured to ...

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Номер записи: 57
26-12-2013 дата публикации

INTERCONNECTED ARITHMETIC LOGIC UNITS

Номер: US20130346462A1
Автор: BERGLAND Tyson, MAHAN Justin Michael, TOKSVIG Michael J.M.
Принадлежит:

An arithmetic logic stage in a graphics pipeline includes a number of arithmetic logic units (ALUs). The ALUs each include, for example, a multiplier and an adder. The ALUs are interconnected by circuitry that, for example, routes the output from the multiplier in one ALU to both the adder in that ALU and an adder in another ALU. 120-. (canceled)21. An arithmetic logic stage circuit of a graphics processor unit pipeline , the circuit comprising:a plurality of arithmetic logic units (ALUs); andprogrammable interconnections coupled between the ALUs and programmable according to programming code, wherein the interconnections are operable to allow the plurality of ALUs to implement, on a single pass, a multiply-add operation according to a first programming code and a multidimensional dot product computation according to a second programming code.22. The circuit of wherein the programming code comprises a respective code for each off the ALUs and wherein the respective code is symmetrical with respect to each other code.23. The circuit of wherein the interconnections are asymmetric with respect to each of the ALUs.24. The circuit of wherein each of the ALUs is analogous.25. The circuit of wherein the multidimensional dot product computation comprises a four-dimensional dot product.26. A method comprising:performing a first type of operation and performing a second type of operation using a plurality of arithmetic logic units (ALUs) comprising a first ALU, a second ALU, a third ALU and a fourth ALU, each of the ALUs comprising a first digital circuit operable for performing the first type of operation and a second digital circuit operable for performing the second type of operation;routing data that is output from the first digital circuit of the first ALU to both the second digital circuit of the second ALU and the second digital circuit of the third ALU, the routing through circuitry interconnecting the ALUs, the circuitry comprising a first multiplexer coupled between ...

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Номер записи: 58
26-12-2013 дата публикации

METHOD AND APPARATUS FOR SYNTHESISING A SUM OF ADDENDS OPERATION AND AN INTEGRATED CIRCUIT

Номер: US20130346927A1
Автор: Drane Theo Alan
Принадлежит: IMAGINATION TECHNOLOGIES LIMITED

A method is provided for a synthesising In RTL, a logic circuit and for manufacturing an integrated circuit for performing a sum of addends with faithful rounding. In this, optimisation constraints for a value of bits which may be discarded and a constant to include in a sum of addends are determined (). Next, the maximum number of whole columns that can be removed from the sum of addends array is derived () and those columns are discarded (). Next, a number of bits which can be removed from the least significant column is derived () and these bits are discarded (). The constant is included in the sum of addends and a logic array synthesised in RTL () before manufacturing an integrated circuit. 1. A method for deriving an Register Transfer Language (RTL) representation of a logic circuit for performing a sum of addends operation with faithful rounding , comprising:a) determining a number of bits to discard from a result of the sum of addends to produce a faithfully rounded result;b) determining a value of bits which may be discarded prior to performing the sum of addends operation and a constant to include in the sum of addends operation;c) determining how many least significant whole columns of bits may be discarded from the sum of addends operation;d) discarding those said columns;e) determining how many bits of a next least significant column can be discarded from the sum of addends operation;f) discarding those said bits from said next least significant column; andg) deriving an RTL representation of the sum of addends operation with said truncated columns and bits, and including said constant.2. The method of claim 1 , further comprising manufacturing an integrated circuit using the derived RTL representation of the sum of addends operation.3. A method according to claim 1 , in which the number of bits discarded in steps d) and f) is maximised.4. A method according to in which the sum of addends operation represents a multiplication.5. A method according to in ...

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Номер записи: 59
16-01-2014 дата публикации

Method and apparatus for decimal floating-point data logical extraction

Номер: US20140019506A1
Автор: Shihjong J. Kuo
Принадлежит: Intel Corp

Embodiments of systems, apparatuses, and methods for performing BIDSplit instructions in a computer processor are described. In some embodiments, the execution of a BIDSplit instruction tests the encoding of a binary-integer decimal source value and extracts a sign, exponent, and/or significand into a destination.

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Номер записи: 60
23-01-2014 дата публикации

Simd integer addition including mathematical operation on masks

Номер: US20140025717A1
Автор: Sergey Lyalin
Принадлежит: Intel Corp

Methods, apparatuses, and articles associated with SIMD adding two integers are disclosed. In embodiments, a method may include element-wise SIMD adding corresponding elements of a first SIMD-sized integer (A) and a second SIMD-sized integer (B) to generate a SIMD-sized integer result (R) and a carry bit. A may have an integer size (SizeA), while B may have an integer size (SizeB). The addition, in response to SizeA greater than SizeB, may further include updating R and the carry bit in view of one or more elements of A that do not have corresponding element or elements of B. Further, element-wise SIMD adding may include performing one or more mathematical operations on first one or more masks, with the first one or more masks interpreted as integers, and interpreting one or more integer results of the one or more mathematical operations as second one or more masks.

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Номер записи: 61
23-01-2014 дата публикации

CIRCUIT AND METHOD FOR GENERATING RANDOM NUMBER

Номер: US20140025718A1
Автор: Chen Shun-Hsiung
Принадлежит: Nuvoton Technology Corporation

A circuit and a method for generating a random number are provided. The circuit for generating the random number includes an analog-to-digital converter and a controller. The analog-to-digital converter sequentially generates a plurality of digital data in response to an analog signal. The controller utilizes an estimation procedure to sequentially analyze a variation trend of the plurality of digital data in a time sequence or extract components of the plurality of digital data within a preset frequency band. In addition, the controller generates a true random number based on a result of the estimation procedure. 1. A method for generating a random number , comprising:using an analog signal to cause an analog-to-digital converter to sequentially generate a plurality of digital data;sequentially analyzing a variation trend of the plurality of digital data in a time sequence or sequentially extracting components of the plurality of digital data within a preset frequency band by using an estimation procedure; andgenerating a true random number based on a result of the estimation procedure.2. The method for generating the random number according to claim 1 , further comprising:generating a random number seed based on the true random number; andfeeding the random number seed into a pseudo random number generator such that the pseudo random number generator generates a pseudo random number.3. The method for generating the random number according to claim 1 , wherein the step of sequentially analyzing the variation trend of the plurality of digital data in the time sequence using the estimation procedure comprises:obtaining an average of the plurality of digital data;selecting the plurality of digital data one by one so as to sequentially set each of the plurality of digital data as a sampling data;determining whether a value of the sampling data is greater than the average;if the value of the sampling data is greater than the average, determining that the sampling data ...

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Номер записи: 62
30-01-2014 дата публикации

Methods and Systems for Determining Characteristics of a Sequence of n-state Symbols

Номер: US20140032623A1
Автор: Peter Lablans
Принадлежит: Individual

Maximum length properties of n-state sequences of n-state symbols with n=2 or n>2 are tested. Checkwords are generated from p consecutive n-state symbols in a sequence of n-state symbols which may overlap by (p−1) n-state symbols. If a sequence has n p −1 n-state symbols in which 2 consecutive checkwords overlap in (p−1) n-state symbols and each checkword formed in the extended sequence is unique, then the sequence is a maximum length n-state sequence. An n-state feedback shift register based sequence generator with p n-state register elements is tested on the content of the shift register for n p −1 cycles. If the shift register content is not repeated the sequence is maximum length. Generation of a sequence is stopped when the content repeats. Non-reversible n-state inverters and non-reversible n-state logic functions are applied to generate n-state sequences

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Номер записи: 63
06-02-2014 дата публикации

Memory system generating random number and method generating random number

Номер: US20140037086A1
Автор: Changkyu Seol, Hong Rak Son, Junjin Kong, Pilsang Yoon
Принадлежит: SAMSUNG ELECTRONICS CO LTD

In a memory of non-volatile memory cells, a random number is generated by programming non-volatile memory cells, reading the programmed non-volatile memory cells using a random number read voltage selected in accordance with a characteristic of the non-volatile memory cells to generate random read data, and generating the random number from the random read data.

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Номер записи: 64
06-02-2014 дата публикации

RANDOM NUMBER GENERATING SYSTEM BASED ON MEMORY START-UP NOISE

Номер: US20140040338A1
Автор: Handschuh Helena, Schrijen Geert Jan, Van Der Sluis Erik
Принадлежит: INTRINSIC ID B.V.

A random number generating system for generating a sequence of random numbers comprising a memory, the memory being writable, volatile and configured such that the memory contains an at least partially random memory content upon each powering-up of the memory, an instantiating unit configured for seeding the random number generating system with a seed dependent upon the at least partially random memory content, the sequence of random numbers being generated in dependence upon the seed, and an over-writing unit configured for over-writing at least part of the memory with random numbers generated by the random number generating system in dependence upon the seed. 1. A random number generating system for generating a sequence of random numbers comprisinga memory, the memory being writable, volatile and configured such that the memory contains an at least partially random memory content upon each powering-up of the memory,an instantiating unit configured for seeding the random number generating system with a seed dependent upon the at least partially random memory content, the sequence of random numbers being generated in dependence upon the seed, andan over-writing unit configured for over-writing at least part of the memory with random numbers generated by the random number generating system in dependence upon the seed.2. A random number generating system as in claim 1 , wherein the over-writing unit is configured to over-write the memory with random numbers throughout the generation of the sequence of random numbers.3. A random number generating system as in claim 2 , wherein the over-writing unit is configured to write a random number generated by the random number generating system in dependence upon the seed each time a predetermined number of random numbers of the sequence of random numbers have been generated.4. A random number generating system as in claim 1 , wherein the over-writing unit is configured for over-writing the at least part of the memory with ...

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Номер записи: 65
13-02-2014 дата публикации

OPERATION CIRCUIT AND CONTROL METHOD OF OPERATION CIRCUIT

Номер: US20140046994A1
Автор: KAMOSHIDA Shiro
Принадлежит:

An operation circuit includes: a register that holds a decimal floating point number of a DPD (densely-packed decimal) format having a sign field, a combination field and a succeeding mantissa field; a first logical operation circuit that performs an operation including an exclusive logical sum operation and a modulo operation on values of the combination field; a second logical operation circuit that performs an operation including an exclusive logical sum operation and a modulo operation on values of the succeeding mantissa field; and a third logical operation circuit that performs a logical operation on a value of the sign field, an operation result of the first logical operation circuit and an operation result of the second logical operation circuit. 1. An operation circuit , comprising:a register that holds a decimal floating point number of a DPD (densely-packed decimal) format having a sign field, a combination field and a succeeding mantissa field;a first logical operation circuit that performs an operation including an exclusive logical sum operation and a modulo operation on values of the combination field;a second logical operation circuit that performs an operation including an exclusive logical sum operation and a modulo operation on values of the succeeding mantissa field; anda third logical operation circuit that performs a logical operation on a value of the sign field, an operation result of the first logical operation circuit and an operation result of the second logical operation circuit.2. The operation circuit according to claim 1 , further comprisinga comparison circuit that detects an error of the decimal floating point number by comparing an error detecting code generated by the first logical operation circuit and an expected value of error detecting code of the decimal floating point number.3. The operation circuit according to claim 2 , further comprisinga transmission circuit that transmits the decimal floating point number to the first ...

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Номер записи: 66
20-02-2014 дата публикации

Filters and Functions Using Exponential Decay

Номер: US20140050415A1
Автор: Sims Karl P.
Принадлежит:

The technology described in this document relates to filters and functions that are based on exponential decay functions. In one aspect, the technology is embodied in a method that includes using a computing device to compute a first function as a combination of (i) an exponential decay function, a decay factor for which is chosen based on a Gaussian function, and (ii) at least a second function that is obtained by one or more convolution operations on the decay function. The first function provides an approximation of at least a portion of the Gaussian function. 1. A method comprising:using a computing device to compute a first function as a combination of (i) an exponential decay function, a decay factor for which is chosen based on a Gaussian function, and (ii) at least a second function that is obtained by one or more convolution operations on the decay function, the first function providing an approximation of at least a portion of the Gaussian function.2. The method of claim 1 , wherein the exponential decay function comprises a spatial domain function.3. The method of claim 2 , wherein the approximation of the Gaussian function is provided as a combination of the first function and a spatially-reversed version of the first function.4. The method of claim 1 , wherein the exponential decay function comprises a time domain function.5. The method of claim 4 , wherein the approximation of the Gaussian function is provided as a combination of the first function and a time-reversed version of the first function.6. The method of claim 1 , comprising computing the second function as a self-convolution of the decay function.7. The method of claim 1 , comprising computing the second function as a convolution between two convolution sums based on the decay function.8. The method of claim 1 , wherein computing the combination comprises selecting corresponding weights for the decay function and at least the second function such that a sum of the weights is substantially ...

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Номер записи: 67
20-02-2014 дата публикации

APPARATUS AND ARCHITECTURE FOR GENERAL POWERING COMPUTATION

Номер: US20140052767A1
Автор: Diaz Brugueira Javier, Vazquez Alvarez Alvaro
Принадлежит: UNIVERSIDADE DE SANTIAGO DE COMPOSTELA

An apparatus for general powering computation is disclosed. The apparatus is capable of computing a powering function of a floating-point number with an unrestricted exponent. The unrestricted exponent can be a fixed-point or a floating-point exponent. Additionally, the unrestricted exponent can be an inverse of a number in order to enable for q-th root computation using the same hardware processor and architecture. 1. An apparatus for general powering computation comprising:(a) a plurality of memory elements; and{'sup': 'Z', '(b) a hardware processor configured for computing a powering function Xof a floating-point number X, wherein Z is an unrestricted exponent.'}2. The apparatus of claim 1 , wherein said unrestricted exponent is a fixed-point or a floating-point exponent.3. The apparatus of claim 2 , wherein said unrestricted exponent is an inverse of a number resulting in a q-th root computation using said hardware processor.4. The apparatus of claim 3 , wherein said hardware processor comprises a multiplexing unit claim 3 , a reciprocal unit claim 3 , a logarithm unit claim 3 , an exponential unit claim 3 , a multiplication unit claim 3 , a shifter unit claim 3 , or combinations thereof.5. The apparatus of claim 4 , wherein said reciprocal unit claim 4 , said logarithm unit claim 4 , and said multiplication unit are configured for performing computations contemporaneously.6. The apparatus of claim 5 , wherein said exponential unit is configured for performing computations in an on-line basis.7. The apparatus of claim 6 , wherein said reciprocal unit claim 6 , said logarithm unit claim 6 , and said multiplication unit are configured for performing computations in a most-significant-digit first basis.8. The apparatus of claim 7 , wherein said hardware processor is chosen from the group consisting of an integrated circuit claim 7 , a FPGA device claim 7 , a microprocessor claim 7 , a microcontroller claim 7 , a digital signal processor (DSP) claim 7 , and a ...

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Номер записи: 68
27-02-2014 дата публикации

Reducing bias in hardware generated random numbers

Номер: US20140059100A1
Автор: John S. Liberty, Marty L. Tsai
Принадлежит: International Business Machines Corp

A random number generator of a processor comprises a whitener for reducing the bias in random numbers generated by the random number generator. The whitener receives a random number of a first length read by an array of latches with inputs from an array of oscillators. The whitener dynamically creates a mask of the first length based on a parity of at least one previous random number read from the array of latches during at least one cycle prior to reading the random number. The whitener applies a compare operation between the random number and the mask to generate a whitened random number of the first length, with reduced bias, without reducing randomness.

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Номер записи: 69
27-02-2014 дата публикации

Accuracy configurable adders and methods

Номер: US20140059105A1
Автор: Andrew B. Kahng, Seokhyeong Kang
Принадлежит: UNIVERSITY OF CALIFORNIA

A preferred method of accuracy configuration with an approximate adder receives two input operands and generates a first approximate adder output with a plurality of sub-adders having a first accuracy under a first condition. Error detection and correction is selectively enabled to generate a next approximate adder output having a second accuracy that is higher than the first accuracy under a second condition. In preferred embodiments, a pipelined architecture provides selectable stages and the enablement of each successive stage provides a high level of accuracy. Power gated control can achieve enablement of error correction stages to conserve power.

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Номер записи: 70
27-02-2014 дата публикации

Arithmetic circuit for performing division based on restoring division

Номер: US20140059106A1
Автор: Kenichi Kitamura, Kensuke SHINOMIYA
Принадлежит: Fujitsu Ltd

An arithmetic circuit for performing division based on restoring division includes an intermediate remainder register configured to store an intermediate remainder, a quotient prediction circuit configured to perform, based on information about two most significant digits of the intermediate remainder and a most significant digit of a divisor, quotient prediction having lower precision than a highest precision obtainable from the information, thereby generating a prediction result, a fixed-value multiplication circuit configured to output one or more N-th (N: integer) multiples of the divisor selected in response to the prediction result, one or more subtracters configured to subtract, from the intermediate remainder, the one or more N-th multiples of the divisor output from the fixed-value multiplication circuit, and a partial quotient calculating circuit configured to obtain a partial quotient in response to one or more carry-out bits of one or more subtractions performed by the one or more subtracters.

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Номер записи: 71
06-03-2014 дата публикации

PSEUDO RANDOM NUMBER GENERATOR AND METHOD FOR PROVIDING A PSEUDO RANDOM SEQUENCE

Номер: US20140067891A1
Автор: Goettfert Rainer
Принадлежит: INFINEON TECHNOLOGIES AG

In various embodiments, a pseudo random number generator is provided. The pseudo random number generator may include: a pair of shift registers, wherein a first shift register in the pair is a linear shift register and a second shift register in the pair is a nonlinear shift register, wherein the linear shift register is configured to receive a first output sequence from the nonlinear shift register, and to take the first output sequence as a basis for providing a second output sequence; wherein the pseudo random number generator is configured to take the second output sequence as a basis for providing a pseudo random sequence. 1. A pseudo random number generator , comprising:a pair of shift registers, wherein a first shift register in the pair is a linear shift register and a second shift register in the pair is a nonlinear shift register, wherein the linear shift register is configured to receive a first output sequence from the nonlinear shift register, and to take the first output sequence as a basis for providing a second output sequence;wherein the pseudo random number generator is configured to take the second output sequence as a basis for providing a pseudo random sequence.2. The pseudo random number generator as claimed in claim 1 ,wherein the linear shift register has maximum periodicity.3. The pseudo random number generator as claimed in claim 1 ,wherein the nonlinear shift register has maximum periodicity.4. The pseudo random number generator as claimed in claim 1 ,wherein a length of the nonlinear shift register is less than or equal to a length of the linear shift register.5. The pseudo random number generator as claimed in claim 1 ,wherein a length of the nonlinear shift register is chosen to be in a range between ≧5 and ≦50.6. The pseudo random number generator as claimed in claim 1 ,wherein a length of the linear shift register is chosen to be in a range between ≧5 and ≦50 memory elements longer than a length of the nonlinear shift register.7. The ...

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Номер записи: 72
06-03-2014 дата публикации

Squaring Circuit

Номер: US20140067893A1
Автор: Gupta Saurabh, Thornton Mitchell A.
Принадлежит:

Methods, apparatuses, and computer program products for squaring an operand include identifying a fixed-point value with a fixed word size and a substring size for substrings of the fixed-point value, wherein the fixed-point value comprises a binary bit string. A square of the fixed-point value can be determined using the fixed point value, the substring size, and least significant bits of the fix-point value equal to the substring size. 1. A method for squaring a value , comprising;identifying a fixed-point value with a fixed word size and a substring size for substrings of the fixed-point value, wherein the fixed-point value comprises a binary bit siring; anddetermining a square of the fixed-point value using the fixed point value, the substring size, and least significant bits of the fix-point value equal to the substring size.2. The method of claim 1 , wherein determining the square comprises:iteratively determining squares of substrings of the fixed-point value using least significant oils of each operand equal to the substring size and the substring of the fixed-point value, wherein the operand in each iteration comprises a portion of the previous operand, wherein the operand is formed by decatenating the previous operand least significant bits equal to the substring size.3. The method of claim 1 , wherein determining the square includes:identifying the fixed-point valise as an operand;determining a substring of the operand as least significant bits of the operand where the sub-string is of a specified substring size;decatenating the substring from the operand to form a word;squaring the substring using the word, the substring, and the substring size;add the square of the substring to a result;if a length of the word is greater than zero, identifying the word as the operand and executing the determining, decatenating, squaring, and adding steps; andif the length of the word and substring is zero iterating once more to account for non-zero residual values, and ...

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Номер записи: 73
13-03-2014 дата публикации

ARCHITECTURE GUIDED OPTIMAL SYSTEM PRECISION DEFINITION ALGORITHM FOR CUSTOM INTEGRATED CIRCUIT

Номер: US20140074900A1
Автор: Ng Pius, Padmanabhan Satish, Pandurangan Anand, Selvaraj Siva
Принадлежит: ALGOTOCHIP CORPORATION

Systems and methods are disclosed to automatically determine an optimal number format representation for a model or code to be implemented in a custom integrated circuit (IC) by determining a ratio of dynamic range to static range in the model or code, and selecting a floating point or a fixed point number representation based on the ratio; determining the optimal number representation format based on a cost function that includes hardware area and power cost associated with a predetermined bit precision arithmetic; automatically generating a processor architecture customized to the optimal number representation format; and synthesizing the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication. 1. A method to automatically determine an optimal number format representation for a model or code to be implemented in a custom integrated circuit (IC) , comprising:a. determining a ratio of dynamic range to static range in the model or code, and selecting a floating point or a fixed point number representation based on the ratio;b. determining an optimal number representation format based on a cost function that includes hardware area cost and power cost associated with a predetermined bit precision arithmetic;c. automatically generating a processor architecture customized to the optimal number representation format; andd. synthesizing the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.2. The method of claim 1 , comprising using a memory storage requirement for the number representation as an optimization cost.3. The method of claim 1 , comprising determining real-time performance for the number representation as an optimization cost.4. The method of claim 1 , comprising determining the number of bits needed in the number representation format.5. The method of claim 4 , wherein the number of bits comprises any ...

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Номер записи: 74
13-03-2014 дата публикации

NUMBER REPRESENTATION AND MEMORY SYSTEM FOR ARITHMETIC

Номер: US20140074902A1
Автор: Gustafson John L., Lu Shih-Lien L., Naeimi Helia, Nathan Ralph
Принадлежит: Intel Corporation

A method, device and system for representing numbers in a computer including storing a floating-point number M in a computer memory; representing the floating-point number M as an interval with lower and upper bounds A and B when it is accessed by using at least two floating-point numbers in the memory; and then representing M as an interval with lower and upper bounds A and B when it is used in a calculation by using at least three floating-point numbers in the memory. Calculations are performed using the interval and when the data is written back to the memory it may be stored as an interval if the size of the interval is significant, i.e. larger than a first threshold value. A warning regarding the suspect accuracy of any data stored as an interval may be issued if the interval is too large, i.e. larger than a second threshold value. 1. A method for representing numbers in a memory of a computer system , the method comprising:storing a floating-point number M in the memory;representing the floating-point number M as an interval with lower and upper bounds A and B by using at least two floating-point numbers in the memory if M is accessed; andrepresenting the floating-point number M as an interval with lower and upper bounds A and B by using at least three floating-point numbers in the memory if M is used in a calculation.2. The method of claim 1 , wherein:representing the floating-point number M, when it is accessed, includes using a floating-point number R in which M is the midpoint of the interval and R is the radius so that A=M−R and B=M+R.3. The method of claim 2 , wherein:representing the floating-point number M, if it is used in a calculation, includes using a floating-point number N in which M+N is the midpoint of the interval and R is the radius so that A=(M+N)−R and B=(M+N)+R.4. The method of claim 3 , wherein:if(N>1FP) then M=M+1FP and N=N−1FP, and if (N<1FP) then M=M−1FP and N=N+1FP.5. The method of claim 4 , further comprising:representing the ...

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Номер записи: 75
20-03-2014 дата публикации

Performing a division operation using a split division circuit

Номер: US20140082036A1
Автор: Ivan E. Sutherland, Josephus C. Ebergen, Navaneeth P. Jamadagni
Принадлежит: Oracle International Corp

The disclosed embodiments disclose techniques for using a split division circuit that includes a first divider that is optimized for a first range of divisor values and a second divider that is optimized for a second range of divisor values; the first range is distinct from the second range. During operation, the circuit receives a divisor for the division operation. The circuit: determines whether the divisor is in the first range or the second range to determine whether the first divider or the second divider should perform the division operation; performs the division operation in the selected host divider; and then outputs the result that was generated by the selected host divider.

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Номер записи: 76
27-03-2014 дата публикации

Modified Fixed-Point Algorithm For Implementing Infrared Sensor Radiation Equation

Номер: US20140089362A1
Автор: Karaki Habib Sami, Khanna Ankit
Принадлежит:

A system including an integrated circuit chip also includes a microcontroller in the chip and an algorithm for execution by the microcontroller. The algorithm includes addition, subtraction, and multiplication operators (e.g. ) and shift-left and shift-right operators (e.g., ) configured for solving particular equations (Eqns. 1-4). Input numbers are within particular ranges to allow the shift operators to shift binary bits so each number so it fits within a register of a particular width. An IR sensor () may convert IR radiation () to produce a voltage (V) representing the temperature (T) of an IR emitting object (). The algorithm () operates in conjunction with the microcontroller () to convert the voltage (V) into a value representing the temperature (T) of the remote object () without keeping track of decimal points and resolution of the numbers. 1. A system comprising:(a) an integrated circuit chip;(b) a microcontroller in the integrated circuit chip; (1) a plurality of addition operators, a plurality of subtraction operators, a plurality of multiplication operators, a plurality of shift-left operators, and a plurality of shift-right operators configured so as to solve a particular group of equations, and', '(2) wherein for a plurality of input numbers each having a predetermined value within a predetermined range, respectively, the various shift-left and shift-right operators shift numbers are generated according to the algorithm so as to automatically establish the resolution of each number so it fits within a register of a predetermined number of bits, and wherein the microcontroller is particularly configured for solving the particular group of equations for the input numbers and their associated predetermined ranges., '(c) an algorithm coupled to the microcontroller, the algorithm including'}2. The system of configured to convert IR (infrared) radiation emitted by a remote object to a value representative of a temperature Tof the remote object claim 1 , ...

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Номер записи: 77
03-04-2014 дата публикации

Random Number Generator In A MPP Database

Номер: US20140095526A1
Автор: Caleb Welton, Florian Schoppmann, Hitoshi Harada
Принадлежит: Pivotal Software Inc

A random number generation process generated uncorrelated random numbers from identical random number sequences on parallel processing database segments of an MPP database without communications between the segments by establishing a different starting position in the sequence on each segment using an identifier that is unique to each segment, query slice information and the number of segments. A master node dispatches a seed value to initialize the random number sequence generation on all segments, and dispatches the query slice information and information as to the number of segments during a normal query plan dispatch process.

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Номер записи: 78
03-04-2014 дата публикации

System and Method with Specific Ordered Execution Over Physical Elements

Номер: US20140095564A1
Автор: III Donald Wood, Kwak Sung Ung, Loomis, MA Edward Tangkwai, Muchsel Robert Michael, Parvarandeh Pirooz
Принадлежит:

The invention relates to semiconductor devices, and more particularly, to systems, devices and methods of utilizing inherent differences among physical elements in an electrical component to generate unique and non-duplicable numbers that are statistically random and repeatable. These bits may be applied as identifications, random number seeds or encryption keys in many security applications, e.g., a financial terminal. An integrator is coupled to a plurality of physical elements, selects two physical elements or element sets, and generates an integrated difference signal according to a difference between these two physical elements or element sets. A comparison-decision logic further determines whether the difference between the selected two physical elements is associated with a bit of “1” or “0”. In some embodiments, a multi-bit number constitutes multiple bits each of which may be derived from a difference between two randomly selected physical elements or element sets. 1. A number generator , comprising:a plurality of physical elements in which every two physical elements are associated with an inherent difference due to non-uniformity and imprecision of a manufacturing process;an integrator, coupled to the plurality of physical elements, the integrator selecting two sets of physical elements from the plurality of physical elements, amplifying over time a difference between the two selected sets of physical elements and generating a first integrated difference signal; anda comparison-decision logic, coupled to the integrator, the comparison-decision logic determining whether the difference between the two selected sets of physical elements is associated with a first bit of “1” or “0”.2. The number generator according to claim 1 , wherein each of the plurality of physical elements is made of a capacitor claim 1 , and the integrator is implemented based on a differential operational amplifier and an integration capacitor to integrate the difference between two ...

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Номер записи: 79
03-04-2014 дата публикации

Fused Multiply-Adder with Booth-Encoding

Номер: US20140095568A1
Автор: Christophe J. Layer, Klaus M. Kroener, Maarten J. Boersma, Silvia M. Mueller
Принадлежит: International Business Machines Corp

A fused multiply-adder is disclosed. The fused multiply-adder includes a Booth encoder, a fraction multiplier, a carry corrector, and an adder. The Booth encoder initially encodes a first operand. The fraction multiplier multiplies the Booth-encoded first operand by a second operand to produce partial products, and then reduces the partial products into a set of redundant sum and carry vectors. The carry corrector then generates a carry correction factor for correcting the carry vectors. The adder adds the redundant sum and carry vectors and the carry correction factor to a third operand to yield a final result.

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Номер записи: 80
10-04-2014 дата публикации

MIXED PRECISION ESTIMATE INSTRUCTION COMPUTING NARROW PRECISION RESULT FOR WIDE PRECISION INPUTS

Номер: US20140101216A1
Автор: Gschwind Michael K., Salapura Valentina
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A technique is provided for performing a mixed precision estimate. A processing circuit receives an input of a first precision having a wide precision value. The processing circuit computes an output in an output exponent range corresponding to a narrow precision value based on the input having the wide precision value. 1. A computer system configured to perform a mixed precision estimate , the system comprising:a processing circuit, the system configured to perform a method comprising:receiving, by the processing circuit, an input of a wide precision having a wide precision value; andcomputing, by the processing circuit, an output in an output exponent range corresponding to a narrow precision value based on the input having the wide precision value.2. The computer system of claim 1 , wherein the method further comprises storing claim 1 , by the processing circuit claim 1 , the output in a register having an architected register storage format in a wide precision format.3. The computer system of claim 1 , wherein the method further comprises based on the wide precision value of the input having an input exponent failing to correspond to the output exponent range claim 1 , generating the output as an out of range value.4. The computer system of claim 3 , wherein the out of range value comprises at least one of zero and infinity.5. The computer system of claim 1 , wherein the method further comprises based on the input comprising a wide not a number (NaN) claim 1 , converting the wide not a number to a narrow not a number in which not a number properties are preserved.6. The computer system of claim 1 , wherein the method further comprises based on the input having the wide precision value with an input exponent failing to adhere to a valid exponent range of a valid single precision value claim 1 , generating a mantissa mask based on the input exponent to be applied to a mantissa of the output.7. The computer system of claim 6 , wherein the method further comprises ...

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Номер записи: 81
10-04-2014 дата публикации

Chaos-based pseudo-random number generation

Номер: US20140101217A1
Автор: Abhinav S. MANSINGKA, Ahmed Gomaa Ahmed RADWAN, Khaled Nabil Salama, Mohamed L. BARAKAT
Принадлежит: King Abdullah University of Science and Technology KAUST

Various methods and systems related to chaos-based pseudo-random number generation are presented. In one example, among others, a system includes a pseudo-random number generator (PRNG) to generate a series of digital outputs and a nonlinear post processing circuit to perform an exclusive OR (XOR) operation on a first portion of a current digital output of the PRNG and a permutated version of a corresponding first portion of a previous post processed output to generate a corresponding first portion of a current post processed output. In another example, a method includes receiving at least a first portion of a current output from a PRNG and performing an XOR operation on the first portion of the current PRNG output with a permutated version of a corresponding first portion of a previous post processed output to generate a corresponding first portion of a current post processed output.

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Номер записи: 82
06-01-2022 дата публикации

CONTROL SYSTEM AND CONTROL DEVICE

Номер: US20220004155A1
Автор: KAWAI Ko, TOKU Takahiro
Принадлежит: Omron Corporation

This control system includes: a first arithmetic unit for doing cyclic execution of a first task to which one or a plurality of processes are allocated using a first control cycle; and a second arithmetic unit for doing cyclic execution of a second task to which one or a plurality of processes are allocated using a second control cycle that is longer than the first control cycle. For the first task, a first data collection process with a first input data as the target and a corresponding first data processing process are allocated. Depending on the setting via the support device, a second data collection process with a second input data as the target and a corresponding second data processing process are allocated to either of the first task and the second task. 1. A control system comprising:a control device that executes a control arithmetic for controlling a control target; anda support device that sets content of the control arithmetic which is executed by the control device,wherein the control device includes a first arithmetic unit for cyclically executing a first task to which one or a plurality of processes is allocated in a first control cycle and a second arithmetic unit for cyclically executing a second task to which one or a plurality of processes is allocated in a second control cycle that is longer than the first control cycle,the control arithmetic includes a data collection process of collecting input data that is capable of being referred to by the control device and a data processing process of processing the collected input data to generate new data,a first data collection process with first input data as a target and a corresponding first data processing process are allocated to the first task, anda second data collection process with second input data as a target and a corresponding second data processing process are allocated to either of the first task and the second task in accordance with a setting via the support device.2. The control ...

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Номер записи: 83
06-01-2022 дата публикации

CIRCULAR ACCUMULATOR FOR FLOATING POINT ADDITION

Номер: US20220004362A1
Автор: LAMB Aaron Douglass
Принадлежит:

Certain aspects of the present disclosure are directed to methods and apparatus for circular floating point addition. An example method generally includes obtaining a first floating point number represented by a first significand and a first exponent, obtaining a second floating point number represented by a second significand and second exponent, and adding the first floating point number and the second floating point number using a circular accumulator device. 1. A circular accumulator device configured for performing floating point number addition , comprising: each adder device of the plurality of adder devices comprises at least a carry-in input, a carry-out output, a sum output, a first addend input, and a second addend input;', 'the plurality of adder devices comprises at least a first adder device, a last adder device, and a plurality of intermediate adder devices;', 'the plurality of intermediate adder devices are connected in series between the carry-out output of the first adder device and the carry-in input of the last adder device;', 'the carry-out output of the last adder device is coupled with the carry-in input of the first adder device forming a combinatorial loop;, 'a plurality of adder devices coupled in series, wherein each control device of the plurality of control devices comprises a carry-in input, a carry-out output, and a control signal input; and', 'at least one control device of the plurality of control devices is inserted in series between one or more pairs of adder devices of the plurality of adder devices; and, 'a plurality of control devices, wherein obtain a first floating point number represented by a first significand and a first exponent;', 'obtain a second floating point number represented by a second significand and second exponent;', 'shift the first significand based on the first exponent to generate a first circularly-shifted floating point number comprising a first plurality of bits; and', 'shift the second significand based ...

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Номер записи: 84
06-01-2022 дата публикации

PRODUCT-SUM CALCULATION UNIT, NEUROMORPHIC DEVICE, AND PRODUCT-SUM CALCULATION METHOD

Номер: US20220004853A1
Автор: SHIBATA Tatsuo
Принадлежит: TDK Corporation

A multiply-accumulate calculation device includes: a plurality of first multiple calculation elements configured to generate first output signals by multiplying a first input signal corresponding to an input value by a weight and output the first output signals; and an accumulate calculation unit configured to calculate a sum of the first output signals output from the plurality of first multiple calculation elements in a calculation period from a point in time at which transition to a steady state has occurred after transient responses caused by charging to parasitic capacitors of the plurality of first multiple calculation elements according to input of the first input signal to a point in time after transient responses caused by discharging from the parasitic capacitors of the plurality of first multiple calculation elements according to input of the first input signal have started to be generated. 1. A multiply-accumulate calculation device comprising:a plurality of first multiple calculation elements configured to generate first output signals by multiplying a first input signal corresponding to an input value by a weight and output the first output signals; andan accumulate calculation unit configured to calculate a sum of the first output signals output from the plurality of first multiple calculation elements in a calculation period from a point in time at which transition to a steady state has occurred after transient responses caused by charging to parasitic capacitors of the plurality of first multiple calculation elements according to input of the first input signal to a point in time after transient responses caused by discharging from the parasitic capacitors of the plurality of first multiple calculation elements according to input of the first input signal have started to be generated.2. The multiply-accumulate calculation device according to claim 1 , wherein each of the plurality of first multiple calculation elements is a variable resistance ...

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Номер записи: 85
06-01-2022 дата публикации

SYSTEMS AND METHODS FOR ELECTRONIC GAMING WITH TRIGGER CONDITIONS

Номер: US20220005313A1
Автор: Ching Erick, Decasa, JR. Rogelio, Mizzi Jennifer, Sanborn Hanna, Uss Jeffrey
Принадлежит:

In one aspect, an electronic gaming system is described. The electronic gaming system includes a display device, a random number generator (RNG), a player input interface, and a game controller configured to execute instructions stored in a tangible, non-transitory, computer-readable medium. When executed by the game controller, the instructions cause the game controller to at least determine, during play of a base game, that an enhancement trigger condition is satisfied and convert the symbol displayed on each position having one of the first frame and the second frame displayed thereon into a wild symbol. The instructions further cause the game controller to determine that a bonus game trigger condition is satisfied and convert a plurality of positions on each reel with at least one position having the second frame displayed thereon, into a bonus reel. The instructions also cause the game controller to generate a bonus game outcome. 1. An electronic gaming system comprising:at least one display device;a player input interface configured to receive player input from a player; determine, during play of a base game, that an enhancement trigger condition is satisfied, the enhancement trigger condition occurring when a frame is displayed on at least one position of a reel of a plurality of reels on the at least one display device;', 'convert a symbol displayed on each position having the frame displayed thereon into a wild symbol;', 'determine, upon completion of the base game, that a bonus game trigger condition is satisfied, the bonus game trigger condition occurring when the frame is displayed;', 'convert, upon activation of a bonus game, a plurality of positions on each reel with at least one position having the frame displayed thereon, into a bonus reel; and', 'generate a bonus game outcome, wherein the bonus game outcome is associated with a symbol displayed within each frame on each bonus reel and provides a contribution toward a target level of return to player ...

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Номер записи: 86
01-01-2015 дата публикации

RANDOM NUMBER GENERATOR

Номер: US20150005048A1
Автор: KAIBLINGER Harald, Schrötter Florian
Принадлежит: Novomatic AG

The present invention relates to a random number generator for the provision of a random number and/or a random number combination and/or random number matrix. According to invention the random number generator comprises a monitor apparatus Far monitoring at least one skill/skilled sport installation, on which a game of skill/skilled sport can be executed by at least one participant, which delivers at least one game outcome, wherein the monitoring apparatus comprises game outcome ascertainment means for the determination of the game outcome, and a determination apparatus for the determination of the winning number and/or winning number combination and/or winning number matrix from one or multiple determined game outcomes. 1. A random number generator for the provision of a random number and/or a random number combination and/or a random number matrix , comprising:a monitoring apparatus for monitoring a skill and/or skilled sport installation on which a game of skill and/or skilled sport which provides at least one game outcome can be executed by at least one participant, wherein the monitoring apparatus comprises a game outcome determination device for determining the game outcome; anda determination device for determining the random number and/or random number combination and/or random number matrix from the determined game outcome.2. The random number generator of claim 1 , wherein the skill and/or skilled sport installation is a skittle alley installation claim 1 , bowling alley installation claim 1 , dart stand or shooting gallery installation.3. The random number generator of claim 1 , wherein the determination device comprises a computation apparatus for the computation of a random number of numerical value out of multiple respective game outcomes in accordance with a specifiable calculation specification and/or an allocation apparatus for the allocation of the individual numerical values or the numbers calculated thereof to each number slot of the sequence of ...

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Номер записи: 87
07-01-2016 дата публикации

NON-ATOMIC SPLIT-PATH FUSED MULTIPLY-ACCUMULATE

Номер: US20160004504A1
Автор: ELMER THOMAS
Принадлежит:

A microprocessor performs a fused multiply-accumulate operation of a form ±A*B±C using first and second execution units. An input operand analyzer circuit determines whether values of A, B and/or C meet a sufficient condition to perform a joint accumulation of C with partial products of A and B. The first instruction execution unit multiplies A and B and jointly accumulates C to partial products of A and B when the values of A, B and/or C meet a sufficient condition to perform a joint accumulation of C with the partial products of A and B. The second instruction execution unit separately accumulates C to the products of A and B when the values of A, B and/or C do not meet a sufficient condition to perform a joint accumulation of C with the partial products of A and B. 1. A microprocessor operable to perform a fused multiply-accumulate operation of a form ±A*B±C , wherein A , B , and C are input operands , the microprocessor comprising:an input operand analyzer circuit that determines whether values of A, B and/or C meet a sufficient condition to perform a joint accumulation of C with partial products of A and B;a first instruction execution unit that multiplies A and B and jointly accumulates C to partial products of A and B when the values of A, B and/or C meet a sufficient condition to perform a joint accumulation of C with the partial products of A and B; anda second instruction execution unit that separately accumulates C to the products of A and B when the values of A, B and/or C do not meet a sufficient condition to perform a joint accumulation of C with the partial products of A and B.2. The microprocessor of claim 1 , wherein the first instruction execution unit is a multiplier operable to execute multiplication instructions and perform at least a first part of the fused multiply-accumulate operation.3. The microprocessor of claim 1 , wherein the second instruction execution unit is an adder operable to execute addition and subtraction instructions and ...

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Номер записи: 88
07-01-2016 дата публикации

TEMPORALLY SPLIT FUSED MULTIPLY-ACCUMULATE OPERATION

Номер: US20160004505A1
Автор: ELMER THOMAS
Принадлежит:

A microprocessor splits a fused multiply-accumulate operation of the form A*B+C into first and second multiply-accumulate sub-operations to be performed by a multiplier and an adder. The first sub-operation at least multiplies A and B, and conditionally also accumulates C to the partial products of A and B to generate an unrounded nonredundant sum. The unrounded nonredundant sum is stored in memory shared by the multiplier and adder for an indefinite time period, enabling the multiplier and adder to perform other operations unrelated to the multiply-accumulate operation. The second sub-operation conditionally accumulates C to the unrounded nonredundant sum if C is not already incorporated into the value, and then generates a final rounded result. 1. A method in a microprocessor for performing a fused multiply-accumulate operation of a form ±A*B±C , wherein A , B and C are input operands , and wherein no rounding occurs before C is accumulated to a product of A and B , the method comprising:splitting the fused multiply-accumulate operation into first and second multiply-accumulate sub-operations to be performed by one or more instruction execution units;in the first multiply-accumulate sub-operation, selecting whether to accumulate partial products of A and B with C, or to instead accumulate only the partial products of A and B, and to generate therefrom an unrounded nonredundant sum;in the second multiply-accumulate sub-operation, accumulating C with the unrounded nonredundant sum if the first multiply-accumulate sub-operation produced the unrounded nonredundant sum without accumulating C; andin the second multiply-accumulate sub-operation, generating a final rounded result of the fused multiply-accumulate operation.2. The method of claim 1 , wherein the unrounded nonredundant sum is provided immediately to the second multiply-accumulate sub-operation so that it can commence with minimal delay.3. The method of claim 1 , wherein the fused multiply-accumulate ...

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Номер записи: 89
07-01-2016 дата публикации

STANDARD FORMAT INTERMEDIATE RESULT

Номер: US20160004506A1
Автор: ELMER THOMAS
Принадлежит:

A microprocessor comprises an instruction pipeline, a shared memory, and first and second arithmetic processing units in the instruction pipeline, each capable of reading or receiving operands from and writing or providing results to the shared memory. The first arithmetic processing unit performs a first portion of a mathematical operation to produce an intermediate result vector that is not a complete, final result of the mathematical operation. The first arithmetic processing unit generates a plurality of non-architectural calculation control indicators that indicate how subsequent calculations to generate a final result from the intermediate result vector should proceed. The second arithmetic processing unit performs a second portion of the mathematical operation, in accordance with the calculation control indicators, to produce a complete, final result of the mathematical operation. 1. A microprocessor comprising:an instruction pipeline;a shared memory; andfirst and second arithmetic processing units in the instruction pipeline, each reading operands from and writing results to the shared memory;the first arithmetic processing unit performing a first portion of a mathematical operation to produce an intermediate result vector that is not a complete, final result of the mathematical operation;the first arithmetic processing unit generating a plurality of non-architectural calculation control indicators that indicate how subsequent calculations to generate a final result from the intermediate result vector should proceed; andthe second arithmetic processing unit performing a second portion of the mathematical operation, in accordance with the calculation control indicators, to produce a complete, final result of the mathematical operation.2. The microprocessor of claim 1 , wherein the intermediate result vector is an unrounded value and the complete claim 1 , final result is a rounded value.3. The microprocessor of claim 1 , wherein the mathematical operation is ...

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Номер записи: 90
07-01-2016 дата публикации

SPLIT-PATH HEURISTIC FOR PERFORMING A FUSED FMA OPERATION

Номер: US20160004507A1
Автор: ELMER THOMAS
Принадлежит:

A microprocessor performs a fused multiply-accumulate operation of a form ±A*B±C. An evaluation is made to detect whether values of A, B, and/or C meet a sufficient condition for performing a joint accumulation of C with partial products of A and B. If so, a joint accumulation of C is done with partial products of A and B and result of the joint accumulation is rounded. If not, then a primary accumulation is done of the partial products of A and B. This generates an unrounded non-redundant result of the primary accumulation. The unrounded result is then truncated to generate an unrounded non-redundant intermediate result vector that excludes one or more least significant bits of the unrounded non-redundant result. A secondary accumulation is then performed, adding or subtracting C to the unrounded non-redundant intermediate result vector. Finally, the result of the secondary accumulation is rounded. 1. A method in a microprocessor for performing a fused multiply-accumulate operation of a form ±A*B±C , where A , B and C are input operands , the method comprising:detecting whether values of A, B, and/or C meet a sufficient condition for performing a joint accumulation of C with partial products of A and B;if so, then performing a joint accumulation of C with partial products of A and B and rounding a result of the joint accumulation; andif not, then performing a primary accumulation of the partial products of A and B, generating an unrounded non-redundant result of the primary accumulation, excluding one or more least significant bits of the unrounded non-redundant result to generate a non-redundant intermediate result vector, performing a secondary accumulation of C to the unrounded non-redundant intermediate result vector, and rounding a result of the secondary accumulation.2. The method of claim 1 , wherein if A claim 1 , B and/or C meet a sufficient condition for performing a joint accumulation of C with partial products of A and B claim 1 , then reducing the ...

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Номер записи: 91
07-01-2016 дата публикации

SUBDIVISION OF A FUSED COMPOUND ARITHMETIC OPERATION

Номер: US20160004508A1
Автор: ELMER THOMAS
Принадлежит:

A microprocessor prepares a fused multiply-accumulate operation of a form ±A*B±C for execution by issuing first and second multiply-accumulate microinstructions to one or more instruction execution units to complete the fused multiply-accumulate operation. The first multiply-accumulate microinstruction causes an unrounded nonredundant result vector to be generated from a first accumulation of a selected one of (a) the partial products of A and B or (b) C with the partial products of A and B. The second multiply-accumulate microinstruction causes performance of a second accumulation of C with the unrounded nonredundant result vector, if the first accumulation did not include C. The second multiply-accumulate microinstruction also causes a final rounded result to be generated from the unrounded nonredundant result vector, wherein the final rounded result is a complete result of the fused multiply-accumulate operation. 1. A method in a microprocessor for preparing for execution of a fused multiply-accumulate operation of a form ±A*B±C , wherein A , B and C are input operands , and wherein no rounding occurs before C is accumulated to a product of A and B , the method comprising:issuing first and second multiply-accumulate microinstructions to one or more instruction execution units to complete the fused multiply-accumulate operation;wherein the first multiply-accumulate microinstruction causes an unrounded nonredundant result vector to be generated from a first accumulation of a selected one of (a) the partial products of A and B or (b) C with the partial products of A and B;wherein the second multiply-accumulate microinstruction causes performance of a second accumulation of C with the unrounded nonredundant result vector, if the first accumulation did not include C; andwherein the second multiply-accumulate microinstruction also causes a final rounded result to be generated from the unrounded nonredundant result vector, wherein the final rounded result is a complete ...

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Номер записи: 92
07-01-2016 дата публикации

RANDOM NUMBER GENERATOR

Номер: US20160004510A1
Автор: FISCHER Viktor, HADDAD Patrick
Принадлежит:

An integrated random signal generation circuit includes two logic gates, the output of each gate coupled to a respective first input of the other gate via assemblies of delay elements. The respective delays introduced by the assemblies of delay elements are adjustable. 1. An integrated random signal generation circuit comprising:a plurality of delay element assemblies, each delay element assembly having an adjustable delay;a first logic gate having a first input, a second input, and an output;a second logic gate having a first input, a second input, and an output, the output of the first logic gate coupled through at least one first delay element assembly of the plurality of delay element assemblies to the first input of the second logic gate, the output of the second logic gate coupled through at least one second delay element assembly of the plurality of delay element assemblies to the first input of the first logic gate.2. The integrated random signal generation circuit of claim 1 , wherein each delay element assembly comprises:a first sub-assembly configured to provide a non-adjustable delay; anda second sub-assembly configured to provide an adjustable delay.3. The integrated random signal generation circuit of claim 2 , wherein each second sub-assembly comprises:a plurality of groups of series-connected delay elements, each one of the groups of series-connected delay elements having a different number of delay elements coupled in series.4. The integrated random signal generation circuit of claim 2 , wherein each second sub-assembly comprises:groups connected in parallel of delay elements, each group having a delay different from another group of the same sub-assembly, the adjustment of the introduced delay being obtained by the selection of the group conveying the signal a plurality of series-connected delay elements, each one of the plurality of series-connected delay elements coupled in parallel with the other ones of the plurality of series connected delay ...

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Номер записи: 93
04-01-2018 дата публикации

INJECTING CPU TIME JITTER TO IMPROVE ENTROPY QUALITY FOR RANDOM NUMBER GENERATOR

Номер: US20180004486A1
Автор: Sweeny James W., Visegrady Tamas
Принадлежит:

Aspects of present disclosure relate to random number generator, a method and a computer program product of improving entropy quality of the random number generator. The method may include: receiving, at an input/output interface module of the random number generator, a request to generate a random number having a predetermined number of random bits, and starting a random bit generating loop to generate each of the random bits of the random number to be generated. In certain embodiments, random bit generating loop may include: incorporating a CPU_Time as a randomness factor in generating random number to improve entropy quality, including non-deterministic memory-subsystem latencies in entropy extraction, such as those introduced by unpredictable cache movements, generating a Candidate_Bit by using a Clock_Time, and generating a random bit for random number by using a von Neumann unbiasing analysis module, until every random bits of the random number is generated. 1. A random number generator comprising:an input/output interface module configured to receive, from a requester, a request to generate a random number having a plurality of random bits, initiate a random bit generating loop to generate each of the plurality of random bits, and transmit the random number generated to the requester;a CPU time extraction module configured to extract a CPU time from a central processing unit (CPU) clock of a CPU of a computer;a clock time extraction module configured to extract a clock time from the CPU clock;a jitter collection module configured to accumulate non-predictable time differences by observing a latency of multiple operations and inducing a cache-related non-determinism by purging a CPU cache; anda von Neumann unbiasing analysis module configured to perform a von Neumann unbiasing analysis and to generate the plurality of random bits for the random number.2. The random number generator of claim 1 , wherein the clock time comprises a real time clock of the CPU for ...

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Номер записи: 94
07-01-2021 дата публикации

PREPARE FOR SHORTER PRECISION (ROUND FOR REROUND) MODE IN A DECIMAL FLOATING-POINT INSTRUCTION

Номер: US20210004206A1
Автор: Schmookler Martin Stanley, Schwarz Eric Mark
Принадлежит:

An instruction is executed in round-for-reround mode wherein the permissible resultant value that is closest to and no greater in magnitude than the infinitely precise result is selected. If the selected value is not exact and the units digit of the selected value is either 0 or 5, then the digit is incremented by one and the selected value is delivered. In all other cases, the selected value is delivered. 1. A computer implemented method for indicating with any least significant decimal coefficient digit of 0 or 5 that a result of a rounding of a decimal floating-point (DFP) number to a lesser precision in a computer processor is an exact (precise) result , the method comprising:executing, by the computer processor, a DFP round-for-reround instruction in a round-for-reround mode, wherein the DFP round-for-reround instruction is configured to perform a DFP operation on a DFP operand, the executing the DFP round-for-reround instruction comprising:based on being in the round-for-reround mode, forming, by the computer processor, from a decimal coefficient number having a high order portion and a low order portion, an intermediate result from the high order portion, wherein the intermediate result has a least significant decimal coefficient digit; 'based on the least significant coefficient digit of the intermediate result being 0 or 5 and based on the low order portion having any value other than 0, incrementing the least significant coefficient digit of the intermediate result; and', 'without changing any coefficient digit of the intermediate result, other than the least significant decimal coefficient digit, creating from the intermediate result a rounded-for-reround DFP number, the creating comprisingstoring in computer processor storage, by the computer processor, the intermediate result as a final result of the executed DFP operation, wherein the intermediate result is the rounded-for-reround DFP number, wherein a final result having a least significant digit of 0 ...

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Номер записи: 95
07-01-2021 дата публикации

TRIGONOMETRIC FUNCTION CALCULATING DEVICE

Номер: US20210004207A1
Автор: MARUYAMA HIROFUMI, YAMAZAKI Masato
Принадлежит:

A trigonometric function calculating device includes: an address generator that generates an address signal that is formed from plural bit strings and corresponds to a phase; a trigonometric function table that stores first sines and first cosines that respectively correspond to phases expressed by upper bits of the address signals, and second sines and a second cosines that respectively correspond to phases expressed by lower bits of the address signals; a calculation circuit that outputs, as a calculated value, a sine that corresponds to the address signal by calculating processing using the first sine, the first cosine, the second sine and the second cosine that correspond to the address signal and have been extracted by referring to the trigonometric function table; and a correcting section that corrects the calculated value on the basis of a correction value corresponding to the address signal. 1. A trigonometric function calculating device comprising at least one processor and at least one memory , wherein:the at least one processor is configured to generate an address signal that is formed from a plurality of bit strings and that corresponds to a phase;the at least one memory stores a trigonometric function table that includes first sines and first cosines that respectively correspond to phases expressed by upper bits of the address signals, and second sines and second cosines that respectively correspond to phases expressed by lower bits of the address signals;the at least one processor is configured to output, as a calculated value, a sine that corresponds to the address signal by calculating processing using the first sine, the first cosine, the second sine and the second cosine that correspond to the address signal and have been extracted by referring to the trigonometric function table; andthe at least one processor is configured to correct the calculated value on the basis of a correction value that corresponds to the address signal.2. The trigonometric ...

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Номер записи: 96
07-01-2021 дата публикации

COUNTER BASED MULTIPLY-AND-ACCUMULATE CIRCUIT FOR NEURAL NETWORK

Номер: US20210004208A1
Автор: CHUANG Pierce I-Jen, LAI Liangzhen
Принадлежит: Facebook Technologies, LLC

Disclosed herein includes a system, a method, and a device for improving computation efficiency of a neural network. In one aspect, adder circuitry is configured to add input data from processing of the neural network and a first number of bits of accumulated data for the neural network to generate summation data. In one aspect, according to a carry value of the adding from the adder circuitry, a multiplexer is configured to select between i) a second number of bits of the accumulated data and ii) incremented data comprising the second number of bits of the accumulated data incremented by a predetermined value. The summation data appended with the selected one of the second number of bits of the accumulated data or the incremented data may form appended data. 1. A multiply and accumulate circuit for a neural network comprising:adder circuitry configured to generate summation data by adding input data from processing of the neural network and a first number of bits of accumulated data for the neural network; anda multiplexer configured to select, according to a carry value of the adding by the adder circuitry, between i) a second number of bits of the accumulated data and ii) incremented data comprising the second number of bits of the accumulated data incremented by a predetermined value, the summation data appended with the selected one of the second number of bits of the accumulated data or the incremented data forming appended data.2. The multiply and accumulate circuit of claim 1 , wherein the multiplexer is configured to select the second number of bits of the accumulated data claim 1 , in response to the carry value of the adding being zero.3. The multiply and accumulate circuit of claim 1 , wherein the multiplexer is configured to select the incremented data claim 1 , in response to the carry value of the adding being one.4. The multiply and accumulate circuit of claim 1 , wherein the adder circuitry is configured to provide the first number of bits of the ...

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Номер записи: 97
02-01-2020 дата публикации

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND COMPUTER READABLE MEDIUM

Номер: US20200004503A1
Автор: FUNATSUKI Masahiro, Minegishi Noriyuki, TAKEUCHI Tomomi
Принадлежит: Mitsubishi Electric Corporation

A database stores interface transfer capacity information in which calculation formulas for calculation of a data transfer capacity are described, correspondingly to types of interface circuits. A transfer time evaluation unit acquires a calculation formula corresponding to a type of a specified interface circuit which has been specified from among a plurality of interface circuits as an interface circuit to connect a plurality of arithmetic operational devices among which execution of a plurality of arithmetic operation processes is divided, from the interface transfer capacity information, and calculates the data transfer capacity of the specified interface circuit by using the acquired calculation formula. 1. An information processing device comprising:a storage device to store interface transfer capacity information in which calculation formulas for calculation of a data transfer capacity are described, correspondingly to types of interface circuits; andprocessing circuitry to acquire a calculation formula corresponding to a type of a specified interface circuit which has been specified from among a plurality of interface circuits as an interface circuit to connect a plurality of arithmetic operational devices among which execution of a plurality of arithmetic operation processes is divided, from the interface transfer capacity information, and to calculate the data transfer capacity of the specified interface circuit by using the acquired calculation formula.2. The information processing device according to claim 1 , whereinthe storage device stores the interface transfer capacity information in which the calculation formulas are described, correspondingly to combinations of the types of the interface circuits and types of the arithmetic operational devices, andthe processing circuitry acquires a calculation formula corresponding to a combination of the type of the specified interface circuit and a type of an arithmetic operational device among the plurality of ...

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Номер записи: 98
02-01-2020 дата публикации

Internet-enabled audio visual graphing calculator

Номер: US20200004504A1
Автор: Eli A. Luberoff, Jennifer M. Wales, Stephen A. Clower
Принадлежит: Desmos Inc

A method of graphically representing mathematical expressions in both audio and visual formats on a user device is described. Embodiments of the present invention include an Internet-enabled audio-visual graphing calculator that receives input from a user device in at least one of at least one of audio, visual, or Braille formats. An embodiment of the present invention interprets input received from the user device as a typeset mathematical expression, parses the typeset mathematical expression into an interpreted mathematical expression and compiles the interpreted mathematical expression into an evaluation function. At least one point is sampled on the evaluation function. The sampled evaluation function is rendered as a graph on a visual display of a user device. In an embodiment of the invention, an audible representation of the rendered graph is generated for playback on the user device.

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Номер записи: 99
07-01-2021 дата публикации

CALCULATING DEVICE

Номер: US20210004238A1
Автор: GOTO Hayato, TATSUMURA Kosuke
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to one embodiment, a calculating device includes a first memory, a second memory, a third memory, a first arithmetic module, a second arithmetic module, a first conductive line electrically connecting a first output terminal of the first memory and a first input terminal of the first arithmetic module, a second conductive line electrically connecting a second output terminal of the first memory and a first input terminal of the second arithmetic module, a third conductive line electrically connecting a first output terminal of the second memory and a second input terminal of the second arithmetic module, a fourth conductive line electrically connecting a first output terminal of the third memory and a third input terminal of the second arithmetic module, and a fifth conductive line electrically connecting a first output terminal of the second arithmetic module and a second input terminal of the first arithmetic module. 116-. (canceled)17. A calculating device , comprising:a first memory;a second memory;a third memory;a first arithmetic module; anda second arithmetic module,whereinthe first memory stores a first variable group {x},the second memory stores a second variable group {y},the third memory stores a first parameter group {J},the first variable group {x} includes N (N being an integer of 2 or more) ith entries of a first variable xi (i being an integer not less than 1 and not more than N),the second variable group {y} includes N ith entries of a second variable yi (i being an integer not less than 1 and not more than N),{'sub': 'l,m', 'the first parameter group {J} includes N×N first parameters J(l being an integer not less than 1 and not more than N, and m being an integer not less than 1 and not more than N),'}the first arithmetic module update the ith entry of the first variable xi based on the ith entry of the second variable yi,the second arithmetic module update the ith entry of the second variable yi based on at least at least a part of the ...

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Номер записи: 100