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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 18417. Отображено 100.
05-01-2012 дата публикации

Methods, structures, and devices for reducing operational energy in phase change memory

Номер: US20120002465A1
Автор: Roy E. Meade
Принадлежит: Micron Technology Inc

Methods of forming and operating phase change memory devices include adjusting an activation energy barrier between a metastable phase and a stable phase of a phase change material in a memory cell. In some embodiments, the activation energy barrier is adjusted by applying stress to the phase change material in the memory cell. Memory devices include a phase change memory cell and a material, structure, or device for applying stress to the phase change material in the memory cell. In some embodiments, a piezoelectric device may be used to apply stress to the phase change material. In additional embodiments, a material having a thermal expansion coefficient greater than that of the phase change material may be positioned to apply stress to the phase change material.

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Номер записи: 1
26-01-2012 дата публикации

Non-Volatile Memory Element And Memory Device Including The Same

Номер: US20120018695A1
Автор: Chang-Bum Lee, Chang-Jung Kim, Dong-Soo Lee, Ji-hyun Hur, Man Chang, Myoung-Jae Lee, Seung-Ryul Lee, Young-Bae Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Example embodiments, relate to a non-volatile memory element and a memory device including the same. The non-volatile memory element may include a memory layer having a multi-layered structure between two electrodes. The memory layer may include first and second material layers and may show a resistance change characteristic due to movement of ionic species therebetween. The first material layer may be an oxygen-supplying layer. The second material layer may be an oxide layer having a multi-trap level.

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Номер записи: 2
02-02-2012 дата публикации

Memory resistor having plural different active materials

Номер: US20120026776A1
Автор: Jianhua Yang, Minxian Max Zhang, R. Stanley Williams
Принадлежит: Hewlett Packard Development Co LP

Methods and means related to memory resistors are provided. A memristor includes at least two different active materials disposed between a pair of electrodes. The active materials are selected to exhibit respective and opposite changes in electrical resistance in response to changes in oxygen ion content. The active materials are subject to oxygen ion reconfiguration under the influence of an applied electric field. An electrical resistance of the memristor is thus adjustable by way of applied programming voltages and is non-volatile between programming events.

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Номер записи: 3
09-02-2012 дата публикации

Semiconductor device and method for driving semiconductor device

Номер: US20120033505A1
Автор: Kiyoshi Kato, Yusuke Sekine
Принадлежит: Semiconductor Energy Laboratory Co Ltd

A semiconductor device with a novel structure is provided, in which the operation voltage is reduced or the storage capacity is increased by reducing variation in the threshold voltages of memory cells after writing. The semiconductor device includes a plurality of memory cells each including a transistor including an oxide semiconductor and a transistor including a material other than an oxide semiconductor, a driver circuit that drives the plurality of memory cells, and a potential generating circuit that generates a plurality of potentials supplied to the driver circuit. The driver circuit includes a data buffer, a writing circuit that writes one potential of the plurality of potentials into each of the plurality of memory cells as data, a reading circuit that reads the data written into the memory cells, and a verifying circuit that verifies whether the read data agrees with data held in the data buffer or not.

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Номер записи: 4
16-02-2012 дата публикации

Method and apparatus for optically reading information

Номер: US20120037698A9
Автор: Torsten Hupe, uml e+ee lkening Stephan V+e
Принадлежит: BAYER INNOVATION GMBH

The present invention relates to a novel type of information carrier, on which information is stored in the form of diffraction structures. The information carrier according to the invention can be read by being drawn manually through a reading device. The present invention also relates to a device with which an information carrier according to the invention can be read.

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Номер записи: 5
16-02-2012 дата публикации

Semiconductor memory device

Номер: US20120039110A1
Автор: Hiroshi Maejima, Koji Hosono
Принадлежит: Toshiba Corp

A memory-cell array that includes a first line, a second line intersecting the first line, and a memory cell including a variable resistive element provided in the intersection of the first and the second lines; a data-write unit configured to apply a voltage pulse to the memory cell through the first and the second lines, the voltage pulse to set and/or reset data; and a detector unit configured to compare a cell current that flows through the memory cell by the voltage pulse at the time of setting and/or resetting the data with a reference current generated from the initial value of the cell current, and to control the data-write unit in accordance with a result of comparison.

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Номер записи: 6
16-02-2012 дата публикации

Destruction of data stored in phase change memory

Номер: US20120039117A1
Автор: Gary Edward Webb
Принадлежит: Individual

A mechanism and means by which the data information pattern stored in Phase Change Memory PCM ( 21 ) can be quickly destroyed and made unreadable upon the receipt of a destruction stimuli( 11 ) by the application of a targeted thermal heat source generated by an internal integrated thermal heater ( 26 ), a heat source mounted under the PCM ( 28 ), on top of the PCM ( 29 ), within the PCB ( 30 ), or an externally generated heat source ( 27 ). Such an operation is non-destructive and while the stored data is rendered unreadable, the physical PCM device is unharmed and can be used again.

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Номер записи: 7
23-02-2012 дата публикации

Memory devices using a plurality of diodes as program selectors for memory cells

Номер: US20120044736A1
Автор: Shine C. Chung
Принадлежит: Chung Shine C

At least one junction diode fabricated in standard CMOS logic processes can be used as program selectors for the memory cells that can be programmed based on the directions of current flow. These memory cells are MRAM, RRAM, CBRAM, or other memory cells that have a resistive element coupled to the P terminal of the first diode and to the N terminal of a second diode. The diodes can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diodes. By applying a high voltage to a resistive element and switching the N terminal of the first diode to a low voltage while disabling the second diode, a current flows through the memory cell can change the resistance into one state. Similarly, by applying a low voltage to a resistive element and switching the P terminal of the second diode to a high voltage while disabling the first diode, a current flows through the memory cell can change the resistance into another state. The P+ active region of the diode can be isolated from the N+ active region in an N well by using dummy MOS gate, SBL, or STI isolations.

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Номер записи: 8
23-02-2012 дата публикации

One-time programmable memories using polysilicon diodes as program selectors

Номер: US20120044738A1
Автор: Shine C. Chung
Принадлежит: Chung Shine C

Polysilicon diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, using electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse etc. as OTP element The diode can be constructed by P+/N+ implants on a polysilicon as a program selector. The OTP device has an OTP element coupled to a polysilicon diode. The OTP devices can be used to construct a two-dimensional OTP memory with the N-terminals of the diodes in a row connected as a wordline and the OTP elements in a column connected as a bitline. By applying a high voltage between a selected bitline and a selected wordline to turn on a diode in a selected cell for suitable duration of time, a current flows through an OTP element may change the resistance state. The cell data in the OTP memory can also be read by turning on a selected wordline and to couple a selected bitline to a sense amplifier. The wordlines may have high-resistivity local wordlines coupled to low-resistivity global wordlines through conductive contact(s) or via(s).

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Номер записи: 9
23-02-2012 дата публикации

Reversible resistive memory using diodes formed in cmos processes as program selectors

Номер: US20120044747A1
Автор: Shine C. Chung
Принадлежит: Chung Shine C

Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for reversible resistive memory cells that can be programmed based on magnitude, duration, voltage-limit, or current-limit of a supply voltage or current. These cells are PCM, RRAM, CBRAM, or other memory cells that have a reversible resistive element coupled to a diode. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. The memory cells can be used to construct a two-dimensional memory array with the N terminals of the diodes in a row connected as a wordline and the reversible resistive elements in a column connected as a bitline. By applying a voltage or a current to a selected bitline and to a selected wordline to turn on the diode, a selected cell can be programmed into different states reversibly based on magnitude, duration, voltage-limit, or current-limit. The data in the reversible resistive memory can also be read by turning on a selected wordline to couple a selected bitline to a sense amplifier. The wordlines may have high-resistivity local wordlines coupled to low-resistive global wordlines through conductive contact(s) or via(s).

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Номер записи: 10
23-02-2012 дата публикации

Variable resistance nonvolatile storage device and method of forming memory cell

Номер: US20120044749A1
Автор: Kazuhiko Shimakawa, Shunsaku Muraoka, Takeshi Takagi, Yoshihiko Kanzawa
Принадлежит: Panasonic Corp

A variable resistance nonvolatile storage device which includes (i) a semiconductor substrate ( 301 ), (ii) a variable resistance element ( 309 ) having: lower and upper electrodes ( 309 a, 309 c ); and a variable resistance layer ( 309 b ) whose resistance value reversibly varies based on voltage signals each of which has a different polarity and is applied between the electrodes ( 309 a, 309 c ), and (iii) a MOS transistor ( 317 ) formed on the substrate ( 301 ), wherein the variable resistance layer ( 309 b ) includes: oxygen-deficient transition metal oxide layers ( 309 b - 1, 309 b - 2 ) having compositions MO x and MO y (where x<y) and in contact with the electrodes ( 309 a, 309 c ) respectively, and a diffusion layer region ( 302 b ) is connected with the lower electrode ( 309 a ) to form a memory cell ( 300 ), the region ( 302 b ) serving as a drain of the transistor ( 317 ) upon application of a voltage signal which causes a resistance change to high resistance state in the variable resistance layer ( 309 b ).

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Номер записи: 11
23-02-2012 дата публикации

Programmably reversible resistive device cells using cmos logic processes

Номер: US20120044753A1
Автор: Shine C. Chung
Принадлежит: Chung Shine C

Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for reversible resistive devices, such as PCM, RRAM, CBRAM, or other memory cells. The reversible resistive devices have a reversible resistive element coupled to a diode. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a voltage or a current between a reversible resistive element and the N terminal of a diode, the reversible resistive device can be programmed into different states based on magnitude, duration, voltage-limit, or current-limit in a reversible manner. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI/LOCOS isolations.

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Номер записи: 12
01-03-2012 дата публикации

Non-volatile memory device

Номер: US20120051170A1
Автор: Dong Keun Kim, Jung Hyuk YOON
Принадлежит: Hynix Semiconductor Inc

A non-volatile memory device includes a cell array configured to read or write data, a local column switch configured to selectively connect a bit line of the cell array to a global bit line in response to a column selection signal, a global column switch configured to selectively connect the global bit line to a sense-amp in response to an enable signal, and a switching unit configured to selectively connect or sever a current path of the global column switch in response to a control signal corresponding to a bank active operation.

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Номер записи: 13
08-03-2012 дата публикации

Semiconductor memory apparatus and method for controlling programming current pulse

Номер: US20120057417A1
Автор: Yong Bok An
Принадлежит: Hynix Semiconductor Inc

A semiconductor memory apparatus includes a write control code generation unit configured to generate a write control code which is updated at each pulsing timing of an external test pulse signal applied through a pad; and a data write unit configured to output a programming current pulse which has a magnitude corresponding to the code value of the write control code.

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Номер записи: 14
15-03-2012 дата публикации

Multi-level resistance change memory

Номер: US20120063193A1
Автор: Reika Ichihara
Принадлежит: Individual

According to one embodiment, a multi-level resistance change memory includes a memory cell includes first and second resistance change films connected in series, and a capacitor connected in parallel to the first resistance change film, a voltage pulse generating circuit generating a first voltage pulse with a first pulse width to divide a voltage of the first voltage pulse into the first and second resistance change films based on a resistance ratio thereof, and generating a second voltage pulse with a second pulse width shorter than the first pulse width to apply a voltage of the second voltage pulse to the second resistance change film by a transient response of the capacitor, and a control circuit which is stored multi-level data to the memory cell by using the first and second voltage pulses in a writing.

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Номер записи: 15
22-03-2012 дата публикации

Reactive metal implated oxide based memory

Номер: US20120069624A1
Автор: D.V. Nirmal Ramaswamy, Gurtej S. Sandhu
Принадлежит: Micron Technology Inc

Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming an oxide over the first conductive element, implanting a reactive metal into the oxide, and forming a second conductive element over the oxide.

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Номер записи: 16
22-03-2012 дата публикации

Nonvolatile semiconductor memory device

Номер: US20120069627A1
Автор: Hiroshi Kanno, Mitsuru Sato, Natsuki Kikuchi, Takafumi SHIMOTORI, Takayuki Tsukamoto, Yoichi MINEMURA
Принадлежит: Toshiba Corp

A nonvolatile semiconductor memory device includes: a memory cell array including plural first lines, plural second lines, and plural memory cells each including a variable resistance element; a first decoder connected to at least one ends of the plurality of first lines and configured to select at least one of the first lines; at least one pair of second decoders connected to both ends of the plurality of second lines and configured such that one of the pair of second decoders is selected for selecting the second lines according to a distance between the one of the first lines selected by the first decoder and the both ends of the second lines; and a voltage application circuit configured to apply a certain voltage between the first line and the second line selected by the first decoder and the second decoder.

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Номер записи: 17
29-03-2012 дата публикации

Resistor structure for a non-volatile memory device and method

Номер: US20120075907A1
Автор: Sung Hyun Jo
Принадлежит: Crossbar Inc

A non-volatile resistive switching memory device. The device includes a first electrode, a second electrode, a switching material in direct contact with a metal region of the second electrode, and a resistive material disposed between the second electrode and the switching material. The resistive material has an ohmic characteristic and a resistance substantially the same as an on state resistance of the switching device. The resistive material allows for a change in a resistance of the switching material upon application of voltage pulse without time delay and free of a reverse bias after the voltage pulse. The first voltage pulse causes a programming current to flow from the second electrode to the first electrode. The resistive material further causes the programming current to be no greater than a predetermined value.

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Номер записи: 18
29-03-2012 дата публикации

Resistive Random Access Memory and Verifying Method Thereof

Номер: US20120075908A1
Автор: Chih-He Lin, Pei-Chia Chiang, Shyh-Shyuan Sheu, Wen-Pin Lin
Принадлежит: Industrial Technology Research Institute ITRI

A resistive random access memory (RRAM) and a verifying method thereof are provided. The RRAM comprises at least one resistive memory cell. The resistive memory cell comprises a resistive memory element and a transistor, wherein one terminal of the resistive memory element is coupled to a first terminal of the transistor. The verifying method comprises the following steps: Whether the resistive memory cell passes verification is determined. During a first time period and under the circumstance that the resistive memory cell fails to pass verification, a reference voltage is applied to the other terminal of the resistive memory element and a voltage pulse is applied to a second terminal of the transistor according to a voltage signal to write a reverse voltage to the resistive memory cell.

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Номер записи: 19
29-03-2012 дата публикации

Phase change memory state determination using threshold edge detection

Номер: US20120075923A1
Автор: Aswin Thiruvengadam
Принадлежит: Numonyx BV Amsterdam Rolle Branch

Subject matter disclosed herein relates to techniques to read a memory cell that involve a threshold edge phenomenon of a reset state of phase change memory.

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Номер записи: 20
05-04-2012 дата публикации

Phase change memory apparatus having row control cell

Номер: US20120081954A1
Автор: Kyoung Wook Park
Принадлежит: Hynix Semiconductor Inc

A semiconductor integrated circuit includes a phase change memory apparatus includes a plurality of row control cells and a plurality of phase change memory cells formed on the row control cells while being electrically connected to the row control cells. The plurality of row control cells and the plurality of phase change memory cells are vertically stacked in a cell array area.

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Номер записи: 21
19-04-2012 дата публикации

Non-volatile memory device and methods for manufacturing the same

Номер: US20120091424A1
Автор: Chrong-Jung Lin, Ya-Chin King
Принадлежит: Individual

A variable and reversible resistive element includes a transition metal oxide layer, a bottom electrode and at least one conductive plug module. The bottom electrode is disposed under the transition metal oxide layer. The conductive plug module is disposed on the transition metal oxide layer. The conductive plug module includes a metal plug and a barrier layer. The conductive plug is electrically connected with the transition metal oxide layer. The barrier layer surrounds the metal plug, wherein the transition metal oxide layer is made by reacting a portion of a dielectric layer being directly below the metal plug and a portion of the barrier layer contacting the portion of the dielectric layer, wherein the dielectric layer is formed on the bottom electrode. Moreover, a non-volatile memory device and methods for operating and manufacturing the same is disclosed in specification.

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Номер записи: 22
19-04-2012 дата публикации

Resistive Memory Element and Use Thereof

Номер: US20120092920A1
Автор: Sakyo Hirose
Принадлежит: Murata Manufacturing Co Ltd

A resistive memory element that includes an element body and at least a pair of electrodes opposed to each other with at least a portion of the element body interposed therebetween. The element body is made of an oxide semiconductor which has a composition represented by the general formula: (Ba 1-x Sr x )Ti 1-y M y O 3 (wherein M is at least one from among Mn, Fe, and Co; 0≦x≦1.0; and 0.005≦y≦0.05). The first electrode of the pair of electrodes is made of a material which can form a Schottky barrier which can develop a rectifying property and resistance change characteristics in an interface region between the first electrode and the element body. The second electrode is made of a material which provides a more ohmic junction to the element body as compared with the first electrode.

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Номер записи: 23
26-04-2012 дата публикации

Cross point variable resistance nonvolatile memory device

Номер: US20120099367A1
Автор: Kazuhiko Shimakawa, Ryotaro Azuma
Принадлежит: Panasonic Corp

A cross point variable resistance nonvolatile memory device includes memory cells having the same orientation for stable characteristics of all layers. Each memory cell ( 51 ) is placed at a different one of cross points of bit lines ( 53 ) in an X direction and word lines ( 52 ) in a Y direction formed in layers. In a multilayer cross point structure where vertical array planes sharing the word lines are aligned in the Y direction each for a group of bit lines aligned in a Z direction, even and odd layer bit line selection switch elements ( 57, 58 ) switch electrical connection and disconnection between a global bit line ( 56 ) and commonly-connected even layer bit lines and commonly-connected odd layer bit lines, respectively. A bidirectional current limiting circuit ( 92 ) having parallel-connected P-type current limiting element ( 91 ) and N-type current limiting element ( 90 ) is provided between the global bit line and the switch elements.

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Номер записи: 24
03-05-2012 дата публикации

Phase-change memory device

Номер: US20120106244A1
Автор: Ki-won Lim, Won-ryul Chung, Young-Ran Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A phase-change memory device and its firing method are provided. The firing method of the phase-change memory device includes applying a writing current to phase-change memory cells, identifying a state of the phase-change memory cells after applying the writing current, and applying a firing current, in which an additional current is added to the writing current, to the phase-change memory cells in accordance with the state.

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Номер записи: 25
17-05-2012 дата публикации

Phase change memory device

Номер: US20120120724A1
Автор: Hyuck-Soo Yoon
Принадлежит: Individual

A phase change memory device includes a signal generator configured to generate first and second sensing and amplifying enable signals which are sequentially activated during an activation period of a word line selection signal and each of which has a certain activation period length, a resistance sensor configured to sense a resistance value by applying a certain operation current to a phase change memory cell corresponding to the word line selection signal during an activation period of the first sensing and amplifying enable signal and a voltage level amplifier configured to logically determine a voltage level of the resistance sensing signal based on a voltage level of a logic reference signal during an activation period of the second sensing.

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Номер записи: 26
24-05-2012 дата публикации

Memory resistor adjustment using feedback control

Номер: US20120127780A1
Автор: Gilberto Ribeiro, Jianhua Yang, John Paul Strachan, Julien Borghetti, Matthew D. Pickett
Принадлежит: Hewlett Packard Development Co LP

Apparatus and methods related to memory resistors are provided. A feedback controller applies adjustment signals to a memristor. A non-volatile electrical resistance of the memristor is sensed by the feedback controller during the adjustment. The memristor is adjusted to particular values lying between first and second limiting values with minimal overshoot. Increased memristor service life, faster operation, lower power consumption, and higher operational integrity are achieved by the present teachings.

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Номер записи: 27
14-06-2012 дата публикации

Programming reversible resistance switching elements

Номер: US20120147657A1
Автор: Deepak C. Sekar, Klaus Schuegraf, Roy Scheuerlein
Принадлежит: SanDisk 3D LLC

A storage system and method for operating the storage system that uses reversible resistance-switching elements is described. Techniques are disclosed herein for varying programming conditions to account for different resistances that memory cells have. These techniques can program memory cells in fewer attempts, which can save time and/or power. Techniques are disclosed herein for achieving a high programming bandwidth while reducing the worst case current and/or power consumption.

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Номер записи: 28
19-07-2012 дата публикации

Memory unit and method of operating the same

Номер: US20120182785A1
Автор: Wataru Otsuka
Принадлежит: Sony Corp

A memory unit includes memory cells each having a memory element and a transistor, word lines and first and second bit lines, and a drive section. In performing setting operation for a first memory element located on one word line and in performing resetting operation for a second memory element located on the one word line, the drive section applies a given word line electric potential to the one word line, and sets an electric potential of a bit line on a lower electric potential side out of the first and the second bit lines corresponding to the first memory element to a value higher than a value of an electric potential of a bit line on the lower electric potential side corresponding to the second memory element by an amount of given electric potential difference.

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Номер записи: 29
23-08-2012 дата публикации

Memory apparatus

Номер: US20120212994A1
Автор: Chieko Nakashima, Hiroshi Yoshihara, Kentaro Ogata, Makoto Kitagawa, Tomohito Tsushima, Tsunenori Shiimoto
Принадлежит: Sony Corp

A memory apparatus includes: a plurality of memory cells which includes a first resistance change element; and a read-out circuit which determines the size of a resistance value of the first resistance change element by comparing the resistance state of a memory cell selected among the plurality of memory cells to the resistance state of a reference memory cell, wherein the reference memory cell includes a second resistance change element, a resistance value of the second resistance change element with respect to an applied voltage is smaller than that in a high resistance state of the first resistance change element, and the second resistance change element shows the same resistance change characteristic as the first resistance change element.

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Номер записи: 30
30-08-2012 дата публикации

Write bandwidth in a memory characterized by a variable write time

Номер: US20120218814A1
Автор: John A. Bivens, Luis A. Lastras-Montano, Michele M. Franceschini
Принадлежит: International Business Machines Corp

A memory system that includes a plurality of memory arrays having memory cells characterized by a variable write time. The memory system also includes a memory bus configured to receive write commands, and a plurality of data buffers configured to communicate with the memory arrays. The memory system further includes an address buffer configured to communicate with the memory arrays to store the write addresses. A mechanism configured to receive a write command and to split a data line received with the write command into a number of parts is also included in the memory system. The parts of the data line are stored in different data buffers and the writing of the parts of the data line to memory arrays at the write address is initiated. The write command is completed when write completion signals specifying the write address have been received from all of the memory arrays.

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Номер записи: 31
06-09-2012 дата публикации

Three dimensional memory system with intelligent select circuit

Номер: US20120224410A1
Автор: Tianhong Yan
Принадлежит: SanDisk 3D LLC

A three dimensional monolithic memory array of non-volatile storage elements includes a plurality of word lines and a plurality of bit lines. The plurality of bit lines are grouped into columns. Performing memory operation on the non-volatile storage elements includes selectively connecting bit lines to sense amplifiers using selection circuits that include a storage device, a select circuit connected to the storage device and one or more level shifters providing two or more interfaces to the respective selection circuit.

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Номер записи: 32
20-09-2012 дата публикации

Sensing resistive states

Номер: US20120236623A1
Автор: Muhammad Shakeel Qureshi
Принадлежит: Hewlett Packard Development Co LP

A memory device capable of being sensed with an oscillating signal includes a first terminal of a memristive element connected to an oscillating signal supply, and a second terminal of the memristive element connected to sensing circuitry, the sensing circuitry to determine an attenuation of an oscillating signal from the oscillating signal supply. A crossbar array includes a first set of parallel lines selectively connected to an oscillating signal supply, a second set of parallel lines intersecting the first set of parallel lines, the second set of parallel lines selectively connected to sensing circuitry, memristive memory elements being disposed at crosspoints between the first set of parallel lines and the second set of parallel lines, in which a memory controller of the crossbar array is to determine a resistive state of one of the memory elements by determining, with the sensing circuitry, an attenuation of an oscillating signal produced by the oscillating signal supply.

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Номер записи: 33
20-09-2012 дата публикации

Program cycle skip

Номер: US20120236663A1
Автор: Gopinath Balakrishnan, Luca Fasoli, Tz-yi Liu, Yan Li, Yuheng Zhang
Принадлежит: SanDisk 3D LLC

A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.

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Номер записи: 34
27-09-2012 дата публикации

Nonvolatile memory device

Номер: US20120241707A1
Автор: Kensuke Takahashi
Принадлежит: Toshiba Corp

According to one embodiment, a nonvolatile memory device includes a word line interconnect layer, a bit line interconnect layer, and a pillar. The word line interconnect layer includes a plurality of word lines extending in a first direction. The bit line interconnect layer includes a plurality of bit lines extending in a second direction. The pillar is disposed between each of the word lines and each of the bit lines. The pillar includes a current selection film and a plurality of variable resistance films stacked on the current selection film. One variable resistance film includes a metal and either oxygen or nitrogen. Remainder of the variable resistance films include the metal, either oxygen or nitrogen, and a highly electronegative substance having electronegativity higher than electronegativity of the metal. A concentration of highly electronegative substance in the remainder of the variable resistance films is different among the variable resistance films.

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Номер записи: 35
27-09-2012 дата публикации

Memory device

Номер: US20120243292A1
Автор: Akira Takashima, Daisuke Matsushita, Hidenori Miyagawa, Takashi Yamauchi, Yuuichi Kamimuta
Принадлежит: Individual

According to one embodiment, a memory device includes a first electrode including a crystallized Si x Ge 1-x layer (0≦x<1), a second electrode including a metal element, a variable resistance part between the first and second electrode, the part including an amorphous Si layer, and a control circuit controlling a filament in the amorphous Si layer, the filament including the metal element.

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Номер записи: 36
27-09-2012 дата публикации

Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance

Номер: US20120243298A1
Автор: Glen Hush
Принадлежит: Individual

The invention relates to a method and apparatus providing a memory cell array in which each resistance memory cell is connected in series to a capacitive element. Access transistors are not necessary to perform read and write operations on the memory cell. In one exemplary embodiment, the capacitive element is a capacitor.

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Номер записи: 37
27-09-2012 дата публикации

Control Method for Memory Cell

Номер: US20120243346A1
Автор: Ching-Chih HSU, Frederick T. Chen, Heng-Yuan Lee, Pang-Shiu Chen, Yen-Ya Hsu, Yu-Sheng Chen
Принадлежит: Industrial Technology Research Institute ITRI

A control method for at least one memory cell. The memory cell includes a transistor and a resistor. The resistor is connected to the transistor in series between a first node and a second node. In a programming mode, the memory cell is programmed. When it is determined that the memory cell has been successfully programmed, impedance of the memory cell is in a first state. When it is determined that the memory cell has not been successfully programmed, a specific action is executed to reset the memory cell. The impedance of the memory cell is in a second state after the step resetting the memory cell. The impedance of the memory cell in the second state is higher than that of the memory cell in the first state.

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Номер записи: 38
04-10-2012 дата публикации

Semiconductor memory device and controlling method thereof

Номер: US20120250393A1
Автор: Masanobu Shirakawa
Принадлежит: Individual

According to one embodiment, a semiconductor memory device includes a memory cell array in which memory cells each including at least a rectification element and a variable resistance element, which are connected in series, a peripheral circuit, a sense amplifier configured to sense the memory cells via the peripheral circuit, and a control circuit configured to control operations of the memory cell array and the sense amplifier. The control circuit is configured to boost a potential of a selected bit line, which is one of a first even bit line and a first odd bit line of a first side, by charge sharing of a second even bit line and a second odd bit line which are nonselected bit lines and physically neighbor the first even bit line or the first odd bit line of the first side, which is connected to a selected one of the memory cells.

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Номер записи: 39
11-10-2012 дата публикации

Semiconductor device

Номер: US20120257437A1
Автор: Akiyoshi Seko, Tatsuya Matano
Принадлежит: Elpida Memory Inc

A semiconductor device includes first and second interconnects, a variable resistance element that may assume a first resistance value or a second resistance value in response to the current flowing therein, and second transistors connected between the first and second interconnects in series with each other on both sides of the variable resistance element, and a power supply circuit unit that delivers the power supply to a control electrode of the first transistor. The power supply circuit unit supplies the power of a first power supply when the variable resistance element is to make transition to the first resistance value and the power supply circuit unit supplies the power of a second power supply when the variable resistance element is to make transition to the second resistance value, thereby allowing transitioning of the resistance values of the variable resistance element

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Номер записи: 40
18-10-2012 дата публикации

Arrays Of Nonvolatile Memory Cells And Methods Of Forming Arrays Of Nonvolatile Memory Cells

Номер: US20120262973A1
Автор: Jun Liu
Принадлежит: Individual

An array of nonvolatile memory cells includes a plurality of vertically stacked tiers of nonvolatile memory cells. The tiers individually include a first plurality of horizontally oriented first electrode lines and a second plurality of horizontally oriented second electrode lines crossing relative to the first electrode lines. Individual of the memory cells include a crossing one of the first electrode lines and one of the second electrode lines and material there-between. Specifically, programmable material, a select device in series with the programmable material, and current conductive material in series between and with the programmable material and the select device are provided in series with such crossing ones of the first and second electrode lines. The material and devices may be oriented for predominant current flow in defined horizontal and vertical directions. Method and other implementations and aspects are disclosed.

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Номер записи: 41
18-10-2012 дата публикации

Semiconductor memory device

Номер: US20120266043A1
Автор: Kazuya Ishihara, Mitsuru Nakura, Nobuyoshi Awaya
Принадлежит: Individual

The invention realizes a semiconductor memory device that can efficiently execute a detection of a data error that might possibly occur in a continuous reading action, and a correction of the error data. The semiconductor memory device uses a variable resistive element made of a metal oxide for storing information. During a reading action of coded data with an ECC in the semiconductor memory device, when a data error is detected by an ECC circuit, a writing voltage pulse having a polarity opposite to a polarity of a reading voltage pulse is applied to all memory cells from which the error is detected so as to correct bits from which the error is detected, on an assumption that an erroneous writing has occurred due to the application of the writing voltage pulse having the polarity same as the polarity of the applied reading voltage pulse.

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Номер записи: 42
25-10-2012 дата публикации

Semiconductor device and its manufacturing method

Номер: US20120268981A1
Автор: Fumihiko Nitta, Nozomu Matsuzaki, Satoru Hanzawa, Toshihiro Tanaka
Принадлежит: Renesas Electronics Corp

In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.

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Номер записи: 43
08-11-2012 дата публикации

Nonvolatile latch circuit and nonvolatile flip-flop circuit

Номер: US20120280713A1
Автор: Yoshikazu Katoh
Принадлежит: Panasonic Corp

A nonvolatile latch circuit of the invention includes a variable resistance element which is formed by interposing an oxide layer between electrodes, and changes to a low resistance state by applying a voltage to cause current flow in the direction from the first to the second electrode, and changes to a high resistance state by applying a voltage to cause current flow in the reverse direction, wherein a first terminal of a transistor, a first terminal of other transistor, an output terminal of an inverter circuit, and an output terminal of other inverter circuit are respectively connected to one electrode, the other electrode, a second terminal of the transistor, and a second terminal of the other transistor, and a current flowing through the variable resistance element when changed to a low resistance state is smaller in absolute value than a current therethrough when changed to a high resistance state.

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Номер записи: 44
08-11-2012 дата публикации

Variable resistance nonvolatile storage device

Номер: US20120281453A1
Автор: Kazuhiko Shimakawa, Satoru Mitani, Shunsaku Muraoka, Yoshihiko Kanzawa
Принадлежит: Kazuhiko Shimakawa, Satoru Mitani, Shunsaku Muraoka, Yoshihiko Kanzawa

The variable resistance nonvolatile storage device includes a memory cell ( 300 ) that is formed by connecting in series a variable resistance element ( 309 ) including a variable resistance layer ( 309 b ) which reversibly changes based on electrical signals each having a different polarity and a transistor ( 317 ) including a semiconductor substrate ( 301 ) and two N-type diffusion layer regions ( 302 a, 302 b ), wherein the variable resistance layer ( 309 b ) includes an oxygen-deficient oxide of a transition metal, lower and upper electrodes ( 309 a, 309 c ) are made of materials of different elements, a standard electrode potential V 1 of the lower electrode ( 309 a ), a standard electrode potential V 2 of the upper electrode ( 309 c ), and a standard electrode potential V t of the transition metal satisfy V t <V 2 and V 1 <V 2 , and the lower electrode ( 309 a ) is connected with the N-type diffusion layer region ( 302 b ), the electrical signals being applied between the lower and upper electrodes ( 309 a, 309 c ).

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Номер записи: 45
29-11-2012 дата публикации

Memory cell operation

Номер: US20120300530A1
Автор: John K. Zahurak, Roy E. Meade
Принадлежит: Micron Technology Inc

Methods, devices, and systems associated with memory cell operation are described. One or more methods of operating a memory cell include charging a capacitor coupled to the memory cell to a particular voltage level and programming the memory cell from a first state to a second state by controlling discharge of the capacitor through a resistive switching element of the memory cell.

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Номер записи: 46
06-12-2012 дата публикации

Nitrogen Doped Aluminum Oxide Resistive Random Access Memory

Номер: US20120305881A1
Автор: Siu-Weng S. Wong, Sung Il Park, Wanki Kim, Zhiping Zhang
Принадлежит: Leland Stanford Junior University

A resistive random access memory (RRAM) device is provided that includes a first electrode, a second electrode, and a resistance-change film disposed between the first electrode and the second electrode, where the resistance-change film includes an atomic ratio of aluminum, oxygen and nitrogen.

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Номер записи: 47
06-12-2012 дата публикации

Resistive memory devices and memory systems having the same

Номер: US20120307547A1
Автор: Joon Min PARK, Kwang Jin Lee
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A nonvolatile memory device includes an array of resistive memory cells and a write driver, which is configured to drive a selected bit line in the array with a reset current pulse, which is responsive to a first external voltage input through a first terminal/pad of the memory device during a memory cell reset operation. The write driver is further configured to drive the selected bit line in sequence with a first set current pulse, which is responsive to the first external voltage, and a second set current pulse, which is responsive to a second external voltage input through a second terminal/pad of the memory device during a memory cell set operation.

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Номер записи: 48
13-12-2012 дата публикации

Cell-state measurement in resistive memory

Номер: US20120314481A1
Автор: Abu Sebastian, Angeliki Pantazi, Charalampos Pozidis, Christoph Hagleitner, Gael Close, Nikolaos Papandreou
Принадлежит: International Business Machines Corp

Apparatus and method for measuring the state of a resistive memory cell. A bias voltage controller applies a bias voltage to the cell and controls the level of the bias voltage. A feedback signal generator senses cell current due to the bias voltage and generates a feedback signal (S FB ) dependent on the difference between the cell current and a predetermined target current. The bias voltage controller controls the bias voltage level in dependence on the feedback signal (S FB ) such that the cell current converges on the target current. An output is provided indicative of the bias voltage level at which the cell current corresponds to the target current, thus providing a voltage-based metric for cell-state.

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Номер записи: 49
13-12-2012 дата публикации

Set pulse for phase change memory programming

Номер: US20120314491A1
Автор: Andrew Oen, Aswin Thiruvengadam, Rich Fackenthal, William Melton
Принадлежит: Micron Technology Inc

Subject matter disclosed herein relates to a memory device, and more particularly to a single pulse algorithm for programming a phase change memory.

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Номер записи: 50
13-12-2012 дата публикации

Non-volatile memory device having phase-change material and method for fabricating the same

Номер: US20120314492A1
Автор: Ji-Won Jung, Yong-Shik Shin
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A non-volatile memory device includes a plurality of memory blocks. Each of memory blocks includes a main area including a plurality of first memory cells having a phase-change material and a spare area including at least one second memory cell for storing initial information about the plurality of first memory cells. In the non-volatile memory device, a circuit of the at least one second memory cell is cut off according to the initial information, and the initial information is defective block information that is information about a defect of the plurality of memory blocks.

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Номер записи: 51
20-12-2012 дата публикации

Resistance-change memory device and method of operating the same

Номер: US20120320659A1
Автор: Makoto Kitagawa
Принадлежит: Sony Corp

Disclosed herein is a resistance-change memory device including a bit line; a voltage supplying layer; a memory element connected between the bit line and the voltage supplying layer, a resistance value of the memory element being changed in accordance with an applied voltage; and a drive controlling circuit causing a first current to flow through the bit line and causing a second current smaller than the first current to flow through the bit line, thereby controlling a resistance decreasing operation in which the memory element is made to transit from a high resistance state to a low resistance state by using the second current.

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Номер записи: 52
27-12-2012 дата публикации

Programming of phase-change memory cells

Номер: US20120327709A1
Автор: Abu Sebastian, Angeliki Pantazi, Charalampos Pozidis, Nikolaos Papandreou, Urs Frey
Принадлежит: International Business Machines Corp

A method and apparatus for programming a phase-change memory cell. A bias voltage signal (V BL ) is applied to the cell. A measurement portion (m) of this bias voltage signal has a profile which varies with time. A measurement (T M ), which is dependent on a predetermined condition being satisfied, is then made. The predetermined condition is dependent on cell current during the measurement portion (m) of the bias voltage signal. A programming signal is generated in dependence on the measurement (T M ), and the programming signal is applied to program the cell.

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Номер записи: 53
03-01-2013 дата публикации

Magnetoresistive element and method of manufacturing the same

Номер: US20130001652A1
Автор: Hideaki Harakawa, Jyunichi OZEKI, Keiji Hosotani, Masatoshi Yoshikawa, Satoshi Seto, Tatsuya Kishi
Принадлежит: Individual

According to one embodiment, a magnetoresistive element includes a storage layer having a variable and perpendicular magnetization, a tunnel barrier layer on the storage layer, a reference layer having an invariable and perpendicular magnetization on the tunnel barrier layer, a hard mask layer on the reference layer, and a sidewall spacer layer on sidewalls of the reference layer and the hard mask layer. An in-plane size of the reference layer is smaller than an in-plane size of the storage layer. A difference between the in-plane sizes of the storage layer and the reference layer is 2 nm or less. The sidewall spacer layer includes a material selected from a group of a diamond, DLC, BN, SiC, B 4 C, Al 2 O 3 and AlN.

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Номер записи: 54
03-01-2013 дата публикации

Refresh architecture and algorithm for non-volatile memories

Номер: US20130003451A1
Автор: Ferdinando Bedeschi, Roberto Gastaldi
Принадлежит: Micron Technology Inc

Methods and systems to refresh a non-volatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device performs either a first refresh of memory cells using a margined read reference level or a second refresh of error-corrected memory cells using a non-margined read reference level.

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Номер записи: 55
10-01-2013 дата публикации

Memory system with data line switching scheme

Номер: US20130010523A1
Автор: Luca Fasoli, Tianhong Yan
Принадлежит: SanDisk 3D LLC

A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines (e.g. bit lines) of a first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines that are connected to control circuitry. To increase the performance of memory operations, the second selection circuits can change their selections independently of each other.

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Номер записи: 56
10-01-2013 дата публикации

Descending set verify for phase change memory

Номер: US20130010533A1
Автор: Ferdinando Bedeschi
Принадлежит: Micron Technology Inc

Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.

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Номер записи: 57
17-01-2013 дата публикации

Multi-partitioning of memories

Номер: US20130019058A1
Автор: Danilo Caraccio, Emanuele Confalonieri, Federico Tiziani
Принадлежит: Individual

Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.

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Номер записи: 58
24-01-2013 дата публикации

Resistive ram, method for fabricating the same, and method for driving the same

Номер: US20130021835A1
Автор: Hyun-Sang Hwang, Myoung-Woo Son, Xinjun Liu
Принадлежит: Individual

A resistive random access memory (ReRAM) includes a first electrode, a threshold switching layer formed over the first electrode and configured to perform a switching operation according to an applied voltage, a resistance change layer formed over the threshold switching layer, and configured to perform a resistance change operation, and a second electrode formed over the resistance change layer, wherein the threshold switching layer comprises a stoichiometric transition oxide while the resistance change layer comprises a non-stoichiometric transition metal oxide.

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Номер записи: 59
24-01-2013 дата публикации

Programming at least one multi-level phase change memory cell

Номер: US20130021845A1
Автор: Abu Sebastian, Angeliki Pantazi, Evangelos S. Eleftheriou, Haris Pozidis, Nikolaos Papandreou
Принадлежит: International Business Machines Corp

A method is provided that comprises a step of programming the PCM cell to have a respective definite cell state by at least one current pulse flowing to the PCM cell, said respective definite cell state being defined at least by a respective definite resistance level, a step of controlling said respective current pulse by a respective bitline pulse and a respective wordline pulse, and a step of controlling said respective bitline pulse and said respective wordline pulse dependent on an actual resistance value of the PCM cell and a respective reference resistance value being defined for the definite resistance level.

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Номер записи: 60
31-01-2013 дата публикации

Nonvolatile semiconductor memory apparatus and manufacturing method thereof

Номер: US20130029469A1
Автор: Takeshi Takagi, Takumi Mikawa
Принадлежит: Takeshi Takagi, Takumi Mikawa

A nonvolatile semiconductor memory apparatus including a substrate, lower-layer electrode wires provided on the substrate, an interlayer insulating layer provided with contact holes at locations respectively opposite to the lower-layer electrode wires, resistance variable layers which are respectively connected to the lower-layer electrode wires; and non-ohmic devices which are respectively provided on the resistance variable layers. The non-ohmic devices each has a laminated-layer structure including plural semiconductor layers, a laminated-layer structure including a metal electrode layer and an insulator layer, or a laminated-layer structure including a metal electrode layer and a semiconductor layer. One layer of the laminated-layer structure is embedded to fill each of the contact holes and the semiconductor layer or the insulator layer which is the other layer of the laminated-layer structure has a larger area than an opening of each of the contact holes and is provided on the interlayer insulating layer.

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Номер записи: 61
14-02-2013 дата публикации

Nonvolatile memory element, manufacturing method thereof, and nonvolatile semiconductor device incorporating nonvolatile memory element

Номер: US20130037775A1
Автор: Koji Katayama, Satoru Mitani, Takeshi Takagi, Yoshihiko Kanzawa
Принадлежит: Koji Katayama, Satoru Mitani, Takeshi Takagi, Yoshihiko Kanzawa

A nonvolatile memory element of the present invention comprises a first electrode ( 103 ), a second electrode ( 108 ); a resistance variable layer ( 107 ) which is interposed between the first electrode ( 103 ) and the second electrode ( 107 ) and is configured to switch a resistance value reversibly in response to an electric signal applied between the electrodes ( 103 ) and ( 108 ), and the resistance variable layer ( 107 ) has at least a multi-layer structure in which a first hafnium-containing layer having a composition expressed as HfO x (0.9≦x≦1.6), and a second hafnium-containing layer having a composition expressed as HfO y (1.8≦y≦2.0) are stacked together.

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Номер записи: 62
21-02-2013 дата публикации

Programming at least one multi-level phase change memory cell

Номер: US20130044540A1
Автор: Abu Sebastian, Angeliki Pantazi, Evangelos S. Eleftheriou, Haris Pozidis, Nikolaos Papandreou
Принадлежит: International Business Machines Corp

An apparatus for programming at least one multi-level Phase Change Memory (PCM) cell having a first terminal and a second terminal A programmable control device controls the PCM cell to have a respective cell state by applying at least one current pulse to the PCM cell, the control device controlling the at least one current pulse by applying a respective first pulse to the first terminal and a respective second pulse applied to the second terminal of the PCM cell. The respective cell state is defined by a respective resistance level. The control device receives a reference resistance value defining a target resistance level for the cell, and further receives an actual resistance value of said PCM cell such that the applying the respective first pulse and said respective second pulse is based on said actual resistance value of the PCM cell and said received reference resistance value.

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Номер записи: 63
28-02-2013 дата публикации

Methods, apparatuses, and circuits for programming a memory device

Номер: US20130051136A1
Автор: Agostino Pirovano, Andrea Redaelli, Umberto M. Meotto
Принадлежит: Micron Technology Inc

Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.

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Номер записи: 64
07-03-2013 дата публикации

Method, system, and device for phase change memory switch wall cell with approximately horizontal electrode contact

Номер: US20130058152A1
Автор: Fabio Pellizer, Innocenzo Tortorelli
Принадлежит: Micron Technology Inc

Embodiments disclosed herein may include depositing a storage component material over and/or in a trench in a dielectric material, including depositing the storage component material on approximately vertical walls of the trench and a bottom of the trench. Embodiments may also include etching the storage component material so that at least a portion of the storage component material remains on the approximately vertical walls and the bottom of the trench, wherein the trench is contacting an electrode and a selector such that storage component material on the bottom of the trench contacts the electrode.

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Номер записи: 65
07-03-2013 дата публикации

Device fabrication

Номер: US20130059436A1
Автор: Darrell Rinerson, Robin Cheung
Принадлежит: Individual

Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.

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Номер записи: 66
21-03-2013 дата публикации

METHOD FOR READING A HOLOGRAPHIC MEMORY ON A DATA MEDIUM

Номер: US20130070510A1
Автор: Allot Frances, Bajolle Antoine, Gaspari Sabastien
Принадлежит: GEMALTO SA

The embodiments of this invention also describe to a data medium comprising 1. A data medium comprising{'b': '5', 'a holographic memory () carried by the medium and,'}{'b': 1', '11', '5, 'a photonic crystal () configured, firstly, to filter the light received from a broad-spectrum light source () in order to select a frequency band of the said spectrum and secondly, to guide the light corresponding to the said selected frequency band so as to light the said holographic memory () in a predefined direction.'}21. A data medium according to wherein the photonic crystal () comprises a prohibited band wherein the wavelengths located in the said prohibited band are reflected so as to create a waveguide for those wavelengths.315. A data medium according to or claim 1 , wherein the photonic crystal () comprises an optical resonator that makes it possible to light the holographic memory () coherently with the light spectrum corresponding with the selected frequency band.47. A data medium according to or claim 1 , wherein the format of the said medium is a memory card () that allows the easy handling of the said data medium.5791957. A data medium according to claim 4 , wherein the memory card () comprises a window () that makes it possible to transmit the broad-spectrum light received to the photonic crystal () and in which the said window () and the holographic memory () are positioned on the same side of the memory card ().6791957. A data medium according to claim 4 , wherein the memory card () comprises a window () that makes it possible to transmit the broad-spectrum light received to the photonic crystal () and in which the said window () and the holographic memory () are positioned on opposite sides of the memory card ().71351115. Reading equipment () for reading a data medium having a holographic memory () carried by the medium and claim 4 , a photonic crystal () configured claim 4 , firstly claim 4 , to filter the light received from a broad-spectrum light source () in ...

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Номер записи: 67
21-03-2013 дата публикации

Select devices for memory cell applications

Номер: US20130070511A1
Автор: D.V. Nirmal Ramaswamy, David H. Wells
Принадлежит: Micron Technology Inc

Select devices for memory cell applications and methods of forming the same are described herein. As an example, one or more memory cells comprise a a select device structure including a two terminal select device having a current-voltage (I-V) profile associated therewith, and a non-ohmic device in series with the two terminal select device. The combined two terminal select device and non-ohmic device provide a composite I-V profile of the select device structure that includes a modified characteristic as compared to the I-V profile, and the modified characteristic is based on at least one operating voltage associated with the memory cell.

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Номер записи: 68
18-04-2013 дата публикации

Semiconductor device

Номер: US20130094279A1
Автор: Hiroyuki Kobatake
Принадлежит: Renesas Electronics Corp

A semiconductor device is provided with a lower-layer circuit including a transistor formed over a semiconductor substrate, and a memory cell array formed in an interconnection layer above the semiconductor substrate. Respective memory cells of the memory cell array are provided with a variable resistor element formed in the interconnection layer serving as a memory element. The memory cell array includes a first region directly underneath the memory cells, the first region being a region where a via for electrical coupling with the memory cell is not formed. The lower-layer circuit is disposed in such a way as to overlap at least a part of the first region.

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Номер записи: 69
25-04-2013 дата публикации

Memory array including multi-state memory devices

Номер: US20130103888A1
Автор: Erik Ordentlich, Gadiel Seroussi, Ron M. Roth
Принадлежит: Hewlett Packard Development Co LP

A data storage system including a memory array including a plurality of memory devices programmable in greater than two states. A memory control module may control operations of the memory array, and an encoder module may encode input data for storing to the memory array. The memory array may be an m×n memory array, and the memory control module may control operations of storing data to and retrieving data from the memory array.

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Номер записи: 70
02-05-2013 дата публикации

MEMORY SENSING CIRCUIT

Номер: US20130107615A1
Автор: Keshtbod Parviz
Принадлежит: AVALANCHE TECHNOLOGY, INC.

A sensing circuit includes a sense amplifier circuit having a first and second nodes through which a magnetic memory element is sensed. A first current source is coupled to the first node a second current source is coupled to the second node. A reference magnetic memory element has a resistance associated therewith and is coupled to the first node, the reference magnetic memory element receives current from the first current source. At least one memory element, having a resistance associated therewith, is coupled to the second node and receives current from the second current source. Current from the first current source and current from the second current source are substantially the same. The logic state of the at least one memory element is sensed by a comparison of the resistance of the at least one memory element to the resistance of the reference magnetic memory element. 1. A magnetic memory sensing circuit comprising:a sense amplifier circuit having a first and a second node through which a magnetic memory element is to be read;a first current source coupled to the first node and operative to provide current;a second current source coupled to the second node and operative to provide current;a reference magnetic memory element having a resistance associated therewith and coupled to the first node, the reference magnetic memory element operative to receive current from the first current source;the magnetic memory element that is to be read, having a resistance associated therewith, coupled to the second node, the memory element operative to receive current from the second current source, current from the first current source and current from the second current source are the same;a transistor coupled to the second current source and to which a resistor is coupled, the transistor and the resistor operative to set the current value for the first current source and the second current source with the resistance value of the resistor determining the amount of ...

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Номер записи: 71
02-05-2013 дата публикации

MODIFIED RESET STATE FOR ENHANCED READ MARGIN OF PHASE CHANGE MEMORY

Номер: US20130107618A1
Автор: Boniardi Mattia, IELMINI DANIELE, Pellizzer Fabio, Pirovano Agostino, Redaelli Andrea
Принадлежит: MICRON TECHNOLOGY, INC.

Subject matter disclosed herein relates to techniques involving a structural relaxation (SR) phenomenon for increasing resistance of a Reset state of phase change memory. 1. A method comprising:applying a bias pulse to a phase change memory (PCM) cell to place said PCM cell in a high-resistance state in response to a write command;measuring a read current associated with said high-resistance state of said PCM cell; andapplying a modified bias pulse to said PCM cell to place said PCM cell in a higher-resistance state, wherein said modified bias pulse includes an added trailing edge time (TET) in response to a comparison of said read current with a particular reference current.2. The method of claim 1 , wherein said modified bias pulse is applied to said PCM cell in response to said read current being higher than said particular reference current.3. The method of claim 1 , further comprising:measuring a new read current associated with said higher-resistance state of said PCM cell; anddetermining whether to re-apply said modified bias pulse that includes an increased added trailing edge to said PCM cell, said determining based, at least in part, on a comparison of said new read current with said particular reference current.4. The method of claim 1 , wherein a peak current value of said bias pulse is substantially equal to a peak current value of said modified bias pulse.5. The method of claim 1 , further comprising:increasing a peak current of said modified bias pulse to a value substantially greater than that of said bias pulse.6. The method of claim 1 , wherein said PCM cell in said high-resistance state comprises a phase change material in an amorphous state.7. The method of claim 6 , wherein said PCM cell in said higher-resistance state comprises said phase change material in said amorphous state modified by structural relaxation.8. The method of claim 1 , further comprising:applying said bias pulse individually to subsequent PCM cells in a PCM to place said PCM ...

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Номер записи: 72
09-05-2013 дата публикации

VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE

Номер: US20130114327A1
Автор: Azuma Ryotaro, Ikeda Yuichiro, Kawai Ken, SHIMAKAWA Kazuhiko
Принадлежит:

A variable resistance nonvolatile memory device including memory cells provided at cross-points of first signal lines and second signal lines, each memory cell including a variable resistance element and a current steering element connected to the variable resistance element in series, the variable resistance nonvolatile memory device including a write circuit, a row selection circuit, and a column selection circuit, wherein the write circuit: sequentially selects blocks in an order starting from a block farthest from at least one of the row selection circuit and the column selection circuit and finishing with a block closest to the at least one of the row selection circuit and the column selection circuit; and performs, for each of the selected blocks, initial breakdown on each memory cell included in the selected block. 1. A variable resistance nonvolatile memory device including: a plurality of first signal lines; a plurality of second signal lines crossing the first signal lines; and a memory cell array including a plurality of memory cells provided at cross-points of the first signal lines and the second signal lines ,each of the memory cells including a variable resistance element and a current steering element which is connected to the variable resistance element in series and has two terminals, the variable resistance element having a resistance state which changes to (i) a low resistance state when a first voltage of a predetermined first polarity is applied to the variable resistance element, and (ii) a high resistance state when a second voltage of a second polarity opposite to the first polarity is applied to the variable resistance element, the low resistance state being a state in which the variable resistance element has a resistance value in a first range, and the high resistance state being a state in which the variable resistance element has a resistance value in a second range higher than the first range,the variable resistance nonvolatile memory ...

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Номер записи: 73
09-05-2013 дата публикации

Multilayer Memory Array

Номер: US20130114329A1
Автор: Nickel Janice H., Ribeiro Gilberto Medeiros, Yang Jianhua
Принадлежит:

A multilayer crossbar memory array includes a number of layers. Each layer includes a top set of parallel lines, a bottom set of parallel lines intersecting the top set of parallel lines, and memory elements disposed at intersections between the top set of parallel lines and the bottom set of parallel lines. A top set of parallel lines from one of the layers is a bottom set of parallel lines for an adjacent one of the layers. 1. A multilayer memory array comprising: a top set of parallel lines;', 'a bottom set of parallel lines intersecting said top set of parallel lines; and', 'memory elements disposed at intersections between said top set of parallel lines and said bottom set of parallel lines;, 'a number of layers, each layer comprisingin which a top set of parallel lines from one of said layers is also a bottom set of parallel lines for an adjacent one of said layers.2. The memory array of claim 1 , in which said memory elements are memristive memory elements.3. The memory array of claim 2 , in which said memristive memory elements comprise metal oxide materials.4. The memory array of claim 1 , in which said memory elements inhibit a flow of electric current in one direction.5. The memory array of claim 4 , in which each of said memory elements from one of said layers inhibits electric current from flowing in one direction and each of said memory elements in an adjacent one of said layers inhibits electric current from flowing in an opposite direction as said one direction.6. The memory array of claim 1 , in which electrodes on both ends of said memory elements comprise non-reducing conductive materials.7. The memory array of claim 1 , in which to access a memory element of one of said layers claim 1 , a voltage is applied to a first line from said top set of parallel lines and a second line from said bottom set of parallel lines claim 1 , said top line and said bottom line connected to said memory element.8. The memory array of claim 1 , in which a polarity of ...

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Номер записи: 74
09-05-2013 дата публикации

Memory system and memory managing method thereof

Номер: US20130117500A1
Автор: Sang-Hyun Joo, Sangyong Yoon
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A memory managing method is provided for a memory system, including a nonvolatile memory device and a memory controller controlling the nonvolatile memory device. The memory managing method includes determining whether a program-erase number of a memory block in the nonvolatile memory device reaches a first reference value; managing a life of the memory block according to a first memory managing method when the program-erase number of the memory block is determined to be less than the first reference value; and managing the life of the memory block according to a second memory managing method different from the first memory managing method when the program-erase number of the memory block is determined to be greater than the first reference value.

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Номер записи: 75
16-05-2013 дата публикации

Multi-bit resistive-switching memory cell and array

Номер: US20130119340A1
Автор: Shih-Chieh Wu, Tuo-Hung Hou
Принадлежит: National Chiao Tung University NCTU

This invention proposes a multi-bit resistive-switching memory cell and array thereof. Multiple conduction paths are formed on each memory cell and independent of each other, and each conduction path can be in a high-resistance or low-resistance state, so as to form a multi-bit resistive-switching memory cell. A memory cell array can be formed by arranging a plurality of multi-bit resistive-switching memory cells, and the memory cell array provides a simple, high density, high performance and cost-efficient proposal.

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Номер записи: 76
16-05-2013 дата публикации

NONVOLATILE MEMORY CELL COMPRISING A DIODE AND A RESISTANCE-SWITCHING MATERIAL

Номер: US20130121061A1
Автор: HERNER Scott Brad, Kumar Tanmay, Petti Christopher J.
Принадлежит: SanDisk 3D LLC

A method is provided for programming a memory cell in a memory array. The memory cell includes a resistivity-switching layer of a metal oxide or nitride compound, and the metal oxide or nitride compound includes exactly one metal. The method includes programming the memory cell by changing the resistivity-switching layer from a first resistivity state to a second programmed resistivity state, wherein the second programmed resistivity state stores a data state of the memory cell. Numerous other aspects are provided. 1. A method for programming a memory cell in a memory array , wherein the memory cell comprises a resistivity-switching layer of a metal oxide or nitride compound , the metal oxide or nitride compound including exactly one metal , the method comprising:programming the memory cell by changing the resistivity-switching layer from a first resistivity state to a second programmed resistivity state,wherein the second programmed resistivity state stores a data state of the memory cell.2. The method of claim 1 , wherein the memory array comprises circuitry to program and read the memory cell claim 1 , and wherein the circuitry is adapted to program the memory cell no more than one time claim 1 , and wherein the memory array is a one-time-programmable array.3. The method of claim 2 , wherein the circuitry is adapted to program the memory cell to one of two possible data states.4. The method of claim 2 , wherein the circuitry is adapted to program the memory cell to one of more than two possible data states.5. The method of claim 2 , wherein the circuitry is adapted to program the memory cell to one of three or four possible data states.6. The method of claim 2 , wherein programming the memory cell comprises applying a first programming pulse.7. The method of claim 6 , further comprising reading the memory cell after applying the first programming pulse.8. The method of claim 7 , further comprising applying a second programming pulse if the second programmed ...

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Номер записи: 77
16-05-2013 дата публикации

REWRITING A MEMORY ARRAY

Номер: US20130121062A1
Автор: Ordentlich Erik, Seroussi Gadiel, Vontobel Pascal Olivier
Принадлежит:

A method for rewriting a memory array () with a number of memory elements () includes performing a rewrite process to change the memory array () from an initial state to a target state in a manner that avoids violating to a set of weight constraints at any time during the rewrite process. A memory system includes a memory array () and a memory controller () configured to perform a rewrite process to change the memory array () from an initial state to a target state in a manner that avoids violating a set of weight constraints at any time during the rewrite process. 1. A method for rewriting a memory array comprising a number of memory elements , the method comprising;performing a rewrite process to change said memory array from an initial state to a target state in a manner that avoids violating a set of weight constraints at any time during said rewrite process.2. The method of claim 1 , in which rewriting said memory array comprises:scanning through each of a number of memory elements of said memory array and, for each of said number of memory elements, setting that memory element to a first state if a target state for that memory element is said first state; andscanning through each of said number of memory elements of said memory array and, for each of said number of memory elements, setting that memory element to a second state if a target state for that memory element is said second state.3. The method of claim 1 , in which rewriting said memory array comprises:scanning through each of a number of memory elements of said memory array and for each of said number of memory elements, setting that memory element to a first state if an initial state for that memory element is in a second state and a target state for that memory element is a first state; andscanning through each of said number of memory elements of said memory array and for each of said number of memory elements, setting that memory element to said second state if an initial state for that memory ...

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Номер записи: 78
16-05-2013 дата публикации

MEMORY DEVICE, SEMICONDUCTOR STORAGE DEVICE, METHOD FOR MANUFACTURING MEMORY DEVICE, AND READING METHOD FOR SEMICONDUCTOR STORAGE DEVICE

Номер: US20130121063A1
Автор: Mikawa Takumi, TSUJI Kiyotaka
Принадлежит:

A memory device that can prevent degradation in characteristics of a diode and the destruction due to the miniaturization includes: a substrate; first electrodes, a second electrode, and a third electrode that are stacked above the substrate; a variable resistance layer between the first and second electrodes; and a non-conductive layer between the second and third electrodes. The variable resistance layer includes a high-concentration variable resistance layer closer to the first electrodes, and a low-concentration variable resistance layer closer to the second electrode and having an oxygen concentration lower than that of the high-concentration variable resistance layer. The second and third electrodes and the non-conductive layer comprise the diode, and the first and second electrodes and the variable resistance layer comprise variable resistance elements, a total number of which is equal to that of the first electrodes. 1. A memory device , comprising:a substrate;a plurality of first electrodes, a second electrode, and a third electrode that are stacked above the substrate;a variable resistance layer formed in an island shape between the first electrodes and the second electrode; anda non-conductive layer formed between the second electrode and the third electrode,wherein the variable resistance layer includes a high-concentration variable resistance layer located closer to the first electrodes, and a low-concentration variable resistance layer located closer to the second electrode, the low-concentration variable resistance layer having an oxygen concentration lower than an oxygen concentration of the high-concentration variable resistance layer,the second electrode, the non-conductive layer, and the third electrode comprise a diode,the second electrode, the third electrode, the variable resistance layer, and the non-conductive layer are formed across the first electrodes,the first electrodes, the variable resistance layer, and the second electrode comprise a ...

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Номер записи: 79
30-05-2013 дата публикации

Selector Device for Memory Applications

Номер: US20130134382A1
Автор: Iuliana Radu, Koen Martens, Pieter Blomme, Stefan Cosemans
Принадлежит: Interuniversitair Microelektronica Centrum vzw IMEC, KU Leuven Research and Development

The present disclosure is related to a selector device for memory applications. The selector device for selecting a memory element in a memory array comprises an MIT element and a decoupled heater, thermally linked to the MIT element. The MIT element comprises a MIT material component and a barrier component and is switchable from a high to a low resistance state by heating the MIT element above a transition temperature with the decoupled heater. The barrier component is provided to increase the resistance of the MIT element in the high resistance state.

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Номер записи: 80
06-06-2013 дата публикации

METHODS AND SYSTEMS FOR OPERATING MEMORY ELEMENTS

Номер: US20130141960A1
Автор: Porter John D., Taylor Jennifer
Принадлежит: MICRON TECHNOLOGY, INC.

Methods and systems for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of resistance of the multi-bit memory elements, determination of how many and which memory elements fall into specific memory ranges can be accomplished. Furthermore, storage and/or display of this information may allow for the creation of resistance distribution histograms for modeling of one or more memory arrays. 1. A method of operating a memory device comprising:generating a pulse stream based on capacitance discharge through a memory element;determining a resistance of the memory element based on the pulse stream; andstoring the determined resistance of the memory element.2. The method of claim 1 , comprising generating one or more resistance range based on the stored determined resistance of the memory element.3. The method of claim 2 , comprising determining one or more distributions of resistance levels from the one or more resistance ranges.4. The method of claim 1 , wherein determining the resistance of the memory element based on the pulse stream comprises examining a ratio of a clocked comparator output high time with the clocked comparator output low time.5. The method of claim 1 , wherein determining the resistance of the memory element comprises determining a proportionality of an inverse of the pulse stream.6. The method of claim 1 , comprising monitoring the capacitance discharge via a quantizing circuit.7. The method of claim 6 , wherein monitoring the capacitance discharge comprises monitoring a number of switches of an op amp output in the quantizing circuit from active low to active high.8. The method of claim 1 , wherein storing the determined resistance of the memory element comprises storing the determined resistance of the memory element in an accumulator.9. A method of operating a memory device comprising:monitoring capacitance discharge through a first memory element in a ...

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Номер записи: 81
06-06-2013 дата публикации

Variable resistive memory device and method of fabricating the same

Номер: US20130141967A1
Автор: Hye Jin Choi, Ju Heyuck Baeck, Mann Ho CHO, Tae Hyeon Kim
Принадлежит: Hynix Semiconductor Inc, Industry Academic Cooperation Foundation of Yonsei University

A variable resistive memory device includes an array of a plurality of memory cells. Each of the plurality of memory cells includes first and second electrodes, and an Sb m Se n material layer (where m and n are positive numbers, respectively) interposed between the first electrode and the second electrode. The Sb m Se n material layer includes a separation structure in which a plurality of Sb atoms are in contact with a plurality of Se atoms.

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Номер записи: 82
06-06-2013 дата публикации

SEMICONDUCTOR STORAGE DEVICE

Номер: US20130141968A1
Автор: HANZAWA Satoru, Kinoshita Masaharu, Kobayashi Takashi, Minemura Hiroyuki, Sasago Yoshitaka, Shintani Toshimichi
Принадлежит:

The purpose of the present invention is to improve a rewriting transmission rate and reliability of a phase change memory. To attain the purpose, a plurality of phase change memory cells (SMC or USMC) which are provided in series between a word line () and a bit line () and have a selection element and a storage element that are parallel connected with each other are entirely set, and after that, a part of the cells corresponding to a data pattern is reset. Alternatively, the reverse of the operation is carried out. 1. A semiconductor storage device comprising:a first word line;a first bit line; andN first memory cells (N is an integer of 3 or more) each comprisinga first memory element in which memory information is programed by current; anda first transistor in which a source-drain path of the first transistor is connected in parallel to the first memory element, and provided between the first word line and the first bit line;wherein each of the N first memory elements is serially connected to each other;a resistivity of the first transistor is lower than that of the first memory element in a first state and higher than that of the first memory element in a second state; andin a state in which a first value is memorized in all of the N first memory elements, a control in which M first transistors (M is an integer 2 or more and less than N) in the N transistors are set to the second state, and remaining (N-M) transistors are set to the first state, and a first voltage difference is biased for memorizing a second value that is different from the first value to the M first memory elements is performed.2. The semiconductor storage device according to claim 1 ,wherein, at the time of memorizing the first value to all of the N first memory elements, the first value is memorized to odd-numbered first memory elements in the N first memory elements, and thereafter, the first value is memorized to even-numbered first memory elements in the N first memory elements.3. The ...

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Номер записи: 83
06-06-2013 дата публикации

REDUCED SIGNAL INTERFACE MEMORY DEVICE, SYSTEM, AND METHOD

Номер: US20130141980A1
Автор: Kale Poorna
Принадлежит: MICRON TECHNOLOGY, INC.

A memory has a serial interface. The serial interface is programmable to either use separate dedicated input and output pads, or to use one bidirectional pad. When one bidirectional pad is used, the interface signal count is reduced by one. 1. A memory comprising:a serial data in pad and a serial data out pad;circuitry configured to configure one of the serial data in pad or the serial data out pad to operate as a bidirectional serial data pad; anda control unit coupled to the serial data in pad, the control unit configured to receive serial instructions and to configure the circuitry for bidirectional operation.2. The memory of claim 1 , further comprising a package claim 1 , wherein only one of the serial data in and serial data out pad is bonded to the package.3. The memory of claim 1 , further comprising:a serial shift register coupled to the serial data in pad and the serial data out pad; anda nonvolatile memory core coupled to the serial shift register.4. The memory of claim 3 , wherein the nonvolatile memory core comprises FLASH memory.5. The memory of claim 3 , wherein the nonvolatile memory core comprises phase change memory.6. The memory of claim 1 , wherein the control unit configured to configure the circuitry for bidirectional operation is responsive to receiving an instruction via the serial data in pad.7. The memory of claim 6 , wherein the control unit is configured to configure the circuitry for full duplex operation responsive to receiving a second instruction via the serial data in pad.8. A memory comprising:circuitry coupled to a serial data in pad and a serial data out pad, the circuitry configured to enable bidirectional communication on one of the serial data in pad or the serial data out pad; anda control unit coupled to the serial data in pad and configured to control the circuitry to operate in one of a bidirectional mode or a full duplex mode.9. The memory of claim 8 , wherein the control unit is configured to receive serial instructions ...

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Номер записи: 84
13-06-2013 дата публикации

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND READ METHOD FOR THE SAME

Номер: US20130148406A1
Автор: Azuma Ryotaro, SHIMAKAWA Kazuhiko, TSUJI Kiyotaka
Принадлежит:

A cross point nonvolatile memory device capable of suppressing sneak-current-caused reduction in sensitivity of detection of a resistance value of a memory element is provided. The device includes perpendicular bit and word lines; a cross-point cell array including memory cells each having a resistance value reversibly changing between at least two resistance states according to electrical signals, arranged on cross-points of the word and bit lines; an offset detection cell array including an offset detection cell having a resistance higher than that of the memory cell in a high resistance state, the word lines being shared by the offset detection cell array; a read circuit (a sense amplifier) that determines a resistance state of a selected memory cell based on a current through the selected bit line; and a current source which supplies current to the offset detection cell array in a read operation period. 1. A nonvolatile semiconductor memory device , comprising:word lines formed in parallel in a first plane;bit lines formed in parallel in a second plane and three-dimensionally crossing the word lines, the second plane being parallel to the first plane;a first cross-point cell array including first type cells located at three-dimensional cross-points of the word lines and the bit lines;one or more dummy bit lines formed in parallel and three-dimensionally crossing the word lines in the second plane;a second cross-point cell array including cells, each of which is either the first type cell or a second type cell, located at a corresponding one of three-dimensional cross-points of the word lines and the one or more dummy bit lines, the second cross-point cell array including at least one each of the first type cells and the second type cells for each of the one or more dummy bit lines;a word line selection circuit that selects one of the word lines as a selected word line;a bit line selection circuit that selects one of the bit lines as a selected bit line;a dummy ...

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Номер записи: 85
13-06-2013 дата публикации

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND READ METHOD FOR THE SAME

Номер: US20130148407A1
Автор: SHIMAKAWA Kazuhiko, TSUJI Kiyotaka
Принадлежит:

A nonvolatile semiconductor memory device includes: word lines; bit lines formed so as to three-dimensionally cross the word lines; and a cross-point cell array including cells each provided at a corresponding one of three-dimensional cross-points of the word lines and the bit lines. The cells include: a memory cell including a memory element that operates as a memory by reversibly changing in resistance value between at least two states based on an electrical signal; and an offset detection cell having a constant resistance value that is higher than the resistance value of the memory element in a high resistance state which is a state of the memory element when operating as the memory. 1. A nonvolatile semiconductor memory device comprising:word lines formed in parallel in a first plane;bit lines formed in parallel in a second plane and three-dimensionally crossing the word lines, the second plane being parallel to the first plane; anda cross-point cell array including cells each provided at a corresponding one of three-dimensional cross-points of the word lines and the bit lines,wherein the cells include:a memory cell including a memory element that operates as a memory by reversibly changing in resistance value between at least two states based on an electrical signal applied between a corresponding one of the word lines and a corresponding one of the bit lines; andan offset detection cell having a resistance value that is, irrespective of an electrical signal applied between a corresponding one of the word lines and a corresponding one of the bit lines, higher than the resistance value of the memory element in a high resistance state which is a state of the memory element when operating as the memory.2. The nonvolatile semiconductor memory device according to claim 1 , further comprising:a word line selector that selects one of the word lines as a selected word line;a bit line selector that selects one of the bit lines as a selected bit line; anda read circuit ...

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Номер записи: 86
13-06-2013 дата публикации

METHOD OF PROGRAMMING VARIABLE RESISTANCE NONVOLATILE MEMORY ELEMENT

Номер: US20130148408A1
Автор: Katoh Yoshikazu, Kawai Ken, Muraoka Shunsaku, SHIMAKAWA Kazuhiko
Принадлежит:

A method of programming a variable resistance nonvolatile memory element that removes a defect in a resistance change, ensures an operation widow, and stably sustains a resistance change operation, the method including: applying, when the detect in the resistance change occurs in the variable resistance nonvolatile memory element, a recovery voltage pulse at least once to the variable resistance nonvolatile memory element, the recovery voltage pulse including: a first recovery voltage pulse that has an amplitude greater than amplitudes of a normal high resistance writing voltage pulse and a low resistance writing voltage pulse; and a second recovery voltage pulse that is the low resistance writing voltage pulse following the first recovery voltage pulse. 1. A method of programming a variable resistance nonvolatile memory element , the method of programming reversibly changing , by applying a voltage pulse to the variable resistance nonvolatile memory element , a resistance state of the variable resistance nonvolatile memory element ,wherein the variable resistance nonvolatile memory element includes: a first electrode; a second electrode; and an oxygen-deficient transition metal oxide layer provided between the first and second electrodes,the transition metal oxide layer includes: a first transition metal oxide layer that is in contact with the first electrode; and a second transition metal oxide layer that is in contact with the second electrode and has a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first transition metal oxide layer, andafter the variable resistance nonvolatile memory element is manufactured and an initial breakdown voltage pulse having a predetermined amplitude is applied between the first and second electrodes, the variable resistance nonvolatile memory element has characteristics of (i) changing to a low resistance state when a low resistance writing voltage pulse for providing a negative electric potential to the ...

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Номер записи: 87
13-06-2013 дата публикации

CIRCUIT AND SYSTEM OF USING FINFET FOR BUILDING PROGRAMMABLE RESISTIVE DEVICES

Номер: US20130148409A1
Автор: Chung Shine C.
Принадлежит:

Junction diodes or MOS devices fabricated in standard FinFET technologies can be used as program selectors or One-Time Programmable (OTP) element in a programmable resistive device, such as interconnect fuse, contact/via fuse, anti-fuse, or emerging nonvolatile memory such as MRAM, PCRAM, CBRAM, or RRAM. The MOS or diode can be built on at least one fin structure or at least one active region that has at least one first active region and a second active region. The first and the second active regions can be isolated by a dummy MOS gate or silicide block layer (SBL) to construct a diode. 1. A programmable resistive memory , comprising: a resistive element;', 'at least one fin structure coupled to the resistive element, the at least one fin structure being a semiconductor structure and including at least a first active region and a second active region, the first active region having a first type of dopant, and the second active region having the first type of dopant or the second type of dopant; and', 'a gate provided over at least a portion of the at least one fin structure, the gate being provided between or adjacent both the first and second active regions,, 'a plurality of programmable resistive cells, at least one of the programmable resistive cells comprisingwherein at least a portion of the first and second active regions residing in a common well or on an isolated substrate.2. A programmable resistive memory as recited in claim 1 , wherein an insulator material is provided between the gate and the at least a portion of the at least one fin structure.3. A programmable resistive memory as recited in claim 1 , wherein the resistive element is coupled to a first supply voltage line claim 1 , and wherein the first active region is coupled to the resistive element claim 1 , the second active region is coupled to a second supply voltage line claim 1 , and the MOS gate is coupled to a third supply voltage line.4. A programmable resistive memory as recited in claim 3 ...

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Номер записи: 88
13-06-2013 дата публикации

METHODS OF PROGRAMMING TWO TERMINAL MEMORY CELLS

Номер: US20130148421A1
Автор: Scheuerlein Roy E., Thorp Tyler J.
Принадлежит: SanDisk 3D LLC

Methods of programming two terminal memory cells are provided. A method includes: (a) reading information of a memory page including first, second, and nth memory cells, the information including first, second, and nth program pulse tuning instructions; (b) creating a first program pulse in accordance with the first program pulse tuning instructions to program the first memory cell; (c) locking the first memory cell from further programming pulses; (d) creating a second program pulse in accordance with the second program pulse tuning instructions to program the second memory cell; (e) locking the second memory cell from further programming pulses; and (f) creating an nth program pulse in accordance with the nth program pulse tuning instructions to program the nth memory cell. 1. A method comprising:reading information of a memory page including first, second, and nth memory cells, the information including first, second, and nth program pulse tuning instructions;creating a first program pulse in accordance with the first program pulse tuning instructions to program the first memory cell;locking the first memory cell from further programming pulses;creating a second program pulse in accordance with the second program pulse tuning instructions to program the second memory cell;locking the second memory cell from further programming pulses; andcreating an nth program pulse in accordance with the nth program pulse tuning instructions to program the nth memory cell.2. The method of claim 1 , wherein the first claim 1 , second claim 1 , and nth program tuning instructions are different from one another in at least one respect.3. The method of claim 1 , wherein the information of a memory page is stored in a memory page sideband area.4. The method of claim 1 , wherein each of the first claim 1 , second claim 1 , and nth program pulse tuning instructions includes a voltage level instruction.5. The method of claim 4 , wherein at least one voltage level instruction includes a ...

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Номер записи: 89
20-06-2013 дата публикации

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

Номер: US20130155756A1
Автор: Inoue Hirofumi, Nagashima Hiroyuki
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A nonvolatile semiconductor memory device comprises a cell array including plural MATs (unit cell arrays) arranged in matrix, each MAT containing a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells connected at intersections of the first and second lines between both lines, each memory cell containing an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data; and a plurality of write/erase circuits connected to the MATs and operative to execute data write or erase to the memory cells inside the MATs in accordance with input data. A part of the plurality of write/erase circuits writes data to memory cells inside a corresponding MAT while another part of the plurality of write/erase circuits erases data from memory cells inside a corresponding MAT at the same time. 1. A nonvolatile semiconductor memory device , comprising:a cell array including plural MATs (unit cell arrays), each MAT having a plurality of first lines, a plurality of second lines intersecting said plurality of first lines, and a plurality of memory cells connected at intersections of said first and second lines between both lines, each memory cell having an electrically erasable programmable variable resistive element; anda plurality of write/erase circuits connected to said MATs, respectively, whereina part of said plurality of write/erase circuits each applies a set voltage to one selected first line and one selected second line to write data to one of said memory cells inside a corresponding MAT while another part of said plurality of write/erase circuits each applies a reset voltage to one selected first line and one selected second line to erase data from one of said memory cells inside a corresponding MAT at the same time.2. The nonvolatile semiconductor memory device according to claim 1 , further comprising a pulse generator operative to generate a write ...

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Номер записи: 90
20-06-2013 дата публикации

PHASE CHANGE MEMORY DEVICES, METHOD FOR ENCODING, AND METHODS FOR STORING DATA

Номер: US20130155766A1
Автор: Liu Zhiyong
Принадлежит: INTERMEC IP CORP.

Phase change memory cells including a phase change media can be encoded using a source of energy that is not integral with the memory cell. External sources of energy include thermal heads, such as those used in direct thermal printing or thermal transfer printing and sources of electromagnetic radiation, such as lasers. Such types of phase change memory devices can be associated with substrates that include thermochromic materials or are suitable for thermal transfer printing so that the memory cells can be encoded and print media applied to the substrate using the same source of thermal energy. 1. A phase-change memory device comprising:a memory cell including a phase change media having a crystallization temperature and a melting temperature; a first electrically conductive member beneath the phase change media, and a second electrically conductive member above the phase change media; anda substrate associated with the memory cell, wherein the memory cell is free of a resistive material configured to emit thermal energy in response to flow of electric current through the resistive material and increase the temperature of the phase change media by transferring at least a portion of the emitted thermal energy to the phase change media.2. The memory device of claim 1 , wherein the phase change media comprises a chalcogenide.3. The memory device of claim 1 , wherein the phase change media is a chalcogenide alloy including elements selected from tellurium claim 1 , germanium claim 1 , antimony claim 1 , and sulfur.4. The memory device of claim 1 , further comprising a plurality of additional memory cells.5. The memory device of claim 4 , wherein the substrate is a semiconductive material.6. The memory device of wherein the substrate further comprises a thermochromic media.7. The memory device of claim 4 , wherein the substrate further comprises a thermal transfer print media.8. The memory device of claim 5 , wherein the substrate further comprises a thermochromic ...

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Номер записи: 91
20-06-2013 дата публикации

APPARATUSES AND METHODS FOR SENSING A PHASE-CHANGE TEST CELL AND DETERMINING CHANGES TO THE TEST CELL RESISTANCE DUE TO THERMAL EXPOSURE

Номер: US20130155767A1
Автор: Brand Jason, Snodgress Jason
Принадлежит: MICRON TECHNOLOGY, INC.

A phase change memory array may include at least one cell used to determine whether the array has been altered by thermal exposure over time. The cell may be the same or different from the other cells. In some embodiments, the cell is only read in response to an event. If, in response to that reading, it is determined that the cell has changed state or resistance, it may deduce whether the change is a result of thermal exposure. Corrective measures may then be taken. 1. A method , comprising:sensing a characteristic of a phase change test cell that is configured to be more sensitive to thermal degradation than phase change memory cells of a phase change memory array;determining whether the sensed characteristic of the phase change test cell is within a tolerance range of an initial value; andrefreshing the phase change memory array responsive to a determination that the sensed characteristic of the phase change test cell is outside the tolerance range of the initial value.2. The method of claim 1 , wherein determining whether the sensed characteristic of the phase change test cell is within the tolerance range of the initial value comprises comparing the sensed characteristic to the threshold.3. The method of claim 1 , wherein sensing the characteristic of the phase change test cell comprises sensing a resistance of the phase change test cell.4. The method of claim 3 , further comprising storing an initial resistance value of the phase change memory cell as the threshold value.5. The method of claim 4 , further comprising measuring the initial resistance value of the phase change memory cell.6. The method of claim 1 , further comprising refreshing the phase change memory array responsive to the determination that the sensed characteristic of the phase change test cell is less than the initial value.7. The method of claim 1 , further comprising refreshing the phase change memory array responsive to the determination that the sensed characteristic of the phase change ...

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Номер записи: 92
27-06-2013 дата публикации

Method of programming variable resistance element, method of initializing variable resistance element, and nonvolatile storage device

Номер: US20130163308A1
Автор: Mitsuteru Iijima, Takeshi Takagi
Принадлежит: Panasonic Corp

Programming a variable resistance element includes: a writing step of applying a writing voltage pulse to transition metal oxide comprising two stacked metal oxide layers to decrease resistance of the metal oxide, each metal oxide layer having different oxygen deficiency; and an erasing step of applying an erasing voltage pulse, of different polarity than the writing pulse, to the metal oxide to increase resistance of the metal oxide. |Vw 1 |>|Vw 2 |. Vw 1 represents writing voltage for first to N-th steps, Vw 2 represents writing voltage for (N+1)-th and subsequent steps, where N≧1, |Ve 1 |>|Ve 2 |. Ve 1 represents erasing voltage for first to M-th steps. Vet represents erasing voltage for M+1-th and subsequent steps. tw 1 <te 1 . tw 1 represents writing pulse width for first to N-th steps. te 1 represents erasing pulse width for first to M-th steps. M≧1. The (N+1)-th writing step follows the M-th erasing step.

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Номер записи: 93
27-06-2013 дата публикации

Parallel programming scheme in multi-bit phase change memory

Номер: US20130163322A1
Автор: Chung H. Lam, Jing Li
Принадлежит: International Business Machines Corp

A system, a method for parallel programming multiple bits of a phase change memory array for high bandwidth. The system and method includes parallel programming scheme wherein a common wordline (WL) is driven with a first pulse of one of: gradually increasing (RESET) or decreasing (SET) amplitudes which control current flow through one or more phase change memory cells associated with the WL. Simultaneously therewith, one or more bitlines (BLs) are driven with one or more second pulses, each second pulse more narrow than that of the first pulse applied to the WL. The starting time of the one or more second pulses may vary with each bitline driven at a time later than, but within the window of the wordline pulse to achieve a programming current suitable for achieving the corresponding memory cell state.

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Номер записи: 94
27-06-2013 дата публикации

SEMICONDUCTOR MEMORY DEVICE USING VARIABLE RESISTANCE ELEMENT OR PHASE-CHANGE ELEMENT AS MEMORY DEVICE

Номер: US20130163323A1
Автор: YASUTAKE Nobuaki
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A semiconductor memory device includes a first conductive line, a second conductive line, a cell unit, a silicon nitride film and a double-sidewall film. The first conductive line extends in a first direction. The second conductive line extends in a second direction crossing the first direction. The cell unit includes a phase-change film and a rectifier element connected in series with each other between the first conductive line and the second conductive line. The silicon nitride film is formed on a side surface of the phase-change film. The double-sidewall film includes a silicon oxide film and the silicon nitride film formed on a side surface of the rectifier element. 1. A semiconductor memory device comprising:a first conductive line extending in a first direction;a second conductive line extending in a second direction crossing the first direction;a cell unit including a phase-change film and a rectifier element connected in series with each other between the first conductive line and the second conductive line;a silicon nitride film formed on an all side surface of the phase-change film in a plane in which the silicon nitride film and the phase-change film are cut in parallel with the first direction and the second direction; anda double-sidewall film including a silicon oxide film and the silicon nitride film formed on an all side surface of the rectifier element in a plane in which the double-sidewall film and the rectifier element are cut in parallel with the first direction and the second direction.2. The semiconductor memory device according to claim 1 , whereinthe rectifier element and the phase-change film are cut along a plane planes parallel to the first direction and the second direction, and a sectional area of the rectifier element is smaller than a sectional area of the phase-change film.3. The semiconductor memory device according to claim 1 , further comprising:a coating oxide film formed between the cell units to isolate the cell units from ...

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Номер записи: 95
27-06-2013 дата публикации

Semiconductor device and method for operating the same

Номер: US20130163348A1
Автор: Dong Keun Kim, Jung Hyuk YOON
Принадлежит: SK hynix Inc

A semiconductor device and a method for operating the same are provided relating to a nonvolatile memory device for sensing data using resistance change. The semiconductor device comprises a verification read control unit configured to sequentially output verification read data received from a sense amplifier into a global input/output line in response to a test signal, and a read data latch unit configured to store sequentially the verification read data received from the global input output line in response to a latch enable signal in activation of the test signal.

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Номер записи: 96
04-07-2013 дата публикации

Variable resistance memory device

Номер: US20130170282A1
Автор: Jae-Yun YI
Принадлежит: Individual

A variable resistance memory device includes: first and second structures that each include a first electrode, a second electrode, and a variable resistance material layer interposed between the first and second electrodes and configured to switch between different resistance states depending on a voltage applied across the variable resistance material layer; and a material layer interposed between the first and second structures and configured to pass a bidirectional current according to a voltage applied across the material layer. The first and second structures are symmetrical with respect to the material layer.

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Номер записи: 97
04-07-2013 дата публикации

Drive Method for Memory Element and Storage Device Using Memory Element

Номер: US20130170285A1
Автор: FUKUOKA Toshimi, FURUTA Shigeo, Hayashi Yutaka, MASUDA Yuichiro, Naitou Yasuhisa, ONO Masatoshi, Shimizu Tetsuo, Somu Kumaragurubaran, Suga Hiroshi, Sumiya Touru, TAKAHASHI Tsuyoshi
Принадлежит:

In a drive method for a memory element that includes an insulating substrate, a first electrode and a second electrode provided on the insulating substrate, and an inter-electrode gap portion provided between the first electrode and the second electrode and having a gap of the order of nanometers where a phenomenon of a change in resistance value between the first and second electrodes occurs, and that can perform a transition from a predetermined low-resistance state to a predetermined high-resistance state and a transition from the high-resistance state to the low-resistance state, a current pulse is applied to the memory element by a constant current circuit upon the transition from the high-resistance state to the low-resistance state. 1. A drive method for a memory element , the memory element comprising an insulating substrate; a first electrode and a second electrode provided on the insulating substrate; and an inter-electrode gap portion provided between the first electrode and the second electrode and having a gap of an order of nanometers where a phenomenon of a change in resistance value between the first and second electrodes occurs , wherein a state of the memory element can be shifted from a predetermined low-resistance state to a predetermined high-resistance state and from the high-resistance state to the low-resistance state , the method comprising:applying a current pulse to a memory element by a constant current circuit upon a shift from a high-resistance state to a low-resistance state.2. The drive method for a memory element according to claim 1 , wherein the current pulse is applied through the constant current circuit such that a current value changes in a stepwise manner.3. A storage device claim 1 , comprising:a memory element comprising an insulating substrate; a first electrode and a second electrode provided on the insulating substrate; and an inter-electrode gap portion provided between the first electrode and the second electrode and ...

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Номер записи: 98
04-07-2013 дата публикации

VARIABLE RESISTANCE MEMORY WITH LATTICE ARRAY USING ENCLOSING TRANSISTORS

Номер: US20130170291A1
Автор: Liu Jun
Принадлежит: MICRON TECHNOLOGY, INC.

A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations. 133-. (canceled)34. A method of programming a phase change memory array comprising:biasing bitline contacts of the array at a same voltage;turning on a word line forming a plurality of transistors, wherein at least two transistors surround a selected phase change memory element, the at least two transistors sharing a common source/drain region and the selected phase change memory element being in contact with the common source/drain region; andturning on a top electrode select line to transfer a current through the selected phase change memory element, wherein the current is transferred from the common source/drain region and across the at least two transistors to the bitline contacts.35. A method of programming a phase change memory array comprising:biasing bitline contacts of the array at a same voltage;turning on a selected top electrode select line to transfer a current through a selected phase change memory element,wherein at least three word line transistors share a common source/drain region, the common source/drain ...

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Номер записи: 99
11-07-2013 дата публикации

Device structure for long endurance memristors

Номер: US20130175497A1
Автор: Jianhua Yang, Minxian Max Zhang, R. Stanley Williams
Принадлежит: Hewlett Packard Development Co LP

A memristor includes a first electrode formed of a first metal, a second electrode formed of a second material, wherein the second material comprises a different material from the first metal, and a switching layer positioned between the first electrode and the second electrode. The switching layer is formed of a composition of a first material comprising the first metal and a second nonmetal material, in which the switching layer is in direct contact with the first electrode and in which at least one conduction channel is configured to be formed in the switching layer from an interaction between the first metal and the second nonmetal material.

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Номер записи: 100