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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 9119. Отображено 100.
05-01-2012 дата публикации

Methods, structures, and devices for reducing operational energy in phase change memory

Номер: US20120002465A1
Автор: Roy E. Meade
Принадлежит: Micron Technology Inc

Methods of forming and operating phase change memory devices include adjusting an activation energy barrier between a metastable phase and a stable phase of a phase change material in a memory cell. In some embodiments, the activation energy barrier is adjusted by applying stress to the phase change material in the memory cell. Memory devices include a phase change memory cell and a material, structure, or device for applying stress to the phase change material in the memory cell. In some embodiments, a piezoelectric device may be used to apply stress to the phase change material. In additional embodiments, a material having a thermal expansion coefficient greater than that of the phase change material may be positioned to apply stress to the phase change material.

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16-02-2012 дата публикации

Destruction of data stored in phase change memory

Номер: US20120039117A1
Автор: Gary Edward Webb
Принадлежит: Individual

A mechanism and means by which the data information pattern stored in Phase Change Memory PCM ( 21 ) can be quickly destroyed and made unreadable upon the receipt of a destruction stimuli( 11 ) by the application of a targeted thermal heat source generated by an internal integrated thermal heater ( 26 ), a heat source mounted under the PCM ( 28 ), on top of the PCM ( 29 ), within the PCB ( 30 ), or an externally generated heat source ( 27 ). Such an operation is non-destructive and while the stored data is rendered unreadable, the physical PCM device is unharmed and can be used again.

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15-03-2012 дата публикации

Method for improving writability of sram memory

Номер: US20120063211A1

A method for improving writability of an SRAM cell is disclosed. In one aspect, the method includes applying a first voltage higher than the global ground voltage and a third voltage higher than the global supply voltage to the ground supply nodes of the invertors of the SRAM cell, pre-charging one of the complementary bitlines to the global ground voltage, and applying a second voltage higher than the global supply voltage to the access transistors during a write operation to the SRAM cell.

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15-03-2012 дата публикации

Memory and method for sensing data in a memory using complementary sensing scheme

Номер: US20120063249A1
Принадлежит: FREESCALE SEMICONDUCTOR INC

In a memory ( 100 ), a local data line pair ( 116, 118 ) is precharged to a first logic state and a global data line pair ( 101, 104 ) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair ( 116, 118 ) to develop a differential local data line voltage. The differential local data line voltage is subsequently amplified to form an amplified differential local data line voltage. A selected one of the global data line pair ( 101, 104 ) is driven to the first logic state in response to the amplified differential local data line voltage to form a differential global data line voltage.

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15-03-2012 дата публикации

Apparatus and method for read preamble disable

Номер: US20120066433A1
Принадлежит: SPANSION LLC

A memory device is provided. The memory device includes a preamble disable memory and a memory controller. The preamble disable memory is arranged to store preamble disable data. The preamble disable data includes an indication as to whether a read preamble should be enabled or disabled. In response to a read command, if the preamble disable data includes an indication that the read preamble should be enabled, the memory controller provides the read preamble. Alternatively, in response to the read command, if the preamble disable data includes an indication that the read preamble should be disabled, the memory controller disables the read preamble.

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17-05-2012 дата публикации

Phase change memory device

Номер: US20120120724A1
Автор: Hyuck-Soo Yoon
Принадлежит: Individual

A phase change memory device includes a signal generator configured to generate first and second sensing and amplifying enable signals which are sequentially activated during an activation period of a word line selection signal and each of which has a certain activation period length, a resistance sensor configured to sense a resistance value by applying a certain operation current to a phase change memory cell corresponding to the word line selection signal during an activation period of the first sensing and amplifying enable signal and a voltage level amplifier configured to logically determine a voltage level of the resistance sensing signal based on a voltage level of a logic reference signal during an activation period of the second sensing.

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24-05-2012 дата публикации

Semiconductor storage device

Номер: US20120127784A1
Автор: Fumihiko Tachibana
Принадлежит: Toshiba Corp

According to one embodiment, a dummy cell simulates an operation of a memory cell. A main dummy bit line transmits a signal read out from the dummy cell. An inverter makes a sense amplifier circuit to operate based on a potential of the main dummy bit line. n (n is a positive integer) number of auxiliary dummy bit lines are provided. A switching element connects at least one of the n number of auxiliary dummy bit lines to the main dummy bit line.

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14-06-2012 дата публикации

Semiconductor memory device

Номер: US20120147683A1
Автор: Tsuyoshi Midorikawa
Принадлежит: Toshiba Corp

A memory cell is provided at an intersection of a word line and a bit line, and a dummy cell is provided at an intersection of a dummy word line and a dummy bit line. A delay circuit delays a signal read into the dummy bit line to generate a sense amplifier activating signal. A sense amplifier circuit starts an operation based on a change in the sense amplifier activating signal, and detects/amplifies a signal read out from the memory cell into the bit line. The delay circuit is configured having a first logical gate circuit and a second logical gate circuit alternately cascade-connected. A second delay time is longer than a first delay time, the second delay time being a time required for an output signal of the second logical gate circuit to switch from a first logical state to a second logical state, and a first delay time being a time required for an output signal of the first logical gate circuit to switch from a first logical state to a second logical state.

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14-06-2012 дата публикации

Semiconductor memory device

Номер: US20120147687A1
Автор: Toshiaki Douzaka
Принадлежит: Toshiba Corp

A row decoder is disposed on a side of a memory cell array in a column direction and supplies one of word lines with a first drive signal for selecting one of memory cells. A dummy word line is formed extending in the column direction. A dummy bit line is formed extending in a row direction. At least one of the dummy word line and the dummy bit line is disposed outside of the memory cell array. The row decoder outputs a second drive signal toward a sense amplifier circuit via the dummy bit line and the dummy word line.

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28-06-2012 дата публикации

Complementary read-only memory (rom) cell and method for manufacturing the same

Номер: US20120163063A1
Автор: Jitendra Dasani
Принадлежит: STMICROELECTRONICS PVT LTD

A complementary read-only memory (ROM) cell includes a transistor; and a bit line and a complementary bit line adjacent to the transistor; wherein a drain terminal of the transistor is connected to one of the bit line and the complementary bit line based on data programmed in the ROM cell.

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28-06-2012 дата публикации

Method for writing data in semiconductor storage device and semiconductor storage device

Номер: US20120163089A1
Автор: Katsutoshi Saeki
Принадлежит: Lapis Semiconductor Co Ltd

A method for writing data in a semiconductor storage device and a semiconductor storage device are provided, that can reduce variations in readout current from a sub storage region which serves as a reference cell for the memory cells of the semiconductor storage device, thereby preventing an improper determination from being made when determining the readout current from a memory cell. In the method, data is written on a memory cell in two data write steps by applying voltages to the first and second impurity regions of the memory cell, the voltages being different in magnitude from each other.

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05-07-2012 дата публикации

Differential data sensing

Номер: US20120169378A1
Принадлежит: STMICROELECTRONICS PVT LTD

A first sensing circuit has input terminals coupled to a true differential signal line and a complementary differential signal line. A second sensing circuit also has input terminals coupled to said true signal and said complementary signal. Each sensing circuit has a true signal sensing path and a complementary signal sensing path. The first sensing circuit has an imbalance that is biased towards the complementary signal sensing path, while the second sensing circuit has an imbalance that is biased towards the true signal sensing path. Outputs from the first and second sensing circuits are processed by a logic circuit producing an output signal that is indicative of whether there a sufficient differential signal for sensing has been developed between the true differential signal line and the complementary differential signal line.

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26-07-2012 дата публикации

Timing adjustment circuit for a memory interface and method of adjusting timing for memory interface

Номер: US20120188833A1
Принадлежит: Toshiba Corp

According to one embodiment, a timing adjustment circuit for a memory interface is presented. The circuit is provided with a gate circuit, an original gate signal generation circuit, a high impedance prevention unit, an impedance control unit and a gate leveling circuit. The gate circuit performs gating of a data strobe signal outputted from a memory. The original gate signal generation circuit generates an original gate signal based on information of a read latency and a burst length. The high impedance prevention unit to prevent the data strobe signal from being in a high impedance state. The impedance control unit controls execution and release of operation of the high impedance prevention unit. The gate leveling circuit outputs a timing adjusted gate signal to the gate circuit based on the original gate signal and the data strobe signal.

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23-08-2012 дата публикации

Semiconductor memory device for minimizing mismatch of sense amplifier

Номер: US20120213025A1
Автор: Dong Chul Koo
Принадлежит: Hynix Semiconductor Inc

A semiconductor memory device is provided. The semiconductor memory device includes a cross-coupled latch type sense amplifier and a buffer that prevents mismatch. The buffer is formed between PMOS transistors and NMOS transistors of the sense amplifier so that mismatch for transistors operating in pair can be minimized.

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13-09-2012 дата публикации

Maintenance of amplified signals using high-voltage-threshold transistors

Номер: US20120230140A1
Автор: Simon Lovett
Принадлежит: Micron Technology Inc

Systems, apparatus, memory devices, sense amplifiers and methods are provided, such as a system that includes an input node, a first transistor having a gate that couples to the input node, and a second transistor having another gate that couples to the input node. In one or more embodiments, the second transistor has a greater activation voltage threshold than does the first transistor and the first transistor amplifies a signal that is present on the input node. In one such embodiment, after the first transistor amplifies the signal, the second transistor maintains the amplified signal on the input node while the first transistor is deactivated.

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29-11-2012 дата публикации

Advanced memory device having improved performance, reduced power and increased reliability

Номер: US20120300563A1
Принадлежит: International Business Machines Corp

An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

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20-12-2012 дата публикации

Low voltage sensing scheme having reduced active power down standby current

Номер: US20120320687A1
Автор: Tae Kim
Принадлежит: Individual

A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL* nodes. The clamping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

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28-02-2013 дата публикации

High speed multiple memory interface i/o cell

Номер: US20130049799A1
Принадлежит: LSI Corp

A calibration circuit includes an amplifier, a current steering digital-to-analog converter (DAC), a comparator, a slew calibration network, and an on-die termination (ODT) network. The amplifier generally has a first input, a second input, and an output. The first input generally receives a reference signal. The current steering digital-to-analog converter (DAC) generally has a first input coupled to the output of the amplifier, a first output coupled to the second input of the amplifier, and a second output coupled to a circuit node. The comparator generally has a first input receiving the reference signal, a second input coupled to the circuit node, and an output at which an output of the calibration circuit may be presented. The slew calibration network is generally coupled to the circuit node and configured to adjust a slew rate of the calibration circuit. The on-die termination (ODT) network is generally coupled to the circuit node.

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07-03-2013 дата публикации

Amplifiers using gated diodes

Номер: US20130057347A1
Принадлежит: International Business Machines Corp

A circuit comprises a control line and a two terminal semiconductor device having a first terminal is coupled to a signal line, and a second terminal is coupled to the control line. The semiconductor device has a capacitance when a voltage on the first terminal is above a threshold and has a smaller capacitance when a voltage on the first terminal is below the threshold. A signal is placed on the signal line and a voltage on the control line is modified. When the signal falls below the threshold, the semiconductor device acts as a very small capacitor and the output will be a small value. When the signal is above the threshold, the semiconductor device acts as a large capacitor and the output will be influenced by the signal and the modified voltage on the control line and the signal is amplified.

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28-03-2013 дата публикации

Semiconductor device

Номер: US20130077397A1
Принадлежит: Toshiba Corp

A semiconductor device according to an embodiment includes: a first transistor including a gate connected to a first interconnection, a first source, and a first drain, one of the first source and the first drain being connected to a second interconnection; and a second transistor including a gate structure, a second source, and a second drain, one of the second source and second drain being connected to a third interconnection and the other of the second source and second drain being connected to a fourth interconnection. The gate structure includes a gate insulation film, a gate electrode, and a threshold-modulating film provided between the gate insulation film and the gate electrode to modulate a threshold voltage, the other of the first source and first drain of the first transistor is connected to the gate electrode.

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28-03-2013 дата публикации

Memory storage device, memory controller, and temperature management method

Номер: US20130080680A1
Автор: Chien-Hua Chu
Принадлежит: Phison Electronics Corp

A temperature management method suitable for a memory storage device having a rewritable non-volatile memory module and a memory controller used for controlling the rewritable non-volatile memory module are provided. The temperature management method includes detecting and determining whether the hot-spot temperature of the memory storage device is higher than a predetermined temperature; and when affirmative, making the memory controller execute a cooling process, so as to reduce the hot-spot temperature of the memory storage device. Accordingly, the problem of heat buildup of the (rewritable non-volatile) memory storage device can be mitigated, as well as the problems of data loss and device aging of the (rewritable non-volatile) memory storage device.

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04-04-2013 дата публикации

TEMPERATURE DETECTION CIRCUIT OF SEMICONDUCTOR MEMORY APPARTUS

Номер: US20130083616A1
Принадлежит: HYNIX SEMICONDUCTOR INC.

A temperature detection circuit of a semiconductor memory apparatus includes a fixed period oscillator, a temperature variable signal generating unit and a counting unit. The oscillator is configured to generate a fixed period oscillator signal when an enable signal is enabled. The temperature variable signal generating unit is configured to generate a temperature variable signal whose enable interval varies based on temperature variations, when the enable signal is enabled. The counting unit is configured to count the oscillator signal during the enable interval of the temperature variable signal to generate a temperature information signal. 1. A temperature detection circuit of a semiconductor memory apparatus comprising:a temperature variable signal generating unit configured to enable a temperature variable signal when an enable signal is enabled, and to charge a capacitor, and to discharge the capacitor when a voltage level of the capacitor is increased to above a reference voltage level, and to disable the temperature variable signal when the voltage level of the capacitor is decreased to below the reference voltage level; anda counting unit configured to count an oscillator signal during an enable interval of the temperature variable signal to generate a temperature information signal.2. The temperature detection circuit of claim 1 , wherein the temperature information signal includes a mufti-bit code.3. The temperature detection circuit of claim 2 , wherein the temperature variable signal generating unit includes:a charging unit configured to apply an external voltage to the capacitor to charge the capacitor when the enable signal is enabled; anda discharging unit configured to discharge the capacitor when the voltage level of the capacitor is increased to above the reference voltage level, andthe temperature variable signal generating unit is configured to enable the temperature variable signal when the enable signal is enabled, and to disable the ...

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18-04-2013 дата публикации

Complementary Reference Method for High Reliability Trap-Type Non-Volatile Memory

Номер: US20130094299A1
Принадлежит: Halo LSI Inc

Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.

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18-04-2013 дата публикации

Complementary Reference Method for High Reliability Trap-Type Non-Volatile Memory

Номер: US20130094303A1
Принадлежит: HALO LSI, INC.

Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits. 1. A method of complementary pairing of memory cells comprising:providing a set of at least two reference cells per erase block wherein a first reference cell has a value of ‘1’ and a second reference cell has a value of ‘0’; andcomparing a selected memory cell in said erase block to said two reference cells to determine whether said memory cell has a value of ‘0’ or ‘1’.2. The method according to wherein said comparing is performed by a sense amplifier wherein said sense amplifier performs a subtraction-like function in order to determine whether said selected memory cell's signal is closer to said first or second reference signal.3. The method according to wherein said comparing is performed by a data latch wherein said data latch performs a subtraction-like function in order to determine whether said selected memory cell's signal is closer to said first or second reference signal.4. The method according to wherein said subtraction-like function is performed by a voltage subtractor circuit.5. The method according to wherein:a first sense amplifier compares said selected memory cell to said first reference cell;a second sense amplifier compares said selected memory cell to said second reference cell; anda third sense amplifier compares outputs from said first and second sense amplifiers to each other to find the output with the largest delta voltage or current.6. The method according to wherein said first claim 5 , second claim 5 , and third sense amplifiers are voltage sense amplifiers or current sense amplifiers.7. The method according to wherein:a first voltage subtractor compares said selected memory cell to said first reference cell;a second voltage subtractor compares said selected memory cell to said ...

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25-04-2013 дата публикации

Semiconductor memory device and method for driving the same

Номер: US20130100748A1
Автор: Yasuhiko Takemura
Принадлежит: Semiconductor Energy Laboratory Co Ltd

In a conventional DRAM, data read errors are more likely to occur along with miniaturization of DRAM. A small change in the potential of a first bit line is inverted by a first inverter constituted by an n-channel transistor and a p-channel transistor, and is output to a second bit line through a first selection transistor, which is a first switch. Since the potential of the second bit line is the inverse of the potential of the first bit line, the potential difference between the first bit line and the second bit line is increased. The increased potential difference is amplified by a known sense amplifier, a flip-flop circuit composed of the first inverter and a second inverter (constituted by an n-channel transistor and a p-channel transistor), or the like.

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25-04-2013 дата публикации

NANO-SENSE AMPLIFIER

Номер: US20130100749A1
Принадлежит: SOITEC

A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline addressing the cells of the series, and a reading stage that includes a sense transistor, the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter. 1. A sense amplifier (nSA) of a series of cells (Ci , Cj) of a memory , including:{'b': 1', '2, 'a writing stage comprising a CMOS inverter (T-T), the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline (LBL) addressing the cells of said series, and'}{'b': '3', 'a reading stage comprising a sense transistor (T), the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter,'}wherein one or more of the transistors are multigate transistors.2. The sense amplifier according to claim 1 , wherein at least one multigate transistor is a FinFET.3. The sense amplifier according to claim 1 , wherein the input of the writing stage is directly connected to the input terminal of the inverter claim 1 , said input terminal being intended to be connected to a main bitline (MBL) which will address a plurality of sense amplifiers in parallel.44. The sense amplifier according to claim 1 , wherein the reading stage comprises an additional transistor (T) complementary to the sense transistor claim 1 , the additional transistor and the sense transistor forming a CMOS inverter claim 1 , the input of which is connected to the output of the reading stage and the output of which is connected to the input of the inverter of ...

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02-05-2013 дата публикации

Memory Program Discharge Circuit of Bit Lines With Multiple Discharge Paths

Номер: US20130107637A1
Принадлежит:

A memory integrated circuit has an array of nonvolatile memory cells, bit lines accessing the array of nonvolatile memory cells, and bit line discharge circuitry. The bit lines have multiple discharge paths for a bit line at a same time, during a program operation. 1. An apparatus , comprising:an array of memory cells; a first discharge node coupled to discharge a charge on said at least one bit line; and', 'a second discharge node coupled to discharge a charge on said at least one bit line, the first discharge node and the second discharge nodes at different locations along said at least one bit line; and, 'a plurality of bit lines accessing the array of memory cells, at least one bit line of the plurality of bit lines each havingdischarge circuitry electrically connected to the first discharge node and the second discharge node of the at least one bit line coupled to provide multiple discharge paths, wherein the discharge circuitry coupled to the first discharge node and the discharge circuitry coupled to the second discharge node are controlled by different signals.2. The apparatus of claim 1 , further comprising:control circuitry providing the different signals for the at least one bit line of the plurality of bit lines at a same time.3. The apparatus of claim 1 , a first plurality of discharge transistors electrically connected to the first discharge nodes of the plurality of bit lines, such that different bit lines of the plurality of bit lines discharge the charge through different discharge transistors of the first plurality of discharge transistors, and', 'a second plurality of discharge transistors electrically connected to the second discharge nodes of the plurality of bit lines, such that different bit lines of the plurality of bit lines discharge the charge through different discharge transistors of the second plurality of discharge transistors., 'wherein the discharge circuitry includes4. The apparatus of claim 1 ,wherein the discharge path of the ...

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02-05-2013 дата публикации

MEMORY DEVICE, SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF

Номер: US20130107648A1
Принадлежит: ELPIDA MEMORY, INC.

A semiconductor memory device comprises a memory cell array, first and second bit lines, first and second amplifiers, and a sense amplifier control circuit. An amplifying element in the first sense amplifier amplifiers the signal of the first bit line and converts it into an output current. The second bit line is selectively connected to the first bit line via the first sense amplifier. A signal voltage decision unit in the second sense amplifier determines the signal level of the second bit line being supplied with the output current. The sense amplifier control circuit controls connection between the amplifying element and the unit in accordance with a determination timing, which switches the above connection from a connected state to a disconnected state at a first timing in a normal operation and switches in the same manner at a delayed second timing in a refresh operation. 1. A semiconductor device comprising:a word line;a local bit line;a first voltage line configured to be supplied with a first voltage;a memory cell coupled between the local bit line and the first voltage line, the memory cell including a first transistor of which a gate is coupled to the word line;a second voltage line configured to be supplied with a second voltage;a second transistor coupled between the local bit line and the second voltage line;a global bit line;a third voltage line configured to be supplied with a third voltage; andthird and fourth transistors coupled in series between the global bit line and the third voltage line, a gate of the third transistor being coupled to the local bit line.2. The semiconductor device as claimed in claim 1 , wherein the fourth transistor is configured to be controlled to maintain an on-state during a first time period when the semiconductor device is in a first mode claim 1 , and to maintain the on-state during a second time period when the semiconductor device is in a second mode claim 1 , the first and second time periods being different from ...

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02-05-2013 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20130107652A1
Автор: YOON Jae Man
Принадлежит:

A semiconductor memory device including a memory cell array including at least one word line, at least one cell bit line, and at least one memory cell that is disposed in a region where the at least one word line and the at least one cell bit line cross each other; at least one sense amplifier that is disposed above or below the memory cell array to be overlapped with the memory cell array in a planar fashion, connected to at least one bit line connected to the at least one cell bit line, and at least one complementary bit line corresponding to the at least one bit line, and senses data stored in the at least one memory cell; a decompression unit for decompressing a signal having a lower voltage level from among a signal of the at least one bit line and a signal of the at least one complementary bit line; a boosting unit for boosting a signal having a higher voltage level from among the signal of the at least one bit line and the signal of the at least one complementary bit line; and an equalizing unit for equalizing the signal of the at least one bit line and the signal of the at least one complementary bit line. 1. A semiconductor memory device comprising:a memory cell array that is disposed at a first layer and comprises at least one word line, at least one cell bit line, and at least one memory cell which is disposed in a region where the at least one word line and the at least one cell bit line cross each other;at least one sense amplifier configured to sense data stored in the at least one memory cell, the at least one sense amplifier being disposed at a second layer different from the first layer and connected to at least one bit line and at least one complementary bit line, the at least one bit line being connected to the at least one cell bit line,output device that is connected to the at least one cell bit line,wherein the bit line is connected to the output device via the cell bit line.2. (canceled)3. The semiconductor memory device of claim 1 , wherein ...

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09-05-2013 дата публикации

MEMORY METHODS AND SYSTEMS WITH ADIABATIC SWITCHING

Номер: US20130114353A1
Принадлежит: RAMBUS INC.

A memory system includes wordlines and pairs of complementary bitlines that provide access to memory storage elements. Capacitive and resistive loads associated with wordlines and bitlines are driven relatively slowly between voltage levels to reduce peak current, and thus power dissipation. Power dissipation is further reduced by charging complementary bitlines at substantially different rates. 1. A memory comprising:a voltage generator to provide a varying supply voltage; anda memory core having storage cells and sense amplifiers, each sense amplifier having an N-sense supply node to receive a constant supply voltage, and a P-sense supply node coupled to the voltage generator to receive the varying supply voltage.2. The memory of claim 1 , further comprising:a memory interface coupled to the memory core to issue memory-control signals; andtiming-control circuitry coupled to the memory interface and the voltage generator, the timing-control circuitry to synchronize the varying supply voltage with the memory-control signals.3. The memory of claim 2 , wherein the voltage generator is to provide a second varying supply voltage claim 2 , the memory core includes a wordline claim 2 , the memory-control signals include a wordline-select signal claim 2 , and the timing-control circuitry synchronizes the wordline-select signal with the second varying supply voltage.4. The memory of claim 3 , wherein the second varying supply voltage is sinusoidal.5. The memory of claim 2 , wherein the varying supply voltage is sinusoidal.6. The memory of claim 1 , the memory core including claim 1 , for each sense amplifier claim 1 , a complementary pair of bitlines claim 1 , each bitline connected to a respective one of the sense nodes; and wherein each sense amplifier amplifies a voltage difference between the respective pair of complementary sense nodes by selectively connecting one of the bitlines to the N-sense supply node while connecting the other of the bitlines to the P-sense ...

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06-06-2013 дата публикации

INPUT-OUTPUT LINE SENSE AMPLIFIER HAVING ADJUSTABLE OUTPUT DRIVE CAPABILITY

Номер: US20130141993A1
Принадлежит: MICRON TECHNOLOGY, INC.

An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capacities to tailor the output drive of the sense amplifier. 1. A apparatus comprising:a first plurality of sense amplifiers, a first sense amplifier of the first plurality of sense amplifiers configured to provide a first output signal based on a first sensed state, wherein the first sense amplifier has a first output current drive setting;a second plurality of sense amplifiers, a second sense amplifier of the plurality of sense amplifiers configured to provide a second output signal based on a second sensed state, wherein the second sense amplifier has a second output drive setting, the second output current drive setting different than the first output current drive setting; anda data output circuit coupled to the first plurality of sense amplifiers and to the second plurality of sense amplifiers, the data output circuit configured to receive the first output signal and the second output signal and to provide output signals based on at least one of the first output signal or the second output signal.2. The apparatus of claim 1 , wherein the first sense amplifier comprises a first current driver configured to provide the first output signal having the first output current drive setting claim 1 , and wherein the second sense amplifier comprises a second current driver configured to provide the second output signal having the second output current drive setting.3. The apparatus of claim 2 , wherein the first current driver comprises a source follower stage comprising a plurality of transistors claim 2 , wherein each transistor of the plurality of transistors is coupled to a respective switch pair claim 2 , wherein the respective switch pair is configured to activate an associated transistor of the ...

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13-06-2013 дата публикации

Sense amplifier with offset current injection

Номер: US20130148432A1
Принадлежит: Atmel Corp

A sense amplifier includes a sense input node, a current mirror circuit to mirror the current on the sense input node, and a result output node. A current source supplies an offset current. The sense amplifier increases the current on the sense input node by the offset current and reduces the offset current from the mirrored current at the result output node.

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20-06-2013 дата публикации

STORAGE DEVICE

Номер: US20130155790A1
Автор: Atsumi Tomoaki

Noise attributed to signals of a word line, in first and second bit lines which are overlapped with the same word line in memory cells stacked in a three-dimensional manner is reduced in a storage device with a folded bit-line architecture. The storage device includes a driver circuit including a sense amplifier, and first and second memory cell arrays which are stacked each other. The first memory cell array includes a first memory cell electrically connected to the first bit line and a first word line, and the second memory cell array includes a second memory cell electrically connected to the second bit line and a second word line. The first and second bit lines are electrically connected to the sense amplifier in the folded bit-line architecture. The first word line, first bit line, second bit line, and second word line are disposed in this manner over the driver circuit. 1. A semiconductor device comprising:a driver circuit comprising a sense amplifier, the sense amplifier being electrically connected to a first bit line and a second bit line;a first memory cell array comprising a first memory cell, the first memory cell being electrically connected to the first bit line and a first word line; anda second memory cell array comprising a second memory cell over the first memory cell array, the second memory cell being electrically connected to the second bit line and a second word line,wherein the first bit line is provided over the first word line,wherein the second word line is provided over the second bit line, andwherein the first memory cell overlaps with the second memory cell.2. The semiconductor device according to claim 1 , wherein the first memory cell array is provided over the driver circuit.3. The semiconductor device according to claim 2 , wherein the driver circuit comprises a transistor comprising a channel formation region in a single-crystal semiconductor substrate.4. The semiconductor device according to claim 1 , wherein each of the first ...

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20-06-2013 дата публикации

SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE

Номер: US20130155798A1
Автор: KAJIGAYA Kazuhiko
Принадлежит: ELPIDA MEMORY, INC.

A semiconductor device is disclosed which comprises first and second local bit lines coupled to a plurality of memory cells arranged in first and second areas, respectively, a differential type local sense amplifier amplifying a voltage difference between the first and second local bit lines, a global bit line arranged in an extending direction of the first and second local bit lines, and first and second switches controlling electrical connections between the first and second local bit lines and the global bit line, respectively. 1. A semiconductor device comprising:a first local bit line coupled to a plurality of memory cells arranged in a first area;a second local bit line coupled to a plurality of memory cells arranged in a second area;a local sense amplifier of a differential type amplifying a voltage difference between the first and second local bit lines;a global bit line arranged in an extending direction of the first and second local bit lines;a first switch controlling an electrical connection between the first local bit line and the global bit line; anda second switch controlling an electrical connection between the second local bit line and the global bit line.2. The semiconductor device according to claim 1 , further comprising a global sense amplifier of a single-ended type connected to one end of the global bit line.3. The semiconductor device according to claim 1 , further comprising a control circuit controlling the first and second switches claim 1 ,wherein in response to a selected memory cell of the memory cells, the control circuit renders one of the first and second switches conductive and renders the other thereof non-conductive.4. The semiconductor device according to claim 3 , wherein the control circuit renders the first switch conductive when the selected memory cell is in the first area claim 3 , and renders the second switch conductive when the selected memory cell is in the second area.5. The semiconductor device according to claim 4 , ...

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27-06-2013 дата публикации

SYSTEMS AND METHODS OF NON-VOLATILE MEMORY SENSING INCLUDING SELECTIVE/DIFFERENTIAL THRESHOLD VOLTAGE FEATURES

Номер: US20130163363A1
Автор: SAHA Samar, Tran Hieu Van
Принадлежит:

Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween, an insulating layer over the channel region, and a gate portion of the insulating layer. Moreover, with regard to the device, the shape of the insulating layer and/or the shape or implantation of a junction region are of varied dimension as between the gate-to-drain and gate-to-source junctions to provide differential threshold voltages between them. 18.-. (canceled)9. A sensing circuit comprising:a data column including an output voltage node, a memory cell, a first PMOS transistor that is diode-connected, and a first differential threshold NMOS transistor having a drain connected to a drain of the first PMOS transistor to form the output voltage node and a source connected to a first node; anda first memory column comprising a second differential threshold NMOS transistor having a drain connected to the first node; anda second memory column connected to the first node in parallel with the first memory column, wherein each memory column includes a differential threshold MOS transistor;wherein one or more of the differential threshold transistors are transistors that each have a gate-to-source threshold voltage that differs from a gate-to-drain threshold voltage.10. The sensing circuit of further comprising one or more additional memory columns.11. A sensing circuit or differential sense amplifier comprising:a reference column including a reference voltage node, a reference memory cell, a first differential threshold PMOS transistor that is diode-connected and has a drain connected to the reference voltage node, and a first differential threshold NMOS transistor having a drain connected to the reference ...

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04-07-2013 дата публикации

Sense-amplifier circuit of memory and calibrating method thereof

Номер: US20130170309A1
Автор: shi-wen Chen
Принадлежит: United Microelectronics Corp

A sense-amplifier circuit of a memory, which includes a sense-amplifier unit, a first switch unit and a second switch unit. The sense-amplifier unit is constituted by a plurality of transistor switches and having a first, a second, a third and a fourth connection terminal. The first switch unit is configured to be parallel coupled between the first and second connection terminals of the sense-amplifier unit. The second switch unit is configured to be parallel coupled between the third and fourth connection terminals of the sense-amplifier unit. The first and second switch units each are constituted by a plurality of transistor switches coupled in parallel and are configured to control each of the parallel-coupled transistor switches on or off in the first and second switch units so as to calibrate a sensing range of the sense-amplifier unit. A calibrating method for a sense-amplifier circuit of a memory is also provided.

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04-07-2013 дата публикации

Reducing power consumption of memory

Номер: US20130173944A1
Принадлежит: LSI Corp

Described embodiments provide for a memory system having a transparent source bias (TSB) circuit. A monitor in the memory system monitors a process, temperature, and/or a leakage current of the memory. The system determines whether at least one of the monitored process, temperature, and leakage current reaches a corresponding threshold. The threshold is set based on a power budget of the memory. If the corresponding threshold is reached, the TSB is disabled and the memory operates at a relatively high speed. If the corresponding threshold is not reached, the TSB is enabled and the memory operates at a relatively law speed.

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11-07-2013 дата публикации

SYSTEM AND METHOD OF REFERENCE CELL TESTING

Номер: US20130176774A1
Принадлежит: QUALCOMM Incorported

Systems and methods of testing a reference cell in a memory array are disclosed. In a particular embodiment, a method includes coupling a first reference cell of a first reference cell pair of a memory array to a first input of a first sense amplifier of the memory array. The method also includes providing a reference signal to a second input of the first sense amplifier. The reference signal is associated with a second reference cell pair of the memory array. 1. A method comprising:coupling a first reference cell of a first reference cell pair of the a memory array to a first input of a first sense amplifier of the memory array; andproviding a reference signal to a second input of the first sense amplifier, wherein the reference signal is associated with a second reference cell pair of the memory array.2. The method of claim 1 , wherein the first sense amplifier includes comparator circuitry configured to output a comparator output value that is dependent upon a first signal received at the first input of the first sense amplifier and upon a second signal received at the second input of the first sense amplifier.3. The method of claim 1 , further comprising after coupling the first reference cell to the first input of the first sense amplifier and providing the reference signal to the second input of the first sense amplifier claim 1 , determining whether the first reference cell is functional by comparing an output of the first sense amplifier to a first predetermined threshold.4. The method of claim 3 , further comprising when the first reference cell is determined to be non-functional claim 3 , replacing use of the first reference cell in the memory array with use of a redundant reference cell of the memory array.5. The method of claim 3 , further comprising:coupling a second reference cell of the first reference cell pair to a first input of a second sense amplifier of the memory array;providing a second reference signal to a second input of the second sense ...

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18-07-2013 дата публикации

SYSTEM AND METHOD FOR MODIFYING ACTIVATION OF A SENSE AMPLIFIER

Номер: US20130182491A1
Принадлежит: MARVELL WORLD TRADE LTD.

Systems, methods, and other embodiments associated with controlling a sense amplifier in a memory device are described. According to one embodiment, an apparatus includes a signal generator configured to generate a sense enable signal that activates a sense amplifier of a memory cell in a memory device. The apparatus includes a dummy memory cell connected to a current mirror circuit that is configured to detect a timing variation in the dummy memory cell from a predefined timing and to alter a timing of the sense enable signal based, at least in part, on the timing variation. The apparatus also includes a controller configured to modify the timing of the sense enable signal by selectively enabling one or more of a plurality of semiconductor gates in the current mirror circuit. The plurality of semiconductor gates are connected in parallel. 1. An apparatus , comprising:a signal generator configured to generate a sense enable signal that activates a sense amplifier of a memory cell in a memory device;a dummy memory cell connected to a current mirror circuit that is configured to detect a timing variation in the dummy memory cell from a predefined timing and to alter a timing of the sense enable signal based, at least in part, on the timing variation; anda controller configured to modify the timing of the sense enable signal by selectively enabling one or more of a plurality of semiconductor gates in the current mirror circuit, where the plurality of semiconductor gates are connected in parallel.2. The apparatus of claim 1 , wherein the memory device is a static random access memory (SRAM) and the apparatus is integrated with the SRAM.3. The apparatus of claim 1 , wherein the controller is configured to modify the timing of the sense enable signal to advance when the sense enable signal occurs.4. The apparatus of claim 3 , wherein the controller is configured to advance when the sense enable signal occurs by an amount based on a number of the plurality of semiconductor ...

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25-07-2013 дата публикации

SYMMETRICALLY OPERATING SINGLE-ENDED INPUT BUFFER DEVICES AND METHODS

Номер: US20130187703A1
Принадлежит: MICRON TECHNOLOGY, INC.

Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One example buffer has a symmetrical response to a single input signal applied to the first input terminal by mimicking the transition of a signal applied to the second input terminal in the opposite direction. The buffer includes two amplifier circuits structured to be complementary with respect to each other. Each of the amplifier circuits includes a first transistor having a first input node that receives an input signal transitioning across a range of high and low voltage levels, and a second transistor having a second input node that receives a reference signal. The first input node is coupled to the second transistor through a capacitor to mimic the second input node transitioning in the direction opposite to the transition of the input signal. 1. An apparatus , comprising:a first transistor configured to receive an input signal and adjust a resistance of a second transistor based, at least in part, on the input signal, the first transistor configured to provide an output signal based, at least in part, on the input signal,wherein a rate at which the output signal is provided is based, at least in part, on a magnitude of the resistance of the second transistor.2. The apparatus of claim 1 , wherein the resistance is an ON-resistance.3. The apparatus of claim 1 , wherein the input signal comprises an analog signal and the output signal comprises a digital signal.4. The apparatus of claim 3 , wherein the first transistor is configured to provide the output signal having a first state when the input signal has a voltage less than a reference voltage and to provide the output signal having a second state when the input signal has a voltage greater than the reference voltage.5. The apparatus of claim 1 , wherein a terminal of the first transistor and a terminal of the second transistor are capacitively coupled.6. The apparatus of claim 1 , ...

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01-08-2013 дата публикации

Spurious induced charge cleanup for one time programmable (otp) memory

Номер: US20130194885A1
Автор: Jack Z. Peng
Принадлежит: Jack Z. Peng

A high density, low voltage, and low-power one time programmable (OTP) memory is based on core cells with a one transistor design. A CLEAN pulse is directed to a single shunt device at the output of the column decoder so spurious charges that may have been stored in the floating nodes can be cleaned up. Such arrangement also allows for the simultaneous initialization of bit lines, data lines, and sensing lines to zero. Core area layout size is substantially reduced, and operational power requirements are exceeding low making these particularly suitable in HF and UHF RFID applications.

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08-08-2013 дата публикации

MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATION

Номер: US20130201770A1
Принадлежит:

Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated. 1. A method of operation within a memory component , the method comprising:receiving, during a first command reception interval, a row command and a row address, the row address indicating a row of storage cells within the memory component;decoding the row address upon receiving the row command to select a row of storage cells within the memory component;receiving, during a second command reception interval and after decoding the row address has commenced, a first column command and a first column address, the first column address indicating a first column of data within a first subrow of storage cells included within the row of storage cells, and the first column command indicating a memory access operation to be carried out with respect to the first column of data; andtransferring a first subrow of data, including the first column of data, from the first subrow of storage cells to a first set of sense amplifiers in response to the first column command.2. The method of further comprising executing the memory access operation indicated by the first column command with respect to the first column of data after transferring the first subrow of data from the first subrow of storage cells to the first set of sense amplifiers.3. The method of wherein executing the memory access operation comprises transferring the first column of data from the first set of sense amplifiers to an output driver of the memory component in a memory read operation claim 2 , the output driver to output the first column of data from the memory component claim 2 , wherein an elapsed time between receipt of the first column ...

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22-08-2013 дата публикации

Spin-transfer torque memory self-reference read method

Номер: US20130215674A1
Принадлежит: SEAGATE TECHNOLOGY LLC

A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage. Then applying a low resistance state polarized write current through the magnetic tunnel junction data cell, forming a low second resistance state magnetic tunnel junction data cell. A second read current is applied through the low second resistance state magnetic tunnel junction data cell to forming a second bit line read voltage. The method also includes comparing the first bit line read voltage with the second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state.

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22-08-2013 дата публикации

Method for semiconductor memory interface device with noise cancellation circuitry having phase and gain adjustments

Номер: US20130215694A1
Принадлежит: Individual

A memory interface circuit is provided, comprising: a first signal output circuit configured to output a first signal via a first signal line to a first I/O terminal; a second signal output circuit configured to output a second signal via a second signal line to a second I/O terminal; and a noise cancellation circuit having at least one phase adjusting element and at least one gain adjusting element to reduce a noise signal induced on the second signal line due to the presence of the first signal on the first signal line, wherein the second signal line is disposed adjacent to the first signal line.

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22-08-2013 дата публикации

SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE

Номер: US20130215698A1
Автор: NAGATA Kyoichi
Принадлежит: ELPIDA MEMORY, INC.

A semiconductor device comprises first and second global bit lines, a sense amplifier amplifying a voltage difference of the first and second global bit lines, first and second local bit lines corresponding to the first and second global bit lines, and first and second hierarchical switches controlling electrical connections between the first and second global bit lines and the first and second local bit line. In a precharge operation prior to accessing a selected memory cell belong to the first local bit lines, a pair of the first and second hierarchical switches, which is not in an access path, is kept ON, and remaining ones thereof are kept OFF. Subsequently, in an access to the selected memory cell, a first hierarchical switch of the pair is switched from ON to OFF, and simultaneously a first hierarchical switches in the access path is switched from OFF to ON. 1. A semiconductor device comprising:a first global bit line;a second global bit line;a sense amplifier amplifying a voltage difference between the first and second global bit lines;a plurality of first local bit lines arranged corresponding to the first global bit line;a plurality of second local bit lines arranged corresponding to the second global bit line;a plurality of first hierarchical switches controlling electrical connections between the first global bit line and the first local bit lines, respectively;a plurality of second hierarchical switches controlling electrical connections between the second global bit line and the second local bit lines, respectively; anda control circuit controlling an operation of the sense amplifier and operations of the first and second hierarchical switches,wherein, in a precharge operation prior to an access to a selected memory cell coupled to one of the first local bit lines, the control circuit keeps a pair of the first and second hierarchical switches in an ON-state and keeps remaining ones of the first and second hierarchical switches in an OFF-state, the pair ...

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22-08-2013 дата публикации

Semiconductor memory device changing refresh interval depending on temperature

Номер: US20130215700A1
Принадлежит: Fujitsu Semiconductor Ltd

A semiconductor memory device includes a memory core circuit having memory cells for storing data, a circuit configured to refresh the memory core circuit at a refresh interval, a temperature detecting unit configured to detect temperature, and a control circuit configured to shorten the refresh interval immediately in response to detection of a predetermined temperature rise by the temperature detecting unit and to elongate the refresh interval after refreshing every one of the memory cells at least once in response to detection of a temperature drop by the temperature detecting unit.

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22-08-2013 дата публикации

Write data mask method and system

Номер: US20130219134A1
Принадлежит: ATI TECHNOLOGIES ULC

A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command.

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29-08-2013 дата публикации

Oscillator based on a 6T SRAM for measuring the Bias Temperature Instability

Номер: US20130222071A1
Принадлежит: National Chiao Tung University NCTU

The present invention provides an oscillator which is based on a 6T SRAM for measuring the Bias Temperature Instability. The oscillator includes a first control unit, a first inverter, a second control unit, and a second inverter. The first control unit is coupled with the first inverter. The second control unit is coupled with the second inverter. The first control unit and the second control unit is used to control the first inverter and the second inverter being selected, biased, and connected respectively, so that the NBTI and the PBTI of the SRAM can be measured separately, and the real time stability of the SRAM can be monitored immediately.

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29-08-2013 дата публикации

NONVOLATILE MEMORY DEVICE HAVING ADJUSTABLE PROGRAM PULSE WIDTH

Номер: US20130223143A1
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A method of programming a nonvolatile memory device comprises determining a temperature condition of the nonvolatile memory device, determining a program pulse period according to the temperature condition, supplying a program voltage to a selected word line using the program pulse period, and supplying a pass voltage to unselected word lines while supplying the program voltage to the selected word line. 1. A method of programming a nonvolatile memory device , comprising:determining a temperature condition of the nonvolatile memory device;determining a program pulse period according to the temperature condition;supplying a program voltage to a selected word line using the program pulse period; andsupplying a pass voltage to unselected word lines while supplying the program voltage to the selected word line.2. The method of claim 1 , further comprising increasing the program pulse period in response to a temperature decrease of the nonvolatile memory.3. The method of claim 1 , further comprising decreasing the program pulse period in response to a temperature increase of the nonvolatile memory device.4. The method of claim 1 , further comprising adjusting the program pulse period according to a physical location of the selected word line.5. The method of claim 4 , wherein a program pulse period determined where the selected word line is an uppermost word line adjacent to a bit line is shorter than a program pulse period determined where the selected word line is not the uppermost word line.6. The method of claim 1 , wherein the program pulse period determined according to a temperature variation becomes relatively shorter after a predetermined number of program loops.7. A nonvolatile memory device comprising:a memory cell array comprising memory cells arranged in word lines and bit lines;an address decoder configured to select one of the word lines of the memory cell array;a temperature code generator circuit configured to detect a current temperature of the ...

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29-08-2013 дата публикации

SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE

Номер: US20130223164A1
Принадлежит: RENESAS ELECTRONICS CORPORATION

To improve reading accuracy of a sense amplifier circuit and a semiconductor memory device. A sense amplifier circuit includes an N type FET which is a sensing transistor connected between a power supply and a ground via a data line that extends to a memory cell, a resistance element that is connected between a gate of the sensing transistor and the power supply, and a capacitance element that is connected between the gate of the sensing transistor and the ground. 1. A sense amplifier circuit comprising:a sensing transistor that is connected between a first power supply and a second power supply through a memory cell connection line that extends to a memory cell;a resistance element that is connected between the first power supply and a control terminal of the sensing transistor; anda capacitance element that is connected between the second power supply and the control terminal of the sensing transistor.2. The sense amplifier circuit according to claim 1 , wherein a first capacity from the sensing transistor to the second power supply through the capacitance element is equal to a second capacity from the sensing transistor to the second power supply through the memory cell connection line.3. The sense amplifier circuit according to claim 1 , comprising a current-mirror circuit that mirrors a current flowing through the sensing transistor claim 1 ,wherein a first capacity from the sensing transistor to the second power supply through the capacitance element is based on a second capacity from the sensing transistor to the second power supply through the memory cell connection line and a third capacity of a circuit in an output side of the current-mirror circuit.4. The sense amplifier circuit according to claim 3 , wherein the third capacity is a capacity in which a parasitic capacity of an output-side transistor of the current-mirror circuit claim 3 , a whole parasitic capacity of an output line from the output-side transistor to an output inverter which is an output ...

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05-09-2013 дата публикации

Systems, memories, and methods for repair in open digit memory architectures

Номер: US20130229883A1
Принадлежит: Micron Technology Inc

A memory with extra digit lines in full size end arrays with an open digit architecture, which can use the extra digit lines to form repair cells. In one example, folded digit sense amplifiers are connected to an end array with an open digit architecture such that each sense amplifier corresponds to a group of four digit lines. Two digit lines of the group connect to two open digit sense amplifiers and the other two digit lines connect to the corresponding folded digit sense amplifier. A repair method can be performed on memories including the end arrays with folded digit sense amplifiers. A row in a core array including a replaceable IO is activated and a row in an end array is activated. The repair cells in the end array can be sensed by the folded digit sense amplifiers to generate a replacement IO, which is selected rather than the replaceable IO.

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05-09-2013 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20130229887A1
Автор: KURODA Naoki
Принадлежит: Panasonic Corporation

In a static random access memory (SRAM) device having a hierarchical bit line architecture, a local sense amplifier (SA) circuit includes P-channel transistors which precharge local bit lines connected to memory cells, P-channel transistors each having a gate connected to a corresponding one of the local bit lines and a drain connected to a corresponding one of global bit lines, and N-channel transistors each having a gate connected to a corresponding one of the global bit lines and a drain connected to a corresponding one of the local bit lines. As a result, restore operation to a non-selected memory cell during write operation can be achieved without the need of a fine timing control, the speed of read operation by a feedback function can be increased, and the area can be reduced. 2. The semiconductor memory device of claim 1 , whereinthe first and second signal lines are local bit lines,the third and fourth signal lines are global bit lines,the local and global bit lines form a hierarchical bit line architecture.3. The semiconductor memory device of claim 1 , wherein a first cell transistor of the first conductivity type having a source connected to the first power supply potential, a drain connected to a first memory node, and a gate connected to a second memory node,', 'a second cell transistor of the first conductivity type having a source connected to the first power supply potential, a drain connected to the second memory node, and a gate connected to the first memory node,', 'a third cell transistor of the second conductivity type having a source connected to the second power supply potential, a drain connected to the first memory node, and a gate connected to the second memory node,', 'a fourth cell transistor of the second conductivity type having a source connected to the second power supply potential, a drain connected to the second memory node, and a gate connected to the first memory node,', 'a fifth cell transistor of the second conductivity type ...

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12-09-2013 дата публикации

OUTPUT DRIVING CIRCUIT CAPABLE OF DECREASING NOISE, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME

Номер: US20130235675A1
Автор: Cho Young Chul
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

An output driving circuit includes a first pull-up transistor, a first pull-down transistor and a second pull-down transistor. The first pull-up transistor is configured to generate a first output signal at the output node in response to a first control signal. The first pull-down transistor is configured to generate a second output signal at the output node in response to a second control signal. The second pull-down transistor is configured to connect the output node to the first ground voltage in response to a third control signal. The memory device including the output driving circuit may be insensitive to noise and may have little data transmission error.

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12-09-2013 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20130235676A1
Автор: Takagiwa Teruo
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A semiconductor memory device according to an embodiment includes a memory cell array that includes a plurality of cell columns each configured by a plurality of memory cells, and a column control circuit that includes a plurality of sense amplifier-data latch units each including a plurality of sense amplifiers that detect and amplify data of the memory cells and a plurality of data latches. One of the plurality of sense amplifier-data latch units is a first sense amplifier-data latch unit and another of the plurality of sense amplifier-data latch units is a second sense amplifier-data latch unit, the first sense amplifier-data latch unit and the second sense amplifier-data latch unit having different numbers of the cell columns capable of being handled. 1. A semiconductor memory device comprising:a memory cell array that includes a plurality of cell columns each configured by a plurality of memory cells; anda column control circuit that includes a plurality of sense amplifier-data latch units each including a plurality of sense amplifiers that detect and amplify data of the memory cells and a plurality of data latches,one of the plurality of sense amplifier-data latch units is a first sense amplifier-data latch unit and another of the plurality of sense amplifier-data latch units is a second sense amplifier-data latch unit, the first sense amplifier-data latch unit and the second sense amplifier-data latch unit having different numbers of the cell columns capable of being handled.2. The semiconductor memory device according to claim 1 ,wherein, when a set of the sense amplifiers capable of handling one of the cell columns is set as a sense amplifier set, a set of the data latches capable of handling one of the cell columns is set as a data latch set, and a set of the one of the sense amplifier sets and the one of the data latch sets is set as a column set,the sense amplifier-data latch unit includes a common control circuit that is used in common for controlling a ...

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12-09-2013 дата публикации

Bipolar primary sense amplifier

Номер: US20130235686A1
Автор: Perry H. Pelley
Принадлежит: Individual

A sense amplifier for a memory includes two bipolar transistors and isolation switches for selectively coupling and decoupling the base of the bipolar transistors to bit lines during portions of a read cycle. The sense amplifier has a feedback circuit that couples the collector of one of the bi polar transistors to the base of the other bipolar transistor and vice versa.

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12-09-2013 дата публикации

Asymmetric Sense Amplifier Design

Номер: US20130235687A1

A circuit includes a first inverter including a first PMOS transistor and a first NMOS transistor, and a second inverter including a second PMOS transistor and a second NMOS transistor. A first node is connected to gates of the first PMOS transistor and the first NMOS transistor and drains of the second PMOS transistor and the second NMOS transistor. A second node is connected to gates of the second PMOS transistor and the second NMOS transistor and drains of the first PMOS transistor and the first NMOS transistor. The circuit further includes a first capacitor having a first capacitance connected to the first node; and a second capacitor having a second capacitance connected to the second node. The second capacitance is greater than the first capacitance. 1. A method for reading from a memory , the method comprising:pre-charging a first node and a second node of a sense amplifier to a same voltage, wherein the first node is coupled to a power supply node through a first capacitor, and the second node is coupled to the power supply node through a second capacitor, and wherein the first capacitor has a first capacitance smaller than a second capacitance of the second capacitor;receiving a data voltage from a bit line of the memory into a data line;after the step of receiving the data voltage, receiving a fixed voltage into the sense amplifier, wherein the fixed voltage is connected to the first node in the sense amplifier; andat a time the fixed voltage is received, simultaneously receiving the data voltage on the data line into the sense amplifier, wherein the voltage is received to the second node.2. The method of claim 1 , wherein the fixed voltage is a logic high voltage substantially equal to the same voltage claim 1 , and wherein the method further comprises claim 1 , after the fixed voltage and the data voltage are received claim 1 , discharging the first and the second nodes until the sense amplifier enters into a stable state.3. The method of further ...

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19-09-2013 дата публикации

SEMICONDUCTOR DEVICE, METHOD FOR CONTROLLING THE SAME, AND SEMICONDUCTOR SYSTEM

Номер: US20130242674A1
Принадлежит: ELPIDA MEMORY, INC.

The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits holding the results of temperature measurement. A refresh period is set from outputs of the latch circuits inclusive of the result of temperature measurement carried out last time for each of a plurality of different reference temperatures. After start of measurement, temperature measurements are repeated every wait time corresponding to circulation of the refresh operations. The refresh period is set such that the high-temperature side results of temperature measurement are prioritized. 2. The system as claimed in claim 1 , wherein the first semiconductor device further comprises:a comparator configured to compare a plurality of reference voltages with an output of the temperature sensor;a plurality of latch circuits;a control circuit configured to render the comparator to output a plurality of comparison results by comparing each of the plurality of reference voltages with the output of the temperature sensor, render each of the plurality of latch circuits to latch a corresponding one of the plurality of comparison results, and render the encoder to produce the code including the bits with the priority by encoding outputs of the plurality of latch circuits.3. The system as claimed in claim 2 , the code is set to a first predetermined value when a first one of the outputs of the latch circuits has a first level, regardless of levels of the remaining of the outputs of the latch circuits; and', 'the code is set to a second predetermined value when the first one of the outputs of the latch circuits has a second level different from the first level and a second one of the outputs of the latch circuit has a third level, regardless of levels of the remaining of the outputs of the latch circuits., 'wherein ...

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26-09-2013 дата публикации

Redundant memory array for replacing memory sections of main memory

Номер: US20130254513A1
Автор: Yoshinori Fujiwara
Принадлежит: Micron Technology Inc

Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory section of a redundant memory array. One such memory includes a fuse block having programmable elements configured to be programmed to identify main memory sections to be mapped to redundant memory sections of the redundant memory array. The memory further includes a redundant memory logic circuit coupled to the redundant memory array and the fuse block. The redundant memory logic is configured to map the memory for a main memory section identified in the fuse block to at least one of the redundant memory sections of the redundant memory array.

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03-10-2013 дата публикации

Semiconductor device

Номер: US20130258793A1
Принадлежит: Elpida Memory Inc

A semiconductor device includes a sense amplifier circuit. The sense amplifier circuit includes a cross-coupled first transistor and second transistor that perform amplification. The sources of the cross-coupled transistors are respectively connected in series with a third transistor and a fourth transistor, and electrical current supply capability of the third and fourth transistors is controlled by a control voltage given to control electrodes of the third and fourth transistors. In a data retaining period, a minimum sub-threshold current necessary for retaining the data is flowed to the third and fourth transistors according to the control voltage, and bit line potential is maintained.

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03-10-2013 дата публикации

SINGLE-ENDED READ RANDOM ACCESS MEMORY

Номер: US20130258795A1
Принадлежит: NATIONAL CHUNG CHENG UNIVERSITY

A single-ended read random access memory including a plurality of memory units, a clock generator, a bit line load circuit, a control processing unit, and a sensing unit is revealed. The memory units are coupled to a bit line and the clock generator is for generating a clock signal. The bit line load circuit charges the memory units to an operating voltage according to the clock signal. The control processing unit controls at least one of the memory units according to the clock signal to make the memory unit store a stored voltage according to the operating voltage. The sensing unit generates a sensing threshold according to the clock signal and a data dependency, and outputs a data signal according to the sensing threshold and the stored voltage. The operating voltage includes a noise whose ratio to the operating voltage is inversely proportional to the operating voltage. 1. A single-ended read random access memory comprising:a plurality of memory units coupled to a bit line;a clock generator that generates a clock signal;a bit line load circuit that charges the memory units to an operating voltage according to the clock signal;a control processing unit that controls at least one of the memory units according to the clock signal so as to make the memory unit stores a stored voltage in accordance with the operating voltage; anda sensing unit that generates a sensing threshold according to the clock signal and the stored voltage, and outputs a data signal according to the sensing threshold and the stored voltage;wherein the operating voltage includes a noise and a ratio of the noise to the operating voltage is inversely proportional to the operating voltage.2. The device as claimed in claim 1 , wherein the sensing unit outputs an amplified voltage according to the stored voltage.3. The device as claimed in claim 2 , wherein the sensing unit outputs the amplified voltage according to the noise so as to output the data signal.4. The device as claimed in claim 1 , ...

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10-10-2013 дата публикации

Semiconductor device and method of operating the same

Номер: US20130265833A1
Автор: Hyun Taek Jung, Mark Pyo
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device and a method of operating the same, the semiconductor device including a sense amplifier connected between a bit line and a complementary bit line; a first power supply circuit configured to select between supplying a power supply voltage to the first node and blocking the power supply voltage from the first node in response to a first control signal; a second power supply circuit configured to select between supplying a ground voltage to the second node and blocking the ground voltage from the second node in response to a second control signal; and a first boosting circuit configured to boost a voltage at the first node in response to a third control signal.

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31-10-2013 дата публикации

SEMICONDUCTOR MEMORY WITH SENSE AMPLIFIER

Номер: US20130286760A1
Автор: Takahashi Hiroyuki
Принадлежит:

In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier row in which transistors of a first conductive type are arranged and a second sense-amplifier row in which transistors of a second conductive type are arranged, and the driver transistors constitutes at least one transistor row including a first driver transistor of the first conductive type corresponding to the first sense-amplifier row and a second driver transistor of the second conductive type corresponding to the second sense-amplifier row between the first sense-amplifier row and the second sense-amplifier row. 1. A semiconductor memory device , comprising:a plurality of sense amplifiers driving bit lines to which memory cells are connected;a plurality of sense amplifier drivers supplying a power supply to the sense amplifiers, each of sense amplifier drivers having first and second driver transistors, and the first driver transistor having a first diffusion regions in a first well region and the second driver transistor having a second diffusion region in a second well region which is different conductivity type from the first well region, andan element separation region formed between the first and second well region,wherein the first and second driver transistors are arranged in parallel with a first direction so as to be arranged one of second driver transistors between two of the first driver transistors,wherein the first diffusion region comprises first and second sides, the first side is parallel to the first direction and the second side is perpendicular to the first direction,wherein the second diffusion region comprises third and fourth sides, the third side is parallel to the first direction and the fourth side is ...

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07-11-2013 дата публикации

CIRCUITS AND METHODS FOR CALIBRATING OFFSET IN AN AMPLIFIER

Номер: US20130294179A1
Автор: LEE Peter, Lee Winston
Принадлежит: MARVELL WORLD TRADE LTD.

In one embodiment, the present disclosure includes a circuit comprising an amplifier having an input and an output, an offset detection circuit to detect an offset of the amplifier at the output of the amplifier, and an offset generation circuit having an input coupled to the offset detection circuit and an output coupled to the input of the amplifier to generate an offset at the input of the amplifier during an operational phase of the amplifier based on the detected offset. The generated offset cancels a least a portion of the offset of the amplifier. In one implementation, the amplifier is a sense amplifier in a memory. 120-. (canceled)21. A method for determining offset in an amplifier , the method comprising:generating, using offset generation circuitry, an offset value at an input of an amplifier;determining, using offset detection circuitry, whether an output of the amplifier is greater than an output threshold; andsetting, using control circuitry, an offset inject value which indicates that an offset should be generated at the input of the amplifier if the output is determined to be greater than the output threshold.22. The method of claim 21 , further comprising:generating an incremented offset value by incrementing the offset by an offset increment value if the output is determined to be greater than the output threshold;determining, using offset detection circuitry, whether the output of the amplifier is greater than a output threshold; andstoring, using offset value storage circuitry, the incremented offset value if the output is less than or equal to the output threshold.23. The method of claim 22 , wherein the offset value and incremented offset value is determined by successive approximation.24. The method of claim 21 , wherein the input of the amplifier is a first polarity input of the amplifier and the output of the amplifier is associated with the first polarity of the input.25. The method of claim 21 , further comprising storing the generated ...

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07-11-2013 дата публикации

SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR DEVICE USING THE SAME

Номер: US20130294185A1
Автор: KIM Hyung Soo
Принадлежит: SK HYNIX INC.

A sense amplifier circuit includes an enable signal generation unit configured to generate an enable signal when a change in a voltage level of input signals is sensed; a sink unit configured to provide a sense voltage in response to the enable signal; and a sense unit configured to generate an output signal in response to the sense voltage and the input signals. 1. A sense amplifier circuit , comprising:an enable signal generation unit configured to generate an enable signal when a change in a voltage level of input signals is sensed;a sink unit configured to provide a sense voltage in response to the enable signal; anda sense unit configured to generate an output signal in response to the sense voltage and the input signals.2. The sense amplifier circuit according to claim 1 , wherein the enable signal generation unit receives a sense control signal and supplies the sense control signal as the enable signal when the change in the voltage level of the input signals is sensed.3. The sense amplifier circuit according to claim 2 , further comprising a cut-off unit configured to prevent the sense voltage from being supplied to the sense unit when the sense control signal is disabled.4. The sense amplifier circuit according to claim 2 , wherein:the input signals are a pair of input signals, andthe enable signal generation unit provides the sense control signal as the enable signal when a voltage level of one of the pair of input signals shifts to a specific voltage level.5. The sense amplifier circuit according to claim 1 , wherein the enable signal generation unit further comprises a first PMOS transistor operably coupled in parallel with a second PMOS transistor.6. The sense amplifier circuit according to claim 5 , wherein the enable signal generation unit receives input signals through a gate of the first PMOS transistor and a gate of the second PMOS transistor.7. A sense amplifier circuit claim 5 , comprising:an enable signal generation unit configured to generate ...

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21-11-2013 дата публикации

Apparatuses and methods for coupling load current to a common source

Номер: US20130308385A1
Автор: Toru Tanzawa
Принадлежит: Individual

Apparatuses and methods are disclosed, including an apparatus with a string of charge storage devices coupled to a common source, a first switch coupled between the string of charge storage devices and a load current source, and a second switch coupled between the load current source and the common source. Additional apparatuses and methods are described.

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21-11-2013 дата публикации

SEMICONDUCTOR DEVICE HAVING SENSE AMPLIFIER CIRCUIT

Номер: US20130308403A1
Принадлежит: ELPIDA MEMORY, INC.

Disclosed herein is a device that includes: a first control element that controls an amount of current flowing between a second line and a first node according to a potential of a first line; a second control element that controls an amount of current flowing between the first line and the first node according to a potential of the second line; a first control circuit that performs a first operation to fix potentials of the first and second lines at a first potential; a second control circuit that performs a second operation to connect the first node to the second node; and a third control circuit that fixes a potential of the first node at a second potential after the first control circuit stops the first operation until the second control circuit starts the second operation. 1. A semiconductor device comprising:a first line;a second line;a first node;a second node supplied with a first power supply potential;a first control element that controls an amount of current flowing between the second line and the first node according to a potential of the first line;a second control element that controls an amount of current flowing between the first line and the first node according to a potential of the second line;a first control circuit that performs a first operation to fix potentials of the first and second lines at a first potential;a second control circuit that performs a second operation to connect the first node to the second node; anda third control circuit that fixes a potential of the first node at a second potential after the first control circuit stops the first operation until the second control circuit starts the second operation.2. The semiconductor device as claimed in claim 1 , wherein the first potential and the second potential are substantially the same potential.3. The semiconductor device as claimed in claim 1 , further comprising first and second memory cells claim 1 ,wherein the first line receives data read from the first memory cell, and the ...

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28-11-2013 дата публикации

SENSE AMPLIFIER CIRUIT AND SEMICONDUCTOR DEVICE

Номер: US20130315018A1
Принадлежит: ELPIDA MEMORY, INC.

A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes. 1. A semiconductor device comprising:a first conductive line;a second conductive line;a first transistor coupled between the first conductive line and a first power supply line, the first transistor including a control terminal coupled to a first control line;a second transistor coupled between a second power supply line and a first node, the second transistor including a control terminal coupled to a second control line different from the first control line;a third transistor coupled between the first conductive line and the first node, the first transistor including a control terminal coupled to a third control line; anda fourth transistor coupled between the second conductive line and a third power supply line, the fourth transistor including a control terminal connected to the first node;wherein the first power supply line is able to be supplied an intermediate voltage which is intermediate between a voltage of the second power supply line and a voltage of the second power supply line.2. The semiconductor device according to claim 1 , further comprising a memory cell coupled ...

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19-12-2013 дата публикации

SEMICONDUCTOR DEVICE, METHOD OF RETRIEVING DATA, AND MICROCOMPUTER

Номер: US20130336078A1
Автор: YAMAMOTO Shohei
Принадлежит:

A semiconductor device includes a data memory cell for storing data; a reference data memory cell for storing reference data to be compared with the data; an inverted data memory cell for storing inverted data of the reference data; a sense amplifier unit; and a data output unit. In a first retrieving process, the sense amplifier unit differentially amplifies the data and the reference data, and adjusts an output thereof when a voltage difference between the data and the reference data becomes a predetermined retrievable voltage difference. In a second retrieving process, the sense amplifier unit differentially amplifies the data and the inverted data, and adjusts an output thereof when a voltage difference between the data and the inverted data becomes the predetermined retrievable voltage difference. The data output unit determines and outputs the data according to a result of the first retrieving process and the second retrieving process. 1. A semiconductor device comprising:a data memory cell for storing data;a reference data memory cell for storing reference data to be compared with the data;an inverted data memory cell for storing inverted data of the reference data;a sense amplifier unit; anda data output unit,wherein said sense amplifier unit is configured to perform a first retrieving process, in which the sense amplifier unit differentially amplifies the data stored in the data memory cell and the reference data stored in the reference data memory cell, and adjusts an output thereof when a voltage difference between the data and the reference data becomes a predetermined retrievable voltage difference,said sense amplifier unit is configured to perform a second retrieving process, in which the sense amplifier unit differentially amplifies the data stored in the data memory cell and the inverted data stored in the inverted data memory cell, and adjusts an output thereof when a voltage difference between the data and the inverted data becomes the ...

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26-12-2013 дата публикации

Bitline for Memory

Номер: US20130343140A1
Автор: Raed Sabbah
Принадлежит: Micron Technology Inc

Subject matter disclosed herein relates to accessing memory, and more particularly to operation of a partitioned bitline.

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02-01-2014 дата публикации

SEMICONDUCTOR DEVICE HAVING OPEN BITLINE STRUCTURE

Номер: US20140003113A1
Принадлежит:

Disclosed herein is a semiconductor device that includes: a plurality of memory arrays disposed in a first direction and a second direction that crosses the first direction; a plurality of row decoders disposed along a first side of the memory arrays; a plurality of first column decoders each disposed along a second side that does not face the first side of an associated one of the memory arrays; and a plurality of second column decoders each disposed along a third side that faces the second side of an associated one of the memory arrays. Each of the memory arrays is sandwiched between a corresponding one of the first column decoders and a corresponding one of the second column decoders. 1. A semiconductor device comprising:a plurality of memory mats arranged in a first direction and selected based on a mat address, the plurality of memory mats including a first memory mat disposed in one end portion of the first direction, a second memory mat disposed in the other end portion of the first direction, and a third memory mat positioned between the first and second memory mats; anda plurality of sense amplifier areas each arranged between two of the memory mats that are adjacent to each other in the first direction, each of the sense amplifier areas including a plurality of sense amplifiers, whereineach of the memory mats includes a plurality of bit lines extending in the first direction, a plurality of word lines extending in a second direction that crosses the first direction, and a plurality of memory cells disposed at intersections of the bit lines and word lines,each of the sense amplifiers is connected to an associated one of the bit lines included in an adjacent one of the memory mats on one side of the first direction, and to an associated one of the bit lines included in an adjacent one of the memory mats on the other side of the first direction,the first and third memory mats are selected when the mat address indicates a first value, andthe second and third ...

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02-01-2014 дата публикации

Semiconductor memory apparatus and method of operating using the same

Номер: US20140003129A1
Автор: Kwang Myoung Rho
Принадлежит: SK hynix Inc

A semiconductor memory apparatus includes a resistive memory cell coupled between a bit line and a bit line bar; a control unit configured to couple the bit line to a first node and apply a reference voltage to a second node in response to a first sense amplifier enable signal and a second sense amplifier enable signal; a data output sense amplifier configured to sense and amplify a voltage of the first node and a voltage of the second node; a data transfer unit configured to couple the first and second nodes to a data line and a data line bar in response to a column select signal; and a data input unit configured to drive the bit line and the bit line bar according to voltage levels of the first and second nodes in response to a write enable signal.

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02-01-2014 дата публикации

SEMICONDUCTOR STORAGE DEVICE

Номер: US20140003149A1
Автор: MAEJIMA Hiroshi
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to one embodiment, a semiconductor storage device of an embodiment of the present disclosure is provided with peripheral circuits, a memory cell array, upper bit lines, and first and second connecting parts. The memory cell array is disposed above the peripheral circuit, and includes at least first and second regions. The upper bit lines extend in a first direction and are above the memory cell array. The first and second connecting parts are respectively provided with contact plugs, and one of these connecting parts is formed between first and second regions. The upper bit lines includes a first group of upper bit lines which are connected to the peripheral circuits via the first connecting part, and a second group of upper bit lines which are connected to the peripheral circuits via the second connecting part. 1. A semiconductor storage device , comprising:a plurality of peripheral circuits on a semiconductor substrate;a memory cell array having a plurality of semiconductor layers above the peripheral circuits, the memory cell array including two or more regions;a plurality of upper bit lines disposed in one or more layers above the memory cell array and extending in a first direction, each of the upper bit lines electrically connected to at least one of the peripheral circuits;a plurality of lower bit lines disposed in one or more layers below the memory cell array and extending in the first direction, each of the lower bit lines corresponding to a respective upper bit line; anda plurality of connection parts including contact plugs connecting upper bit lines to corresponding lower bit lines,wherein a first group of the upper bit lines are connected to the peripheral circuits via a first connecting part and respective lower bit lines, the first connecting part disposed between two regions of the memory cell array, and a second group of the upper bit lines are connected to the peripheral circuits via a second connecting part and respective lower bit ...

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02-01-2014 дата публикации

SEMICONDUCTOR APPARATUS AND TEST CIRCUIT THEREOF

Номер: US20140003161A1
Автор: Kim Yong Ju, SON Jong Ho
Принадлежит: SK HYNIX INC.

A test circuit of a semiconductor apparatus includes a test temperature information generation section, an erroneous operation prevention unit, and a refresh cycle adjustment unit. The test temperature information generation section outputs test temperature information having a plurality of bits in a test operation mode, and irregularly changes logic values of the plurality of bits and transition time points of the logic values. The erroneous operation prevention unit generates a temperature compensation signal in response to the test temperature information. The refresh cycle adjustment unit changes a cycle of a reference refresh signal in response to the temperature compensation signal, and generates a refresh signal. 1. A test circuit of a semiconductor apparatus comprising:a test temperature information generation section configured to output test temperature information having a plurality of bits in a test operation mode, and to irregularly change logic values of the plurality of bits and transition time points of the logic values;an erroneous operation prevention unit configured to generate a temperature compensation signal in response to the test temperature information; anda refresh cycle adjustment unit configured to change a cycle of a reference refresh signal in response to the temperature compensation signal, and to generate a refresh signal.2. The test circuit of the semiconductor apparatus according to claim 1 , wherein the test temperature information generation section is configured to generate the test temperature information in response to an oscillation signal.3. The test circuit of the semiconductor apparatus according to claim 1 , further comprising:a cycle monitoring unit configured to compare a test refresh signal, which has a cycle corresponding to the test temperature information, with the refresh signal, and to output a test result.4. The test circuit of the semiconductor apparatus according to claim 1 , further comprising:a selection ...

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02-01-2014 дата публикации

Memory array with on and off-state wordline voltages having different temperature coefficients

Номер: US20140003164A1
Принадлежит: International Business Machines Corp

Disclosed is a memory array structure, where a wordline driver selectively applies a high on-state voltage (VWLH) or a low off-state voltage (VWLL) to a wordline. VWLH has a slightly negative temperature coefficient so that it is regulated as high as the gate dielectric reliability limits allow, whereas VWLL has a substantially neutral temperature coefficient. To accomplish this, the wordline driver is coupled to one or more voltage regulation circuits. In one embodiment, the wordline driver is coupled to a single voltage regulation circuit, which incorporates a single voltage reference circuit having a single output stage that outputs multiple reference voltages. Also disclosed is a voltage reference circuit, which can be incorporated into the voltage regulation circuit of a memory array structure, as described, or, alternatively, into any other integrated circuit structure requiring voltages with different temperature coefficients. Also disclosed is a method of operating a memory array structure.

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02-01-2014 дата публикации

SEMICONDUCTOR MEMORY APPARATUS

Номер: US20140003165A1
Принадлежит: SK HYNIX INC.

A semiconductor memory apparatus includes a sense amplifier driving control unit configured to be applied with first and second driving voltages, and generate first to third sense amplifier driving signals in response to a mat enable signal, a sense amplifier enable signal and a power-up signal; a sense amplifier driving unit configured to, in response to the first to third sense amplifier driving signals, connect first and second sense amplifier driving nodes to cause the first and second sense amplifier driving nodes to have substantially the same voltage level, or disconnect the first and second sense amplifier driving nodes to apply first and second sense amplifier driving voltages to the first and second sense amplifier driving nodes; and a sense amplifier configured to be applied with the first and second sense amplifier driving voltages, and sense and amplify a voltage difference of a bit line and a bit line bar. 1. A semiconductor memory apparatus comprising:a sense amplifier driving control unit configured to be applied with a first driving voltage and a second driving voltage which have different voltage levels, and generate a first sense amplifier driving signal, a second sense amplifier driving signal and a third sense amplifier driving signal in response to a mat enable signal, a sense amplifier enable signal and a power-up signal;a sense amplifier driving unit configured to, in response to the first to third sense amplifier driving signals, connect a first sense amplifier driving node and a second sense amplifier driving node to cause the first and second sense amplifier driving nodes to have substantially the same voltage level, or disconnect the first sense amplifier driving node and the second sense amplifier driving node to apply a first sense amplifier driving voltage to the first sense amplifier driving node and apply a second sense amplifier driving voltage to the second sense amplifier driving node; anda sense amplifier configured to be applied ...

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02-01-2014 дата публикации

SEMICONDUCTOR MEMORY APPARATUS

Номер: US20140003171A1
Автор: KO Jae Bum
Принадлежит: SK HYNIX INC.

A semiconductor memory apparatus includes a first chip including a refresh signal generation unit which is configured to receive an external command and generate a refresh signal; and a second chip including a first delay unit which is configured to receive the refresh signal through a first through-silicon via and delay the received refresh signal, a first selection unit which is configured to output an output signal of the first delay unit to the first chip through a second through-silicon via in response to a first select signal, and a first core region which is configured to receive the output signal of the first delay unit and perform a refresh operation. 1. A semiconductor memory apparatus comprising:a first chip; anda second chip electrically coupled to the first chip by a first through silicon via and a second through silicon via;wherein the first chip comprises:a refresh signal generation unit configured to receive an external command and generate a refresh signal; and wherein the second chip comprises:a first delay unit configured to receive the refresh signal through the first through-silicon via and to delay the received refresh signal,a first selection unit configured to output an output signal of the is first delay unit to the first chip through the second through-silicon via in response to a first select signal, anda first core region configured to receive the output signal of the first delay unit and to perform a refresh operation.2. The semiconductor memory apparatus according to claim 1 , wherein the second chip is stacked on the first chip.3. The semiconductor memory apparatus according to claim 1 , wherein the first selection unit is configured to output the output signal of the first delay unit to the second through-silicon via when the first select signal is enabled claim 1 , and to prevent the output signal of the first delay unit from being outputted to the second through-silicon via when the first select signal is disabled.4. The ...

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02-01-2014 дата публикации

Memory Device, System Having the Same, and Method for Manufacturing the Same

Номер: US20140003177A1
Автор: In Chul JEONG
Принадлежит:

A memory device includes a memory cell array including normal memory cells arranged in a form of matrix, and a sense amplifier array including sense amplifiers each amplifying a signal output from each of the normal memory cells. Some of the sense amplifiers have different sizes so that they may have different sense capabilities depending on a layout location. The size is determined according to at least one of a channel length and a channel width of a MOS transistor included in each of the some sense amplifiers. 1. A memory device , comprising:a memory cell array including memory cells arranged in a matrix; anda sense amplifier array including a plurality of sense amplifiers, each sense amplifier configured to amplify a signal output from each cell of a set of memory cells;wherein each sense amplifier of the sense amplifier array is formed of a plurality of transistors, andwherein an average size among the plurality of transistors that form a first sense amplifier of the sense amplifier array is larger than an average size among the plurality of transistors that form a second sense amplifier of the sense amplifier array.2. The memory device of claim 1 , wherein the first sense amplifier is an edge sense amplifier claim 1 , and the second sense amplifier is an inner sense amplifier.3. The memory device of claim 1 , wherein an average channel length among the plurality of transistors that form the first sense amplifier of the sense amplifier array is larger than an average channel length among the plurality of transistors that form the second sense amplifier of the sense amplifier array.4. The memory device of claim 1 , wherein an average channel width among the plurality of transistors that form the first sense amplifier of the sense amplifier array is larger than an average channel width among the plurality of transistors that form the second sense amplifier of the sense amplifier array.5. (canceled)6. (canceled)7. The memory device of claim 1 , wherein an average ...

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09-01-2014 дата публикации

MEMORY WITH REDUNDANT SENSE AMPLIFIER

Номер: US20140010030A1
Принадлежит: Apple Inc.

Embodiments of a memory are disclosed that may reduce the likelihood of a miss-read while reading a weak data storage cell. The memory may include a number of data storage cells, a column multiplexer, a first sense amplifier and a second sense amplifier, and an output circuit. The gain level of the first sense amplifier may be higher than the gain level of the second sense amplifier. The output circuit may include a multiplexer and the multiplexer may be operable to controllably select one of the outputs of the first and second sense amplifiers and pass the value of the selected sense amplifier. The output circuit may include a node that couples the outputs of the first and second sense amplifiers and the outputs of the first and second sense amplifiers may be able to be set to a high impedance state. 1. An apparatus , comprising:a plurality of data storage cells;a decoder circuit configured to select a data storage cell from the plurality of data storage cells;a control circuit configured to store test data in the selected data storage cell;a first sense amplifier configured to amplify the stored test data in the selected data storage cell using a first gain level;wherein the control circuit is further configured to compare test data to the stored data amplified using the first gain level; anda second sense amplifier configured to amplify the stored test data in the selected data storage cell using a second gain level responsive to a determination that the stored test data amplified using the first gain level does not match the test data, wherein the second gain level is greater than the first gain level; and compare the test data to the stored test data amplified using the second gain level; and', 'store information indicative of the strength of the selected data storage cell dependent upon the comparison of the test data to the stored data amplified using the second gain level., 'wherein the control circuit is further configured to2. The apparatus of claim 1 , ...

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09-01-2014 дата публикации

Dynamic memory performance throttling

Номер: US20140013070A1
Принадлежит: Intel Corp

Dynamic memory performance throttling. An embodiment of a memory device includes a memory stack including coupled memory elements; the memory elements including multiple ranks, the plurality of ranks including a first rank and a second rank, and a logic device including a memory controller. The memory controller is to determine an amount of misalignment between data signals relating to a read request for the first rank and a read request for the second rank, and, upon determining that misaligment between the first rank and the second rank is greater than a threshold, the memory controller is to insert a time shift between a data signal for the first rank and a data signal for the second rank.

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16-01-2014 дата публикации

MEMORY WITH TERMINATION CIRCUIT

Номер: US20140016401A1
Принадлежит: RENESAS ELECTRONICS CORPORATION

Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data. 1. A semiconductor device on a chip and for use with a memory device , the semiconductor device comprising:an external data terminal configured to be coupled to the memory device via a signal line and configured to receive a first set of burst data from the memory device and to receive a second set of burst data from the memory device after an interval;a termination circuit coupled to the external data terminal;a buffer circuit having an input coupled to the external data terminal; and the control circuit configured to provide the control signal having the first level to the termination circuit so that the termination circuit is activated from a start of receiving the first set of burst data until an end of receiving the second set of burst data if the interval is determined to be less than or equal to a threshold, and', 'the control circuit configured to provide the control signal having the second level to the termination circuit so that the termination circuit is deactivated from an end ...

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16-01-2014 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20140016418A1
Принадлежит: SK HYNIX INC.

A semiconductor memory device includes a first core region and a second core region disposed along a first reference line parallel to a major axis, the first reference line connecting an input pad and an output pad; first and second cell blocks disposed in the first core region along the first reference line; third and fourth cell blocks disposed in the second core region along the first reference line; and a repeater positioned between the third and fourth cell blocks, and configured to receive data outputted from the first cell block or the second cell block, amplify the received data and transfer the amplified data to a second global input/output line. Reducing the number of needed global input/output lines leads to layout area reduction. Moreover, since repeaters are driven in read operations for a limited number of cell blocks, signal gain may be reduced, thus reducing overall power consumption. 1. A semiconductor memory device comprising:a first core region and a second core region disposed along a first reference line substantially parallel to a major axis, the first reference line connecting an input pad and an output pad;first and second cell blocks disposed in the first core region along the first reference line;third and fourth cell blocks disposed in the second core region along the first reference line; anda repeater positioned between the third and fourth cell blocks, and configured to receive data outputted from the first cell block or the second cell block, through a first global input/output line in a read operation for the first cell block or the second cell block, amplify the received data and transfer the amplified data to a second global input/output line.2. The semiconductor memory device according to claim 1 , further comprising:a data output unit configured to receive the data amplified by the repeater, through the second global input/output line, and output the received data to a third global input/output line.3. The semiconductor memory ...

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16-01-2014 дата публикации

MEMORY DEVICE AND A METHOD OF OPERATING SUCH A MEMORY DEVICE IN A SPECULATIVE READ MODE

Номер: US20140016419A1
Автор: Hold Betina
Принадлежит: ARM LIMITED

A memory includes an array of memory cells with each memory cell coupled to an associated pair of bit lines. Read control circuitry is configured to activate a number of addressed memory cells in order to couple each addressed memory cell to its associated pair of bit lines. Sense amplifier circuitry is then coupled to the bit lines to determine the data value stored in each addressed memory. In a speculative read mode of operation, the sense amplifier circuitry evaluates the differential signals. Error detection circuitry is then used to capture the differential signals on the associated pair of bit lines for each addressed memory cell, and to apply an error detection operation to determine if the differential signals as evaluated by the sense amplifier circuitry had not developed to the necessary degree and, in that event, an error signal is asserted. 119-. (canceled)20. A memory device comprising:an array of memory cells, each memory cell being coupled to an associated pair of bit lines;read control circuitry configured during a read operation to activate a number of addressed memory cells in order to couple each addressed memory cell to its associated pair of bit lines;sense amplifier circuitry coupled to the bit lines and configured during the read operation to determine the data value stored in each addressed memory cell by evaluation of a pair of signals that develop on the associated pair of bit lines during the read operation in dependence on the data value stored in that addressed memory cell;the sense amplifier circuitry being configured in a speculative read mode of operation to evaluate the pair of signals on the associated pair of bit lines for each addressed memory cell after a speculative read time period that is not guaranteed to be sufficient for the pair of signals to have developed to a degree necessary for the sense amplifier circuitry to correctly determine the data value stored in each addressed memory cell; anderror detection circuitry ...

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16-01-2014 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20140016420A1
Автор: JEONG In-Chul
Принадлежит:

A semiconductor memory device includes a sense amplifier circuit region including first wells disposed in a first direction, a driving circuit region including second wells disposed in a second direction, and a conjunction region disposed at an intersection region of the sense amplifier circuit region and the driving circuit region, a part of each of the first wells extending from the sense amplifier circuit region into the conjunction region, and the second wells being outside of the conjunction region. 1. A semiconductor memory device , comprising:a sense amplifier circuit region including first wells disposed in a first direction;a driving circuit region including second wells disposed in a second direction; anda conjunction region disposed at an intersection region of the sense amplifier circuit region and the driving circuit region, a part of each of the first wells extending from the sense amplifier circuit region into the conjunction region, and the second wells being outside of the conjunction region.2. The semiconductor memory device as claimed in claim 1 , wherein the part of each of the first wells in the conjunction region includes first and second partial wells extending from the sense amplifier circuit region at both sides of the conjunction region into the conjunction region claim 1 , the first and second partial wells being spaced apart from each other.3. The semiconductor memory device as claimed in claim 2 , wherein a length of the first partial well or the second partial well in the first direction is greater than about 5% of a width of the conjunction region in the first direction.4. The semiconductor memory device as claimed in claim 2 , wherein lengths of the first partial well and the second partial well in the first direction are substantially identical to each other.5. The semiconductor memory device as claimed in claim 2 , further comprising a third well in the conjunction region claim 2 , the third well connecting the first partial well ...

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23-01-2014 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20140022857A1
Автор: MIYATAKE Shinichi
Принадлежит: ELPIDA MEMORY, INC.

A semiconductor device including a sense amplifier that includes a first transistor and a second transistor. The first transistor includes a first gate electrode formed over a first channel region and connected to a first bit line, a first diffusion region connected to a second bit line with a first side edge defining the first channel region, and a second diffusion region connected to a power line and includes a second side edge defining the first channel region. The second transistor includes a second gate electrode formed over a second channel region and connected to the second bit line, a third diffusion region connected to the first bit line and includes a third side edge defining the second channel region, and a fourth diffusion region connected to the power line with a fourth side edge defining the second channel region. Directions of the bit lines and diffusion side edges are prescribed. 1. A semiconductor device , comprising:a first memory cell;a second memory cell;a first bit line extending in a first direction and being connected to the first memory cell;a second bit line extending in the first direction and being connected to the second memory cell;a first power line; anda sense amplifier circuit comprising a first transistor and a second transistor, the first transistor including a first gate electrode that is formed over a first channel region and connected to the first bit line, a first diffusion region that is connected to the second bit line and includes a first side edge defining the first channel region and a second diffusion region that is connected to the first power line and includes a second side edge defining the first channel region, and the second transistor including a second gate electrode that is formed over a second channel region and connected to the second bit line, a third diffusion region that is connected to the first bit line and includes a third side edge defining the second channel region and a fourth diffusion region that is ...

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30-01-2014 дата публикации

SENSE AMPLIFIER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME

Номер: US20140029359A1
Автор: Kim Hyung-Soo
Принадлежит: SK HYNIX INC.

A sense amplifier circuit includes a first pull-up transistor configured to pull-up drive a data bar line in response to a voltage of a data line, a first pull-down transistor configured to pull-down drive the data bar line in response to the voltage of the data line, and to receive the voltage of the data line through a back gate of the first pull-down transistor, a second pull-up transistor configured to pull-up drive the data line in response to a voltage of the data bar line, and a second pull-down transistor configured to pull-down drive the data line in response to the voltage of the data bar line, and to receive the voltage of the data bar line through a back gate of the second pull-down transistor. 1. A sense amplifier circuit comprising:a first pull-up transistor configured to pull-up drive a data bar line in response to a voltage of a data line;a first pull-down transistor configured to pull-down drive the data bar line in response to the voltage of the data line, and to receive the voltage of the data line through a back gate of the first pull-down transistor;a second pull-up transistor configured to pull-up drive the data line in response to a voltage of the data bar line; anda second pull-down transistor configured to pull-down drive the data line in response to the voltage of the data bar line, and to receive the voltage of the data bar line through a back gate of the second pull-down transistor.2. The sense amplifier circuit of claim 1 , wherein each of the first pull-down transistor and the second pull-down transistor includes a fully depleted silicon on insulator (FDSOI) NMOS transistor.3. The sense amplifier circuit of claim 2 , wherein each of the first pull-up transistor and the second pull-up transistor includes a PMOS transistor.4. A memory device comprising:one or more cell arrays,a bit line and a bit bar line connected to the one or more cell arrays;a first pull-up transistor configured to pull-up drive the bit bar line in response to a ...

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06-02-2014 дата публикации

Temperature based compensation during verify operations for non-volatile storage

Номер: US20140036601A1
Принадлежит: SanDisk Technologies LLC

A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation.

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13-02-2014 дата публикации

Sense Amplifier Circuit for Nonvolatile Memory

Номер: US20140043928A1
Автор: Yong Seop Lee
Принадлежит: Dongbu HitekCo Ltd

A sense amplifier circuit for a nonvolatile memory that includes a first amplifier to perform a switching operation to output a first signal on a sense amplifier based logic (SABL) node depending on the state of a sensing enable signal, a second amplifier to perform a switching operation to output a second signal on the SABL node depending on the state of the sensing enable signal, a current mirror that sinks current on the SABL node depending on the sensing enable signal and a bit line signal, and an inverter arranged to output the signal on the SABL node as a data signal.

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20-02-2014 дата публикации

SEMICONDUCTOR MEMORY DEVICES

Номер: US20140050039A1
Автор: PARK Min Su
Принадлежит: SK HYNIX INC.

A semiconductor memory device includes a memory bank having a first cell block including a plurality of memory cells coupled to a first word line which can be activated in response to a row address signal, a second cell block including a plurality of memory cells coupled to a second word line, and a dummy cell block including a plurality of memory cells coupled to a third word line which can be activated in response to the row address signal. The first and second cell blocks share a first sense amplifier. The second cell block and the dummy cell block share a second sense amplifier. The first cell block is disposed adjacent to a first edge of the memory bank, and the dummy cell block is disposed adjacent to a second edge of the memory bank opposing the first edge. 1. A semiconductor memory device comprising:a first cell block including a first plurality of memory cells coupled to a first word line;a second cell block including a second plurality of memory cells coupled to a second word line; anda dummy cell block including a third plurality of memory cells coupled to a third word line,wherein the first and second cell blocks share a first sense amplifier, the second cell block and the dummy cell block share a second sense amplifier, the first cell block is disposed adjacent to a first edge of the semiconductor memory device where a row address signal is inputted, and the dummy cell block is disposed adjacent to a second edge of the semiconductor memory device opposing the first edge.2. The semiconductor memory device of :wherein when the row address signal indicates the first cell block is being accessed and no failed memory cells exists in the first cell block, the first and third word lines are simultaneously activated; andwherein when the row address signal indicates the first cell block is being accessed and at least one failed memory cell exists in the first cell block, the first and third redundancy word lines are simultaneously activated.3. The semiconductor ...

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20-02-2014 дата публикации

Bit line sense amplifier and layout method therefor

Номер: US20140050040A1
Автор: Hyoun Mi YU
Принадлежит: SK hynix Inc

A bit line sense amplifier and a layout method therefor which can reduce coupling capacitance. The bit line sense amplifier is disposed between a first memory cell block and a second memory cell block adjacent to the first memory cell block and configured to include first and third switching elements substantially symmetrically formed in a first direction so that the drain terminals of the first and third switching elements face each other, second and fourth switching elements substantially symmetrically formed in the first direction so that the drain terminals of the second and fourth switching elements face each other, a first line configured to electrically couple the gate terminal of the first switching element and the drain terminal of the second switching element, and a second line configured to electrically couple the gate terminal of the third switching element and the drain terminal of the fourth switching element.

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27-02-2014 дата публикации

SENSE AMPLIFIERS, MEMORIES, AND APPARATUSES AND METHODS FOR SENSING A DATA STATE OF A MEMORY CELL

Номер: US20140056089A1
Автор: Vimercati Daniele
Принадлежит: MICRON TECHNOLOGY, INC.

Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell are disclosed. An example apparatus includes a differential amplifier configured to amplify a voltage difference between voltages applied to first and second amplifier input nodes to provide an output. The example apparatus further includes first and second capacitances coupled to the first and second amplifier input nodes. A switch block coupled to the first and second capacitances is configured to couple during a first phase a reference input node to the first and second capacitances and to the first amplifier input node. The switch block is further configured to couple during the first phase an output of the amplifier to the second amplifier input node to establish a compensation condition. During a second phase, the switch block couples its input nodes to the first and second capacitances. 1. An apparatus , comprising:a data line and a reference line;a precharge circuit configured to precharge the data line and the reference line during a precharge phase;a switch block having a data line input coupled to the data line, a reference data line input coupled to the reference line, a reference input, and a feedback input, the switch block further including a data line output, a reference data line output, a reference output, and a feedback output, during the precharge phase the switch block configured to couple the reference input to the data line output, the reference data line output, and the reference output, and further couple the feedback input to the feedback output, during an evaluation phase the switch block configured to couple the data line input to the data line output and further couple the reference data line input to the reference data line output;a first capacitance coupled to the data line output;a second capacitance coupled to the reference data line output; anda differential amplifier coupled to the first and second capacitances and configured to ...

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27-02-2014 дата публикации

TECHNIQUES FOR REDUCING DISTURBANCE IN A SEMICONDUCTOR MEMORY DEVICE

Номер: US20140056090A1
Принадлежит: MICRON TECHNOLOGY, INC.

Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment. 1. A semiconductor memory device comprising:a plurality of memory cells; anddata write and sense circuitry coupled to the plurality of memory cells, wherein the data write and sense circuitry is configured to perform a read operation and a writeback operation on a first memory cell of the plurality of memory cells, wherein the data write and sense circuitry is also configured to perform a disturbance recovery operation on a second memory cell of the plurality of memory cells, and wherein the disturbance recovery operation is performed in between the read operation and the writeback operation.2. The semiconductor memory device according to claim 1 , wherein the data write and sense circuitry comprises a plurality of local data sense amplifiers coupled to a plurality of global data sense amplifiers via one or more global bit lines.3. The semiconductor memory device according to claim 2 , wherein the plurality of local data sense amplifiers are arranged in one or more local data sense amplifier subarrays claim 2 , and the plurality of global data sense amplifiers are arranged in one or more global data sense amplifier subarrays.4. The semiconductor memory device according to claim 2 , wherein the plurality of local data sense amplifiers are coupled to a single global data sense amplifier via a single global bit line.5. The semiconductor ...

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06-03-2014 дата публикации

DATA VERIFICATION DEVICE AND A SEMICONDUCTOR DEVICE INCLUDING THE SAME

Номер: US20140063910A1
Автор: YI Jae Ung
Принадлежит: SK HYNIX INC.

A semiconductor device includes a data verification device. The data verification device includes a data storage unit for storing data to be input to a memory region in response to a first or second control signal, an input data verifier for deactivating an output of a sense amplifier in response to the first control signal and transmitting the input data stored in the data storage unit to an external pad, and a sense-amplifier verifier for transmitting the input data stored in the data storage unit to the sense amplifier upon in response to the second control signal. 1. A data verification device comprising:a data storage unit configured to store input data in response to a first or second control signal generated in a test mode;an input data verifier configured to deactivate an output of a sense amplifier in response to the first control signal, and transmit the input data provided by the data storage unit to an external pad; anda sense-amplifier verifier configured to transmit the input data provided by the data storage unit to the sense amplifier in response to the second control signal, wherein the sense amplifier senses the input data transmitted thereto and transmits sensed data to the external pad.2. The data verification device according to claim 1 , wherein the data storage unit includes a latch that stores the input data in response to the first or second control signal.3. The data verification device according to claim 2 , wherein the latch transmits the stored input data to the input data verifier in response to the first control signal.4. The data verification device according to claim 2 , wherein the latch transmits the stored input data to the sense-amplifier verifier in response to the second control signal.5. The data verification device according to claim 1 , wherein the data storage unit is coupled to a data input buffer claim 1 , and receives the input data through the data input buffer and stores the input data.6. The data verification device ...

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06-03-2014 дата публикации

SEMICONDUCTOR APPARATUS

Номер: US20140063926A1
Принадлежит: SK HYNIX INC.

A semiconductor apparatus includes: a sense amplifier unit enabled for a predetermined time during a read operation in response to a first read enable signal, enabled before a write operation in response to a second read enable signal, and disabled when the write operation is started, and a switch unit configured to connect a write driver and a memory unit during the write operation in response to a first select signal, connect the sense amplifier unit and the memory unit for the predetermined time during the read operation in response to a control signal, and disconnect the sense amplifier and the memory unit when the write operation is started. 1. A semiconductor apparatus comprising:a sense amplifier unit enabled for a predetermined time during a read operation in response to a first read enable signal, enabled before a write operation in response to a second read enable signal, and disabled when the write operation is started; anda switch unit configured to connect a write driver and a memory unit during the write operation in response to a first select signal, connect the sense amplifier unit and the memory unit for the predetermined time during the read operation in response to a control signal, and disconnect the sense amplifier and the memory unit when the write operation is started.2. The semiconductor apparatus according to claim 1 , further comprising a control unit configured to generate the control signal and the second read enable signal in response to the first read enable signal and a second select signal.3. The semiconductor apparatus according to claim 2 , wherein the control unit generates the second read enable signal by delaying the first read enable signal.4. The semiconductor apparatus according to claim 3 , wherein the first select signal comprises a signal enabled during a write operation.5. The semiconductor apparatus according to claim 4 , wherein the second select signal comprises a signal enabled during a read operation.6. The ...

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06-03-2014 дата публикации

SEMICONDUCTOR DEVICE AND DATA OUTPUT CIRCUIT THEREFOR

Номер: US20140063979A1
Автор: LEE Sang Ho
Принадлежит: SK HYNIX INC.

A semiconductor device includes a memory cell array configured to include a plurality of memory cells connected between a plurality of bit lines and a plurality of word lines, a bit line sense amplifier connected to a bit line of the bit lines and configured to amplify data stored in a selected memory cell and transfer the amplified data to a segment I/O line, a control signal generator configured to determine a level of an I/O switch control signal in response to a level of a power source voltage, and a local sense amplifier connected between the segment I/O line and an local I/O line and configured to couple or separate the segment I/O line and the local I/O line in response to the I/O switch control signal, amplify the data transferred to the segment I/O line, and supply the amplified data to the local I/O line. 1. A semiconductor device , comprising:a memory cell array configured to comprise a plurality of memory cells connected between a plurality of bit lines and a plurality of word lines;a bit line sense amplifier (BLSA) connected to a bit line of the bit lines and configured to amplify data stored in a selected memory cell and transfer the amplified data to a segment input/output (I/O) line;a control signal generator configured to determine a level of an I/O switch control signal in response to a level of a power source voltage; anda local sense amplifier (LSA) connected between the segment I/O line and an local I/O line and configured to couple or separate the segment I/O line and the local I/O line in response to the I/O switch control signal, amplify the data transferred to the segment I/O line, and supply the amplified data to the local I/O line.2. The semiconductor device according to claim 1 , wherein the control signal generator outputs the I/O switch control signal in response to a pre-switching control signal and a level detection signal determined by the level of the power source voltage.3. The semiconductor device according to claim 2 , wherein ...

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06-03-2014 дата публикации

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE

Номер: US20140063992A1
Автор: YOSHIDA Soichiro
Принадлежит: Elpida Memory, Inc

A semiconductor device includes a plurality of memory cell arrays each including a plurality of memory cells and a first bit line coupled to the memory cells, a second bit line, a first voltage line, a plurality of first sense amplifiers each including a first transistor of which a gate is coupled to the first bit line of a corresponding one of the memory cell arrays and a second transistor, the first and second transistors in each of the first sense amplifiers being coupled in series between the second bit line and the first voltage line, a temperature detection circuit configured to detect a temperature of the semiconductor device, and a control circuit configured to receive an output of the temperature detection circuit and to supply a control signal to the gate of each of the second transistors. 1. A semiconductor device , comprising:a plurality of memory cell arrays each including a plurality of memory cells and a first bit line coupled to the memory cells;a second bit line;a first voltage line;a plurality of first sense amplifiers each including a first transistor of which a gate is coupled to the first bit line of a corresponding one of the memory cell arrays and a second transistor, the first and second transistors in each of the first sense amplifiers being coupled in series between the second bit line and the first voltage line;a temperature detection circuit configured to detect a temperature of the semiconductor device; anda control circuit configured to receive an output of the temperature detection circuit and to supply a control signal to the gate of each of the second transistors.2. The semiconductor device as claimed in claim 1 , further comprising a sense amplifier circuit including an amplifying circuit and a third transistor claim 1 , the sense amplifying circuit and the third transistor being coupled in series between the second bit line and a second voltage line claim 1 , the control circuit being configured to supply an additional control ...

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06-03-2014 дата публикации

SEMICONDUCTOR DEVICE INCLUDING BURIED GATE, MODULE AND SYSTEM, AND METHOD FOR MANUFACTURING

Номер: US20140064004A1
Автор: JANG Tae Su
Принадлежит: SK HYNIX INC.

An embodiment of the semiconductor device includes a recess formed in an active region, a gate buried in a lower part of the recess, a first capping insulation film formed over the gate, a second capping insulation film formed over the first capping insulation film, and a third capping insulation film formed over the second capping insulation film. In the semiconductor device including the buried gate, mechanical stress caused by a nitride film can be reduced by reducing the volume of a nitride film in a capping insulation film formed over a buried gate, and the ratio of silicon to nitrogen of the nitride film is adjusted, so that mechanical stress is reduced, resulting in improvement of operation characteristics of the semiconductor device. 1. A semiconductor device comprising:a recess formed in an active region;a gate buried in a lower part of the recess;a first capping insulation film formed over the gate;a second capping insulation film formed over the first capping insulation film; anda third capping insulation film formed over the second capping insulation film so as to fill the recess.2. The semiconductor device according to claim 1 , wherein the first capping insulation film comprises a silicon nitride film having a higher nitrogen ratio than a SiNmaterial.3. The semiconductor device according to claim 1 , wherein the first capping insulation film is formed over a sidewall of the recess and over the gate.4. The semiconductor device according to claim 1 , wherein the second capping insulation film includes an oxide film in which the first capping insulation film is partially oxidized.5. The semiconductor device according to claim 1 , wherein the third capping insulation film comprises a silicon nitride film having a higher nitrogen ratio than a SiNmaterial.6. The semiconductor device according to claim 1 , wherein the third capping insulation film includes an oxide film.7. The semiconductor device according to claim 6 , wherein the third capping insulation ...

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06-03-2014 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME

Номер: US20140064005A1
Автор: JANG Woong-Ju
Принадлежит: SK HYNIX INC.

A semiconductor memory device includes a bit line pre-sense amplifier configured to sense a potential difference between bit line pair and amplify the voltages of the bit line pair based on the sensed potential difference, a bit line main sense amplifier configured to sense a potential difference between the bit line pair and amplify the voltages of the bit line pair to first and second driving voltages based on the sensed potential difference, and a power supplying controller configured to supply the second driving voltage to the bit line pre-sense amplifier and the bit line main sense amplifier. 1. A semiconductor memory device , comprising:a bit line pre-sense amplifier configured to sense a potential difference between bit line pair and amplify voltages of the bit line pair based on the sensed potential difference;a bit line main sense amplifier configured to sense a potential difference between the bit line pair and amplify voltages of the bit line pair to first and second driving voltages based on the sensed potential difference; anda power supplying controller configured to supply the second driving voltage to the bit line pre-sense amplifier and the bit line main sense amplifier.2. The semiconductor memory device of claim 1 , wherein the power supplying controller supplies the second driving voltage to the bit line pre-sense amplifier and then supplies the second driving voltage to the bit line main sense amplifier.3. The semiconductor memory device of claim 1 , further comprising a power line driving unit configured to generate the first and the second driving voltages in response to first and second driving control signals.4. The semiconductor memory device of claim 3 , wherein the power supplying controller comprises:a first power source transfer unit for transferring the second driving voltage to the bit line pre-sense amplifier; anda second power source transfer unit for transferring the second driving voltage to the bit line main sense amplifier.5. The ...

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06-03-2014 дата публикации

JUNCTIONLESS SEMICONDUCTOR DEVICE HAVING BURIED GATE, APPARATUS INCLUDING THE SAME, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE

Номер: US20140064006A1
Принадлежит: SK HYNIX INC.

A junctionless semiconductor device having a buried gate, a module and system each having the same, and a method for forming the semiconductor device are disclosed. A source, a drain, and a body of a semiconductor device having a buried gate are doped with the same type of impurities, so that the junctionless semiconductor device does not include a PN junction between the source and the body or between the body and the drain. As a result, a leakage current caused by GIDL is reduced so that operation characteristics of the semiconductor device are improved and the size of a current-flowing region is increased, resulting in an increased operation current. 1. A junctionless semiconductor device comprising:an active region disposed over an underlying substrate and defined by a device isolation film over the underlying substrate;an insulation layer disposed between the active region and the underlying substrate; anda plurality of buried gates formed in the device isolation film and the active region,wherein source and drain regions and a body in the active region around a buried gate are doped with the same-type impurities.2. The junctionless semiconductor device according to claim 1 , wherein the impurities are implanted into the active region with substantially uniform density.3. The junctionless semiconductor device according to claim 1 , wherein the active region is formed of a silicon layer claim 1 , and the impurities are N-type impurities.4. The junctionless semiconductor device according to claim 1 , wherein the active region is formed using any of a silicon germanium (SiGe) substrate claim 1 , a germanium (Ge) substrate claim 1 , and a group 3 compound semiconductor substrate or a group 5 compound semiconductor substrate claim 1 , and the impurities are P-type impurities.5. The junctionless semiconductor device according to claim 1 , wherein the active region is isolated from the underlying substrate by the insulation layer.6. The junctionless semiconductor ...

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06-03-2014 дата публикации

SEMICONDUCTOR INTEGRATED CIRCUIT HAVING DIFFERENTIAL SIGNAL TRANSMISSION STRUCTURE AND METHOD FOR DRIVING THE SAME

Номер: US20140064007A1
Автор: KIM Ki-Up
Принадлежит: SK HYNIX INC.

A semiconductor integrated circuit includes an input data line pair, a sense amplifier configured to sense and amplify data loaded in the input data line pair and transmit the amplified data to an output data line pair, in response to a control signal, and a sense amplification controller configured to sense an amplification level of the output data line pair, limit an activation period of a sense amplification enable signal, and output the limited signal as the control signal. 1. A semiconductor integrated circuit , comprising:an input data line pair;a sense amplifier configured to sense and amplify data loaded on the input data line pair and output the amplified data to an output data line pair, in response to a control signal; anda sense amplification controller configured to detect an amplification level on the output data line pair, and output the control signal for controlling the sense amplifier based on a sense amplification enable signal and the detected amplification level.2. The semiconductor integrated circuit of claim 1 , wherein the sense amplification enable signal is activated during a predetermined period in response to a command.3. The semiconductor integrated circuit of claim 1 , wherein the sense amplification controller comprises:a reset unit configured to reset a sensing node in response to the sense amplification enable signal;a sensing driving unit configured to sense voltage levels of the output data line pair and drive the sensing node to a predetermined voltage level; andan output unit configured to output the control signal in response to the sense amplification enable signal and a voltage on the sensing node.4. The semiconductor integrated circuit of claim 3 , wherein the reset unit comprises an NMOS transistor having a source coupled to a ground voltage terminal claim 3 , a drain coupled to the sensing node claim 3 , and a gate to receive an inverted sense amplification enable signal.5. The semiconductor integrated circuit of claim 3 , ...

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13-03-2014 дата публикации

Adjusting bit-line discharge time in memory arrays based on characterized word-line delay and gate delay

Номер: US20140071775A1
Принадлежит: LSI Corp

A memory tracking circuit controls discharge duration of a tracking bit-line based on (i) a signal received at the far end of a tracking row after a propagation delay and (ii) a signal applied to a transistor-based gate delay. The tracking circuit (i) extends the discharge duration when one or more of (a) the propagation delay and (b) the transistor-based gate delay is shorter than an uncontrolled discharge duration of the tracking bit-line, and (ii) does not extend the discharge duration otherwise. Based on the discharge duration, the tracking circuit activates a reset signal that resets a clock-pulse generator to switch the memory from an access operation to a recess state. Controlling the discharge duration, and consequently the reset signal, based on the propagation delay and the gate delay allows the clock-pulse generator to adjust access times to account for the memory array configuration and process, temperature, and voltage conditions.

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