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Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 897. Отображено 100.
14-06-2012 дата публикации

Method of forming a gettering structure and the structure therefor

Номер: US20120146024A1
Автор: David Lysacek, Jana Vojtechovska, Lubomir Dornak, Lukas Valek, Petr Kostelnik, Petr Panek
Принадлежит: Individual

At least one exemplary embodiment is directed to a method of forming a multilayered Bettering structure that can be used to control wafer warpage.

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Номер записи: 1
14-06-2012 дата публикации

Method for manufacturing semiconductor device

Номер: US20120149170A1
Автор: Toru Nakazawa
Принадлежит: Canon Inc

A method includes forming first insulating films on first and second faces of a substrate, removing the first insulating film on the second face, forming polysilicon films on the first insulating film on the first face and the second face, forming second insulating films on the polysilicon films on the first face and the second face, etching the second insulating film on the first face using a mask including an opening, removing the second insulating films on the first face and the second face, removing the polysilicon film on the side of the first face and forming a passivation film which protects the polysilicon film on the side of the second face so that the polysilicon film on the side of the second face is not removed in the polysilicon film removing step, after the polysilicon film forming step and before the polysilicon film removing step.

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Номер записи: 2
22-11-2012 дата публикации

Associative memory

Номер: US20120296933A1
Автор: Gannady Lapir, Harry Urbshat
Принадлежит: BDGB Enterprise Software SARL

A computer-implemented method comprising retrieving documents in response to an input query based on a similarity measure.

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Номер записи: 3
25-04-2013 дата публикации

PROCESSES FOR SUPPRESSING MINORITY CARRIER LIFETIME DEGRADATION IN SILICON WAFERS

Номер: US20130102129A1
Автор: Falster Robert J., Voronkov Vladimir V.
Принадлежит: MEMC SINGAPORE PTE. LTD. (UEN200614794D)

Processes for suppressing minority carrier lifetime degradation in silicon wafers are disclosed. The processes involve quench cooling the wafers to increase the density of nano-precipitates in the silicon wafers and the rate at which interstitial atoms are consumed by the nano-precipitates. 1. A process to suppress minority carrier lifetime degradation related to a minority carrier lifetime degradation defect in a silicon wafer comprising boron , boron being present in the wafer in a concentration of at least about 10atoms/cm , the degradation defect comprising a fast-diffusing component and a dimeric oxygen-containing component , the process comprising:{'sub': '1', 'heating the silicon wafer to a temperature T, which is sufficient to dissolve pre-existing nano-precipitates of the fast-diffusing component of the degradation defect;'}{'sub': 1', '2', '1, 'cooling the silicon wafer from Tto a temperature Tat a cooling rate Rof at least about 100° C./sec; and'}{'sub': 2', '3', '2', '1', '2, 'cooling the silicon wafer from Tto a temperature Tat a cooling rate R, wherein the ratio of Rto Ris at least about 2:1.'}2. The process as set forth in wherein the pre-existing nano-precipitates dissolved in the heating step are composed of boron claim 1 , copper claim 1 , nickel or combinations thereof.3. The process as set forth in wherein the pre-existing nano-precipitates dissolved in the heating step are composed of boron.4. The process as set forth in wherein the ratio of Rto Ris at least about 3:1.5. The process as set forth in wherein the ratio of Rto Ris at least about 10:1.6. The process as set forth in wherein the ratio of Rto Ris at least about 50:1.7. The process as set forth in wherein minority charge carriers are generated while the wafer is cooled from Tto T.8. The process as set forth in wherein minority charge carriers are generated by illuminating the wafer while the wafer is cooled from Tto T.9. The process as set forth in wherein minority charge carriers are ...

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Номер записи: 4
11-07-2013 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR APPARATUS

Номер: US20130178046A1
Автор: CHEN CHIA-NAN, HSIEH Yen-Chang, LI Chun-Chao, Liu Heng, Sheu Jinn Kong, Shih Ya-Hsuan
Принадлежит: PHOSTEK, INC.

A method of manufacturing a semiconductor apparatus is disclosed. A first-type doped layer, a second-type doped layer, and an internal electrical connection layer are formed. The internal electrical connection layer is deposited and electrically coupled between the first-type doped layer and the second-type doped layer. In one embodiment, the internal electrical connection layer is formed by using a group IV based precursor and nitrogen based precursor. In another embodiment, the internal electrical connection layer is formed by a mixture comprising a carbon-contained doping source, and the internal electrical connection layer has a carbon concentration greater than 10atoms/cm. In a further embodiment, the internal electrical connection layer is formed at a temperature lower than those of the first-type doped layer and the second-type doped layer. 1. A method of manufacturing a semiconductor apparatus , comprising:providing a base structure;forming a first-type doped layer above the base structure;forming an internal electrical connection layer by using a mixture comprising a group IV-based precursor and a nitrogen-based precursor, the number of atoms of group IV element and nitrogen element is greater than 50% of the total number of atoms in the internal electrical connection layer; andforming a second-type doped layer, the internal electrical connection layer being deposited between the first-type doped layer and the second-type doped layer, and being electrically coupled between the first-type doped layer and the second-type doped layer.2. The method of claim 1 , wherein the step of forming the internal electrical connection layer comprises using a carbon-based precursor.3. The method of claim 1 , wherein the step of forming the internal electrical connection layer comprises using carbon as a doping source such that the internal electrical connection layer includes a carbon element with a concentration greater than 10atoms/cm.4. The method of claim 1 , wherein ...

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Номер записи: 5
15-08-2013 дата публикации

DIMENSIONAL SILICA-BASED POROUS SILICON STRUCTURES AND METHODS OF FABRICATION

Номер: US20130209781A1
Автор: "OMalley Shawn Michael", Bellman Robert Alan, Borrelli Nicholas Francis, Deneka David Alan, Schneider Vitor Marino
Принадлежит:

Methods of fabricating dimensional silica-based substrates or structures comprising a porous silicon layers are contemplated. According to one embodiment, oxygen is extracted from the atomic elemental composition of a silica glass substrate by reacting a metallic gas with the substrate in a heated inert atmosphere to form a metal-oxygen complex along a surface of the substrate. The metal-oxygen complex is removed from the surface of the silica glass substrate to yield a crystalline porous silicon surface portion and one or more additional layers are formed over the crystalline porous silicon surface portion of the silica glass substrate to yield a dimensional silica-based substrate or structure comprising the porous silicon layer. Embodiments are also contemplated where the substrate is glass-based, but is not necessarily a silica-based glass substrate. Additional embodiments are disclosed and claimed. 1. A method of fabricating a dimensional silica glass substrate or structure having a porous silicon surface layer portion of the method comprising:providing a silica glass substrate;extracting oxygen from the atomic elemental composition of a surface portion of the silica glass substrate by reacting a metallic gas with the surface of the silica glass substrate in a heated inert atmosphere to form a metal-oxygen complex in the surface portion of the silica glass substrate, wherein the inert atmosphere is heated to a reaction temperature sufficient to facilitate the oxygen extraction; andremoving the metal-oxygen complex from the surface portion of the silica glass substrate to yield a crystalline porous silicon surface portion in the surface of the silica glass substrate;2. A method as claimed in further the step of of:utilizing the porous silicon surface portion of the silica glass substrate as a seed layer and epitaxially growing or depositing a semiconductor or crystalline material overlayer on the porous silicon surface portion of the silica glass substrate.3. A ...

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Номер записи: 6
02-01-2014 дата публикации

MANUFACTURING METHOD OF EPITAXIAL SILICON WAFER, AND EPITAXIAL SILICON WAFER

Номер: US20140001605A1
Автор: Kawashima Tadashi, NONAKA Naoya, SHINAGAWA Masayuki, UESONO Gou
Принадлежит:

A method includes: a backside-oxidation-film-formation step in which an oxidation film is formed on a backside of a silicon wafer; a backside-oxidation-film-removal step in which the oxidation film provided at an outer periphery of the silicon wafer is removed; an argon-annealing step in which the silicon wafer after the backside-oxidation-film-removal step is subjected to a heat treatment in an argon gas atmosphere at a temperature in a range from 1200 to 1220 degrees C. for 60 minutes or more and 120 minutes or less; and an epitaxial-film-formation step in which an epitaxial film is formed on a surface of the silicon wafer after the argon-annealing step. 1. A manufacturing method of an epitaxial silicon wafer provided by forming an epitaxial film on a surface of a silicon wafer added with phosphorus so that resistivity of the silicon wafer falls at or below 0.9 mΩ·cm , the method comprising:forming an oxidation film on a backside of a silicon wafer cut out from a single crystal ingot prepared by a Czochralski process;removing the oxidation film present at an outer periphery of the silicon wafer;argon annealing in which a heat treatment is applied on the silicon wafer after removing the oxidation film in an argon gas atmosphere at a temperature in a range from 1200 to 1220 degrees C. for 60 minutes or more and 120 minutes or less; andforming the epitaxial film on the surface of the silicon wafer after applying the argon annealing.2. The manufacturing method of an epitaxial silicon wafer according to claim 1 , further comprising:performing a pit-evaluation heat treatment on an evaluation silicon wafer cut out from the single crystal ingot, all of steps from the forming of the oxidation film on the backside to the forming of the epitaxial film being performed on the silicon wafer cut out from a section including a cut point of the evaluation silicon wafer when pits are observed on a surface of the evaluation silicon wafer.3. The manufacturing method of an epitaxial ...

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Номер записи: 7
13-02-2014 дата публикации

SYSTEMS AND METHODS FOR PREPARATION OF EPITAXIALLY TEXTURED THICK FILMS

Номер: US20140045346A1
Автор: Im James S.
Принадлежит: The Trustees of Columbia University in the City of New York

The disclosed subject matter relates to the use of laser crystallization of thin films to create epitaxially textured crystalline thick films. In one or more embodiments, a method for preparing a thick crystalline film includes providing a film for crystallization on a substrate, wherein at least a portion of the substrate is substantially transparent to laser irradiation, said film including a seed layer having a predominant surface crystallographic orientation; and a top layer disposed above the seed layer; irradiating the film from the back side of the substrate using a pulsed laser to melt a first portion of the top layer at an interface with the seed layer while a second portion of the top layer remains solid; and re-solidifying the first portion of the top layer to form a crystalline laser epitaxial with the seed layer thereby releasing heat to melt an adjacent portion of the top layer. 1providing a film for crystallization on a substrate, wherein at least a portion of the substrate is substantially transparent to laser irradiation, said film comprising:(a) a seed layer having a predominant surface crystallographic orientation; and(b) a top layer disposed above the seed layer;irradiating the film from the back side of the substrate using a pulsed laser to melt a first portion of the top layer at an interface with the seed layer while a second portion of the top layer remains solid; andre-solidifying the first portion of the top layer to form a crystalline laser epitaxial with the seed layer thereby releasing heat to melt an adjacent portion of the top layer.. A method for preparing a thick crystalline film, comprising: This application is a continuation of and claims the benefit under 35 U.S.C. §120 of U.S. application Ser. No. 12/275,727, filed on Nov. 21, 2008, entitled “Systems and Methods for Preparation of Epitaxially Textured Thick Films,” now U.S. Pat. No. 8,557,040, the contents of which are incorporated herein by reference, which claims the benefit ...

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Номер записи: 8
27-02-2014 дата публикации

LARGE HIGH-QUALITY EPITAXIAL WAFERS

Номер: US20140054609A1
Автор: "OLoughlin Michael", Burk Albert Augustus
Принадлежит: CREE, INC.

Large high-quality epitaxial wafers are disclosed. Embodiments of the invention provide silicon carbide epitaxial wafers with low basal plane dislocation (BPD) densities. In some embodiments, these wafers are of the 4H polytype. These wafers can be at least about 100 mm in diameter and have an epitaxial layer from about 1 micron to about microns thick. In some embodiments the wafers include an epitaxial stack with a buffer layer and a drift layer and the (BPD) density in the drift layer is less than about 2 cm. A wafer according to embodiments of the invention can be made by placing an SiC substrate wafer in a reactor and using a facile step flow to cause a majority of ad-atoms to be coincident with an edge or kink of an atomic step on a surface of the SiC substrate wafer. 1. A silicon carbide wafer having a diameter of at least 100 mm and an epitaxial layer from about 1 micron to about 300 microns thick , wherein a basal plane dislocation (BPD) density of at least a portion of the epitaxial layer is less than about 2 cm.2. The silicon carbide wafer of wherein the epitaxial layer is from about 1 to about 50 microns thick.3. The silicon carbide wafer of wherein the diameter is between about 100 and about 300 mm claim 2 , the epitaxial layer is between about 25 microns and about 35 microns thick claim 2 , and the BPD density is between about 0.5 cmand about 2 cm.4. The silicon carbide wafer of wherein the diameter is between about 100 and about 200 mm and the BPD density is less than about 1 cm.5. The silicon carbide wafer of wherein the density of basal plane dislocations in the epitaxial layer capable of causing forward voltage drift in devices made from the silicon carbide wafer is from about 0.05 cmto about 0.2 cm.6. The silicon carbide wafer of wherein the density of basal plane dislocations in the epitaxial layer capable of causing forward voltage drift in devices made from the silicon carbide wafer is less than about 0.1 cm.7. The silicon carbide wafer of ...

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Номер записи: 9
10-04-2014 дата публикации

Method for Producing a Semiconductor Device and Field-Effect Semiconductor Device

Номер: US20140097488A1
Автор: IRSIGLER Peter, Schulze Hans-Joachim
Принадлежит:

A method for producing a semiconductor device is provided. The method includes providing a wafer including a main surface and a silicon layer arranged at the main surface and having a nitrogen concentration of at least about 3*10cm, and partially out-diffusing nitrogen to reduce the nitrogen concentration at least close to the main surface. Further, a semiconductor device is provided. 1. A method for producing a semiconductor device , comprising:{'sup': 14', '−3, 'providing a wafer comprising a main surface and a silicon layer arranged at the main surface and having a nitrogen concentration of at least about 3*10cm; and'}partially out-diffusing nitrogen to reduce the nitrogen concentration at least close to the main surface.2. The method of claim 1 , wherein the nitrogen concentration of the silicon layer is reduced by at least a factor of two at least in a first portion extending from the main surface to depth of about 50 μm.3. The method of claim 1 , wherein the nitrogen concentration prior to partially out-diffusing the nitrogen is higher than about 5*10cm.4. The method of claim 1 , wherein the nitrogen concentration after partially out-diffusing the nitrogen is at the main surface lower than about 2*10cm.5. The method of claim 1 , wherein the nitrogen concentration of the silicon layer after partially out-diffusing the nitrogen is lower than about 2*10cmat least in a first portion extending from the main surface to a depth of about 50 μm.6. The method of claim 1 , wherein the wafer has a size of at least 8″.7. The method of claim 1 , wherein the wafer comprises a back surface which is arranged opposite to the main surface claim 1 , the method further comprising forming at the back surface a diffusion barrier for nitrogen prior to partially out-diffusing the nitrogen.8. The method of claim 1 , wherein partially out-diffusing the nitrogen is performed such that an oxygen concentration of the silicon layer close to the main surface is below about 2*10cm.9. The ...

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Номер записи: 10
01-01-2015 дата публикации

METHOD FOR MANUFACTURING SILICON SINGLE CRYSTAL WAFER AND ELECTRONIC DEVICE

Номер: US20150001680A1
Автор: Ebara Koji, Oka Tetsuya
Принадлежит:

According to the present invention, there is provided a method for manufacturing a silicon single crystal wafer, wherein a first heat treatment for holding a silicon single crystal wafer in an oxygen containing atmosphere at a first heat treatment temperature for 1 to 60 seconds and cooling it to 800° C. or less at a temperature falling rate of 1 to 100° C./second by using a rapid heating/rapid cooling apparatus is performed to inwardly diffuse oxygen and form an oxygen concentration peak region near a surface of the silicon single crystal wafer, and then a second heat treatment is performed to agglomerate oxygen in the silicon single crystal wafer into the oxygen concentration peak region. As a result, it is possible to provide the method for manufacturing a silicon single crystal wafer that enables forming an excellent gettering layer close to a device forming region. 110-. (canceled)11. A method for manufacturing a silicon single crystal wafer , whereina first heat treatment for holding a silicon single crystal wafer in an oxygen containing atmosphere at a first heat treatment temperature for 1 to 60 seconds and cooling it to 800° C. or less at a temperature falling rate of 1 to 100° C./second by using a rapid heating/rapid cooling apparatus is performed to inwardly diffuse oxygen and form an oxygen concentration peak region near a surface of the silicon single crystal wafer, and then a second heat treatment is performed to agglomerate oxygen in the silicon single crystal wafer into the oxygen concentration peak region.12. The method for manufacturing a silicon single crystal wafer according to claim 11 ,{'sup': 17', '3', '17', '3, "wherein oxygen concentration of the silicon single crystal to which the first and second heat treatments are performed is set to 4×10atoms/cm(ASTM'79) or more and 16×10atoms/cm(ASTM'79) or less."}13. The method for manufacturing a silicon single crystal wafer according to claim 11 ,wherein conditions of the first and second heat ...

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Номер записи: 11
07-01-2016 дата публикации

METHOD FOR PURIFYING METALLURGICAL SILICON

Номер: US20160005623A1
Автор: Ruda Harry, Shams-Kolahi Wahid, Souza Christina F
Принадлежит:

The present disclosure provides a method for upgrading materials, for example crystalline metallurgical silicon, to remove impurities using microwave processing to induce migration of impurities in the material to one or both of internal surfaces where they are trapped and neutralized or one or more external surfaces followed by trapping of the impurity by binding to gettering agents on the surface with subsequent removal of the impurity and gettering agent. 1. A method for removing impurities from semiconductors ,comprising: irradiating a semiconductor with microwave radiation with power in a range from about 0.3 kW to about 300 kW, at a frequency in a range from about 300 MHz to 600 GHz for a selected period of time to cause microwave thermal and field induced migration of impurities to one or more internal interfaces at which the impurities are trapped and neutralized and/or to one or more external surfaces having located thereon gettering agents at which the impurities bind with the gettering agent; andfor impurities bound to the gettering agent on the one or more external surfaces, removing the gettering agents.2. The method according to wherein the gettering agents are removed by any one or combination of chemical etching claim 1 , and acid leaching.3. The method according to including varying the frequency of irradiation in said power and frequency range.4. The method according to including placing the semiconductor on a susceptor material more susceptible to microwave heating for locally raising the temperature of the semiconductor during microwave processing.5. The method according to claim 4 , wherein said susceptor material is a microwave absorbing ceramic.6. The method according to claim 5 , wherein said susceptor material any one of silicon carbide and alumina.7. The method according to wherein said selected period of time is from seconds to ½ hour.8. The method according to wherein said semiconductor is metallurgical grade silicon.9. The method ...

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Номер записи: 12
08-01-2015 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

Номер: US20150008478A1
Автор: Amano Shinji, CHENG Weitao, OKABE YOSHIFUMI, Shiga Tomofusa
Принадлежит:

A manufacturing method of a semiconductor device includes applying at least one of a particle ray and a radial ray to a surface of a semiconductor substrate on which a transistor including a gate insulation film and a gate electrode has been formed adjacent to the surface, and annealing the semiconductor substrate for recovering a crystal defect contained in the gate insulation film and the gate electrode, after the applying. Further, the manufacturing method includes pre-annealing for reducing a content of a hydrogen molecule and a water molecule contained in the gate insulation film and the gate electrode to a predetermined concentration, before the applying. In the semiconductor device manufactured by this method, a concentration of thermally stable defect existing in the gate insulation film is reduced to a predetermined concentration. 1. A manufacturing method of a semiconductor device , comprising:forming an element including a transistor having a gate insulation film and a gate electrode adjacent to a surface of a semiconductor substrate;applying at least one of a particle ray and a radial ray to the semiconductor substrate from a side adjacent to the surface, after the the forming of the element;annealing the semiconductor substrate by heating the semiconductor substrate for recovering a crystal defect contained in the gate insulation film and the gate electrode, after the applying; andpre-annealing the semiconductor substrate by heating the semiconductor substrate for reducing a content of a hydrogen molecule and a water molecule contained in the gate insulation film and the gate electrode, before the applying.2. The manufacturing method of the semiconductor device according to claim 1 , wherein the content is made less than 6×10cmby the pre-annealing.3. The manufacturing method of the semiconductor device according to claim 2 , wherein the content is made equal to or less than 1×10cmby the pre-annealing.4. The manufacturing method of the semiconductor ...

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Номер записи: 13
15-01-2015 дата публикации

METHOD OF FORMING SALICIDE BLOCK WITH REDUCED DEFECTS

Номер: US20150017785A1
Автор: Chang Hsu Sheng, Chen Chien Wei, GU Meimei, Yi Yijun
Принадлежит: SHANGHAI HUALI MICROELECTRONICS CORPORATION

A method of forming a salicide block with reduced defects is disclosed, the method including performing an ultraviolet cure process on a silicon nitride layer deposited in a previous step. High-energy ultraviolet light used in the ultraviolet cure process breaks the hydrogen-containing chemical bonds such as silicon-hydrogen and nitrogen-hydrogen in the silicon nitride layer, and the dissociated hydrogen forms molecular hydrogen which is thereafter evacuated away by a vacuuming apparatus. In this way, the hydrogen content in the silicon nitride layer can be effectively decreased and the reaction between hydrogen in the silicon nitride layer and photoresist subsequently coated thereon can hence be reduced. As a result, a salicide block with reduced defects can be obtained, thus improving process reliability and product yield. 1. A method of forming a salicide block , comprising the following steps in the sequence set forth:depositing a silicon nitride layer over a silicon wafer by plasma enhanced chemical vapor deposition, wherein the silicon nitride layer includes hydrogen-containing chemical bonds such as silicon-hydrogen and nitrogen-hydrogen;performing an ultraviolet cure process on the silicon nitride layer to break the hydrogen-containing chemical bonds and removing hydrogen; andpatterning the silicon nitride layer by photolithography and etching to form a salicide block.2. The method of claim 1 , further comprising the steps of:sputtering a metal over the silicon wafer;performing a rapid annealing process to form metal silicides over portions of the silicon wafer not covered by the salicide block; andstripping away the remaining metal not formed into the metal silicides.3. The method of claim 1 , wherein performing an ultraviolet cure process on the silicon nitride layer comprises:disposing the silicon wafer with the silicon nitride layer deposited thereon in an ultraviolet chamber; andirradiating ultraviolet light on the silicon nitride layer and vacuuming ...

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Номер записи: 14
18-01-2018 дата публикации

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

Номер: US20180019327A1
Автор: Chiu Yi-Wei, HO Wen-Zhong, Hsu Chi-Chin, Weng Tzu-Chan
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin structure over the base. The fin structure has sidewalls. The semiconductor device structure includes a passivation layer over the sidewalls. The passivation layer includes dopants. The dopants include at least one element selected from group 4A elements, and the dopants and the substrate are made of different materials. The semiconductor device structure includes an isolation layer over the base and surrounding the fin structure and the passivation layer. A first upper portion of the fin structure and a second upper portion of the passivation layer protrude from the isolation layer. The semiconductor device structure includes a gate electrode over the first upper portion of the fin structure and the second upper portion of the passivation layer. 1. A semiconductor device structure , comprising:a substrate having a base and a fin structure over the base, wherein the fin structure has sidewalls;a passivation layer over the sidewalls, wherein the passivation layer comprises dopants, the dopants comprise at least one element selected from group 4A elements, and the dopants and the substrate are made of different materials;an isolation layer over the base and surrounding the fin structure and the passivation layer, wherein a first upper portion of the fin structure and a second upper portion of the passivation layer protrude from the isolation layer, and the second upper portion of the passivation layer covers top portions of the sidewalls;a gate electrode over the first upper portion of the fin structure and the second upper portion of the passivation layer, wherein the second upper portion of the passivation layer is between the top portions of the sidewalls and the gate electrode; anda gate dielectric layer between the gate electrode and the fin structure and between the gate electrode and the second upper portion of the passivation layer, ...

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Номер записи: 15
16-01-2020 дата публикации

METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE HAVING OXIDE LAYER

Номер: US20200020544A1
Автор: Chang I-Ming, Chao Huang-Lin, Fang Ziwei, Lin Chih-Cheng, WU Chi-Ying, You Wei-Ming
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A method for forming a semiconductor device structure is provided. The method includes depositing a gate dielectric layer over a substrate. The substrate has a base portion and a first fin portion over the base portion, and the gate dielectric layer is over the first fin portion. The method includes forming a gate electrode layer over the gate dielectric layer. The gate electrode layer includes fluorine. The method includes annealing the gate electrode layer and the gate dielectric layer so that fluorine from the gate electrode layer diffuses into the gate dielectric layer. 1. A method for forming a semiconductor device structure , comprising:depositing a gate dielectric layer over a substrate, wherein the substrate has a base portion and a first fin portion over the base portion, and the gate dielectric layer is over the first fin portion;forming a gate electrode layer over the gate dielectric layer, wherein the gate electrode layer comprises fluorine; andannealing the gate electrode layer and the gate dielectric layer so that fluorine from the gate electrode layer diffuses into the gate dielectric layer.2. The method for forming the semiconductor device structure as claimed in claim 1 , further comprising:forming a semiconductor oxynitride layer over the first fin portion before depositing the gate dielectric layer over the substrate, wherein the gate dielectric layer is formed over the semiconductor oxynitride layer.3. The method for forming the semiconductor device structure as claimed in claim 2 , wherein the semiconductor oxynitride layer is formed using a rapid thermal nitridation treatment.4. The method for forming the semiconductor device structure as claimed in claim 1 , further comprising:annealing the gate dielectric layer using an annealing gas containing nitrous oxide before forming the gate electrode layer over the gate dielectric layer.5. The method for forming the semiconductor device structure as claimed in claim 1 , wherein the substrate further ...

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Номер записи: 16
22-01-2015 дата публикации

Finlike Structures and Methods of Making Same

Номер: US20150024566A1
Автор: Chen Chao-Cheng, Jang Syun-Ming, Yeh Ming-Hsi
Принадлежит:

Semiconductor materials, particularly III-V materials used to form, e.g., a finlike structure can suffer structural damage during chemical mechanical polishing steps. This damage can be reduced or eliminated by oxidizing the damaged surface of the material and then etching away the oxidized material. The etching step can be accomplished simultaneously with a step of etching back a patterned oxide layers, such as a shallow trench isolation layer. 1. A method of forming a semiconductor device , the method comprising:forming a patterned dielectric layer on a substrate, the patterned dielectric layer having openings therein;forming a first semiconductor material in the openings; and oxidizing the first semiconductor material, thereby forming an oxidized layer on the first semiconductor material; and', 'removing at least a portion of the oxidized layer., 'performing one or more process cycles, each process cycle comprising2. The method of claim 1 , wherein the removing at least the portion of the oxidized layer further comprises removing a portion of the patterned dielectric layer.3. The method of claim 1 , wherein the forming the patterned dielectric layer comprises:forming a dielectric layer on the substrate; andpatterning the dielectric layer, wherein the openings are formed in the dielectric layer.4. The method of claim 1 , wherein the forming the patterned dielectric layer comprises:forming trenches in the substrate;forming a dielectric material in the trenches, wherein the dielectric material overfills the trenches;planarizing the dielectric material, wherein a topmost surface of the dielectric material is substantially coplanar with a topmost surface of the substrate; andremoving a portion of the substrate, wherein sidewalls of the dielectric material are at least partially exposed.5. The method of claim 1 , wherein the forming the first semiconductor material in the openings comprises:epitaxially growing the first semiconductor material in the openings; ...

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Номер записи: 17
28-01-2016 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20160027867A1
Автор: Matsushita Kenichi
Принадлежит:

A semiconductor device includes a semiconductor layer having a first p-type semiconductor region at a first surface and a first n-type semiconductor region at a second surface opposite the first. A second n-type semiconductor region having a n-type dopant concentration lower than the first n-type semiconductor region is between the first p-type and first n-type semiconductor regions. A third n-type semiconductor region is disposed between the second n-type semiconductor region and the first p-type semiconductor region. a fourth n-type semiconductor region is disposed between the first n-type semiconductor region and the second n-type semiconductor region. The fourth n-type semiconductor region has a stored carrier lifetime longer than the third n-type semiconductor region and a crystal lattice defect level is higher in the third n-type semiconductor than in the fourth n-type semiconductor region. An anode is disposed on the first surface and a cathode is disposed on the second surface. 1. A semiconductor device , comprising:a semiconductor layer that has a first surface and a second surface opposite the first surface;a first p-type semiconductor region in the semiconductor layer at the first surface;a first n-type semiconductor region in the semiconductor layer at the second surface;a second n-type semiconductor region in the semiconductor layer between the first p-type semiconductor region and the first n-type semiconductor region, the second n-type semiconductor region having a concentration of n-type dopant that is lower than a concentration of n-type dopant in the first n-type semiconductor region;a third n-type semiconductor region in the semiconductor layer between the first p-type semiconductor region and the second n-type semiconductor region, the third n-type semiconductor region having a concentration of n-type dopant lower than the concentration of n-type dopant in the second n-type semiconductor region;a fourth n-type semiconductor region in the ...

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Номер записи: 18
24-01-2019 дата публикации

METHOD OF PRODUCING SEMICONDUCTOR EPITAXIAL WAFER, SEMICONDUCTOR EPITAXIAL WAFER, AND METHOD OF PRODUCING SOLID-STATE IMAGE SENSOR

Номер: US20190027533A1
Автор: OKUYAMA Ryosuke
Принадлежит: SUMCO CORPORATION

A production method for a semiconductor epitaxial wafer includes: irradiating a surface of a semiconductor wafer with cluster ions to form a modified layer in a surface portion of the semiconductor wafer, in which the modified layer includes a constituent element of the cluster ions in solid solution. The production method further includes forming an epitaxial layer on the modified layer of the semiconductor wafer. The irradiating is performed such that a portion of the modified layer in a thickness direction becomes an amorphous layer and an average depth of an amorphous layer surface from a semiconductor wafer surface-side of the amorphous layer is at least 20 nm from the surface of the semiconductor wafer. 1. A method of producing a semiconductor epitaxial wafer , comprising:irradiating a surface of a semiconductor wafer with cluster ions to form a modified layer in a surface portion of the semiconductor wafer, the modified layer including a constituent element of the cluster ions in solid solution; andforming an epitaxial layer on the modified layer of the semiconductor wafer, a portion of the modified layer in a thickness direction becomes an amorphous layer, the amorphous layer having a first surface and a second surface disposed on a side opposite of the first surface, the first surface being closer to the surface of the semiconductor wafer than the second surface, and', 'an average depth of the first surface of the amorphous layer from the surface of the semiconductor wafer is at least 20 nm., 'wherein the irradiating is performed such that'}2. The method of producing the semiconductor epitaxial wafer of claim 1 , wherein the irradiating is performed such that the average depth is at least 20 nm and no greater than 200 nm from the surface of the semiconductor wafer.3. The method of producing the semiconductor epitaxial wafer of claim 1 , wherein the irradiating is performed such that an average thickness of the amorphous layer is no greater than 100 nm.4. ...

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Номер записи: 19
23-01-2020 дата публикации

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20200027748A1
Автор: Nakamura Katsumi
Принадлежит: Mitsubishi Electric Corporation

A semiconductor device of the present invention includes a substrate having a drift layer, metal wiring formed on an upper surface of the substrate, and an electrode formed on a back surface of the substrate, wherein the lifetime of carriers in the drift layer satisfies the following expression 1: 1. A method of manufacturing a semiconductor device , comprising:a manufacturing step of forming a first diffusion layer on an upper surface side of a substrate having a drift layer, performing film forming and performing etching;a gettering layer forming step of forming a gettering layer on a lower surface side of the drift layer exposed at a lower surface of the substrate;an annealing step of heating the substrate to capture by the gettering layer a metal impurity, contaminant atoms and damage introduced in the drift layer in the manufacturing step;a removal step of removing the gettering layer after the annealing step;a step of forming a second diffusion layer on the lower surface side of the drift layer after the removal step; anda step of forming an electrode so that the electrode contacts the second diffusion layer, wherein the gettering layer forming step includes:a step of forming doped polysilicon doped with an impurity so that the doped polysilicon contacts the drift layer exposed at the lower surface of the substrate; anda preprocessing annealing step of heating the substrate to diffuse the impurity to the lower surface side of the drift layer so that a gettering layer having crystal defects and the impurity is formed on the lower surface side of the drift layer, andwherein the doped polysilicon is also removed in the removal step.2. The method of manufacturing a semiconductor device according to claim 1 , wherein the temperature of the substrate in the preprocessing annealing step is in a range from 900 to 1000 [° C.].3. The method of manufacturing a semiconductor device according to claim 2 , wherein the density of the impurity in the doped polysilicon is ...

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Номер записи: 20
02-02-2017 дата публикации

SEMICONDUCTOR CHIP ARRANGEMENT AND METHOD THEREOF

Номер: US20170032966A1
Автор: LAVEN Johannes, Schulze Hans-Joachim
Принадлежит:

A method for processing a semiconductor carrier is provided, the method including: providing a semiconductor carrier including a doped substrate region and a device region disposed over a first side of the doped substrate region, the device region including at least part of one or more electrical devices; and implanting ions into the doped substrate region to form a gettering region in the doped substrate region of the semiconductor carrier. 1. A method for manufacturing a semiconductor device:providing a semiconductor carrier comprising a doped substrate region and a device region disposed over a first side of the doped substrate region;forming one or more electrical devices at least partially in the device region;forming a gettering region comprising hydrogen-decorated intrinsic point defect complexes in the doped substrate region of the semiconductor carrier; andadhering a metal layer disposed directly to a second side of the doped substrate region, wherein the second side of the doped substrate region faces a direction opposite to a direction which the first side of the doped substrate region faces.2. The method of claim 1 , wherein the doped substrate region comprises a highly doped region and wherein the gettering region is formed at least partially in the highly doped region.3. The method of claim 2 , wherein the highly doped region has a dopant concentration higher than a concentration of the hydrogen-decorated intrinsic point defect complexes.4. The method of claim 2 , wherein the highly doped region has a dopant concentration ten or more times higher than a concentration of the hydrogen-decorated intrinsic point defect complexes.5. The method of claim 2 , wherein the highly doped region includes a dopant carrier concentration greater than about 10cm.6. The method of claim 1 , wherein the substrate region comprises a highly doped region and an extremely highly doped region claim 1 , and wherein the gettering region is formed at least partially in at least ...

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Номер записи: 21
02-02-2017 дата публикации

Integrated Circuit Devices and Methods of Manufacturing the Same

Номер: US20170033013A1
Автор: CHOI Soo-jung, KIM Weon-Hong, LEE MIN-JOO, Song Moon-Kyun, YOO Dong-su
Принадлежит:

An integrated circuit device may include a gate insulation layer covering a top surface and opposite sidewalls of a fin-shaped active region, a gate electrode covering the gate insulation layer and a hydrogen atomic layer disposed along an interface between the fin-shaped active region and the gate insulation layer. A method of manufacturing the integrated circuit device may include forming an insulating layer covering a lower portion of a preliminary fin-shaped active region, forming a fin-shaped active region having an outer surface with an increased smoothness through annealing an upper portion of the preliminary fin-shaped active region in a hydrogen atmosphere and forming a hydrogen atomic layer covering the outer surface of the fin-shaped active region. A gate insulation layer and a gate electrode may be formed to cover a top surface and opposite sidewalls of the fin-shaped active region. 1. A method of manufacturing an integrated circuit device , the method comprising:forming a preliminary fin-shaped active region by partially etching a substrate;forming an insulating layer covering a lower, portion of the preliminary fin-shaped active region such that an upper portion of the preliminary fin-shaped active region protrudes above the insulating layer;forming a fin-shaped active region and a hydrogen atomic layer by annealing the protruding portion of the preliminary fin-shaped active region in a hydrogen atmosphere, the fin-shaped active region having a smoother surface than a surface of the preliminary fin-shaped active region and the hydrogen atomic layer covering the surface of the fin-shaped active region;forming a gate insulation layer on the hydrogen atomic layer to cover a top surface and opposite sidewalls of the fin-shaped active region; andforming a gate electrode on the gate insulation layer to cover the top surface and the opposite sidewalls of the fin-shaped active region.2. The method of claim 1 , wherein forming a fin-shaped active region and a ...

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Номер записи: 22
16-02-2017 дата публикации

Silicon wafer and method for manufacturing same

Номер: US20170044688A1
Автор: Keiichiro Hiraki, Kouzou Nakamura, Satoshi Kudo, SHUHEI Matsuda, Tegi Kim, Toshiyuki Muranaka
Принадлежит: Sumco Corp

A manufacturing method of this invention includes: a step of slicing a silicon single crystal containing boron as an acceptor and obtaining a non-heat-treated silicon wafer, a step of determining a boron concentration with respect to the non-heat-treated silicon wafer, and a step of determining an oxygen donor concentration with respect to the non-heat-treated silicon wafer, in which a determination as to whether or not to perform a heat treatment at a temperature of 300° C. or more on the non-heat-treated silicon wafer is made based on a boron concentration determined in the step of determining a boron concentration, and an oxygen donor concentration determined in the step of determining an oxygen donor concentration. By this means, a wafer in which unevenly distributed LPDs that are present on the wafer are reduced is obtained.

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Номер записи: 23
06-02-2020 дата публикации

Photoelectric conversion device and manufacturing method and apparatus thereof

Номер: US20200043672A1
Автор: Haruhi Oooka, Hideyuki Nakao, Kenji Fujinaga, Kenji Todori, Shigehiko Mori, Takeshi Gotanda
Принадлежит: Toshiba Corp

A method for manufacturing a photoelectric conversion device, that includes: forming a laminate structure of a substrate, a transparent electrode, an active layer produced by wet-coating, and a counter electrode, stacked in this order; and thereafter forming a cavity by: (a) pressing an adhesive material just against a defect formed on the surface of said counter electrode, and then peeling off said adhesive material together with said defect and the peripheral part thereof; or (b) sucking a defect formed on the surface of said counter electrode, so as to remove said defect and the peripheral part thereof, where said cavity penetrates through the counter electrode and unreached to the transparent electrode.

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Номер записи: 24
18-02-2021 дата публикации

SEMICONDUCTOR CHIP GETTERING

Номер: US20210050223A1
Автор: Agarwal Rahul, BARBER IVOR, Bhagavat Milind S., CHENG YUEN TING, CHOK GUAN SIN, VALLIAPPAN VENKATACHALAM
Принадлежит:

Various semiconductor chips with gettering regions and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a first side and a second side opposite the first side. The first side has a plurality of laser ablation craters. Each of the ablation craters has a bottom. A gettering region is in the semiconductor chip beneath the laser ablation craters. The gettering region includes plural structural defects. At least some of the structural defects emanate from at least some of the bottoms of the laser ablation craters. 1. A method of manufacturing , comprising:irradiating a first side of a semiconductor chip with laser pulses having a pulse duration to create a plurality of laser ablation craters, each of the ablation craters having a bottom; andwherein the pulse duration is long enough to create a gettering region in the semiconductor chip beneath the laser ablation craters, the gettering region including plural structural defects, at least some of the structural defects emanating from at least some of the bottoms of the laser ablation craters.2. The method of claim 1 , wherein at least some of the laser ablation craters overlap laterally.3. The method of claim 1 , wherein at least some of the laser ablation craters comprise sloped sidewalls.4. The method of claim 3 , wherein a first laser ablation crater of the laser ablation craters comprises sidewalls sloped in a first direction and a second laser ablation crater of the laser ablation craters adjacent to the first laser ablation crater comprises sidewalls sloped in a second direction opposite the first direction.5. The method of claim 4 , wherein some of the laser ablation craters have a first average depth and other of the laser ablation craters have a second average depth less than the first average depth and at least some of the laser ablation craters having the first average depth comprise sloped sidewalls.6. The method of claim 4 , wherein ...

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Номер записи: 25
18-02-2016 дата публикации

METHOD OF OUTGASSING A MASK MATERIAL DEPOSITED OVER A WORKPIECE IN A PROCESS TOOL

Номер: US20160049313A1
Автор: Eaton Brad, Kumar Ajay, Kumar Prabhat, Lei Wei-Sheng, Papanu James S., Wohlert Martin S.
Принадлежит:

Embodiments of the invention include methods and apparatuses for outgassing a workpiece prior to a plasma processing operation. An embodiment of the invention may comprise transferring a workpiece having a mask to an outgassing station that has one or more heating elements. The workpiece may then be heated to an outgassing temperature that causes moisture from the mask layer to be outgassed. After outgassing the workpiece, the workpiece may be transferred to a plasma processing chamber. In an additional embodiment, one or more outgassing stations may be located within a process tool that has a factory interface, a load lock coupled to the factory interface, a transfer chamber coupled to the load lock, and a plasma processing chamber coupled to the transfer chamber. According to an embodiment, an outgassing station may be located within any of the components of the process tool. 1. A method for outgassing a workpiece , comprising:transferring a workpiece having a mask to an outgassing station having one or more heating elements;heating the workpiece to an outgassing temperature that causes moisture from the mask layer to be outgassed, wherein heating the workpiece to an outgassing temperature is performed concurrently with at least one other process; andtransferring the workpiece to a plasma processing chamber after the mask layer has been outgassed.2. The method of claim 1 , wherein the outgassing station is within a process tool that comprises a factory interface claim 1 , a load lock coupled to the factory interface claim 1 , a transfer chamber coupled to the load lock claim 1 , and the plasma processing chamber coupled to the transfer chamber.3. A method for outgassing a workpiece claim 1 , comprising:transferring a workpiece having a mask to an outgassing station having one or more heating elements;heating the workpiece to an outgassing temperature that causes moisture from the mask layer to be outgassed; andtransferring the workpiece to a plasma processing ...

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Номер записи: 26
25-02-2016 дата публикации

EXTERNAL GETTERING METHOD AND DEVICE

Номер: US20160056051A1
Автор: Pour Cheng P., Tan Michael
Принадлежит:

Disclosed embodiments include external gettering provided by electronic packaging. An external gettering element for a semiconductor substrate, which may be incorporated as part of an electronic packaging for the structure, is disclosed. Semiconductor structures and stacked semiconductor structures including an external gettering element are also disclosed. An encapsulation mold compound providing external gettering is also disclosed. Methods of fabricating such devices are also disclosed. 1. A method of providing gettering to a semiconductor device , the method comprising:providing a first semiconductor substrate, the first semiconductor substrate comprising a first section for forming semiconductor devices and a second section; andapplying electronic packaging configured to provide gettering adjacent to the second section of the first semiconductor substrate.2. The method of claim 1 , further comprising:performing a stress-relief process at the second section of the first semiconductor substrate; andapplying the electronic packaging and an external gettering element adjacent to the second section of the first semiconductor substrate.3. The method of claim 2 , wherein the electronic packaging comprises an adhesive material claim 2 , the step of applying the electronic packaging and an external gettering element further comprising:imbuing a gettering material with ions in order to attract ions or contaminants within the first semiconductor substrate toward the second section;integrating the gettering material into the adhesive material; andapplying the adhesive material to the second section of the first semiconductor substrate.4. The method of claim 3 , wherein the adhesive material is a dual-sided adhesive material claim 3 , the method further comprising:providing a second semiconductor substrate, the second semiconductor substrate comprising a third section for forming semiconductor devices and a fourth section; andadhering the second semiconductor substrate to ...

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Номер записи: 27
23-02-2017 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20170054000A1
Автор: Inoue Masanori, KUMAGAI Yuji, TAKENOIRI Shunji, TATEMICHI Shuhei
Принадлежит:

A semiconductor device with a high radiation tolerance is provided. A semiconductor device comprising a semiconductor substrate, a first body region and a second body region provided on a front surface side of the semiconductor substrate, a neck portion provided between the first body region and the second body region, a first source region formed within the first body region and a second source region formed within the second body region, a first gate electrode provided to face the first body region between the first source region and the neck portion, a second gate electrode provided to face the second body region between the second source region and the neck portion, and an insulating film continuously provided between the first gate electrode and the semiconductor substrate, between the second gate electrode and the semiconductor substrate, and on the front surface side of the neck portion, is provided. 1. A semiconductor device comprising:a semiconductor substrate of a first conductivity type;a first body region and a second body region having a second conductivity type and provided in a front surface side of the semiconductor substrate;a neck portion of the first conductivity type provided between the first body region and the second body region;a first source region having the first conductivity type and formed within the first body region and a second source region having the first conductivity type and formed within the second body region;a first gate electrode facing the first body region between the first source region and the neck portion and a second gate electrode facing the second body region between the second source region and the neck portion; andan insulating film continuously provided between the first gate electrode and the semiconductor substrate, between the second gate electrode and the semiconductor substrate, and on a front surface side of the neck portion.2. The semiconductor device according to claim 1 , wherein an end portion of the ...

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Номер записи: 28
03-03-2016 дата публикации

Method for Processing an Oxygen Containing Semiconductor Body

Номер: US20160064206A1
Автор: Hans-Joachim Schulze, Helmut Oefner
Принадлежит: INFINEON TECHNOLOGIES AG, Vdf Futureceuticals

A method for processing a semiconductor body is disclosed. In an embodiment, the method includes reducing an oxygen concentration in a silicon wafer in a first region adjoining a first surface of the silicon wafer by a first heat treatment, creating vacancies in a crystal lattice of the wafer at least in a second region adjoining the first region by implanting particles via the first surface into the wafer and forming oxygen precipitates in the second region by a second heat treatment.

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Номер записи: 29
02-03-2017 дата публикации

METHOD FOR DISSOLVING A SILICON DIOXIDE LAYER

Номер: US20170062236A1
Автор: Kononchuk Oleg, Landru Didier
Принадлежит:

This disclosure relates to a method for dissolving a silicon dioxide layer in a structure, including, from the back surface thereof to the front surface thereof, a supporting substrate, the silicon dioxide layer and a semiconductor layer, the dissolution method being implemented in a furnace in which structures are supported on a support, the dissolution method resulting in the diffusion of oxygen atoms included in the silicon dioxide layer through the semiconductor layer and generating volatile products, and the furnace including traps suitable for reacting with the volatile products, so as to reduce the concentration gradient of the volatile products parallel to the front surface of at least one structure. 1. A method for dissolving a silicon dioxide layer in a semiconductor-on-insulator type structure , the method comprising:providing semiconductor-on-insulator type structures on a support in a furnace, each of the semiconductor-on-insulator type structures comprising a rear face and a front face and including a supporting substrate, a silicon dioxide layer over the supporting substrate, and a semiconductor layer on a side of the silicon dioxide layer opposite the supporting substrate, the support configured for holding the semiconductor-on-insulator type structures with a predetermined distance between the semiconductor-on-insulator type structures, the front face of one of the semiconductor-on-insulator type structures opposite the rear face of another of the semiconductor-on-insulator type structures adjacent to the front face of the one of the semiconductor-on-insulator type structures;providing a non-oxidizing atmosphere within the furnace by providing an inert or reducing gas flow entering the furnace through a gas inlet;heating the semiconductor-on-insulator type structures within the furnace and causing the diffusion of oxygen atoms in the silicon dioxide layers through the semiconductor layers; andreacting oxygen in the inert or reducing gas flow with ...

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Номер записи: 30
12-03-2015 дата публикации

Cup-Like Getter Scheme

Номер: US20150069539A1
Автор: Chan Chih-Jen, Chang Che-Ming, CHOU Chung-Yen, HSIEH Yuan-Chih, LIN SHIH-WEI, Tseng Lee-Chuan
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure relates to a method of gettering that provides for a high efficiency gettering process by increasing an area in which a getter layer is deposited, and an associated apparatus. In some embodiments, the method is performed by providing a substrate into a processing chamber having one or more residual gases. A cavity is formed within a top surface of the substrate. The cavity has a bottom surface and sidewalls extending from the bottom surface to the top surface. A getter layer, which absorbs the one or more residual gases, is deposited over the substrate at a position extending from the bottom surface of the cavity to a location on the sidewalls. By depositing the getter layer to extend to a location on the sidewalls of the cavity, the area of the substrate that is able to absorb the one or more residual gases is increased. 1. A method of gettering , comprising:providing a substrate into a processing chamber having one or more residual gases;forming a cavity within a top surface of the substrate, wherein the cavity comprises a bottom surface and sidewalls extending from the bottom surface to the top surface of the substrate; anddepositing a getter layer, configured to absorb the one or more residual gases, over the substrate at a position extending from the bottom surface of the cavity to a location on the sidewalls.2. The method of claim 1 ,forming a bonding layer onto the top surface of the substrate, wherein the cavity is located between sections of the bonding layer; andselectively etching the getter layer to expose the bonding layer.3. The method of claim 2 , further comprising:depositing a protective layer over the getter layer;reducing a thickness of the protective layer to expose the getter layer overlying the bonding layer; andselectively etching the getter layer according to the protective layer to remove the getter layer overlying the bonding layer.4. The method of claim 3 , further comprising:reducing the thickness of the protective ...

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Номер записи: 31
19-03-2015 дата публикации

SEMICONDUCTOR COMPONENT HAVING A PASSIVATION LAYER AND PRODUCTION METHOD

Номер: US20150076597A1
Автор: PFAFFENLEHNER Manfred, Schmitt Markus, Schulze Hans-Joachim
Принадлежит:

A semiconductor component and a method for producing a semiconductor component are described. The semiconductor component includes a semiconductor body including an inner zone and an edge zone, and a passivation layer, which is arranged at least on a surface of the semiconductor body adjoining the edge zone. The passivation layer includes a semiconductor oxide and that includes a defect region having crystal defects that serve as getter centers for contaminations. 1. A semiconductor component comprising:a semiconductor body comprising an inner zone and an edge zone; anda passivation layer, which is arranged at least on a surface of the semiconductor body adjoining the edge zone, which comprises a semiconductor oxide and which comprises a defect region having crystal defects that serve as getter centers for contaminations.2. The semiconductor component as claimed in claim 1 , wherein the passivation layer comprises:a first sublayer adjoining the semiconductor body in the region of the first surface; anda second sublayer on the first sublayer, wherein the defect region is arranged in the second sublayer.3. The semiconductor component as claimed in claim 1 , wherein a concentration of crystal defects in the at least one defect region is greater than 1E14 cm.4. The semiconductor component as claimed in claim 1 , wherein a concentration of crystal defects in the first passivation layer is less than 1 E13 cm.5. The semiconductor component as claimed in claim 1 , wherein the crystal defects comprise one or a plurality of the following defects:lattice displacements;lattice strains;precipitates of impurity atoms.6. The semiconductor component as claimed in claim 1 , wherein the passivation layer comprises at least one of the following materials:silicon oxide;BPSG;PSG;BSG; andSG (silicate glass).7. The semiconductor component as claimed in claim 1 , further comprising:at least one rectifying junction in the inner zone.8. The semiconductor component as claimed in claim 7 , ...

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Номер записи: 32
05-06-2014 дата публикации

DISLOCATION ENGINEERING USING A SCANNED LASER

Номер: US20140154872A1
Автор: Lai Chung Woh, Liu Xiao Hu, MADAN ANITA, Schwarz Klaus W., SCOTT J. CAMPBELL
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A method for generating patterned strained regions in a semiconductor device is provided. The method includes directing a light-emitting beam locally onto a surface portion of a semiconductor body; and manipulating a plurality of dislocations located proximate to the surface portion of the semiconductor body utilizing the light-emitting beam, the light-emitting beam being characterized as having a scan speed, so as to produce the patterned strained regions. 1. A method for manipulating dislocations from a semiconductor device , comprising:directing a light-emitting beam locally onto a surface portion of a semiconductor body that includes active regions of the semiconductor device; andmanipulating a plurality of dislocations located proximate to the surface portion of the semiconductor body utilizing the light-emitting beam,wherein manipulating the plurality of dislocations comprises directly scanning the plurality of dislocations with the light-emitting beam to manipulate a location of each of the plurality of dislocations on the surface portion of the semiconductor body by adjusting a temperature of the surface portion of the semiconductor body corresponding to the plurality of dislocations and adjusting a scan speed of the laser beam.2. The method of claim 1 , wherein manipulating the plurality of dislocations further comprises heating the plurality of dislocations with the laser beam such that the plurality of dislocations are driven away from the surface portion of the semiconductor body into the substrate. This is a divisional application of application Ser. No. 13/372,713, filed Feb. 14, 2012 which is a divisional application of application Ser. No. 12/242,990, filed Oct. 1, 2008 and assigned U.S. Pat. No. 8,138,066, dated Mar. 20, 2012.This invention relates to a system and method for manipulating dislocations in semiconductor devices using a scanned laser.Currently, 65 nanometer (nm) technology and beyond makes extensive use of strain engineering to optimize ...

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Номер записи: 33
05-06-2014 дата публикации

DISLOCATION ENGINEERING USING A SCANNED LASER

Номер: US20140154873A1
Автор: Lai Chung Woh, Liu Xiao Hu, MADAN ANITA, Schwarz Klaus W., SCOTT J. CAMPBELL
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A system for manipulating dislocations on semiconductor devices, includes a moveable laser configured to generate a laser beam locally on a surface portion of the semiconductor body having a plurality of dislocations, the moveable laser being characterized as having a scan speed, the moveable laser manipulates the plurality of dislocations on the surface portion of the semiconductor body by adjusting the temperature and the scan speed of the laser beam. 1. A method for manipulating dislocations from a semiconductor device , comprising:directing a light-emitting beam locally onto a surface portion of a semiconductor body that includes active regions of the semiconductor device; andmanipulating a plurality of dislocations located proximate to the surface portion of the semiconductor body utilizing the light-emitting beam;wherein manipulating the plurality of dislocations comprises directly scanning the plurality of dislocations with the light-emitting beam to manipulate a size of the plurality of dislocations on the surface portion of the semiconductor body by adjusting a temperature of the surface portion of the semiconductor body corresponding to the plurality of dislocations and adjusting a scan speed of the laser beam.2. The method of claim 1 , wherein manipulating the plurality of dislocations further comprises scanning across the plurality of dislocations with the laser beam such that the plurality of dislocations grow over the length of a scan of the laser beam enabling the removal of threading dislocations from a relaxed strained layer on the semiconductor device. This is a divisional application of Ser. No. 13/565,018, filed Aug. 2, 2012, which is a divisional of application Ser. No. 13/372,713, filed Feb. 14, 2012, which is a divisional application of application Ser. No. 12/242,990, filed Oct. 1, 2008.This invention relates to a system and method for manipulating dislocations in semiconductor devices using a scanned laser.Currently, 65 nanometer (nm) ...

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Номер записи: 34
16-03-2017 дата публикации

EPITAXIAL SILICON WAFER AND METHOD FOR PRODUCING THE EPITAXIAL SILICON WAFER

Номер: US20170076959A1
Автор: FUJISE Jun, Ono Toshiaki
Принадлежит: SUMCO CORPORATION

A method for producing an epitaxial silicon wafer, including a preliminary thermal treatment step of subjecting a silicon wafer to thermal treatment for increasing a density of oxygen precipitates, the silicon wafer being one that has an oxygen concentration in a range of 9×10atoms/cmto 16×10atoms/cm, contains no dislocation cluster and no COP, and contains an oxygen precipitation suppression region, and an epitaxial layer forming step of forming an epitaxial layer on a surface of the silicon wafer after the preliminary thermal treatment step. The production method further includes a thermal treatment condition determining step of determining a thermal treatment condition in the preliminary thermal treatment step, based on a ratio of the oxygen precipitation suppression region of the silicon wafer before the preliminary thermal treatment step is carried out. 1. An epitaxial silicon wafer having an epitaxial layer on a surface of a silicon wafer that contains no dislocation cluster and no COP ,{'sup': 4', '2, 'wherein when an oxygen precipitate density is evaluated by subjecting the epitaxial silicon water to oxygen precipitate evaluation thermal treatment in which the epitaxial silicon wafer is thermally treated at 1000° C. for 16 hours, a density of oxygen precipitates in a central portion in a thickness direction of the silicon wafer is 5×10/cmor more throughout an entire region in a radial direction of the silicon wafer.'}2. A method for producing an epitaxial silicon water , comprising:{'sup': 17', '3', '17', '3, 'a preliminary thermal treatment step of subjecting a silicon wafer to thermal treatment for increasing a density of oxygen precipitates, the silicon wafer being one that has an oxygen concentration in a range of 9×10atoms/cmto 16×10atoms/cm, contains no dislocation cluster and no COP, and contains an oxygen precipitation suppression region; and'}an epitaxial layer forming step of forming an epitaxial layer on a surface of the silicon wafer after the ...

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Номер записи: 35
16-03-2017 дата публикации

METHOD OF PRODUCING SEMICONDUCTOR EPITAXIAL WAFER, SEMICONDUCTOR EPITAXIAL WAFER, AND METHOD OF PRODUCING SOLID-STATE IMAGE SENSING DEVICE

Номер: US20170077171A1
Автор: Kadono Takeshi, Kurita Kazunari
Принадлежит: SUMCO CORPORATION

The present invention provides a method of more efficiently producing a semiconductor epitaxial wafer, which can suppress metal contamination by achieving higher gettering capability. 1. A method of producing a semiconductor epitaxial wafer , comprising:a first step of irradiating a semiconductor wafer with cluster ions to form a modifying layer formed from a constituent element of the cluster ions contained as a solid solution in a surface portion of the semiconductor wafer, the semiconductor wafer being composed of semiconductor material; anda second step of forming an epitaxial layer on the modifying layer of the semiconductor wafer, to obtain a semiconductor epitaxial wafer having the half width of a concentration profile of the constituent element in the depth direction of the modifying layer is 100 nm or less.2. The method of producing a semiconductor epitaxial wafer according to claim 1 , wherein the semiconductor wafer is a silicon wafer.3. The method of producing a semiconductor epitaxial wafer according to claim 1 , wherein the semiconductor wafer is an epitaxial silicon wafer in which a silicon epitaxial layer is formed on a surface of a silicon wafer claim 1 , and the modifying layer is formed in a surface portion of the silicon epitaxial layer in the first step.4. The method of producing a semiconductor epitaxial wafer claim 1 , according to claim 1 , wherein after the first step claim 1 , the semiconductor wafer is transferred into an epitaxial growth apparatus to be subjected to the second step without heat treating the semiconductor wafer for recovering the crystallinity.5. The method of producing a semiconductor epitaxial wafer according to claim 1 , wherein the cluster ions contain carbon as a constituent element.6. The method of producing a semiconductor epitaxial wafer according to claim 5 , wherein the cluster ions contain at least two kinds of elements including carbon as constituent elements.7. The method of producing a semiconductor epitaxial ...

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Номер записи: 36
05-03-2020 дата публикации

APPARATUS AND PROCESS FOR ELECTRON BEAM MEDIATED PLASMA ETCH AND DEPOSITION PROCESSES

Номер: US20200075346A1
Автор: RANJAN ALOK, Ventzek Peter
Принадлежит:

Disclosed embodiments apply electron beams to substrates for microelectronic workpieces to improve plasma etch and deposition processes. The electron beams are generated and directed to substrate surfaces using DC (direct current) biasing, RF (radio frequency) plasma sources, and/or other electron beam generation and control techniques. For certain embodiments, DC-biased RF plasma sources, such as DC superposition (DCS) or hybrid DC-RF sources, are used to provide controllable electron beams on surfaces opposite a DC-biased electrode. For certain further embodiments, the DC-biased electrode is pulsed. Further, electron beams can also be generated through electron beam extraction from external and/or non-ambipolar sources. The disclosed techniques can also be used with additional electron beam sources and/or additional etch or deposition processes. 1. A method of processing a microelectronic workpiece , comprising:generating an electron beam;delivering the electron beam to a substrate for a microelectronic workpiece within a processing chamber; andperforming at least one of a plasma etch process or a plasma deposition process with respect to the surface of the microelectronic workpiece.2. The method of claim 1 , wherein the delivering comprises delivering the electron beam to one or more selected regions of the substrate to cause electron stimulated chemistry to be induced for the one or more selected regions.3. The method of claim 2 , further comprising using one or more masks to determine the one or more selected regions of the substrate.4. The method of claim 2 , wherein the electron stimulated chemistry promotes or inhibits at least one of an etch process claim 2 , a deposition process claim 2 , or a passivation process.5. The method of claim 1 , wherein the delivering comprises applying direct current (DC) biasing for at least one of the generating or the delivering.6. The method of claim 1 , further comprising applying a radio frequency (RF) bias to the ...

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Номер записи: 37
12-03-2020 дата публикации

Integrated Structures and Methods of Forming Integrated Structures

Номер: US20200083238A1
Автор: Hu Yongjun Jeff, McTeer Allen
Принадлежит: MICRON TECHNOLOGY, INC.

Some embodiments include an integrated structure having semiconductor material within a region between two parallel surfaces. The semiconductor material has grain boundaries parallel to the parallel surfaces. At least one circuit component utilizes a region of the semiconductor material in a gated device. The semiconductor material has little if any metal therein so that the gated device has Ion/Ioff characteristics similar to if the semiconductor material had no metal therein. Some embodiments include a method in which semiconductor material is provided between a pair of parallel surfaces, and in which the parallel surfaces and semiconductor material extend between a first end and a second end. Metal is formed adjacent the first end, and gettering material is formed adjacent the second end. Thermal processing induces crystallization of the semiconductor material and drives the metal along the semiconductor material and into the gettering material. The gettering material is then removed. 135-. (canceled)36: An integrated structure comprising:semiconductor material extending through dielectric material, the semiconductor material comprising a first end spaced from a second end;a metal over the first end of the semiconductor material; anda gettering material over the second end of the semiconductor material.371: The integrated structure of claim wherein the dielectric material comprises interior surfaces on opposing sides of the semiconductor material , the interior surfaces being in a parallel relationship to each other , the semiconductor material having grain boundaries parallel to the parallel interior surfaces.381: The integrated structure of claim further comprising at least one circuit component utilizing a region of the semiconductor material in a gated device.391: The integrated structure of claim wherein the semiconductor material comprises a channel structure and the dielectric material comprises a portion of a gated device.403: The integrated structure of ...

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Номер записи: 38
31-03-2016 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM

Номер: US20160093508A1
Автор: Ogawa Arito
Принадлежит: HITACHI KOKUSAI ELECTRIC INC.

The present invention provides a technology that includes: forming an intermediate film on a substrate having an insulating film formed thereon; and forming a metal film on the intermediate film. The intermediate film is more susceptible to oxidation than the metal film and has a smaller thickness than the metal film. 1. A method of manufacturing a semiconductor device comprising:forming an intermediate film on a substrate having an insulating film formed thereon; andforming a first metal film on the intermediate film,the intermediate film being more susceptible to oxidation than the first metal film, the intermediate film having a smaller thickness than the first metal film.2. The method according to claim 1 , whereinthe intermediate film is a second metal film made of a material different from the first metal film.3. The method according to claim 1 , whereinthe intermediate film is more susceptible to oxidation than the substrate.4. The method according to claim 1 , whereinthe intermediate film getters oxygen.5. The method according to claim 4 , whereinthe intermediate film getters oxygen diffusing from an interior of the insulating film.6. The method according to claim 4 , whereinthe intermediate film getters externally incoming oxygen that has passed through the first metal film.7. The method according to claim 4 , whereinthe intermediate film getters the oxygen, and at least a part of the intermediate film is changed into an insulating film.8. The method according to claim 7 , whereinthe intermediate film getters the oxygen, and a part of the intermediate film excluding the part changed into the insulating film is left unchanged.9. The method according to claim 4 , whereinthe intermediate film getters the oxygen, and the entire intermediate film is changed into an insulating film.10. The method according to claim 1 , whereina thickness of the intermediate film is set based on an amount of metal content included in the intermediate film, the amount of metal ...

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Номер записи: 39
14-04-2016 дата публикации

Method for Manufacturing a Semiconductor Wafer, and Semiconductor Device Having a Low Concentration of Interstitial Oxygen

Номер: US20160104622A1
Автор: CASPARY Nico, Momeni Mohammad, Oefner Helmut, Ploss Reinhard, Santos Rodriguez Francisco Javier, Schulze Hans-Joachim
Принадлежит: INFINEON TECHNOLOGIES AG

A method for manufacturing a substrate wafer includes providing a device wafer () having a first side () and a second side (); subjecting the device wafer () to a first high temperature process for reducing the oxygen content of the device wafer () at least in a region () at the second side (); bonding the second side () of the device wafer () to a first side () of a carrier wafer () to form a substrate wafer (); processing the first side () of the substrate wafer () to reduce the thickness of the device wafer (); subjecting the substrate wafer () to a second high temperature process for reducing the oxygen content at least of the device wafer (); and at least partially integrating at least one semiconductor component () into the device wafer () after the second high temperature process. 1. A method for manufacturing a substrate wafer , the method comprising:providing a device wafer having a first side and a second side opposite the first side, the device wafer being made of a semiconductor material and having a first thickness;subjecting the device wafer to a first high temperature process for reducing the oxygen content of the device wafer at least in a region at the second side;bonding the second side of the device wafer to a first side of a carrier wafer to form a substrate wafer comprising the device wafer bonded to the carrier wafer, the carrier wafer having a second side opposite the first side which second side of the carrier wafer forms the second side of the substrate wafer, wherein the first side of the device wafer forms a first side of the substrate wafer;processing the first side of the substrate wafer, which is formed by the first side of the device wafer, to reduce the thickness of the device wafer to a second thickness less than the first thickness of the device wafer;subjecting the substrate wafer to a second high temperature process for reducing the oxygen content at least of the device wafer bonded to the carrier wafer;at least partially ...

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Номер записи: 40
26-03-2020 дата публикации

Bonding method for semiconductor substrate, and bonded semiconductor substrate

Номер: US20200098703A1
Автор: Hongtao Xu, MENG CHEN, Nan GAO, Xin Su, XING Wei
Принадлежит: Shanghai Simgui Technology Co Ltd

The present disclosure provides a bonding method for a semiconductor substrate, which may improve flatness of a bonded substrate. The present disclosure further provides a bonded semiconductor substrate. The semiconductor substrate is thermally treated prior to bonding, and oxygen precipitates in the semiconductor substrate are partially or totally converted to interstitial oxygen atoms in the thermal treatment.

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Номер записи: 41
03-07-2014 дата публикации

METHOD OF HEALING DEFECT AT JUNCTION OF SEMICONDUCTOR DEVICE USING GERMANIUM

Номер: US20140187021A1
Автор: Heo Jong Gon, Jun Dong Hwan, PARK Jin Hong, Park Won Kyu, Shim Jae Woo
Принадлежит: Korea Advanced Nano Fab Center

This invention relates to a method of healing defects at junctions of a semiconductor device, which includes growing a p-Ge layer on a substrate, performing ion implantation on the p-Ge layer to form an n+ Ge region or performing in-situ doping on the p-Ge layer and then etching to form an n+ Ge region or depositing an oxide film on the p-Ge layer and performing patterning, etching and in-situ doping to form an n+ Ge layer, forming a capping oxide film, performing annealing at 600˜700° C. for 1˜3 hr, and depositing an electrode, and in which annealing enables Ge defects at n+/p junctions to be healed and the depth of junctions to be comparatively reduced, thus minimizing leakage current, thereby improving properties of the semiconductor device and achieving high integration and fineness of the semiconductor device. 1. A method of healing a defect at a junction of a semiconductor device using germanium (Ge) , comprising:1) growing a p-Ge layer on a substrate;2) depositing an oxide film on the p-Ge layer, and patterning the oxide film, thus forming a pattern for an n+ Ge region;3) subjecting the pattern for an n+ Ge region to ion implantation using a n-type dopant, thus forming an n+ Ge region;4) forming a capping oxide film on the p-Ge layer;5) performing annealing at 600˜700° C. for 1˜3 hr; and6) subjecting the capping oxide film to patterning for forming an electrode, depositing the electrode, and performing annealing.2. The method of claim 1 , wherein the p-Ge layer in 1) is formed by growing Ge to a thickness of 300˜500 nm on a silicon (Si) substrate at 350˜450° C. and 7.5˜8.5 Pa claim 1 , performing annealing at 800˜850° C. for 20 min˜1 hr in an Hatmosphere claim 1 , repeating the preceding once more claim 1 , additionally growing a Ge layer at 550˜650° C. and 7.5˜8.5 Pa claim 1 , and performing annealing at 700˜800° C. for 10˜20 min in an Hatmosphere.3. The method of claim 1 , wherein the electrode in 6) comprises any one selected from among Ti claim 1 , Ni ...

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Номер записи: 42
21-04-2016 дата публикации

Avalanche Diode Having an Enhanced Defect Concentration Level and Method of Making the Same

Номер: US20160111413A1
Автор: Esmark Kai, Schneider Jens, Wendel Martin
Принадлежит:

The invention relates to an avalanche diode that can be employed as an ESD protection device. An avalanche ignition region is formed at the p-n junction of the diode and includes an enhanced defect concentration level to provide rapid onset of avalanche current. The avalanche ignition region is preferably formed wider than the diode depletion zone, and is preferably created by placement, preferably by ion implantation, of an atomic specie different from that of the principal device structure. The doping concentration of the placed atomic specie should be sufficiently high to ensure substantially immediate onset of avalanche current when the diode breakdown voltage is exceeded. The new atomic specie preferably comprises argon or nitrogen, but other atomic species can be employed. However, other means of increasing a defect concentration level in the diode depletion zone, such as an altered annealing program, are also contemplated. 1. A method of forming an avalanche diode , the method comprising:forming a first diode region next to a second diode region in a substrate, the second diode region oppositely doped from the first diode region;forming an avalanche ignition region surrounding a junction of the first diode region and the second diode region; andforming a depletion zone surrounding the junction of the first diode region with the second diode region, wherein the depletion zone is wider than the avalanche ignition region.2. The method as claimed in claim 1 , wherein the avalanche ignition region has a defect concentration level greater than a defect concentration level of the first diode region and the second diode region.3. The method as claimed in claim 1 , wherein the depletion zone is created by applying a reverse voltage to the avalanche diode.4. The method as claimed in claim 1 , wherein the avalanche ignition region comprises an atomic species different from an atomic species forming a principle structure of the first diode region and the second diode ...

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Номер записи: 43
20-04-2017 дата публикации

EXTERNAL GETTERING METHOD AND DEVICE

Номер: US20170110381A1
Автор: Pour Cheng P., Tan Michael
Принадлежит:

Disclosed embodiments include external gettering provided by electronic packaging. An external gettering element for a semiconductor substrate, which may be incorporated as part of an electronic packaging for the structure, is disclosed. Semiconductor structures and stacked semiconductor structures including an external gettering element are also disclosed. An encapsulation mold compound providing external gettering is also disclosed. Methods of fabricating such devices are also disclosed. 1. A semiconductor wafer comprising:a substrate having a device section for forming semiconductor devices and a backside section; andan external gettering element arranged adjacent said backside section of said substrate, said external gettering element comprising a gettering material for forming a denude zone at said device section.2. The semiconductor wafer of claim 1 , said external gettering element further comprising an adhesive material claim 1 , wherein said gettering material is integrated with said adhesive material.3. The semiconductor wafer of claim 2 , wherein said adhesive material is a die attach film.4. The semiconductor wafer of claim 1 , further comprising an adhesive material configured to adhere said gettering material to said backside section of said substrate.5. The semiconductor wafer of claim 1 , wherein said gettering material is imbued with particular polarities or quantities of ions in order to attract ions or contaminants within said substrate toward said backside section.6. A stacked semiconductor structure including a plurality of wafers claim 1 , said structure comprising:a first substrate having a first device section designated for forming semiconductor devices and a first backside section;a second substrate having a second device section designated for forming semiconductor devices and a second backside section; andan external gettering element arranged adjacent to at least one of said first backside section of said first substrate and said second ...

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Номер записи: 44
10-07-2014 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20140193964A1
Автор: LIU Po-Tsun, Teng Li-Feng, Wang Wei-Ya
Принадлежит: NATIONAL CHIAO TUNG UNIVERSITY

The present invention provides a method of manufacturing a semiconductor device. The method at least comprises the following steps. First, the semiconductor device, which comprises a gate, a gate dielectric layer, an active layer, a source and a drain, is manufactured. However, the semiconductor device has a plurality of defects, and the active layer is a metal oxide thin film. After annealing the semiconductor device, it will be transferred into a chamber. A final step of injecting a supercritical fluid carried with a co-solvent into the chamber is then performed to modify the abovementioned defects. 1. A method of manufacturing semiconductor device by a supercritical fluid carried with a co-solvent to modify the defects of semiconductor device , comprising:forming a gate dielectric layer on a gate by conducting a first hydrogen plasma treatment;forming an active layer on the gate dielectric layer by conducting a second hydrogen plasma treatment; anddisposing a source and a drain on the active layer, wherein the semiconductor device having a plurality of defects, and the active layer being a metal oxide thin film;annealing the semiconductor device, wherein the temperature for annealing the semiconductor device is between 350° C. and 450° C.;transferring the semiconductor device into a chamber at 100° C. to 200° C. and 1500 psi to 3000 psi; andinjecting a supercritical fluid carried with a co-solvent into the chamber to modify the plurality of defects.210-. (canceled)11. The method according to claim 1 , wherein the supercritical fluid is selected from the group consisting of carbon dioxide claim 1 , oxygen claim 1 , ammonia claim 1 , nitrogen claim 1 , hydrogen and water vapor. 1. Field of the InventionThe present invention relates to a method of manufacturing a semiconductor device, particularly to a method of manufacturing a semiconductor device by a supercritical fluid carried with a co-solvent to modify the defects of semiconductor device.2. Description of the ...

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Номер записи: 45
30-04-2015 дата публикации

CZOCHRALSKI SUBSTRATES HAVING REDUCED OXYGEN DONORS

Номер: US20150118861A1
Автор: BALSTER SCOTT GERARD, HOWER Philip Leland, LIN John, MATHUR Guru, PARK SEUNG-SA, SUCHER Bradley David, Wise Rick L., Zhang Yongxi
Принадлежит:

A method of semiconductor fabrication includes providing an unpatterned lightly doped Czochralski bulk silicon substrate (LDCBS substrate) having a concentration of oxygen atoms of at least (≧) 10atoms/cmwith a boron doping or n-type doping concentration of between 1×10cmand 5×10cm. Before any oxidization processing, the LDCBS substrate is annealed at a nucleating temperature between 550° C. and 760° C. for a nucleating time that nucleates the oxygen atoms in a sub-surface region of the LDCBS substrate to form oxygen precipitates therefrom. After the annealing, a surface of the LDCBS substrate or an epitaxial layer on the surface of the LDCBS substrate is initially oxidized in an oxidizing ambient at a peak temperature of between 800° C. and 925° C. for a time less than or equal (≦) to 30 minutes. 1. A method of semiconductor fabrication , comprising:{'sup': 17', '3', '12', '−3', '14', '−3, 'providing an unpatterned lightly doped Czochralski bulk silicon substrate (LDCBS substrate) having a concentration of oxygen atoms of at least (≧) 10atoms/cmwith a boron doping or n-type doping concentration of between 1×10cmand 5×10cm;'}before any oxidization processing, annealing said LDCBS substrate at a nucleating temperature between 550° C. and 760° C. for a nucleating time that nucleates said oxygen atoms in a sub-surface region of said LDCBS substrate to form oxygen precipitates therefrom, andafter said annealing, initially oxidizing a surface of said LDCBS substrate or an epitaxial layer on said surface of said LDCBS substrate in an oxidizing ambient at a peak temperature of between 800° C. and 925° C. for a time less than or equal (≦) to 30 minutes.2. The method of claim 1 , wherein said nucleating time is 1 to 3 hours.3. The method of claim 1 , wherein said nucleating temperature is between 575° C. and 690° C.4. The method of claim 1 , wherein said oxidizing ambient comprises steam.5. The method of claim 1 , wherein said annealing and said initially oxidizing are both ...

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Номер записи: 46
02-04-2020 дата публикации

Methods For Film Modification

Номер: US20200105541A1
Автор: Bhargav S. CITLA, Chentsau Chris Ying, Erica Chen, Jethro Tannos, Matthew August Mattson
Принадлежит: Applied Materials Inc

A method of converting films is disclosed. A method of modifying films is also disclosed. Some methods advantageously convert films from a first elemental composition to a second elemental composition. Some methods advantageously modify film properties without modifying film composition.

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Номер записи: 47
11-05-2017 дата публикации

Methods and systems to improve yield in multiple chips integration processes

Номер: US20170133358A1
Автор: Chang Runzi, Lee Winston
Принадлежит:

The present disclosure includes systems and techniques relating to methods and systems that improve yield in multiple chips integration processes. In some implementations, a method includes providing, in a chamber, a first integrated circuit chip and a second integrated circuit chip supported on a carrier, flowing a molding compound to cover the first integrated circuit chip, the second integrated circuit chip, and the carrier; and flowing a forming gas into the chamber while curing the molding compound. 1. A method for minimizing yield losses in multiple chip integration , the method comprising:providing, in a chamber, a first integrated circuit chip and a second integrated circuit chip supported on a carrier;flowing a molding compound to cover the first integrated circuit chip, the second integrated circuit chip, and the carrier; andflowing a forming gas into the chamber while curing the molding compound.2. The method of claim 1 , wherein the forming gas comprises Hand N.3. The method of claim 1 , further comprising controlling a pressure of the forming gas in the chamber to increase permeation of the forming gas into a gate oxide and a silicon surface of the first integrated circuit chip.4. The method of claim 1 , further comprising controlling a temperature of the forming gas to increase permeation of the forming gas into the gate oxide and the silicon surface of the first integrated circuit chip.5. The method of claim 1 , wherein flowing the forming gas into the chamber comprises introducing the forming gas through a plurality of nozzles defined in a top cover of the chamber.6. The method of claim 5 , wherein the plurality of nozzles is arranged concentrically about a central nozzle.7. The method of claim 5 , further comprising adjusting a distance between the plurality of nozzles and the first integrated circuit chip claim 5 , and a mole fraction ratio of Hand N.8. The method of claim 1 , wherein curing the molding compound occurs at a temperature between 180° ...

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Номер записи: 48
28-05-2015 дата публикации

THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE FABRICATION INCLUDING WAFER SCALE MEMBRANE

Номер: US20150147869A1
Автор: JR. Douglas C., La Tulipe, Purushothaman Sampath, Vichiconti James
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Method and Apparatus so configured for the fabrication of three-dimensional integrated devices. A crystalline substrate within an area of a donor semiconductor wafer is etched. The substrate side is located opposite a device layer and has a buried insulating layer and a substrate thickness. The etching removes at least a substantial portion of the crystalline substrate within the area such that the device layer and the buried insulating layer in the area is to conform to a pattern specific topology on an acceptor surface. The donor semiconductor wafer is supported with a supporting structure that allows the donor semiconductor wafer to flexibly conform to the pattern specific topology within at least a portion of the area after the etching to enable conformality and reliable bonding to the device surfaces of an acceptor wafer to form a three dimensional integrated device. 1. A method for fabricating three-dimensional integrated circuits , the method comprising:etching crystalline substrate within an area of a substrate side of a donor semiconductor wafer, the substrate side having a substrate thickness and being located opposite a donor wafer membrane comprising a device layer of the donor semiconductor wafer and a buried insulating layer, to remove at least a substantial portion of the crystalline substrate within the area such that the device layer and the buried insulating layer of the donor wafer membrane in the area is configured to conform to a pattern specific topology on an acceptor surface; andsupporting the donor semiconductor wafer with a supporting structure, the supporting structure allowing the donor semiconductor wafer to flexibly conform to the pattern specific topology within at least a portion of the area after the etching.2. The method of claim 1 , wherein the area comprises substantially an entire side of the substrate side claim 1 , and wherein the supporting structure comprises a separate supporting structure attached to the donor semiconductor ...

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Номер записи: 49
18-05-2017 дата публикации

Integrated Structures and Methods of Forming Integrated Structures

Номер: US20170141119A1
Автор: Hu Yongjun Jeff, McTeer Allen
Принадлежит:

Some embodiments include an integrated structure having semiconductor material within a region between two parallel surfaces. The semiconductor material has grain boundaries parallel to the parallel surfaces. At least one circuit component utilizes a region of the semiconductor material in a gated device. The semiconductor material has little if any metal therein so that the gated device has Ion/Ioff characteristics similar to if the semiconductor material had no metal therein. Some embodiments include a method in which semiconductor material is provided between a pair of parallel surfaces, and in which the parallel surfaces and semiconductor material extend between a first end and a second end. Metal is formed adjacent the first end, and gettering material is formed adjacent the second end. Thermal processing induces crystallization of the semiconductor material and drives the metal along the semiconductor material and into the gettering material. The gettering material is then removed. 1. An integrated structure comprising semiconductor material within a region between two parallel surfaces , the semiconductor material having grain boundaries parallel to the parallel surfaces; at least one circuit component utilizing a region of the semiconductor material in a gated device; the semiconductor material having little if any metal therein so that the gated device has Ion/Ioff characteristics within a same order of magnitude as would occur if the semiconductor material had no metal therein.2. The integrated structure of having a NAND string with the parallel surfaces being on opposing sides of a channel region; the gated device being one of a plurality of gated devices corresponding to memory cells of the NAND string claim 1 , and a metal concentration being low or non-existent throughout an entirety of the channel region so that all of the memory cells of the NAND string have said Ion/Ioff characteristics.3. The integrated structure of having a U-shaped NAND string ...

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Номер записи: 50
14-08-2014 дата публикации

SEMICONDUCTOR MANUFACTURING APPARATUS AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Номер: US20140227807A1
Автор: Matsunaga Kentaro, NAKAJIMA Yumi, Yoneda Eiji
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A semiconductor manufacturing apparatus according to the present embodiment includes a vacuum chamber. A stage mounts a semiconductor substrate thereon within the vacuum chamber. An electrostatic chuck fixes the semiconductor substrate onto the stage. A sensor detects a height of a surface of the semiconductor substrate fixed onto the stage by the electrostatic chuck. A processor determines whether the surface of the semiconductor substrate is distorted based on the height of the surface of the semiconductor substrate. The processor calculates correction values for a pattern transferred onto the surface of the semiconductor substrate by exposure based on the height of the surface of the semiconductor substrate when the surface of the semiconductor substrate is distorted. An exposure part exposes the surface of the semiconductor substrate to light using the correction values. 1. A semiconductor manufacturing apparatus comprising:a vacuum chamber;a stage mounting a semiconductor substrate thereon within the vacuum chamber;an electrostatic chuck fixing the semiconductor substrate onto the stage;a sensor detecting a height of a surface of the semiconductor substrate fixed onto the stage by the electrostatic chuck;a processor determining whether the surface of the semiconductor substrate is distorted based on the height of the surface of the semiconductor substrate, and calculating correction values for a pattern transferred onto the surface of the semiconductor substrate by exposure based on the height of the surface of the semiconductor substrate when the surface of the semiconductor substrate is distorted; andan exposure part exposing the surface of the semiconductor substrate to light using the correction values.3. The apparatus of claim 1 , whereinthe sensor detects a height of a plurality of grid points on the surface of the semiconductor substrate,the processor calculates the correction values for the pattern transferred onto the surface of the semiconductor ...

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Номер записи: 51
30-04-2020 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE

Номер: US20200135847A1
Автор: KIYOI Akira
Принадлежит: Mitsubishi Electric Corporation

In a step, acceptor ions are implanted from a back surface of a semiconductor substrate. In a step, a wet process of immersing the semiconductor substrate in a chemical solution including hydrofluoric acid is performed, to introduce hydrogen atoms into the semiconductor substrate. In a step, proton radiation is provided to the back surface of the semiconductor substrate, to introduce hydrogen atoms into the semiconductor substrate and form radiation-induced defects. In a step, an annealing process is performed on the semiconductor substrate, to form hydrogen-related donors by reaction of the hydrogen atoms and the radiation-induced defects and reduce the radiation-induced defects. 1. A method of manufacturing a semiconductor device , comprising:forming a semiconductor element in a semiconductor substrate having a first main surface and a second main surface and being of a first conductivity type having a first carrier concentration, the semiconductor element being for conducting a current between the first main surface and the second main surface, implanting acceptor ions from the second main surface of the semiconductor substrate,', 'performing, from the second main surface of the semiconductor substrate, a wet process of accumulating hydrogen atoms in a region of the semiconductor substrate where the acceptor ions are implanted,', 'providing radiation of charged particles from the second main surface of the semiconductor substrate, and', 'after the performing a wet process and the providing radiation of charged particles, performing an annealing process on the semiconductor substrate, to form a field stop layer of the first conductivity type having a second carrier concentration higher than the first carrier concentration in the semiconductor substrate., 'the forming a semiconductor element including'}2. The method of manufacturing a semiconductor device according to claim 1 , whereinin the implanting acceptor ions, ions of a Group 13 element are implanted as the ...

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Номер записи: 52
22-09-2022 дата публикации

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THEREOF

Номер: US20220301885A1
Автор: CHEN I-Sheng, LI SIAO-JING, Li Yi-Jing
Принадлежит:

A semiconductor structure and a method for forming a semiconductor structure are provided. A sacrificial gate layer is removed to form a gate trench exposing a sacrificial dielectric layer. An ion implantation is performed to a portion of a substrate covered by the sacrificial dielectric layer in the gate trench. The sacrificial dielectric layer is removed to expose the substrate from the gate trench. An interfacial layer is formed over the substrate in the gate trench. A metal gate structure is formed over the interfacial layer in the gate trench. 1. A method , comprising:receiving a substrate comprising a sacrificial gate structure disposed thereon, wherein the sacrificial gate structure comprises a sacrificial gate layer and a sacrificial dielectric layer;removing the sacrificial gate layer to form a gate trench exposing the sacrificial dielectric layer;performing an ion implantation to a portion of the substrate covered by the sacrificial dielectric layer in the gate trench;removing the sacrificial dielectric layer to expose the substrate from the gate trench;forming an interfacial layer over the substrate in the gate trench; andforming a metal gate structure over the interfacial layer in the gate trench.2. The method of claim 1 , wherein the ion implantation includes a fluorination treatment process.3. The method of claim 2 , wherein a gas source of the fluorination treatment process includes boron fluoride (BF) and silicon fluoride (SiF).4. The method of claim 3 , wherein a dose range of the boron fluoride (BF) ranges from approximately 5×10(ions/cm) to approximately 5×10(ions/cm).5. The method of claim 3 , wherein a dose range of the silicon fluoride (SiF) ranges from approximately 1×10(ions/cm) to approximately 2×10(ions/cm).6. The method of claim 1 , wherein an energy of the ion implantation ranges from approximately 0.1 keV to approximately 2 keV.7. The method of claim 1 , wherein the removing of the sacrificial dielectric layer from the substrate forms a ...

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Номер записи: 53
11-09-2014 дата публикации

Method and equipment for removing photoresist residue after dry etch

Номер: US20140256138A1
Автор: Chia-I Shen, Han-Ti Hsiaw, Mu-Chen Chen, Wei-Fan LIAO, Yi-Tse Huang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method for removing photoresist residue includes etching a photoresist layer disposed over a front side of a semiconductor substrate during fabrication of a semiconductor device, and exposing at least one of the front side and the back side of the semiconductor substrate to an atmosphere comprising active oxygen. The method further includes cleaning at least one of the front side and the back side of the semiconductor substrate with a cleaning fluid.

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Номер записи: 54
18-09-2014 дата публикации

METAL STRUCTURES AND METHODS OF USING SAME FOR TRANSPORTING OR GETTERING MATERIALS DISPOSED WITHIN SEMICONDUCTOR SUBSTRATES

Номер: US20140264757A1
Автор: Presser Nathan, TAYLOR David P.
Принадлежит: The Aerospace Corporation

Embodiments of the present invention provide metal structures for transporting or gettering materials disposed on or within a semiconductor substrate. A structure for transporting a material disposed on or within a semiconductor substrate may include a metal structure disposed within the semiconductor substrate and at a spaced distance from the material. The metal structure is configured to transport the material through the semiconductor substrate and to concentrate the material at the metal structure. The material may include a contaminant disposed within the semiconductor substrate, e.g., that originates from electronic circuitry on the substrate. 1. A structure for transporting a material disposed on or within a semiconductor substrate , the structure comprising:a metal structure disposed within the semiconductor substrate and at a spaced distance from the material,the metal structure being configured to transport the material thereto through the semiconductor substrate and to concentrate the material at the metal structure.2. The structure of claim 1 , wherein the material comprises a contaminant disposed within the semiconductor substrate.3. The structure of claim 2 , further comprising electronic circuitry disposed on the semiconductor substrate claim 2 , the contaminant comprising a second metal originating from the electronic circuitry.4. The structure of claim 3 , wherein the semiconductor substrate comprises silicon claim 3 , the metal structure comprises platinum claim 3 , and the second metal is H claim 3 , Al claim 3 , Ca claim 3 , Cu claim 3 , Fe claim 3 , or Na.5. The structure of claim 3 , wherein the contaminant diffuses through the semiconductor substrate and interferes with operation of the electronic circuitry in the absence of the metal structure.6. The structure of claim 1 , wherein the metal structure comprises Al claim 1 , Au claim 1 , Ag claim 1 , Ca claim 1 , Cu claim 1 , K claim 1 , Li claim 1 , Mn claim 1 , Na claim 1 , Pt claim 1 , or ...

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Номер записи: 55
23-06-2016 дата публикации

METHOD OF PRODUCING SEMICONDUCTOR EPITAXIAL WAFER, SEMICONDUCTOR EPITAXIAL WAFER, AND METHOD OF PRODUCING SOLID-STATE IMAGE SENSING DEVICE

Номер: US20160181311A1
Автор: Kadono Takeshi, Kurita Kazunari
Принадлежит: SUMCO CORPORATION

The present invention provides a method of producing a semiconductor epitaxial wafer, which can suppress metal contamination by achieving higher gettering capability. 1. A method of producing a semiconductor epitaxial wafer , comprising:a first step of irradiating a surface portion of a semiconductor wafer with cluster ions thereby forming a modifying layer formed from carbon and a dopant element contained as a solid solution that are constituent elements of the cluster ions, in the surface portion of the semiconductor wafer; anda second step of forming an epitaxial layer on the modifying layer of the semiconductor wafer, the epitaxial layer having a dopant element concentration lower than the peak concentration of the dopant element in the modifying layer.2. The method of producing a semiconductor epitaxial wafer claim 1 , according to claim 1 , wherein the cluster ions are formed by ionizing a compound containing both the carbon and the dopant element.3. The method of producing a semiconductor epitaxial wafer claim 1 , according to claim 1 , wherein the dopant element is one or more elements selected from the group consisting of boron claim 1 , phosphorus claim 1 , arsenic claim 1 , and antimony.4. The method of producing a semiconductor epitaxial wafer claim 1 , according to claim 1 , wherein the semiconductor wafer is a silicon wafer.5. The method of producing a semiconductor epitaxial wafer claim 1 , according to claim 1 , wherein the semiconductor wafer is an epitaxial silicon wafer in which an epitaxial silicon layer is formed on a surface of a silicon wafer claim 1 , and the modifying layer is formed in the surface portion of the epitaxial silicon layer in the first step.6. The method of producing a semiconductor epitaxial wafer claim 1 , according to claim 1 , further comprising claim 1 , after the first step and before the second step claim 1 , a step of performing heat treatment for recovering the crystallinity on the semiconductor wafer.7. A ...

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Номер записи: 56
23-06-2016 дата публикации

METHOD OF PRODUCING SEMICONDUCTOR EPITAXIAL WAFER, SEMICONDUCTOR EPITAXIAL WAFER, AND METHOD OF PRODUCING SOLID-STATE IMAGE SENSING DEVICE

Номер: US20160181312A1
Автор: Kadono Takeshi, Kurita Kazunari
Принадлежит: SUMCO CORPORATION

An object is to provide a method of producing a semiconductor epitaxial wafer having higher gettering capability and a reduced haze level of the surface of a semiconductor epitaxial layer. 1. A method of producing a semiconductor epitaxial wafer , comprising:a first step of irradiating a semiconductor wafer with cluster ions thereby forming a modifying layer formed from a constituent element of the cluster ions contained as a solid solution, in a surface portion of the semiconductor wafer;a second step of performing heat treatment for crystallinity recovery on the semiconductor wafer after the first step such that the haze level of the surface portion of the semiconductor wafer is 0.20 ppm or less; anda third step of forming an epitaxial layer on the modifying layer of the semiconductor wafer after the second step.2. The method of producing a semiconductor epitaxial wafer claim 1 , according to claim 1 , wherein the semiconductor wafer is a silicon wafer.3. The method of producing a semiconductor epitaxial wafer claim 1 , according to claim 1 , wherein the semiconductor wafer is an epitaxial silicon wafer in which a silicon epitaxial layer is formed on a surface of a silicon wafer claim 1 , and the modifying layer is formed in a surface portion of the silicon epitaxial layer in the first step.4. The method of producing a semiconductor epitaxial wafer claim 1 , according to claim 1 , wherein the cluster ions contain carbon as a constituent element.5. The method of producing a semiconductor epitaxial wafer claim 4 , according to claim 4 , wherein the cluster ions contain at least two kinds of elements including carbon as constituent elements.6. The method of producing a semiconductor epitaxial wafer claim 4 , according to claim 4 , wherein the dose of the cluster ions of carbon is 2.0×10atoms/cmor more.7. A semiconductor epitaxial wafer claim 4 , comprising:a semiconductor wafer; a modifying layer formed from a certain element contained as a solid solution in the ...

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Номер записи: 57
23-06-2016 дата публикации

METHOD OF PRODUCING SEMICONDUCTOR EPITAXIAL WAFER, SEMICONDUCTOR EPITAXIAL WAFER, AND METHOD OF PRODUCING SOLID-STATE IMAGE SENSING DEVICE

Номер: US20160181313A1
Автор: Kadono Takeshi, Kurita Kazunari
Принадлежит: SUMCO CORPORATION

Provided is a semiconductor epitaxial wafer having metal contamination reduced by achieving higher gettering capability, a method of producing the semiconductor epitaxial wafer, and a method of producing a solid-state image sensing device using the semiconductor epitaxial wafer. The method of producing a semiconductor epitaxial wafer includes a first step of irradiating a semiconductor wafer containing at least one of carbon and nitrogen with cluster ions thereby forming a modifying layer formed from a constituent element of the cluster ions contained as a solid solution, in a surface portion of the semiconductor wafer ; and a second step of forming a first epitaxial layer on the modifying layer of the semiconductor wafer 1. A method of producing a semiconductor epitaxial wafer , comprising:a first step of irradiating a semiconductor wafer containing at least one of carbon and nitrogen with cluster ions thereby forming a modifying layer formed from a constituent element of the cluster ions contained as a solid solution, in a surface portion of the semiconductor wafer; anda second step of forming a first epitaxial layer on the modifying layer of the semiconductor wafer.2. The method of producing a semiconductor epitaxial wafer claim 1 , according to claim 1 , wherein the semiconductor wafer is a silicon wafer.3. The method of producing a semiconductor epitaxial wafer claim 1 , according to claim 1 , wherein the semiconductor wafer is an epitaxial wafer in which a second epitaxial layer is formed on a surface of a silicon wafer claim 1 , and in the first step claim 1 , the modifying layer is formed on a surface of the second epitaxial layer.4. The method of producing a semiconductor epitaxial wafer claim 1 , according to claim 1 , wherein the carbon concentration of the semiconductor wafer is 1×10atoms/cmor more and 1×10atoms/cmor less (ASTM F123 1981) claim 1 , whereas the nitrogen concentration thereof is 5×10atoms/cmor more and 5×10atoms/cmor less.5. The method of ...

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Номер записи: 58
02-07-2015 дата публикации

Method to improve slip resistance of silicon wafers

Номер: US20150187597A1
Автор: Bradley David Sucher, Rick L. Wise
Принадлежит: Texas Instruments Inc

By controlling the concentration and size of bulk micro defects (BMD) during the manufacture of an integrated circuit slip and associated yield loss due to slip may be eliminated. A process for eliminating slip that is customized to an integrated circuit (IC) manufacturing flow is disclosed. The process is adapted to the oxygen content of the starting material and to the thermal budget of an IC manufacturing flow and generates a sufficient concentration of BMDs of a size that is optimized to getter microcracks thereby eliminating slip. Slip is eliminated in unpatterned wafers and in wafers containing shallow trench isolation and deep trench isolation using a BMD nucleation anneal and a BMD growth anneal.

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Номер записи: 59
28-06-2018 дата публикации

METHOD OF TREATING SILICON WAFERS TO HAVE INTRINSIC GETTERING AND GATE OXIDE INTEGRITY YIELD

Номер: US20180182641A1
Автор: Falster Robert, Hudson Carissima Marie, Ji Jun Hawn, Kim Byung Chun, Kim Tae Hoon, Lee Young Jung, PARK Soon Sung, Ryu Jae-Woo
Принадлежит:

The disclosure is directed to a method to recover the gate oxide integrity yield of a silicon wafer after rapid thermal anneal in an ambient atmosphere comprising a nitrogen containing gas, such as NHor N. Generally, rapid thermal anneals in an ambient atmosphere comprising a nitrogen containing gas, such as NHor Nto thereby imprint an oxygen precipitate profile can degrade the GOI yield of a silicon wafer by exposing as-grown crystal defects (oxygen precipitate) and vacancies generated by the silicon nitride film. The present invention restores GOI yield by stripping the silicon nitride layer, which is followed by wafer oxidation, which is followed by stripping the silicon oxide layer. 1. A method of treating a single crystal silicon wafer , the method comprising:heat treating the single crystal silicon wafer in a first ambient atmosphere comprising a nitrogen-containing gas at a temperature of at least about 1100° C. to increase a density of crystal lattice vacancies in a bulk region of the single crystal silicon wafer and to form a silicon nitride layer on a front surface of the single crystal silicon wafer, wherein the single crystal silicon wafer comprises two major, parallel surfaces, one of which is the front surface and one of which is a back surface, a central plane between the front surface and the back surface, a circumferential edge joining the front surface and the back surface, a front surface layer having a depth, D, measured from the front surface and toward the central plane, and wherein the bulk region is between the front surface layer and the central plane;removing the silicon nitride layer from the front surface of the single crystal silicon wafer;heat treating the single crystal silicon wafer in a second ambient atmosphere comprising oxygen and a temperature between about 900° C. and about 1100° C. for a duration greater than 30 minutes to form a silicon oxide layer on the front surface of the single crystal silicon wafer having a minimum ...

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Номер записи: 60
29-06-2017 дата публикации

METHOD FOR PRODUCING LOW-PERMITTIVITY SPACERS

Номер: US20170186623A1
Автор: Garcia-Barros Maxime, Morand Yves, Posseme Nicolas
Принадлежит:

There is provided a method for manufacturing a transistor from a stack including at least one gate pattern comprising at least one flank, the method including forming at least one gate spacer over at least the flank of the gate pattern; and reducing, after a step of exposure of the stack to a temperature greater than or equal to 600° C., of a dielectric permittivity of the at least one gate spacer, the reducing including at least one ion implantation in a portion at least of a thickness of the at least one gate spacer. 150.-. (canceled)51. A method for manufacturing a transistor using a stack comprising at least one gate pattern comprising at least one flank and being located above an underlying layer made of a semi-conductor material , the method comprising:forming, at least partially, at least one gate spacer by depositing at least one layer made of a non-carbon material on the at least one flank of the at least one gate pattern;after the depositing of the at least one layer made of a non-carbon material, performing at least one step of exposing the stack to a temperature greater than or equal to 600° C.; andafter the at least one step of exposing, performing at least one step of reducing of a dielectric permittivity of the at least one gate spacer, the reducing comprising at least one ion implantation in a portion at least of a thickness of the at least one gate spacer,wherein parameters of the at least one ion implantation including species implanted, energy, and implantation dose, being chosen such that the at least one ion implantation reduces the dielectric permittivity of the at least one gate spacer, andwherein, during the at least one ion implantation, the at least one gate spacer is present only on the at least one gate pattern.52. The method according to claim 51 , further comprising at least one step of forming at least one source/drain zone in a peripheral zone surrounding the at least one gate pattern and located above the underlying layer claim 51 , ...

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Номер записи: 61
06-07-2017 дата публикации

REMOVING PARTICULATE CONTAMINANTS FROM THE BACKSIDE OF A WAFER OR RETICLE

Номер: US20170194134A1
Автор: KIEVIT Olaf, OOSTROM Sjoerd, Papen-Botterhuis Nicole Ellen, Van Der Donck Jacques Cor Johan
Принадлежит: Nederlandse Organisatie voor toegepast-natuurwetenschappelijk Onderzoek TNO

The invention is directed to a method for removing particulate contaminants from the backside of a wafer or reticle, and to a cleaning substrate for use in such method. In the method of the invention particulate contaminants are removed from the backside of a wafer or reticle with a cleaning substrate. The cleaning substrate comprises protrusions and a tacky layer between the protrusions. The method comprises contacting the backside of the wafer or reticle with the protrusions of the cleaning substrate while maintaining a distance between the wafer or reticle and the tacky layer, the distance being in the range of 1-10 μm. 1. Method for removing particulate contaminants from the backside of a wafer or reticle with a cleaning substrate , said cleaning substrate comprising protrusions and a tacky layer between said protrusions , and wherein said method comprises contacting the backside of said wafer or reticle with the protrusions of said cleaning substrate while maintaining a distance between the wafer or reticle and said tacky layer , the distance being in the range of 1-10 μm.2. Method according to claim 1 , wherein said tacky layer comprises one or more materials selected from acrylic or methacrylic adhesive claim 1 , and polyurethane.3. Method according to claim 1 , wherein the tacky layer has a thickness of 5-25 μm.4. Method according to claim 3 , wherein the tacky layer has a thickness of 10-20 μm.5. Method according to claim 1 , wherein said protrusions protrude 5-35 μm from the cleaning substrate base surface.6. Method according to claim 5 , wherein said protrusions protrude 10-30 μm from the cleaning substrate base surface.7. Method according to claim 1 , wherein said contacting comprises holding the wafer or reticle to the cleaning substrate by one or more forces selected from the group consisting of electrostatic claim 1 , vacuum claim 1 , overpressure claim 1 , and capillary force.8. Method according to claim 1 , wherein said wafer is a silicon wafer.9. ...

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Номер записи: 62
11-06-2020 дата публикации

GETTERING LAYER FORMING APPARATUS, GETTERING LAYER FORMING METHOD AND COMPUTER-READABLE RECORDING MEDIUM

Номер: US20200185232A1
Автор: FUKUOKA Tetsuo
Принадлежит:

A gettering layer forming apparatus configured to form a gettering layer on a substrate includes a substrate holder configured to hold the substrate; a wrapping film configured to be brought into contact with the substrate held by the substrate holder and polish the substrate; a base configured to support the wrapping film, and configured to be moved in a vertical direction and rotated around a vertical axis; and a water supply configured to supply water onto the substrate held by the substrate holder. 1. A gettering layer forming apparatus configured to form a gettering layer on a substrate , the gettering layer forming apparatus comprising:a substrate holder configured to hold the substrate;a wrapping film configured to be brought into contact with the substrate held by the substrate holder and polish the substrate;a base configured to support the wrapping film, and configured to be moved in a vertical direction and rotated around a vertical axis; anda water supply configured to supply water onto the substrate held by the substrate holder.2. The gettering layer forming apparatus of claim 1 ,wherein multiple protrusions are formed on a surface of the wrapping film, andthe protrusions are brought into contact with the substrate while gaps are maintained between the protrusions.3. The gettering layer forming apparatus of claim 2 ,wherein each protrusion has a columnar shape.4. The gettering layer forming apparatus of claim 1 ,wherein the wrapping film is brought into contact with an entire surface of the substrate.5. The gettering layer forming apparatus of claim 1 , further comprising:a flexible member, having flexibility, disposed to cover the wrapping film.6. The gettering layer forming apparatus of claim 1 ,wherein multiple protrusions each having a narrowing width toward the substrate holder when viewed from a side are formed on a surface of the wrapping film.7. The gettering layer forming apparatus of claim 6 , further comprising:a driver configured to rotate ...

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Номер записи: 63
02-10-2014 дата публикации

Semiconductor Substrate and a Method of Manufacturing the Same

Номер: US20140291809A1
Автор: Pfirsch Frank, Schulze Hans-Joachim, Timme Hans-Joerg
Принадлежит:

The semiconductor substrate includes a high-ohmic semiconductor material with a conduction band edge and a valence band edge, separated by a bandgap, wherein the semiconductor material includes acceptor or donor impurity atoms or crystal defects, whose energy levels are located at least 120 meV from the conduction band edge, as well as from the valence band edge in the bandgap; and wherein the concentration of the impurity atoms or crystal defects is larger than 1×10cm. 1. A semiconductor substrate comprising a semiconductor material with a conduction band edge and a valence band edge , separated by a bandgap , wherein the semiconductor material comprises a base doping and donor impurity atoms different from the base doping or a base doping and crystal defects , wherein the donor impurity atoms comprise selenium (Se) , a concentration of the donor impurity atoms being larger than 1×10cm , wherein the semiconductor substrate includes an electronic device zone comprising the selenium (Se) atoms , and wherein a region of the semiconductor substrate comprising the selenium (Se) atoms forms at least a portion of a drift or base region of the electronic device.2. The semiconductor substrate according to claim 1 , wherein at least 50% of the substrate volume comprises semiconductor material with the impurity atoms or crystal defects.3. The semiconductor substrate according to claim 1 , wherein the maximum concentration of the impurity atoms or crystal defects is smaller or equal to 1×10cm.4. The semiconductor substrate according to claim 1 , wherein the semiconductor material is manufactured using a Czochralski or Magnetic Czochralski growing technique.5. The semiconductor substrate according to claim 1 , wherein a concentration of interstitial oxygen in the semiconductor substrate is between 1×10cmand 1×10cm claim 1 , and wherein concentration of impurity atoms is between 1×10cmand 1×10cm.6. The semiconductor substrate according to claim 1 , comprising a base doping claim ...

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Номер записи: 64
02-10-2014 дата публикации

PROCESSING A WAFER FOR AN ELECTRONIC CIRCUIT

Номер: US20140291815A1
Автор: Jordan Doug, Mallik Kanad, Wilshaw Peter
Принадлежит: ISIS INNOVATION LIMITED

According to a disclosed embodiment, there is provided a method of processing a silicon wafer for use in a substrate for an electronic circuit, comprising: impregnating the silicon wafer with impurities that form one or more deep energy levels within the band gap of silicon, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level; and pre-processing the silicon wafer, prior to or after said impregnation step, so that precipitation of oxide during, after, or during and after, said impregnating step is suppressed. 1. A method of processing a silicon wafer for use in a substrate for an electronic circuit , comprising:impregnating the silicon wafer with impurities that form one or more deep energy levels within the band gap of silicon, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level; andpre-processing the silicon wafer, prior to or after said impregnation step, so that precipitation of oxide during, after, or during and after, said impregnating step is suppressed.2. A method according to claim 1 , wherein said pre-processing comprises removing the oxide clusters/nuclei to a level that is insufficient to give rise to significant precipitation in subsequent processing steps.3. A method according to claim 2 , wherein said pre-processing comprises a heat treatment that dissolves all or a proportion of oxide clusters/nuclei present before said pre-processing.4. A method according to claim 3 , wherein said heat treatment is followed by a cooling that is sufficiently rapid to prevent significant creation of new oxide clusters/nuclei during the cooling process.5. A method according to claim 4 , wherein said cooling comprises reducing the temperature of ...

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Номер записи: 65
25-06-2020 дата публикации

SEMICONDUCTOR CHIP GETTERING

Номер: US20200203177A1
Автор: Agarwal Rahul, BARBER IVOR, Bhagavat Milind S., CHENG YUEN TING, CHOK GUAN SIN, VALLIAPPAN VENKATACHALAM
Принадлежит:

Various semiconductor chips with gettering regions and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a first side and a second side opposite the first side. The first side has a plurality of laser ablation craters. Each of the ablation craters has a bottom. A gettering region is in the semiconductor chip beneath the laser ablation craters. The gettering region includes plural structural defects. At least some of the structural defects emanate from at least some of the bottoms of the laser ablation craters. 1. An apparatus , comprising:a semiconductor chip having a first side and a second side opposite the first side;the first side having a plurality of laser ablation craters, each of the ablation craters having a bottom; anda gettering region in the semiconductor chip beneath the laser ablation craters, the gettering region including plural structural defects, at least some of the structural defects emanating from at least some of the bottoms of the laser ablation craters.2. The apparatus of claim 1 , wherein at least some of the laser ablation craters overlap laterally.3. The apparatus of claim 1 , wherein the laser ablation craters comprises sloped sidewalls.4. The apparatus of claim 3 , wherein a first laser ablation crater of the laser ablation craters comprises sidewalls sloped in a first direction and a second laser ablation crater of the laser ablation craters adjacent to the first laser ablation crater comprises sidewalls sloped in a second direction opposite the first direction.5. The apparatus of claim 1 , wherein the structural defects comprise cracks and voids.6. The apparatus of claim 1 , wherein some of the laser ablation craters have a first average depth and other of the laser ablation craters have a second average depth less than the first average depth.7. The apparatus of claim 1 , comprising a circuit board claim 1 , the semiconductor chip being mounted on the circuit ...

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Номер записи: 66
25-06-2020 дата публикации

METHOD OF EVALUATING IMPURITY GETTERING CAPABILITY OF EPITAXIAL SILICON WAFER AND EPITAXIAL SILICON WAFER

Номер: US20200203178A1
Автор: Kurita Kazunari, OKUYAMA Ryosuke, Shigematsu Satoshi
Принадлежит: SUMCO CORPORATION

Provided is a method of evaluating the impurity gettering capability of an epitaxial silicon wafer, which allows for very precise evaluation of the impurity gettering behavior of a modified layer formed immediately under an epitaxial layer, the modified layer containing carbon in solid solution. In this method, a modified layer located immediately under an epitaxial layer, the modified layer containing carbon in solid solution, is analyzed by three-dimensional atom probe microscopy, and the impurity gettering capability of the modified layer is evaluated based on a three-dimensional map of carbon in the modified layer, obtained by the analysis. 1. A method of evaluating an impurity gettering capability of an epitaxial silicon wafer produced through:implanting ions containing carbon through a surface of a silicon wafer to form a modified layer in a surface portion of the silicon wafer, the modified layer containing carbon in solid solution, andforming an epitaxial layer on the modified layer of the silicon wafer,the method comprising:subjecting the silicon wafer to a heat treatment after implanting,then analyzing the modified layer of the silicon wafer by a three-dimensional atom probe microscopy to obtain a three-dimensional map of carbon in the modified layer, andevaluating an impurity gettering capability of the modified layer based on the three-dimensional map of carbon.2. The method according to claim 1 , comprising:identifying carbon aggregates in a region ranging from a surface of the modified layer to a depth of 200 nm on the three-dimensional map of carbon, obtaining concentration profiles of carbon and an impurity in and around the carbon aggregates, andevaluating the impurity gettering capability of the modified layer based on the concentration profiles.3. The method according to claim 1 , comprising:identifying carbon aggregates in a region ranging from a surface of the modified layer to a depth of 200 nm on the three-dimensional map of carbon, ...

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Номер записи: 67
20-08-2015 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20150235866A1
Автор: Nakamura Katsumi
Принадлежит:

A semiconductor device of the present invention includes a substrate having a drift layer, metal wiring formed on an upper surface of the substrate, and an electrode formed on a back surface of the substrate, wherein the lifetime of carriers in the drift layer satisfies the following expression 1: 119-. (canceled)21. The semiconductor device according to claim 20 , wherein the substrate is formed of a wide-bandgap semiconductor.22. The semiconductor device according to claim 21 , wherein the wide-bandgap semiconductor is silicon carbide claim 21 , a gallium nitride-based material or diamond.23. A method of manufacturing a semiconductor device claim 21 , comprising:a manufacturing step of forming a first diffusion layer on an upper surface side of a substrate having a drift layer, performing film forming and performing etching;a gettering layer forming step of forming a gettering layer on a lower surface side of the drift layer exposed at a lower surface of the substrate;an annealing step of heating the substrate to capture by the gettering layer a metal impurity, contaminant atoms and damage introduced in the drift layer in the manufacturing step;a removal step of removing the gettering layer after the annealing step;a step of forming a second diffusion layer on the lower surface side of the drift layer after the removal step; anda step of forming an electrode so that the electrode contacts the second diffusion layer, wherein the gettering layer forming step includes:a step of forming doped polysilicon doped with an impurity so that the doped polysilicon contacts the drift layer exposed at the lower surface of the substrate; anda preprocessing annealing step of heating the substrate to diffuse the impurity to the lower surface side of the drift layer so that a gettering layer having crystal defects and the impurity is formed on the lower surface side of the drift layer, andwherein the doped polysilicon is also removed in the removal step.24. The method of ...

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Номер записи: 68
09-07-2020 дата публикации

METHOD OF PRODUCING SEMICONDUCTOR EPITAXIAL WAFER, SEMICONDUCTOR EPITAXIAL WAFER, AND METHOD OF PRODUCING SOLID-STATE IMAGE SENSOR

Номер: US20200219929A1
Автор: OKUYAMA Ryosuke
Принадлежит: SUMCO CORPORATION

A method of producing a semiconductor epitaxial wafer is provided. The method includes irradiating a surface of a semiconductor wafer with cluster ions to form a modified layer in a surface portion of the semiconductor wafer, in which the modified layer includes a constituent element of the cluster ions in solid solution. The method further includes forming an epitaxial layer on the modified layer of the semiconductor wafer. The irradiating is performed such that a portion of the modified layer in a thickness direction becomes an amorphous layer, and an average depth of an amorphous layer surface from a semiconductor wafer surface-side of the amorphous layer is at least 20 nm from the surface of the semiconductor wafer. 1. A method of producing a semiconductor epitaxial wafer , the method comprising:irradiating a surface of a semiconductor wafer with cluster ions to form a modified layer in a surface portion of the semiconductor wafer, the modified layer including a constituent element of the cluster ions in solid solution; andforming an epitaxial layer on the modified layer of the semiconductor wafer, a portion of the modified layer in a thickness direction becomes an amorphous layer, the amorphous layer having a first surface and a second surface disposed on a side opposite of the first surface, the first surface being closer to the surface of the semiconductor wafer than the second surface, and', 'an average depth of the first surface of the amorphous layer from the surface of the semiconductor wafer is at least 20 nm., 'wherein the irradiating is performed such that'}2. The method of producing the semiconductor epitaxial wafer of claim 1 , wherein the irradiating is performed such that the average depth is at least 20 nm and no greater than 200 nm from the surface of the semiconductor wafer.3. The method of producing the semiconductor epitaxial wafer of claim 1 , wherein the irradiating is performed such that an average thickness of the amorphous layer is no ...

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Номер записи: 69
06-11-2014 дата публикации

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

Номер: US20140329366A1
Автор: ARAYA Takeshi, KOMATANI Tsutomu
Принадлежит:

A method for fabricating a semiconductor device including: forming a silicon layer on an upper face of a nitride semiconductor layer including a channel layer of a FET; thermally treating the nitride semiconductor layer in the process of forming the silicon layer or after the process of forming the silicon layer; and forming an insulating layer on an upper face of the silicon layer after the process of forming the silicon layer. 1. A method for fabricating a semiconductor device comprising:forming a silicon layer on an upper face of a nitride semiconductor layer including a channel layer of a FET;thermally treating the nitride semiconductor layer in the process of forming the silicon layer or after the process of forming the silicon layer; andforming an insulating layer on an upper face of the silicon layer after the process of forming the silicon layer,wherein the process of forming the insulating layer is performed after the process of forming the silicon layer and before the process of thermally treating the nitride semiconductor layer.2. A method for fabricating a semiconductor device comprising:forming a silicon layer on an upper face of a nitride semiconductor layer including a channel layer of a FET;thermally treating the nitride semiconductor layer in the process of forming the silicon layer or after the process of forming the silicon layer; andforming an insulating layer on an upper face of the silicon layer after the process of forming the silicon layer,further comprising forming an ohmic electrode on the upper face of the nitride semiconductor layer after the process of forming the silicon layer,wherein:the process of forming the ohmic electrode includes a process of annealing the ohmic electrode; andthe process of thermally treating the nitride semiconductor layer is the process of annealing the ohmic electrode. This application is a divisional of U.S. application Ser. No. 13/186,111 filed Jul. 19, 2011, which is based upon and claims the benefit of ...

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Номер записи: 70
09-09-2021 дата публикации

SEMICONDUCTOR DEVICE STRUCTURE HAVING GATE DIELECTRIC LAYER

Номер: US20210280432A1
Автор: Chang I-Ming, Chao Huang-Lin, Fang Ziwei, Lin Chih-Cheng, WU Chi-Ying, You Wei-Ming
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an isolation layer over the base portion and surrounding the fin portion. The semiconductor device structure includes a metal gate stack over the isolation layer and wrapping around an upper part of the fin portion. The metal gate stack includes a gate dielectric layer and a metal gate electrode layer over the gate dielectric layer, and the gate dielectric layer includes fluorine. A first part of the isolation layer is not covered by the metal gate stack, the first part includes fluorine, and a first concentration of fluorine in the first part increases toward a first top surface of the first part. 1. A semiconductor device structure , comprising:a substrate having a base portion and a fin portion over the base portion;an isolation layer over the base portion and surrounding the fin portion; anda metal gate stack over the isolation layer and wrapping around an upper part of the fin portion, wherein the metal gate stack comprises a gate dielectric layer and a metal gate electrode layer over the gate dielectric layer, the gate dielectric layer comprises fluorine,a first part of the isolation layer is not covered by the metal gate stack, the first part comprises fluorine, and a first concentration of fluorine in the first part increases toward a first top surface of the first part.2. The semiconductor device structure as claimed in claim 1 , further comprising:a spacer layer over sidewalls of the metal gate stack, wherein the first part of the isolation layer is not covered by the spacer layer.3. The semiconductor device structure as claimed in claim 1 , further comprising:an insulating layer over the isolation layer and the fin portion, wherein the metal gate stack is embedded in the insulating layer, and the insulating layer covers the first part of the ...

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Номер записи: 71
31-08-2017 дата публикации

TRENCH METAL INSULATOR METAL CAPACITOR WITH OXYGEN GETTERING LAYER

Номер: US20170250073A1
Автор: Ando Takashi, Cartier Eduard A., Chudzik Michael P., Dasgupta Aritra, Ho Herbert L., Kang Donghun, Krishnan Rishikesh, Narayanan Vijay, RIM Kern
Принадлежит:

A method including forming an oxygen gettering layer on one side of an insulating layer of a deep trench capacitor between the insulating layer and a substrate, the oxygen gettering layer including an aluminum containing compound, and depositing an inner electrode on top of the insulating layer, the inner electrode including a metal. 1. A method comprising:forming a deep trench capacitor in a semiconductor substrate, the deep trench capacitor comprising an oxygen gettering layer on a first side of a node dielectric, the oxygen gettering layer comprising an aluminum containing compound.2. The method of claim 1 , wherein the aluminum containing compound comprises titanium aluminum nitride claim 1 , titanium aluminum carbide claim 1 , tantalum aluminum nitride claim 1 , tantalum aluminum carbide claim 1 , tungsten aluminum nitride claim 1 , tungsten aluminum carbide claim 1 , cobalt aluminum nitride claim 1 , or cobalt aluminum carbide.3. The method of claim 1 , further comprising:causing the oxygen gettering layer to be in direct contact with both the node dielectric and the semiconductor substrate, and serve as an outer electrode of the deep trench capacitor, the outer electrode of the deep trench capacitor being positioned below the node dielectric.4. The method of claim 1 , further comprising:causing the oxygen gettering layer to be in direct contact with both the node dielectric and a polysilicon fill material, and serve as an inner electrode of the deep trench capacitor, the inner electrode of the deep trench capacitor being positioned above the node dielectric.5. The method of claim 1 , wherein the deep trench capacitor is void on an interfacial oxide.6. The method of claim 1 , further comprising forming a transistor on a surface of the semiconductor substrate claim 1 , wherein the transistor is formed prior to forming the deep trench capacitor.7. The method of claim 6 , further comprising forming a barrier layer located on physically exposed surfaces of the ...

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Номер записи: 72
07-09-2017 дата публикации

THERMAL PROCESSING METHOD FOR WAFER

Номер: US20170256419A1
Автор: CHANG RICHARD R., Xiao Deyuan
Принадлежит:

The present invention relates to a thermal processing method for wafer. A wafer is placed in an environment filled with a gas mixture comprising oxygen gas and deuterium gas, and a rapid thermal processing process is performed on a surface of the wafer. As a result, a denuded zone is formed on the surface of the wafer, deuterium atoms, which may be released to improve characteristics at an interface of semiconductor devices in a later fabrication process, are held in the wafer, and bulk micro-defects are formed far from the semiconductor devices. 1. A thermal processing method for wafer , comprising:placing at least one wafer in an environment filled with a gas mixture comprising oxygen gas and deuterium gas, and performing a rapid thermal process on a surface of the least one wafer,{'sup': 12', '3', '18', '3, 'wherein a concentration of a deuterium solid solution in the at least one wafer falls within 1×10atom/cmto 8×10atom/cm.'}2. The thermal processing method for wafer as claim 1 , wherein the gas mixture further comprises argon gas and nitrogen gas.3. The thermal processing method for wafer as claim 1 , wherein the gas partial pressure of the oxygen gas in the gas mixture falls within 1% to 99%.4. The thermal processing method for wafer as claim 1 , wherein the gas partial pressure of the deuterium gas in the gas mixture falls within 1% to 99%.5. The thermal processing method for wafer as claim 2 , wherein the gas partial pressure of the argon gas in the gas mixture falls within 1% to 99%.6. The thermal processing method for wafer as claim 2 , wherein the gas partial pressure of the nitrogen gas in the gas mixture falls within 1% to 99%.7. The thermal processing method for wafer as claim 1 , wherein the rapid thermal process comprises a rapid heating process and a rapid cooling process.8. The thermal processing method for wafer as claim 7 , wherein in the rapid thermal process claim 7 , the least one wafer was cooled from a predetermined high temperature which ...

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Номер записи: 73
07-09-2017 дата публикации

THERMAL PROCESSING METHOD FOR WAFER

Номер: US20170256420A1
Автор: CHANG RICHARD R., Xiao Deyuan
Принадлежит:

The present invention relates to a thermal processing method for wafer. A wafer is placed in an environment filled with a non-oxygenated gas mixture comprising deuterium gas and at least one kind of low active gas, and a rapid heating processing process is performed on a surface of the wafer to heat the wafer to a predetermined high temperature. Then, the wafer is placed in an environment filled with an oxygenated gas mixture, and a rapid cooling processing process is performed on a surface of the wafer. As a result, a denuded zone is formed on the surface of the wafer, deuterium atoms, which may be released to improve characteristics at an interface of semiconductor devices in a later fabrication process, are held in the wafer, and bulk micro-defects are formed far from the semiconductor devices. 1. A thermal processing method for wafer , comprising:placing at least one wafer in an environment filled with a non-oxygenated gas mixture comprising deuterium gas and at least one kind of low active gas, and performing a rapid heating process on a surface of the least one wafer to heat the least one wafer to a predetermined high temperature; andafter the least one wafer's reaching the predetermined high temperature, placing the least one wafer in an environment filled with an oxygenated gas mixture, and performing a rapid cooling process on a surface of the least one wafer.2. The thermal processing method for wafer as claim 1 , wherein the at least one kind of low active gas comprises argon gas and nitrogen gas.3. The thermal processing method for wafer as claim 2 , wherein the gas partial pressure of the argon gas in the non-oxygenated gas mixture falls within 1% to 99%.4. The thermal processing method for wafer as claim 2 , wherein the gas partial pressure of the nitrogen gas in the non-oxygenated gas mixture falls within 1% to 99%.5. The thermal processing method for wafer as claim 1 , wherein the gas partial pressure of the deuterium gas in the non-oxygenated gas ...

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Номер записи: 74
06-09-2018 дата публикации

GETTERING LAYER FORMATION AND SUBSTRATE

Номер: US20180254194A1
Автор: Li Xia, Tao Gengming, YANG Bin
Принадлежит:

An integrated circuit (IC) device may include a substrate having an active device layer. The integrated circuit may also include a first defect layer. The first defect layer may have a first surface facing a backside of the active device layer. The integrated circuit may further include a second defect layer. The second defect layer may face a second surface opposite the first surface of the first defect layer. 1. An integrated circuit (IC) device , comprising:a substrate including:an active device layer;a first defect layer having a first surface facing a backside of the active device layer; anda second defect layer facing a second surface opposite the first surface of the first defect layer.2. The IC device of claim 1 , in which the second defect layer comprises a backside barrier layer.3. The IC device of claim 2 , in which the backside barrier layer comprises micro-fractures.4. The IC device of claim 1 , further comprising a back-end-of-line (BEOL) contact layer electrically coupled to the active device layer of the substrate.5. The IC device of claim 1 , in which the substrate comprises an epitaxial layer including the active device layer.6. The IC device of claim 1 , in which the first defect layer comprises SiOx and/or SiNx.7. The IC device of claim 1 , in which the first defect layer comprises an ion-implanted layer.8. The IC device of claim 7 , in which the ion-implanted layer comprises O or N implants.9. The IC device of claim 1 , in which the second defect layer comprises a thinned intrinsic gettering region.10. The IC device of claim 1 , integrated into a chip claim 1 , the chip incorporated into at least one of a music player claim 1 , a video player claim 1 , an entertainment unit claim 1 , a navigation device claim 1 , a communications device claim 1 , a personal digital assistant (PDA) claim 1 , a fixed location data unit claim 1 , a mobile phone claim 1 , and a portable computer.11. A method of fabricating an integrated circuit (IC) device claim 1 , ...

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Номер записи: 75
22-09-2016 дата публикации

SEMICONDUCTOR MANUFACTURING METHOD

Номер: US20160276170A1
Автор: HAYASHI Hidekazu, Okuda Shinya, WATANABE Kei
Принадлежит:

A semiconductor manufacturing method in accordance with an embodiment includes feeding a first gas, which contains a component of a first film, to a reaction chamber, and forming a first film over a semiconductor substrate, which is accommodated in the reaction chamber, through plasma CVD. The semiconductor manufacturing method includes feeding a second gas to the reaction chamber after forming the first film, allowing the first gas in the reaction chamber to react on the second gas, and forming a second film, which has a composition different from that of the first film, over the surface of the first film. The semiconductor manufacturing method includes selectively removing the second film. 1. A semiconductor manufacturing method comprising:feeding a first gas to a reaction chamber for forming a first film over a semiconductor substrate using plasma CVD method, the semiconductor substrate provided in the reaction chamber, the first gas comprises a component of a first film;feeding a second gas to the reaction chamber for forming a second film over the surface of the first film after forming the first film, allowing the first gas in the reaction chamber to react on the second gas, the second film comprises a composition different from that of the first film; andselectively removing the second film.2. The semiconductor manufacturing method according to claim 1 , wherein with plasma produced in the reaction chamber claim 1 , the second film is formed over the surface of the first film.3. The semiconductor manufacturing method according to claim 1 , wherein when feeding of the first gas to the reaction chamber is suspended claim 1 , feeding of the second gas to the reaction chamber is started at the same time.4. The semiconductor manufacturing method according to claim 1 , wherein before feeding of the first gas to the reaction chamber is suspended claim 1 , feeding of the second gas to the reaction chamber is started.5. The semiconductor manufacturing method according ...

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Номер записи: 76
11-12-2014 дата публикации

METHOD FOR EVALUATING SILICON SINGLE CRYSTAL AND METHOD FOR MANUFACTURING SILICON SINGLE CRYSTAL

Номер: US20140363904A1
Автор: Hoshi Ryoji, Kamada Hiroyuki, Matsumoto Suguru
Принадлежит:

The present invention provides a method for evaluating silicon single crystal wherein an amount Δ[C] of carriers generated due to oxygen donors produced when a heat treatment is performed to the silicon single crystal is calculated and evaluated, the amount Δ[C] being calculated from oxygen concentration [Oi] in the silicon single crystal, a temperature T of the heat treatment, a time t of the heat treatment, and an oxygen diffusion coefficient D(T) at the temperature T by using the following relational expression: 14-. (canceled)5. A method for evaluating silicon single crystal wherein an amount A[C] of carriers generated due to oxygen donors produced when a heat treatment is performed to the silicon single crystal is calculated and evaluated , the amount A[C] being calculated from oxygen concentration [Oi] in the silicon single crystal , a temperature T of the heat treatment , a time t of the heat treatment , and an oxygen diffusion coefficient D(T) at the temperature T by using the following relational expression:{'br': None, 'i': C]=α[Oi]', 'D', 'T', 'Oi]·t, 'sup': '5', 'Δ[×exp(−β·()·[) (where α and β are constants)'}61. The method for evaluating silicon single crystal according to claim , wherein the oxygen concentration in the silicon single crystal to be evaluated is set to 9×10atoms/cm(ASTM' 79) or less.71. The method for evaluating silicon single crystal according to claim , wherein an amount of carriers generated due to oxygen donors is calculated by using the relational expression , and a resistivity of the silicon single crystal after the heat treatment is calculated by using the calculated amount of carriers generated and is evaluated.82. The method for evaluating silicon single crystal according to claim , wherein an amount of carriers generated due to oxygen donors is calculated by using the relational expression , and a resistivity of the silicon single crystal after the heat treatment is calculated by using the calculated amount of carriers ...

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Номер записи: 77
28-09-2017 дата публикации

WORKPIECE EVALUATING METHOD

Номер: US20170278759A1
Автор: Harada Seiji, Sukegawa Naoya
Принадлежит:

A workpiece evaluating method evaluates the gettering property of a device wafer having a plurality of devices formed on the front side of the wafer and having a gettering layer formed inside the wafer. The method includes the steps of applying excitation light for exciting a carrier to the wafer, applying microwaves to a light applied area where the excitation light is applied and also to an area other than the light applied area, measuring the intensity of the microwaves reflected from the light applied area and from the area other than the light applied area, subtracting the intensity of the microwaves reflected from the area other than the light applied area from the intensity of the microwaves reflected from the light applied area to thereby obtain a differential signal, and determining the gettering property of the gettering layer according to the intensity of the differential signal obtained above. 1. A workpiece evaluating method for evaluating the gettering property of a workpiece having a plurality of devices formed on a front side of said workpiece and having a gettering layer formed inside said workpiece , said workpiece evaluating method comprising:an excitation light applying step of applying excitation light for exciting a carrier to said workpiece;a microwave applying step of applying microwaves to a light applied area where said excitation light is applied and also to an area other than said light applied area on said workpiece, after performing said excitation light applying step;a measuring step of measuring the intensity of said microwaves reflected from said light applied area and from the area other than said light applied area after performing said microwave applying step, and next subtracting the intensity of said microwaves reflected from the area other than said light applied area from the intensity of said microwaves reflected from said light applied area to thereby obtain a differential signal; anda gettering property determining step of ...

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Номер записи: 78
29-08-2019 дата публикации

Integrated Structures and Methods of Forming Integrated Structures

Номер: US20190267390A1
Автор: Hu Yongjun Jeff, McTeer Allen
Принадлежит: MICRON TECHNOLOGY, INC.

Some embodiments include an integrated structure having semiconductor material within a region between two parallel surfaces. The semiconductor material has grain boundaries parallel to the parallel surfaces. At least one circuit component utilizes a region of the semiconductor material in a gated device. The semiconductor material has little if any metal therein so that the gated device has Ion/Ioff characteristics similar to if the semiconductor material had no metal therein. Some embodiments include a method in which semiconductor material is provided between a pair of parallel surfaces, and in which the parallel surfaces and semiconductor material extend between a first end and a second end. Metal is formed adjacent the first end, and gettering material is formed adjacent the second end. Thermal processing induces crystallization of the semiconductor material and drives the metal along the semiconductor material and into the gettering material. The gettering material is then removed. 1. An integrated structure comprising semiconductor material within a region between two parallel surfaces , the semiconductor material having grain boundaries parallel to the parallel surfaces; at least one circuit component utilizing a region of the semiconductor material in a gated device; the semiconductor material having little if any metal therein so that the gated device has Ion/Ioff characteristics within a same order of magnitude as would occur if the semiconductor material had no metal therein.2. The integrated structure of having a NAND string with the parallel surfaces being on opposing sides of a channel region; the gated device being one of a plurality of gated devices corresponding to memory cells of the NAND string claim 1 , and a metal concentration being low or non-existent throughout an entirety of the channel region so that all of the memory cells of the NAND string have said Ion/Ioff characteristics.3. The integrated structure of having a U-shaped NAND string ...

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Номер записи: 79
27-09-2018 дата публикации

METHOD AND DEVICE FOR PASSIVATING DEFECTS IN SEMICONDUCTOR SUBSTRATES

Номер: US20180277710A1
Автор: Elser Hans-Peter, JOOSS WOLFGANG, PERNAU THOMAS, Reichart Andreas, Romer Olaf, Scheiffele Wolfgang, Volk Peter
Принадлежит:

The invention relates to methods and an apparatus for passivating defects of a semiconductor substrate, in particular a silicon based solar cell. According to the method, the substrate is irradiated with electromagnetic radiation during a first process phase, wherein the radiation directed onto the substrate has wavelengths at least in the region below 1200 nm and an intensity of at least 8000 Watt/m. This can lead to a heating of the substrate, or a temperature control can be provided. Subsequently, the substrate is irradiated with electromagnetic radiation during a temperature-holding phase following the first process phase, wherein the radiation directed onto the substrate has wavelengths primarily in the region below 1200 nm and an intensity of at least 8000 Watt/m, while a side of the substrate facing away from a source of the electromagnetic radiation is cooled via a contact with a support cooled by a cooling device. The apparatus comprises a continuous furnace having an elongated process chamber with at least three zones arranged in the sequence of a first processing zone, a temperature-holding zone and a cooling zone, and at least one transport unit for receiving and transporting the substrate through the zones. The apparatus further comprises at least one first radiation source which can irradiate electromagnetic radiation onto a section of the transport unit located in the first process zone, and which is configured to generate radiation having wavelengths at least in the region below 1200 nm and an intensity of at least 8000 Watt/m, and at least one second radiation source which can irradiate electromagnetic radiation onto a section of the transport unit located in the temperature-holding zone, and which is configured to generate radiation having wavelengths at least in the region below 1200 nm and an intensity of at least 8000 Watt/m. At least one cooling unit is arranged in heat-conducting contact with the section of the transport unit positioned in the ...

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Номер записи: 80
15-10-2015 дата публикации

Method of Manufacturing Semiconductor Devices Containing Chalcogen Atoms

Номер: US20150294868A1
Автор: NEIDHART Thomas, Riss Josef, Schmidt Gerhard
Принадлежит:

Chalcogen atoms are implanted into a single crystalline semiconductor substrate. At a density of interstitial oxygen of at least 5E16 cmthermal donors containing oxygen are generated at crystal defects in the semiconductor substrate. Then the semiconductor substrate is heated up to a temperature above a deactivation temperature at which the thermal donors become inactive, wherein a portion of electrically active chalcogen atoms is increased. 1. A method of manufacturing a semiconductor device , the method comprising:implanting chalcogen atoms into a single crystalline semiconductor substrate;{'sup': '−3', 'generating thermal donors containing oxygen at crystal defects in the semiconductor substrate at a density of interstitial oxygen of at least 5E16 cm; and then'}heating the semiconductor substrate up to a temperature above a deactivation temperature at which the thermal donors become inactive, wherein a portion of electrically active chalcogen atoms is increased.2. The method of claim 1 , whereinthe thermal donors are generated in a cooling phase of a first high temperature anneal above 900° C. for diffusing the chalcogen atoms.3. The method of claim 2 , further comprising:introducing auxiliary impurities into the semiconductor substrate for increasing a density of interstitial semiconductor atoms before the first high temperature anneal.4. The method of claim 3 , whereinthe auxiliary impurities are phosphorus atoms.5. The method of claim 3 , further comprising:removing an auxiliary layer predominantly containing the auxiliary impurities after the first high temperature anneal.6. The method of claim 1 , whereinthe semiconductor substrate is a Czochralski silicon wafer obtained from a Czochralski-grown silicon ingot.7. The method of claim 2 , whereina cooling phase of the first high temperature anneal pauses for at least 5 minutes in a temperature range above an activation temperature of the thermal donors and below a deactivation temperature of the thermal donors. ...

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Номер записи: 81
15-10-2015 дата публикации

Microwave Anneal (MWA) for Defect Recovery

Номер: US20150294881A1
Автор: TSAI Chun Hsiung, Wann Clement Hsingjen
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

The embodiments of processes and structures described above provide mechanisms for annealing defects by microwave anneal (MWA). MWA causes ionic/atomic (ionic and/or atomic) polarization, electronic polarization, and/or interfacial polarization in a substrate with dopants, damages, and interfaces in crystalline structures. The polarizations make the local temperatures higher than the substrate temperature. As a result, MWA can remove damages at a relatively low substrate temperature than other anneal mechanisms and is able to prevent undesirable dopant diffusion. The relatively low substrate temperature also makes MWA compatible with advanced processing technologies which demands lower substrate temperatures during front-end processing. MWA used in annealing defects (or damages) created in forming source and drain regions improves NMOS transistor performance. 1. A method of forming a semiconductor device , comprising:providing a substrate;performing at least one crystalline damaging process; andperforming at least one microwave anneal (MWA) process, wherein one of the at least microwave anneal process is a multi-stage MWA process.2. The method of claim 1 , wherein two or more crystalline damaging processes are performed.3. The method of claim 1 , wherein the one of the at least one microwave anneal process is performed in a microwave anneal system with at top susceptor and a bottom susceptor.4. The method of claim 3 , wherein the top susceptor and the bottom susceptor are made of an energy converting material with a loss tangent in a range from about 0.1 to about 2.5. The method of claim 1 , wherein frequency of the multi-stage MWA process is in a range from about 5 GHz to about 10 GHz.6. The method of claim 1 , wherein second stage of the multi-stage MWA process has a power in a range from about 3000 watts to about 7000 watts.7. The method of claim 1 , wherein substrate temperature of first stage of the multi-stage MWA process is in a range from about 350° C. to ...

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Номер записи: 82
25-12-2014 дата публикации

METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

Номер: US20140377938A1
Автор: Kuribayashi Hidenao, NAKAZAWA Haruo, OGINO Masaaki, Teranishi Hideaki
Принадлежит:

A method for producing a semiconductor device is disclosed which includes a diffusion step of forming, on a CZ-FZ silicon semiconductor substrate, a deep diffusion layer involving a high-temperature and long-term thermal diffusion process which is performed at a thermal diffusion temperature of 1290° C. to a melting temperature of a silicon crystal for 100 hours or more; and a giving step of giving a diffusion source for an interstitial silicon atom to surface layers of two main surfaces of the silicon semiconductor substrate before the high-temperature, long-term thermal diffusion process. The step of giving the diffusion source for the interstitial silicon atom to the surface layers of the two main surfaces of the silicon semiconductor substrate is performed by forming thermally-oxidized films on two main surfaces of the silicon semiconductor substrate or by implanting silicon ions into surface layers of the two main surfaces of the silicon semiconductor substrate. 1. A method for producing a semiconductor device comprising:a diffusion step of forming a diffusion layer with a high-temperature and long-term thermal diffusion process which is performed for 100 hours or more on a silicon semiconductor substrate produced by a floating zone method, at a thermal diffusion temperature of at least about 1290° C. to a melting temperature of a silicon crystal; anda giving step of giving a diffusion source for a silicon atom, which becomes an interstitial atom in the silicon semiconductor substrate in the diffusion step, to surface layers of two main surfaces of the silicon semiconductor substrate before the diffusion step.2. The method for producing a semiconductor device according to claim 1 , wherein the semiconductor substrate is cut from a silicon crystal which is produced by the floating zone method using polycrystalline silicon as a raw material.3. The method for producing a semiconductor device according to claim 1 , wherein the semiconductor substrate is cut from a ...

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Номер записи: 83
06-10-2016 дата публикации

METHOD OF PRODUCING EPITAXIAL SILICON WAFER, EPITAXIAL SILICON WAFER, AND METHOD OF PRODUCING SOLID-STATE IMAGE SENSING DEVICE

Номер: US20160293426A1
Автор: Kadono Takeshi
Принадлежит: SUMCO CORPORATION

Provided is an epitaxial silicon wafer free of epitaxial defects caused by dislocation clusters and COPs with reduced metal contamination achieved by higher gettering capability and a method of producing the epitaxial wafer. 1. A method of producing an epitaxial silicon wafer , comprising:a first step of irradiating a silicon wafer free of dislocation clusters and COPs with cluster ions including a constituent element contributing to gettering of heavy metal to form a modifying layer formed from the constituent element of the cluster ions in a surface portion of the silicon wafer,a second step of forming an epitaxial layer on the modifying layer of the silicon wafer,wherein, in the first step, the silicon wafer is irradiated with the cluster ions such that the full width half maximum of a concentration profile of the constituent element in the depth direction of the modifying later after the second step is 100 nm or less.2. The method of producing an epitaxial silicon wafer according to claim 1 , wherein the cluster ions contain carbon as a constituent element.3. The method of producing an epitaxial silicon wafer according to claim 2 , wherein the cluster ions contain at least two kinds of elements including carbon as constituent elements.4. The method of producing an epitaxial silicon wafer according to claim 1 , wherein claim 1 , after the first step claim 1 , the silicon wafer is transferred into an epitaxial growth apparatus to be subjected to the second step without heat treating the silicon wafer for recovering its crystallinity.5. The method of producing an epitaxial silicon wafer according to claim 1 , wherein claim 1 , in the first step claim 1 , the silicon wafer is irradiated with the cluster ions such that the peak of a concentration profile of the constituent element in the depth direction of the modifying layer lies at a depth within 150 nm from the surface of the silicon wafer.6. The method of producing an epitaxial silicon wafer according to claim 5 ...

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Номер записи: 84
29-10-2015 дата публикации

STRUCTURE AND METHOD FOR METAL GATE STACK OXYGEN CONCENTRATION CONTROL USING AN OXYGEN DIFFUSION BARRIER LAYER AND A SACRIFICIAL OXYGEN GETTERING LAYER

Номер: US20150311126A1
Автор: CHAMBERS James Joseph, NIIMI Hiroaki
Принадлежит:

A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates have effective work functions above 4.85 eV and the NMOS gates have effective work functions below 4.25 eV. Metal work function layers in both the NMOS and PMOS gates are oxidized to increase their effective work functions to the desired PMOS range. An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over the NMOS gates. A getter anneal extracts the oxygen from the NMOS work function layers and adds metal atom enrichment to the NMOS work function layers, reducing their effective work functions to the desired NMOS range. Processes and materials for the metal work function layers, the oxidation process and oxygen gettering are disclosed. 1. A process of forming an integrated circuit , comprising the steps of:forming a dummy PMOS gate stack and a dummy NMOS gate stack, wherein said dummy PMOS gate stack includes a PMOS gate dielectric layer, a PMOS gate work function metal layer and a PMOS dummy gate layer, and said dummy NMOS gate stack includes a NMOS gate dielectric layer, a NMOS gate work function metal layer and a NMOS dummy gate layer;removing said PMOS dummy gate layer and said NMOS dummy gate layer;performing a low temperature oxidation process on the NMOS gate work function metal layer and the PMOS gate work function metal layer;after performing the low temperature oxidation process, forming an oxygen diffusion barrier layer over said PMOS gate work function metal layer;forming an oxygen getter layer over said NMOS gate work function metal layer, wherein said oxygen getter layer is blocked from said PMOS gate work function metal layer by said oxygen diffusion barrier layer;performing a getter anneal process with the oxygen diffusion barrier layer over the PMOS gate work function metal layer and the oxygen getter layer over the ...

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Номер записи: 85
02-11-2017 дата публикации

Semiconductor Device Having a Defined Oxygen Concentration

Номер: US20170316929A1
Автор: CASPARY Nico, Momeni Mohammad, Oefner Helmut, Ploss Reinhard, Santos Rodriguez Francisco Javier, Schulze Hans-Joachim
Принадлежит:

A method for manufacturing a substrate wafer includes providing a device wafer () having a first side () and a second side (); subjecting the device wafer () to a first high temperature process for reducing the oxygen content of the device wafer () at least in a region () at the second side (); bonding the second side () of the device wafer () to a first side () of a carrier wafer () to form a substrate wafer (); processing the first side () of the substrate wafer () to reduce the thickness of the device wafer (); subjecting the substrate wafer () to a second high temperature process for reducing the oxygen content at least of the device wafer (); and at least partially integrating at least one semiconductor component () into the device wafer () after the second high temperature process. 120-. (canceled)21. A semiconductor device , comprising:a semiconductor substrate having a first side, a second side opposite the first side, and a thickness;at least one semiconductor component integrated in the semiconductor substrate;a first metallization at the first side of the semiconductor substrate;a second metallization at the second side of the semiconductor substrate;wherein the semiconductor substrate has an oxygen concentration along a thickness line of the semiconductor substrate which has a global maximum at a position of 20% to 80% of the thickness relative to the first side,wherein the global maximum is at least 2-times larger than the oxygen concentrations at each of the first side and the second side of the semiconductor substrate.22. The semiconductor device of claim 21 , wherein the global maximum is at least 5-times larger than the oxygen concentrations at each of the first side and the second side of the semiconductor substrate.23. The semiconductor device of claim 21 , wherein the global maximum of the oxygen concentration is less than 5*10/cm.24. The semiconductor device of claim 21 , wherein the global maximum of the oxygen concentration is equal to or less ...

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Номер записи: 86
17-11-2016 дата публикации

APPARATUS AND METHOD FOR REMOVING PARTICLES PRESENT ON A WAFER USING PHOTOELECTRONS AND AN ELECTRIC FIELD

Номер: US20160336196A1
Автор: Kim Si Hyun, SIM Jae Hee
Принадлежит:

A wafer processing apparatus includes a particle charger for charging particles adsorbed onto a wafer with photoelectrons emitted from an emitter metal layer and a particle remover for applying an electric field to the wafer, which removes the charged particles from the wafer. 1. A wafer processing apparatus , comprising:a particle charger charging particles adsorbed onto a surface of a wafer with photoelectrons emitted via the photoelectric effect; anda particle remover applying an electric field to the wafer transferred from the particle charger, the electric field removing the charged particles from the wafer.2. The apparatus of claim 1 , wherein the particle charger is separate from the particle remover.3. The apparatus of claim 1 , wherein the particle charger comprises:a first supporter supporting the wafer;an emitter metal layer emitting the photoelectrons via the photoelectric effect such that the particles adsorbed onto the surface of the wafer are charged with the photoelectrons; anda light source generating a light toward the emitter metal layer to induce the photoelectric effect.4. The apparatus of claim 3 , wherein the particle remover comprises:a second supporter supporting the wafer transferred from the particle charger;an electrode plate generating the electric field applied to the wafer transferred from the particle charger so that the charged particles are detached from the wafer; anda power supply unit supplying power to the electrode plate.5. The apparatus of claim 3 , wherein the wafer is loaded into the particle charger and spaced apart from the emitter metal layer by a certain distance.6. The apparatus of claim 3 ,wherein the particle charger further comprises a transparent member disposed between the light source and the emitter metal layer such that the light generated from the light source reaches the emitter metal layer through the transparent member; andwherein the transparent member supports the emitter metal layer such that a top ...

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Номер записи: 87
08-11-2018 дата публикации

GETTERING LAYER FORMING METHOD

Номер: US20180323080A1
Автор: Harada Seiji
Принадлежит:

A gettering layer forming method includes a coating step of applying a solution of metal salt to a back side of a wafer, and a drying step of drying the wafer after performing the coating step, thereby forming a gettering layer containing the metal salt on the back side of the wafer. 1. A gettering layer forming method for forming a gettering layer on a back side of a wafer having devices formed on a front side , the gettering layer forming method comprising:a coating step of applying a solution of metal salt to the back side of the wafer; anda drying step of drying the wafer after performing the coating step, thereby forming the gettering layer containing the metal salt on the back side of the wafer.2. The gettering layer forming method according to claim 1 , wherein the metal salt contains divalent metal claim 1 , and the gettering layer contains 1×10atoms or more of the divalent metal per cm.3. The gettering layer forming method according to claim 1 , wherein the metal salt contains trivalent metal claim 1 , and the gettering layer contains 1×10atoms or more of the trivalent metal per cm. The present invention relates to a gettering layer forming method for forming a gettering layer on a wafer, the gettering layer having a function of capturing impurities.There is an increasing chance of thinning a wafer by any method such as grinding before dividing the wafer into device chips, so as to reduce the thickness and weight of each device chip adapted to be incorporated into electronic equipment or the like. For example, the wafer can be thinned by rotating a tool (abrasive member) containing abrasive grains dispersed in a bond and pressing this tool against a work surface of the wafer to thereby grind the work surface.In grinding the wafer as described above, minute marks (flaws) or strain may be produced on the work surface of the wafer. Such marks or strain has a gettering function of capturing impurities such as copper (Cu) having an adverse effect on the device ...

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Номер записи: 88
08-11-2018 дата публикации

GETTERING LAYER FORMING METHOD

Номер: US20180323081A1
Автор: Harada Seiji, Shitabo Daigo, Takeuchi Hiroki
Принадлежит:

A gettering layer forming method includes a coating step of applying a solution of metal salt to a back side of a wafer, and a diffusing step of heating the wafer after performing the coating step, thereby diffusing the metal salt on the back side of the wafer to form a gettering layer containing the metal salt on the back side of the wafer, in which the metal salt is diffused in the gettering layer. 1. A gettering layer forming method for forming a gettering layer on a back side of a wafer having devices formed on a front side , the gettering layer forming method comprising:a coating step of applying a solution of metal salt to the back side of the wafer; anda diffusing step of heating the wafer after performing the coating step, thereby diffusing the metal salt on the back side of the wafer to form the gettering layer containing the metal salt on the back side of the wafer, wherein the metal salt is diffused in the gettering layer.2. The gettering layer forming method according to claim 1 , wherein the diffusing step comprises the step of applying a laser beam to the back side of the wafer claim 1 , the laser beam having an absorption wavelength to the wafer claim 1 , thereby heating the wafer to diffuse the metal salt.3. The gettering layer forming method according to claim 1 , wherein the metal salt contains divalent metal claim 1 , and the gettering layer contains 1×10atoms or more of the divalent metal per cm.4. The gettering layer forming method according to claim 1 , wherein the metal salt contains trivalent metal claim 1 , and the gettering layer contains 1×10atoms or more of the trivalent metal per cm. The present invention relates to a gettering layer forming method for forming a gettering layer on a wafer, the gettering layer having a function of capturing impurities.There is an increasing chance of thinning a wafer by any method such as grinding before dividing the wafer into device chips, so as to reduce the thickness and weight of each device chip ...

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Номер записи: 89
08-10-2020 дата публикации

METHOD FOR MANUFACTURING ELECTRONIC DEVICE AND METHOD FOR REMOVING IMPURITY USING SAME

Номер: US20200321528A1
Автор: Lee Sang Wook, Shin Dong Hoon
Принадлежит:

Provided are a method for manufacturing an electronic device capable of efficiently utilizing a material and a method for removing impurities using the same. The method for manufacturing an electronic device comprises the steps of: placing a transfer film on a plurality of functional layers which are positioned apart from each other on a source substrate; bringing a first transfer target into close contact with the lower surface of the transfer film by applying pressure to a portion of the transfer film that corresponds to the first transfer target from among the plurality of functional layers by using a probe; separating the transfer film from the source substrate in a state in which the first transfer target is in close contact with the lower surface; placing the transfer film on a target substrate in the state in which the first transfer target is in close contact with the lower surface; placing the first transfer target on the target substrate by applying pressure to a portion of the transfer film that corresponds to the first transfer target; and separating the transfer film from the target substrate in a state in which the first transfer target is positioned on the target surface. 1. A method for manufacturing an electronic device , comprising:placing a transfer film on a plurality of functional layers positioned apart from each other on a source substrate;applying pressure to a portion of the transfer film that corresponds to a first transfer target from among the plurality of functional layers through a probe to bring the first transfer target into close contact with a lower surface of the transfer film;separating the transfer film from the source substrate in a state in which the first transfer target is in close contact with the lower surface of the transfer film;placing the transfer film on a target substrate in the state in which the first transfer target is in close contact with the lower surface of the transfer film;applying pressure to a portion of ...

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Номер записи: 90
22-11-2018 дата публикации

SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AS A GETTERING LAYER

Номер: US20180337063A1
Автор: Takeuchi Hideki
Принадлежит:

A semiconductor device may include a semiconductor substrate having a front side and a back side opposite the front side, and a superlattice gettering layer on the front side of a semiconductor substrate. The superlattice gettering layer may include stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The device may further include an active semiconductor layer on the superlattice gettering layer opposite the semiconductor substrate, at least one semiconductor circuit in the active semiconductor layer, at least one metal interconnect layer on the active layer, and at least one metal through-via extending from the at least one metal interconnect layer to the back side of the semiconductor substrate. The superlattice gettering layer may further include gettered metal ions. 1. A semiconductor device comprising:a semiconductor substrate having a front side and a back side opposite the front side;a superlattice gettering layer on the front side of the semiconductor substrate, the superlattice gettering layer comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;an active semiconductor layer on the superlattice gettering layer opposite the semiconductor substrate;at least one semiconductor device in the active semiconductor layer; andat least one metal interconnect layer on the active layer, and at least one metal through-via extending from the at least one metal interconnect layer to the back side of the semiconductor substrate;the superlattice gettering layer further comprising gettered metal ions.2. The ...

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Номер записи: 91
22-11-2018 дата публикации

METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AS A GETTERING LAYER

Номер: US20180337064A1
Автор: Takeuchi Hideki
Принадлежит:

A semiconductor processing method may include forming a superlattice gettering layer on a front side of a semiconductor substrate having a first thickness, epitaxially growing an active semiconductor layer on the superlattice gettering layer opposite the semiconductor substrate, forming at least one semiconductor device in the active semiconductor layer, and forming at least one metal interconnect layer on the active layer, and at least one metal through-via extending from the at least one metal interconnect layer into the semiconductor substrate. The method may further include thinning the semiconductor substrate from a back side thereof to a second thickness less than the first thickness, and thinning the semiconductor substrate. The superlattice gettering layer getters metal ions released by the forming of the at least one metal interconnect layer and at least one metal through-via, and thinning the substrate. 1. A semiconductor processing method comprising:forming a superlattice gettering layer on a front side of a semiconductor substrate having a first thickness, the superlattice gettering layer comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;epitaxially growing an active semiconductor layer on the superlattice gettering layer opposite the semiconductor substrate;forming at least one semiconductor device in the active semiconductor layer;forming at least one metal interconnect layer on the active layer, and at least one metal through-via extending from the at least one metal interconnect layer into the semiconductor substrate; andthinning the semiconductor substrate from a back side thereof to a second thickness less than the first thickness;the superlattice gettering layer configured to getter metal ions released ...

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Номер записи: 92
07-11-2019 дата публикации

EXTERNAL GETTERING METHOD AND DEVICE

Номер: US20190341321A1
Автор: Pour Cheng P., Tan Michael
Принадлежит:

Disclosed embodiments include external gettering provided by electronic packaging. An external gettering element for a semiconductor substrate, which may be incorporated as part of an electronic packaging for the structure, is disclosed. Semiconductor structures and stacked semiconductor structures including an external gettering element are also disclosed. An encapsulation mold compound providing external gettering is also disclosed. Methods of fabricating such devices are also disclosed. 1. A semiconductor wafer comprising:a substrate having a device section for forming semiconductor devices and a backside section; andan external gettering element arranged adjacent said backside section of said substrate, said external gettering element comprising (i) a gettering material for forming a denude zone at said device section and (ii) an adhesive material,wherein said gettering material is separate from said adhesive material.2. The semiconductor wafer of claim 1 , wherein said adhesive material is a die attach film.3. The semiconductor wafer of claim 1 , wherein said adhesive material is configured to adhere said gettering material to said backside section of said substrate.4. The semiconductor wafer of claim 1 , wherein said gettering material is imbued with particular polarities or quantities of ions in order to attract ions or contaminants within said substrate toward said backside section.5. A stacked semiconductor structure including a plurality of wafers claim 1 , said structure comprising:a first substrate having a first device section designated for forming semiconductor devices and a first backside section;a second substrate having a second device section designated for forming semiconductor devices and a second backside section facing said first backside section of said first substrate; andan external gettering element arranged adjacent to at least one of said first backside section of said first substrate and said second backside section of said second ...

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Номер записи: 93
24-12-2015 дата публикации

Method of Reducing an Impurity Concentration in a Semiconductor Body, Method of Manufacturing a Semiconductor Device and Semiconductor Device

Номер: US20150371871A1
Автор: Schulze Hans-Joachim
Принадлежит:

A method of reducing an impurity concentration in a semiconductor body includes irradiating the semiconductor body with particles through a first side of the semiconductor body. The method further includes removing at least a part of impurities from an irradiated part of the semiconductor body by out-diffusion during thermal treatment in a temperature range between 450° C. to 1200° C. 1. A method of reducing an impurity concentration in a semiconductor body , the method comprising:irradiating the semiconductor body with particles through a first side of the semiconductor body; andremoving at least a part of impurities from an irradiated part of the semiconductor body by out-diffusion during thermal treatment in a temperature range between 450° C. to 1200° C.2. The method of claim 1 , wherein the semiconductor body is a magnetic Czochralski silicon body.3. The method of claim 1 , wherein the impurities include nitrogen.4. The method of claim 3 , wherein the thermal treatment is in the temperature range between 700° C. to 1200° C.5. The method of claim 1 , wherein the impurities include carbon.6. The method of claim 5 , wherein the thermal treatment is in the temperature range between 650° C. to 900° C.7. The method of claim 1 , wherein the particles include at least one of protons and helium ions.810. The method of claim 1 , wherein the thermal treatment is carried out for a duration between seconds to twenty hours.9. A method of manufacturing a semiconductor device claim 1 , the method comprising:irradiating the semiconductor body with particles through a first side of the semiconductor body;removing at least a part of impurities from an irradiated part of the semiconductor body by out-diffusion during thermal treatment in a temperature range between 450° C. to 1200° C.; andforming a first load terminal structure at the first side of the semiconductor body.10. The method of claim of claim 9 , wherein the semiconductor device is a vertical semiconductor device claim ...

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Номер записи: 94
28-12-2017 дата публикации

Integrated Circuit Devices

Номер: US20170372971A1
Автор: CHOI Soo-jung, KIM Weon-Hong, LEE MIN-JOO, Song Moon-Kyun, YOO Dong-su
Принадлежит:

An integrated circuit device may include a gate insulation layer covering a top surface and opposite sidewalls of a fin-shaped active region, a gate electrode covering the gate insulation layer and a hydrogen atomic layer disposed along an interface between the fin-shaped active region and the gate insulation layer. A method of manufacturing the integrated circuit device may include forming an insulating layer covering a lower portion of a preliminary fin-shaped active region, forming a fin-shaped active region having an outer surface with an increased smoothness through annealing an upper portion of the preliminary fin-shaped active region in a hydrogen atmosphere and forming a hydrogen atomic layer covering the outer surface of the fin-shaped active region. A gate insulation layer and a gate electrode may be formed to cover a top surface and opposite sidewalls of the fin-shaped active region. 1. An integrated circuit device comprising:a fin-shaped active region;a gate insulation layer covering a top surface and opposite sidewalls of the fin-shaped active region;a gate electrode covering the gate insulation layer on the top surface and on the opposite sidewalls of the fin-shaped active region; anda hydrogen atomic layer extending along an interface between the fin-shaped active region and the gate insulation layer.2. The integrated circuit device of claim 1 , wherein the hydrogen atomic layer comprises at least one of a protium atom (H) and a deuterium atom (H).3. The integrated circuit device of claim 1 , wherein the gate insulation layer comprises:an interface layer on the hydrogen atomic layer; anda high-k dielectric layer on the interface layer, the high-k dielectric layer having a dielectric constant greater than a dielectric constant of the interface layer.4. The integrated circuit device of claim 3 , wherein the gate insulation layer further comprises a lower gate insulation layer between the hydrogen atomic layer and the interface layer claim 3 , the lower ...

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Номер записи: 95
28-12-2017 дата публикации

Integrated Structures and Methods of Forming Integrated Structures

Номер: US20170373076A1
Автор: Hu Yongjun Jeff, McTeer Allen
Принадлежит:

Some embodiments include an integrated structure having semiconductor material within a region between two parallel surfaces. The semiconductor material has grain boundaries parallel to the parallel surfaces. At least one circuit component utilizes a region of the semiconductor material in a gated device. The semiconductor material has little if any metal therein so that the gated device has Ion/Ioff characteristics similar to if the semiconductor material had no metal therein. Some embodiments include a method in which semiconductor material is provided between a pair of parallel surfaces, and in which the parallel surfaces and semiconductor material extend between a first end and a second end. Metal is formed adjacent the first end, and gettering material is formed adjacent the second end. Thermal processing induces crystallization of the semiconductor material and drives the metal along the semiconductor material and into the gettering material. The gettering material is then removed. 1: An integrated structure comprising semiconductor material within a region between two parallel surfaces , the semiconductor material having grain boundaries parallel to the parallel surfaces; at least one circuit component utilizing a region of the semiconductor material in a gated device; the semiconductor material having little if any metal therein so that the gated device has Ion/Ioff characteristics within a same order of magnitude as would occur if the semiconductor material had no metal therein.2: The integrated structure of having a NAND string with the parallel surfaces being on opposing sides of a channel region; the gated device being one of a plurality of gated devices corresponding to memory cells of the NAND string claim 1 , and a metal concentration being low or non-existent throughout an entirety of the channel region so that all of the memory cells of the NAND string have said Ion/Ioff characteristics.3: The integrated structure of having a U-shaped NAND string ...

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Номер записи: 96
26-11-2020 дата публикации

Phosphorus Fugitive Emission Control

Номер: US20200373170A1
Автор: JR. Peter G., Koo Il-Woong, Lee Jun Seok, Miller Timothy J., Mittal Deven Raj, Ryan, Wang Cuiyang
Принадлежит:

A method of processing and passivating an implanted workpiece is disclosed, wherein, after passivation, the fugitive emissions of the workpiece are reduced to acceptably low levels. This may be especially beneficial when phosphorus, arsine, germane or another toxic species is the dopant being implanted into the workpiece. In one embodiment, a sputtering process is performed after the implantation process. This sputtering process is used to sputter the dopant at the surface of the workpiece, effectively lowering the dopant concentration at the top surface of the workpiece. In another embodiment, a chemical etching process is performed to lower the dopant concentration at the top surface. After this sputtering or chemical etching process, a traditional passivation process can be performed. 1. A method of reducing gaseous emissions from a workpiece implanted with a dopant , comprising:removing the dopant from a top surface of the workpiece after implanting the workpiece; andpassivating the top surface of the implanted workpiece.2. The method of claim 1 , wherein the dopant is removed from the top surface by sputtering.3. The method of claim 2 , wherein an inert gas is used to sputter the top surface.4. The method of claim 3 , wherein the inert gas is argon.5. The method of claim 1 , wherein the dopant is removed from the top surface using chemical etching.6. The method of claim 5 , wherein hydrogen claim 5 , CF claim 5 , or NFis used during the chemical etching.7. The method of claim 1 , wherein the passivating is performed in a nitrogen rich environment or an oxygen rich environment.8. The method of claim 1 , wherein the dopant comprises phosphine claim 1 , arsine or germane.9. The method of claim 1 , wherein the dopant is removed from the top surface by a combination of sputtering and chemical etching.10. A method of reducing gaseous emissions from an implanted workpiece claim 1 , comprising:performing a sputtering process after the workpiece has been implanted, ...

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Номер записи: 97
25-02-2010 дата публикации

Semiconductor device gate structure including a gettering layer

Номер: US20100048010A1
Автор: Cheng-Lung Hung, Chien-Hao Chen, Donald Y. Chao, Kuo-Tai Huang, Peng-Fu Hsu, Yong-Tian Hou
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method is provided that allows for maintaining a desired equivalent oxide thickness (EOT) by reducing the thickness of an interfacial layer in a gate structure. An interfacial layer is formed on a substrate, a gate dielectric layer such as, a high-k gate dielectric, is formed on the interfacial layer. A gettering layer is formed on the substrate overlying the interfacial layer. The gettering layer may function to getter oxygen from the interfacial layer such that the interfacial layer thickness is decreased and/or restricted from growth.

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Номер записи: 98
02-08-2011 дата публикации

Semiconductor device gate structure including a gettering layer

Номер: US7989321B2
Автор: Cheng-Lung Hung, Chien-Hao Chen, Donald Y. Chao, Kuo-Tai Huang, Peng-Fu Hsu, Yong-Tian Hou
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method is provided that allows for maintaining a desired equivalent oxide thickness (EOT) by reducing the thickness of an interfacial layer in a gate structure. An interfacial layer is formed on a substrate, a gate dielectric layer such as, a high-k gate dielectric, is formed on the interfacial layer. A gettering layer is formed on the substrate overlying the interfacial layer. The gettering layer may function to getter oxygen from the interfacial layer such that the interfacial layer thickness is decreased and/or restricted from growth.

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Номер записи: 99
29-06-1993 дата публикации

Semiconductor gettering process using backside chemical mechanical planarization (CMP) and dopant diffusion

Номер: US5223734A
Автор: Gurtej S. Sandhu, Trung T. Doan, Tyler A. Lowrey
Принадлежит: Micron Technology Inc

A gettering process for semiconductor manufacturing is disclosed. The gettering process is performed after device formation and after a protective layer such as (BPSG) or (PSG) has been applied to the front side of a semiconductor wafer. The gettering process includes thinning and roughening a backside of the wafer using chemical mechanical planarization (CMP). During the (CMP) dislocations are formed which function as a trap of mobile contaminants. Additionally a gettering agent such as phosphorus is deposited and diffused into the backside of the wafer. The wafer can then be annealed for driving in the gettering agent and segregating mobile contaminants in the wafer at gettering centers formed at the dislocations and at gettering agent sites within the wafer crystal structure. The annealing step may also function to reflow and planarize the (BPSG) or (PSG) protective layer.

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Номер записи: 100