Verfahren zum Herstellen von multifunktionellen, monolithisch-integrierten Schaltungsanordnungen

VERFAHREN ZUR HERSTELLUNG EINES FELDEFFEKT-TRANSISTORS

METHOD OF MANUFACTURING A TRANSISTOR

Semiconductor device manufacture

PHOTODETECTOR INTEGRATED CIRCUIT

Semiconductor device and method of fabricating semiconductor device

A semiconductor device, such as a p-HEMT or a quantum well laser, includes a semiconductor base substrate (101 or 121) having a lattice constant and a surface; and a strained layer (3 or 24) grown on the surface of the semiconductor base substrate and comprising a semiconductor having a zinc-blende crystal structure with a lattice constant different from that of the semiconductor base substrate. The interface between the semiconductor base substrate and the strained layer is in a crystal plane which satisfies the relationship of (1 - * small Greek nu * cos 2 * small Greek alpha *)/cos * small Greek lambda * > 2(1 - * small Greek nu */4), where * small Greek nu * is the Poisson ratio, * small Greek alpha * is the angle between the Burgers vector and the dislocation line, and * small Greek lambda * is the angle between the Burgers vector and the direction in the interface, normal to the dislocation line, and the strained layer is epitaxially grown on the surface of the semiconductor base ...

A method and system for magnetically assisted statistical assembly of wafers

Single supply hfet with temperature compensation

Semiconductor structure

INTEGRATED CIRCUITS EMPLOYING ION-BOMBARDED INP LAYERS

Verfahren zur Herstellung von Feldeffekt-Transistoren

A millimeter wave overprotection circuit based on a Schottky diode and a preparation method thereof

Manufacturing method of InP PIN photoelectric detector integrated device

Group III nitride based flip-chip integrated circuit and method for fabricating

Dispositif optoélectronique réalisé en optique intégrée et procédé de réalisation

Dispositif optoélectronique intégré dans lequel le transistor de commande T3, T4, T5 entoure le dispositif optoélectronique D6, D7, D8 Ce transistor de commande et le dispositif optoélectronique sont réalisés par gravure dans une même série de couches. Application : réalisation de photodétecteurs et de laser.

Transistor a effet de champ, son procede de realisation, et procede d'integration monolithique d'un transistor a effet de champ et d'un laser

L'invention concerne notamment un transistor a effet de champ, comportant une grille a jonction PN enterree, ce transistor comportant : - une couche active 28, ayant un dopage N; - une couche a forte conductivite 25, ayant un dopage N+; et etant divisee en deux parties distinctes qui sont separees par un espace et qui se terminent chacune par un plan 31, 35 incline de 45° par rapport au plan de la couche active 28; - deux plots de metal 33, 34 constituant respectivement des contacts de source et de drain pour le transistor; - un barreau 30 de materiau semi-conducteur ayant un dopage de type P et comportant une face 37 en contact avec la couche active 28 pour constituer une jonction PN qui est la grille de commande du transistor; et ayant deux faces 32, 36 inclinees a 45° par rapport au plan de la couche active 28, et separees respectivement des deux plans 31, 35 terminaux des couches 35, par un espace vide ayant une largeur constante; - un plot de metal 30 situe sur le barreau 23' et constituant ...

METHOD OF FABRICATING MONOLITHIC MULTIFUNCTION INTERGRATED CIRCUIT DEVICES

모놀리식 집적 회로(MMIC) 구조 및 이러한 구조를 형성하기 위한 방법

... 제1 전극 및 제2 전극 사이에 캐리어들의 흐름을 제어하기 위한 컨트롤 전극을 구비하는 트랜지스터 장치를 갖는 반도체 구조를 형성하기 위한 방법이 개시된다. 패시베이션층은 상기 제1 전극, 상기 제2 전극 및 상기 컨트롤 전극 상에 증착된다. 식각 정지층은 상기 컨트롤 전극 상부의 상기 패시베이션층 상에 증착된다. 유전층은 상기 식각 정지층 상부에 형성된다. 윈도우는 상기 컨트롤 전극 상부에 배치되는 상기 식각 정지층의 일부를 노출시키도록 상기 컨트롤 전극 상부의 상기 유전층 내의 선택된 영역을 통해 식각된다. 금속층이 상기 식각 정지층의 일부 상에 형성되고, 상기 유전층도 상기 금속층 상에 형성된다. 제2의 금속층이 앞서 언급한 제1의 금속층 상에 형성된 상기 유전층 상에 증착된다.

NORMALLY OFF III-NITRIDE SEMICONDUCTOR DEVICE HAVING A PROGRAMMABLE GATE

A III-nitride semiconductor device which includes a charged gate insulation body. © KIPO & WIPO 2008 ...

SEMICONDUCTOR DEVICE COMPRISING A PN-HETEROJUNCTION

An electric device is disclosed comprising a pn-heterojunction (4) formed by a nanowire (3) of 111-V semiconductor material and a semiconductor body (1) comprising a group IV semiconductor material. The nanowire (3) is positioned in direct contact with the surface (2) of the semiconductor body (1) and has a first conductivity type, the semiconductor body (1) has a second conductivity type opposite to the first conductivity type, the nanowire (3) forming with the semiconductor body (1) a pn-heterojunction (4). The nanowire of III-V semiconductor material can be used as a diffusion source (5) of dopant atoms into the semiconductor body. The diffused group III atoms and/or the group V atoms from the III-V material are the dopant atoms forming a region (6) in the semiconductor body in direct contact with the nanowire (3). © KIPO & WIPO 2007 ...

Wafer to wafer bonding techniques for iii-v wafers and cmos wafers

Method for fabricating bipolar transistor

A fabrication method of bipolar transistor is provided. First, a first mask layer exposing a p-type III-V compound semiconductor layer is formed on thereto after a n-type III-V compound semiconductor layer and a undoped III-V compound semiconductor layer and the p-type III-V compound semiconductor layer are formed on a substrate in sequence. Then, the first mask layer is removed after a emitter electrode structure is formed on the p-type III-V compound semiconductor layer. Next, the portion of the p-type III-V compound semiconductor layer and the undoped III-V compound semiconductor layer are removed to expose a first surface of the n-type III-V compound semiconductor layer after a second mask layer is formed on the emitter electrode layer and a portion of the p-type III-V compound semiconductor layer. Then, a plurality of electrodes are respectively formed on the first surface and the second surface and the emitter electrode structure after the second mask layer is removed to expose a ...

Semiconductor device and method of manufacturing the same

GROUP III HEMT AND CAPACITOR THAT SHARE STRUCTURAL FEATURES

A High Mobility Electron Transistor, HEMT, (10) and a capacitor (14, 18, 20, 22, 24) co-formed on an integrated circuit share at least one structural feature, thereby tightly integrating the two components. In one embodiment, the shared feature may be a 2DEG channel of the HEMT (10), which also functions in lieu of a base metal layer of a conventional capacitor (12). In another embodiment, a dialectic layer of the capacitor (14, 18, 20, 22, 24) may be formed in a passivation step of forming the HEMT (10). In another embodiment, a metal contact of the HEMT (10) (e.g., source, gate, or drain contact) comprises a metal layer or contact of the capacitor (22). In these embodiments, one or more processing steps required to form a conventional capacitor (12) are obviated by exploiting one or more processing steps already performed in fabrication of the HEMT (10).

HETEROJUNCTION BIPOLAR TRANSISTORS AND METHOD OF FABRICATING THE SAME

A semiconductor device comprises a heterojunction bipolar transistor (HBT). The HBT (104) comprises an emitter, a collector, and a base between the emitter and the collector. A width of the emitter is smaller than 100 nanometers, which is suitable for high speed applications.

DRIVING CIRCUIT, DRIVING IC, AND DRIVING SYSTEM

The present application relates to the technical field of electronic circuits, and provides a driving circuit, a driving IC, and a driving system. The driving circuit comprises a control module and a driving signal output module. The control module is electrically connected to the driving signal output module, and the driving signal output module is used to electrically connect to a device to be driven. The driving signal output module comprises at least two transistors, and the at least two transistors are formed by means of epitaxial growth on the same substrate. The control module is used to control the off states of the at least two transistors so as to control the working state of said device. The driving circuit, driving IC, and driving system provided by the present application have the advantages of achieving miniaturization and increasing the degree of integration.

Planar bipolar transistors including heterojunction transistors

A bipolar transistor is constructed to include a substrate, a collector layer epitaxial grown on the substrate and a base layer ion implanted in the collector layer. Next a further epitaxial layer is grown on the collector layer over the ion implanted base layer. A base contact region is ion implanted in this further epitaxial layer between the surface of this further layer and the base layer. The base contact region surrounds and defines an emitter in the further layer. A base ohmic contact is formed on the surface of the further layer in a location overlaying and contacting the base contact region. An emitter ohmic contact is also formed on the surface of the further layer in contact with the emitter. Additionally a collector ohmic contact is also formed on this same surface in a position isolated from the emitter by the base contact region. The collector ohmic makes an electrical contact with the collector by utilizing the further layer as a contact pathway.

Method of making buffer layers for III-V devices using solid phase epitaxy

A new III-IV buffer material is described which is produced by low temperature growth of III-V compounds by MBE that has unique and desirable properties, particularly for closely spaced, submicron gate length active III-V semiconductor devices, such as HEMT's, MESFET's and MISFET's. In the case of the III-V material, GaAs, the buffer is grown under arsenic stable growth conditions, at a growth rate of 1 micron/hour, and at a substrate temperature preferably in the range of 150 to about 300° C. The new material is crystalline, highly resistive, optically inactive, and can be overgrown with high quality III-V active layers.

Method of producing a two-dimensional electron gas semiconductor device

Disclosed is a method of producing a compound semiconductor device comprising an enhancement-mode transistor and a depletion-mode transistor, each of which has a heterojunction and utilizes a two-dimensional electron gas. The method of producing the device comprises the steps of: forming an undoped GaAs channel layer on a semi-insulating GaAs substrate; forming an N-type AlGaAs electron-supply layer so as to form the heterojunction; forming an N-type GaAs layer; forming an AlGaAs layer; selectively etching the AlGaAs layer to form a recess; performing an etching treatment using an etchant which can etch rapidly GaAs and etch slowly AlGaAs to form simultaneously grooves for gate electrodes of the enhancement-mode transistor and the depletion-mode transistor, the bottoms of the grooves being in the N-type AlGaAs layer and the distance between the bottoms being equal to the thickness of the AlGaAs layer; and forming simultaneously the gate electrodes in the grooves.

Method of fabricating optical device using multiple sacrificial spacer layers

The present invention is a method of fabricating an optical device using multiple sacrificial spacer layers. The first step in this process is to fabricate the underlying base structure and deposit an optical structure thereon. A facet is then created at the ends of the optical structure and alternating sacrificial and intermediate layers are fabricated on the device. A mask layer is deposited on the structure, with openings created in the layers to allow use of an etchant. User-defined portions of the spacer layers are subsequently removed with the etchant to create air gaps between the intermediate layers.

Semiconductor device

Method of producing a monolithically integrated millimeter wave circuit

A method and an arrangement for an integrated millimeter wave circuit wherein a Schottky diode and an HFET are produced in a quasi-planar arrangement from a semiconductor layer sequence. Due to the quasi-planar arrangement, the manufacturing process is simplified since particularly the contact regions of the Schottky diode and the HFET are produced simultaneously.

HEMT with etch-stop

A compound semiconductor device comprises an enhancement-mode transistor and a depletion-mode transistor, each of which has a heterojunction and utilizes a two-dimensional electron gas. The method of producing the device comprises the steps of: forming an undoped GaAs channel layer on a semi-insulating GaAs substrate; forming an N-type AlGaAs electron-supply layer so as to form the heterojunction; forming an N-type GaAs layer; forming an AlGaAs layer; selectively etching the AlGaAs layer to form a recess; performing an etching treatment using an etchant which can etch rapidly GaAs and etch slowly AlGaAs to form simultaneously grooves for gate electrodes of the enhancement-mode transistor and the depletion-mode transistor, the bottoms of the grooves being in the N-type AlGaAs layer and the distance between the bottoms being equal to the thickness of the AlGaAs layer; and forming simultaneously the gate electrodes in the grooves.

SEMICONDUCTOR DEVICE

A semiconductor device has a semiconductor substrate, and multiple first bipolar transistors on the first primary surface side of the semiconductor substrate. The first bipolar transistors have a first height between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. The semiconductor device further has at least one second bipolar transistor on the first primary surface side of the semiconductor substrate. The second bipolar transistor have a second height, greater than the first height, between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. Also, the semiconductor has a first bump stretching over the multiple first bipolar transistors and the at least one second bipolar transistor. 1. A semiconductor device comprising:a semiconductor substrate;a plurality of first bipolar transistors on a first primary surface side of the semiconductor substrate, the first bipolar transistors having a first height between an emitter layer and an emitter electrode in a direction perpendicular to the first primary surface;at least one second bipolar transistor on the first primary surface side of the semiconductor substrate, the second bipolar transistor having a second height, greater than the first height, between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface; anda first bump stretching over the plurality of first bipolar transistors and the second bipolar transistor.2. The semiconductor device according to claim 1 , further comprising:a plurality of third bipolar transistors on the first primary surface side of the semiconductor substrate, the third bipolar transistors having the second height between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface; anda second bump stretching over the plurality of third bipolar transistors.3. The semiconductor device according to ...

DEVICES RELATED TO BARRIER FOR METALLIZATION OF GALLIUM BASED SEMICONDUCTOR

Disclosed are structures and methods related to a barrier layer for metallization of a selected semiconductor such as indium gallium phosphide (InGaP). In some embodiments, the barrier layer can include tantalum nitride (TaN). Such a barrier layer can provide desirable features such as barrier functionality, improved adhesion of a metal layer, reduced diffusion, reduced reactivity between the metal and InGaP, and stability during the fabrication process. In some embodiments, structures formed in such a manner can be configured as an emitter of a gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) or an on-die high-value capacitance element.

Semiconductor device and power amplifier circuit

A semiconductor device includes a semiconductor substrate and first and second bipolar transistors. The semiconductor substrate includes first and second main surfaces opposing each other. The first bipolar transistor is formed on the first main surface of the semiconductor substrate and includes a first emitter layer. The second bipolar transistor is formed on the first main surface of the semiconductor substrate and includes a second emitter layer and a resistor layer. The resistor layer is stacked on the second emitter layer in a direction normal to the first main surface.

NITRIDE SEMICONDUCTOR DEVICE

A first transistor of the present invention includes a first nitride semiconductor layer, and a first gate electrode, a first source electrode and a first drain electrode formed thereon. The second transistor includes a second nitride semiconductor layer, and a second gate electrode, a second source electrode and a second drain electrode formed thereon. The source electrode is electrically connected to a lower region of a first region on the substrate, the second source electrode is electrically connected to a lower region of a second region on the substrate, and a first insulating region is disposed between a portion corresponding to the first region on the substrate and a portion corresponding to the second region on the substrate.

Method of transferring a semiconductor layer

The disclosed technology generally relates to manufacturing of semiconductor devices, and more particularly to manufacturing of a semiconductor device by transferring an active layer from a donor substrate. One aspect is a method of manufacturing a semiconductor device includes providing a donor wafer for transferring an active layer, comprising a group IV, a group III-IV or a group II-VI semiconductor material, to a handling wafer. The method includes forming the active layer on a sacrificial layer of the donor wafer, bonding the donor wafer to the handling wafer, and selectively etching the sacrificial layer to remove the donor wafer from the handling wafer, thereby leaving the active layer on the handling wafer.

Semiconductor device and semiconductor circuit including the device

A semiconductor device is disclosed. The semiconductor device includes a second conductive type substrate including a first first-conductive-type doping layer and a plurality of devices on the second conductive type substrate, wherein a first device of the devices includes a first nitride semiconductor layer on the first first-conductive-type doping layer, a second nitride semiconductor layer brought together with the first nitride semiconductor layer to form a first heterojunction interface, between the first first-conductive-type doping layer and the first nitride semiconductor layer, a first contact electrically connected to the first heterojunction interface, and a contact connector electrically connecting the first contact to the first first-conductive-type doping layer.

Epitaxial structure of N-face group III nitride, active device, and gate protection device thereof

The present invention relates to an epitaxial structure of N-face group III nitride, its active device, and its gate protection device. The epitaxial structure of N-face AlGaN/GaN comprises a silicon substrate, a buffer layer (C-doped) on the silicon substrate, an i-GaN (C-doped) layer on the buffer layer (C-doped), an i-AlyGaN buffer layer on the i-GaN (C-doped) layer, an i-GaN channel layer on the i-AlyGaN buffer layer, and an i-AlxGaN layer on the i-GaN channel layer, where x=0.1˜0.3 and y=0.05˜0.75. By connecting a depletion-mode (D-mode) AlGaN/GaN high electron mobility transistor (HEMT) to the gate of a p-GaN gate enhancement-mode (E-mode) AlGaN/GaN HEMT in device design, the gate of the p-GaN gate E-mode AlGaN/GaN HEMT can be protected under any gate voltage.

HIGH PERFORMANCE POWER MODULE

Junction high electron mobility transistor-heterojunction bipolar transistor monolithic microwave integrated circuit and method of fabrication

Method of generating active semiconductor structures by means of starting structures which have a two-dimensional charge carrier layer parallel to the surface

A novel unipolar transistor device has been realised starting from two-dimensional electron systems (2DES) in modulation-doped AlGaAS/GaAs heterostructures. A 600nm wide 1D channel is insulated laterally from 2DES regimes by 700nm wide deep mesa etched trenches. The conductivity in the quasi-one-dimensional channel can be tuned via the in-plane lateral-field effect of the adjacent 2DES-gates where the vacuum (or air) in the etched trenches serves as the dielectric. Room temperature operation is demonstrated yielding a 16µS transconductance corresponding to 160mS/mm 2D transconductance. ...

Halbleiterbauelement und Verfahren zur Herstellung des Halbleiterbauelements

A semiconductor device, such as a p-HEMT or a quantum well laser, includes a semiconductor base substrate (101 or 121) having a lattice constant and a surface; and a strained layer (3 or 24) grown on the surface of the semiconductor base substrate and comprising a semiconductor having a zinc-blende crystal structure with a lattice constant different from that of the semiconductor base substrate. The interface between the semiconductor base substrate and the strained layer is in a crystal plane which satisfies the relationship of (1 - * small Greek nu * cos 2 * small Greek alpha *)/cos * small Greek lambda * > 2(1 - * small Greek nu */4), where * small Greek nu * is the Poisson ratio, * small Greek alpha * is the angle between the Burgers vector and the dislocation line, and * small Greek lambda * is the angle between the Burgers vector and the direction in the interface, normal to the dislocation line, and the strained layer is epitaxially grown on the surface of the semiconductor base ...

HALBLEITERANORDNUNG MIT EINER INTEGRIERTEN SCHALTUNG UND VERFAHREN ZU DEREN HERSTELLUNG.

Komplementäre bipolar Halbleiteranordnung

Heterostruktur-Feldeffekttransistor mit schwerschmelzendem Gatter und Verfahren

Semiconductor assembly and method of manufacture

A monolithically integrated semiconductor assembly (100) is presented. The semiconductor assembly includes a substrate (110) including silicon (Si), and gallium nitride (GaN) semiconductor device (121-127) is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure (130) fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. The device may be a HEMT (high electron mobility transistor), a JFET (junction gate field effect transistor) or a MOSFET (metal-oxide-semiconductor field-effect transistor). The TVS supplies a overvoltage or surge voltage protection to prevent the GaN device entering avalanche mode.

PHOTO DETECTOR INTEGRATED CIRCUIT

III-V INTEGRATED CIRCUITS

A method of making a III-V semiconductor integrated circuit including at least two dissimilar devices such as an FET 10 and a diode 9 comprises using an etch inhibiting layer 5 such as Ga Al As to separate the devices. Initially a gallium arsenide diode 9 is formed on a substrate 2 by etching away gallium arsenide layers 6, 7 using an H2O2: NH4 OH etch until the inhibiting layer 5 is reached. Further etching of layers 3-5 then takes place using an HF : H2O etch to form FET 10. A polyimide coating is then patterned to leave a layer 14 on the diode before ohmic contacts 13a, b, c, gate contact 15 and Schottky contact 16 are formed. ...

Semiconductor device and method of fabricating semiconductor device

Coupon wafer and method of preparation thereof

A coupon wafer comprising a device coupon 110 for use in a micro-transfer printing process used to fabricate an optoelectronic device. The coupon wafer includes a wafer substrate 224 where the device coupon is attached to the wafer substrate via a dielectric tether 222. The coupon is attached to the wafer substrate by a release layer 220 formed from a sacrificial layer which is removed by etching prior to the transfer process. The tether may additionally comprise a photoresist layer (302, fig 3A).

III-V INTEGRATED CIRCUITS

Semiconductor devices

METHOD OF MANUFACTURING GAAS SEMICONDUCTOR DEVICE

A METHOD OF MANUFACTURING GaAs SEMICONDUCTOR DEVICE Amethod of manufacturing a GaAs semiconductor device of an E/D construction having a GaAs/AlGaAS heterojunction and utilizing two-dimensional electron gas, comprising the steps of forming a heterojunction semiconductor substrate and etching a portion of the substrate to provide a gate portion of a depletion-mode FET. When the substrate comprising a semi-insulating GaAs layer, an undoped GaAs, an N-type AlGaAs layer of an electron-supply layer, and a GaAs layer is formed, the GaAs layer is composed of a first GaAs layer, an etching stoppable AlGaAs layer, and a second GaAs layer, the first GaAs layer being formed on the N type GaAs layer. The etching for provision of the gate portion is carried out by a dry etching method using an etchant of CCl2F2 gas, so that the second GaAs layer can be etched but the AlGaAs layer cannot be etched. Thus, the thickness of the layers between a gate electrode of the depletion-mode FET and the GaAs/AlGaAs ...

INTEGRATED CIRCUITS EMPLOYING ION-BOMBARDED INP LAYERS

INTEGRATED CIRCUITS EMPLOYING ION-BOMBARDED InP LAYERS The property of materials in the InP system, whereby helium ion or deuteron bombarded p-type material becomes highly resistive but n-type material remains relatively conductive, is utilized to fabricate integrated circuits which include buried semiconductor interconnections or bus bars between devices.

GROUP III NITRIDE BASED FLIP-CHIP INTEGRATED CIRCUIT AND METHOD FOR FABRICATING

A flip-chip integrated circuit and method for fabricating the integrated circuit are disclosed. A method according to the invention comprises forming a plurality of active semiconductor devices on a wafer and separating the active semiconductor devices. Passive components and interconnections are formed on a surface of a circuit substrate and at least one conductive via is formed through the circuit substrate. At least one of the active semiconductor devices is flip-chip mounted on the circuit substrate with at least one of the bonding pads in electrical contact with one of the conductive via. A flip-chip integrated circuit according to the present invention comprises a circuit substrate having passive components and interconnections on one surface and can have a conductive via through it. An active semiconductor device is flip- chip mounted on the circuit substrate, one of the at least one via is in contact with one of the at least one the device~s terminal. The present invention is particularly ...

Manufacturing method of InP PIN photodetector integrated device

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

FIELD-EFFECT TRANSISTORS HAS MODE DEPLETION AND HAS JUST MODE ENRICHISSEMENTMONOLITHIQUEMENT AND PROCESS TO MANUFACTURE THEM

매칭 문턱전압을 갖는 집적회로 및 그 제조 방법

... 집적회로는 기판, 기판에 형성된 버퍼층, 버퍼층에 형성된 배리어층, 및 인핸스먼트 모드 장치를 디플리션 모드 장치로부터 절연하는 절연영역을 포함한다. 집적회로는 일 게이트 접촉 홈에 배치되는 인핸스먼트 모드 장치용 제1 게이트 접촉부와, 제2 게이트 접촉 홈에 배치되는 디플리션 모드 장치용 제2 게이트 접촉부를 더 포함한다.

A power semiconductor device with an auxiliary gate structure

The disclosure relates to power semiconductor devices in GaN technology. The disclosure proposes an integrated auxiliary (double) gate terminal and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device and a low-voltage auxiliary GaN device wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal. In other embodiments a pull-down network for the switching-off of the high threshold voltage GaN transistor is formed by additional auxiliary low-voltage ...

Integration of lateral and vertical quantum well transistors in the same epitaxial stack

An epitaxial stack (10) is provided that allows integration of both vertical and horizontal quantum effect devices. Epitaxial stack (10) allows fabrication of both quantum well resonant tunneling transistors (27) and Stark-effect transistors (34), thus allowing for circuit integration of different quantum effect devices in the same epitaxial stack.

High density gallium nitride devices using island topology

A Gallium Nitride (GaN) series of devicestransistors and diodes are disclosedthat have greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The devices also include a simpler and superior flip chip connection scheme and a means to reduce the thermal resistance. A simplified fabrication process is disclosed and the layout scheme which uses island electrodes rather than finger electrodes is shown to increase the active area density by two to five times that of conventional interdigitated structures. Ultra low on resistance transistors and very low loss diodes can be built using the island topology. Specifically, the present disclosure provides a means to enhance cost/effective performance of all lateral GaN structures.

Methods of manufacturing engineered substrate structures for power and RF applications

A method of manufacturing a substrate includes forming a support structure by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core in a first adhesion shell, encapsulating the first adhesion shell in a conductive shell, encapsulating the conductive shell in a second adhesion shell, and encapsulating the second adhesion shell in a barrier shell. The method also includes joining a bonding layer to the support structure, joining a substantially single crystalline silicon layer to the bonding layer, forming an epitaxial silicon layer by epitaxial growth on the substantially single crystalline silicon layer, and forming one or more epitaxial III-V layers by epitaxial growth on the epitaxial silicon layer.

Field effect transistor including strained germanium fins

In one example, a device includes a p-type field effect transistor region and n-type field effect transistor region. The p-type field effect transistor region includes at least one fin including strained germanium. The n-type field effect transistor region also includes at least one fin including strained germanium.

WURTZITE HETEROEPITAXIAL STRUCTURES WITH INCLINED SIDEWALL FACETS FOR DEFECT PROPAGATION CONTROL IN SILICON CMOS-COMPATIBLE SEMICONDUCTOR DEVICES

III-N semiconductor heterostructures including a raised III-N semiconductor structures with inclined sidewall facets are described. In embodiments, lateral epitaxial overgrowth favoring semi-polar inclined sidewall facets is employed to bend crystal defects from vertical propagation to horizontal propagation. In embodiments, arbitrarily large merged III-N semiconductor structures having low defect density surfaces may be overgrown from trenches exposing a (100) surface of a silicon substrate. III-N devices, such as III-N transistors, may be further formed on the raised III-N semiconductor structures while silicon-based transistors may be formed in other regions of the silicon substrate.

Semiconductor device, method for manufacturing the same, power supply, and high-frequency amplifier

A semiconductor device includes: a first transistor that includes a first gate electrode, a first source electrode, a first drain electrode, and a first nitride semiconductor laminate that includes a first electron transit layer and a first electron supply layer; a second transistor that includes a second gate electrode, a second source electrode, a second drain electrode, and a second nitride semiconductor laminate that includes a second electrode transit layer and a second electron supply layer, the second drain electrode being a common electrode that also serves as the first source electrode, the second electron transit layer having part that underlies the second gate electrode and that contains a p-type dopant; and a p-type-dopant-diffusion-blocking layer.

Extreme high mobility CMOS logic

A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.

Semiconductor device including a photosensitive resin covering at least a portion of a substrate having a via hole

A semiconductor device includes a substrate with a via hole. An electrode is formed on a surface of the substrate so that a portion of the electrode extends through the via hole. A photosensitive resin is formed over the surface so as to cover an aperture of the via hole.

GaAs Semiconductor device

This invention relates to a GaAs semiconductor device and more particularly to a GaAs static induction transistor integrated circuit which operates at a very high speed. Gallium arsenide has the features that the mobility of electrons is higher than that in silicon and that the band structure has a direct gap. The mobility of electrons in gallium arsenide is several times as high as that in silicon; this is very suitable for the manufacture of a semiconductor device of high-speed operation. Further, since gallium arsenide has the direct gap, the electron-hole recombination rate is high and the minority carrier storage effect is extremely small. By causing the recombination at the direct gap, light emission can be achieved more efficiently. Accordingly, a light receiving and emitting semiconductor device can be obtained through the use of gallium arsenide. As the propagation velocity of light is very fast, signal transfer between semiconductor chips can be achieved at ultra-high speed. By ...

Gate Drivers and Voltage Regulators for Gallium Nitride Devices and Integrated Circuits

Voltage stabilizing and voltage regulating circuits implemented in GaN HEMT technology provide stable output voltages suitable for use in applications such as GaN power transistor gate drivers and low voltage auxiliary power supplies for GaN integrated circuits. Gate driver and voltage regulator modules include at least one GaN D-mode HEMT (DHEMT) and at least two GaN E-mode HEMTs (EHEMTs) connected together in series, so that the at least one DHEMT operates as a variable resistor and the at least two EHEMTs operate as a Zener diode that limits the output voltage. The gate driver and voltage regulator modules may be implemented as a GaN integrated circuits, and may be monolithically integrated together with other components such as amplifiers and power HEMTs on a single die to provide a GaN HEMT power module IC. 1. A gate driver circuit for a gallium nitride (GaN) power high electron mobility transistor (HEMT) , comprising:an input point that receives an input voltage and an output point that outputs an output voltage to drive the power HEMT;a series circuit comprising at least one GaN D-mode HEMT (DHEMT) and at least first and second GaN E-mode HEMTs (EHEMTs); a gate of the DHEMT is connected to the source of the DHEMT;', 'a source of the first EHEMT is connected to a drain of the second EHEMT;', 'a gate of the first EHEMT is connected to the drain of the first EHEMT;', 'a source of the second EHEMT is connected to a circuit common; and', 'a gate of the second EHEMT is connected to the drain of the second EHEMT., 'wherein: a drain of the DHEMT is connect to the input point and a source of the DHEMT is connected to a drain of the first EHEMT and to the output point;'}2. The gate driver circuit of claim 1 , wherein the gate driver circuit provides voltage down-shifting and over-voltage protection to drive the GaN power HEMT.3. The gate driver circuit of claim 1 , wherein the at least one DHEMT operates as a variable resistor and the at least first and second EHEMTs ...

Vertical System Integration

The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.

MASKLESS PROCESS FOR FABRICATING GATE STRUCTURES AND SCHOTTKY DIODES

An integrated circuit structure and methodologies of forming same. In an embodiment, the integrated circuit structure includes a transistor gate structure in a first region of semiconductor material and a diode in a second region of the semiconductor material. The gate structure has a gate electrode of conductive material with a liner along sides and a bottom of the gate electrode. The gate electrode has a gate length less than a threshold dimension value. The diode includes a body of the conductive material in contact with the semiconductor material and includes the liner along sides of the body of conductive material. The body of conductive material has a lateral dimension greater than the threshold dimension value. The liner can include, for example, a gate dielectric and a diffusion barrier in some embodiments. In other embodiments, the liner is the gate dielectric (without any diffusion barrier).

Method of fabricating optical device using multiple sacrificial spacer layers

The present invention is a method of fabricating an optical device using multiple sacrificial spacer layers. The first step in this process is to fabricate the underlying base structure and deposit an optical structure thereon. A facet is then created at the ends of the optical structure and alternating sacrificial and intermediate layers are fabricated on the device. A mask layer is deposited on the structure, with openings created in the layers to allow use of an etchant. User-defined portions of the spacer layers are subsequently removed with the etchant to create air gaps between the intermediate layers.

III-N TRANSISTORS WITH ENHANCED BREAKDOWN VOLTAGE

Semiconductor device and manufacturing method therefor

Monolithically integrated pin diode and schottky diode circuit and method of fabricating same

A Microwave/Millimeter-wave Monolithic Integrated Circuit (MMIC) device (100) including PIN diode and Schottky diode circuits (102, 104) provides improved performance with a reduced cost of manufacture. The planar, glass-passivated, MMIC device is fabricated in silicon technology and includes mesa isolation (110,112) between the PIN diode (102) and the Schottky diode (104). The PIN and Schottky diodes include respective anode regions (122,116) having different thicknesses and resistivity for implementing the PIN and Schottky diode functions. Furthermore, the Schottky anode region (116) is formed relatively late in the process for fabricating the Si MMIC device to allow the Schottky anode region (116) to be formed in approximately the same plane as the PIN anode region (122) and to allow precise control of the relative thicknesses of the PIN and Schottky anode regions.

Fabrication of GaAs integrated circuits

A process for manufacturing selectively doped heterostructure field-effect transistors (SDHTs), a desired wafer structure for SDHT fabrication and a method for isolating SDHTs on the wafer are disclosed herein. The wafer has epitaxial layers grown on a substrate. The layers are: a buffer layer of GaAs, a first spacer layer of AlGaAs, a donor layer of AlGaAs, a second spacer layer of AlGaAs, a first cap layer of GaAs, an etch-stop layer of AlGaAs and a second cap layer of GaAs. A protective layer of AlGaAs may then be grown on the second cap layer to protect the second cap layer from contamination or damage. Also a superlattice may first be grown on the substrate. Openings are made in the protective layer and then in the second cap layer where enhancement type SDHTs are to be formed. The remaining protective layer is then etched along with the exposed etch-stop layer with a selective etch to expose the first cap layer and the second cap layer where respective enhancement-type SDHTs and depletion-type ...

Complementary bipolar semiconductor device

A complementary semiconductor device is disclosed which comprises a substrate (1) and four layer structure (2 ... 6) of pnpn provided on the substrate wherein the first three layers (2, 3, 5) constitute a pnp-type bipolar transistor and the second to fourth layers (3, 5, 6) constitute an npn-type bipolar transistor. According to the present invention, the pnp- and npn-type transistors can be produced by crystal growth of one time and thus production steps are simple and yield is remarkably improved. ...

Monolithic integrated device of PIN diode and field effect transistor and method of manufacturing the same

Method of manufacturing a semiconductor integrated circuit device

MONOLITHIC INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURING METHOD

PROBLEM TO BE SOLVED: To provide a monolithic integrated circuit device and its manufacturing method whereby an epitaxial layer is laminated on the same substrate for form transistors and diodes, without re-growing the epitaxial layer on the same substrate, low frequency noises are reduced and the manufacturing yield can be improved. SOLUTION: Gate electrodes 9 of epitaxial layer 1 HJFETs 22 having hetero- junctions are formed on the epitaxial layer 1 surface of the substrate 100, source electrodes 7 and drain electrodes 8 are buried in an n+ GaAs contact layer 2 on the epitaxial layer 1 with the gate electrodes 9 sandwiched thereamong. Cathode electrodes 6 of SBDs 21 are buried and formed in the contact layer 2 through an element isolation layer 10. An n- GaAs layer 4 is formed on regions near the cathode electrodes 6 on the contact layer 2 through an etching stopper layer 3, and anode electrodes 5 are buried and formed in the n- GaAs layer 4. COPYRIGHT: (C)2001,JPO ...

Sperrschicht-Feldeffekttransistor und dessen Herstellungsverfahren

Heterojunction-Verbundhalbleitervorrichtung und Verfahren zu ihrer Herstellung

Anordnung mit Supergitter-Struktur und Verfahren und Vorrichtung zu ihrer Herstellung.

Planare PIN-Diode und Verfahren zu deren Herstellung

Verfahren zur Herstellung von Quantenstrukturen, insbesondere von Quantenpunkten und Tunnelbarrieren sowie Bauelemente mit solchen Quantenstrukturen

SEMICONDUCTOR COMPONENT WITH DOUBLE GATE AND ITS MANUFACTURING PROCESSES

Vertical system integration

PHOTONIC-INTEGRATED-CIRCUIT FABRICATION PROCESS

An improved process for fabricating photonic circuits is disclosed. The inventive process starts with a growth of a base wafer comprising a stack of epitaxial layers of various materials. At least a portion of each of the material layers will ultimately be a functioning part of any of a number of devices which will form the PIC or will serve a role in at least one of the fabrication processing steps. Specific inventive processing steps are addressed to interconnecting passive waveguides, active devices, and grating filtering regions without the substantial optical discontinuities which appear in the prior art, and etching continuous waveguide mesas to different depths in different regions of the PIC so as to optimize the performance of each PIC device.

METHOD FOR MANUFACTURING JUST CIRCUITS HAS SEMICONDUCTOR

Method for realization of components semiconductors, in particular on GaAs or InP, with récupérationdu substrate by chemical way

Ce procédé est caractérisé par les étapes consistant à: (a) produire un substrat (1) en GaAs ou InP, (b) épitaxier sur ce substrat une couche intercalaire (2) en AlGaAs ou AlInAs riche en aluminium (au moins 40%), (c) épitaxier sur cette couche intercalaire une couche active (3) d'un matériau riche en aluminium, (d) réaliser, par gravure et métallisation, un ensemble de composants (5), (e) appliquer une couche protectrice (6) d'un matériau de passivation ou d'une résine photosensible, (f) graver sélectivement cette couche protectrice jusqu'à mettre à nu la couche intercalaire entre les composants, (g) fixer sur l'ensemble une plaque support commune (8) solidarisant mécaniquement les composants, et (h) dissoudre le matériau de la couche intercalaire par action chimique d'un solvant sur les régions (7) mises à nu, en laissant intacts les autres matériaux de manière à séparer, sans le dissoudre, le substrat d'avec les composants.

Semiconductor opto-electronic devices in particular for calculating machines

N-type layer sandwich formation - in 6-valent atom doped III-vV semiconductor by doping with 2-valent atom, forming interface

Opto-electronic device produced with integrated optics and method of production

Formation of a plug layer in a device with made up semiconductor and integrated circuit obtained

Un circuit intégré semiconducteur comporte un substrat (51), une couche tampon (52) placée sur le substrat et formée d'un matériau semiconducteur composé des groupes III-V qui contient du bore à un niveau de concentration appartenant à l'intervalle compris entre 0,001 et 0,1 en fraction molaire par rapport aux éléments du groupe III de ladite couche tampon, et une couche active (54) placée sur la couche tampon, où la couche active comporte plusieurs dispositifs à semiconducteur actifs.

비고유 반도체 기판들 상의 넓은 밴드 갭 트랜지스터들 및 그 제조 방법들

... 반도체 기판 상에 GaN 트랜지스터를 형성하는 기법들이 개시된다. 절연 층이 반도체 기판의 상부 상에 형성된다. Ⅲ-Ⅴ족 반도체 재료를 포함하는 트렌치 재료로 채워진 트렌치가 절연 층을 통해 형성되고, 반도체 기판 내로 연장된다. 트렌치 재료보다 낮은 결함 밀도를 갖는 Ⅲ-Ⅴ족 재료를 포함하는 채널 구조체가 트렌치에 인접하여 절연 층의 상부 상에 바로 형성된다. 소스 및 드레인이 채널 구조체의 반대측들 상에 형성되고, 게이트가 채널 구조체 상에 형성된다. 반도체 기판은 GaN 트랜지스터들 및 다른 트랜지스터들 모두가 형성될 수 있는 평면을 형성한다.

Electronic device and manufacturing method

Semiconductor wafer, method of producing semiconductor wafer, and electronic device

There is provided a compound semiconductor wafer that is suitably used as a semiconductor wafer to form a plurality of different types of devices such as an HBT and an FET thereon. The semiconductor wafer includes a first semiconductor, a carrier-trapping layer that is formed on the first semiconductor and has an electron-trapping center or a hole-trapping center, a second semiconductor that is epitaxially grown on the carrier-trapping layer and serves as a channel in which a free electron or a free hole moves, and a third semiconductor including a stack represented by n-type semiconductor/p-type semiconductor/n-type semiconductor or represented by p-type semiconductor/n-type semiconductor/p-type semiconductor, where the stack epitaxially grown on the second semiconductor.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer formed in contact with the first semiconductor layer, and a third semiconductor layer of a second conductivity type formed in contact with the second semiconductor layer, the first semiconductor layer provided with a first semiconductor region at a given distance from an interface between the first semiconductor layer and the second semiconductor layer, and an impurity concentration of the first semiconductor region higher than an impurity concentration of the first semiconductor layer except where the first semiconductor region is formed.

Semiconductor on insulator (xoi) for high performance field effect transistors

Semiconductor-on-insulator (XOI) structures and methods of fabricating XOI structures are provided. Single-crystalline semiconductor is grown on a source substrate, patterned, and transferred onto a target substrate, such as a Si/SiO 2 substrate, thereby assembling an XOI substrate. The transfer process can be conducted through a stamping method or a bonding method. Multiple transfers can be carried out to form heterogenous compound semiconductor devices. The single-crystalline semiconductor can be II-IV or III-V compound semiconductor, such as InAs. A thermal oxide layer can be grown on the patterned single crystalline semiconductor, providing improved electrical characteristics and interface properties. In addition, strain tuning is accomplished via a capping layer formed on the single-crystalline semiconductor before transferring the single-crystalline semiconductor to the target substrate.

Programmable Gate III-Nitride Power Transistor

A III-nitride semiconductor device which includes a charged floating gate electrode.

Integrated circuit and method of fabricating same

A method includes providing a substrate with at least one semiconducting layer. The method also includes forming a plurality of isolation barriers within the at least one semiconducting layer, thereby forming a plurality of device islands. The method further includes inserting a plurality of electronic devices into a portion of the at least one semiconducting layer such that each electronic device is substantially isolated from each other electronic device by the device islands.

Semiconductor device and manufacturing method thereof

In a transistor including a wide band gap semiconductor layer as a semiconductor layer, a wide band gap semiconductor layer is separated into an island shape by an insulating layer with passivation properties for preventing atmospheric components from permeating. The edge portion of the island shape wide band gap semiconductor layer is in contact with the insulating film; thus, moisture or atmospheric components can be prevented from entering from the edge portion of the semiconductor layer to the wide band gap semiconductor layer.

Monolithic Group III-V Power Converter

A power arrangement that includes a monolithically integrated III-nitride power stage having III-nitride power switches and III-nitride driver switches.

Highly scaled etsoi floating body memory and memory circuit

A floating body memory cell, memory circuit, and method for fabricating floating body memory cells. The floating body memory cell includes a bi-layer heterojunction having a first semiconductor coupled to a second semiconductor. The first semiconductor and the second semiconductor have different energy band gaps. The floating body memory cell includes a buried insulator layer. The floating body memory cell includes a back transistor gate separated from the second semiconductor of the bi-layer heterojunction by at least the buried insulated layer. The floating body memory cell also includes a front transistor gate coupled to the first semiconductor of the bi-layer heterojunction.

Integrated capacitive device and integrated analog digital converter comprising such a device

An integrated capacitive device includes an electrically conducting comb, at least some of whose teeth form first electrodes of capacitors, and electrically conducting fingers extending between the teeth of the comb so as to form second electrodes of the capacitors. The device includes a first finger-teeth set having a single reference finger forming a reference capacitor having a reference capacitive value, at least one second finger-teeth set including several fingers, the reference finger and the number of fingers of the second finger-teeth set or sets forming a geometric series with ratio two. At least one additional set includes a single additional finger forming, with at least one tooth of the comb, an additional capacitor having an additional capacitive value substantially equal to half the reference capacitive value.

Nitride electronic device and method for manufacturing the same

The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.

Semiconductor integrated circuit device

In a high-frequency circuit, it is necessary to block galvanically between active elements such as transistors and between an active element and an external terminal, and thus MIM capacitors or the like are used frequently. Among these MIM capacitors, one coupled to the external terminal is easily affected by static electricity from outside, which easily causes a problem of electro-static breakdown or the like. The present invention is a semiconductor integrated circuit device formed over a semi-insulating compound semiconductor substrate in which a first electrode of an MIM capacitor electrically coupled to an external pad is electrically coupled to the semi-insulating compound semiconductor substrate, and on the other side, a second electrode of the MIM capacitor is electrically coupled to the semi-insulating compound semiconductor substrate.

Semiconductor device and solid state relay using same

A semiconductor device includes one or more unipolar compound semiconductor element; and bypass semiconductor elements externally connected to the respective compound semiconductor elements in parallel. A turn-on voltage of the bypass semiconductor elements is smaller than a turn-on voltage of the compound semiconductor elements in the direction from the source to the drain.

Semiconductor structure

A semiconductor structure includes a barrier layer, a spacer structure, and a channel layer. The barrier layer includes a group III nitride. The spacer structure includes first and second aluminum nitride layers and an intermediate layer. The intermediate layer includes a group III nitride and is between the first and second aluminum nitride layers. The intermediate layer has a first free charge carrier density at an interface with the second aluminum nitride layer. The spacer structure is between the barrier layer and the channel layer. The channel layer includes a group III nitride and has a second free charge carrier density at an interface with the first aluminum nitride layer of the spacer structure. The first aluminum nitride layer, the intermediate layer, and the second aluminum nitride layer have layer thicknesses so the first free charge carrier density is less than 10% of the second free charge carrier density.

SEMICONDUCTOR DEVICE

A semiconductor device according to the present invention includes a substrate; a nitride semiconductor layer formed above the substrate and having a laminated structure including at least three layers; a heterojunction bipolar transistor formed in a region of the nitride semiconductor layer; and a field-effect transistor formed in a region of the nitride semiconductor layer, the region being different from the region in which the heterojunction bipolar transistor is formed. 119-. (canceled)20. A semiconductor device comprising:a substrate;a nitride semiconductor layer formed above the substrate and having a laminated structure including at least three layers;a heterojunction bipolar transistor formed in a first region of the nitride semiconductor layer;a field-effect transistor formed in a second region of the nitride semiconductor layer, the second region being different from the first region in which the heterojunction bipolar transistor is formed, wherein: a first nitride semiconductor layer formed above the substrate;', 'a second nitride semiconductor layer formed on the first nitride semiconductor layer;', 'a third nitride semiconductor layer formed on the second nitride semiconductor layer; and', 'an isolation region which separates each of the first nitride semiconductor layer and the second nitride semiconductor layer into the first region in which the heterojunction bipolar transistor is formed and the second region in which the field-effect transistor is formed, the first region and the second region being electrically isolated from each other,, 'the nitride semiconductor layer includesa collector electrode of the heterojunction bipolar transistor is electrically connected to the first nitride semiconductor layer in the first region,a base electrode of the heterojunction bipolar transistor is electrically connected to the second nitride semiconductor layer in the first region,an emitter electrode of the heterojunction bipolar transistor is electrically ...

Method and system for ultra miniaturized packages for transient voltage suppressors

A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The transient voltage suppressor (TVS) assembly includes a semiconductor die including a contact surface on a single side of the die, the die further including a substrate comprising a layer of at least one of an electrical insulator material, a semi-insulating material, and a first wide band gap semiconductor having a conductivity of a first polarity, at least a TVS device including a plurality of wide band gap semiconductor layers formed on the substrate; a first electrode coupled in electrical contact with the TVS device and extending to the contact surface, and a second electrode electrically coupled to the substrate extending to the contact surface.

ISOLATOR CIRCUIT AND SEMICONDUCTOR DEVICE

An isolator circuit capable of two-way electrical disconnection and a semiconductor device including the isolator circuit are provided. A data holding portion is provided in an isolator circuit without the need for additional provision of a data holding portion outside the isolator circuit, and data which is to be input to a logic circuit that is in an off state at this moment is stored in the data holding portion. The data holding portion may be formed using a transistor with small off-state current and a buffer. The buffer can include an inverter circuit and a clocked inverter circuit. 1. An isolator circuit comprising:a first terminal;a second terminal;a first transistor;a second transistor;a first buffer; anda second buffer,wherein the first terminal is electrically connected to one of a source and a drain of the first transistor,wherein the first terminal is electrically connected to an output terminal of the second buffer,wherein the other of the source and the drain of the first transistor is electrically connected to an input terminal of the first buffer,wherein an input terminal of the second buffer is electrically connected to one of a source and a drain of the second transistor,wherein the second terminal is electrically connected to an output terminal of the first buffer, andwherein the second terminal is electrically connected to the other of the source and the drain of the second transistor.2. The isolator circuit according to claim 1 , wherein an off-state current per micrometer of channel width in each of the first transistor and the second transistor is 1×10A or lower.3. The isolator circuit according to claim 1 , wherein each of the first buffer and the second buffer comprises an inverter circuit and a clocked inverter circuit.4. The isolator circuit according to claim 1 , wherein a channel formation layer of each of the first transistor and the second transistor is formed in an oxide semiconductor layer.5. A semiconductor device comprising:a logic ...

Semiconductor apparatus comprised of two types of transistors

A semiconductor apparatus that includes two types of transistors is disclosed. The first semiconductor chip includes the first semiconductor device of a type of GaAs-HEMT, while, the second semiconductor chip includes the second semiconductor device of another type of GaN-HEMT. The second semiconductor device is formed in a SiC substrate, and the first semiconductor chip is mounted in an inactive region of the SiC substrate.

Monolithic Group III-V and Group IV Device

According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in. the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a side-wall of the trench.

Process-compensated hbt power amplifier bias circuits and methods

The present disclosure relates to a system for biasing a power amplifier. The system can include a first die that includes a power amplifier circuit and a passive component having an electrical property that depends on one or more conditions of the first die. Further, the system can include a second die including a bias signal generating circuit that is configured to generate a bias signal based at least in part on measurement of the electrical property of the passive component of the first die.

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICE

According to example embodiments, a semiconductor device may include a high electron mobility transistor (HEMT) on a first region of a substrate, and a diode on a second region of the substrate. The HEMT may be electrically connected to the diode. The HEMT and the diode may be formed on an upper surface of the substrate such as to be spaced apart from each other in a horizontal direction. The HEMT may include a semiconductor layer. The diode may be formed on another portion of the substrate on which the semiconductor layer is not formed. The HEMT and the diode may be cascode-connected to each other. 1. A semiconductor device comprising:a substrate;a high electron mobility transistor (HEMT) on a first region of the substrate, the HEMT including a semiconductor layer; anda diode on a second region of the substrate,the diode being electrically connected to the HEMT.2. The semiconductor device of claim 1 , wherein the HEMT includes:a source electrode electrically connected to a first region of the semiconductor layer;a drain electrode electrically connected to a second region of the semiconductor layer; anda gate electrode on the semiconductor layer between the source electrode and the drain electrode.3. The semiconductor device of claim 2 , wherein an upper surface of the substrate contacts one of the source electrode and the drain electrode.4. The semiconductor device of claim 3 , whereinthe source electrode is spaced apart from the substrate, andthe drain electrode contacts the substrate and the semiconductor layer.5. The semiconductor device of claim 1 , wherein the semiconductor layer includes a channel layer and a channel supply layer.6. The semiconductor device of claim 1 , wherein the semiconductor layer includes a gallium nitride (GaN)-based material.7. The semiconductor device of claim 1 , wherein the diode is a Schottky diode.8. The semiconductor device of claim 7 , wherein the diode includes:an anode that forms a Schottky contact with the substrate; anda ...

SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, METHOD FOR PRODUCING SEMICONDUCTOR WAFER, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

There is provided a semiconductor device including: a first source and a first drain of a first-channel-type MISFET formed on a first semiconductor crystal layer, which are made of a compound having an atom constituting the first semiconductor crystal layer and a nickel atom, a compound having an atom constituting the first semiconductor crystal layer and a cobalt atom, or a compound having an atom constituting the first semiconductor crystal layer, a nickel atom, and a cobalt atom; and a second source and a second drain of a second-channel-type MISFET formed on a second semiconductor crystal layer, which are made of a compound having an atom constituting the second semiconductor crystal layer and a nickel atom, a compound having an atom constituting the second semiconductor crystal layer and a cobalt atom, or a compound having an atom constituting the second semiconductor crystal layer, a nickel atom, and a cobalt atom. 1. A semiconductor device comprising:a base wafer;a first semiconductor crystal layer positioned above the base wafer;a second semiconductor crystal layer positioned above a partial area of the first semiconductor crystal layer;a first MISFET having a channel formed in a part of an area of the first semiconductor crystal layer above which the second semiconductor crystal layer does not exist and having a first source and a first drain; anda second MISFET having a channel formed in a part of the second semiconductor crystal layer and having a second source and a second drain, whereinthe first MISFET is a first-cannel-type MISFET and the second MISFET is a second-channel-type MISFET, the second-channel-type being different from the first-channel-type,the first source and the first drain are made of a compound having an atom constituting the first semiconductor crystal layer and a nickel atom, a compound having an atom constituting the first semiconductor crystal layer and a cobalt atom, or a compound having an atom constituting the first semiconductor ...

Over-voltage protection of gallium nitride semiconductor devices

A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon carbide (SiC), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR CIRCUIT INCLUDING THE SAME

A semiconductor device is disclosed. The semiconductor device includes a substrate and a plurality of devices on the substrate, wherein a first device of the devices includes a first nitride semiconductor layer on the substrate, a second nitride semiconductor layer brought together with the first nitride semiconductor layer to form a first heterojunction interface, between the substrate and the first nitride semiconductor layer, a third nitride semiconductor layer brought together with the second nitride semiconductor layer to form a second heterojunction interface, between the substrate and the second nitride semiconductor layer, and a first contact electrically connected to the first and second heterojunction interfaces. 1. A semiconductor device , comprising:a substrate; anda plurality of devices on the substrate,wherein a first device of the devices comprises:a first nitride semiconductor layer on the substrate;a second nitride semiconductor layer brought together with the first nitride semiconductor layer to form a first heterojunction interface, between the substrate and the first nitride semiconductor layer;a third nitride semiconductor layer brought together with the second nitride semiconductor layer to form a second heterojunction interface, between the substrate and the second nitride semiconductor layer; anda first contact configured to be electrically connected to the first and second heterojunction interfaces.2. The semiconductor device according to claim 1 , wherein the first device further comprises a fourth nitride semiconductor layer brought together with the third nitride semiconductor layer to form a third heterojunction interface claim 1 , between the37-. (canceled)8. The semiconductor device according to claim 2 , wherein a second device of the devices comprises:a fifth nitride semiconductor layer on the substrate;a sixth nitride semiconductor layer brought together with the fifth nitride semiconductor layer to form a fourth heterojunction ...

Creation of wide band gap material for integration to soi thereof

Devices and methods for forming a device are presented. The method for forming the device includes providing a support substrate having first crystal orientation. A trap rich layer is formed on the support substrate. An insulator layer is formed over a top surface of the trap rich layer. The method further includes forming a top surface layer having second crystal orientation on the insulator layer. The support substrate, the trap rich layer, the insulator layer and the top surface layer correspond to a substrate and the substrate is defined with at least first and second device regions. A transistor is formed in the top surface layer in the first device region and a wide band gap device is formed in the second device region.

SEMICONDUCTOR DEVICE AND RELATED MANUFACTURING METHOD

A semiconductor device may include a substrate, an n-channel field-effect transistor positioned on the substrate, and a p-channel field-effect transistor positioned on the substrate. The n-channel field-effect transistor may include an n-type silicide source portion, an n-type silicide drain portion, and a first n-type channel region. The first n-type channel region may be positioned between the n-type silicide source portion and the n-type silicide drain portion and may directly contact each of the n-type silicide source portion and the n-type silicide drain portion. 1. A method for manufacturing a semiconductor device , the method comprising:preparing a substrate;providing an n-channel field-effect transistor positioned on the substrate, wherein the n-channel field-effect transistor comprises an n-type silicide source portion, an n-type silicide drain portion, and a first n-type channel region, and wherein the first n-type channel region is positioned between the n-type silicide source portion and the n-type silicide drain portion and directly contacts each of the n-type silicide source portion and the n-type silicide drain portion; andproviding a p-channel field-effect transistor positioned on the substrate.2. The method of claim 1 , wherein the first n-type channel region is a first potion of a fin structure claim 1 , wherein the p-channel field-effect transistor comprises a second n-type channel region claim 1 , wherein the second n-type channel region is a second portion of the fin structure claim 1 , and wherein the fin structure is formed of or comprises at least one of germanium claim 1 , silicon-germanium claim 1 , and a III-V compound semiconductor material.3. The method of claim 2 , wherein a doping concentration value of the second n-type channel region is less than a doping concentration value of the first n-type channel region.4. The method of claim 1 , wherein a doping concentration value at a gate-channel interface of the first n-type channel region ...

CO-INTEGRATION OF HIGH CARRIER MOBILILTY PFET AND NFET DEVICES ON THE SAME SUBSTRATE USING LOW TEMPERATURE CONDENSATION

Embodiments of the invention are directed to fin-based field effect transistor (FET) devices formed on a substrate. In a non-limiting example, the devices a first fin formed in a p-type FET (PFET) region of the substrate, wherein the first fin includes a top region, a central region, and a bottom region. The central region of the first fin includes an epitaxial first material in-situ doped with a first type of semiconductor material at a first concentration level. The top region of the first fin includes the epitaxial first material in-situ doped with the first type of semiconductor material at the first concentration level, along with an anneal-induced second concentration level of the first type of semiconductor material. A final concentration level of the first type of semiconductor material in the top region includes the first concentration level and the second concentration level. 1. Fin-based field effect transistor (FET) devices formed on a substrate , the devices comprising:a first fin formed in a p-type FET (PFET) region of the substrate, wherein the first fin comprises a top region, a central region, and a bottom region;wherein the central region of the first fin comprises an epitaxial first material in-situ doped with a first type of semiconductor material at a first concentration level; the epitaxial first material in-situ doped with the first type of semiconductor material at the first concentration level; and', 'an anneal-induced second concentration level of the first type of semiconductor material;, 'wherein the top region of the first fin compriseswherein a final concentration level of the first type of semiconductor material in the top region comprises the first concentration level and the second concentration level.2. The devices of claim 1 , wherein the final concentration level is greater than or equal to about 50%.3. The devices of claim 2 , wherein the first concentration level is less than or equal to about 30%; and4. The devices of claim 3 , ...

SCHOTTKY DIODE STRUCTURES AND INTEGRATION WITH III-V TRANSISTORS

Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed. 1. A semiconductor device , comprising:a Schottky stack including a first layer above a substrate, and a second layer above the first layer, wherein the first layer includes an III-V material, and the second layer is a polarization layer;a Schottky anode in contact with the second layer to form a Schottky barrier at an interface between the Schottky anode and the second layer of the Schottky stack; anda cathode through the second layer of the Schottky stack and in contact with the first layer of the Schottky stack, wherein a current is to flow from the Schottky anode through the Schottky barrier in a vertical direction orthogonal to a surface of the substrate, and vertically through the second layer to the first layer of the Schottky stack, following the first layer of the Schottky stack in a horizontal direction to the cathode.2. The semiconductor device of claim 1 , wherein the Schottky anode is partially embedded into the second layer of the Schottky stack.3. The semiconductor device of claim 1 , wherein the second layer of the Schottky stack includes a material selected from the group ...

High-Dielectric Constant Capacitor Structures on III-V Substrates

A semiconductor structure includes a III-V semiconductor structure; a first electrode; a first barrier layer disposed over the first electrode; a first adhesion layer disposed over the first electrode; a first passivation layer disposed over the first adhesion layer; a dielectric layer disposed over the first passivation layer; a second passivation layer disposed over the dielectric layer; a second adhesion layer disposed over the second passivation layer; a second barrier layer disposed over the second adhesion layer; and a second electrode disposed over the second barrier layer.

DIELECTRIC LINING LAYERS FOR SEMICONDUCTOR DEVICES

Solid-state assemblies including dielectric lining layers having localized charges are provided. Processes to form the solid-state assemblies also are provided. The solid-state assemblies can included in CMOS transistors, where first dielectric lining layers having localized charges of positive polarity can be adjacent to the PMOS member and a second dielectric lining layers having localized charges of positive polarity can be adjacent to an NMOS member. The first dielectric lining layers can be adjacent to a first gate electrode of the CMOS transistor, and the second dielectric lining can be adjacent to a second gate electrode of the CMOS transistor. The first dielectric lining layers and the second dielectric lining layers can improve, at least in part, the performance of the CMOS transistor by attracting mobile carriers into respective transport channels of the PMOS member and the NMOS member. 125-. (canceled)26. A solid assembly , comprising:a carrier-doped semiconductor layer including mobile charges of a first polarity;a dielectric layer including localized charges of a second polarity opposite the first polarity; andan electrode member adjacent to the dielectric layer and further adjacent to the carrier-doped semiconductor layer.27. The solid assembly of claim 26 , wherein the carrier-doped semiconductor layer comprises an n-type III-V semiconductor compound claim 26 , and wherein the second polarity is positive polarity.28. The solid assembly of claim 26 , wherein the carrier-doped semiconductor layer comprises a p-type III-V semiconductor compound claim 26 , and wherein the second polarity is negative polarity.29. The solid assembly of claim 26 , wherein the dielectric layer comprises a low-K material comprising oxygen claim 26 , nitrogen claim 26 , carbon claim 26 , or silicon.30. The solid assembly of claim 26 , wherein the localized charges of the second polarity are arranged within the dielectric layer to an average charge density in a range of 10cmto ...

Gate Drivers and Voltage Regulators for Gallium Nitride Devices and Integrated Circuits

Voltage stabilizing and voltage regulating circuits implemented in GaN HEMT technology provide stable output voltages suitable for use in applications such as GaN power transistor gate drivers and low voltage auxiliary power supplies for GaN integrated circuits. Gate driver and voltage regulator modules include at least one GaN D-mode HEMT (DHEMT) and at least two GaN E-mode HEMTs (EHEMTs) connected together in series, so that the at least one DHEMT operates as a variable resistor and the at least two EHEMTs operate as a Zener diode that limits the output voltage. The gate driver and voltage regulator modules may be implemented as a GaN integrated circuits, and may be monolithically integrated together with other components such as amplifiers and power HEMTs on a single die to provide a GaN HEMT power module IC. 1. A gate driver circuit for a gallium nitride (GaN) power transistor , comprising:an input point that receives an input voltage and an output point that outputs an output voltage to drive the GaN power transistor;a series circuit comprising at least one GaN D-mode HEMT (DHEMT) with gate-to-source connection and at least first to fourth GaN E-mode HEMTs (EHEMTs) each with drain-to-gate connection;an output EHEMT having a drain connected to the input point and a source connected to the output point;wherein a drain of the DHEMT is connected to the input point and a source of the DHEMT is connected to a drain of the first EHEMT and to a gate of the output EHEMT;wherein a source of the first EHEMT is connected to a drain of the second EHEMT, a source of the second EHEMT is connected to a drain of the third EHEMT, a source of the third EHEMT is connected to a drain of the fourth EHEMT, and a source of the fourth EHEMT is connected to a circuit common.2. The gate driver circuit of claim 1 , wherein the output EHEMT comprises a source follower amplifier.3. The gate driver circuit of claim 1 , further comprising an amplifier;wherein the output point is connected to ...

Iii-v compound semiconductor device having metal contacts and method of making the same

A semiconductor device comprises a semiconductor substrate; a channel layer of at least a first III-V semiconductor compound above the semiconductor substrate; a gate stack structure above a first portion of the channel layer; a source region and a drain region comprising at least a second III-V semiconductor compound above a second portion of the channel layer; and a first metal contact structure above the S/D regions comprising a first metallic contact layer contacting the S/D regions. The first metallic contact layer comprises at least one metal-III-V semiconductor compound.

Schottky barrier diode formed with nitride semiconductor substrate

An SBD is obtained by forming, on a front surface of a substrate in which a first nitride semiconductor layer and a second nitride semiconductor layer are laminated, an anode electrode configured to make Schottky contact and a cathode electrode configured to make Ohmic contact. The anode electrode is made to have a mixture of a portion that is in direct contact with the second nitride semiconductor layer and a portion that is in contact with the second nitride semiconductor layer via a fourth nitride semiconductor layer and a third nitride semiconductor layer. Using a p-type nitride semiconductor as the fourth layer makes it possible to suppress the leakage current. Using, as the third layer, a nitride semiconductor that is wider in band gap than the second nitride semiconductor layer makes it possible to keep down the lowest value of forward voltage at which a forward current flows.

EPITAXIAL STRUCTURE OF N-FACE GROUP III NITRIDE, ACTIVE DEVICE, AND METHOD FOR FABRICATING THE SAME WITH INTEGRATION AND POLARITY INVERSION

The present invention provides an epitaxial structure of N-face group III nitride, its active device, and the method for fabricating the same. By using a fluorine-ion structure in device design, a 2DEG in the epitaxial structure of N-face group III nitride below the fluorine-ion structure will be depleted. Then the 2DEG is located at a junction between a i-GaN channel layer and a i-AlGaN layer, and thus fabricating GaN enhancement-mode AlGaN/GaN high electron mobility transistors (HEMTs), hybrid Schottky barrier diodes (SBDs), or hybrid devices. After the fabrication step for polarity inversion, namely, generating stress in a passivation dielectric layer, the 2DEG will be raised from the junction between the i-GaN channel layer and the i-AlGaN layer to the junction between the i-GaN channel layer and the i-AlGaN layer. 1. An epitaxial structure of N-face AlGaN/GaN , comprising:a substrate;a buffer layer (C-doped) layer on the substrate;a carbon doped (C-doped) i-GaN layer on the buffer layer (C-doped);{'sub': 'y', 'an i-AlGaN layer, located on said C-doped i-GaN layer;'}{'sub': 'y', 'an i-GaN channel layer, located on said i-AlGaN layer;'}{'sub': 'x', 'an i-AlGaN layer, located on said i-GaN channel layer;'}{'sub': 'x', 'a fluorine-ion structure, located in said i-AlGaN layer; and'}a first gate dielectric layer, located on said fluorine-ion structure;where x=0.1˜0.3 and y=0.05˜0.75.2. The structure of claim 1 , wherein an i-AlGaN grading buffer layer is further disposed between said C-doped i-GaN layer and said i-AlGaN layer and z=0.01˜0.75.3. The structure of claim 1 , wherein the two-dimensional electron gas in said i-GaN channel layer is depleted below said fluorine-ion structure and the two-dimensional electron gas is located at the junction between said i-GaN channel layer and said i-AlGaN layer.4. A method for fabricating an enhancement-mode N-face AlGaN/GaN high electron mobility transistor with polarity inversion using an epitaxial structure of N-face AlGaN/ ...

Compound semiconductor monolithic integrated circuit device with transistors and diodes

A compound semiconductor monolithically integrated circuit device with transistors and diodes comprises a compound semiconductor substrate, a transistor epitaxial structure, a transistor upper structure, a first diode, and a second diode. The transistor epitaxial structure forms on the compound semiconductor substrate. The first diode, the second diode, and the transistor upper structure form on a first part, a second part, and a third part of the transistor epitaxial structure, respectively. The transistor upper structure and the third part of the transistor epitaxial structure form a transistor. The first diode comprises a first part of an n-type doped epitaxial layer, a first part of a first intrinsic epitaxial layer, a first electrode, and a second electrode. The second diode comprises a second part of the n-type doped epitaxial layer, a second part of the first intrinsic epitaxial layer, a first electrode, and a second electrode.

INTEGRATED ENHANCEMENT MODE AND DEPLETION MODE DEVICE STRUCTURE AND METHOD OF MAKING THE SAME

A method of forming an integrated circuit can include forming a heterostructure over a substrate structure, wherein the given substrate structure comprises a given semiconductor material. The method can include etching a castellated channel region in an e-mode device area of the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, the ridge channels comprising another semiconductor material. The method can also include forming an isolation region on the heterostructure to electrically isolate the e-mode device area from a d-mode device area of the heterostructure. The method can further include forming a mask with an opening that defines a castellated gate opening overlying the castellated channel region and the mask defines an opening overlaying a single planar gate overlying the d-mode device area of the heterostructure. The method can also include performing a contact fill with conductive material to form a castellated gate contact. 1. A method of forming an integrated circuit comprising:forming a heterostructure over a substrate structure, wherein the substrate structure comprises a given semiconductor material;etching a castellated channel region in an e-mode device area of the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, the ridge channels comprising another semiconductor material;forming an isolation region on the heterostructure to electrically isolate the e-mode device area from a d-mode device area of the heterostructure;forming a mask with an opening that defines a castellated gate opening overlying the castellated channel region and the mask defines an opening overlaying a single planar gate overlying the d-mode device area of the heterostructure;performing a contact fill with conductive material to form a castellated gate contact that extends across the castellated channel region and substantially surrounds each of the plurality of ridge ...

SEMICONDUCTOR DEVICE

To enhance electromigration resistance of an electrode.

Field effect transistor (fet) structure with integrated gate connected diodes

A structure having: a plurality of field effect transistors (FETs) connected between a common input and a common output, each one of the field effect transistors comprises: a source region, a drain region, and a gate electrode for controlling carriers through a channel region of a transistor region of the structure between the source region and the drain region; a plurality of diodes, each one of the diodes being associated with a corresponding one of the plurality of FETs, each one of the diodes having an electrode in Schottky contact with a diode region of the corresponding one of the FETs. The gate electrode and the diode electrode extend along parallel lines. The source region, the drain region, the channel region, and a diode region having therein the diode are disposed along a common line.

Semiconductor Device and Method for Forming the Semiconductor Device

A semiconductor device and a method for forming the semiconductor device. The semiconductor device includes: a unipolar component at least including a first epitaxial layer and a first substrate; and a bypass component at least including a second epitaxial layer and a second substrate; the unipolar component and the bypass component are connected in parallel; a difference of a thickness of the unipolar component and a thickness of the bypass component is lower than or equal to a predetermined value. 1. A semiconductor device , comprising:a unipolar component at least comprising a first epitaxial layer and a first substrate, wherein a source electrode of the unipolar component is an aluminum silicon type element; anda bypass component at least comprising a second epitaxial layer and a second substrate, wherein a barrier metal of the bypass component is a titanium or molybdenum type element; the unipolar component and the bypass component are connected in parallel;wherein a difference of a first thickness and a second thickness is lower than or equal to 10% and higher than or equal to −10%;the first thickness is an addition of the thickness of the first epitaxial layer and the thickness of the first substrate, the second thickness is an addition of the thickness of the second epitaxial layer and the thickness of the second substrate.2. The semiconductor device according to claim 1 , wherein the unipolar component and the bypass component comprise silicon carbide material.3. (canceled)4. The semiconductor device according to claim 1 , wherein a difference of a first concentration and a second concentration is lower than or equal to 10% and higher than or equal to −10%;the first concentration is a concentration of carriers in the first epitaxial layer, and the second concentration is a concentration of carriers in the second epitaxial layer.5. (canceled)6. A method for forming a semiconductor device claim 1 , comprising:providing a unipolar component at least comprising ...

HETEROLITHIC MICROWAVE INTEGRATED CIRCUITS INCLUDING GALLIUM-NITRIDE DEVICES ON HIGHLY DOPED REGIONS OF INTRINSIC SILICON

Apparatus and methods relating to heterolithic microwave integrated circuits HMICs are described. An HMIC can include different semiconductor devices formed from different semiconductor systems in different regions of a same substrate. An HMIC can also include bulk regions of low-loss electrically-insulating material extending through the substrate and located between the different semiconductor regions. Passive RF circuit elements can be formed on the low-loss electrically-insulating material.

Plasma protection diode for a hemt device

A silicon substrate having a III-V compound layer disposed thereon is provided. A diode is formed in the silicon substrate through an ion implantation process. The diode is formed proximate to an interface between the silicon substrate and the III-V compound layer. An opening is etched through the III-V compound layer to expose the diode. The opening is filled with a conductive material. Thereby, a via is formed that is coupled to the diode. A High Electron Mobility Transistor (HEMT) device is formed at least partially in the III-V compound layer.

Semiconductor device

Provided is a semiconductor device including: a DC/DC converter circuit, wherein the DC/DC converter circuit includes a transistor of a normally-off type, having a first drain electrode connected to an input terminal and a first source electrode connected to an output terminal, which is formed in a first compound semiconductor substrate having a two-dimensional electron gas layer, and a transistor having a second drain electrode connected to the first source electrode and a grounded second source electrode.

Integrated ESD Protection Circuit for GaN Based Device

The present disclosure relates to an electrostatic discharge (ESD) protection circuit integrated with a gallium nitride (GaN) based transistor and configured to clamp a gate input voltage of the gallium nitride (GaN) based transistor during an ESD surge event, and associated methods. In some embodiments, the ESD protection circuit includes a first ESD protection stage and a second ESD protection stage connected between a gate terminal and a source terminal of the GaN based transistor. The first ESD protection stage includes a first plurality of GaN based gate-to-source shorted transistors connected in series and further connected to a first terminal of a first resistor. The second ESD protection stage is connected to the first ESD protection stage in parallel. The second ESD protection stage comprises a first GaN based shunt transistor having a gate terminal connected to the first terminal of the first resistor. 1. An electrostatic discharge (ESD) protection circuit integrated with a gallium nitride (GaN) based transistor , the ESD protection circuit comprising:a first ESD protection stage connected between a gate terminal and a source terminal of the GaN based transistor and comprising a first plurality of GaN based gate-to-source shorted transistors connected in series and further connected to a first terminal of a first resistor; anda second ESD protection stage connected to the first ESD protection stage in parallel and comprising a first GaN based shunt transistor having a gate terminal connected to the first terminal of the first resistor.2. The ESD protection circuit of claim 1 , wherein the GaN based transistor is an enhancement mode high electron mobility transistor (E-HEMT).3. The ESD protection circuit of claim 1 , wherein the first GaN based shunt transistor has a first S/D terminal connected to the gate terminal of the GaN based transistor.4. The ESD protection circuit of claim 1 , wherein the first GaN based shunt transistor has a second S/D terminal ...

Enhancement Mode Field-Effect Transistor with a Gate Dielectric Layer Recessed on a Composite Barrier Layer for High Static Performance

An enhancement mode field-effect transistor (E-FET) for high static performance is provided. A composite barrier layer comprises a lower barrier layer and an upper barrier layer. The upper barrier layer is arranged over the lower barrier layer and has a different polarization than the lower barrier layer. Further, the composite barrier layer comprises a gate opening. A channel layer is arranged under the composite barrier layer, such that a heterojunction is defined at an interface between the channel layer and the composite barrier layer. A gate dielectric layer is arranged over the composite barrier layer and within the gate opening. A gate electrode is arranged over the gate dielectric layer. A method for manufacturing the E-FET is also provided. 1. An enhancement mode transistor comprising:a composite barrier layer comprising a lower barrier layer and an upper barrier layer, wherein the upper barrier layer is arranged over the lower barrier layer and has a different polarization than the lower barrier layer, and wherein the composite barrier layer further comprises a gate opening;a channel layer arranged under the composite barrier layer, such that a heterojunction is defined at an interface between the channel layer and the composite barrier layer;a gate dielectric layer arranged over the composite barrier layer and within the gate opening;a gate electrode arranged over the gate dielectric layer;a source electrode arranged to a first side of the gate dielectric; anda drain electrode arranged to a second side of the gate dielectric;wherein the gate opening has a first length between the first side of the gate dielectric and a first side of the upper barrier layer nearest the first side of the gate dielectric, and wherein the gate opening has a second length between a second side of the gate dielectric and a second side of the upper barrier layer nearest the second side of the gate dielectric, the second length differing from the first length.2. The enhancement ...

SEMICONDUCTOR DEVICE

A semiconductor device includes an enhancement mode high electron mobility transistor (HEMT) with an active region and an isolation region. The HEMT includes a substrate, a group III-V body layer, a group III-V barrier layer, a group III-V gate structure and a group III-V patterned structure. The group III-V body layer and the group III-V barrier layer are disposed on the substrate. The group III-V gate structure is disposed on the group III-V barrier layer within the active region. The group III-V patterned structure is disposed on the group III-V barrier layer within the isolation region. The composition of the group III-V patterned structure is the same as the composition of the group III-V gate structure. 1. A semiconductor device , comprising: a substrate;', 'a group III-V body layer and a group III-V barrier layer disposed on the substrate;', 'a group III-V gate structure disposed on the group III-V barrier layer in the active region; and', 'a group III-V patterned structure disposed on the group III-V barrier layer in the isolation region, wherein a composition of the group III-V patterned structure is the same as a composition of the group III-V gate structure., 'an enhancement mode high electron mobility transistor comprising an active region and an isolation region, wherein the enhancement mode high electron mobility transistor comprises2. The semiconductor device according to claim 1 , wherein a bottom surface of the group III-V gate structure is aligned with a bottom surface of the group III-V patterned structure.3. The semiconductor device according to claim 1 , wherein the composition of the group III-V gate structure and the composition of the group III-V patterned structure are p-type GaN or p-type AlGaN.4. The semiconductor device according to claim 1 , further comprising an etch stop layer disposed between the group III-V patterned structure and the group III-V barrier layer.5. The semiconductor device of claim 1 , further comprising an etch mask ...

COMPOUND SEMICONDUCTOR DEVICES HAVING BURIED RESISTORS FORMED IN BUFFER LAYER

Structures and methods are provided for fabricating a semiconductor device (e.g., III-V compound semiconductor device) having buried resistors formed within a buffer layer of the semiconductor device. For instance, a semiconductor device includes a buffer layer disposed on a substrate, a channel layer disposed on the buffer layer, and a buried resistor disposed within the buffer layer. The buffer and channel layers may be formed of compound semiconductor materials such as III-V compound semiconductor materials. Utilizing the buffer layer of a compound semiconductor structure to form buried resistors provides a space-efficient design with increased integration density since the resistors do not have to occupy a large amount of space on the active surface of a semiconductor integrated circuit chip. 1. A method , comprising:forming a buffer layer on a substrate;forming a channel layer on the buffer layer; andforming a buried resistor within the buffer layer.2. The method of claim 1 , further comprising forming a contact plug through the channel layer to the buried resistor in the buffer layer.3. The method of claim 2 , wherein the contact plug and the buried resistor are formed of a same material.4. The method of claim 2 , further comprising forming an ohmic contact on a surface of the contact plug exposed through the channel layer.5. The method of claim 1 , further comprising forming a trench isolation structure within the channel layer and the buffer layer to define a resistor region for the buried resistor.6. The method of claim 1 , wherein forming a buried resistor within the buffer layer comprises:performing a first etch process to etch a recess region through the channel layer and a first portion of the buffer layer;performing a second etch process to etch a resistor region in a second portion of the buffer layer, wherein performing the second etch process comprises laterally etching away a portion of the second portion of the buffer layer beneath the first ...

Semiconductor Device Containing HEMT and MISFET and Method of Forming the Same

A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer. 1. A method comprising:forming a stack of semiconductor layers over a substrate, each semiconductor layer in the stack of semiconductor layers having a different band gap than an adjacent semiconductor layer in the stack of semiconductor layers;forming a capping layer over the stack of semiconductor layers, the capping layer comprising a first source opening, a first drain opening, a second source opening, and a second drain opening;simultaneously forming first and second source and drain features in the respective first and second source and drain openings;forming a first gate opening between the first source feature and the first drain feature;forming a gate dielectric layer in the first gate opening;forming a second gate opening between the second source feature and the second drain feature; andsimultaneously forming a gate electrode layer in the first gate opening and the second gate opening.2. The method of claim 1 , wherein the forming the stack of semiconductor layers comprises:forming a first III-V compound layer on the substrate;forming a second III-V compound layer on the first III-V compound layer;forming a third III-V compound layer over the second III-V compound layer; andforming a fourth III-V ...

III-NITRIDE MATERIAL SEMICONDUCTOR STRUCTURES ON CONDUCTIVE SILICON SUBSTRATES

III-nitride materials are described herein, including material structures comprising III-nitride material regions (e.g., gallium nitride material regions). In certain cases, the material structures also comprise substrates having relatively high electrical conductivities. Certain embodiments include one or more features that reduce the degree to which thermal runaway occurs, which can enhance device performance including at elevated flange temperatures. Some embodiments include one or more features that reduce the degree of capacitive coupling exhibited during operation. For example, in some embodiments, relatively thick III-nitride material regions and/or relatively small ohmic contacts are employed. 1. A semiconductor structure for an integrated circuit component , comprising:a substrate, at least a portion of which is made of bulk silicon having an electronic resistivity of less than 0.10 Ω-cm when the silicon is at 25° C.; anda III-nitride material region located over the substrate.2. A semiconductor structure for an integrated circuit component , comprising:a substrate, at least a portion of which comprises silicon having an electronic resistivity of less than 0.10 Ω-cm when the silicon is at 25° C.; anda III-nitride material region located over the substrate, wherein the integrated circuit component is configured to operate at a frequency greater than 50 MHz.3. The semiconductor structure of claim 1 , wherein the integrated circuit component is configured to operate at a frequency greater than 50 MHz.4. The semiconductor structure of claim 1 ,wherein the integrated circuit component is an active device.5. The semiconductor structure of claim 1 ,wherein the integrated circuit component is a discrete component.6. The semiconductor structure of claim 1 ,wherein the substrate includes a silicon-on-insulator structure.7. The semiconductor structure of claim 2 ,wherein the substrate comprises bulk silicon or silicon carbide.8. The semiconductor structure of claim 1 ...

SEMICONDUCTOR DEVICE

A semiconductor device according to an embodiment includes, a first conductivity type semiconductor substrate including one of Si and SiC; a second conductivity type semiconductor region at a surface of the semiconductor substrate, a GaN-based semiconductor layer on the semiconductor substrate, and a lateral semiconductor element at the GaN-based semiconductor layer and above the semiconductor region, the lateral semiconductor element having a first electrode and a second electrode electrically connected to the semiconductor region. 1. A semiconductor device , comprising:a first conductivity type semiconductor substrate including one of Si and SiC;a second conductivity type semiconductor region at a surface of the semiconductor substrate;a GaN-based semiconductor layer on the semiconductor substrate; anda lateral semiconductor element provided at the GaN-based semiconductor layer and above the semiconductor region, the lateral semiconductor element having a first electrode electrically connected to the semiconductor region, and a second electrode.2. The device according to claim 1 , further comprising an insulating film between the first electrode and the second electrode on the GaN-based semiconductor layer.3. The device according to claim 1 , further comprising a conductive plug on the semiconductor region claim 1 , the conductive plug extending through the GaN-based semiconductor layer and electrically connecting the first electrode and the semiconductor region.4. The device according to claim 1 , further comprising an element isolation region surrounding the lateral semiconductor element claim 1 , whereinan edge of the semiconductor region at the surface of the semiconductor substrate is immediately below the element isolation region.5. The device according to claim 1 , wherein the lateral semiconductor element is a transistor having a source electrode claim 1 , a gate electrode claim 1 , and a drain electrode claim 1 , the source electrode being the first ...

GaN-BASED SCHOTTKY DIODE RECTIFIER

The present disclosure involves a GaN-based Schottky diode rectifier and a method of manufacturing the same. The GaN-based Schottky diode rectifier includes: a substrate, on which a GaN intrinsic layer and a barrier layer are grown in turn; a p-type two-dimension electron gas depletion layer located on an upper surface of the barrier layer; a cathode electrode located at a position on the upper surface of the barrier layer where is different from the position where the p-type two-dimension electron gas depletion layer is formed; and an anode electrode including a first part and a second part electrically connected to each other. 1. A GaN-based Schottky diode rectifier , comprising:a substrate, on which a GaN intrinsic layer and a barrier layer are grown in turn;a p-type two-dimension electron gas depletion layer located on an upper surface of the barrier layer to cover a part or whole of the upper surface of the barrier layer, or partially or fully formed in the upper surface of the barrier layer;a cathode electrode located at a position on the upper surface of the barrier layer which is different from the position where the p-type two-dimension electron gas depletion layer is located; andan anode electrode including a first part and a second part that are electrically connected to each other, wherein the first part of the anode electrode is located on an upper surface of the p-type two-dimension electron gas depletion layer and the second part of the anode electrode is in contact with a part of the upper surface of the barrier layer that is not covered by the p-type two-dimension electron gas depletion layer, and the second part and the cathode electrode are located at either side of the p-type two-dimension electron gas depletion layer.2. The GaN-based Schottky diode rectifier according to claim 1 , wherein the upper surface of the barrier layer is covered by a passivated dielectric layer the passivated dielectric layer covering rest parts of the upper surface of ...

ISOLATION REGIONS FOR SEMICONDUCTOR STRUCTURES AND METHODS OF FORMING THE SAME

Semiconductor structures including isolation regions and methods of forming the same are provided. A first layer is formed over a substrate, where the first layer comprises a semiconductor material. First and second trenches are etched, with each of the first and second trenches extending through the first layer and into the substrate. A wet etchant is introduced into the trenches, and the wet etchant etches a first opening below the first trench and a second opening below the second trench. Each of the first and second openings extends laterally below the first layer. The first and second openings are separated by a portion of the substrate adjoining the first and second openings. An oxidation process is performed to oxidize the portion of the substrate adjoining the first and second openings. An insulating material is deposited that fills the openings and the trenches. 1. A method of forming a semiconductor structure having a substrate , the method comprising:forming a first layer over the substrate, the first layer comprising semiconductor material;etching first and second trenches, each of the first and second trenches extending through the first layer and into the substrate;introducing a wet etchant into the trenches, the wet etchant etching a first opening below the first trench and a second opening below the second trench, each of the first and second openings extending laterally below the first layer, the first and second openings being separated by a portion of the substrate adjoining the first and second openings;performing a diffusion oxidation process to oxidize the portion of the substrate adjoining the first and second openings;depositing an insulating material that fills the openings and the trenches; andforming a via that extends through the first layer and into the substrate, the via comprising a conductive material with sidewalls that are coated with an etch stop layer.2. The method of claim 1 , further comprising:forming one or more transistors ...

SEMICONDUCTOR DEVICE STRUCTURES AND METHODS OF MANUFACTURING THE SAME

A semiconductor device structure and a method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, a first electrode and a second electrode. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The third nitride semiconductor layer is disposed on the second nitride semiconductor layer. The first electrode is disposed on the second nitride semiconductor layer and spaced apart from the third nitride semiconductor layer. The second electrode covers an upper surface of the third nitride semiconductor layer and is in direct contact with the first nitride semiconductor layer. 1. A semiconductor device structure , comprising:a substrate;a first nitride semiconductor layer disposed on the substrate;a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer;a third nitride semiconductor layer disposed on the second nitride semiconductor layer;a first electrode disposed on the second nitride semiconductor layer and spaced apart from the third nitride semiconductor layer; anda second electrode covering an upper surface of the third nitride semiconductor layer and in direct contact with the first nitride semiconductor layer.2. The semiconductor device structure of claim 1 , wherein the third nitride semiconductor layer comprises p-type dopant.3. The semiconductor device structure of claim 1 , wherein the third nitride semiconductor layer comprises at least one of p-doped GaN layer claim 1 , p-doped AlGaN layer and p-doped AlN layer.4. The semiconductor device structure of claim 1 , wherein a portion of the upper surface of the third nitride semiconductor layer is exposed from the second electrode.5. The ...

Integrated circuit device structures and double-sided fabrication techniques

Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

Complementary gallium nitride integrated circuits and methods of their fabrication

An embodiment of a complementary GaN integrated circuit includes a GaN layer with a first bandgap. A second layer with a second bandgap is formed on the GaN layer, resulting in a 2DEG in a contact region between the GaN layer and the second layer. The second layer has a relatively thin portion and a relatively thick portion. A third layer is formed over the relatively thick portion of the second layer. The third layer has a third bandgap that is different from the second bandgap, resulting in a 2DHG in a contact region between the second layer and the third layer. A transistor of a first conductivity type includes the 2DHG, the relatively thick portion of the second layer, and the third layer, and a transistor of a second conductivity type includes the 2DEG and the relatively thin portion of the second layer.

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor layer laminate disposed on a semiconductor substrate, a first and a second low-side transistors, and a first and a second high-side transistors. Each of the transistors is disposed on the semiconductor layer laminate, and includes a gate electrode, a source electrode, and a drain electrode. The second low-side transistor is disposed between the first low-side transistor and the first high-side transistor, and the first high-side transistor is disposed between the second low-side transistor and the second high-side transistor. The source electrodes of the first and the second low-side transistors are combined into one source electrode, the drain electrodes of the first and the second high-side transistors are combined into one drain electrode, and the drain electrode of the second low-side transistor and the source electrode of the first high-side transistor are combined into one first electrode. 1. A semiconductor device comprising:a semiconductor layer laminate disposed on a semiconductor substrate;a first low-side transistor disposed on the semiconductor layer laminate, and having a gate electrode, a source electrode, and a drain electrode;a second low-side transistor disposed on the semiconductor layer laminate, and having a gate electrode, a source electrode, and a drain electrode;a first high-side transistor disposed on the semiconductor layer laminate, and having a gate electrode, a source electrode, and a drain electrode; anda second high-side transistor disposed on the semiconductor layer laminate, and having a gate electrode, a source electrode, and a drain electrode,wherein the second low-side transistor is disposed between the first low-side transistor and the first high-side transistor,the first high-side transistor is disposed between the second low-side transistor and the second high-side transistor,the source electrode of the first low-side transistor and the source electrode of the second low-side ...

SWITCHING CIRCUIT

In one embodiment, an impedance matching network is disclosed that includes a first circuit comprising a first variable component providing a first variable capacitance or inductance, and a second circuit comprising a second variable component providing a second variable capacitance or inductance. Each of the first circuit and the second circuit includes plurality of switching circuits configured to provide the first variable capacitance or inductance and the second variable capacitance or inductance. Each of the plurality of switching circuits includes a diode and a driver circuit configured to switch the diode. The driver circuit includes a first switch, a second switch coupled in series with the first switch, and a filter circuit that is coupled at a first end between the first switch and the second switch, and is operably coupled at a second end to the diode. 1. An impedance matching network comprising:an RF input configured to couple to an RF source;an RF output configured to couple to a load;a first circuit comprising a first variable component providing a first variable capacitance or inductance; anda second circuit comprising a second variable component providing a second variable capacitance or inductance; a diode; and', a first switch;', 'a second switch coupled in series with the first switch; and', 'a filter circuit that is coupled at a first end between the first switch and the second switch, and is operably coupled at a second end to the diode., 'a driver circuit configured to switch the diode, the driver circuit comprising], 'wherein each of the first circuit and the second circuit comprises a plurality of switching circuits configured to provide the first variable capacitance or inductance and the second variable capacitance or inductance, respectively, each of the plurality of switching circuits comprising211-. (canceled)12. A method of matching an impedance , the method comprising: a first circuit comprising a first variable component providing a ...

Integrated Circuit with First and Second Switching Devices, Half Bridge Circuit and Method of Manufacturing

An integrated circuit includes a first switching device including a first semiconductor region in a first section of a semiconductor portion and a second switching device including a second semiconductor region in a second section of the semiconductor portion. The first and second sections as well as electrode structures of the first and second switching devices outside the semiconductor portion are arranged along a vertical axis perpendicular to a first surface of the semiconductor portion.

TECHNIQUES FOR FORMING TRANSISTORS INCLUDING GROUP III-V MATERIAL NANOWIRES USING SACRIFICIAL GROUP IV MATERIAL LAYERS

Techniques are disclosed for forming transistors including one or more group III-V semiconductor material nanowires using sacrificial group IV semiconductor material layers. In some cases, the transistors may include a gate-all-around (GAA) configuration. In some cases, the techniques may include forming a replacement fin stack that includes group III-V material layer (such as indium gallium arsenide, indium arsenide, or indium antimonide) formed on a group IV material buffer layer (such as silicon, germanium, or silicon germanium), such that the group IV buffer layer can be later removed using a selective etch process to leave the group III-V material for use as a nanowire in a transistor channel. In some such cases, the group III-V material layer may be grown pseudomorphically to the underlying group IV material, so as to not form misfit dislocations. The techniques may be used to form transistors including any number of nanowires. 1. An integrated circuit including at least one transistor , the integrated circuit comprising:a substrate;a body above the substrate, the body including group III-V semiconductor material;a gate structure wrapped around the body, the gate structure including a gate electrode and a gate dielectric, the gate dielectric between the gate electrode and the body; anda trench below the body and extending into a portion of the substrate, wherein material of the gate dielectric and the gate electrode are included in the portion of the trench that extends into the substrate.2. The integrated circuit of claim 1 , wherein the substrate is a bulk silicon substrate.3. The integrated circuit of claim 1 , wherein the trench comprises a bottom portion including {111} faceting.4. The integrated circuit of claim 1 , wherein the body has a vertical thickness below the critical thickness of the group III-V semiconductor material included in the body.5. The integrated circuit of claim 1 , wherein the group III-V semiconductor material included in the body ...

ENHANCEMENT/DEPLETION DEVICE PAIRS AND METHODS OF PRODUCING THE SAME

Enhancement/depletion device pairs and methods of producing the same are disclosed. A disclosed example multilayered die includes a depletion mode device that includes a first polarization layer and a voltage tuning layer, and an enhancement mode device adjacent the depletion mode device, where the enhancement mode device includes a second polarization layer, and where the second polarization layer includes an opening corresponding to a gate of the enhancement mode device. 120-. (canceled)21. A multilayered die comprising:a depletion mode device having a first polarization layer and a voltage tuning layer; andan enhancement mode device adjacent the depletion mode device, the enhancement mode device having a second polarization layer, wherein the second polarization layer comprises an opening corresponding to a gate of the enhancement mode device.22. The multilayered die of claim 21 , wherein the first and second polarization layers are applied during a same process.23. The multilayered die of claim 21 , wherein at least one of the first or second polarization layers comprise an aluminum indium nitride layer and an aluminum nitride layer.24. The multilayered die of claim 23 , wherein the aluminum indium nitride layer and the aluminum nitride layer are each 1 to 10 nanometers in thickness.25. The multilayered die of claim 21 , wherein the voltage tuning layer comprises aluminum gallium nitride having less than 40% of aluminum by volume.26. The multilayered die of claim 21 , wherein the voltage tuning layer is 2 to 8 nanometers in thickness.27. An integrated circuit device comprising: a depletion mode device having a voltage tuning layer and a first polarization layer, and', 'an enhancement mode device adjacent to the depletion mode device, wherein the enhancement mode device comprises a second polarization layer having an opening corresponding to a gate of the enhancement mode device., 'a plurality of device pairs, each device pair comprising28. The integrated circuit ...

POWER AMPLIFIER MODULES INCLUDING RELATED SYSTEMS, DEVICES, AND METHODS

One aspect of this disclosure is a power amplifier system that includes a control interface, a power amplifier, a passive component on a same die as the power amplifier, and a bias circuit on a different die than the power amplifier. The control interface can operate as a serial interface or as a general purpose input/output interface. The power amplifier can be controllable based at least partly on an output signal from the control interface. The bias circuit can generate a bias signal based at least partly on an indication of the electrical property of the passive component. Other embodiments of the system are provided along with related methods and components thereof. 129.-. (canceled)30. A power amplifier system comprising:a control interface configured to receive an input signal, operate as a serial interface in response to the input signal having a first value, operate as a general purpose input/output interface in response to the input signal having a second value, and provide an output signal;a power amplifier configured to amplify a radio frequency signal, the power amplifier controllable based at least partly on the output signal;a passive component having an electrical property that depends on a condition of a die that includes the passive component and the power amplifier; anda bias circuit included on a different die than the power amplifier, the bias circuit configured to generate a bias signal based at least partly on an indication of the electrical property of the passive component.31. The power amplifier system of wherein the control interface is configured to set a mode of the power amplifier.32. The power amplifier system of wherein the passive component includes a resistor and the electrical property is a resistance.33. The power amplifier system of wherein the power amplifier includes a heterojunction bipolar transistor claim 30 , and the passive component includes a semiconductor resistor having a resistive layer formed of a material that is ...

Method of Manufacturing an Integrated Circuit

A method of manufacturing an integrated circuit includes: growing an epitaxial layer on a process surface of a base substrate; forming, by processes applied to an exposed first surface of the epitaxial layer, first transistor cells in the epitaxial layer, each first transistor cell including a first gate electrode; and forming, by processes applied to a surface opposite to the first surface, second transistor cells, each second transistor cell including a second gate electrode. 1. A method of manufacturing an integrated circuit , the method comprising:growing an epitaxial layer on a process surface of a base substrate;forming, by processes applied to an exposed first surface of the epitaxial layer, first transistor cells in the epitaxial layer, each first transistor cell comprising a first gate electrode; andforming, by processes applied to a surface opposite to the first surface, second transistor cells, each second transistor cell comprising a second gate electrode.2. The method of claim 1 , further comprising:removing at least a portion of the base substrate after forming the first transistor cells and before forming the second transistor cells.3. The method of claim 1 , wherein the second transistor cells are formed in the epitaxial layer.4. The method of claim 1 , wherein the second transistor cells are formed in the base substrate.5. The method of claim 1 , further comprising:growing, after forming the first transistor cells, a further epitaxial layer on a side of the base substrate opposite to the epitaxial layer with the first transistor cells, wherein the second transistor cells are formed in the further epitaxial layer.6. The method of claim 1 , further comprising:forming, before growing the epitaxial layer, an auxiliary structure from a material different from a material of the base substrate on the process surface.7. The method of claim 6 , further comprising:removing, before forming the second transistor cells, the base substrate after forming the first ...

Method of Manufacturing a Semiconductor Die

A method of manufacturing a semiconductor die includes: forming a power HEMT (high-electron-mobility transistor) in a III-nitride semiconductor substrate, the power HEMT having a gate, a source and a drain; monolithically integrating a first gate driver HEMT with the power HEMT in the III-nitride semiconductor substrate, the first gate driver HEMT having a gate, a source and a drain and logically forming part of a driver; and electrically connecting the first gate driver HEMT to the gate of the power HEMT so that the first gate driver HEMT is operable to turn the power HEMT off or on responsive to an externally-generated control signal received from the driver or other device. 1. A method of manufacturing a semiconductor die , the method comprising:forming a power HEMT (high-electron-mobility transistor) in a III-nitride semiconductor substrate, the power HEMT having a gate, a source and a drain;monolithically integrating a first gate driver HEMT with the power HEMT in the III-nitride semiconductor substrate, the first gate driver HEMT having a gate, a source and a drain and logically forming part of a driver; andelectrically connecting the first gate driver HEMT to the gate of the power HEMT so that the first gate driver HEMT is operable to turn the power HEMT off or on responsive to an externally-generated control signal received from the driver or other device.2. The method of claim 1 , further comprising forming an isolation region in the III-nitride semiconductor substrate that separates the power HEMT from the first gate driver HEMT.3. The method of claim 1 , wherein the power HEMT and the first gate driver HEMT share a common source region disposed in the III-nitride semiconductor substrate.4. The method of claim 1 , further comprising:electrically connecting the drain of the first gate driver HEMT to the gate of the power HEMT; andelectrically connecting the source of the first gate driver HEMT to the source of the power HEMT.5. The method of claim 1 , ...

III-N TRANSISTORS WITH INTEGRATED LINEARIZATION DEVICES

Disclosed herein are IC structures, packages, and devices that include linearization devices integrated on the same support structure as III-N transistors. A linearization device may be any suitable device that may exhibit behavior complementary to that of a III-N transistor so that a combined behavior of the III-N transistor and the linearization device includes less nonlinearity than the behavior of the III-N transistor alone. Linearization devices may be implemented as, e.g., one-sided diodes, two-sided diodes, or P-type transistors. Integrating linearization devices on the same support structure with III-N transistors advantageously provides an integrated solution based on III-N transistor technology, thus providing a viable approach to reducing or eliminating nonlinear behavior of III-N transistors. In some implementations, linearization devices may be integrated with III-N transistors by being disposed side-by-side with the III-N transistors, advantageously enabling implementation of both the III-N transistors and the linearization devices in a single device layer.

POWER SEMICONDUCTOR ELEMENT

A power semiconductor element includes: a main transistor including a first gate electrode, a first drain electrode, and a first source electrode; a sensor transistor including a second gate electrode, a second drain electrode, and a second source electrode; and a gate switch transistor including a third gate electrode, and a third drain electrode, a third source electrode. The first gate electrode, the second gate electrode, and the third drain electrode are connected, the first drain electrode and the second drain electrode are connected, the first source electrode and the second source electrode are connected via a sensor resistor, the first source electrode and the third source electrode are connected, the second source electrode and the third gate electrode are connected via a switch resistor, and the main transistor, the sensor transistor, and the gate switch transistor are formed with a nitride semiconductor. 1. A power semiconductor element comprising:a main transistor including a first gate electrode, a first drain electrode, and a first source electrode;a sensor transistor including a second gate electrode, a second drain electrode, and a second source electrode; anda gate switch transistor including a third gate electrode, a third drain electrode, and a third source electrode;a sensor resistor; anda switch resistor,wherein the first gate electrode, the second gate electrode, and the third drain electrode are connected,the first drain electrode and the second drain electrode are connected,the first source electrode and the second source electrode are connected via the sensor resistor,the first source electrode and the third source electrode are connected,the second source electrode and the third gate electrode are connected via the switch resistor, andthe main transistor, the sensor transistor, and the gate switch transistor are formed with a nitride semiconductor.2. The power semiconductor element according to claim 1 , further comprisinga capacitor ...

GALLIUM NITRIDE NMOS ON SI (111) CO-INTEGRATED WITH A SILICON PMOS

This disclosure is directed to a complementary metal oxide semiconductor (CMOS) transistor that includes a gallium nitride n-type MOS and a silicon P-type MOS. The transistor includes silicon 111 substrate, a gallium nitride transistor formed in a trench in the silicon 111 substrate, the gallium nitride transistor comprising a source electrode, a gate electrode, and a drain electrode; a polysilicon layer formed on the gallium nitride transistor, the polysilicon layer coplanar with a top side of the silicon 111 substrate; a first metal via disposed on the source electrode; a second metal via disposed on the gate electrode and isolated from the first metal via by a polysilicon layer; a first trench contact formed on the first metal via; and a second trench contact formed on the second metal via; the first trench contact isolated from the second trench contact by at least one replacement metal gate (RMG) polysilicon island. 1. An apparatus comprising:a silicon substrate;a gallium nitride transistor formed in a trench in the silicon substrate, the gallium nitride transistor comprising a source electrode, a gate electrode, and a drain electrode;a silicon layer formed over the gallium nitride transistor, the silicon layer coplanar with a top side of the silicon substrate;a first metal via disposed on the source electrode;a second metal via disposed on the gate electrode and isolated from the first metal via;a first trench contact formed on the first metal via; anda second trench contact formed on the second metal via.2. The apparatus of claim 1 , further comprising a transistor formed on the silicon substrate proximate to the gallium nitride transistor.3. The apparatus of claim 2 , wherein the transistor comprises a p-type metal oxide semiconductor (PMOS) transistor.4. The apparatus of claim 2 , wherein the transistor comprises: a dielectric material on the silicon substrate,', 'a gate metal on the dielectric material, and', 'a dielectric spacer on each sidewall of the ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

A semiconductor device includes a buffer layer formed with a semiconductor adapted to produce piezoelectric polarization, and a channel layer stacked on the buffer layer, wherein a two-dimensional hole gas, generated in the channel layer by piezoelectric polarization of the buffer layer, is used as a carrier of the channel layer. On a complementary semiconductor device, the semiconductor device described above and an n-type field effect transistor are formed on the same compound semiconductor substrate. Also, a level shift circuit is manufactured by using the semiconductor device. Further, a semiconductor device manufacturing method includes forming a compound semiconductor base portion, forming a buffer layer on the base portion, forming a channel layer on the buffer layer, forming a gate on the channel layer, and forming a drain and source with the gate therebetween on the channel layer. 1. A complementary semiconductor device , comprising:a compound semiconductor substrate;a semiconductor device and an n-type field effect transistor on the compound semiconductor substrate, wherein the semiconductor device comprises:a buffer layer that includes a semiconductor configured to produce piezoelectric polarization; anda channel layer stacked on the buffer layer,wherein a semiconductor layer of GaAlInP is stacked between the buffer layer and the compound semiconductor substrate.2. The complementary semiconductor device of claim 1 , wherein the semiconductor device is a p-type filed effect transistor.3. The complementary semiconductor device of claim 1 , wherein the compound semiconductor substrate is a GaAs single crystal substrate.4. The complementary semiconductor device of claim 1 , wherein the semiconductor is configured to produce the piezoelectric polarization in the buffer layer is InGaP.5. The complementary semiconductor device of claim 1 ,wherein the semiconductor configured to produce the piezoelectric polarization in the buffer layer is pure InGaP.6. The ...

POWER DIODE, RECTIFIER, AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

With a non-linear element (e.g., a diode) with small reverse saturation current, a power diode or rectifier is provided. A non-linear element includes a first electrode provided over a substrate, an oxide semiconductor film provided on and in contact with the first electrode and having a concentration of hydrogen of 5×10atoms/cmor less, a second electrode provided on and in contact with the oxide semiconductor film, a gate insulating film covering the first electrode, the oxide semiconductor film, and the second electrode, and third electrodes provided in contact with the gate insulating film and facing each other with the first electrode, the oxide semiconductor film, and the second electrode interposed therebetween or a third electrode provided in contact with the gate insulating film and surrounding the second electrode. The third electrodes are connected to the first electrode or the second electrode. With the non-linear element, a power diode or a rectifier is formed. 1. A rectifier comprising a first non-linear element and a second non-linear element , each of the first non-linear element and the second non-linear element comprising:a first electrode provided over a substrate;an oxide semiconductor film provided on and in contact with the first electrode;a second electrode provided on and in contact with the oxide semiconductor film;a gate insulating film covering the first electrode, the oxide semiconductor film, and the second electrode; anda third electrode provided in contact with the gate insulating film and adjacent to a side surface of the oxide semiconductor film, the third electrode being connected to the first electrode or the second electrode,wherein an anode of the first non-linear element is connected to a lower potential side reference potential,wherein a cathode of the first non-linear element is connected to an input portion and an anode of the second non-linear element, andwherein a cathode of the second non-linear element is connected to an ...

Metal Oxide Thin Film Semiconductor Device Monolithically Integrated With Dissimilar Device on the Same Wafer

A monolithically integrated circuit comprising a semiconducting wafer, a metal oxide thin film semiconductor device disposed adjacent a first region of the semiconducting wafer, and a dissimilar semiconductor device disposed adjacent a second region of the semiconducting wafer and fabrication methods thereof. 17-. (canceled)8. A monolithically integrated circuit comprising:a semiconducting wafer comprising an alloy of two or more of indium, gallium, aluminum, phosphorus, nitrogen, and arsenic;a metal oxide thin film semiconductor device disposed adjacent a first region of the semiconducting wafer;a dissimilar semiconductor device disposed adjacent a second region of the semiconducting wafer, the dissimilar semiconductor device being electrically isolated from the first region of the semiconducting wafer; andan electrically conducting interconnect layer connecting the metal oxide thin film semiconductor device to the dissimilar semiconductor device.9. (canceled)10. The monolithically integrated circuit of wherein the dissimilar semiconductor device is a compound semiconductor transistor.11. The monolithically integrated circuit of wherein the metal oxide thin film semiconductor device includes a metal oxide thin film semiconductor device gate and a metal oxide thin film semiconductor device dielectric layer and the dissimilar semiconductor device includes a dissimilar semiconductor device gate and a dissimilar semiconductor device passivation layer claim 8 , at least one of the metal oxide thin film semiconductor device gate and metal oxide thin film semiconductor device dielectric layer being formed from a same material and concurrently with the dissimilar semiconductor device gate and the dissimilar semiconductor device passivation layer claim 8 , respectively.1220.-. (canceled) This application is a divisional of copending U.S. application Ser. No. 16/722,022, filed Dec. 20, 2019, entitled “Metal Oxide Thin Film Semiconductor Device Monolithically Integrated With ...

Semiconductor device

The semiconductor device includes a trench that penetrates a barrier layer, and reaches a middle portion of a channel layer among an n+ layer, an n-type layer, a p-type layer, the channel layer, and the barrier layer which are formed above a substrate, a gate electrode arranged within the groove through a gate insulating film, and a source electrode and a drain electrode which are formed above the barrier layer on both sides of the gate electrode. The n-type layer and the drain electrode are electrically coupled by a connection portion that reaches the n+ layer. The p-type layer and the source electrode are electrically coupled by a connection portion that reaches the p-type layer. A diode including a p-type layer and an n-type layer is provided between the source electrode and the drain electrode, to thereby prevent the breaking of an element caused by an avalanche breakdown.

METHODS AND APPARATUS TO FORM SILICON-BASED TRANSISTORS ON GROUP III-NITRIDE MATERIALS USING ASPECT RATIO TRAPPING

Methods and apparatus to form silicon-based transistors on group III-nitride materials using aspect ratio trapping are disclosed. An example integrated circuit includes a group III-nitride substrate and a fin of silicon formed on the group III-nitride substrate. The integrated circuit further includes a first transistor formed on the fin of silicon and a second transistor formed on the group III-nitride substrate. 1. An integrated circuit comprising:a silicon substrate comprising a planar surface oriented in a <111> crystal lattice plane;a group III-nitride layer in contact with the surface of the silicon substrate;a dielectric material layer on the group III-nitride layer;a fin of semiconductor material with a cubic crystal structure located in a trench of the dielectric material layer and in contact with the group III-nitride layer, the fin comprising a height of the fin that is not less than twice a width of the fin;a first transistor comprising a first gate dielectric, the first gate dielectric on and in direct contact with the fin; anda second transistor comprising a second gate dielectric, the second gate dielectric on and in direct contact with the group III-nitride layer and a sidewall of the dielectric material layer.2. The integrated circuit of claim 1 , wherein the group III-nitride layer comprises a crystallinity epitaxial to a crystallinity of the surface of the silicon substrate.3. The integrated circuit of claim 2 , wherein the group III-nitride layer has a thickness of not less than 2 micrometers between the fin and the surface of the silicon substrate and between the second transistor and the surface of the silicon substrate.4. The integrated circuit of claim 1 , wherein the group III-nitride layer comprises a plurality of intermediate layers between the surface of the silicon substrate and a top surface of the group III-nitride layer.5. The integrated circuit of claim 4 , wherein the plurality of intermediate layers are between the fin and the ...

Gallium nitride voltage regulator

A gallium nitride transistor can include a silicon substrate and a first oxide layer and a second oxide layer on the substrate. A first gallium nitride layer may reside on the silicon substrate and the first and second oxide layers. A polarization layer may reside on the first gallium nitride layer. A two dimensional electron gas may exist in the first gallium nitride layer proximate to the polarization layer. A second gallium nitride layer may reside on a first sidewall of the polarization layer and on the first oxide layer on the substrate. A first p-doped gallium nitride layer may reside on the second gallium nitride layer. A third gallium nitride layer may reside on a second sidewall of the polarization layer and on the second oxide layer on the substrate. A second p-doped gallium nitride layer may reside on the second gallium nitride layer.

Semiconductor device

On a single-crystal semiconductor substrate with an upper surface including a first direction in which an inverted mesa step extends and a second direction in which a forward mesa step extends in response to anisotropic etching in which an etching rate depends on crystal plane orientation, a bipolar transistor including a collector layer, a base layer, and an emitter layer that are epitaxially grown, and a base wire connected to the base layer are arranged. A step is provided at an edge of the base layer, and the base wire is extended from inside to outside of the base layer in a direction intersecting the first direction in a plan view. An intersection of the edge of the base layer and the base wire has a disconnection prevention structure that makes it difficult for step-caused disconnection of the base wire to occur.

SEMICONDUCTOR APPARATUS

A semiconductor apparatus includes a substrate; a nitride semiconductor layer formed on the substrate; a transistor formed on the nitride semiconductor layer, and including a source electrode, a gate electrode, and a drain electrode disposed in this order; and a diode formed on the nitride semiconductor layer, and including an anode electrode and a cathode electrode disposed in this order. The semiconductor apparatus has a transistor/diode pair in which the source electrode, the gate electrode, the drain electrode, the anode electrode, and the cathode electrode are sequentially disposed in this order, and the drain electrode of the transistor and the anode electrode of the diode are connected by a drain/anode common electrode wiring and serve as a common electrode. 1. A semiconductor apparatus comprising:a substrate;a nitride semiconductor layer formed on the substrate;a transistor formed on the nitride semiconductor layer, and including a source electrode, a gate electrode, and a drain electrode disposed in this order; anda diode formed on the nitride semiconductor layer, and including an anode electrode and a cathode electrode disposed in this order,wherein the semiconductor apparatus has a transistor/diode pair in which the source electrode, the gate electrode, the drain electrode, the anode electrode, and the cathode electrode are disposed in this order, and the drain electrode of the transistor and the anode electrode of the diode are connected by a drain/anode common electrode wiring for serving as a common electrode.2. The semiconductor apparatus according to claim 1 , whereinthe transistor/diode pair is disposed at regular intervals on the nitride semiconductor layer with the source electrode of the transistor and the cathode electrode of the diode being shared by the pair.3. The semiconductor apparatus according to claim 1 , whereinthe electrodes of the transistor and the electrodes of the diode are symmetrically disposed with respect to the source ...

SEMICONDUCTOR DEVICE HAVING A Pd-CONTAINING ADHESION LAYER

According to present invention, a semiconductor device includes a semiconductor substrate formed of GaAs, an adhesion layer formed of Pd or an alloy containing Pd on the semiconductor substrate, a barrier layer formed of Co or an alloy containing Co on the adhesion layer, and a metal layer formed of Cu, Ag or Au on the barrier layer. 1. A method of manufacturing a semiconductor device , comprising:a step of forming an adhesion layer of Pd or an alloy containing Pd on a semiconductor substrate formed of GaAs;a step of forming a barrier layer of Co or an alloy containing Co on the adhesion layer; anda heat treatment step of increasing the temperature of the semiconductor substrate, the adhesion layer and the barrier layer to 25° C. to 250° C. to form Pd—Ga—As on the adhesion layer and to form an alloy layer containing Co and Pd between the adhesion layer and the barrier layer.2. The method of manufacturing a semiconductor device according to claim 1 , comprising a step of forming a metal layer of Cu claim 1 , Ag or Au on the barrier layer before the heat treatment step.3. A method of manufacturing a semiconductor device claim 1 , comprising: a step of performing electroless plating on the semiconductor substrate to form a barrier layer of Co—P or Co—W—P on the adhesion layer; and', 'a step of forming a metal layer of Cu, Ag or Au on the barrier layer., 'a step of forming an adhesion layer of Pd or an alloy containing Pd on a semiconductor substrate formed of GaAs;'}4. The method of manufacturing a semiconductor device according to claim 3 , wherein the metal layer is of a two-layer structure having Au in a lower layer and having Cu in an upper layer. The present invention relates to a semiconductor device having a metal layer used, for example, as an electrode and to a method of manufacturing the semiconductor device.PTL 1 discloses a technique to form a barrier layer, a seed layer and a wiring layer on a side wall of an insulating film by a wet process.PTL 1: ...

Device Including PCM RF Switch Integrated with Group III-V Semiconductors

There are disclosed herein various implementations of a semiconductor device including a group III-V layer situated over a substrate, and a phase-change material (PCM) radio frequency (RF) switch situated over the group III-V layer. The PCM RF switch couples a group III-V transistor situated over the group III-V layer to one of an integrated passive element or another group III-V transistor situated over the group III-V layer. The PCM RF switch includes a heating element transverse to the PCM, the heating element underlying an active segment of the PCM. The PCM RF switch is configured to be electrically conductive when the active segment of the PCM is in a crystalline state, and to be electrically insulative when the active segment of the PCM is in an amorphous state. 1. A method for using a substrate having a group III-V layer thereon , and a group III-V transistor formed over said group III-V layer , said method comprising:forming a phase-change material (PCM) radio frequency (RF) switch over said group III-V layer;coupling said PCM RF switch between said group III-V transistor and one of an integrated passive element or another group III-V transistor situated over said group III-V layer;said PCM RF switch including a heating element transverse to said PCM, said heating element underlying an active segment of said PCM;said PCM RF switch being configured to be electrically conductive when said active segment of said PCM is in a crystalline state, and to be electrically insulative when said active segment of said PCM is in an amorphous state.2. The method of claim 1 , comprising forming said integrated passive element prior to forming said PCM RF switch.3. The method of claim 1 , comprising forming said integrated passive element after forming said PCM RF switch.4. The method of claim 1 , wherein said coupling said PCM RF switch between said group III-V transistor and one of an integrated passive element or another group III-V transistor situated over said group III ...

High switching frequency, low loss and small form factor fully integrated power stage

A method for fabricating a semiconductor device includes, for a substrate having a first region protected by a cap layer, forming a first device on a second region of the substrate. The substrate includes an insulator layer disposed between a first semiconductor layer and a second semiconductor layer each including a first semiconductor material. The method further includes forming a second device on the first region, including forming one or more transistors each having a channel formed from a second semiconductor material different from the first semiconductor material.

Integrated Resistor for Semiconductor Device

A heterostructure semiconductor device includes first and second active areas, each electrically isolated from one another, and each including first and second active layers with an electrical charge disposed therebetween. A power transistor is formed in the first active area, and an integrated gate resistor is formed in the second active area. A gate array laterally extends over the first active area of the power transistor. First and second ohmic contacts are respectively disposed at first and second lateral ends of the integrated gate resistor, the first and second ohmic contacts are electrically connected to the second portion of the second active layer, the second ohmic contact also being electrically connected to the gate array. A gate bus is electrically connected to the first ohmic contact. 121-. (canceled)22. A heterostructure semiconductor device comprising:a substrate;a first active layer disposed above the substrate;a second active layer disposed above the first active layer, an electrical charge layer formed between the first and second active layers; a first portion of the first active layer;', 'a first portion of the second active layer; and', 'a first portion of the electrical charge layer;, 'a first active area comprising a power transistor which includes a second portion of the first active layer;', 'a second portion of the second active layer;', 'a second portion of the electrical charge layer, the second portion of the electrical charge layer is laterally separated from the first portion of the electrical charge layer; and', 'a first contact disposed above the second active layer; and', 'a second contact disposed above the second active layer and laterally spaced apart from the first contact, the first and second contacts being electrically coupled to the second portion of the electrical charge layer;, 'a second active area comprising a gate resistance which includesa gate array disposed over the first active area, the gate array configured as a ...

CONTACT STRUCTURE AND EXTENSION FORMATION FOR III-V NFET

FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions. 1. A method of fabricating fin-type field-effect transistors , comprising:obtaining a semiconductor substrate;epitaxially growing a first III-V blanket layer directly on a top surface of the semiconductor substrate;epitaxially growing a second III-V blanket layer above the first III-V blanket layer;forming a plurality of III-V fin structures from the second III-V blanket layer;forming a plurality of gate structures on the III-V fin structures;forming dielectric spacers on the gate structures;forming a plurality of recesses through the first III-V blanket layer and the III-V fin structures down to the semiconductor substrate, thereby forming a plurality of columns extending upwardly from the semiconductor substrate, each of the columns including a III-V base formed from the first III-V blanket layer, a portion of one of the III-V fin structures, one of the plurality of gate structures, and one of the dielectric spacers;epitaxially growing a silicon-based semiconductor layer on an exposed surface of the semiconductor substrate and within the recesses such that a portion of the silicon-based semiconductor layer adjoins the portions of the III-V fin structures comprising each of the columns;subjecting the columns and the silicon-based semiconductor layer to a first annealing process, thereby causing diffusion of silicon from the silicon-based semiconductor layer into the III-V fin structures to form n-type junctions, andforming n-type source/drain regions from the silicon-based semiconductor layer.2. The method of claim 1 , further including:growing a III-V semi-isolating layer on the first blanket layer, ...

Semiconductor device

A semiconductor device including a main region, a sense region, a separation region electrically isolating the main and sense region regions includes a first semiconductor layer positioned on the main surface of a semiconductor substrate, a plurality of main cells disposed in the main region, and a plurality of sense cells disposed in the sense region. Source regions of the main cell become conductive with a source electrode and source regions of the sense cell become conductive with a sense electrode. The separation region includes a plurality of second conductivity type separation body regions and a barrier region and is disposed within a first semiconductor layer and is disposed to abut on the surface of the first semiconductor layer.

CONTACT STRUCTURE AND EXTENSION FORMATION FOR III-V NFET

FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions. 1. A method comprising: epitaxially growing a III-V blanket layer on the semiconductor substrate;', 'forming the III-V fin structures above the III-V blanket layer, and', 'forming the plurality of recesses through the III-V blanket layer and the III-V fin structures down to the semiconductor substrate such that the III-V bases of the columns are formed from the III-V blanket layer on the semiconductor substrate;, 'obtaining a semiconductor structure including a semiconductor substrate and a plurality of columns extending from the semiconductor substrate, the columns being separated by a plurality of recesses, each of the columns including a III-V base and a III-V fin structure, the III-V fin structure being positioned on the III-V base, wherein obtaining the semiconductor structure includesepitaxially growing a silicon-containing layer on the semiconductor substrate and within the recesses such that a portion of the silicon-containing layer adjoins the III-V fin structures;causing diffusion of silicon from the silicon-containing layer into the III-V fin structures to form n-type junctions, andforming n-type source/drain regions from the silicon-containing layer.2. The method of claim 1 , further including:growing a III-V semi-isolating layer on the III-V blanket layer,forming a second III-V blanket layer on the III-V semi-isolating layer,forming the III-V fin structures from the second III-V blanket layer, andforming the plurality of recess through the III-V semi-isolating layer, wherein the III-V base of each column includes a portion of the semi-isolating III-V layer adjoining one of the III-V fin ...

FinFET SRAM Having Discontinuous PMOS Fin Lines

An IC chip includes a logic circuit cells array and a static random access memory (SRAM) cells array. The logic circuit cells array includes a plurality of logic circuit cells abutted to one another in a first direction. The logic circuit cells array includes one or more continuous first fin lines that each extends across at least three of the abutted logic circuit cells in the first direction. The static random access memory (SRAM) cells array includes a plurality of SRAM cells abutted to one another in the first direction. The SRAM cells array includes discontinuous second fin lines. 1. A device , comprising:a first P-type well region and a second P-type well region each spanning in a first direction, wherein the first P-type well region and the second P-type well region are spaced apart from each other in a second direction different from the first direction;an N-type well region spanning in the first direction and disposed between the first and second P-type well regions;a first active region and a second active region disposed over the first P-type well region and the second P-type well regions, respectively;a third active region and a fourth active region disposed over a first portion and a second portion of the N-type well region, respectively, wherein the third active region and the fourth active region are spaced apart from each other in the first direction; anda fifth active region disposed over both the first and second portions of the N-type well region, wherein the fifth active region is spaced apart from the third and fourth active regions in the second direction, and wherein the first, second, third, fourth, and fifth active regions each span in the first direction.2. The device of claim 1 , wherein:the first active region is substantially longer than each of the third active region, the fourth active region, and the fifth active region in the first direction; andthe second active region is substantially longer than each of the third active region, ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor layer is formed on semiconductor substrate. Semiconductor layer has a plurality of well regions in a surface remote from semiconductor substrate. Semiconductor layer includes drift region in addition to the plurality of well regions. The plurality of well regions each include body region, source region, and contact region. Source region is in contact with body region. Contact region is in contact with both body region and source region. Body region, source region, and source wire are at an identical potential because of contact region. Semiconductor layer includes ineffective region R at the surface remote from semiconductor substrate. 1. A semiconductor device comprising:a semiconductor substrate; a plurality of well regions in top portions remote from the semiconductor substrate, the plurality of well regions each including a source region;', 'a drift region in a part other than the plurality of well regions; and', 'an ineffective region at the surface remote from the semiconductor substrate;, 'a semiconductor layer disposed on the semiconductor substrate, the semiconductor layer comprisinga gate insulating layer disposed on the semiconductor layer, the gate insulating layer exposing at least part of each of the source regions of the plurality of well regions both inside and outside the ineffective region;a gate electrode disposed on the gate insulating layer outside the ineffective region, the gate electrode being not disposed inside the ineffective region;an insulating film covered the gate electrode outside the ineffective region, the insulating film being put on at least part of the gate insulating layer inside the ineffective region; anda source wire put on the insulating film both inside and outside the ineffective region, the source wire being in contact with the exposed at least part of each of the source regions of the plurality of well regions.2. The semiconductor device according to claim 1 , wherein an conductive or non-conductive foreign ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

There is provided a semiconductor device configured to include a plurality of semiconductor units formed in a semiconductor layer. Each of the semiconductor units comprises a mesa portion; a Schottky electrode formed on the mesa portion; an insulating film formed continuously on another portion of the Schottky electrode that is nearer to an edge of an upper face of the mesa portion than one portion of the Schottky electrode, on a side face of the mesa portion, and on a surface of the semiconductor layer other than the mesa portion; and a wiring electrode formed on the Schottky electrode and the insulating film. An angle between the side face of the mesa portion and the surface of the semiconductor layer is 90 degrees. A part of the wiring electrode is placed between the insulating films formed on opposed side faces of adjacent mesa portions. The insulating films formed on the opposed side faces are interconnected on the surface of the semiconductor layer, such as to separate the part of the wiring electrode from the semiconductor layer. 1. A semiconductor device including a plurality of semiconductor units formed in a semiconductor layer , a mesa portion protruded upward in the semiconductor layer and configured to include an upper face and a side face;', 'a Schottky electrode configured to form a Schottky contact with the semiconductor layer on the upper face of the mesa portion;', 'an insulating film formed continuously on another portion of the Schottky electrode that is nearer to an edge of the upper face than one portion of the Schottky electrode on the upper face of the mesa portion, on the side face of the mesa portion, and on a surface of the semiconductor layer other than the mesa portion; and', 'a wiring electrode formed on the Schottky electrode and the insulating film, wherein, 'each of the semiconductor units comprisingan angle between the side face of the mesa portion and the surface of the semiconductor layer is not less than 85 degrees and not ...

Bidirectional Switch with Passive Electrical Network for Substrate Potential Stabilization

A device includes a semiconductor body having an active region and a substrate region that is beneath the active region. A bidirectional switch is formed in the semiconductor body having first and second gate structures that are configured to block voltage across two polarities as between first and second input-output terminals that are in ohmic contact with the electrically conductive channel. First and second switching devices are configured to electrically connect the substrate region to the first and second input-output terminals, respectively. A passive electrical network includes a first capacitance connected between a control terminal of the first switching device and the second input-output terminal and a second capacitance connected between a control terminal of the second switching device and the first input-output terminal. The passive electrical network is configured temporarily electrically connect the substrate region to the first and second input-output terminal at different voltage conditions. 1. A semiconductor device , comprising:a semiconductor body comprising an active region and a substrate region that is disposed beneath the active region,a bidirectional switch formed in the semiconductor body and configured to block voltage across two polarities, the bidirectional switch comprising: first and second gate structures that are each configured to control a conductive state of an electrically conductive channel that is disposed in the upper active region, and first and second input-output terminals that are each in ohmic contact with the electrically conductive channel;a first switching device configured to electrically connect the substrate region to the first input-output terminal;a second switching device configured to electrically connect the substrate region to the second input-output terminal;a passive electrical network comprising a first capacitance and a second capacitance, the first capacitance being connected between a control terminal ...

PLASMA PROTECTION DIODE FOR A HEMT DEVICE

A silicon substrate having a III-V compound layer disposed thereon is provided. A diode is formed in the silicon substrate through an ion implantation process. The diode is formed proximate to an interface between the silicon substrate and the III-V compound layer. An opening is etched through the III-V compound layer to expose the diode. The opening is filled with a conductive material. Thereby, a via is formed that is coupled to the diode. A High Electron Mobility Transistor (HEMT) device is formed at least partially in the III-V compound layer. 1. A semiconductor device , comprising:a transistor device disposed at least partially over a III-V compound layer;a conductive via disposed below the transistor; and a first doped portion that is disposed below and electrically coupled to the via; and', 'a second doped portion that surrounds the first doped portion except an upper surface of the first doped portion, wherein the first doped portion and the second doped portion have different types of conductivity., 'a diode electrically coupled to the transistor through the conductive via, wherein the diode includes2. The semiconductor device of claim 1 , wherein:the transistor includes a source, a drain, and a gate;the gate is disposed between the source and the drain in a top view; anda portion of the gate extends beyond the source and the drain in the top view.3. The semiconductor device of claim 2 , wherein at least a portion of the source and the drain are located within the III-V compound layer.4. The semiconductor device of claim 1 , wherein:the diode is under reverse bias when an amount of plasma charge of the transistor is below a threshold; andthe diode turns on when the amount of plasma charge exceeds the threshold, thereby diverting the plasma charge to a substrate surrounding the diode.5. The semiconductor device of claim 1 , wherein the conductive via is in direct contact with a gate of the transistor.6. The semiconductor device of claim 1 , wherein the ...

Semiconductor device

A semiconductor device includes a first nitride semiconductor layer having a first region, a second nitride semiconductor layer that is on the first nitride semiconductor layer and contains carbon and silicon, a third nitride semiconductor layer that is on the second nitride semiconductor layer and has a second region, a fourth nitride semiconductor layer on the third nitride semiconductor layer, the fourth nitride semiconductor layer having a band gap that is wider than a band gap of the third nitride semiconductor layer, a source electrode that is on the fourth nitride semiconductor layer and is electrically connected to the first region, a drain electrode that is on the fourth nitride semiconductor layer and is electrically connected to the second region, and a gate electrode that is on the fourth nitride semiconductor layer and is between the source electrode and the drain electrode.

HETEROJUNCTION BIPOLAR TRANSISTOR AND SEMICONDUCTOR DEVICE

A first sub-collector layer functions as an inflow path of a collector current that flows in a collector layer of a heterojunction bipolar transistor. A collector ballast resistor layer having a lower doping concentration than the first sub-collector layer is disposed between the collector layer and the first sub-collector layer. 1. A heterojunction bipolar transistor comprising:a collector layer;a base layer;an emitter layer;a first sub-collector layer functioning as an inflow path of a collector current that flows in the collector layer; anda collector ballast resistor layer disposed between the collector layer and the first sub-collector layer and having a lower doping concentration than the first sub-collector layer.2. The heterojunction bipolar transistor according to claim 1 , further comprising:a second sub-collector layer disposed between the collector ballast resistor layer and the collector layer and having a higher doping concentration than each of the collector layer and the collector ballast resistor layer.3. The heterojunction bipolar transistor according to claim 1 , wherein the collector ballast resistor layer includes a semiconductor layer containing AlGaAs or GaAs as a main component.4. The heterojunction bipolar transistor according to claim 3 , whereinthe collector layer is formed of GaAs,the collector ballast resistor layer includes a first collector ballast resistor layer and a second collector ballast resistor layer that is disposed between the first collector ballast resistor layer and the first sub-collector layer,the second collector ballast resistor layer is formed of AlGaAs, anda composition of the first collector ballast resistor layer is changed from AlGaAs to GaAs in a direction from the second collector ballast resistor layer toward the collector layer.5. The heterojunction bipolar transistor according to claim 1 , further comprising:an emitter ballast resistor layer that is disposed on a side opposite to the base layer as viewed from ...

TRANSISTOR CONNECTED DIODES AND CONNECTED III-N DEVICES AND THEIR METHODS OF FABRICATION

A transistor connected diode structure is described. In an example, the transistor connected diode structure includes a group III-N semiconductor material disposed on substrate. A raised source structure and a raised drain structure are disposed on the group III-N semiconductor material. A mobility enhancement layer is disposed on the group III-N semiconductor material. A polarization charge inducing layer is disposed on the mobility enhancement layer, the polarization charge inducing layer having a first portion and a second portion separated by a gap. A gate dielectric layer disposed on the mobility enhancement layer in the gap. A first metal electrode having a first portion disposed on the raised drain structure, a second portion disposed above the second portion of the polarization charge inducing layer and a third portion disposed on the gate dielectric layer in the gap. A second metal electrode disposed on the raised source structure. 1. A transistor connected diode structure , comprising:a group III-nitride (III-N) semiconductor material disposed on a substrate;a raised source structure and a raised drain structure disposed on the group III-N semiconductor material;a mobility enhancement layer disposed on the group III-N semiconductor material, between the raised source structure and the raised drain structure;a polarization charge inducing layer disposed on the mobility enhancement layer between the raised source structure and the raised drain structure, the polarization charge inducing layer having a first portion and a second portion separated by a gap;a gate dielectric layer disposed on the mobility enhancement layer in the gap;a first metal electrode having a first portion disposed on the raised drain structure, a second portion disposed above the second portion of the polarization charge inducing layer and a third portion disposed on the gate dielectric layer in the gap; anda second metal electrode disposed on the raised source structure.2. The ...

Transistors and fabrication method thereof

A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate, and forming a quantum well layer on the semiconductor substrate. The method also includes forming a potential energy barrier layer on the semiconductor substrate, and forming an isolation structure to isolate different transistor regions. Further, the method includes patterning the transistor region to form trenches by removing portions of the quantum well layer and the potential energy barrier layer corresponding to a source region and a drain region, and filling trenches with a semiconductor material to form a source and a drain. Further, the method also includes forming a gate structure on a portion of the quantum well layer and the potential energy barrier layer corresponding to a gate region.

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

A method of forming a semiconductor device including a semiconductor substrate having a first surface and a second surface, and having a gallium nitride-containing layer provided on the first surface of the semiconductor substrate includes grinding, polishing, and etching the second surface of the semiconductor substrate of which a thickness is d1, and reducing the thickness of the semiconductor substrate to one-fifth or less of d1. 1. A method of forming a semiconductor device including a semiconductor substrate having a first surface and a second surface , and having a gallium nitride-containing layer provided on the first surface of the semiconductor substrate , comprising:grinding, polishing, and etching the second surface of the semiconductor substrate of which a thickness is dl; andreducing the thickness of the semiconductor substrate to one-fifth or less of dl,wherein an amount of polishing is between ½ and 1/50 of an amount of grinding, and an amount of etching is between 1/200 and 1/5000 of the amount of grinding.2. The method according to claim 1 ,wherein a surface roughness Ra of the second surface of the semiconductor substrate after grinding, polishing, and etching the second surface of the semiconductor substrate is 0.006 μm or greater and 0.008 μm or less.3. The method according to claim 1 ,wherein a total thickness of the semiconductor substrate after grinding, polishing, and etching the second surface of the semiconductor substrate and the gallium nitride-containing layer is 25 μm or less per 1 inch of a diameter of the semiconductor substrate.4. The method according to claim 1 ,wherein after grinding, polishing, and etching the second surface of the semiconductor substrate, the semiconductor substrate is mounted on a planar support stand, and a difference between a height of a center of the semiconductor substrate from the support stand and a height of an end of the semiconductor substrate from the support stand is 150 μm or less.5. The method ...

Semiconductor device with multiple hbts having different emitter ballast resistances

The present disclosure relates to a semiconductor device with multiple heterojunction bipolar transistors (HBTs) that have different emitter ballast resistances. The disclosed semiconductor device includes a substrate, a first HBT and a second HBT formed over the substrate. The first HBT includes a first collector, a first base over the first collector, a first emitter over the first base, and a first cap structure over the first emitter. The second HBT includes a second collector, a second base over the second collector, a second emitter over the second base, and a second cap structure over the second emitter. Herein, the first cap structure is different from the second cap structure, such that a first emitter ballast resistance from the first cap structure is at least 1.5 times greater than a second emitter ballast resistance from the second cap structure.

SILICON CARBIDE SEMICONDUCTOR DEVICE

A silicon carbide semiconductor device includes a transistor region, a diode region, a gate line region, and a gate pad region. The gate pad region and the gate line region are each disposed to be sandwiched between the diode region and the diode region, and a gate electrode on the gate pad region and the gate line region is formed on an insulating film formed on an epitaxial layer. Thus, breakdown of the insulating film in the gate region can be prevented without causing deterioration in quality of the gate insulating film, upon switching and avalanche breakdown. 1. A silicon carbide semiconductor device comprising , a laminated structure that includes a first conductive type semiconductor substrate , a first conductive type first silicon carbide semiconductor layer located on a main surface of the semiconductor substrate , and a first ohmic electrode located on a back surface of the semiconductor substrate , the laminated structure including a transistor region , a termination region , and a diode region , each region including a part of the semiconductor substrate , a part of the first silicon carbide semiconductor layer , and a part of the first ohmic electrode , wherein the termination region surrounds the transistor region and the diode region is located between the termination region and the termination region as viewed in a direction perpendicular to the main surface of the semiconductor substrate ,whereinthe transistor region includes a plurality of unit cell regions,the silicon carbide semiconductor device comprises:in each of the unit cell regions,a second conductive type first well region located in a part of the first silicon carbide semiconductor layer;a first conductive type source region located in the first well region;a second silicon carbide semiconductor layer formed on a part of the first silicon carbide semiconductor layer so as to be in contact with at least a part of the first well region and a part of the source region, the second silicon ...

RESISTOR AND RESISTOR-TRANSISTOR-LOGIC CIRCUIT WITH GAN STRUCTURE AND METHOD OF MANUFACTURING THE SAME

A resistor-transistor-logic (RTL) circuit with GaN structure, including a GaN layer, a AlGaN barrier layer on the GaN layer, multiple p-type doped GaN capping layers on the AlGaN barrier layer, wherein parts of the p-type doped GaN capping layers in a high-voltage region and in a low-voltage region convert the underlying GaN layer into gate depletion areas, the GaN layer not covered by the p-type doped GaN capping layers in a resistor region becomes a 2DEG resistor. 1. A resistor-transistor-logic circuit with GaN structures , comprising:a GaN layer with a high-voltage device region, a low-voltage device region and a resistor region;an AlGaN barrier layer on said GaN layer;multiple p-type doped GaN capping layers on said AlGaN barrier layer, wherein parts of said p-type doped GaN capping layers in said high-voltage device region and said low-voltage device region convert said GaN layer under said parts of said p-type doped GaN capping layers into gate depletion regions, said GaN layer not covered by said p-type doped GaN capping layers in said resistor region functions as a 2DEG resistor;multiple first gates, wherein each of said first gates is formed on one of said p-type doped GaN capping layers in said high-voltage device region;multiple first sources and first drains formed on said GaN layer in said high-voltage device region, wherein said first gates, said first sources and said first drains constitute high-voltage HEMTs;multiple second gates, wherein each of said second gates is formed on one of said p-type doped GaN capping layers in said low-voltage device region; andmultiple second sources and second drains formed on said GaN layer in said low-voltage device region, wherein said second gates, said second sources and said second drains constitute low-voltage logic FETs.2. The resistor-transistor-logic circuit with GaN structures of claim 1 , wherein a spacing between said second gate and said second source of said low-voltage logic FET is equal to a spacing ...

Tunneling field effect transistor device and related manufacturing method

A transistor device may include a first source portion including a first InSb material set and a first first-type dopant set. The transistor device may include a first drain portion including a second InSb material set and a first second-type dopant set. The transistor device may include a first gate and a corresponding first channel portion disposed between the first source portion and the first drain portion and including a third InSb material set. The transistor device may include a second drain portion including a first GaSb material set and a second first-type dopant set. The transistor device may include a second source portion including a second GaSb material set and a second second-type dopant set. The transistor device may include a second gate and a corresponding second channel portion disposed between the second source portion and the second drain portion and including a third GaSb material set.

ELECTRONIC DEVICES INCLUDING VERTICAL MEMORY CELLS AND RELATED METHODS

An electronic device comprises an array of memory cells comprising a channel material laterally proximate to tiers of alternating conductive materials and dielectric materials. The channel material comprises a heterogeneous semiconductive material varying in composition across a width thereof. Related electronic systems and methods are also disclosed. 1. An electronic device , comprising:an array of memory cells comprising a channel material laterally proximate to tiers of alternating conductive materials and dielectric materials, the channel material comprising a heterogeneous semiconductive material varying in composition across a width thereof.2. The electronic device of claim 1 , wherein the heterogeneous semiconductive material comprises a heterogeneous structure comprising two or more different materials that each individually exhibit a substantially homogeneous composition.3. The electronic device of claim 1 , wherein the heterogeneous semiconductive material comprises a single semiconductive material comprising two or more elements claim 1 , wherein atomic concentrations of the two or more elements of the single semiconductive material vary across the width of the heterogeneous semiconductive material.4. The electronic device of claim 1 , wherein the heterogeneous semiconductive material comprises one or more of a nitride-containing material claim 1 , an oxide-containing material claim 1 , a semiconductive sulfide material claim 1 , a semiconductive selenide material claim 1 , a semiconductive phosphide material claim 1 , a semiconductive arsenide material claim 1 , a semiconductive telluride material claim 1 , and a semiconductive antimonide material.5. The electronic device of claim 1 , wherein the heterogeneous semiconductive material comprises one or more of boron nitride claim 1 , aluminum nitride claim 1 , gallium nitride claim 1 , indium nitride claim 1 , gallium arsenide nitride claim 1 , aluminum gallium nitride claim 1 , indium gallium nitride ...

LOW RESISTANCE SOURCE/DRAIN REGIONS IN III-V TRANSISTORS

Low resistance source/drain regions in III-V transistors are disclosed. More particularly, a source and a drain are formed from heavily doped III-V materials that have lower resistances than a barrier layer and/or a cap layer under the drain. In an exemplary aspect, the barrier and cap layers are formed over a mobility channel layer and then etched to form source and drain recesses. A source and a drain are then epitaxially grown in the recesses. The source and the drain may include one or more layers, with the top layer having the lowest bandgap, thus helping to lower contact resistance. By lowering the resistance of the source and the drain, the overall resistance of the transistor may be lowered to allow for operation at higher frequencies. 1. A transistor comprising:a substrate having a horizontal axis and a vertical axis;a mobility channel layer positioned above the substrate on the vertical axis;a barrier layer positioned above the mobility channel layer on the vertical axis, the barrier layer comprising a barrier structure, the barrier structure comprising a first side and a second side, the second side facing opposite the first side along the horizontal axis, a shared junction between the barrier layer and the mobility channel layer forming a channel;a source positioned horizontally adjacent to the first side of the barrier structure, the source comprising a first III-V material;a drain positioned horizontally adjacent to the second side of the barrier structure, the drain comprising a second III-V material; anda gate positioned above the barrier structure.2. The transistor of claim 1 , further comprising a cap layer positioned between the gate and the barrier layer.3. The transistor of claim 1 , wherein the mobility channel layer comprises a III-V material.4. The transistor of claim 3 , wherein the mobility channel layer comprises an undoped Gallium Nitride (GaN) material.5. The transistor of claim 1 , wherein the mobility channel layer comprises the first ...

EPITAXIAL STRUCTURE OF N-FACE GROUP III NITRIDE, ACTIVE DEVICE, AND GATE PROTECTION DEVICE THEREOF

The present invention relates to an epitaxial structure of N-face group III nitride, its active device, and its gate protection device. The epitaxial structure of N-face AlGaN/GaN comprises a silicon substrate, a buffer layer (C-doped) on the silicon substrate, an i-GaN (C-doped) layer on the buffer layer (C-doped), an i-AlGaN buffer layer on the i-GaN (C-doped) layer, an i-GaN channel layer on the i-AlGaN buffer layer, and an i-AlGaN layer on the i-GaN channel layer, where x=0.1˜0.3 and y=0.05˜0.75. By connecting a depletion-mode (D-mode) AlGaN/GaN high electron mobility transistor (HEMT) to the gate of a p-GaN gate enhancement-mode (E-mode) AlGaN/GaN HEMT in device design, the gate of the p-GaN gate E-mode AlGaN/GaN HEMT can be protected under any gate voltage. 1. An epitaxial structure of enhancement-mode (E-mode) N-face AlGaN/GaN high electron mobility transistor (HEMT) with polarity inversion , comprising:an epitaxial structure of N-face AlGaN/GaN; andan etched p-GaN gate structure, located on said epitaxial structure of N-face AlGaN/GaN, the two-dimensional electron gas (2DEG) below said etched p-GaN gate structure being depleted;where said epitaxial structure of N-face AlGaN/GaN includes:a silicon substrate;a buffer layer (C-doped), located on the silicon substrate;an i-GaN (C-doped) layer, located on the buffer layer (C-doped);{'sub': 'y', 'an i-AlGaN buffer layer, located on the i-GaN (C-doped) layer;'}{'sub': 'y', 'an i-GaN channel layer, located on the i-AlGaN buffer layer, said 2DEG formed in said i-GaN channel layer; and'}{'sub': x', 'x, 'an i-AlGaN layer, located on the i-GaN channel layer, where x=0.1˜0.3 and y=0.05˜0.75, and the N-face of said i-AlGaN layer moving the 2DEG located below said i-GaN channel layer to the top of said i-GaN channel layer by polarity inversion.'}2. The epitaxial structure of E-mode N-face AlGaN/GaN HEMT with polarity inversion of claim 1 , wherein an i-AlGaN grading buffer layer is added between said i-GaN (C-doped) layer ...

WAFER LEVEL INTEGRATION INCLUDING DESIGN/CO-DESIGN, STRUCTURE PROCESS, EQUIPMENT STRESS MANAGEMENT, AND THERMAL MANAGEMENT

A multi-layer wafer and method of manufacturing such wafer are provided. The method comprises applying a stress compensating oxide layer to each of two heterogeneous wafers, applying at least one bonding oxide layer to at least one of the two heterogeneous wafers, chemical-mechanical polishing the at least one bonding oxide layer, and low temperature bonding the two heterogeneous wafers to form a multi-layer wafer pair. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafers having a stress compensating oxide layer and at least one bonding oxide layer applied to at least one of the two heterogeneous wafers. The two heterogeneous wafers are low temperature bonded together to form the multi-layer wafer. 114-. (canceled)15. A multi-layer wafer comprising:two heterogeneous wafers, each of the heterogeneous wafers having a stress compensating oxide layer;at least one bonding oxide layer applied to at least one of the two heterogeneous wafers;the two heterogeneous wafers low temperature bonded together to form the multi-layer wafer.16. The multi-layer wafer of claim 15 , wherein each of the two heterogeneous wafers are formed from at least one of: complementary metal-oxide semiconductor (CMOS) and GaN on Si claim 15 , CMOS and glass claim 15 , CMOS and sapphire claim 15 , CMOS and SiC on Si claim 15 , CMOS and diamond on Si claim 15 , or CMOS and sapphire on Si.17. The multi-layer wafer of claim 15 , wherein the stress compensating oxide layer is comprised of tetraethyl orthosilicate (TEOS).18. The multi-layer wafer of claim 15 , wherein each stress compensating oxide layer comprises a different stoichiometric SiOx deposition.19. The multi-layer wafer of claim 15 , further comprising islands of heterogeneous material in at least one heterogeneous wafer formed by at least one of depositing or growing the heterogeneous material.20. The multi-layer wafer of claim 19 , further comprising:channels between the islands of heterogeneous material ...

HIGH ASPECT RATIO CHANNEL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME

The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface. The semiconductor device further includes a first vertical channel layer laterally interposed between and in contact with the dielectric layer and the dielectric filling layer at a first side of the dielectric filling layer, wherein the first vertical channel layer extends above the common top surface. 1. A method of manufacturing a semiconductor device , the method comprising:forming on a semiconductor substrate a dielectric isolation layer having an opening formed therethrough;forming a fin structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer;forming on the dielectric isolation layer a first vertical channel layer extending along and in contact with a first exposed sidewall of the protruding portion of the fin structure, wherein the first vertical channel layer comprises a first channel material different from the material of the fin structure;forming a dielectric layer on the dielectric isolation layer and contacting the first vertical channel layer, wherein the dielectric layer has a top surface that is vertically lower than a top surface of the first vertical channel layer;removing at least ...