ПОЛУПРОВОДНИКОВЫЙ ПРИБОР ДЛЯ БЕЗОПАСНОГО ЭЛЕКТРОННОГО ЭЛЕМЕНТА

Изобретение относится к коммутационной технике и может быть использовано в устройствах автоматики и телемеханики. Изобретение позволяет получить полупроводниковые приборы для безопасных электронных элементов. Сущность изобретения: в полупроводниковом приборе, содержащем кристалл со структурно интегрированными пассивными и активными компонентами, полевой транзистор с обеднением канала, диод сток-подложка и высокоомный резистор интегрированы в структуру кристалла так, что обрыв электрических соединений его внутренних компонентов является невозможной неисправностью. В другом варианте полупроводникового прибора для безопасного электронного элемента, по крайней мере, одной контактной площадке кристалла соответствуют два внешних вывода полупроводникового прибора, каждый из которых связан с контактной площадкой кристалла несоприкасающимися друг с другом перемычками. 2 н.п. ф-лы, 4 ил.

Устройство для управления фазовой и групповой скоростью поверхностной электромагнитной волны инфракрасного диапазона на основе тонкой пленки полупроводника с графеновыми обкладками

Полезная модель относится к области оптоэлектроники и плазмоники. Устройство для управления фазовой и групповой скоростью поверхностной электромагнитной волны инфракрасного диапазона на основе тонкой пленки полупроводника с графеновыми обкладками содержит источник излучения, поляризатор, глухое зеркало, призму ввода, блок управления, внешний источник напряжения и симметричную волноводную структуру, представляющую собой тонкую полупроводниковую пленку, помещенную между двумя одинаковыми диэлектрическими немагнитными обкладками, на каждой границе раздела волноводной структуры «диэлектрик-полупроводниковая пленка» присутствуют монослои графена, на которых с помощью внешнего источника напряжения и блока управления подается разность потенциалов, определяющая концентрацию носителей в каждом из слоев графена и, как следствие, их электрическую проводимость, изменение которой приводит к изменению фазовой и групповой скорости распространяющейся в волноводной структуре поверхностной волны. Технический ...

ПОДЛОЖКА ДЛЯ КАСКАДНЫХ СОЛНЕЧНЫХ ЭЛЕМЕНТОВ

... 1. Подложка для каскадных солнечных элементов, содержащая тонкую базисную часть в виде изолирующей пластинки, отличающаяся тем, что на ней сформирована монокристаллическая пленка германия толщиной не более 5 мкм, причем пленка в плоскости имеет полосковое строение, в котором непокрытые участки подложки (просветы) занимают не более 5% от общей площади подложки, а ширина просветов не превосходит 5 мкм. ! 2. Подложка по п.1, отличающаяся тем, что монокристаллическая пленка германия сформирована путем ее осаждения на подложку и последующей перекристаллизации. ! 3. Подложка по п.1, отличающаяся тем, что германиевые полоски имеют форму прямоугольников, причем перпендикулярно им нанесены прямоугольные электроконтактные площадки с шириной, равной ширине германиевых полосок, на расстояниях друг от друга, превосходящих ширину полосок не менее чем в 10 раз. ! 4. Подложка по п.3, отличающаяся тем, что электроконтактные площадки проходят по нижней поверхности полосок, между германием и исходной пластинкой ...

Vorrichtung zum Abaetzen von Halbleiterkoerpern fuer Transistoren oder kugelfoermiger Gestalt

Field effect transistor having increased carrier mobility

Improvements in or relating to electrical asymmetrical conducting devices having a crystalline semi-conductor

... 780,260. Semi-conductor devices. TELEFUNKEN GES. June 17, 1954 [June 17, 1953], No. 17767/54. Class 37. A PN junction is produced by plunging a portion of a semi-conductor crystal 7, such as germanium of one conductivity type, into a melted mass 9 of impurity characteristic of the opposite conductivity type. The impurity material, which may be indium, may be melted by passing current through a support electrode 10. The inserted portion of the semi-conductor is pointed. The invention enables the extent of diffusion and the area of the PN junction to be controlled.

Improvements in and relating to semi-conductive devices

... 863,612. Transistors. MULLARD Ltd. May 21, 1957, No. 16102/57. Class 37. A method of making a semi-conductor device comprises the steps of diffusing a first impurity into a semi-conductor crystal to form a relatively thick diffused layer therein, removing material from part of the crystal to a depth extending through, or through at least 70% of the diffused layer, and diffusing into the new surface thus formed a second impurity characteristic of the same conductivity type, and possibly of the same material, as the first, to produce a relatively thin diffused layer beneath the new surface. Diffusion of the second impurity may be from an applied layer or pellet, from the atmosphere, or from the first-diffused layer, and a point contact can be made to the new surface after the second diffusion step. As shown, Fig. 1, in the manufacture of a PNP transistor, a slice 1 of P-type monocrystalline germanium is heated at 830‹ C. for about 2 hours in a current of hydrogen in a chamber containing a ...

Improvements in or relating to semi-conductor arrangements and methods of producing such arrangements

... 896,730. Transistors. SIEDMENS & HALSKE A.G. Jan. 21, 1960 [Jan. 27, 1959], No. 2299/60. Class 37. A unipolar transistor comprises a body of one conductivity type with a surface layer of opposite conductivity type and of higher resistivity, formed by impurity diffusion, spaced portions of which are provided with ohmic contacts. In the embodiments a further layer of the same conductivity type as the body is provided on the first layer between the ohmic contacts. In one embodiment the first layer, which is a P-type layer 9 (Fig. 5), on a circular N-type disc 4 is provided with a central ohmic electrode 1, annular ohmic electrode 2, and an annular N-type layer beneath electrode 3. In another arrangement a P-type layer 9 surrounding an N-type cylinder (Fig. 4a) is provided with an annular N-type layer associated with electrode 3, and annular ohmic electrodes 2. Alternatively (Fig. 4b) the N- type layer extends the full length of the cylinder, in which case washer shaped ohmic contacts are provided ...

SEMICONDUCTOR ARRANGEMENT WITH LOWERED SURFACE FIELD STRENGTH

PROTECTION DIODE TO THE PROTECTION OF SEMICONDUCTOR CIRCUITS AGAINST ELECTROSTATIC UNLOADINGS

HIGH VOLTAGE SEMICONDUCTOR ARRANGEMENT CONCLUSION

SEMICONDUCTOR ARRANGEMENT.

INFRARED-OPTO-ELECTRONIC CONSTRUCTION UNIT.

PROCEDURE FOR SIMULTANEOUS MANUFACTURING OF SNAPPING SHORT CHANNEL AND TENSION CELEBRATIONS MOS TRANSISTORS IN VLSI CIRCUITS.

PROCEDURE FOR MANUFACTURING A HIGHLY INTEGRATED READ-ONLY MEMORY.

DUENNFILMTRANSISTOR.

TRANSISTOR STRUCTURE.

SEMICONDUCTOR HETEROSTRUCTURE.

PROCEDURE FOR THE PRODUCTION OF A BIPOLAR TRANSISTOR.

SEMICONDUCTOR ARRANGEMENT WITH A BIPOLAR TRANSISTOR AND A MOS TRANSISTOR AND PROCEDURE FOR THEIR PRODUCTION.

Thyristor

THYRISTOR

Unipolar strengthening planar transistor

PROCEDURE FOR THE USE OF A SEMICONDUCTOR ARRANGEMENT WITH A SUBSTRATE, WHICH EXHIBITS A DIELECTRICALLY INSULATING SEMICONDUCTOR ISLAND

IMPROVEMENTS IN PLANAR P-N JUNCTIONS

Elektrodensystem unsymmetrischer Leitfähigkeit.

Kristallkontakteinrichtung.

Transistron unipolaire

Steuerbarer Gleichrichter

Dispositif électronique comprenant un corps en matière semi-conductrice

Elément semi-conducteur cristallin à plusieurs électrodes et procédé de fabrication de cet élément.

Verfahren zur Herstellung eines Germaniumkontaktes für Kristallkontaktvorrichtungen.

Flächentransistor

Unipolartransistor und Verfahren zur Herstellung desselben

Verfahren zur Herstellung einer Halbleitervorrichtung

Hermetisch abgedichtete Halbleiteranordnung und Verfahren zu ihrer Herstellung

Verfahren zur Herstellung eines Transistors

Soupape commandée, à semi-conducteur monocristallin

Verfahren zur Herstellung von Halbleiterscheiben

Utilisation d'un transistor unipolaire à effet de champ

Dispositif semi-conducteur photosensible et procédé de fabrication dudit dispositif

Verfahren zur Herstellung einer Halbleitervorrichtung

THYRISTOR WITH ANODE TRANSVERSE FIELD EMITTER.

POWER SEMICONDUCTOR ELEMENT WITH ZONE GUARD RINGS.

INTEGRATED SEMICONDUCTOR DEVICE WITH TREIBERTRANSISTOR.

WITHOUT SPERRVERZOEGERUNG DISCONNECTIBLE THYRISTOR.

PROCEDURES FOR MANUFACTURING HALBLEITERKOERPERN WITH DEFINING, BY AETZEN OBTAINED AND COVERING EDGE PROFILE WITH A GLASS.

ACHIEVEMENT THYRISTOR AND PROCEDURE FOR ITS PRODUCTION.

INFRARED LIGHT RADIATING DEVICE.

ACHIEVEMENT THYRISTOR, PROCEDURE FOR ITS PRODUCTION AND USE OF SUCH THYRISTORS IN STATIC INVERTER CIRCUITS.

SEMICONDUCTOR DEVICE, IN PARTICULAR DISCONNECTIBLE THYRISTOR.

HIGH CURRENT MOS FIELD-EFFECT TRANSISTOR.

PROCEDURE FOR THE PRODUCTION OF A SEMICONDUCTOR ARRANGEMENT.

HIGH VOLTAGE SEMICONDUCTOR DEVICE.

SEMICONDUCTOR COMPONENT.

Arrangement for the characteristic improvement of semiconductor structures provided with P/N transitions.

Semiconductor device.

Semiconductor device.

SEMICONDUCTOR COMPONENT.

BIPOLAR, OVER A GATE DISCONNECTIBLE POWER SEMICONDUCTOR ELEMENT.

PROCEDURE FOR THE ATTACHMENT OF A TAPERED EDGE OUTLINE AT A DISK.

SEMICONDUCTOR COMPONENT AS WELL AS PROCEDURE FOR ITS PRODUCTION.

SEMICONDUCTOR COMPONENT AS WELL AS PROCEDURE FOR ITS PRODUCTION.

SEMICONDUCTOR COMPONENT.

SEMICONDUCTOR COMPONENT AND PROCEDURE FOR ITS PRODUCTION.

DISCONNECTIBLE POWER SEMICONDUCTOR ELEMENT.

Semiconductor switching mechanism.

Vertical double-diffusion MOS transistor structure

The invention provides a vertical double-diffusion MOS transistor structure and belongs to the field of semiconductor devices. The vertical double-diffusion MOS transistor structure comprises a semiconductor substrate, an epitaxial layer, a source doped area, a channel area, a gate oxide layer and a polysilicon gate; moreover, a thick insulating layer is arranged between the polysilicon gate and the epitaxial layer at positions beside the channel area in a horizontal direction; and due to the introduction of the insulating layer, the relative distance between the polysilicon gate and the epitaxial layer is increased, namely the distance between two polar plates of a gate-drain capacitor is increased, so that under conditions of not changing the area of the polysilicon gate and not increasing the on resistance of the device, the gate-drain capacitor of the device is effectively reduced, the electrical charging-discharging time of the gate-drain capacitor in a process of opening or closing ...

Trench gate SOI LIGBT device

The invention discloses a groove-gate SOI LIGBT device, and relates to semiconductor power device technologies. The groove-gate SOI LIGBT device comprises a substrate, a buried oxide layer, an N-type buffer layer, an anode P<+> region, an anode metal, an N-type drift region, a field oxide layer, a front metal dielectric layer, a P<+> region, an N<+> region, a polysilicon groove gate, an LIGBT device gate oxide layer, a P-type channel region, a polysilicon groove-gate metal and a cathode metal, the cathode metal is connected with the P<+> region and the N<+> region, and the P<+> region 10 is arranged between the N<+>region 11 and the anode P<+> region 4. The groove-gate SOI LIGBT device reduces the electric field intensity around the gate oxide layer, prevents a hot carrier from being implanted into the gate oxide, and improves the reliability of the device.

Semiconductor device

Thin-film transistor substrate, electronic device and preparation method thereof

The invention discloses a thin-film transistor substrate, which comprises a backing material, and at least one thin-film transistor arranged on the backing material; wherein the thin-film transistor comprises a semiconductor island and at least one grid electrode. The semiconductor island has a source electrode region, a drain electrode region, a passage region positioned therebetween, and a plurality of secondary grain boundaries. In a region of the grid electrode corresponding to the passage region, a first included angle, which is substantially not a 90 DEG C, is formed between a line for connecting the source electrode region center with the drain electrode region center and an extension direction of the grid electrode, and a second included angle, which is substantially not a 0 or 90 DEG C, is formed between a line for connecting the source electrode region center with the drain electrode region center and the secondary grain boundaries of the passage region. In addition, the invention ...

IC with complementary heterojunction field effect transistors

Ce circuit comporte une hétérojonction formée entre une couche (6) Alx Ga1 - x As (ou Alz In1 - z As) et une couche (5) Gay In1 - y As et défi nissant, au niveau de la couche Gay In1 - y As, un puits quantique comportant des sous-bandes de type HH et LH, Selon l'invention, la composition de Gay In1 - y As est choisie de manière que la séparation en énergie des sous-bandes HH1 , HH2 et LH1 , soit telle que le peuplement de la sous-bande LH1 , soit essentiellement négligeable et que le courant de fuite de grille du transistor à canal p soit essentiellement indépendant des trous lourds HH1 et HH2 de faible transparence tunnel, et l'épaisseur de la couche comprenant Alx Ga1 - x As est choisie plus faible pour le transistor à canal p que pour le transistor à canal n, le rapport de ces épaisseurs respectives étant un rapport prédéterminé fonction de la transparence tunnel relative des trous peuplant les sous-niveaux HH1 et HH2 par rapport à celle des électrons.

METHOD FOR MANUFACTURING SEMICONDUCTOR BODIES EDGE HAS PROFILES OF DEFINITE FORM OBTAINED BY ATTACK CHEMICAL AND PROVIDED With a COATING OUT OF GLASS

THYRISTOR HAS ELECTRODE OF SHORT-CIRCUIT Of TRANSMITTER FOR ORDERING OF COMMUTATION HAS NULL TENSION

GENERATOR OF TENSION OF REFERS AND MEASURING CIRCUIT OF the TENSION OF THRESHOLD Of a TRANSISTOR MOS, APPLICABLE THIS GENERATOR OF TENSION OF REFERS

SEMICONDUCTOR DEVICE OF DEVIATION Of ELECTRONS OF the TYPE “HAS TRANSPORT BALLISTIC”, AND MANUFACTORING PROCESS Of SUCH a DEVICE

Improvements to devices and methods for making same

Thyristor with differently doped base layers - has specified mean impurities concentration in higher doped base layer and matrix of shunt channels of specified width

SEMICONDUCTOR DEVICE HAS TRANSISTOR REMOVING THE PRODUCTION OF STRAY CURRENT

LOGICAL CIRCUIT HAS TRANSISTORS SCHOTTKY

OPTO-ELECTRONIC DETECTOR

HYPERFREQUENCY TRANSISTOR DOUBLE HETEROJUNCTION

STRUCTURE FOR RADIO FREQUENCY APPLICATION

DEVICE TO REMOVE OVERPRESSURES HAS SEMICONDUCTOR, WHOSE TENSION Of STARTING CAN BE PREDETERMINEE WITH PRECISION, AND ITS MANUFACTORING PROCESS

COMPOSITE STRUCTURE HAS HIGH HEAT DISSIPATION

THYRISTOR HAS FIELD EFFECT

Photoconductive member comprising amorphous germanium, amorphous silicon and nitrogen

HBT INSENSITIVE EXTERNAL TEMPERATURE AND ASSOCIATED INTEGRATED CIRCUIT.

METHOD FOR REALIZATION OF STRUCTURES INTO MULTI-LAYER HAS PROPERTIES CONTROLEES

Bipolar integrated circuit pnp transistor - has p-type substrate with p-implantation zones and n-type epitaxial layer

Controlled valve, with single-crystal semiconductor

element semiconductor

Manufactoring process of semiconductor devices

SEMICONDUCTOR DEVICE AND ITS MANUFACTORING PROCESS

DEVICE HAS LOADS COUPLEES HAS TWO PHASES

cHARGE-COUPLED ONEcONSTRUCTION UNIT

TRANSISTOR

Concentric diode with semiconductor

Power transistor for monolithic integrated circuit - has low collector resistance achieved by using two extra domains of opposite conduction type