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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Форма поиска

Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 5682. Отображено 100.
11-07-2017 дата публикации

Вычислительное устройство режектирования помех

Номер: RU0000172504U1

Устройство относится к вычислительной технике и предназначено для выделения сигналов движущихся целей на фоне пассивных помех при групповой перестройке несущей частоты зондирующих импульсов. Достигаемый технический результат - повышение эффективности выделения сигналов движущихся целей. Указанный результат достигается тем, что вычислительное устройство режектирования помех содержит первый и второй блоки задержки, блок весовых коэффициентов, первый и второй комплексные перемножители, весовой блок, комплексный сумматор, блок комплексного сопряжения, блок переключения, блок точности, блок коммутации, двухканальный коммутатор и синхрогенератор, определенным образом соединенные между собой и осуществляющие когерентную обработку исходных отсчетов. 11 ил. Ц 1 172504 ко РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ и, 278 м ил $ хх 5%“ $ < м. п | РЦ ‘’ х я (50) МПК НОЗН 17/06 (2006.01) (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (21)(22) Заявка: 2017111140, 03.04.2017 (24) Дата начала отсчета срока действия патента: 03.04.2017 Дата регистрации: 11.07.2017 Приоритет(ы): (22) Дата подачи заявки: 03.04.2017 (45) Опубликовано: 11.07.2017 Бюл. № 20 Адрес для переписки: 390005, г. Рязань, ул. Гагарина, 59/1, ФГБОУ ВО "РГРТУ", патентная служба (72) Автор(ы): Попов Дмитрий Иванович (КО) (73) Патентообладатель(и): Федеральное государственное бюджетное образовательное учреждение высшего образования "Рязанский государственный радиотехнический университет" (КО) (56) Список документов, цитированных в отчете о поиске: 30 743208, 25.06.1980. КП 2599621 СТ, 10.10.2016. ВП 157117 91, 20.11.2015. 05 5886914 А, 23.04.1999. (54) ВЫЧИСЛИТЕЛЬНОЕ УСТРОЙСТВО РЕЖЕКТИРОВАНИЯ ПОМЕХ (57) Реферат: Устройство относится к вычислительной технике и предназначено для выделения сигналов движущихся целей на фоне пассивных помех при групповой перестройке несущей частоты зондирующих импульсов. Достигаемый технический результат - повышение эффективности выделения сигналов движущихся ...

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30-06-2020 дата публикации

Адаптивный цифровой фильтр для подавления нефлуктуационных помех

Номер: RU0000198305U1

Полезная модель относится к области радиотехники и может быть использована в устройствах цифровой обработки сигналов, проходящих по каналам связи, в которых существует возможность искажения сигналов, связанных с наличием в каналах внешних нефлуктуационных помех. Заявленный адаптивный цифровой фильтр для подавления нефлуктуационных помех, содержащий первый преобразователь комплексной огибающей сигнала в комплексно сопряженную огибающую; первый регистр задержки, состоящий из последовательно соединенных первого, второго, третьего элементов задержки; второй регистр задержки, состоящий из последовательно соединенных четвертого, пятого, шестого элементов задержки; первый, второй и третий перемножители выходных сигналов первого регистра задержки с весовыми коэффициентами; первый сумматор; первый, второй и третий интеграторы; пятый, шестой и седьмой перемножители выходных сигналов второго регистра задержки с сигналом первой схемы адаптивной подстройки весовых коэффициентов, состоящей из последовательно соединенных блока вычисления производной, первого блока вычисления модуля, второго сумматора с напряжением -G и четвертого перемножителя с напряжением -d1, предложенный фильтр характеризуется тем, что включает второй преобразователь комплексной огибающей сигнала в комплексно сопряженную огибающую, вход которого соединен с выходом первого сумматора и с входом третьего регистра задержки, состоящего из последовательно соединенных седьмого, восьмого, девятого элементов задержки, выходы которых соединены с первыми входами восьмого, девятого и десятого перемножителей выходных сигналов третьего регистра задержки с весовыми коэффициентами, при этом выходы указанных перемножителей соединены с входами третьего сумматора, выход которого является выходом устройства и одновременно - входом второй схемы адаптивной подстройки весовых коэффициентов, содержащей последовательно соединенные второй блок вычисления модуля, блок возведения в квадрат, четвертый сумматор, на второй вход которого ...

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12-01-2012 дата публикации

Nicam decoder with output resampler

Номер: US20120008724A1
Принадлежит: THAT Corp

A NICAM audio signal re-sampler may include a non-linear interpolator configured to interpolate in a non-linear manner between sequential digital samples that are based on a stream of demodulated NICAM audio samples. A phase differential calculator may be included that compares phase information at different resolutions.

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16-02-2012 дата публикации

Multi-Branch Rate Change Filter

Номер: US20120041995A1
Автор: Pierre-Andre Laporte
Принадлежит: Individual

The present invention relates to a rate change filter having multiple branches. The multi-branch rate change filter of the present invention achieves higher effective output rates by processing the input sample stream in two or more parallel filter branches with offset states.

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29-03-2012 дата публикации

Scaled signal processing elements for reduced filter tap noise

Номер: US20120076195A1
Принадлежит: Vintomie Networks BV LLC

An adaptive transversal filter having tap weights Wj which are products of corresponding tap coefficients C j and tap gains M j is provided. A filter control loop controls all of the tap coefficients C j such that an error signal derived from the filter output is minimized. One or more tap control loops controls a tap gain M k such that the corresponding tap coefficient C k satisfies a predetermined control condition. For example, |C k | can be maximized subject to a constraint |C k | C max , where C max is a predetermined maximum coefficient value. In this manner, the effect of quantization noise on the coefficients C j can be reduced. Multiple tap control loops can be employed, one for each tap. Alternatively, a single tap control loop can be used to control multiple taps by time interleaving.

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07-06-2012 дата публикации

Down sampling method and down sampling device

Номер: US20120142302A1
Принадлежит: Huawei Device Co Ltd

In the field of communications technologies, a down sampling method and a down sampling device are provided, to enable the energy of a down sampling point obtained in down sampling to be as large as possible. The down sampling method includes: extracting energy statistical values of sampling point sets in a current period; selecting a sampling position corresponding to a sampling point set with the largest energy statistical value as a down sampling position; and performing down sampling according to the down sampling position.

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19-07-2012 дата публикации

Multi-Rate Implementation Without High-Pass Filter

Номер: US20120185524A1
Автор: Jeffrey Clark
Принадлежит: Individual

A filtering method approximates a target Finite Impulse Response (FIR) (or transversal) filter and reduces computational requirements by eliminating high pass filtering required by known multi-rate filters. An input signal is copied into two identical signals and processed in parallel by a full-rate path, and by a reduced-rate path. Parallel filters are computed and applied in each path, the reduced-rate signal is up-sampled, and the two signals summed. The high pass filter required by known multi-rate filters is eliminated and the low pass filter in the prior art is implicit in a down sampling. Linear phase FIR filters are used for down and up sampling, resulting in constant group delay. Added benefits include the option of zero added latency through the filtering and the constant group delay added to the target FIR. The user may choose criteria such as minimum resolution in each band.

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16-08-2012 дата публикации

Reducing steady state error in fixed point implementations of recursive filters

Номер: US20120207200A1
Автор: Vignesh Sethuraman
Принадлежит: Qualcomm Inc

One feature includes a method for implementing a fixed point recursive filter that reduces or eliminates steady state error. The method comprises obtaining a first filter state value, processing the first filter state value to remove a scaling factor to obtain a second filter state value, ascertaining that the recursive filter has reached a steady state, determining a nonlinear drift parameter based on a difference between the first filter state value and the second filter state value multiplied by the scaling factor, and adjusting the second filter state value with the nonlinear drift parameter to reduce steady state error of the recursive filter. Ascertaining that the recursive filter has reached the steady state may include determining that a filter output value at time n is equal to a filter output value at time n−1.

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20-09-2012 дата публикации

Carrier Selection for Multiple Antennas

Номер: US20120238229A1
Автор: Rohit V. Gaikwad
Принадлежит: Broadcom Corp

A method and apparatus is disclosed to process a received single stream communication signal and/or a multiple stream communication. A communications receiver is configured to receive the received communication signal. A communications receiver determines whether the received communication signal includes a single stream communication signal or a multiple stream communication signal. The communications receiver determines whether a received communication signal complies with a known single stream communications standard. The communications receiver determines whether the received communication signal complies with a known multiple stream communications standard. The communications receiver decodes the received communication signal according to the known single stream communications standard upon determining the received communication includes the signal single stream communication signal. The communications receiver decodes the received communication signal according to the known multiple stream communications standard upon determining the received communication includes the multiple stream communication signal.

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25-10-2012 дата публикации

Demultiplexing device, multiplexing device, and relay device

Номер: US20120269238A1
Автор: Akinori Fujimura
Принадлежит: Mitsubishi Electric Corp

A demultiplexing device that can reduce power consumption. The demultiplexing device includes frequency-conversion and reception low-pass-filter units that perform a frequency converting process and a low-pass filtering process causing a signal to pass through a desired band, perform downsampling to reduce a sampling rate to half of a data rate of an input signal, and output the signal, reception channel-filter units that waveform-shape a signal with a desired frequency characteristic and output the waveform-shaped signal, a filter-bank control unit that generates a clock control signal for supplying a clock to frequency-conversion and reception low-pass-filter units and reception channel-filter units corresponding to signal passage bands, based on channel information, and a reception-clock supply unit that supplies a clock to frequency-conversion and reception low-pass-filter units and reception channel-filter units corresponding to signal passage bands, based on the clock control signal.

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04-04-2013 дата публикации

SIGNAL PROCESSOR, FILTER, CONTROL CIRCUIT FOR POWER CONVERTER CIRCUIT, INTERCONNECTION INVERTER SYSTEM AND PWM CONVERTER SYSTEM

Номер: US20130082636A1
Принадлежит: DAIHEN CORPORATION

A signal processor is configured to perform a process equivalent to performing a series of fixed-to-rotating coordinate conversion, a predetermined process and then rotating-to-fixed coordinate conversion, while maintaining linearity and time-invariance. The signal processor performs a process given by the following matrix G: 5. A control circuit for controlling a plurality of switching units inside a power converter circuit by a PWM signal , comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'a signal processor according to ; and'}a PWM signal generator for generation of a PWM signal based on an output signal from the signal processor obtained by an input thereto of a signal based on an output from or as input to the power converter circuit.6. The control circuit according to claim 5 , further comprising a two-phase conversion unit for conversion of a signal based on an output from or an input to the power converter circuit into a first signal and a second signal claim 5 , whereinthe PWM signal generator generates a PWM signal based on both an output signal obtained from an input of the first signal to the signal processor and an output signal obtained from an input of the second signal to the signal processor.7. A control circuit for controlling a plurality of switching units inside a power converter circuit by a PWM signal claim 5 , comprising:a two-phase conversion unit for conversion of a signal based on an output from or an input to the power converter circuit into a first signal and a second signal;{'claim-ref': {'@idref': 'CLM-00002', 'claim 2'}, 'the signal processor according to ; and'}a PWM signal generator for generation of a PWM signal based on an output signal from the signal processor obtained by an input thereto of the first signal and the second signal.8. The control circuit according to claim 6 , whereinthe power converter circuit relates to a three-phase alternate current, andthe two-phase conversion unit converts a signal based on a ...

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16-05-2013 дата публикации

FOLDING SEQUENTIAL ADAPTIVE EQUALIZER

Номер: US20130121395A1
Принадлежит:

A folding adaptive equalizer is provided. The equalizer comprises an equalizer core and an automatic gain control loop. The equalizing transfer function of the equalizer core is modulated by one or more gain control signals generated by the automatic gain control loop and by a folding signal generated by the automatic gain control loop. When the folding signal is inactive, an increase in the gain control signals produces an increase in the high-frequency, high-bandwidth gain of the transfer function of the equalizer core. When the folding signal is active, further gain can be applied by decreasing the gain control signals, which produces a frequency-shift in the transfer function of the equalizer core toward lower bandwidth and an increase in the high-frequency, low-bandwidth gain of the transfer function of the equalizer core. 1. An equalizer , comprising:a gain control loop that produces a folding signal and at least one gain control signal; andan equalizer core coupled to an input signal from a transmission medium that applies a high-bandwidth transfer function and a low-bandwidth transfer function to the input signal to produce an output signal,wherein:the high-bandwidth transfer function has high-bandwidth gain proportional to the at least one gain control signal;when the folding signal is at a first level, the low-bandwidth transfer function has no gain; andwhen the folding signal is at a second level, the low-bandwidth transfer function has low-bandwidth gain inversely proportional to the at least one gain control signal.2. The equalizer of claim 1 , wherein each transfer function has frequency-dependent gain.3. The equalizer of claim 1 , wherein the total gain of the transfer functions applied by the equalizer core approximates the inverse of the losses incurred in the transmission of the input signal through the transmission medium.4. The equalizer of claim 1 , wherein the folding signal is at a first level when the amount of low-frequency gain required to ...

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04-07-2013 дата публикации

Interpolation of Filter Coefficients

Номер: US20130170582A1
Принадлежит: St Ericsson SA

The frequency response of a digital filter, such as a pre-emphasis filter in a signal transmitter having a phase-locked loop, is adjusted using interpolation of the filter coefficients, enabling sets of filter coefficients to be pre-computed or generated as needed in the transmitter. The phase error behavior of the digital filter can be significantly improved.

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18-07-2013 дата публикации

Data Processing Method and System

Номер: US20130181769A1
Автор: Akira Noda
Принадлежит: Shimadzu Corp

For an input signal with a ringing superposed thereon, a ringing-generating filter ( 12 ) generates an analogous ringing waveform from only a peak portion of the signal which precedes the ringing. A subtractor ( 11 ) subtracts the analogous ringing waveform from the input signal to eliminate the ringing. The coefficient of the filter ( 12 ) is determined by applying a calculation method similar to a polynomial division based on the complete pivoting Gaussian elimination to polynomials using a reference data expressing a peak waveform and a ringing waveform, and by using a least squares method for minimizing the square of the covariance so as to allow the presence of noise in the data. Furthermore, by a repetitive process on a plurality of the same datasets, the calculation accuracy of the coefficient is improved even under the condition that the ringing frequency is high and the number of samples in one cycle is small. Thus, the ringing can be correctly eliminated even if the signal frequency is high.

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03-10-2013 дата публикации

Digital filter circuit and digital filter control method

Номер: US20130262545A1
Автор: Atsufumi Shibayama
Принадлежит: NEC Corp

[Objective] To provide a digital filter circuit and a digital filter control method which are capable of reducing circuit scale and power consumption for filter processing in a frequency domain such as an overlap FDE method. [Solution] A digital filter circuit according to the present invention includes: an overlap addition means for giving an overlap of M data (M is a positive integer) between the block and the previous block; an FFT processing means for transforming the generated block by FFT processing; a filter computation means for performing filter processing to the transformed block; an IFFT means for transforming the block, which the filter processing was performed to, by IFFT processing; an overlap removal means for removing M units of data from both ends of the transformed block; and a clock generation means for setting the frequency of a filter processing clock signal based on a value of M, wherein the filter processing clock signal drives the data output unit of the overlap addition means, the FFT means, the filter computation means, the IFFT means, and the input unit of the overlap removal means.

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17-10-2013 дата публикации

Filter system

Номер: US20130275483A1
Принадлежит: SIEMENS AG

A filter system with infinite impulse response is provided. The filter system has a transfer function that includes at least one pair of first order polynomial fractions. In one embodiment, the poles and/or the zeros of the pair of polynomial fractions are complex conjugates, respectively. The gain of the transfer function is realized, for example, by virtue of at least two separate multiplier elements

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24-10-2013 дата публикации

Shift-Invariant Digital Sampling Rate Conversion System

Номер: US20130279562A1
Автор: Stéphan Tassart
Принадлежит: St Ericsson SA

There is described a method of making a linear periodically time varying system shift-invariant, comprising the following steps implemented for each input signal the sampling rate of which has to be converted: —generating a set of polyphase components based on the input signal, —feeding the generated set of polyphase components to the system, and —generating an output signal by performing interleaving, shifting and addition on signals output by the system corresponding to the generated set of polyphase components processed by the system.

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24-10-2013 дата публикации

NICAM Decoder with Output Resampler

Номер: US20130282385A1
Принадлежит: THAT Corp

A NICAM audio signal re-sampler may include a non-linear interpolator configured to interpolate in a non-linear manner between sequential digital samples that are based on a stream of demodulated NICAM audio samples. A phase differential calculator may be included that compares phase information at different resolutions.

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12-12-2013 дата публикации

Method and apparatus for efficient frequency-domain implementation of time-varying filters

Номер: US20130332498A1
Автор: Earl Corban Vickers
Принадлежит: STMicroelectronics lnc USA

Embodiments are directed to efficient frequency-domain implementations of time-varying FIR filters. More specifically, time-varying FIR filters according to embodiments exploit the duality of the fast Fourier transform that windowing in the time domain equals convolution in the frequency domain. In one embodiment, convolution of the output of the FIR filter and a desired windowing function is performed in the frequency domain instead of taking the output of the FIR filter in the frequency domain, converting this output the time domain via an IFFT, and then windowing this output in the time domain before again converting back to the frequency domain. As long as the windowing function has certain characteristics, then the time-varying FIR filter is computationally efficient and introduces minimal audible artifacts into the output of the filter. Concepts described herein are discussed in terms of audio signals and systems but are not limited to audio signals and systems.

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12-12-2013 дата публикации

SIGNAL PROCESSING APPARATUS, SIGNAL PROCESSING METHOD, STORAGE MEDIUM

Номер: US20130332500A1
Принадлежит: NEC Corporation

To obtain a high-quality enhanced signal, disclosed is a signal processing apparatus including a transform unit that transforms a mixed signal in which a first signal and a second signal coexist, into a phase component and a magnitude component or power component for each frequency, a first control unit that replaces the phase component of a predetermined frequency, a second control unit that modifies the magnitude component or power component of the predetermined frequency in accordance with the amount of a change of the magnitude component or power component that arises from replacement by the first control unit, and a reconstruction unit that reconstructs the phase component replaced by the first control unit and the magnitude component or power component modified by the second control unit. 1. A signal processing apparatus comprising:a transform unit that transforms a mixed signal in which a first signal and a second signal coexist, into a phase component and a magnitude component or power component for each frequency;a first control unit that replaces the phase component of a predetermined frequency;a second control unit that modifies the magnitude component or power component of the predetermined frequency in accordance with an amount of a change of the magnitude component or power component that arises from replacement by said first control unit; anda reconstruction unit that reconstructs the phase component replaced by said first control unit and the magnitude component or power component modified by said second control unit.2. The signal processing apparatus according to claim 1 , whereinsaid first control unit includes a replacement amount generation unit that generates a replacement amount of the phase component, andsaid second control unit calculates the change amount based on the replacement amount provided from the replacement amount generation unit, and modifies the magnitude component or power component in accordance with the calculated change amount ...

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02-01-2014 дата публикации

Method and Apparatus for Detecting the Presence of a Signal in a Frequency Band Using Non-Uniform Sampling

Номер: US20140003556A1
Автор: Ajay K. Luthra
Принадлежит: MOTOROLA MOBILITY LLC

A method and apparatus for detecting the presence of a signal in a frequency band using non-uniform sampling includes an analog to digital converter (ADC) ( 110 ) for sampling an analog input signal ( 105 ) to create discrete signal samples ( 115 ), an ADC exciter ( 120 ) for exciting the ADC to sample at non-uniform time periods, a digital filter ( 130 ) for converting the discrete signal samples into an energy versus frequency spectrum ( 300 ), and an energy comparator ( 140 ) coupled to an output of the digital filter. The energy comparator ( 140 ) detects the presence of any frequency bands exceeding an energy setpoint.

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06-02-2014 дата публикации

Whitening filter configuration method, program, and system

Номер: US20140040340A1
Автор: Junya Shimizu
Принадлежит: International Business Machines Corp

A system is configured so that signals passed through an all-pass filter using warp parameter λ are whitening-filtered, and so that the frequency axis is restored by an all-pass filter using warp parameter λ. This optimizes the whitening filter by determining the optimum λ. First, the AR order p is automatically estimated using λ=0. A spectral distance dλ is computed using a discrete Fourier transform spectrum value passed through an all-pass filter using warp parameter λ and a discrete AR spectrum value passed through an all-pass filter using warp parameter λ. The λ which minimizes the spectral distance dλ is set as the warp parameter, and a whitening filter is configured in which the warp parameter has been optimized.

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02-01-2020 дата публикации

Method for Determining a Time of Contact on a Capacitive Sensor Element

Номер: US20200004380A1
Принадлежит: Leopold Kostal GmbH & Co. KG

A method for determining a time of contact of a capacitive sensor includes continuously measuring a capacitance value of the capacitive sensor and processing the measured capacitance value into a digital sensor signal. The sensor signal is filtered to output a filter signal. Initial dynamics of the filter signal are identified upon the filter signal exceeding a first set filter threshold value. A time at which the filter signal falls below a second set filter threshold value is determined as being a potential time of contact of the capacitive sensor. An actual time of contact of the capacitive sensor is determined when the sensor signal relative to an offset of the sensor signal exceeds a sensor signal threshold value. The offset of the sensor signal is a value of the sensor signal prior to the contact of the capacitive sensor. 1. A method for determining a time of contact of a capacitive sensor , the method comprising:continuously measuring a capacitance value of the capacitive sensor and processing the measured capacitance value into a digital sensor signal (SS);filtering the sensor signal (SS) by a digital filter to output therefrom a filter signal (F S);{'b': '1', 'identifying initial dynamics of the filter signal (FS) upon the filter signal (FS) exceeding a first set filter threshold value (FT);'}{'b': '2', 'determining a time at which the filter signal (FS) falls below a second set filter threshold value (FT) as being a potential time of contact of the capacitive sensor;'}{'b': '1', 'determining an actual time of contact of the capacitive sensor when the sensor signal (SS) relative to an offset of the sensor signal (SS) exceeds a sensor signal threshold value (ST), wherein the offset of the sensor signal (SS) is a value of the sensor signal (SS) prior to the contact of the capacitive sensor; and'}outputting the actual time of contact of the capacitive sensor.2. The method of wherein:the digital filter is a FIR filter.3. The method of wherein:the FIR filter has ...

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20-01-2022 дата публикации

ANALOG FIR FILTER

Номер: US20220021374A1
Принадлежит:

A FIR filter (), comprising an input terminal for receiving an input signal, a first filtering circuit comprising: a first transconductance device () configured to generate a first current signal (i) proportional to the input signal; a first analog switch () commuted in n by a first digital gate signal (ϕ) and configured to block the current signal when the first digital gate signal has a first value and to transmit the current signal to a first integrating capacitor () when the first digital gate signal has a second value; characterized in that the first digital gate signal (ϕ) comprises a periodic series of pulses, wherein the pulses have widths proportional to the filter coefficients. 1. A FIR filter , comprising an input terminal for receiving an input signal , a first filtering circuit comprising: a first integrating capacitor , a first transconductance device configured to generate a first current signal proportional to the input signal; a first analog switch commuted by a first digital gate signal and configured to block the current signal when the first digital gate signal has a first value and to transmit the first current signal to the first integrating capacitor when the first digital gate signal has a second value; wherein the first digital gate signal comprises a periodic series of pulses , wherein the pulses have widths proportional to a set of coefficients of the FIR filter.2. The FIR filter of claim 1 , having a gate generator comprising a memory storing the filter coefficients and a digital-to-time converter claim 1 , wherein the filter coefficients are read from the memory and provided to the digital-to-time converter sequentially and synchronously with a clock signal claim 1 , and the digital-to-time converter generates for each received filter coefficient a pulse having a width proportional thereto.3. The FIR filter claim 1 , wherein the first integrating capacitor is periodically reset.4. The FIR filter of claim 1 , wherein the charge stored in ...

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11-01-2018 дата публикации

Digital filter circuit, signal processing device, and digital filter processing method

Номер: US20180013409A1
Принадлежит: NEC Corp

Provided is a digital filter circuit in which a filter coefficient can be easily changed, for which circuit scale and power consumption can be reduced, and which carries out digital filter processing in a frequency domain. This digital filter circuit includes: a separating circuit for separating a first complex number signal, of a frequency domain that was subjected to Fourier transform, into a real number portion and an imaginary number portion; a filter coefficient generating circuit for generating a first frequency domain filter coefficient from a first input filter coefficient and a third input filter coefficient, and for generating a second frequency domain filter coefficient from a second input filter coefficient and the third input filter coefficient; a first filter that filters the separated real number portion using the first frequency domain filter coefficient; a second filter that filters the separated imaginary number portion using the second frequency domain filter coefficient; and a combining circuit for combining the output from the two filters.

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10-01-2019 дата публикации

Laser frequency chirping structures, methods, and applications

Номер: US20190013798A1
Принадлежит: ANALOG PHOTONICS LLC

Aspects of the present disclosure describe systems, methods, and structures including integrated laser systems that employ external chirping structures that may advantageously include phase shifters and/or one or more filters. Further aspects of the present disclosure describe systems, methods, and structures including laser systems that employ external chirping structures that may advantageously include optical phased arrays.

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14-01-2021 дата публикации

SIGNAL PROCESSOR, FILTER, CONTROL CIRCUIT FOR POWER CONVERTER CIRCUIT, INTERCONNECTION INVERTER SYSTEM AND PWM CONVERTER SYSTEM

Номер: US20210013794A1
Принадлежит:

A signal processor is configured to perform a process equivalent to performing a series of fixed-to-rotating coordinate conversion, a predetermined process and then rotating-to-fixed coordinate conversion, while maintaining linearity and time-invariance. The signal processor performs a process given by the following matrix G: 130-. (canceled)32. The signal processor according to claim 31 , wherein the transfer function F(s) is equal to one of K/s (Krepresents an integral gain) claim 31 , K+K/s (Krepresents a proportional gain claim 31 , and Krepresents an integral gain) or K+K/s+K(Krepresents a proportional gain claim 31 , Krepresents an integral gain claim 31 , and Krepresents a differential gain).33. A control circuit for controlling a plurality of switching units inside a power converter circuit by a PWM signal claim 31 , comprising:{'claim-ref': {'@idref': 'CLM-00031', 'claim 31'}, 'a signal processor according to ; and'}a PWM signal generator configured to generate a PWM signal based on an output from the signal processor.34. The control circuit according to claim 33 , wherein the power converter circuit relates to a three-phase alternate current.35. The control circuit according to claim 33 , further comprising a divergence determination unit and an output control unit claim 33 ,wherein the divergence determination unit is configured to determine, based on output signals from the signal processor, if control for driving the plurality of switching units tends to diverge, andwherein when the divergence determination unit determines that the control for driving the plurality of switching units tends to diverge, the output control unit stops the output signal or changes a phase of the output signal to another phase whereby the control for driving the plurality of switching units does not diverge.36. The control circuit according to claim 33 , wherein the power converter circuit comprises a converter circuit for conversion of AC power supplied from an electrical ...

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21-01-2016 дата публикации

Generation of High-Rate Sinusoidal Sequences

Номер: US20160020753A1
Принадлежит:

Provided are, among other things, systems, apparatuses methods and techniques for generating discrete-time sinusoidal sequences. One such apparatus includes a plurality of parallel processing branches, with each of the parallel processing branches operating at a subsampled rate and utilizing a recursive filter to generate sub-rate samples which represent a different subsampling phase of a complete signal that is output by the apparatus. 1. An apparatus for generating discrete-time samples of a sinusoidal waveform , comprising:an output line for providing output samples of a sinusoid that are discrete in time and in value;a plurality of processing branches coupled to the output line, each of said processing branches including a recursive digital filter;a first input line for setting a frequency of the sinusoid; anda second input line for setting an initial state of the recursive digital filter in at least one of said processing branches,wherein each of said processing branches operates at a subsampled rate, and generates an output sequence at said subsampled rate which represents a different subsampling phase of a complete, full-rate sinusoidal sequence in accordance with a value provided on said second input line, andwherein said recursive digital filter within each said processing branch operates independently of the recursive digital filter within the other processing branches and produces subsampled outputs via a linear combination of prior output samples generated within said processing branch.2. An apparatus according to claim 1 , further comprising a multiplexer with inputs that are coupled to outputs of said parallel processing branches and which combines multiple claim 1 , sub-rate inputs into a single claim 1 , full-rate output.3. An apparatus according to claim 1 , wherein the frequency of the sinusoid is established by a programmable coefficient within the recursive digital filter.4. An apparatus according to claim 1 , wherein the initial state of the ...

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17-04-2014 дата публикации

Digitally Controlled Delay Line for a Structured ASIC Having a Via Configurable Fabric for High-Speed Interface

Номер: US20140103985A1
Принадлежит: eASIC Corporation

A Digitally Controlled Delay Line (DCDL) for a Structured ASIC chip is used to delaying input or output signals into or out of core logic in a Structured ASIC. The DCDL has a multi-stage configuration that in a preferred embodiment comprises two fine delay stages for fine tuning the delay using sub-gate delay through an inverter whose delay can be adjusted with parallel CMOS transistors whose gates are biased with a voltage control signal that is thermometer coded. The fine-tune stages are followed by coarse delay stages that use gate-level delay. A DCDL controller outputs control signals that are Grey coded and converted to thermometer coded control signals by a Binary-to-Thermometer Decoder. The DCDL circuit block and accompanying Structured ASIC are manufactured on a 28 nm CMOS process lithographic node or smaller. A high speed routing fabric using a balanced binary tree is employed with the DCDL. 1. A Digitally Controlled Delay Line (DCDL) , comprising:a module for the coarse delay of a signal having an input and an output;a module for the fine delay of a signal, having an input and an output;wherein a signal is capable of being delayed by the fine delay module for a period of time less than the period of time the signal is capable of being delayed by the coarse delay module.2. The DCDL according to claim 1 , wherein:the fine delay module is in series with the coarse delay module, with the output of the fine delay module input into the input of the coarse delay module; and,the coarse delay module comprises a delay producing inverter.3. The DCDL according to claim 2 , further comprising:a circuit for producing a thermometer coded signal output.4. The DCDL according to claim 3 , wherein:the fine delay module comprises a sub-gate delay logic array comprising a delay-producing inverter, the inverter having a plurality of parallel pFET and nFET transistors.5. The DCDL according to claim 3 , wherein:the fine delay module comprises a sub-gate delay logic array ...

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17-01-2019 дата публикации

SIGNAL PROCESSOR, FILTER, CONTROL CIRCUIT FOR POWER CONVERTER CIRCUIT, INTERCONNECTION INVERTER SYSTEM AND PWM CONVERTER SYSTEM

Номер: US20190020261A1
Принадлежит:

A signal processor is configured to perform a process equivalent to performing a series of fixed-to-rotating coordinate conversion, a predetermined process and then rotating-to-fixed coordinate conversion, while maintaining linearity and time-invariance. The signal processor performs a process given by the following matrix G: 130-. (canceled)3223ss. The filter according to claim 31 , wherein G()=G()=0.3323ss. The filter according to claim 31 , wherein G()≠0 and G()≠0.34. The filter according to claim 31 , wherein the transfer function F(s) is equal to one of K/s (Krepresents an integral gain) claim 31 , K+K/s (Krepresents a proportional gain claim 31 , and Krepresents an integral gain) or K+K/s+K·s (Krepresents a proportional gain claim 31 , Krepresents an integral gain claim 31 , and Krepresents a differential gain).35. The filter according to claim 31 , wherein the transfer function F(s) is equal to 1/(T·s+1) claim 31 , where T represents a time constant.36. The filter according to claim 31 , wherein the transfer function F(s) is equal to T·s/(T·s+1) claim 31 , where T represents a time constant.37. The filter according to claim 31 , wherein a positive phase component of a fundamental wave of the first input signal Sis different in phase by 90 degrees from a positive phase component of a fundamental wave of the second input signal S.38. The filter according to claim 31 , wherein the first input signal Sis a non-zero signal claim 31 , and the second input signal Sis zero.39. A filtering system comprising:{'claim-ref': {'@idref': 'CLM-00031', 'claim 31'}, 'a filter according to ; and'}{'sub': 1', '2, 'a signal converter configured to convert three-phase alternate signals to the first input signal Sand the second input signal S.'}40. A filtering system comprising:{'claim-ref': {'@idref': 'CLM-00031', 'claim 31'}, 'a filter according to ; and'}{'sub': 1', '2, 'a signal converter configured to convert a single-phase alternate signal to the first input signal Sand the ...

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17-01-2019 дата публикации

RECEIVING DEVICE

Номер: US20190020508A1
Автор: NODA Yasunori
Принадлежит: Mitsubishi Electric Corporation

A receiving device includes: a resampler to convert a sampling rate of a reception signal, and output a first signal that is a signal having been subjected to sampling rate conversion; an equalizer to perform an adaptive equalization process using the first signal as an input, and output a second signal that is a signal having been subjected to the adaptive equalization process and having a sampling rate that is an integer fraction of an input signal; a correlation calculator to calculate a correlation function between the first signal and the second signal; and a rate controller to control a rate conversion ratio for sampling rate conversion in the resampler on a basis of the correlation function. 1. A receiving device comprising:a resampler to convert a sampling rate of a reception signal, and output a first signal that is a signal having been subjected to sampling rate conversion;an equalizer to perform an adaptive equalization process using the first signal as an input, and output a second signal that is a signal having been subjected to the adaptive equalization process and having a sampling rate that is an integer fraction of an input signal;a correlation calculator to calculate a correlation function between the first signal and the second signal; anda rate controller to control a rate conversion ratio for sampling rate conversion in the resampler on a basis of the correlation function.2. The receiving device according to claim 1 , whereinthe rate controller controls the rate conversion ratio on a basis of a delay time corresponding to a maximum value of the correlation function.3. The receiving device according to claim 1 , further comprisingan upsampler to upsample the second signal, whereinthe correlation calculator calculates a correlation function between the first signal and the second signal having been subjected to upsampling by the upsampler.4. The receiving device according to claim 3 , further comprisinga symbol determiner to perform symbol ...

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28-01-2021 дата публикации

LOW PASS FILTER AND FILTER DIAGNOSTICS

Номер: US20210025943A1
Принадлежит:

As one example, a filter apparatus includes an input to receive an electrical input signal. The filter apparatus includes a forward path connected between the input and an output of the filter apparatus. A feedback path is connected to provide feedback to the forward path based on an output signal at the output of the filter apparatus. A filter bypass is configured to provide the input signal directly to the output and to the feedback path for an activation phase of the filter apparatus. Diagnostics may also be performed. 1. A filter apparatus comprising:an input to receive an electrical input signal;a forward path connected between the input and an output of the filter apparatus;a feedback path connected to provide feedback to the forward path based on an output signal at the output; anda filter bypass configured to send the input signal directly to the output and to the feedback path for an activation phase of the filter apparatus.2. The filter apparatus of claim 1 , wherein the forward path comprises:a gain stage to apply a gain factor to the input signal to provide an intermediate signal; anda combiner configured to add the feedback to the intermediate signal to provide the output signal.3. The filter apparatus of claim 2 , wherein the feedback path comprises:a delay element to impose a predetermined delay to the output signal; anda gain stage to apply another gain factor to the delayed output signal and provide the feedback to the combiner.4. The filter apparatus of claim 2 , wherein the filter bypass comprises a multiplexer having inputs coupled to receive the input signal and an output of the combiner claim 2 , the multiplexer having an output corresponding to the output of the filter apparatus claim 2 , the multiplexer sending one of the input signal and the output of the combiner to the output of the filter apparatus based on a control input.5. The filter apparatus of claim 4 , wherein the control input operates the multiplexer to send the input signal to ...

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24-01-2019 дата публикации

COMPACT MODEL NONLINEAR COMPENSATION OF BANDLIMITED RECEIVER SYSTEMS

Номер: US20190028131A1
Автор: Wang Xiao-Yu
Принадлежит: Massachusetts Institute of Technology

A nonlinear compensator is provided to include a decomposition circuit and a plurality of filter elements. The decomposition circuit has a nonlinear frequency response characteristic and the decomposition circuit is configured to receive an input signal and decompose the input signal into decomposed signals corresponding to positive and negative frequency signal components of the input signal. Each of the plurality of filter elements is configured to receive at least portions of the decomposed signals and apply filter element characteristics to the decomposed signals with the filter element characteristics that are matched to the nonlinear frequency response of the decomposition circuit. 1. A nonlinear compensator comprisinga decomposition circuit having a nonlinear frequency response characteristic, the decomposition circuit being configured to receive an input signal and decompose the input signal provided thereto into decomposed signals corresponding to positive and negative frequency signal components of the input signal; anda plurality of filter elements each of which is configured to receive at least portions of the decomposed signals and apply filter element characteristics to the decomposed signals with the filter element characteristics being matched to the nonlinear frequency response of the decomposition circuit.2. The nonlinear compensator of claim 1 , wherein the plurality of filter elements is configured to reduce the number of tones to characterize the nonlinear system.3. The nonlinear compensator of claim 1 , wherein the plurality of filters comprises at least one of:at least one nonlinear operation element; orat least one linear operation filter.4. The nonlinear compensator of claim 3 , wherein the at least one nonlinear operation element comprises at least one static nonlinear mathematical operation element.5. The nonlinear compensator of claim 3 , wherein the at least one linear operation filter comprises at least one of:at least one static linear ...

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08-02-2018 дата публикации

FILTER ASSEMBLY FOR MEDICAL IMAGE SIGNAL AND DYNAMIC DECIMATION METHOD USING SAME

Номер: US20180035981A1
Принадлежит: SOGANG UNIVERSITY RESEARCH FOUNDATION

The present invention relates to a filter assembly for a medical image signal and a dynamic decimation method using the same. The filter assembly includes a decimation filter that includes an integer number of multiplier accumulators (MACs), changes a cut-off frequency depending on a bandwidth of the medical image signal received through a dynamic impulse response update, and performs a decimation with respect to the received signal according to a decimation ratio, wherein the decimation filter determines a filter coefficient corresponding to an integer interval so as to up-sample the received medical image signal and supplies the filter coefficient to the MACs. 1. A filter assembly for a medical image signal , comprising:an expander configured to receive the medical image signal and up-sample the medical image signal; anda decimation filter including an integer number of multiplier accumulators (MACs), configured to change a cutoff frequency according to bandwidth of the received medical image signal by dynamically updating an impulse response and perform decimation on the up-sampled signal according to a decimation ratio.2. The filter assembly according to claim 1 , wherein the decimation filter calculates a partial sum claim 1 , which is the sum of coefficients of a k-th (wherein k is a positive integer) location of a polyphase filter claim 1 , through each MAC.3. The filter assembly according to claim 1 , wherein each MAC includes:a shift register configured to receive and store coefficients of a polyphase filter;a multiplier configured to multiply the coefficients stored in the shift register by the up-sampled signal;a summer configured to cumulatively sum the multiplied results; anda decimator configured to decimate the summed result.4. The filter assembly according to claim 3 , wherein a frequency band of the received signal is determined by attenuation caused by depth of an object of the medical image signal and filter coefficients for calculating different ...

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11-02-2016 дата публикации

CIRCUIT FOR DETECTING PHASE SHIFT APPLIED TO AN RF SIGNAL

Номер: US20160043703A1
Автор: TOURRET Jean-Robert
Принадлежит:

An RF circuit and method for detecting the amount of phase shift applied to an RF signal. An RF heating apparatus including the RF circuit. The RF circuit includes a phase shifter operable to apply a phase shift to a reference signal to produce a phase shifted reference signal. The RF circuit also includes a phase detector operable to detect a phase difference between the phase shifted RF signal and the phase shifted reference signal. The phase detector has a reduced input range at a frequency of the phase shifted RF signal. The RF circuit further includes a controller operable to control the phase shifter to set the phase of the phase shifted reference signal so that the phase difference between the phase shifted RF signal and the phase shifted reference signal falls within the reduced input range of the phase detector. 1. A circuit for detecting the amount of phase shift applied to an RF signal to produce a phase shifted RF signal in an RF signal path , the circuit comprising:a phase shifter operable to apply a phase shift to a reference signal to produce a phase shifted reference signal;a phase detector operable to detect a phase difference between the phase shifted RF signal and the phase shifted reference signal, wherein the phase detector has a reduced input range at a frequency of the phase shifted RF signal compared to the input range of the phase detector at a frequency lower than the frequency of the phase shifted RF signal, anda controller operable to control the phase shifter to set the phase of the phase shifted reference signal so that the phase difference between the phase shifted RF signal and the phase shifted reference signal falls within the reduced input range of the phase detector.2. The circuit of claim 1 , wherein the controller is operable to:control a phase shifter of the RF signal path for applying an intended phase shift applied to the RF signal to produce the phase shifted RF signal.3. The circuit of claim 2 , wherein the controller is ...

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09-02-2017 дата публикации

Delay Line

Номер: US20170040976A1
Автор: Julian Jenkins
Принадлежит: Perceptia Devices Inc

A delay line is constructed by combining a phase generator and a fabric. The phase generator splits a digital input signal in multiple incrementally delayed versions, which are input to the fabric. The fabric has an array of node filters. Inputs of filters in the first array column are inputs of the fabric. A node filter has a delay element and a cross-coupling element, whose output signals are added or subtracted to form a filter output signal. A node filter in a row is concatenated to the previous filter in the row through its delay element. Inputs of cross-coupling elements are connected to other array rows. Outputs of node filters form the outputs of the fabric. Delay times of delay elements and cross-coupling elements are nominally equal. Drive strengths of cross-coupling elements may be lower than drive strengths of delay elements.

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09-02-2017 дата публикации

Digital Filter With Confidence Input

Номер: US20170040977A1
Автор: Heim Axel, HOCH Martin
Принадлежит: MICROCHIP TECHNOLOGY GERMANY GMBH

A digital filter has an assigned filter function with assigned filter coefficients, an input receiving input samples, another input receiving confidence values, and an output. Each input sample value is associated to an input confidence value, wherein the filter output depends on the input samples, the input confidence values as well as the filter coefficients. The filter contains multiple accumulators, wherein an output sample is produced after a predetermined number of sample values wherein associated confidence values have been input to the filter. 1. A digital filter comprising an assigned filter function with assigned filter coefficients , an input receiving input samples , another input receiving confidence values , and an output ,wherein each input sample value is associated to an input confidence value and wherein each input sample is weighted with its associated confidence value;the filter output depends on both the input samples and the input confidence values, andwherein the filter comprises accumulators configured to accumulate a predefined number the confidence weighted input samples, the associated confidence values, the confidence values weighted with assigned filter coefficients, and the confidence weighted input samples further weighted with the assigned filter coefficients.2. The filter according to claim 1 , comprising:a first branch having a first accumulator receiving the input confidence values weighted with coefficients from a coefficient set and generating a first accumulated value;a second branch having a second accumulator receiving the input confidence values and generating a second accumulated value;a third branch having a third accumulator receiving input sample values weighted with coefficients from the coefficient set and the input confidence values and generating a third accumulated value;a fourth branch having a fourth accumulator receiving the confidence weighted input values and generating a fourth accumulated value.3. The filter ...

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06-02-2020 дата публикации

SIGNAL PROCESSOR, FILTER, CONTROL CIRCUIT FOR POWER CONVERTER CIRCUIT, INTERCONNECTION INVERTER SYSTEM AND PWM CONVERTER SYSTEM

Номер: US20200044557A1
Принадлежит:

A signal processor is configured to perform a process equivalent to performing a series of fixed-to-rotating coordinate conversion, a predetermined process and then rotating-to-fixed coordinate conversion, while maintaining linearity and time-invariance. The signal processor performs a process given by the following matrix G: 130-. (canceled)32. The signal processor according to claim 31 , wherein the transfer function F(s) is equal to one of K/s (Krepresents an integral gain) claim 31 , K+K/s (Krepresents a proportional gain claim 31 , and Krepresents an integral gain) or K+K/s+K·s (Krepresents a proportional gain claim 31 , Krepresents an integral gain claim 31 , and Krepresents a differential gain).33. A control circuit for controlling a plurality of switching units inside a power converter circuit by a PWM signal claim 31 , comprising:{'claim-ref': {'@idref': 'CLM-00031', 'claim 31'}, 'a signal processor according to ; and'}a PWM signal generator configured to generate a PWM signal based on an output from the signal processor.34. The control circuit according to claim 33 , wherein the power converter circuit relates to a three-phase alternate current.35. The control circuit according to claim 33 , further comprising a divergence determination unit and an output control unit claim 33 ,wherein the divergence determination unit is configured to determine, based on output signals from the signal processor, if control for driving the plurality of switching units tends to diverge, andwherein when the divergence determination unit determines that the control for driving the plurality of switching units tends to diverge, the output control unit stops the output signal or changes a phase of the output signal to another phase whereby the control for driving the plurality of switching units does not diverge.36. The control circuit according to claim 33 , wherein the power converter circuit comprises a converter circuit for conversion of AC power supplied from an electrical ...

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06-02-2020 дата публикации

Apparatuses and methods for shifting a digital signal by a shift time to provide a shifted signal

Номер: US20200044626A1
Принадлежит: Apple Inc, Intel IP Corp

An apparatus for shifting a digital signal having a first sample rate by a shift time to provide a shifted signal having a second sample rate is provided. The apparatus includes a sample rate converter configured to provide a value of an interpolated signal at a compensated sample time as a sample of the shifted signal, the interpolated signal being based on the digital signal. The sample rate converter is configured to modify a time interval between a sample time of the digital signal and the compensated sample time based on the shift time.

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03-03-2022 дата публикации

METHOD AND APPARATUS FOR REDUCED SIZE RF FILTER

Номер: US20220069856A1
Принадлежит:

A radio frequency (RF) unit and a method for RF isolation. The RF unit includes first and second RF couplers, an RF filter, and an RF canceler connected in parallel with the RF filter. The first RF coupler is configured to receive an input signal. The RF filter is configured to receive a first portion of the input signal from the first RF coupler and attenuate frequencies outside of a passband of the RF filter from the first portion of the input signal. The RF canceler is configured to receive a second portion of the input signal from the first RF coupler and generate a cancellation signal from the second portion of the input signal based on a target frequency band of the RF canceler. The second RF coupler is configured to combine the cancellation signal with an output of the RF filter to generate an output signal.

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25-02-2016 дата публикации

Control facility with adaptive fault compensation

Номер: US20160056794A1
Принадлежит: SIEMENS AG

A control facility for controlling a controlled system experiencing a disturbance includes a front nodal point receiving a target value and an actual value outputted by the controlled system and supplying a difference value corresponding to a difference between the target value and the actual value to a compensation circuit. The compensation circuit supplies a frequency-filtered and time-delayed signal formed as the sum of the weighted difference value and a weighted feedback signal as an input to a controller for the controlled system. The sum of a filter delay time and of first and second propagation delays is an integer multiple of the cycle duration of the disturbance, and a sum of the filter delay time and the first propagation delay is an integer multiple of the cycle duration minus a propagation time, which elapses until a change in the target value causes a change in the actual value.

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22-02-2018 дата публикации

METHODS AND SYSTEMS FOR EVENT-DRIVEN RECURSIVE CONTINUOUS-TIME DIGITAL SIGNAL PROCESSING

Номер: US20180054186A1
Автор: Chen Yu, TSIVIDIS Yannis
Принадлежит:

Continuous-time digital systems implemented with separate timing paths and data paths are disclosed. The disclosed continuous-time digital systems, can implement an event-grouping and detection method that can be used feedback systems with propagation delays. By implementing event-detection into a feedback loop of a continuous-time digital system, the system can automatically stop when there is no event in the system. When new events are detected the system can commence operation. 1. A continuous-time digital signal processor comprising:an event-grouping block, configured to receive a first input timing signal, a second input timing signal, and to generate an intermediate timing signal;a first time delay block, configured to receive the intermediate timing signal and generate an output timing signal;a second time delay block, configured to receive the output timing signal and generate the second input timing signal;a two-channel memory configured to receive a first data input and a second data input and to generate a first intermediate data signal and a second intermediate data signal;an arithmetic operation block, configured to receive the first intermediate data signal, the second intermediate data signal and to generate an output data signal, the arithmetic operation block comprising:a scalar block configured to receive the second intermediate data signal and generate a scaled version of the second intermediate data signal; andan adder configured to receive the first intermediate data signal and the scaled version of the second intermediate data signal, and generate the output data signal; anda first-in-first-out (FIFO) memory configured to receive the output data signal and to generate the second input data signal.2. The continuous-time digital signal processor of claim 1 , wherein the adder is configured to receive data at the first intermediate data signal and calculate the output data signal claim 1 , in response to a pulse on the intermediate timing signal.3 ...

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23-02-2017 дата публикации

Low power decimator

Номер: US20170054433A1
Принадлежит: Apple Inc

Systems, apparatuses, and methods for implementing a low power decimator. A decimator may receive a plurality of input samples from a digital microphone. The decimator may include one or more coefficient tables for storing values combining two or more filter coefficients for filtering the received samples. The decimator may utilize a concatenation of multiple samples to perform a lookup of a corresponding coefficient table. The coefficient tables may store only the necessary non-redundant values for all coefficient combinations which can be applied to the multiple samples. The result of the lookup of the coefficient table may have its sign inverted or be zeroed based on the values of the multiple samples.

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23-02-2017 дата публикации

ELECTRO-OPTICAL FINITE IMPULSE RESPONSE TRANSMIT FILTER

Номер: US20170054510A1
Принадлежит: MULTIPHY LTD.

An electro-optical FIR transmit filter comprising a segmented MZM including a plurality of MZM segments, for receiving an input optical traveling wave to be filtered; an electrical field driver, for applying a controlled electrical field required for modulation of each MZM using a control signal which controls the electrical field; delay cells associated with at least one MZM, for aligning the control signal with a travelling optical wave; and at least one electrical xT delay cell representing a filter delay, for electrically adjusting the timing of the control signal. The FIR filter's coefficients are implemented in the optical domain by determining the amount of MZM segments driven by each xT delay cell, with respect to the total number of MZM segments. 1. An electro-optical FIR transmit filter comprising:a. a segmented MZM including a plurality of MZM segments, for receiving an input optical traveling wave to be filtered;b. an electrical field driver connected to each MZM segment, for applying a controlled electrical field required for modulation of each MZM using a control signal;c. a control signal input, for inputting said control signal to control the electrical field, required for optical wave modulation;d. at least one delay cell associated with at least one MZM, for aligning said control signal with a travelling optical wave; ande. at least one electrical xT delay cell representing a filter delay, for electrically adjusting the timing of said control signal,wherein the FIR filter's coefficients are implemented in the optical domain by determining the amount of MZM segments driven by each xT delay cell, with respect to the total number of MZM segments.2. The electro-optical FIR transmit filter of claim 1 , wherein all the electrical field drivers apply an electrical field of a constant magnitude to MZM segments.3. The electro-optical FIR transmit filter of claim 1 , wherein the FIR filter's sampling rate is implemented in the electrical domain by ...

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15-05-2014 дата публикации

Carrier Selection for Multiple Antennas

Номер: US20140133609A1
Автор: Rohit V. Gaikwad
Принадлежит: Broadcom Corp

A method and apparatus is disclosed to process a received single stream communication signal and/or a multiple stream communication. A communications receiver is configured to receive the received communication signal. A communications receiver determines whether the received communication signal includes a single stream communication signal or a multiple stream communication signal. The communications receiver determines whether a received communication signal complies with a known single stream communications standard. The communications receiver determines whether the received communication signal complies with a known multiple stream communications standard. The communications receiver decodes the received communication signal according to the known single stream communications standard upon determining the received communication includes the signal single stream communication signal. The communications receiver decodes the received communication signal according to the known multiple stream communications standard upon determining the received communication includes the multiple stream communication signal.

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02-03-2017 дата публикации

CONFIGURABLE FIR FILTER WITH SEGMENTED CELLS

Номер: US20170063346A1
Принадлежит:

A FIR filter includes segment cells, each of which is configurable as an interpolation filter, a decimation filter, a symmetric filter, or an asymmetric filter. Two or more of the segment cells are configurable to be cascaded to form an interpolation filter, a decimation filter, a symmetric filter, an asymmetric filter, a complex symmetric filter, or a complex asymmetric filter. The FIR filter includes registers corresponding to the segment cells for storing coefficient values of the corresponding segment cells. The FIR filter further includes control circuits corresponding to the segment cells for generating control signals. 1. A finite impulse response (FIR) filter , comprising: a first multiplexer that receives first and second input signals and a first control signal, and outputs a first intermediate signal;', 'a second multiplexer that receives a third input signal and the first intermediate output signal, and a second control signal, and outputs a second intermediate signal;', 'a first tapped delay line connected to the second multiplexer for receiving the second intermediate signal, wherein the first tapped delay line includes first and second filter taps and generates first and second tapped signals, respectively, based on a first enable signal, and wherein the first segment cell outputs the second tapped signal as the first output signal;', 'a third multiplexer that receives a fourth input signal and the first output signal, and a third control signal, and outputs a third intermediate signal;', 'a fourth multiplexer that receives a fifth input signal, the first intermediate signal, and the third intermediate signal, and receives as select signals the second control signal and a fourth control signal, and outputs a fourth intermediate signal;', 'a second tapped delay line connected to the fourth multiplexer for receiving the fourth intermediate signal, wherein the second tapped delay line includes third and fourth filter taps and generates respective third ...

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12-03-2015 дата публикации

SIGNAL-ALIGNMENT CIRCUITRY AND METHODS

Номер: US20150070065A1
Принадлежит:

Signal-alignment circuitry, comprising: phase-rotation circuitry connected to receive one or more input clock signals and operable to generate therefrom one or more output clock signals; and control circuitry operable to control the amount of phase rotation applied by the phase-rotation circuitry to carry out a plurality of alignment operations, the alignment operations comprising: one or more first operations each comprising rotating one or more of said output clock signals relative to one or more of the other said output clock signals, to bring a phase relationship between said output clock signals, or clock signals derived therefrom, towards or into a given phase relationship; and one or more second operations each comprising rotating all of said output clock signals together, to bring a phase relationship between said output or derived clock signals and said input clock signals or an external-reference signal towards or into a given phase relationship. 1. Signal-alignment circuitry , comprising:phase-rotation circuitry connected to receive one or more input clock signals and operable to generate therefrom one or more output clock signals; andcontrol circuitry operable to control the amount of phase rotation applied by the phase-rotation circuitry to carry out a plurality of alignment operations, the alignment operations comprising:one or more first operations each comprising rotating one or more of said output clock signals relative to one or more of the other said output clock signals, so as to bring a phase relationship between said output clock signals, or derived clock signals derived therefrom, towards or into a given phase relationship; andone or more second operations each comprising rotating all of said output clock signals together, so as to bring a phase relationship between said output or derived clock signals and said input clock signals or an external-reference signal towards or into a given phase relationship.2. Signal-alignment circuitry as ...

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12-03-2015 дата публикации

LEAST MEAN SQUARE METHOD FOR ESTIMATION IN SPARSE ADAPTIVE NETWORKS

Номер: US20150074161A1

The least mean square method for estimation in sparse adaptive networks is based on the Reweighted Zero Attracting Least Mean Square (RZA-LMS) algorithm, providing estimation for each node in the adaptive network. The extra penalty term of the RZA-LMS algorithm is then integrated into the Incremental LMS (ILMS) algorithm. Alternatively, the extra penalty term of the RZA-LMS algorithm may be integrated into the Diffusion LMS (DLMS) algorithm. 1. Field of the InventionThe present invention relates generally to adaptive networks, such as sensor networks, and particularly to a least mean square method for estimation in sparse adaptive networks.2. Description of the Related ArtLeast mean squares (LMS) algorithms are a class of adaptive filters used to mimic a desired filter by finding the filter coefficients that relate to producing the least mean squares of the error signal (i.e., the difference between the desired and the actual signal). The LMS algorithm is a stochastic gradient descent method, in that the filter is only adapted based on the error at the current time.In an adaptive network having N nodes, where the network has a predefined topology, for each node k, the number of neighbors is given by N, including the node k itself. In the normalized (NLMS) algorithm, at each iteration i, the output of the system at each node is given by d(i)=u(i)w+v(i), where u(i) is a known regressor row vector of length M, wis an unknown column vector of length M, and v(i) represents noise. The variable i is a time index. The output and regressor data are used to produce an estimate of the unknown vector, given by w(i). If the estimate at any time instant i of wis denoted by the vector w(i) then the estimation error is given by e(i)=d(i)−u(i)w(i). The NLMS algorithm is defined by the calculation of w(i) through the iterationwhere the superscript “T” represents the transpose of u(i) and “∥ ∥” represents the Euclidean norm. Further, μrepresents a step size, defined in the range 0<μ<2 ...

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08-03-2018 дата публикации

Data Recovery from Sub-Carriers

Номер: US20180069740A1
Автор: Bogdan John W
Принадлежит:

The data recovery from sub-carriers (DRSC) of a received OFDM signal, contributes a method and a circuit for utilizing parameters of OFDM sub-carriers comprised in the received OFDM signal or subspaces comprising the OFDM sub-carriers for recovering transmitted data symbols from the received OFDM signal affected by deterministic and random distortions introduced by a transmission link. 1. A method for data recovery from sub-carriers (DRSC) of a received orthogonal frequency division multiplexing (OFDM) signal , by utilizing parameters of the OFDM subcarriers comprised in the received OFDM signal; wherein the DRSC method comprises the steps of:oversampling of the received OFDM signal;sampling of frequencies occurring in the oversampled OFDM signal in order to recover the sub-carriers from the oversampled OFDM signal,wherein the sampling of frequencies and the recovery of the OFDM subcarriers are implemented with a real time processor driven by clocks synchronous to frames of the received OFDM signal;processing the oversampled OFDM signal in order to define an inverse transfer function designed to reverse distortions introduced by a transmission link to the received OFDM signal;estimating amplitudes and phases of the recovered OFDM sub-carriers by processing the recovered OFDM sub-carriers;reversing the distortions introduced by the transmission link by utilizing the defined inverse transfer function for transforming the estimated amplitudes and phases;using the transformed amplitudes and phases for recovering data symbols encoded originally in a transmitted OFDM signal.2. A DRSC method as claimed in claim 1 , wherein the real time processor is implemented by utilizing a synchronous circular processor (SCP); wherein the SCP comprises:processing stages which are sequentially connected and fed with consecutive samples derived from the received OFDM signal;wherein the processing stages comprise consecutive circular segments designated for storing or processing of the ...

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28-02-2019 дата публикации

SYSTEM IMPROVING SIGNAL HANDLING

Номер: US20190068170A1
Принадлежит:

The invention provides a system improving signal handling, e.g., transmission and/or processing. In an embodiment, the system may include a filter circuit, a magnitude bit truncation circuit and a utility circuit. The filter circuit may be coupled to a target signal which contains one or more desired signals at one or more interested bands, for attenuating each said interested band to form a filtered signal. The magnitude bit truncation circuit may be coupled to the filter circuit, for truncating one or more bits of each sample of the filtered signal to form a truncated signal. The utility circuit may be coupled to the magnitude bit truncation circuit, for handling the truncated signal to implement handling of the target signal, so as to reduce resource requirement and enhance error tolerance comparing with directly handling the target signal. 1. A system improving signal handling , comprising:a filter circuit coupled to a target signal which contains one or more desired signals at one or more interested bands, for attenuating each said interested band to form a filtered signal;a magnitude bit truncation circuit coupled to the filter circuit, for truncating one or more bits of each sample of the filtered signal to form a truncated signal; anda utility circuit coupled to the magnitude bit truncation circuit, for handling the truncated signal to implement handling of the target signal, so as to reduce resource requirement and enhance error tolerance comparing with directly handling the target signal.2. The system of further comprising:a modulator coupled between the target signal and the filter circuit, for modulating the target signal to a modulated signal of a rougher quantization resolution.3. The system of claim 2 , wherein the modulator is a multi-bit sigma-delta modulator arranged to modulate the target signal by multi-bit sigma-delta modulation.4. The system of claim 2 , wherein the target signal is an analog signal claim 2 , and the modulated signal is a ...

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08-03-2018 дата публикации

Phase Control Signal Generation Device, Phase Control Signal Generation Method, and Phase Control Signal Generation Program

Номер: US20180070177A1
Принадлежит: Clarion Co., Ltd.

A phase control signal generation device generating a phase control signal for each of frequency bands for an audio signal converted into a frequency domain, the phase control signal generation device comprising: a setting change means that is able to change setting of a propagation delay time for each of predetermined frequency bands; a difference obtaining means that obtains a difference between propagation delay times before and after setting change; an updating means that updates a phase control amount of the frequency band for which the propagation delay time is changed, based on the obtained difference; and a phase control signal generating means that generates a phase control signal of each frequency band by performing a smoothing process for the phase control amount in a frequency domain using the updated phase control amount. 1. A phase control signal generation device generating a phase control signal for each of frequency bands for an audio signal converted into a frequency domain , the phase control signal generation device comprising:a setting change unit configured to be able to change setting of a propagation delay time for each of predetermined frequency bands;a difference obtaining unit configured to obtain a difference between propagation delay times before and after setting change;an updating unit configured to update a phase control amount of the frequency band for which the propagation delay time is changed, based on the obtained difference; anda phase control signal generating unit configured to generate a phase control signal of each frequency band by performing a smoothing process for the phase control amount in a frequency domain using the updated phase control amount.2. The phase control signal generation device according to claim 1 ,further comprising:a weighting coefficient storing unit configured to store a weighting coefficient for each of the frequency bands; anda weighting coefficient obtaining unit configured to obtain, from the ...

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09-03-2017 дата публикации

Low Delay Modulated Filter Bank

Номер: US20170070211A1
Автор: EKSTRAND Per
Принадлежит: DOLBY INTERNATIONAL AB

The document relates to modulated sub-sampled digital filter banks, as well as to methods and systems for the design of such filter banks. In particular, the present document proposes a method and apparatus for the improvement of low delay modulated digital filter banks. The method employs modulation of an asymmetric low-pass prototype filter and a new method for optimizing the coefficients of this filter. Further, a specific design for a 64 channel filter bank using a prototype filter length of 640 coefficients and a system delay of 319 samples is given. The method substantially reduces artifacts due to aliasing emerging from independent modifications of subband signals, for example when using a filter bank as a spectral equalizer. The method is preferably implemented in software, running on a standard PC or a digital signal processor (DSP), but can also be hardcoded on a custom chip. The method offers improvements for various types of digital equalizers, adaptive filters, multiband companders and spectral envelope adjusting filter banks used in high frequency reconstruction (HFR) or parametric stereo systems. 1. An apparatus for generating complex-valued output samples , the apparatus comprising:memory that stores real-valued input audio subband samples, a windowed sample vector, and complex-valued output audio samples; and shifts a first subset of the real-valued input audio subband samples in the memory;', 'multiplies the first subset of the real-valued input audio subband samples by the prototype filter coefficients to generate windowed samples;', 'combines the windowed samples to generate the windowed sample vector;', 'multiplies the windowed sample vector by a complex-valued exponential modulation matrix to generate complex-valued output audio subband samples; and', 'stores the complex-valued output audio subband samples in the memory., 'a complex-valued low delay analysis filter bank that generates the complex-valued output audio samples in response to the ...

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09-03-2017 дата публикации

DISCRETE TIME POLYPHASE CHANNELIZER

Номер: US20170070212A1
Принадлежит:

There is provided a finite impulse response (FIR) filter for filtering an input voltage signal to generate an output current signal, the FIR filter including a plurality of sample and hold (SH) circuits configured to simultaneously receive the input voltage signal, to sample the input voltage signal at successive sample times according to a sample clock, and to generate a plurality of sampled voltage signals, and a plurality of programmable analog multipliers coupled to the plurality of SH circuits and configured to multiply the plurality of sampled voltage signals by a plurality of binary multiplication factors to generate the output current signal. 1. A finite impulse response (FIR) filter for filtering an input voltage signal to generate an output current signal , the FIR filter comprising:a plurality of sample and hold (SH) circuits configured to simultaneously receive the input voltage signal, to sample the input voltage signal at successive sample times according to a sample clock, and to generate a plurality of sampled voltage signals; anda plurality of programmable analog multipliers coupled to the plurality of SH circuits and configured to multiply the plurality of sampled voltage signals by a plurality of binary multiplication factors to generate the output current signal.2. The FIR filter of claim 1 , wherein the plurality of sampled voltage signals have a same duration and are staggered in time.3. The FIR filter of claim 1 , further comprising a timing controller configured to generate a plurality of control signals for triggering sample times of the plurality of SH circuits claim 1 , wherein consecutive ones of the plurality of control signals are offset in time by a sampling period.4. The FIR filter of claim 1 , wherein each one of the plurality of programmable analog multipliers is configured to convert a respective one of the plurality of sampled voltage signals to a current signal before multiplying the current signal by a respective one of the ...

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27-02-2020 дата публикации

Pulse code modulation passband filter and method for obtaining multiple filter passbands

Номер: US20200067493A1
Автор: LI Yui Hung
Принадлежит:

A 1st frequency reduction circuit of a filter of the invention downsamples the sampling rate of a signal source to a predetermined value to obtain a 1st PCM stream, a 1st frequency raising circuit raises the sampling rate of the 1st PCM stream to be the same as that of the signal source, a 1st delay circuit delays a stream of the signal source, such that its phase is the same as that of the 1st PCM stream, a 1st adder subtracts the frequency raised 1st PCM steam from the delayed stream of the signal source to obtain a passband , a j-th frequency reduction circuit downsamples the sampling rate of a (j−1)-th PCM stream to a predetermined value to obtain a j-th PCM stream, wherein 2≤j≤n, a j-th frequency raising circuit raises the sampling rate of the j-th PCM stream to be the same as that of the (j−1)-th PCM stream, a j-th delay circuit delays the (j−1)-th PCM stream, such that its phase is the same as that of the j-th PCM stream, a j-th adder subtracts the frequency raised j-th PCM stream from the delayed (j−1)-th PCM stream to obtain a passband j, and when j=n, the j-th PCM stream is a passband n+1. 1. A pulse code modulation passband filter , which comprises a 1st to an n-th delay circuits , a 1st to an n-th frequency reduction circuits , a 1st to an n-th frequency raising circuits and a 1st to an n-th adders , n being an integer greater than or equal to 1 ,characterized in thatthe 1st frequency reduction circuit downsamples the sampling rate of a pulse code modulation stream from a pulse code modulation signal source to a predetermined sampling rate and thereby obtains a 1st pulse code modulation stream,the 1st frequency raising circuit raises the sampling rate of the 1st pulse code modulation stream to be the same as that of the pulse code modulation stream from the pulse code modulation signal source,the 1st delay circuit delays the pulse code modulation stream from the pulse code modulation signal source, such that its phase is the same as that of the 1st pulse ...

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27-02-2020 дата публикации

SIGNAL TRANSMISSION DEVICE AND LINKING METHOD THEREOF

Номер: US20200067557A1
Принадлежит:

A signal transmission device includes a transceiver circuitry and a control circuitry. The transceiver circuitry is configured to receive first device data from an external device through a channel. The control circuitry is configured to calculate a least one system parameter of the transceiver circuitry based on the first device data, second device data associated with the transceiver circuitry, and at least one requirement of a predetermined communication protocol, in order to link with the external device. 1. A signal transmission device comprising:a transceiver circuitry configured to receive first device data from an external device through a channel; anda control circuitry configured to calculate at least one system parameter of the transceiver circuitry based on the first device data, second device data associated with the transceiver circuitry, and at least one requirement of a predetermined communication protocol, in order to link with the external device.2. The signal transmission device of claim 1 , wherein the control circuitry is configured to perform a plurality of shift operations claim 1 , a plurality of add operations claim 1 , and a plurality of comparison operations based on the first device data and the second device data claim 1 , in order to calculate the at least one system parameter.3. The signal transmission device of claim 1 , wherein the transceiver circuitry comprises a finite impulse response filter claim 1 , and the at least one system parameter comprises a plurality of tap coefficients associated with the finite impulse response filter.4. The signal transmission device of claim 3 , wherein the control circuitry comprises:a first processing circuit configured to calculate a first tap coefficient of the plurality of tap coefficients based on a first coefficient and a first predetermined coefficient in the first device data;a second processing circuit configured to calculate a second tap coefficient of the plurality of tap coefficients ...

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07-03-2019 дата публикации

ACTIVE VIBRATION AND NOISE CONTROL DEVICE AND ACTIVE VIBRATION AND NOISE CONTROL CIRCUIT

Номер: US20190071026A1
Принадлежит:

An active vibration and noise control device robust against outside disturbances, and an active vibration and noise control circuit are provided. An adaptive control circuit of this active vibration and noise control device has autocorrelation value calculation units which calculate an autocorrelation value of an error signal or of a target signal, which is a reference signal or a standard signal, and a canceling output limiting unit which determines whether or not an autocorrelation value is less than an autocorrelation threshold value, and limits increases in the cancelling output if it is determined that the autocorrelation value is less than the autocorrelation threshold value. 1. An active vibration noise control apparatus comprising:a basic signal generating unit configured to output a basic signal indicating a target input which is a target noise or a target vibration;an adaptive control circuit configured to perform an adaptive control on the basic signal to output a control signal;a canceling output generating unit configured to generate a canceling output as a canceling sound for the target noise or a canceling vibration for the target vibration based on the control signal; andan error detection unit configured to detect an error as a difference between the canceling output and the target input at a certain evaluation point, and output an error signal, an adaptive filter configured to generate the control signal on a basis of the basic signal or a reference signal based on the basic signal;', 'a filter coefficient computing unit configured to calculate a filter coefficient of the adaptive filter based on the basic signal or the reference signal and the error signal;', 'an autocorrelation value calculation unit configured to calculate an autocorrelation value of a target signal, the target signal being the error signal or the reference or basic signal; and', 'a canceling output limiting unit configured to determine whether or not the autocorrelation value ...

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17-03-2016 дата публикации

Fast FIR Filtering Technique for Multirate Filters

Номер: US20160079960A1
Принадлежит:

Data samples are filtered by using a digital filter where the length of an impulse response of the digital filter is finite, an impulse response of the digital filter is symmetric and the operation of the digital filter is multi-rate. The method uses a polyphase decomposition to break down the input data stream into N parallel substreams and the multi-rate digital filter is separated by a polyphase decomposition into multiple lower-rate sub-filters where each of the sub-filters is separated into a set of simpler sub-sub-filters which operate upon the same set of input samples and which have impulse responses which are jointly centro-symmetric, a set of pre-filtering arithmetic structures, and a set of post-filtering arithmetic structures and performing each such pair of sub-sub-filtering operations using a single shared filter structure, a set of pre-filtering combining adders, and a set of post-filtering separating adders. 1. A method for filtering data samples comprising:using a digital filter to act upon a input data stream in order to transform it into an output data stream, wherein:the length of an impulse response of the digital filter is finite;an impulse response of the digital filter is symmetric;the operation of the digital filter is multi-rate;using a polyphase decomposition to break down the input data stream into N parallel substreams;the multi-rate digital filter being separated by a polyphase decomposition into multiple lower-rate sub-filters;each of the sub-filters being separated one or more times into a set of simpler sub-sub-filters, a set of pre-filtering arithmetic structures, and a set of post-filtering arithmetic structures, according to a fast FIR filtering decomposition algorithm;the set of sub-sub-filters comprising one or more pairs of sub-sub-filters which operate upon the same set of input samples and which have impulse responses which are jointly centro-symmetric;and performing each such pair of sub-sub-filtering operations using a ...

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17-03-2016 дата публикации

PRECISION FREQUENCY MONITOR

Номер: US20160079961A1
Автор: Jin Qu Gary
Принадлежит:

A precision frequency monitor provides a precision frequency monitor value (PFM) indicative of the precision of the frequency or period of an input reference signal. A first averaging module is responsive to the input reference signal to find an average frequency or period during successive predetermined time periods defining operational cycles. A second averaging module is responsive to an output of the first averaging module to average the output of the first averaging module over N operational cycles, where N is an integer, and output an updated PFM value every N operational cycles. An infinite impulse response (IIR) filter is responsive to the output of the first averaging module to filter the output of the first averaging module to output interim updated PFM values within each sequence of N operational cycles. 1. A precision frequency monitor for providing a precision frequency monitor value (PFM) indicative of the precision of the frequency or period of an input reference signal , comprising:a first averaging module responsive to the input reference signal to find an average frequency or period during successive predetermined time periods defining operational cycles;a second averaging module responsive to an output of the first averaging module to average the output of the first averaging module over N operational cycles, where N is an integer, and output an updated PFM value every N operational cycles; andan infinite impulse response (IIR) filter responsive to the output of the first averaging module to filter the output of the first averaging module to output interim updated PFM values within each sequence of N operational cycles.2. A precision frequency monitor as claimed in claim 1 , wherein the IIR filter is a one pole filter.3. A precision frequency monitor as claimed in claim 1 , wherein the second averaging module comprises an adder with a unit delay register in a feedback loop followed by a divider-by-N.4. A precision frequency monitor as claimed in ...

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16-03-2017 дата публикации

Method of Operating a Finite Impulse Response Filter

Номер: US20170077905A1
Автор: CHOI Jaeyoung
Принадлежит:

According to one aspect of the invention, there is provided a method of operating a finite impulse response filter comprising an input; an output; and a plurality of storage elements, each coupled to the input via a sample switch and to the output via a transfer switch, the method comprising: during charging of the plurality of storage elements, applying a sample clock signal to each of the sample switches that achieves an operation mode where up to every one of the sample switches is simultaneously closed to connect all of the plurality of storage elements to the input; and during averaging of the plurality of storage elements, applying a transfer clock signal to each of the transfer switches to close one or more of the transfer switches to connect the storage elements, having charge stored therein, to the output. 1. A method of operating a finite impulse response filter comprisingan input;an output; anda plurality of storage elements, each coupled to the input via a sample switch and to the output via a transfer switch, the method comprising:during charging of the plurality of storage elements, applying a sample clock signal to each of the sample switches that achieves an operation mode where up to every one of the sample switches is simultaneously closed to connect all of the plurality of storage elements to the input; andduring averaging of the plurality of storage elements, applying a transfer clock signal to each of the transfer switches to close one or more of the transfer switches to connect the storage elements, having charge stored therein, to the output.2. The method of claim 1 , wherein the total number of sample switches that are closed is determined by a filter order requirement of the finite impulse response filter.3. The method of claim 1 , wherein all of the transfer switches are simultaneously closed during the averaging of the plurality of storage elements.4. The method of claim 1 , wherein the operation mode of having up to every one of the ...

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16-03-2017 дата публикации

ESTIMATING SECONDARY PATH PHASE IN ACTIVE NOISE CONTROL

Номер: US20170077906A1
Принадлежит:

The technology described in this document can be embodied in a computer-implemented method that includes receiving, by one or more processing devices, a first plurality of values representing a set of coefficients of an adaptive filter disposed in an active noise cancellation system. The method also includes accessing one or more estimates of instantaneous phase values associated with a transfer function representing an effect of a secondary path of the active noise cancellation system, and updating the first plurality of values based on the one or more estimates of the instantaneous phase values to generate a set of updated coefficients for the adaptive filter. The method further includes programming the adaptive filter with the set of updated coefficients to affect operation of the adaptive filter. 1. A computer-implemented method comprising:receiving, by one or more processing devices, a first plurality of values representing a set of coefficients of an adaptive filter disposed in an active noise cancellation system;accessing one or more estimates of instantaneous phase values associated with a transfer function representing an effect of a secondary path of the active noise cancellation system;updating the first plurality of values based on the one or more estimates of the instantaneous phase values to generate a set of updated coefficients for the adaptive filter; andprogramming the adaptive filter with the set of updated coefficients to affect operation of the adaptive filter.2. The method of claim 1 , further comprising:generating one or more updated estimates of the instantaneous phase values;updating the first plurality of values based on the one or more updated estimates of the instantaneous phase values to generate a second set of updated coefficients for the adaptive filter; andprogramming the adaptive filter with the second set of updated coefficients to affect operation of the adaptive filter.3. The method of claim 1 , further comprising:receiving a ...

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14-03-2019 дата публикации

METHOD FOR EQUIVALENT HIGH SAMPLING RATE FIR FILTERING BASED ON FPGA

Номер: US20190080035A1

The present invention provides a method for equivalent high sampling rate FIR filtering based on FPGA, first, the coefficients h(k) of FIR filter are found by using MATLAB, multiplied by an integer and then rounded for the purpose that the rounded coefficients h(k) can be directly used into a FPGA, then the ADC's output of high data rate fis lowered by dividing the ADC's output x(n) into M parallel data streams x(n) of low data rate, and the M×L samples in one clock circle is obtained by delaying the M parallel data streams x(n) simultaneously by 1, 2, . . . , L′ periods of the synchronous clock, at last, the samples y(n) of FIR filtering output is calculated according to the samples selected from the M×L samples, and the filtered data y(n) of data rate fis obtained by putting the samples y(n) together in ascending order of i. Thus, the continuous FIR filtering of an ADC's output sampled with high sampling rate is realized, while the data rates before and after the FIR filtering are unchanged. 2. The method for equivalent high sampling rate FIR filtering based on FPGA of claim 1 , wherein the integer is selected as the integral power of 2. This application claims priority under the Paris Convention to Chinese Patent Application No. 201711015633.X, Filed Oct. 26, 2017, the entirety of which is hereby incorporated by reference for all purposes as if fully set forth herein.The present invention relates to the field of FIR (Finite Impulse Response) filtering, more particularly to a method for equivalent high sampling rate FIR filtering based on FPGA (Field-Programmable Gate Array), which can be applied to the FIR filtering that the highest system clock frequency of a FPGA is lower than the sampling clock frequency of an ADC (Analog-to-digital converter).FIR filter stands for finite impulse response filter, and is also called as non-recursive filter. FIR filter is the most basic electronic component in digital signal processing system. FIR filter has a strict linear ...

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22-03-2018 дата публикации

ELECTRONIC DEVICE IN WIRELESS COMMUNICATIONS SYSTEM, WIRELESS COMMUNICATIONS SYSTEM, AND METHOD

Номер: US20180083805A1
Автор: Dang Jian, XIANG Nan
Принадлежит: SONY CORPORATION

An electronic device in a wireless communications system, the wireless communications system, and a method. The electronic device includes: a reception unit, configured to receive a signal from another electronic device in a wireless communications system; an analysis filtering unit, configured to set an analysis filter group according to a parameter of a non-perfect reconstruction filter group, decompose, by using the analysis filter group, signals received by the reception unit into multiple paths of sub-band signals and perform analysis filtering; and an interference cancellation unit, configured to, for each path of sub-band signals among multiple paths of sub-band signals, cancel inter-band interference in each path of sub-band signals according to each path of sub-band signals and neighboring sub-band signals thereof. 121-. (canceled)22. An electronic device in a wireless communication system , comprising:circuitry, configured to:receive a signal from an other electronic device in the wireless communication system;arrange an analysis filter bank based on parameters of a Non-Perfect Reconstruction filter bank, decompose the received signal into multiple paths of subband signals using the analysis filter bank, and perform analysis filtering; andeliminate, for each path of subband signal among the multiple paths of subband signals, inter-subband interference in each path of subband signal, based on each path of subband signal and its neighboring subband signal.23. The electronic device according to claim 22 , wherein the circuitry is configured to eliminate the inter-subband interference in each path of subband signal in an iterative manner.24. The electronic device according to claim 23 , wherein the circuitry is configured to:initialize each path of estimated subband signal and a number of times of iterations;estimate, based on a neighboring subband signal of each path of subband signal estimated during a last time of iteration, an interference signal for each ...

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24-03-2016 дата публикации

Digital compensation for a non-linear analog receiver

Номер: US20160087604A1
Принадлежит: Nanosemi Inc

Aspects and embodiments are directed to non-linear systems including a digital compensator structure, a method of digital compensation, and methods for designing digital compensator structures for analog receivers. A digital compensator is configured to substantially reduce the one or more nonlinear distortion components in the sampled digital output signal from the analog receiver to provide an output signal achieving a receiver linearity requirement for the combination of the analog receiver and a digital compensator.

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24-03-2016 дата публикации

ADAPTIVE CONTINUOUS-TIME FILTER ADJUSTMENT DEVICE

Номер: US20160087605A1
Принадлежит:

A device includes a controller and an adaptive continuous-time filter that includes a control input and a first array of elements. The controller generates a digital word responsive to a time constant and compares a select bit of the digital word to a corresponding reference word to generate a control bit. The controller includes a duplicate array of elements, and applies the control bit to an adjustable element of the duplicate array of elements to modify the time constant. The controller provides the output word to the control input of the adaptive continuous-time filter to generate a filter response that accounts for effects of semiconductor process variation in the first array of elements.

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31-03-2022 дата публикации

Downscaler and Method of Downscaling

Номер: US20220100466A1
Принадлежит: Imagination Technologies Ltd

A hardware downscaler and an architecture for implementing a FIR filter in which the downscaler can be arranged for downscaling by a half in one dimension. The downscaler can comprise: hardware logic implementing a first three-tap FIR filter; and hardware logic implementing a second three-tap FIR filter; wherein the output from the hardware logic implementing the first three-tap filter is provided as an input to the hardware logic implementing the second three-tap filter.

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25-03-2021 дата публикации

RESOURCE CONSERVING WEIGHTED OVERLAP-ADD CHANNELIZER

Номер: US20210091752A1
Автор: Zhang Hanhui
Принадлежит: HUGHES NETWORK SYSTEMS, LLC

Systems and methods are provided for channelizing. A first stage can provide a WOLA filter bank that can apply a single multiplier resource to perform window weighting for multiple WOLA filter banks. The first stage can remove mixer-based post FFT adjustment and provide equal functionality with a particular modification of tuning mixers at inputs of second stage FIR paths. The first stage can include a variable decimation, using a particular implementation of variable sample block size. 1. A channelizer comprising:a window buffer, configured to store a sequence of signal samples;a weighting logic, coupled to the window buffer, configured to apply a sequence of weighting coefficients to the sequence of signal samples, and output a corresponding sequence of weighted signal (WST) samples;a regrouping logic, configured to group the WST samples into a concatenation of D WST sample blocks, each of the D WST sample blocks including K WST samples, K being an integer;a time folding logic, configured to generate a first time-folded sum, based at least in part on a summation of the D WST sample blocks, and a second time-folded sum based at least in part on a summation of a first plurality of the D WST sample blocks and a subtraction of a second plurality of the D WST sample blocks;a mixer logic, configured to frequency shift the second time-folded sum and output a corresponding adjusted second time-folded sum;a first discrete Fourier Transform logic, configured to generate a first plurality of bandpass outputs, based at least in part on applying a discrete Fourier Transform to the first time-folded sum; anda second discrete Fourier Transform logic, configured to generate a second plurality of bandpass outputs, based at least in part on applying a discrete Fourier Transform to the adjusted second time-folded sum.2. The channelizer of claim 1 , wherein the window buffer is configured to:store integer L of the signal samples as a concatenation of K blocks, each of the K blocks ...

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31-03-2016 дата публикации

Sample rate converter, an analog to digital converter including a sample rate converter and a method of converting a data stream from one data rate to another data rate

Номер: US20160094240A1
Принадлежит: ANALOG DEVICES TECHNOLOGY

It is known to perform sample rate conversion. A sample rate converter is arranged to receive digital data at an input sample rate F s and to output data at an output sample rate F o , where F o =F s /N, and N is decimation factor greater than 1. A problem can arise with sample rate converters when a user wishes to change the decimation rate. Generally a sample rate converter needs to discard the samples in its filter when the decimation rate is changed, and the filter output is unusable until the filter has refilled with values taken at the new decimation rate. The sample rate converter provided here does not suffer from this problem. The sample rate converter includes at least Q channels. Each channel comprises a Qth order filter arranged to select input signals at predetermined intervals from a run of P input signals, and to form a weighted sum of the selected input signals to generate an output value, and where the runs of P input signals of one channel are offset from the runs of P signals of the other channels.

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19-06-2014 дата публикации

Transmitter finite impulse response characterization

Номер: US20140172935A1
Принадлежит: Oracle International Corp

A finite impulse response (FIR) extractor includes at least one controller. The controller injects specified FIR tap values into a first captured waveform that results from transmitting a raw waveform through a transmitter circuit including a FIR filter having pre and post cursor tap values set to zero to create an expected waveform, and injects the specified FIR tap values into the raw waveform to create an ideal waveform. The controller further projects the expected and ideal waveforms onto a second captured waveform that results from transmitting the ideal waveform through the transmitter circuit with the pre and post cursor tap values set to the specified FIR tap values to create a compensated waveform, and extracts FIR tap values from the compensated waveform.

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05-05-2022 дата публикации

METHOD AND DEVICE FOR CONTROLLING FIR FILTER

Номер: US20220141585A1
Принадлежит:

A method for controlling an FIR filter that processes sound signals based on setting of a band filter includes receiving, from a user, an instruction for control data that indicate a gain parameter of an amplitude characteristic corresponding to a transfer function represented as a function of angular frequency, generating a first amplitude characteristic that is an amplitude characteristic of the band filter, as a basis of an amplitude characteristic of the FIR filter, in accordance with the control data, receiving an instruction for a gain limit value from the user, limiting a gain curve of the first amplitude characteristic so as to be within the gain limit value that has been instructed, thereby acquiring a second amplitude characteristic, and setting filter coefficients of the FIR filter based on the second amplitude characteristic.

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05-05-2022 дата публикации

LOUDSPEAKER DRIVER SYSTEMS

Номер: US20220141593A1
Автор: Lesso John P.

A system for driving a transducer having a plurality of coils, the system comprising: a modulator for outputting a digital output signal representative of a received analogue input signal at a modulator output; a clock controlled delay element for applying a delay to the digital output signal to generate a first delayed signal at a delay element output; wherein the modulator output is couplable to a first coil of the plurality of the coils of the transducer and the delay element output is couplable to a second coil of the plurality of coils of the transducer.

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19-03-2020 дата публикации

Digital signal conditioner system

Номер: US20200091947A1
Принадлежит: Viasat Inc

One example includes a digital signal conditioner (DSC) system. A sample selector bank receives a digital sample block of an input signal that is provided at a supported input oversampling factor and selects a subset of samples from the digital sample block based on a selection signal. A tap weights selector bank generates a set of tap weights based on the selection signal. A filter bank receives the subset of the samples from each of the sample selectors and a respective set of tap weights. Each filter provides a weighted sample associated with the respective subset of samples and the respective set of tap weights. A reformattor receives the weighted sample from each of the filters and provides a filtered sample block including the weighted sample from a subset of the filters at an output oversampling factor for each supported input oversampling factor based on a selected supported resampling ratio.

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14-04-2016 дата публикации

DIGITAL FILTER DEVICE AND SIGNAL PROCESSING METHOD

Номер: US20160105160A1
Автор: Hosokawa Kohei
Принадлежит:

Provided is a digital filter device including data rearrangement means for executing rearrangement of input data and outputting rearranged data, intermediate data calculation means for processing the rearranged data input at a specific time and generating intermediate data, filter output first calculation means for calculating a first output value at the specific time by use of the intermediate data, delay means for delaying the rearranged data by processing time taken in the intermediate data calculation means and the file output first calculation means, and filter output second calculation means for inputting output values from the delay means and the filter output first calculation means, calculating a second output value at a time other than the specific time, and outputting a filter output value obtained by adding up the first and second output values. Consequently, it becomes feasible to reduce a circuit scale without impairing performance of a digital filter used in nonlinear compensation and realize nonlinear compensation by an LSI. 1. A digital filter device comprising:a data rearrangement unit which executes rearrangement of input data and outputting rearranged data;an intermediate data calculation unit which processes the rearranged data input at a specific time and generating intermediate data;a filter output first calculation unit which calculates a first output value at the specific time by use of the intermediate data;a delay unit which delays the rearranged data by processing time taken in the intermediate data calculation unit and the filter output first calculation unit; anda filter output second calculation unit which inputs output values from the delay unit and the filter output first calculation unit, calculating a second output value at a time other than the specific time, and outputting a filter output value obtained by adding up the first and second output values.2. The digital filter device according to claim 1 , whereinthe data ...

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04-04-2019 дата публикации

APPARATUS AND METHOD FOR PERFORMING HORIZONTAL FILTER OPERATIONS

Номер: US20190103857A1
Принадлежит:

An apparatus and method for performing FIR filtering and blending operations. A processor comprising: a decode unit to decode a packed N-tap finite impulse response (FIR) filter instruction, the packed N-tap FIR filter instruction to indicate one or more source packed data operands comprising a plurality of packed data elements, at least 3 filter coefficients, and a destination storage location, the plurality of packed data elements comprising data from a signal to be filtered and the plurality of filter coefficients specifying a filter function to be applied; and an execution unit comprising an FIR unit coupled with the decode unit, the FIR unit, in response to the packed N-tap FIR filter instruction being decoded by the decode unit, to perform at least N−1 multiplications to generate at least N−1 products, each of the multiplications comprising one of the filter coefficients multiplied by one of the packed data elements, the execution unit to combine the at least N−1 products in accordance with a specified type of FIR filter being implemented to generate a result packed data element to be stored in the destination storage location. 1. A processor comprising:a decode unit to decode a packed N-tap finite impulse response (FIR) filter instruction, the packed N-tap FIR filter instruction to indicate one or more source packed data operands comprising a plurality of packed data elements, at least 3 filter coefficients, and a destination storage location, the plurality of packed data elements comprising data from a signal to be filtered and the plurality of filter coefficients specifying a filter function to be applied; andan execution unit comprising an FIR unit coupled with the decode unit, the FIR unit, in response to the packed N-tap FIR filter instruction being decoded by the decode unit, to perform at least N−1 multiplications to generate at least N−1 products, each of the multiplications comprising one of the filter coefficients multiplied by one of the packed ...

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19-04-2018 дата публикации

Delta-sigma modulator

Номер: US20180109268A1

A delta-sigma modulator includes a first integrator configured to integrate a sum of an input signal and a first feedback signal, a second integrator configured to integrate a sum of an output value of the first integrator and a second feedback signal, a first FIR filter circuit configured to perform a first FIR filtering on an output modulation signal and a delay modulation signal and feeds back the signals to stage prior to the first integrator, and a second FIR filter circuit configured to perform a second FIR filtering on the output modulation signal and the delay modulation signal and feeds back the signals to a stage prior to the second integrator.

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07-05-2015 дата публикации

Electrical apparatus with a filter for suppressing interference signals

Номер: US20150123469A1
Принадлежит:

An electrical apparatus for a vehicle has a primary control unit for controlling and supplying the electrical apparatus with energy and a secondary output unit subordinate to the control unit and outputs data transmitted by the control unit. The control unit and the output unit are connected to one another via a data line. The control unit has an electrical filter with three inductor coils for suppressing interference signals. The inductor coils are inductively coupled to one another such that a direction of a magnetic flux produced by a first flow of current in the first inductor coil and of a magnetic flux produced by a second flow of current in the second inductor coil in the main body is opposite a direction of a further magnetic flux produced by a third flow of current in the third inductor coil in the main body. 111-. (canceled)121. An electrical apparatus () for a vehicle , the apparatus comprising:{'b': 2', '1, 'a primary control unit () configured to control and supply energy to the electrical apparatus (); and'}{'b': 3', '2', '2', '2', '3', '5, 'a secondary output unit (), downstream of the primary control unit (), configured to output data transmitted from the control unit (), the primary control unit () and the secondary output unit () being connected to one another via a data line (),'}{'b': 2', '16', '17', '18', '19', '17', '18', '19, 'wherein the control unit () comprises an electrical filter () configured to suppress interference signals having three inductors (, , ) that are: (a) arranged on a ferromagnetic base body, (b) electrically isolated from one another and (c) inductively coupled to one another such that a direction of a magnetic flux generated in the base body by a first current flow in the first inductor () and by a second current flow in the second inductor () is opposite a direction of a further magnetic flux generated in the base body by a third current flow in the third inductor (), and'}{'b': 17', '2', '18', '3', '4', '2', '3', '19', ...

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12-05-2016 дата публикации

PROPAGATION DELAY CORRECTION APPARATUS AND PROPAGATION DELAY CORRECTION METHOD

Номер: US20160134985A1
Принадлежит: Clarion Co., Ltd.

A propagation delay tune correction apparatus comprising a means for generating a frequency spectrum signal by performing short-term Fourier transform on an audio signal; a means for setting a propagation delay time for each of a plurality of predetermined frequency bands a means for calculating a phase control amount for each of the plurality of predetermined frequency bands on a basis of the propagation delay time set for each of the plurality of predetermined frequency bands; a means for generating a phase control signal by smoothing the calculated phase control amount for each of the plurality of predetermined frequency hands; a means for controlling a phase of the frequency spectrum signal for each of the plurality of predetermined frequency bands on a basis of the generated phase control signal; and a means for generating an audio signal on which a propagation delay correction is performed by performing inverse short-term Fourier transform on the frequency spectrum signal of which the phase is controlled for each of the plurality of predetermined frequency bands. 1. A propagation delay time correction apparatus , comprising:a frequency spectrum signal generating unit configured to generate a frequency spectrum signal by performing short-term Fourier transform on an audio signal;a propagation delay time setting unit configured to set a propagation delay time for each of a plurality of predetermined frequency bands;a phase control amount calculation unit configured to calculate a phase control amount for each of the plurality of predetermined frequency bands on a basis of the propagation delay time set for each of the plurality of predetermined frequency bands;a phase control signal generating unit configured to generate a phase control signal by smoothing the calculated phase control amount for each of the plurality of predetermined frequency bands;a phase control unit configured to control a phase of the frequency spectrum signal for each of the plurality of ...

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11-05-2017 дата публикации

IMAGE STABILIZATION APPARATUS AND IMAGE STABILIZATION METHOD

Номер: US20170134658A1
Автор: Miyahara Shimpei
Принадлежит:

An image stabilization apparatus comprises: an identification unit that, based on an angular velocity signal outputted from a shake detection unit, a motion vector calculated from a difference between frames of images outputted from an image sensor, and a position signal indicating a position of a correction unit that corrects a shake optically, identifies an output variation of the shake detection unit; and a conversion unit that converts the angular velocity signal into a shake correction amount by correcting the angular velocity signal based on the output variation identified by the identification unit. 1. An image stabilization apparatus comprising:an identification unit that, based on an angular velocity signal outputted from a shake detection unit, a motion vector calculated from a difference between frames of images outputted from an image sensor, and a position signal indicating a position of a correction unit that corrects a shake optically, identifies an output variation of the shake detection unit; anda conversion unit that converts the angular velocity signal into a shake correction amount by correcting the angular velocity signal based on the output variation identified by the identification unit.2. The image stabilization apparatus according to claim 1 , wherein a position detection unit that outputs the position detection signal detects the position of the correction unit and outputs the position signal.3. The image stabilization apparatus according to claim 2 , wherein the position detection unit predicts the position of the correction unit from the angular velocity signal and outputs the position signal.4. The image stabilization apparatus according to claim 1 , wherein the conversion unit claim 1 , based on the output variation claim 1 , changes a coefficient used in the conversion.5. The image stabilization apparatus according to claim 1 , wherein the output variation includes variation of a sensitivity and an offset of the shake detection unit.6. ...

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11-05-2017 дата публикации

MULTI-RATE FILTER SYSTEM

Номер: US20170134854A1
Принадлежит:

A multi-rate filter system is disclosed. More particularly, a computationally efficient multi-rate filter system for processing an audio stream on a consumer electronics device is disclosed. The multi-rate filter system includes a plurality of multi-rate filtering blocks, at least one block including a linear filter component. At least one multi-rate filtering block may include a nonlinear signal processing component. The multi-rate filter system may include a nonlinear functional block. A method of filtering a signal is also disclosed. 1. A multi-rate filter system comprising:an input channel configured to receive an input signal;an output channel configured to output a filtered signal; anda cascade of multi-rate filter blocks coupled between the input channel and the output channel, at least one of the multi-rate filter blocks comprising:a bandselector comprising a bandselector input, a highpass bandselector output, a lowpass bandselector output connected to a subsequent multi- rate filter block, and a downsampler connected between the bandselector input and the lowpass bandselector output;a signal processing block coupled to the highpass bandselector output, the signal processing block comprising a linear filter component and a nonlinear filter component connected to the linear filter component; anda bandcombiner connected to the signal processing block, the bandcombiner comprising two bandcombiner inputs, a bandcombiner output, and an upsampler, a first bandcombiner input connected to the signal processing block, a second bandcombiner input connected to a subsequent multi-rate filter block, and the bandcombiner output connected to a prior multi-rate filter block, the upsampler connected between the bandcombiner inputs and the bandcombiner output.2. The multi-rate filter system in accordance with claim 1 , wherein the nonlinear filter component has an input and an output claim 1 , and the output is a nonlinear function of the input.3. The multi-rate filter system ...

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19-05-2016 дата публикации

DIGITAL FILTER DEVICE, DIGITAL FILTERING METHOD, AND STORAGE MEDIUM HAVING DIGITAL FILTER PROGRAM STORED THEREON

Номер: US20160140083A1
Автор: Shibayama Atsufumi
Принадлежит:

In order to reduce the power consumed when using FFT processing and filtering in the frequency domain together, a digital filter device according to the present invention is provided with: a first filtering means for performing a first fast Fourier transformation using a first data sorting process, first filtering in the frequency domain, a first inverse fast Fourier transformation using a second data sorting process, and overlap removal on a first input block including overlapped data; a second filtering means for performing a second fast Fourier transformation, which simultaneously processes all data in a second input block including overlapped data, second filtering in the frequency domain, a second inverse fast Fourier transformation, which simultaneously processes all received filtered data, and overlap removal; and a data selection means for selecting either the first filtering means or the second filtering means, wherein the operation of the filtering means that is not selected by the data selection means is interrupted. 1. A digital filter device comprising: a first overlap addition unit which generates a first overlap block where a first input block comprising time-domain consecutive N-M pieces of input data (where N is a positive integer and M is a positive integer equal to or less than N) is given additional consecutive M pieces of data immediately preceding the first input block;', 'a first fast Fourier transform unit which transforms, through a fast Fourier transform process involving a first data sorting process, the first overlap block into a first frequency-domain block being in a frequency domain;', 'a first filter computation unit which performs a first filtering process on the first frequency-domain block;', 'a first inverse fast Fourier transform unit which transforms, through an inverse fast Fourier transform process involving a second data sorting process, the first processed block which underwent the first filtering process into a first time- ...

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02-05-2019 дата публикации

FILTER COEFFICIENT CALCULATION DEVICE, SIGNAL GENERATION DEVICE INCLUDING THE SAME, FILTER COEFFICIENT CALCULATION METHOD, AND SIGNAL GENERATION METHOD

Номер: US20190131957A1
Автор: HOSAKA Yasuo
Принадлежит:

A filter coefficient calculation device includes a function unit that has a plurality of functions to be executed by an FIR filter, a function selection unit that selects one or a plurality of functions from among the plurality of functions, and a filter coefficient calculation unit that calculates a filter coefficient in the selected one or plurality of functions, and is configured such that the function unit includes a first transfer function calculation unit, a second transfer function calculation unit, and a third transfer function calculation unit which calculate a transfer function of the FIR filter in the respective functions, and the filter coefficient calculation unit performs inverse Fourier transform on the transfer function in the selected one function or a product of the transfer functions in the plurality of functions to obtain an impulse response of the FIR filter and calculates the impulse response as the filter coefficient. 1. A signal generation device comprising:a filter coefficient calculation device;signal generation means for generating a signal for testing a test target device; anda finite impulse response filter which has a plurality of predetermined functions executable by the finite impulse response filter depending on a filter coefficient, for setting a filter coefficient calculated by the filter coefficient calculation device, receiving the signal from the signal generation means, performing one or some functions on the signal, and outputting the signal to the test target device,wherein the filter coefficient calculation device comprises:a plurality of transfer function calculation means for calculating transfer functions of the finite impulse response filter, each of the plurality of transfer function calculation means corresponds to each of the plurality of predetermined functions of the finite impulse response filter;selection means for selecting one or some of the transfer functions in the plurality of the transfer function ...

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02-05-2019 дата публикации

COMPARATOR ERROR SUPPRESSION

Номер: US20190131988A1
Автор: LI HONGXING
Принадлежит:

Comparator input noise or offset suppression can include an error detector circuit that can operate in a feedback loop, such as during an autozero phase. The error detector circuit can include a time-varying filter response to improve accuracy and convergence time. The comparator can be used in a successive approximation routine (SAR) or other analog-to-digital converter (ADC) circuit, such as to control a digital-to-analog converter (DAC), such as can be used to adjust a tuning circuit within the comparator to compensate for noise or offset. The DAC can be combined with a DAC used for carrying out SAR bit-trials or bit decisions. 1. A system including circuitry for making a comparison capable of compensating for at least one of noise or offset , the system comprising:a comparator circuit, including a comparator output and at least first and second comparator inputs; andan error detector circuit, including an error detector input coupled to the comparator output, and an error detector output coupled to an input of the comparator circuit, wherein the error detector circuit includes a filter circuit, having a time varying filter response, responsive to multiple signal values of the comparator output to adjust a signal value provided to the comparator circuit, the time-varying filter response including a time-varying gain that decreases, during an auto-zero phase or a bit-trial or other comparison phase, from an initial gain value to limit noise during that phase.2. The system of claim 1 , in which the first and second comparator inputs of the comparator circuit are coupled to the same voltage during an auto-zero mode claim 1 , and wherein the filter circuit is responsive to multiple signal values of the comparator output during the auto zero mode to adjust a compensation signal value provided to the comparator circuit to compensate for at least one of noise or offset.3. The system of claim 2 , in which the error detector circuit includes:an accumulator circuit, ...

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08-09-2022 дата публикации

Signal processing apparatus for generating a plurality of output samples using combiner logic based on a hiearchichal tree structure

Номер: US20220283983A1
Автор: Christian VOLMER
Принадлежит: Advantest Corp

Embodiments of the present invention provide a digital signal processing apparatus including a combiner logic and a plurality of processing cores. Input samples of the digital signal processing apparatus are provided to the plurality of processing cores. Sets of output samples of the processing cores are provided to the combiner logic as input samples, and the sets of samples are provided to the combiner nodes c of the highest hierarchical level (h=0). A digital signal processing apparatus or a parallel decimating digital convolver may be used as a building block of a signal processor application-specific integrated circuit (ASIC) and/or part of other instruments for generating output samples. Furthermore, applications of the digital signal processing apparatus described herein can be addressed on a parallel DSP, in a response time of real-time or near to real-time, for flexible (or almost arbitrary high) sample rates.

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08-09-2022 дата публикации

Signal processing apparatus for generating a plurality of output samples

Номер: US20220286114A1
Автор: Christian VOLMER
Принадлежит: Advantest Corp

Embodiments of the present invention provide a digital signal processing apparatus, including an interpolator, an interpolating convolver, or the like, for providing a plurality of output samples or output values in parallel, such as P output samples provided by P Farrow cores, based on a set of input samples or input values, such as 2P+M−2 samples. The digital signal processing apparatus includes a sample distribution logic or structure configured to provide a plurality of subsets of the set of input samples to a plurality of processing cores, such as interpolation cores (e.g., Farrow cores) that perform processing operations associated with different time shifts, for example with respect to a reference time (e.g., a time associated with the input samples). The sample distribution logic includes a hierarchical tree structure having a plurality of hierarchical levels of splitting nodes.

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09-05-2019 дата публикации

Low Loss Reflective Passive Phase Shifter using Time Delay Element

Номер: US20190140622A1
Принадлежит:

A phase shifter for altering the phase of a radio frequency signal is disclosed herein. A Lange coupler is used having reflective ports that are coupled to artificial transmission lines. The artificial transmission lines provide a reflection transmission path, the length of which can be determined by digital control lines. Transistors placed along the length of the central trace provide independent paths to ground that serve to shorten the electrical length of the ATL. Accordingly, by selectively turning the transistors on/off, the electrical length of the ATL can be selected and thus the amount of phase delay introduced by the phase shifter. 1. A phase shifter comprising:(a) a radio frequency coupler having a input port, direct port, coupled port and isolation port;(b) a first central trace coupled between the direct port and ground;(c) a second central trace coupled between the coupled port and ground;(d) a first plurality of switches having a first terminal, a second terminal and a control terminal, the first terminal of each of the first plurality of switches coupled at intervals to the first central trace and the second terminal of each switch of the first plurality of switches coupled to ground; and(e) a second plurality of switches having a first terminal, a second terminal and a control terminal, the first terminal of each of the second plurality of switches coupled at intervals to the second central trace and the second terminal of each switch of the second plurality of switches coupled to ground.2. The phase shifter of claim 1 , wherein for each switch among the first plurality of switches claim 1 , there is a corresponding switch among the second plurality of switches claim 1 , the distance between each switch of the first plurality of switches and the proximal end of the first central trace being the same as the distance between the corresponding switch of the second plurality of switches and the proximal end of the second central trace.3. The phase ...

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09-05-2019 дата публикации

Decimation Filter

Номер: US20190140625A1
Принадлежит:

Filters are discussed where a first window function and a second window function are applied to a digital input signal, wherein a window length of the first window function is longer than a window length of the second window function. The results of this windowing are integrated. 1. A device , comprising:a windowing circuit configured to apply a first window function to a first digital signal to generate a second digital signal and to apply a second window function to the first digital signal to generate a third digital signal, wherein a window length of the first window function is longer than a second window length of the second window function,a first integrator configured to receive the second digital signal, anda second integrator configured to receive the third digital signal.2. The device of claim 1 , wherein the first window length is an integer multiple of the second window length.3. The device of claim 1 , wherein a sampling rate of a fourth digital signal output by the first integrator and a fifth digital signal output by the second integrator is lower than a sampling rate of the first digital signal.4. The device of claim 1 , wherein at least one of the first window function and the second window function is selected from the group consisting of a Tuckey window claim 1 , a Hamming window or a Hanning window.5. The device of claim 1 , wherein the windowing circuit comprises a window function generator configured to generate at least one of the first and second window function based on an interpolation between supporting points.6. The device of claim 1 , wherein the windowing circuit comprises a window function generator configured to generate the second window function claim 1 , wherein the windowing circuit is configured to apply the first window function by:applying a first part of the second window function to generate first samples of the second digital signal, followed byscaling samples of the first digital signal by a maximum value of the second ...

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25-05-2017 дата публикации

METHOD FOR DYNAMIC NOISE REDUCTION OF MAGNETIC FIELD SENSOR SIGNALS AND A MAGNETIC FIELD SENSOR CIRCUIT WITH DYNAMIC NOISE REDUCTION

Номер: US20170146614A1
Принадлежит: Micronas GmbH

A method for dynamic noise reduction of magnetic field sensor signals of a magnetic field sensor circuit with a magnetic field sensor and a switching device, wherein the magnetic field sensor provides a sensor signal to a sensor output, and wherein the switching device comprises a signal comparator, a low pass filter and a multiplexer, and wherein the switching device comprises a signal input interconnected with the sensor signal output and a signal output, and wherein the signal comparator has a first input interconnected with the signal input and a second input interconnected with the low pass filter, and a control signal output interconnected with the multiplexer. In a first method step, the sensor signal is compared to the level of a signal of the low pass filter by means of the signal comparator, and the result is compared to a predetermined threshold value. 1. A method for dynamic noise reduction of magnetic field sensor signals of a magnetic field sensor circuit with a magnetic field sensor and a switching device , the method comprising:providing, via the magnetic field sensor, a sensor signal to a sensor signal output;providing the switching device with a signal comparator, a low pass filter, and a multiplexer, the switching device having a signal input interconnected with the sensor signal output and a signal output, the signal comparator having a first input interconnected with the signal input and a second input interconnected with the low pass filter and a control signal output interconnected with the multiplexer, the multiplexer having a first input interconnected with the signal input and a second input interconnected with the output of the low pass filter and an output interconnected with the signal output;comparing the sensor signal to a level of a signal of the low pass filter via the signal comparator;comparing the result to a predetermined threshold value; andperforming, provided that the result exceeds the predetermined threshold value, a ...

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25-05-2017 дата публикации

IMPROVED DESIGN METHOD OF TWO-STAGE FRM FILTER

Номер: US20170149416A1
Автор: HUANG Shaoguang, Wei Ying
Принадлежит: Shandong University

An improved design method of a two-stage FRM filter includes the following steps: constructing an improved two-stage FRM filter; calculating passband and stopband edge parameters of a prototype filter, passband and stopband edge parameters of a second-stage masking filter and passband and stopband edge parameters of a first-stage masking filter in Case A and Case B, respectively; calculating the complexity of the FRM filter according to the obtained parameters, and finding out one or more sets [M, P, Q] having the lowest complexity within a search range; and optimizing the improved FRM filter. The improved design method of a two-stage FRM filter has the following beneficial effect: as compared to a conventional design method of a two-stage FRM filter, the complexity of a narrow-band FIR (Finite Impulse Response) filter can be reduced through design using the improved method, and power consumption is thus reduced in hardware implementation. 1. An improved design method of a two-stage FRM filter , comprising the following steps: {'br': None, 'i': H', 'z', 'G', 'z', 'H', 'z', 'G', 'z', 'H', 'z, 'sub': ma', 'mc, 'sup': (1)', '(1), '()=()()+(1−())(),'}, '(1) constructing an improved two-stage FRM filter having a transfer function H(z) as follows{'sub': a', 'ma', 'a', 'mc, 'sup': (2)', 'M', '(2)', 'P', '(2)', 'M', '(2)', 'Q, 'wherein G(z)=H(z)H(z)+(1−H(z))H(z) without any constraint among interpolation factors M, P, Q;'}{'sub': a', 'ma', 'mc', 'ma', 'mc, 'sup': (2)', 'M', '(1)', '(1)', '(2)', 'P', '(2)', 'Q, 'H(z) represents a prototype filter, while H(z) and H(z) represent first-stage masking filters, respectively, and H(z) and H(z) represent second-stage masking filters, respectively;'}{'sub': a', 'a', 'a, 'sup': (2)', '(2)', 'M', '(2)', 'M, '(2) searching within a search range for [M, P, Q], and for a certain set [M, P, Q], calculating passband and stopband edge parameters of the prototype filter H(z), passband and stopband edge parameters of the second-stage masking ...

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16-05-2019 дата публикации

VEHICLE SELF-LOCALIZATION USING PARTICLE FILTERS AND VISUAL ODOMETRY

Номер: US20190146500A1
Принадлежит:

Methods and systems herein can let an autonomous vehicle localize itself precisely and in near real-time in a digital map using visual place recognition. Commercial GPS solutions used in the production of autonomous vehicles generally have very low accuracy. For autonomous driving, the vehicle may need to be able to localize in the map very precisely, for example, within a few centimeters. The method and systems herein incorporate visual place recognition into the digital map and localization process. The roadways or routes within the map can be characterized as a set of nodes, which can be augmented with feature vectors that represent the visual scenes captured using camera sensors. These feature vectors can be constantly updated on the map server and then provided to the vehicles driving the roadways. This process can help create and maintain a diverse set of features for visual place recognition. 1. An autonomous vehicle control system , comprising:a sensor, the sensor sensing an environment surrounding a vehicle associated with the vehicle control system, wherein a feature vector describes at least a portion of the environment at a current location of the vehicle on a route;a processor communicatively coupled with the sensor, receiving information from the sensor regarding the feature vector;', 'retrieving feature vector particle information associated with two or more segments of a route of travel for the vehicle, wherein the feature vector particle information comprises a vocabulary of visual descriptors;', 'applying particle filtering to the received information from the sensor regarding the feature vector and the retrieved feature vector particle information associated with two or more segments of a route of travel for the vehicle; and', 'determining the current location of the vehicle on the route based on the applied particle filtering., 'a memory communicatively coupled with and readable by the processor and storing therein a set of instructions which, ...

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31-05-2018 дата публикации

ECHO CANCELLATION FOR TIME OF FLIGHT ANALOGUE TO DIGITAL CONVERTER

Номер: US20180151340A1
Принадлежит:

A method of mass spectrometry is disclosed comprising digitising a signal output from a detector to provide a first digitised signal. A finite impulse response (“FIR”) filter, a digital filter or an echo cancellation filter is applied to the first digitised signal in order to reduce the effect of baseline perturbations, echoes or ringing effects. Alternatively, an analogue signal output from a detector is passed to one or more first power splitters or dividers, wherein one or more first transmission lines are attached to one or more ports of one more said first power splitters or dividers in order to reduce the effect of baseline perturbations, echoes or ringing effects. 1. A method of mass spectrometry comprising:digitising a signal output from a detector to provide a first digitised signal; andapplying a finite impulse response (“FIR”) filter, a digital filter or an echo cancellation filter to said first digitised signal in order to reduce the effect of baseline perturbations, echoes or ringing effects.2. A method as claimed in claim 1 , wherein said finite impulse response filter claim 1 , said digital filter or said echo cancellation filter comprises or is programmed to have one or more filter coefficients and wherein the step of applying said finite impulse response filter or said echo cancellation filter to said first digitised signal further comprises setting or programming said one or more filter coefficients so as substantially to match said perturbations claim 1 , echoes or ringing effects.3. A method as claimed in claim 2 , wherein said one or more filter coefficients are set or programmed in dependence upon the amplitude and/or position of baseline perturbations claim 2 , echoes or ringing effects present in said first digitised signal.4. A method as claimed in claim 1 , wherein said baseline perturbations claim 1 , echoes or ringing effects are caused by impedance mismatches in a signal path.5. A method as claimed in claim 1 , wherein said baseline ...

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15-09-2022 дата публикации

SIGNAL PROCESSOR, FILTER, CONTROL CIRCUIT FOR POWER CONVERTER CIRCUIT, INTERCONNECTION INVERTER SYSTEM AND PWM CONVERTER SYSTEM

Номер: US20220294335A1
Принадлежит:

A signal processor is configured to perform a process equivalent to performing a series of fixed-to-rotating coordinate conversion, a predetermined process and then rotating-to-fixed coordinate conversion, while maintaining linearity and time-invariance. The signal processor performs a process given by the following matrix G: 130-. (canceled)32. A control circuit configured to control a plurality of switching units inside a power converter circuit by a PWM signal , comprising:{'claim-ref': {'@idref': 'CLM-00031', 'claim 31'}, 'a signal processor according to ; and'}a PWM signal generator configured to generate a PWM signal based on an output signal from the signal processor, the output signal being obtained by inputting to the signal processor a power conversion-related signal based on an output from or an input to the power converter circuit.33. The control circuit according to claim 32 , further comprising a two-phase conversion circuit configured to convert a signal based on an output from or an input to the power converter circuit into a first signal and a second signal claim 32 ,wherein the PWM signal generator generates a PWM signal based on both an output signal obtained from an input of the first signal to the signal processor and an output signal obtained from an input of the second signal to the signal processor.34. The control circuit according to claim 33 , wherein the power converter circuit relates to a three-phase alternate current claim 33 , andthe two-phase conversion circuit is configured to convert a signal based on a three-phase output from or three-phase input to the power converter circuit into the first signal and the second signal.35. The control circuit according to claim 33 , wherein the power converter circuit relates to a single-phase alternate current claim 33 , andthe two-phase conversion circuit is configured to generate a signal based on a single-phase output from or single-phase input to the power converter circuit as the first ...

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07-06-2018 дата публикации

Sparse cascaded-integrator-comb filters

Номер: US20180159510A1
Принадлежит: Analog Devices Inc

In a cascaded integrator comb (CIC) filter, a time-varying gain is added before the last integrating stage transforming its sub optimal boxcar impulse response into an FIR filter of arbitrary length. Make the coefficients sparse and taking them from a set of small integers leads to an efficient hardware implementation that does not compromise any of the essential CIC filter characteristics especially the overflow handling. The proposed sparse CIC structure can improve the worst case stop band attenuation by as much as 10 dB while occupying 77% of the chip area and consuming 30% less power compared to a standard a 5 th order CIC filter, and reducing the overall bit growth of the filter and the amount of high rate operations. Design examples are given illustrating the advantages and flexibility of the proposed structure.

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23-05-2019 дата публикации

Glitch immune cascaded integrator comb architecture for higher order signal interpolation

Номер: US20190158070A1
Автор: Ankur Bal, Mohit Singh
Принадлежит: STMicroelectronics International NV

A digital filtering method includes receiving a digital signal, and passing the digital signal through a Pth order comb cascade. The method includes beginning pre-computing of intermediate integrator states of a Pth order integrator cascade as a function of the digital signal, prior to receiving output from a last comb of the Pth order comb cascade. The outputs from each comb of the Pth order comb cascade are then applied to the pre-computed intermediate integrator states to thereby produce a filtered version of the digital signal. The Pth order comb cascade may operate at a sampling frequency, and the pre-computing of the intermediate integrator states is performed at the sampling frequency, while the application of the outputs from each comb of the Pth order comb cascade to the pre-computed intermediate integrator states is performed at a multiple of the sampling frequency.

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23-05-2019 дата публикации

Radio communication receiver and method for configuring a notch filter of the radio communication receiver

Номер: US20190158132A1
Принадлежит: Telefonaktiebolaget LM Ericsson AB

A radio communication receiver and a method performed by the radio communication receiver for configuring a Notch filter of the radio communication receiver. The method comprises retrieving stored and previously determined filter coefficients from a set of filter coefficients, where the retrieved filter coefficients constitute a fraction of the total number of filter coefficients; and setting the rest of the filter coefficients to one. The method further comprises normalising the retrieved filter coefficients; and transforming the filter coefficients such that the Notch position ends up at the one or more frequencies to be filtered out.

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14-05-2020 дата публикации

TECHNIQUES FOR INPUT FORMATTING AND COEFFICIENT SELECTION FOR SAMPLE RATE CONVERTER IN PARALLEL IMPLEMENTATION SCHEME

Номер: US20200153415A1

A sample rate converter (“SRC”) for implementing a rate conversion L/M is described wherein data is input to the SRC at an input rate (“F”) and output from the SRC at an output rate (“F”) equal to F*L/M. The SRC includes a low pass filter (“LPF”) including P multiply-add instances, wherein P is a parallelization factor of the SRC; an input formatter for arranging samples received at the SRC in accordance with the rate conversion L/M and providing P*Tinput samples to the filter at a given time, wherein Tis a number of taps per phase of the LPF; and a coefficient bank for storing a plurality of coefficients and for providing P*Tof the coefficients to the LPF at a given time. 120-. (canceled)21. A sample rate converter (“SRC”) for implementing a rate conversion L/M wherein data is input to the SRC at an input rate (“F”) and output from the SRC at an output rate (“F”) equal to F*L/M , the SRC comprising:a low pass filter (“LPF”) including P filters, wherein P is a parallelization factor of the SRC;an input formatter for arranging samples received at the SRC in accordance with the rate conversion L/M and providing a number of input samples to the filter at a given time; anda coefficient bank for storing a plurality of coefficients and for providing a number of the coefficients to the LPF at a given time.22. The SRC of claim 21 , wherein the number of input samples comprises P*Tinput samples claim 21 , wherein Tis a number of taps per phase of the LPF claim 21 , and wherein the input formatter receives the samples at Fand provides P*Tinput samples to the LPF at F.23. The SRC of claim 21 , wherein the number of the coefficients provided to the LPF at a given time comprises P*Tof the coefficients claim 21 , wherein Tis a number of taps per phase of the LPF claim 21 , and wherein the coefficient bank provides P*Tof the coefficients to the filter at F.24. The SRC of claim 21 , wherein the input formatter comprises a buffer for storing the received samples at Fand first ...

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04-09-2014 дата публикации

Systems and Methods for Signal Reduction Based Data Processor Marginalization

Номер: US20140250352A1
Принадлежит: LSI Corporation

Systems, methods, devices, circuits for data processing, and more particularly to data processing including operational marginalization capability, and/or operational improvement capability. 1. A data processing system , the data processing system comprising: filter a data set to yield a signal component;', 'multiply the signal component by a scalar to yield a product;', 'subtract the product from a data input to yield a signal modified output, wherein the data set is derived from the data input; and', 'select one of the data set and the signal modified output as a processing input; and, 'a signal modification circuit operable toa processing circuit operable to apply a data processing algorithm to the processing input to yield a data output.2. The data processing system of claim 1 , wherein the scalar is programmable.3. The data processing system of claim 2 , wherein the scalar is programmed with a value less than unity that is large enough to decrease a signal to noise ratio of the signal modified output when compared with a signal to noise ratio of the data set.4. The data processing system of claim 2 , wherein the scalar is programmed with a value less than unity that is small enough to increase a reliability of the signal modified output when compared with the data set.5. The data processing system of claim 1 , wherein the data processing system further comprises:an equalizer circuit operable to equalize a sample set to yield the data input; anda data detector circuit operable to apply a data detection algorithm to the data input to yield the data set.6. The data processing system of claim 5 , wherein the resolution of the data input is greater than the resolution of the processing input.7. The data processing system of claim 6 , wherein the resolution of the data input is thirteen bits claim 6 , and wherein the resolution of the processing input is six bits.8. The data processing system of claim 5 , wherein the resolution of the signal component is greater than ...

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11-09-2014 дата публикации

SYSTEMS AND METHODS FOR AN ADJUSTABLE FILTER ENGINE

Номер: US20140258354A1
Автор: Wu Chihsin
Принадлежит: APTINA IMAGING CORPORATION

Systems and methods are provided for an adjustable filter engine. In particular, an electronic system is provided that can include a focus module, memory, and control circuitry. In some embodiments, the focus module can include an adjustable filter engine and a motor. By using the adjustable filter engine to generate a filter with a large number of filter coefficients, the control circuitry can accommodate a variety of system characteristics. For example, by generating a set of cumulative coefficients and re-arranging the order of the cumulative coefficients, the control circuitry can reduce the bit-width requirements of the adjustable filter engine hardware. For instance, the control circuitry can reduce the number of multipliers required to perform a convolution between an updated filter and one or more input signals. In some embodiments, the updated filter can be generated to reduce oscillations of the motor movement due to a new position request.

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15-06-2017 дата публикации

SIGNAL TRANSFER FUNCTION EQUALIZATION IN MULTI-STAGE DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTERS

Номер: US20170170841A1
Принадлежит: ANALOG DEVICES, INC.

Typically, complex systems require a separate and expensive equalizer at the output of an analog-to-digital converter (ADC). Rather than providing a separate equalizer, the effective Signal Transfer Function (STF) of a Multi-stAge noise SHaping (MASH) ADC can be modified by leveraging available digital filtering hardware necessary for quantization noise cancellation. The modification can involves adding calculations in the software previously provided for computing digital quantization noise cancellation filter coefficients, where the calculations are added to take into account equalization as well. As a result, the signal transfer function can be modified to meet ADC or system-level signal-chain specifications without additional equalization hardware. The method is especially attractive for high-speed applications where magnitude and phase responses are more challenging to meet. 1. A method for digital quantization noise cancellation and equalization for a system having a multi-stage noise shaping analog-to-digital converter (MASH ADC) , the method comprising:determining a digital transfer function response of a particular stage in the MASH ADC;determining an equalization filter response; andcombining the digital transfer function response and the equalization filter response into a combined digital filter.2. The method of claim 1 , further comprising:filtering, by the combined digital filter, a digital output of a different stage in the MASH ADC.3. The method of claim 1 , wherein the digital transfer function of the particular stage is a digital signal transfer function estimating an actual signal transfer function of the particular stage.4. The method of claim 1 , wherein the digital transfer function of the particular stage is a digital noise transfer function estimating an actual noise transfer function of the particular stage.5. The method of claim 1 , further comprising:determining a desired signal transfer function response for the system having the MASH ADC ...

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01-07-2021 дата публикации

Method and apparatus for resampling audio signal

Номер: US20210201921A1
Автор: Kah Yong Lee
Принадлежит: Razer Asia Pacific Pte Ltd

A method, a computer-readable medium, and an apparatus for resampling audio signal are provided. The apparatus resamples the audio signal in order to preserve the audio playback quality when dealing with audio playback overrun and underrun problem. The apparatus may receive a data block of the audio signal including a first number of samples. For each sample of the first number of samples, the apparatus may slice a portion of the audio signal corresponding to the sample into a particular number of sub-samples. The apparatus may resample the data block of the audio signal into a second number of samples based on the first number of samples and the particular number of sub-samples associated with each sample of the first number of samples. The apparatus may play back the resampled data block of the audio signal via an electroacoustic device.

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21-06-2018 дата публикации

DETERMINING MOTION OF A MOVEABLE PLATFORM

Номер: US20180172722A1
Принадлежит:

In some examples, to perform motion detection of a moveable platform, variance values based on acceleration data from an accelerometer on the moveable platform are computed. Using the computed variance values, it is determined whether the moveable platform is in motion. 1. An apparatus comprising:a sensor device comprising an accelerometer, the sensor device for mounting on a moveable platform; and compute a variance based on acceleration data from the accelerometer; and', 'determine, using the computed variance, whether the moveable platform is in motion., 'at least one processor configured to2. The apparatus of claim 1 , wherein the variance based on the acceleration data comprises variance values based on the acceleration data claim 1 , and wherein the at least one processor is to determine whether the moveable platform is in motion by:responsive to determining that the variance values are above a first threshold, indicating that the moveable platform is in motion.3. The apparatus of claim 2 , wherein the at least one processor is configured to determine whether the moveable platform is in motion by:determining whether at least a portion of the variance values have fallen from a point at or above the first threshold to a point at or below a second threshold, andresponsive to determining that the at least a portion of the variance values have fallen from the point at or above the first threshold to the point at or below the second threshold, indicating that the moveable platform is not in motion.4. The apparatus of claim 3 , wherein the first threshold is greater than the second threshold.5. The apparatus of claim 3 , wherein the indicating that the moveable platform is in motion is responsive to the variance values within a specified time window being above the first threshold.6. The apparatus of claim 3 , wherein the at least a portion of the variance values is within a specified time window.7. The apparatus of claim 3 , wherein the at least one processor is ...

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01-07-2021 дата публикации

DIGITAL FILTER AND TEMPERATURE SENSOR INCLUDING THE SAME

Номер: US20210203308A1
Автор: KWON Chan Keun
Принадлежит: SK HYNIX INC.

Provided is a digital filter that is configured to generate a first integration signal by integrating data groups, which are generated by sampling sample data within a first time period that overlaps with another time period, configured to generate a second integration signal by integrating data groups, which are generated by sampling the sample data within a second time period that is included in the first time period, the first time period and the second time period overlapping with one another, and configured to output a difference between the first and second integration signals as digital data. The first integration signal is generated during a third time period that is included in the first time period. 1. A digital filter configured to generate a first integration signal by integrating data groups , which are generated by sampling sample data within a first time period that overlaps with another time period , configured to generate a second integration signal by integrating data groups , which are generated by sampling the sample data within a second time period that is included in the first time period , the first time period and the second time period overlapping with one another , and configured to output a difference between the first and second integration signals as digital data ,wherein the first integration signal is generated during a third time period that is included in the first time period.2. The digital filter of claim 1 , wherein the sample data is inputted in the form of a bit stream.3. The digital filter of claim 1 , wherein the second time period occurs before the third time period.4. The digital filter of claim 1 , wherein the data groups claim 1 , which are generated by sampling the sample data within the first time period such that time periods overlap with one another claim 1 , are generated by counting sample data with a first logic value among the sample data that is inputted during the first time period.5. The digital filter of claim ...

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