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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 1978. Отображено 100.
15-03-2012 дата публикации

Transistor substrate dynamic biasing circuit

Номер: US20120062313A1
Автор: Alexandre Valentian, Julien LE COZ, Philippe Flatresse, Sylvain Engels
Принадлежит: STMICROELECTRONICS SA

A dynamic biasing circuit of the substrate of a MOS power transistor may include a first switch configured to connect the substrate to a current source which forward biases the intrinsic source-substrate diode of the transistor, when the gate voltage of the transistor turns the transistor on. The current source may include a stack of diodes in the same conduction direction as the intrinsic diode between the substrate and a supply voltage.

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Номер записи: 1
12-04-2012 дата публикации

Wake-up control circuit for power-gated ic

Номер: US20120087199A1
Автор: Jose Tejada
Принадлежит: Analog Devices Inc

Embodiments of the present invention may provide a power-gating switch circuit. The power-gating switch circuit may comprise a first switch to connect a power supply to a virtual power supply and a second switch to connect the power supply to the virtual power supply in parallel to the first switch. The first switch may have a lower impedance than the second switch. When a wake up signal is received, the second switch may be turned on first and the first switch may be turned on after the virtual power supply reaches a predetermined voltage level.

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Номер записи: 2
28-06-2012 дата публикации

Logic circuit without enhancement mode transistors

Номер: US20120161812A1
Автор: Haoyang Yu
Принадлежит: Triquint Semiconductor Inc

Embodiments of circuits, methods and systems for powering various stages of a logic circuit are disclosed. Other embodiments may also be described and claimed.

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Номер записи: 3
08-11-2012 дата публикации

Logic circuit and semiconductor device

Номер: US20120280715A1
Автор: Yusuke Sekine
Принадлежит: Semiconductor Energy Laboratory Co Ltd

The logic circuit includes an input terminal, an output terminal, a main logic circuit portion that is electrically connected to the input terminal and the output terminal, and a switching element electrically connected to the input terminal and the main logic circuit portion. Further, a first terminal of the switching element is electrically connected to the input terminal, a second terminal of the switching element is electrically connected to a gate of at least one transistor included in the main logic circuit portion, and the switching element is a transistor in which a leakage current in an off state per micrometer of channel width is lower than or equal to 1×10 −17 A.

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Номер записи: 4
15-11-2012 дата публикации

Semiconductor integrated circuit

Номер: US20120286853A1
Автор: Hideyuki Kabuo, Ryouhei SEKI
Принадлежит: Panasonic Corp

A semiconductor integrated circuit includes a main circuit including a transistor, a pseudo-power supply line connected to a first power supply terminal of the main circuit, a first power supply line connected to the pseudo-power supply line via a first switch, a second power supply line connected to a second power supply terminal of the main circuit, a diode having a first end connected to the pseudo-power supply line and a second end connected to the first power supply line so that a potential difference between the pseudo-power supply line and the second power supply line is reduced in a conductive state, and a second switch having a first end connected to the pseudo-power supply line and a second end connected to the second power supply line.

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Номер записи: 5
22-11-2012 дата публикации

Ultra-low power multi-threshold asynchronous circuit design

Номер: US20120293198A1
Автор: Jia DI, Scott Christopher Smith
Принадлежит: University of Arkansas

A multi-threshold null convention logic circuit. The circuit includes a first circuit, a first high-threshold transistor coupled to V cc , and an inverter receiving power from the first high-threshold transistor, driven by the first circuit, and including an output.

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Номер записи: 6
03-01-2013 дата публикации

Semiconductor integrated circuit device

Номер: US20130002337A1
Автор: Masaaki Oyama
Принадлежит: Renesas Electronics Corp

Disclosed here is a semiconductor integrated circuit device configured to suppress a voltage drop over the route for transmitting voltages from a power cut-off switch to a power cut-off region without lowering the degree of freedom in routing signal wires in that region. The semiconductor integrated circuit device includes a semiconductor chip in which the power cut-off switch and power cut-off region are provided. A reduction in the number of wiring channels in the power-cut off region is avoided by locating the power cut-off switch outside the power cut-off region. Over the substrate, a substrate-side feed line is formed to transmit a power-supply voltage from the semiconductor chip to outside thereof via the power cut-off switch, before introducing the voltage again into the chip to feed the power cut-off region, thus suppressing the voltage drop between the power cut-off switch and the power cut-off region.

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Номер записи: 7
18-04-2013 дата публикации

TERMINATION DEVICE SYSTEM

Номер: US20130093459A1
Автор: LI Chunyi, Ma Qingjiang
Принадлежит: MONTAGE TECHNOLOGY (SHANGHAI) CO. LTD.

A termination device system is provided that includes a device required to be terminated with a resistor and a termination circuit. The termination circuit includes a termination resistor circuit and a judgment circuit connected to the termination resistor circuit. The termination resistor circuit includes at least one controlled termination unit. Each controlled termination unit includes a termination connecting end for connecting the device required to be terminated with a resistor, a controlled switch and a resistor, and provides, based on on/off of the controlled switch, a termination resistor for the device connected to the termination connecting end. The judgment circuit judges whether the device is required to be connected to the termination resistor based on a control instruction of a control device controlling the device connected to the termination connecting end, to output an on/off control signal to the controlled switch of the termination resistor circuit to control on/off. 1. A termination resistor circuit , comprising:at least one controlled termination unit, each of which comprising a termination connecting end for connecting a device required to be terminated with a resistor, a controlled switch and a resistor, for providing a termination resistor for the device connected to the termination connecting end based on on/off of the controlled switch.2. The termination resistor circuit as in claim 1 , wherein the at least one controlled termination unit comprises a voltage divider resistor circuit for performing voltage division on a power supply voltage claim 1 , wherein the voltage divider resistor circuit comprises resistors and controlled switches.3. The termination resistor circuit as in claim 1 , wherein the termination resistor circuit is a termination chip claim 1 , and each controlled termination unit is within the termination chip.4. The termination resistor circuit as in claim 1 , wherein the termination resistor circuit comprises a ...

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Номер записи: 8
09-05-2013 дата публикации

TERMINATION CIRCUIT AND DC BALANCE METHOD THEREOF

Номер: US20130113516A1
Автор: Chang Sheng-Ming, CHEN Shang-Ping, Hsieh Bo-Wei, Hung Chih-Chien, Liou Ming-Shi, Luo Yan-Bin
Принадлежит: MEDIATEK INC.

A termination circuit for a plurality of memories controlled by a controller is provided. The termination circuit includes a plurality of drivers, a plurality of resistors and a plurality of capacitors. Each of the drivers is coupled to the memories via a transmission line. Each of the resistors is coupled to the corresponding driver via the corresponding transmission line. Each of the capacitors is coupled between the corresponding resistor and a reference voltage. The controller is coupled to the memories via the drivers, and the controller provides a specific code to one of the drivers when a quantity of logic “0” and a quantity of logic “1” transmitted to the memories via the transmission line corresponding to the one of the drivers are unbalanced, so as to adjust a termination voltage of the capacitor corresponding to the one of the drivers. 1. A termination circuit for a plurality of memories controlled by a controller , comprising:a plurality of drivers, each coupled to the memories via a transmission line;a plurality of resistors, each coupled to the corresponding driver via the corresponding transmission line; anda plurality of capacitors, each coupled between the corresponding resistor and a reference voltage,wherein the controller is coupled to the memories via the drivers, and the controller provides a specific code to one of the drivers when a quantity of logic “0” and a quantity of logic “1” transmitted to the memories via the transmission line corresponding to the one of the drivers are unbalanced, so as to adjust a termination voltage of the capacitor corresponding to the one of the drivers.2. The termination circuit as claimed in claim 1 , wherein the controller further provides data to the memories via the drivers claim 1 , wherein the controller further records the data provided to the memories via each of the drivers and obtains a plurality of statistic values according to a quantity of logic “0” and a quantity of logic “1” of the recorded data.3 ...

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Номер записи: 9
23-05-2013 дата публикации

HIGH-FREQUENCY SEMICONDUCTOR SWITCHING CIRCUIT

Номер: US20130127495A1
Автор: MIYAZAKI Takahito
Принадлежит: Panasonic Corporation

A diode-switch logic circuit of the present invention is configured such that: at least one of paths between a common input-output terminal and respective individual input-output terminals is caused to become a conducting state; control voltages of control terminals are respectively applied to gates of path switching FET stages; logic synthesis voltages of the control voltages of the control terminals are respectively applied to gates of shunt FET stages; and each of the logic synthesis voltages is generated by a logical product of a logical negation of the control voltage applied to one shunt FET stage and a logical sum of the control voltages respectively applied to the remaining shunt FET stages. 1. A high-frequency semiconductor switching circuit comprising:a semiconductor substrate;one common input-output terminal, three or more individual input-output terminals, and three or more control terminals corresponding to the three or more individual input-output terminals, these terminals being formed on the semiconductor substrate;three or more path switching FET stages formed on the semiconductor substrate and each provided between the common input-output terminal and a corresponding one of the three or more individual input-output terminals;one or more shunt FET stages formed on the semiconductor substrate and each provided between ground and at least one of the three or more individual input-output terminals; anda diode-switch logic circuit including diodes and switches formed on the semiconductor substrate such that a group of a part of the diodes and a part of the switches corresponds to each of the one or more shunt FET stages, the diode-switch logic circuit being configured to control the three or more path switching FET stages and the one or more shunt FET stages, wherein:the diode-switch logic circuit is configured to respectively apply control voltages, respectively input to the three or more control terminals, to gates of the three or more path switching ...

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Номер записи: 10
30-05-2013 дата публикации

HIGH-SPEED DRIVER CIRCUIT

Номер: US20130135006A1
Автор: Menolfi Christian I., Toifl Thomas H.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

An inverter-type high speed driver circuit having a first inverter branch and a second inverter branch wherein each of the inverter branches comprising a parallel circuit of a serial connection of a first impedance tuning unit and a respective first clocking transistor and a serial connection of a second impedance tuning unit and a respective second clocking transistor. The impedance tuning units are configured to adapt the conductivity of the respective inverter branch to set the output impedance of the driver circuit and each of the impedance tuning units is controlled in accordance with a data stream. 1. An inverter-type high speed driver circuit comprising:a first inverter branch and a second inverter branch, wherein each of the inverter branches comprising a parallel circuit of a serial connection of a first impedance tuning unit and a respective first clocking transistor and a serial connection of a second impedance tuning unit and a respective second clocking transistor, wherein the impedance tuning units are configured to adapt conductivity of a respective inverter branch to set an output impedance of the driver circuit; wherein each of the impedance tuning units is controlled in accordance with a data stream.2. The driver circuit according to claim 1 , wherein each impedance tuning unit comprises a plurality of parallelized impedance tuning transistors separately controlled by respective weighted data control signals claim 1 , and wherein an impedance weighting unit is provided to generate weighted data control signals as a result of an incoming data signal and a given impedance setting signal.3. The driver circuit according to claim 1 , wherein each of the inverter branches comprises a resistor in series to the parallel circuit.4. The driver circuit according to claim 1 , wherein the inverter branches are interconnected at a node wherein a resistor is serially connected between an output of the driver circuit and the node.5. The driver circuit according to ...

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Номер записи: 11
04-07-2013 дата публикации

ADAPTIVE BUFFER

Номер: US20130169311A1
Автор: MONGA Sushrant
Принадлежит: STMICROELECTRONICS INTERNATIONAL N.V.

An embodiment of a buffer for a transmission line, a circuit including such a buffer, a high-speed data link, and a low-voltage differential signaling (LVDS) system. 115.-. (canceled)16. A circuit , comprising:a node configured to be coupled to load that includes a signal-propagation medium, the load having an impedance;a driver configured to drive a calibration signal onto the node; anda calibrator coupled to the node and configured to generate, in response to the calibration signal, an impedance signal that is related to the impedance of the load.17. The circuit of wherein the node includes an output node.18. The circuit of wherein the node includes an input node.19. The circuit of wherein the driver has an output impedance and is configured to adjust the output impedance in response to the impedance signal.20. The circuit of claim 16 , further comprising a receiving stage coupled to the node claim 16 , having an input impedance claim 16 , and configured to adjust the input impedance in response to the impedance signal.21. The circuit of claim 16 , further comprising a transmitting stage coupled to the node claim 16 , having an output impedance claim 16 , and configured to adjust the output impedance in response to the impedance signal.22. The circuit of wherein the driver includes driver elements that selectively activate in response to the impedance signal to adjust the output impedance of the driver claim 16 ,23. The circuit of wherein the driver has an output impedance and is configured to set the output impedance approximately equal to the impedance of the load in response to the impedance signal.24. The circuit of claim 16 , further comprising a transmitting stage coupled to the node claim 16 , having an output impedance claim 16 , and configured to set the output impedance approximately equal to the impedance of the load in response to the impedance signal.25. The circuit of wherein:the driver includes a calibration portion that is configured to drive the ...

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Номер записи: 12
12-09-2013 дата публикации

IMPEDANCE CALIBRATION DEVICE AND METHOD

Номер: US20130234755A1
Автор: CHAN CHENG-PANG, Chang Che-Wei, Lin Jian-Ru
Принадлежит: Realtek Semiconductor Corp.

An impedance calibration device includes: a variable impedance, an operational unit, an analog-digital converter, and a controller. The operational unit receives a first analog signal and a second analog signal, and performs a difference operation to generate an output voltage. The analog-digital converter generates an adjustment code according to the output voltage. The controller is coupled to the analog-digital converter and the variable impedance, and adjusts a resistance value of the variable impedance according to the adjustment code. 1. An impedance calibration device , comprising:a variable impedance;an operational unit, used for receiving a first analog signal and a second analog signal and performing a difference operation to generate an output voltage, wherein the first analog signal has variation amount information of the variable impedance, and the second analog signal is a reference signal;an analog-digital converter, coupled to the operational unit, and used for receiving the output voltage to generate an adjustment code; anda controller, coupled to the analog-digital converter and the variable impedance, and used for adjusting a resistance value of the variable impedance according to the adjustment code.2. The impedance calibration device according to claim 1 , further comprising:a gain controller, coupled between the operational unit and the analog-digital converter, and used for adjusting a voltage of the output voltage.3. The impedance calibration device according to claim 2 , wherein the output voltage is mapped to a full dynamic range of the analog-digital converter.4. The impedance calibration device according to claim 1 , wherein the controller adjusts the resistance value of the variable impedance according to a maximum variation amount of the variable impedance and a full dynamic range of the analog-digital converter.5. The impedance calibration device according to claim 1 , wherein the first analog signal is a first current generated ...

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Номер записи: 13
31-10-2013 дата публикации

PROGRAMMABLE LSI

Номер: US20130285697A1
Автор: KUROKAWA Yoshiyuki
Принадлежит: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

An object is to achieve both suppression of operation delay and reduction in power consumption of a programmable LSI. A compiler generates, from source code, configuration data needed in a programmable LSI and a time schedule that shows a timing of using the data in the programmable LSI (a timing at which the data is held in a configuration memory) and a timing of storing the data in the programmable LSI before the data is used. Supply of new configuration data to the programmable LSI from the outside (storage of new configuration data) and data rewrite in the configuration memory in the programmable LSI (circuit reconfiguration) are performed independently and concurrently on the basis of the time schedule. 1. A semiconductor device comprising:a programmable LSI comprising a logic circuit unit; anda compiler configured to generate a time schedule and plural pieces of configuration data,wherein the compiler is configured, independently and concurrently on the basis of the time schedule, to store the plural pieces of configuration data in the programmable LSI and reconfigure a configuration of the logic circuit unit in accordance with each of the plural pieces of configuration data.2. The semiconductor device according to claim 1 ,wherein the programmable LSI further comprises a bank group, andwherein the bank group is configured to store the plural pieces of configuration data.3. The semiconductor device according to claim 2 ,wherein the bank group comprises a plurality of memory cells, andwherein each of the memory cells comprises an input bit line, an output bit line, an input word line, an output word line, a reference potential line, a first transistor, a second transistor, and a third transistor.4. The semiconductor device according to claim 3 ,wherein the first transistor comprises a gate electrically connected to the input word line, and a source and a drain one of which is electrically connected to the input bit line,wherein the second transistor comprises a ...

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Номер записи: 14
28-11-2013 дата публикации

METHOD FOR DRIVING SEMICONDUCTOR DEVICE

Номер: US20130314125A1
Автор: Takemura Yasuhiko
Принадлежит: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

A method for driving a semiconductor device capable of reducing an area of a multiplexer and reducing its power consumption is provided. In a method for operating a semiconductor device including a memory and a multiplexer, a first transistor is connected to a first capacitor, and a second transistor is connected to a second capacitor. In the multiplexer, in a third transistor, a source is connected to a first input terminal and a drain is connected to an output terminal and, in a fourth transistor, a source is connected to a second input terminal and a drain is connected to the output terminal. Further, a step of holding a first potential in a node to which the first transistor, the first capacitor, and a gate of the third transistor are connected and holding a second potential higher than the first potential in the node is included. 1. A method for driving a semiconductor device ,the semiconductor device comprising:a memory comprising a first transistor, a first capacitor, a second transistor, and a second capacitor;a multiplexer comprising a third transistor and a fourth transistor;a first input terminal configured to input a first signal, and a second input terminal configured to input a second signal; andan output terminal configured to output the first signal or the second signal,wherein one of a source and a drain of the first transistor is electrically connected to the first capacitor,wherein one of a source and a drain of the second transistor is electrically connected to the second capacitor,wherein a source of the third transistor is electrically connected to the first input terminal, and a drain of the third transistor is electrically connected to the output terminal, andwherein a source the fourth transistor is electrically connected to the second input terminal, and a drain of the fourth transistor is electrically connected to the output terminal,the method comprising the steps of:holding a first potential in one of a first node and a second node; ...

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Номер записи: 15
02-01-2014 дата публикации

ON-DIE TERMINATION CIRCUIT

Номер: US20140002129A1
Автор: JUNG Jong Ho
Принадлежит: SK HYNIX INC.

An on-die termination circuit includes: a clock signal generation block configured to output a clock signal in response to a clock enable signal, a termination block configured to perform a termination operation on an input/output pad in response to the clock signal, a first termination control signal, and a second termination control signal, a first termination control block configured to generate the first termination control signal in response to the clock signal and a latency control signal, a second termination control block configured to control a latency of a second command and to generate the second termination control signal in response to the clock signal and the latency control signal, and a clock enable signal generation block configured to generate the clock enable signal in response to the first command, the first termination control signal, and the second is command. 2. The on-die termination circuit according to claim 1 , wherein the first command corresponds to an on-die termination command.3. The on-die termination circuit according to claim 1 , wherein the second command corresponds to a write command.4. The on-die termination circuit according to claim 1 , wherein the clock signal generation block corresponds to a delay-locked loop.5. The on-die termination circuit according to claim 1 , wherein the first termination control block comprises:a timing control block configured to control the timing of an external command by a set time and to generate the first command;a variable delay unit configured to delay the first command and to generate a preliminary control signal; anda first latency shift block configured to delay the preliminary control signal by a predetermined latency in response to the latency is control signal on the basis of the delay-locked clock signal, and to generate the first termination control signal.6. The on-die termination circuit according to claim 5 , wherein the first latency shift block comprises:a shift control unit ...

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Номер записи: 16
02-01-2014 дата публикации

LOW-POWER, HIGH-VOLTAGE INTEGRATED CIRCUITS

Номер: US20140002181A1
Автор: Motz Mario
Принадлежит:

Embodiments relate to integrated circuits with protection. In one embodiment the protection is coupled between a first circuit provided to control a low power mode of the integrated circuit and a supply voltage. The protection comprises in an embodiment a transistor being one of a depletion transistor or a junction field effect transistor. 1. An integrated circuit (IC) comprising:a first circuit to control a low power mode of the integrated circuit; anda protection device coupled between the first circuit and a supply voltage and comprising a transistor being one of a depletion transistor or a junction field effect transistor.2. The IC of claim 1 , wherein the protection device further comprises a Schottky diode coupled in series with the transistor.3. The IC of claim 2 , further comprising a resistor coupled in series with the Schottky diode and the transistor.4. The IC of claim 3 , where the resistor is coupled between the transistor and the first circuit.5. The IC of claim 1 , wherein the second circuit comprises a load circuit and a Schottky diode claim 1 , wherein the Schottky diode couples the load circuit and the supply voltage.6. The IC of claim 7 , wherein the voltage provided to the oscillator circuit is about 1.5 V.7. The IC of claim 1 , wherein the current consumption of the first circuit is in a range of about 30 nano-Amps (nA) to about 3 micro-amps (μA).8. The IC of claim 1 , wherein the second circuit comprises a load circuit claim 1 , wherein a depletion transistor circuit or a JFET circuit is coupled between the supply voltage and the load circuit.914. The IC of claim claim 1 , further comprising a Schottky diode coupled between the supply voltage and the depletion transistor circuit.10. The IC of claim 1 , wherein the first circuit is configured to control a wake-up and sleep mode of a second circuit of the integrated circuit.11. The IC of claim 1 , wherein the first circuit is an oscillator circuit.12. The IC of claim 12 , wherein the oscillator ...

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Номер записи: 17
06-02-2014 дата публикации

SYSTEM FOR TRANSMISSION LINE TERMINATION BY SIGNAL CANCELLATION

Номер: US20140035615A1
Автор: BINDER Yehuda
Принадлежит: MOSAID TECHNOLOGIES INCORPORATED

A communication system having first and second states for use with a shared transmission line composed of at least two conductors and composed of first and second transmission line segments connected to each other at a single connection point. In the first state, a termination is coupled to the single connection point and is operative to at least attenuate a signal propagated between the first and second segments. In the second state, a driver is coupled to the connection point and is operative to conduct a signal over the first and second segments. 1a connector for connecting to the outlet for coupling to the digital data signal carried over the wire pair; anda termination circuit selectively couplable to said connector and constructed for terminating the digital data signal propagated over the wire pair when said device is connected to said connector,wherein said device is switchable between a first state in which said termination circuit is coupled to said connector and a second state in which said termination circuit is not coupled to said connector.. A device for use with a wire pair in walls of a building and connected to an outlet, the wire pair being connected in a bus topology for carrying a digital data signal, said device comprising: This is a continuation of U.S. application Ser. No. 13/245,433, filed on Nov. 14, 2011, which is a continuation of U.S. application Ser. No. 12/724,952, filed on Mar. 16, 2010, which is a continuation of U.S. application Ser. No. 12/252,025, filed Oct. allowed, which is a continuation of U.S. application Ser. No. 12/026,321, filed Feb. 5, 2008, now U.S. Pat. No. 7,453,284, issued on Nov. 18, 2008, which is a continuation of U.S. application Ser. No. 11/346,396, filed on Feb. 3, 2006, now U.S. Pat. No. 7,336,096, issued on Feb. 26, 2008, which is a division of U.S. application Ser. No. 11/100,453, filed on Apr. 7, 2005, now U.S. Pat. No. 7,068,066, issued on Jun. 27, 2006, which is a continuation of U.S. application Ser. No. ...

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Номер записи: 18
20-02-2014 дата публикации

METHODS AND APPARATUSES INCLUDING A VARIABLE TERMINATION IMPEDANCE RATIO

Номер: US20140050030A1
Автор: Grunzke Terry M.
Принадлежит: MICRON TECHNOLOGY, INC.

Methods of changing a centerline voltage of a data signal are described, along with apparatuses to change the centerline voltage. In one such method, portions of a termination circuit coupled to an output pin are selectively activated to change an impedance of the termination circuit to change the centerline voltage of the data signal driven to the output pin. One such apparatus includes pull-up impedances and pull-down impedances that can be activated to change the centerline voltage of the data signal. Additional embodiments are also described. 1. A memory device comprising:a memory array for storing data;a termination register configured to store termination values;a termination control circuit coupled to the termination register; andan I/O circuit, coupled to the memory array and the termination control circuit, for transmitting data from and receiving data to the memory array, the I/O circuit comprising a plurality of driver and receiver circuits, each of the plurality of driver and receiver circuits having an adjustable pull-up impedance and an adjustable pull-down impedance that are adjusted by the termination control circuit in response to the stored termination values.2. The memory device of and further comprising a control circuit to control operation of the memory device claim 1 , the control circuit coupled to the termination register.3. The memory device of wherein the control circuit is configured to write the termination values to the termination register.4. The memory device of wherein each adjustable pull-up impedance and each adjustable pull-down impedance comprises a plurality of resistance circuits coupled together in parallel claim 1 , each resistance circuit having a fuse in series with a resistance.5. The memory device of wherein the plurality of resistance circuits for the adjustable pull-up impedance are coupled in parallel between an output pin of the memory device and a supply voltage.6. The memory device of wherein the plurality of ...

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Номер записи: 19
01-01-2015 дата публикации

CENTRAL INPUT BUS TERMINATION TOPOLOGY

Номер: US20150002189A1
Автор: BAYER Erich, Dietl Markus, SKERLJ Maurizio, TAMBOURIS Sotirios
Принадлежит:

An input bus termination (IBT) system for an integrated circuit that includes a termination switch coupled to a plurality of input lines of an integrated circuit, each of the plurality of input lines coupled to a common node of the termination switch through a resistor, wherein the termination switch is to generate a termination voltage at the common node based on the composite potential generated by the plurality of input lines at the common node when an input signal is received across the plurality of input lines. 1. An input bus termination (IBT) system for an integrated circuit , comprising:a termination switch coupled to a plurality of input lines of an integrated circuit, each of the plurality of input lines coupled to a common node of the termination switch through a resistor, wherein the termination switch is to generate a termination voltage at the common node based on the composite potential generated by the plurality of input lines at the common node when an input signal is received across the plurality of input lines.2. The IBT system of claim 1 , wherein the termination switch comprises:a first circuit to increase the voltage at the common node when the composite potential falls below a first threshold voltage.3. The IBT system of claim 2 , wherein the termination switch further comprises:a second circuit to decrease the voltage at the common node when the composite potential rises above a second threshold voltage.4. The IBT system of claim 3 , wherein the first and second circuits are coupled together at the common node.5. The IBT system of claim 4 , further comprising a capacitor that couples the common node to a ground or a common power supply line.6. The IBT of claim 4 , wherein the termination voltage is between the first and second threshold voltages.7. The IBT system of claim 1 , wherein the resistors coupling each of the plurality of input lines to the common node are of equal resistance values.8. The IBT of claim 1 , wherein the termination ...

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Номер записи: 20
05-01-2017 дата публикации

ON-DIE TERMINATION ENABLE SIGNAL GENERATOR, SEMICONDUCTOR APPARATUS, AND SEMICONDUCTOR SYSTEM

Номер: US20170005657A1
Автор: KIM Kwang Hyun
Принадлежит:

A semiconductor apparatus may include an on-die termination (ODT) enable signal generator configured to enable an ODT enable signal in response to a data strobe signal, or enable the ODT enable signal in response to a command latch enable signal and an address latch enable signal. The semiconductor apparatus may include an ODT circuit configured to perform an ODT operation in response to the ODT enable signal. 1. A semiconductor apparatus comprising:an on-die termination (ODT) enable signal generator configured to enable an ODT enable signal in response to a data strobe signal, or enable the ODT enable signal in response to a command latch enable signal and an address latch enable signal; andan ODT circuit configured to perform an ODT operation in response to the ODT enable signal,wherein the ODT enable signal generator enables the ODT enable signal in response to the data strobe signal in a non-test and enables the ODT enable signal in response to the command latch enable signal and the address latch enable signal in a test.2. (canceled)3. The semiconductor apparatus of claim 1 , wherein the ODT enable signal generator disables the ODT enable signal in response to a chip enable signal claim 1 , the command latch enable signal claim 1 , and the address latch enable signal.4. The semiconductor apparatus of claim 3 , wherein the ODT enable signal generator includes:a set signal generator configured to generate a set signal in response to the data strobe signal, the command latch enable signal, the address latch enable signal, and a test signal;a reset signal generator configured to generate a reset signal in response to the chip enable signal, the command latch enable signal, and the address latch enable signal; andan enable signal generator configured to enable the ODT enable signal in response to the set signal or disable the ODT enable signal in response to the reset signal.5. The semiconductor apparatus of claim 4 , wherein the set signal generator outputs the ...

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Номер записи: 21
07-01-2016 дата публикации

THRESHOLD LOGIC GATES WITH RESISTIVE NETWORKS

Номер: US20160006437A1
Автор: Kulkarni Niranjan, Vrudhula Sarma, Yang Jinghua, Yu Shimeng
Принадлежит: Arizona Board of Regents on behalf of Arizona State University

This disclosure relates generally to threshold logic elements for integrated circuits (ICs). In one embodiment, a threshold logic element has a first input gate network, a second input gate network, a differential sense amplifier, and a resistive network. The first input gate network is configured to receive a first set of logical signals, while the second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential output in accordance with a threshold logic function. The resistive network is coupled between the differential sense amplifier and the first input gate network and between the differential sense amplifier and the second input gate network. The resistive network makes the threshold logic element less susceptible to process variations. 1. A threshold logic element comprising:a first input gate network configured to receive a first set of logical signals;a second input gate network configured to receive a second set of logical signals;a differential sense amplifier operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential output in accordance with a threshold logic function; anda resistive network coupled between the differential sense amplifier and the first input gate network and between the differential sense amplifier and the second input gate network.2. The threshold logic element of wherein the resistive network comprises a resistive element.3. The threshold logic element of wherein the resistive element comprises a resistive read only memory (RROM) device.4. The threshold logic element of wherein the first input gate network comprises a transmission gate configured to receive a first one of the first set of logical ...

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Номер записи: 22
04-01-2018 дата публикации

HIGH SPEED VOLTAGE LEVEL SHIFTER

Номер: US20180006650A1
Автор: Chen Rui, Lu De, Narayanan Venkat, Sinharoy Samrat, Vattikonda Rakesh, Vilangudipitchai Ramaprasath
Принадлежит:

In one embodiment, a voltage level shifter includes a first NOR gate having a first input configured to receive a first input signal in a first power domain, a second input configured to receive an enable signal in a second power domain, a third input, and an output. The voltage level shifter also includes a second NOR gate having a first input configured to receive a second input signal in the first power domain, a second input configured to receive the enable signal in the second power domain, a third input coupled to the output of the first NOR gate, and an output coupled to the third input of the first NOR gate. The first and second NOR gates are powered by a supply voltage of the second power domain. 1. A voltage level shifter , comprising:a first NOR gate having a first input configured to receive a first input signal in a first power domain, a second input configured to receive an enable signal in a second power domain, a third input, and an output; anda second NOR gate having a first input configured to receive a second input signal in the first power domain, a second input configured to receive the enable signal in the second power domain, a third input coupled to the output of the first NOR gate, and an output coupled to the third input of the first NOR gate;wherein the first and second NOR gates are powered by a supply voltage of the second power domain.2. The voltage level shifter of claim 1 , wherein each of the first and second input signals has a voltage range approximately equal to a first voltage range claim 1 , the enable signal has a voltage range approximately equal to a second voltage range claim 1 , and the second voltage range is greater than the first voltage range.3. The voltage level shifter of claim 2 , wherein the output of each of the first and second NOR gates has a voltage range approximately equal to the second voltage range.4. The voltage level shifter of claim 1 , wherein the first and second input signals are complementary.5. The ...

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Номер записи: 23
04-01-2018 дата публикации

HIGH SPEED VOLTAGE LEVEL SHIFTER

Номер: US20180006651A1
Автор: Chen Rui, Lu De, Narayanan Venkat, Sinharoy Samrat, Vattikonda Rakesh, Vilangudipitchai Ramaprasath
Принадлежит:

In one embodiment, a voltage level shifter includes a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal in a first power domain, and a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node. The voltage level shifter also includes an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor, and a first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground. 1. A voltage level shifter , comprising:a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal in a first power domain;a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node;an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor; anda first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground.2. The voltage level shifter of claim 1 , wherein the inverter is powered by the supply voltage of the second power domain.3. The voltage level shifter of claim 1 , wherein the input signal has a voltage range that is at least 20 percent lower than the supply voltage of the second power domain.4. The voltage level shifter of claim 1 , further comprising an enable circuit configured to receive an enable signal in the second power domain claim 1 , to enable the voltage level shifter when the enable signal has a first logic state claim 1 , and to disable the voltage level shifter when the enable signal has a second ...

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Номер записи: 24
08-01-2015 дата публикации

DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS

Номер: US20150008956A1
Автор: MILLAR Bruce
Принадлежит:

A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination. 1. (canceled)2. A method for controlling the impedance of a buffer having a plurality of pull-up transistors and a plurality of pull-down transistors , the method comprising:receiving a data output signal;receiving an output enable signal;receiving a termination enable signal;receiving a first plurality of impedance control bits, a second plurality of impedance control bits, a third plurality of impedance control bits, and a fourth plurality of impedance control bits;enabling, when the output enable signal is in a first state and the data output signal is in a first state, one or more of the plurality of pull-up transistors determined by the first plurality of impedance control bits;enabling, when the output enable signal is in a first state and the data output signal is in a second state, one or more of the plurality of pull-down transistors determined by the second plurality of impedance control bits; andenabling, when the termination enable signal is in a first state, one or more of the plurality of pull-up transistors determined by the third plurality of impedance control bits and one or more of the plurality of pull-down transistors determined by the fourth plurality of impedance control bits;wherein the first and second pluralities of impedance control bits ...

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Номер записи: 25
12-01-2017 дата публикации

Crowbar Current Elimination

Номер: US20170012624A1
Автор: Miller Edward
Принадлежит:

In one embodiment, an inverter generates an inverted clock signal using (i) first P-type and N-type transistors connected in cascode between supply and ground nodes and (ii) control circuitry receiving different phase-offset input clock signals that ensure that the cascode-connected transistors are never even partially on at the same time, thereby preventing crowbar current from occurring through the cascode-connected devices. In one implementation, the control circuitry has two P-type transistors and two N-type transistors configured to receive three phase-offset input clock signals to prevent crowbar current in the inverter. The control circuitry has pass transistors that selectively allow one of the phase-offset input signals to be applied to the gate of one of the cascode-connected transistors with minimal delay, thereby enabling the inverter to operate properly over a relatively wide range of input clock frequencies. 1. Circuitry comprising:{'b': 3', '3, 'a first P-type transistor (e.g., P) and a first N-type transistor (e.g., N), wherein drains of the first P-type transistor and the first N-type transistor are electrically connected, a source node of the first P-type transistor is coupled to a supply node, and a source of the first N-type transistor is coupled to a sink node; and'}{'b': 1', '2', '3', '3, 'control circuitry connected to generate gate voltages for the first P-type and N-type transistors based on a plurality of phase-offset input signals (e.g., PH, PH, PH) that ensure that (i) the first P-type transistor is turned off before the first N-type transistor is turned on and (ii) the first N-type transistor is turned off before the first P-type transistor is turned on, wherein the control circuitry comprises pass-transistor circuitry that selectively allows one (e.g., PH) of the phase-offset input signals to be applied either to a gate of the first P-type transistor or a gate of the first N-type transistor.'}2. The circuitry of claim 1 , wherein:{'b': ...

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Номер записи: 26
21-01-2016 дата публикации

HIGH SPEED COMPLEMENTARY NMOS LUT LOGIC

Номер: US20160020767A1
Автор: Gunaratna Senani, Sharpe-Geisler Brad, Yew Ting
Принадлежит:

A programmable logic is provided that uses only NMOS pass transistors to pass a true output signal to an internal true node and to pass a complement output signal to an internal complement node. The internal true and complement nodes are cross-coupled through PMOS transistors so that the discharge of one of the internal true and complement nodes switches on a corresponding one of the cross-coupled PMOS transistors to charge a remaining one of the internal true and complement nodes.

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Номер записи: 27
17-04-2014 дата публикации

PROGRAMMABLE LOGIC DEVICE

Номер: US20140103960A1
Автор: KUROKAWA Yoshiyuki, Yamazaki Shunpei
Принадлежит: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

To obtain a PLD that achieves high-speed configuration capable of dynamic configuration, consumes less power, and has a short startup time and a PLD that has a smaller number of transistors or a smaller circuit area than a PLD using an SRAM as a configuration memory, a plurality of logic elements arranged in an array and a switch for selecting electrical connection between the logic elements are provided. The switch includes a first transistor including a multilayer film including an oxide layer and an oxide semiconductor layer, a node that becomes floating when the first transistor is turned off, and a second transistor in which electrical continuity between a source and a drain is determined based on configuration data held at the node. 1. A semiconductor device comprising:a first programmable logic element;a second programmable logic element; anda switch comprising a first transistor and a second transistor,wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor,wherein a first terminal of the second transistor is electrically connected to the first programmable logic element,wherein a second terminal of the second transistor is electrically connected to the second programmable logic element,wherein the first transistor comprises a gate electrode and a multilayer film with a gate insulating film therebetween, andwherein the multilayer film comprises an oxide semiconductor layer comprising a channel formation region.2. The semiconductor device according to claim 1 ,wherein the multilayer film comprises an oxide layer and the oxide semiconductor layer over the oxide layer.3. The semiconductor device according to claim 1 ,wherein the multilayer film comprises the oxide semiconductor layer and an oxide layer over the oxide semiconductor layer.4. The semiconductor device according to claim 1 ,wherein the multilayer film comprises a first oxide layer, the oxide semiconductor layer over the first oxide layer, and a ...

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Номер записи: 28
18-01-2018 дата публикации

IMPEDANCE CALIBRATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME

Номер: US20180019751A1
Автор: JEONG Yo Han
Принадлежит:

An impedance calibration circuit includes a first detection unit configured to generate a first pull-up impedance detection signal according to a resistance value of an internal reference resistor, a second detection unit configured to generate a second pull-up impedance detection signal according to a resistance value of an external reference resistor coupled to an external reference resistor pad, a switching unit configured to select the first pull-up impedance detection signal or the second pull-up impedance detection signal according to the internal impedance calibration enable signal and output the selected pull-up impedance detection signal, and an impedance calibration signal generation unit configured to generate a plurality of impedance calibration signals according to an output of the switching unit. 1. An impedance calibration circuit comprising:a first detection unit configured to generate a first pull-up impedance detection signal according to a resistance value of an internal reference resistor;a second detection unit configured to generate a second pull-up impedance detection signal according to a resistance value of an external reference resistor coupled to an external reference resistor pad;a switching unit configured to select the first pull-up impedance detection signal or the second pull-up impedance detection signal according to an internal impedance calibration enable signal and output the selected pull-up impedance detection signal; andan impedance calibration signal generation unit configured to generate a plurality of impedance calibration signals according to an output of the switching unit.2. The impedance calibration circuit of claim 1 , wherein the first detection unit includes:a replica pull-up driver coupled between a power terminal and the internal reference resistor; anda comparator configured to generate the first pull-up impedance detection signal by comparing a level of a node to which the replica pull-up driver and the internal ...

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Номер записи: 29
16-01-2020 дата публикации

POWER DISTRIBUTION UNIT AND SETTING METHOD THEREOF

Номер: US20200019220A1
Автор: Huang Min-Huang
Принадлежит: Digipower Manufacturing Inc.

A power distribution unit (PDU) and a setting method thereof are provided. The PDU includes a signal input port, a power output port and an embedded system. The embedded system is coupled to the signal input port and the power output port and configured to provide a setting interface. The setting interface is configured to set a current provided by the power output port and a corresponding logic value combination of a plurality of signals received by the signal input port, so as to generate an output rule of the PDU. In response to a plurality of input signals received by the signal input port, the embedded system controls an output of the power output port according to a logic value combination of the received input signal and the set output rule. 1. A power distribution unit , comprising:a signal input port, configured to receive a plurality of signals;a power output port, configured to provide a current; and 'provide a setting interface, wherein the setting interface is configured to set the current provided by the power output port and a corresponding logic value combination of the plurality of signals, so as to generate an output rule of the power distribution unit,', 'an embedded system, coupled to the signal input port and the power output port and configured towherein in response to a plurality of input signals received by the signal input port, the embedded system controls an output of the power output port according to a logic value combination of the received input signals and the set output rule.2. The power distribution unit according to claim 1 , further comprising:a communication interface, coupled to the embedded system and configured to connect to an Ethernet, wherein the embedded system provides the setting interface through the Ethernet,wherein the embedded system receives an external set signal through the Ethernet, so as to generate the output rule according to the external set signal.3. The power distribution unit according to claim 2 , wherein ...

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Номер записи: 30
22-01-2015 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20150022235A1
Автор: KISHIMOTO Satoru, UCHIKI Hideki
Принадлежит:

The disclosed invention provides a semiconductor device capable of suitably controlling the level of an enable signal to resolve NBTI in a PMOS transistor. An input node receives an input signal alternating between high and low levels during normal operation and fixed to a high level during standby. A detection unit receives a signal through the input node and outputs an enable signal. The detection unit sets the enable signal to a low level upon detecting that the input node remains at a high level for a predetermined period. A signal transmission unit includes a P-channel MOS transistor and transmits a signal input to the input node according to control by the enable signal. 16-. (canceled)8. The semiconductor device according to claim 7 ,wherein the charging unit comprises:a constant current source that supplies current to a first node;a MOS transistor that is installed between the first node and ground and on/off controlled in response to the first clock; anda capacitive element installed between the first node and ground,wherein the output unit comprises an inverter that receives a voltage of the first node and the predetermined threshold value is a logical threshold voltage of the inverter.9. A semiconductor device comprising:an input node that receives an input signal alternating between high and low levels during normal operation and fixed to a high level during standby;a detection unit that sets an enable signal to a low level upon detecting that the input node remains at a high level for a predetermined period; anda signal transmission unit that includes P-channel MOS transistors and transmits a signal input to the input node according to control by the enable signal,wherein the signal transmission unit comprises a plurality of stages of inverters to transmit a signal input to the input node, andwherein the semiconductor device further comprises a correction circuit that controls back gate voltages of PMOS transistors comprised in inverters at even stages ...

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Номер записи: 31
22-01-2015 дата публикации

DIGITAL CIRCUITS

Номер: US20150022252A1
Автор: Venås Arne Wanvik
Принадлежит: NORDIC SEMICONDUCTOR ASA

A digital circuit portion comprises a flip-flop () having a clock input () and an output (data); a clock signal (ck); and a gate () between said clock signal (ck) and said clock input (), said gate () being arranged selectively to couple the clock signal (ck) to the clock input () in dependence upon the output of the flip-flop (). 1. A digital circuit portion comprising:a flip-flop having a clock input and an output;a clock signal; anda gate between said clock signal and said clock input, said gate being arranged selectively to couple the clock signal to the clock input in dependence upon the output of the flip-flop.2. A digital circuit portion as claimed in wherein said gate comprises an AND gate claim 1 , a NAND gate or a logically equivalent arrangement.3. A digital circuit portion as claimed in wherein said gate is arranged selectively to couple the clock signal to the clock inputs of a plurality of flip-flops.4. A digital circuit portion as claimed in wherein at least some of said flip-flops are arranged in series.5. A digital circuit portion as claimed in wherein at least some of said flip-flops are arranged in parallel.6. A digital circuit portion as claimed in wherein said gate is controlled on the basis of a comparison between the output of the flip-flop and an input thereof.7. A digital circuit portion as claimed in used for self-gating of a reset synchronisation logic arrangement.8. A digital circuit portion as claimed in comprising first and second flip-flops in series with an input to the first flip-flop held at a fixed logic level. This invention relates to digital circuits which include flip-flops. Flip-flops are a simple yet valuable building block of most digital circuits. Flip-flops rely on having a clock signal at their clock input in order for them to operate.The present inventor has appreciated that where the status of a flip-flop does not change very often it is theoretically wasteful to keep the clock signal running to it since there is ...

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Номер записи: 32
22-01-2015 дата публикации

INTEGRATED CIRCUIT AND DATA INPUT METHOD

Номер: US20150023112A1
Автор: BAE YONGCHEOL, EOM Yoon-Joo, Moon Byongmo
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

An integrated circuit includes a data input such as a data pad for receiving an external data signal input and an on-die termination (ODT) information input for receiving ODT information from an external device. An ODT circuit selectively couples a termination resistor to the data pad based on the ODT information. An input buffer is coupled to the data pad for determining data that is input into the pad using a reference voltage. A reference voltage generator is coupled to the input buffer and generates the reference voltage on the basis of the ODT information. 1. An integrated circuit comprising:a pad configured to receive an external data signal input;an on-die termination (ODT) information input configured to receive ODT information from an external device;an ODT circuit configured to selectively couple a termination resistor to the pad based on the ODT information;an input buffer coupled to the pad and configured to determine a data value based on a reference voltage; anda reference voltage generator coupled to the input buffer and configured to generate the reference voltage based on the ODT information.2. The integrated circuit of claim 1 , wherein the ODT information comprises on/off information indicating whether to perform an ODT operation claim 1 , termination information indicating a pull-up termination or a pull-down termination claim 1 , and resistance information indicating an ODT resistance value.3. The integrated circuit of claim 2 , further comprising a mode register configured to provide least a portion of the ODT information.4. The integrated circuit of claim 1 , wherein the ODT circuit further comprises a pull-up termination circuit including the termination resistor selectively coupled between the pad and a power supply voltage based on the ODT information.5. The integrated circuit of claim 1 , wherein the ODT circuit further comprises a pull-down termination circuit including the termination resistor selectively coupled between the pad and a ...

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Номер записи: 33
21-01-2021 дата публикации

PACKAGED INTEGRATED CIRCUIT MEMORY DEVICES HAVING ENHANCED ON-DIE-TERMINATION CIRCUITS THEREIN AND METHODS OF OPERATING SAME

Номер: US20210020227A1
Автор: KIM Taegyeong, Kim Taesung, Lee Buyeon, Moon Byongmo
Принадлежит:

A memory device includes a pad region having a flag pad separated from an external host, and a signal pad connected to the external host. A bank region is provided having a plurality of memory cells therein. An on-die-termination (ODT) setting circuit is provided, which is configured to receive a control command including first data corresponding to termination resistance requested by the host, and a ODT enable signal. The setting circuit is configured to generate second data corresponding to the ODT resistance. An ODT enable circuit is provided, which is configured to output an ODT flag signal to the flag pad, in response to the control command and the ODT enable signal. A resistor circuit is provided, which is configured to connect the ODT resistance to the signal pad using the second data. 1. A memory device comprising:a pad region having a flag pad and a signal pad thereon;a memory bank region having a plurality of memory cells therein;an on-die-termination (ODT) setting circuit configured to receive a control command including first data corresponding to a termination resistance requested by an external host, and an ODT enable signal, and further configured to generate second data corresponding to an ODT resistance;an ODT enable circuit configured to output an ODT flag signal to the flag pad, in response to the control command and the ODT enable signal; anda resistor circuit configured to connect the ODT resistance to the signal pad, in response to the second data.2. The memory device according to claim 1 , further comprising:a transmitter having an output terminal electrically coupled to the flag pad; anda receiver having an input terminal electrically coupled to the flag pad.3. The memory device according to claim 2 , wherein the receiver is turned off and the transmitter is turned on to thereby output the ODT flag signal claim 2 , in response to receipt of the ODT enable signal by the ODT enable circuit.4. The memory device according to claim 3 , wherein the ...

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Номер записи: 34
16-01-2020 дата публикации

Load driver

Номер: US20200021286A1
Автор: David G. Wright, Erhan Hancioglu, Jason Faris Muriby
Принадлежит: Monterey Research LLC

A method for driving a load includes driving a load to an initial voltage within a voltage window, the voltage window based on an input voltage and an offset voltage, and driving the load to approximately the input voltage.

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Номер записи: 35
25-01-2018 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20180025755A1
Автор: Abe Hideaki, MIKI Takeo, Yano Yuji
Принадлежит:

The present invention provides a semiconductor device that can reduce the power consumption. The semiconductor device includes a plurality of sub-blocks each including a memory cell array, and a plurality of sub-search units corresponding to the respective sub-blocks. Of the data stored in each row of the memory cell array, each sub-block searches for data that matches the input search data according to a search instruction, and outputs a search result indicating hit or miss for each row. Each sub-search unit includes a flag data generation part that generates flag data for presearch to compare with part of the input search data based on the data stored in the corresponding memory cell array, and a search part that compares part of the input search data with the flag data generated by the flag data generation part, and outputs the search instruction to the corresponding sub-block based on the comparison result. 1. A semiconductor device comprising:a plurality of sub-blocks each of which includes a memory cell array; anda plurality of sub-search units provided corresponding to each of the sub-blocks,wherein, of a plurality of data stored in each row of the memory cell array, the sub-block searches for data that matches input search data according a search instruction, and outputs a search result that indicates hit or miss for each row, andwherein the sub-search unit comprises:a flag data generation part that generates flag data for presearch in order to compare with part of the input search data, based on the data stored in the corresponding memory cell array, anda search part that compares part of the input search data with flag data generated by the flag data generation part, and outputs the search instruction to the corresponding sub-block based on the comparison result.2. The semiconductor according to claim 1 ,wherein the sub-search unit further includes a memory that stores the generated flag data.3. The semiconductor device according to claim 1 ,wherein the ...

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Номер записи: 36
28-01-2016 дата публикации

SHARED LOGIC FOR MULTIPLE REGISTERS WITH ASYNCHRONOUS INITIALIZATION

Номер: US20160028383A1
Автор: Gunaratna Senani, Sharpe-Geisler Brad, Yew Ting
Принадлежит:

A control circuit is provided that enables a register to provide a synchronous initialization capability as well as an asynchronous capability despite the register having no asynchronous input. 1. A system , comprising:a control circuit configured to assert a dual-mode initialization signal in response to an assertion of an input initialization signal, the control circuit being further configured to respond to an assertion of a synchronous initialization signal while the input initialization signal is asserted by cycling a master clock and a slave clock responsive to a system clock and to respond to an assertion of an asynchronous initialization signal while the input initialization signal is asserted by asserting both the slave clock and the master clock asynchronously with regard to the system clock; anda register including a master latch in series with a slave latch, the master latch being configured to open responsive to an assertion of the master clock and the slave latch being configured to open responsive to an assertion of the slave clock, the register including a first input transmission gate to the master latch configured to switch on in response to an assertion of the dual-mode initialization signal.2. The system of claim 1 , wherein the register further includes a second input transmission gate to the master latch that is configured to switch on in response to a de-assertion of the dual-mode initialization signal.3. The system of claim 1 , wherein the register is configured to provide a selected one of a preload signal and a set signal to the first input transmission gate.4. The system of claim 3 , wherein the system is incorporated into a programmable logic device claim 3 , and wherein the preload signal is a dynamic signal for the programmable logic device and the set signal is a configuration signal for the programmable logic device.5. The system of claim 4 , wherein the programmable logic device comprises a field programmable gate array.6. The system ...

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Номер записи: 37
28-01-2016 дата публикации

ON-DIE TERMINATION CONTROL WITHOUT A DEDICATED PIN IN A MULTI-RANK SYSTEM

Номер: US20160028395A1
Автор: Bains Kuljit S., Bonen Nadav
Принадлежит:

A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (ODT) settings. One of the ranks is selected to execute the memory access command, and executes the command while all ranks triggered to change the ODT setting have the changed ODT setting. 1. A method for selectively applying on-die termination , comprising:sending a memory access command concurrently to a number of ranks of memory devices corresponding to a memory access operation, the memory access command directed to a target rank to execute the command;triggering one or more non-target ranks of the number of ranks to change an on-die termination (ODT) setting for a duration of the memory access operation; andselecting the target rank to execute the memory access operation.2. The method of claim 1 , wherein sending the memory access command comprises sending a read command claim 1 , and wherein triggering the one or more non-target ranks to change the ODT setting comprises triggering the a non-target rank to engage ODT.3. The method of claim 1 , wherein sending the memory access command comprises sending a write command claim 1 , and wherein triggering the one or more non-target ranks to change the ODT setting comprises triggering the target rank and at least one non-target rank to engage ODT.4. The method of claim 1 , wherein sending the memory access command comprises sending the memory access command from a memory controller.5. The method of claim 1 , wherein sending the memory access command comprises sending multiple sequential commands to generate the memory access operation.6. The method of claim 5 , wherein the triggering further comprises sending a first command indicating the memory access operation ...

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Номер записи: 38
25-01-2018 дата публикации

PROGRAMMABLE ANALOG AND DIGITAL INPUT/OUTPUT FOR POWER APPLICATION

Номер: US20180026636A1
Автор: BIRKNER John, Cheung Herman, CROTTY Patrick J., Ghoman Ranajit, SHANKAR Kapil
Принадлежит:

A threshold comparator block integrated in a programmable logic device (PLD) is disclosed. The threshold comparator block includes: one or more signal comparators configured to receive two analog input signals and provide a digital output signal indicating a comparison result of the two analog input signals; an analog output driver configured to interface with an analog fabric of a programmable fabric of the PLD; a digital input/output (I/O) driver configured to interface with a digital fabric of the programmable fabric of the PLD; and I/O pins configured to provide an interface with a signal wrapper to interface analog and digital signals between the analog output driver and the digital I/O driver and the programmable fabric. The threshold comparator block is configured to interface with one or more adaptive blocks integrated in the PLD via the programmable fabric and the signal wrapper. 1. A threshold comparator block integrated in a programmable logic device (PLD) comprising:one or more signal comparators configured to receive two analog input signals and provide a digital output signal indicating a comparison result of the two analog input signals;an analog output driver configured to interface with an analog fabric of a programmable fabric of the PLD;a digital input/output (I/O) driver configured to interface with a digital fabric of the programmable fabric of the PLD; andI/O pins configured to provide an interface with a signal wrapper to interface analog and digital signals between the analog output driver and the digital I/O driver and the programmable fabric,wherein the threshold comparator block is configured to interface with one or more adaptive blocks integrated in the PLD via the programmable fabric and the signal wrapper.2. The threshold comparator block of claim 1 , wherein the digital output signal of the one or more signal comparators indicates a current direction between the two analog input signals.3. The threshold comparator block of claim 1 , ...

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Номер записи: 39
10-02-2022 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20220045681A1
Автор: Kinugasa Masanori, Wakahoi Tooru
Принадлежит:

According to one embodiment, a semiconductor device includes first, second, third, and fourth circuits. A first voltage is applied to the first circuit. A second voltage is applied to each of the second, third and fourth circuits. The third circuit is configured to generate a first control signal and a second control signal based on a signal generated by the first circuit and a signal generated by the second circuit. The fourth circuit is configured to output an output signal based on the first control signal and the second control signal. The output signal is brought to a high impedance state when at least one of the first voltage or the second voltage is not applied. 1. A semiconductor device comprising:a first circuit to which a first voltage is applied and which is capable of receiving a first input signal and a second input signal and is capable of generating a first signal based on the first input signal, a second signal based on the second input signal, and a third signal obtained by inverting a logic level of the second signal;a second circuit to which a second voltage different from the first voltage is applied and which is capable of receiving the second input signal and is capable of generating a fourth signal based on the second input signal and a fifth signal obtained by inverting a logic level of the fourth signal;a third circuit to which the second voltage is applied and which is capable of generating a first control signal based on the first signal, the second signal, and the fourth signal, and a second control signal based on the first voltage, the first signal, the third signal, and the fifth signal; anda fourth circuit to which the second voltage is applied and which is capable of outputting an output signal based on the first control signal and the second control signal,wherein the output signal is brought to a high impedance state when at least one of the first voltage or the second voltage is not applied.2. The device according to claim 1 , ...

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Номер записи: 40
05-02-2015 дата публикации

COMPENSATED IMPEDANCE CALIBRATION CIRCUIT

Номер: US20150035559A1
Автор: Jones Brian D., Sloan Jeffrey H., Wang Xiaopeng
Принадлежит:

Aspects of the invention provide for compensating impedance calibration circuits. In one embodiment, a compensated impedance calibration circuit, includes: a variable resistor network including a tunable resistor and a fixed resistor; and an external resistance network including a target external precision resistor and a parasitic distribution resistance; wherein a resistance of the variable resistor network is proportional to a resistance of the external resistance network, such that a ratio of an output voltage of the variable resistor network to a power supply voltage is constant. 1. A compensated impedance calibration circuit , comprising:a variable resistor network including a tunable resistor and a fixed resistor; andan external resistance network including a target external precision resistor and a parasitic distribution resistance;wherein a resistance of the variable resistor network is proportional to a resistance of the external resistance network, such that a ratio of an output voltage of the variable resistor network to a power supply voltage is constant.2. The compensated impedance calibration circuit of claim 1 , wherein a value for the fixed resistor is selected from a range of discrete values.3. The compensated impedance calibration circuit of claim 1 , further comprising a voltage reference generator for generating a reference voltage.4. The compensated impedance calibration circuit of claim 3 , further comprising a comparator for comparing the reference voltage to the output voltage of the variable resistor network.5. The compensated impedance calibration circuit of claim 4 , further comprising control logic for receiving an output of the comparator and for tuning the variable resistor network claim 4 , such that the output voltage of the variable resistor network is equal to the reference voltage.6. The compensated impedance calibration circuit of claim 1 , wherein the fixed resistor is a pluggable on-chip resistor. The disclosure relates ...

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Номер записи: 41
04-02-2016 дата публикации

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Номер: US20160036439A1
Автор: Douzaka Toshiaki
Принадлежит:

According to one embodiment, a semiconductor integrated circuit device includes a first line to which a voltage is applied; a first circuit operating based on a data; a second circuit capable of retaining the data; a third circuit between the first line and the first circuit and capable of shutting off a supply of the voltage to the first circuit; and a fourth circuit including a resistor element, the resistor element connected between the first line and the second circuit. The fourth circuit supplies the voltage to the second circuit via the resistor element in a period in which the third circuit shut off the supply of the voltage to the first circuit. 1. A semiconductor integrated circuit device comprising:a first power line to which a first voltage is applied;a first circuit operating based on a first data;a second circuit capable of retaining the first data;a third circuit between the first power line and the first circuit and capable of shutting off a supply of the first voltage to the first circuit; anda fourth circuit including a first resistor element, the first resistor element connected between the first power line and the second circuit,wherein the fourth circuit supplies the first voltage to the second circuit via the first resistor element in a first period in which the third circuit shut off the supply of the first voltage to the first circuit.2. The device according to claim 1 , whereinthe fourth circuit includes a first switch element connected in parallel to the first resistor element between the first power line and the second circuit,the fourth circuit connects the second circuit to the first power line by the first switch which is in an on-state, andthe fourth circuit electrically isolates the second circuit from the first power line by the first switch element which is in an off-state.3. The device according to claim 2 , whereinin a second period when the third circuit supplies the first voltage to the first circuit,the fourth circuit supplies ...

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Номер записи: 42
04-02-2016 дата публикации

Clock state control for power saving in an integrated circuit

Номер: US20160036440A1
Автор: Richard Paterson
Принадлежит: ARM LTD

Sequential logic elements may consume less static power in response to a first state of a clock signal than in response to a second state of a clock signal (the first and second state may be either low or high depending on the type of sequential logic). This can be exploited to reduce static power consumption of an integrated circuit by controlling the level of a clock signal so that is in the first state for a greater amount of time than the second state.

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Номер записи: 43
04-02-2016 дата публикации

FAST VOLTAGE DOMAIN CONVERTERS WITH SYMMETRIC AND SUPPLY INSENSITIVE PROPAGATION DELAY

Номер: US20160036444A1
Автор: Li Shengyuan
Принадлежит:

In one embodiment, a circuit comprises a phase interpolator that converts a single-ended input to a pair of symmetric differential signals within a first voltage domain. The circuit further comprises a comparator that converts the symmetric differential signals into single-ended output in a second different voltage domain. In one embodiment, the single ended output of the comparator is configured to be coupled to drive a switching driver in a switching regulator. In one embodiment, the interpolator comprises a first inverter, a second inverter, and a third inverter connected in series. The interpolator further comprises a first resistor and a second resistor connected in series. The second inverter provides a first output signal. Outputs of the first inverter and the third inverter are connected by the series connected resistors. A node between the resistors provides a second output signal. The first and second output signals are inverted and symmetric. 1. A level shifter comprising:a phase interpolator configured to convert a single-ended input to a pair of symmetric differential signals within a first voltage domain; anda comparator configured to convert the symmetric differential signals into a single-ended output in a second different voltage domain.2. The level shifter of wherein the single ended output of the comparator is configured to be coupled to drive a switching driver of a switching regulator.3. The level shifter of wherein the interpolator comprises a first inverter claim 1 , a second inverter and a third inverter connected in series claim 1 , and further comprises a first resistor and a second resistor connected in series claim 1 , the second inverter providing a first output signal claim 1 ,wherein the first resistor comprises an input terminal and an output terminal and the second resistor comprises an input terminal and an output terminal, andwherein output of the first inverter is connected to the input terminal of the first resistor and output of ...

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Номер записи: 44
17-02-2022 дата публикации

MULTI-MODE STANDARD CELL LOGIC AND SELF-STARTUP FOR BATTERY-INDIFFERENT OR PURE ENERGY HARVESTING SYSTEMS

Номер: US20220052693A1
Автор: Alioto Massimo, JAIN Saurabh, LIN Longyang
Принадлежит: NATIONAL UNIVERSITY OF SINGAPORE

A cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, a battery-indifferent or pure energy harvesting multi-mode system, a method of operating a cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, and a method of operating battery-indifferent or pure energy harvesting multi-mode system. The cell gate structure comprises a CMOS gate circuit; a header circuit coupled to the CMOS gate circuit and comprising first and second header transistors for coupling in parallel between a supply voltage and the CMOS gate circuit; and a footer circuit coupled to the CMOS gate circuit and comprising first and second footer transistors for coupling in parallel between the CMOS gate circuit and a ground voltage; wherein the header and footer circuits are configured for switching between different operation modes of the multi-mode system, the different operation modes chosen from a range from a normal mode in which feedback paths from an output of the CMOS gate circuit to the gate of the second header transistor and to the gate of the second footer transistor are substantially or fully disabled for full swing in the output voltage of the CMOS gate circuit, and a leakage suppression mode in which the feedback paths are substantially or fully enabled. 120-. (canceled)22. The cell logic structure of claim 21 , wherein the first and second header transistors comprise NMOS transistors.23. The cell logic structure of claim 21 , wherein the first and second footer transistors comprise PMOS transistors.24. The cell logic structure of claim 21 , wherein the header and footer circuits are configured for disabling the feedback by overdriving the gates of the first header transistor and the first footer transistor.26. The method of claim 25 , wherein the first and second header transistors comprise NMOS transistors.27. The method of claim 25 , wherein the first and second footer transistors comprise PMOS transistors.28 ...

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Номер записи: 45
12-02-2015 дата публикации

SEMICONDUCTOR DEVICE HAVING IMPEDANCE CALIBRATION FUNCTION TO DATA OUTPUT BUFFER AND SEMICONDUCTOR MODULE HAVING THE SAME

Номер: US20150042379A1
Автор: HARA Kentaro
Принадлежит:

A method for calibrating an output buffer including adjusting a first impedance code applied to a first plurality of first transistor units connected in parallel between a calibration terminal and a first power supply potential so that the potential on the calibration terminal substantially equals a reference potential, applying the first impedance code to a second plurality of first transistor units connected in parallel between a node and the first power supply potential, adjusting a second impedance code applied to a second transistor unit connected between the node and a second power supply potential so that the potential on the node substantially equals the reference potential, applying the first impedance code to a third plurality of first transistor units connected in parallel between a data terminal and the first power supply potential, and applying the second impedance code to a fourth plurality of second transistor units. 1. A method for calibrating an output buffer , the method comprising:adjusting a first impedance code applied to a first plurality of first transistor units connected in parallel between a calibration terminal and a first power supply potential so that the potential on the calibration terminal substantially equals a reference potential;applying the first impedance code to a second plurality of first transistor units connected in parallel between a node and the first power supply potential;adjusting a second impedance code applied to a second transistor unit connected between the node and a second power supply potential so that the potential on the node substantially equals the reference potential;applying the first impedance code to a third plurality of first transistor units connected in parallel between a data terminal and the first power supply potential; andapplying the second impedance code to a fourth plurality of second transistor units connected in parallel between the data terminal and the second power supply potential,wherein ...

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Номер записи: 46
12-02-2015 дата публикации

APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY

Номер: US20150042380A1
Автор: Manning Troy A.
Принадлежит: MICRON TECHNOLOGY, INC.

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access. 1. An apparatus , comprising:an array of memory cells; and perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line;', 'perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line; and', 'accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access., 'sensing circuitry comprising a primary latch coupled to a sense line of the array, the sensing circuitry configured to2. The apparatus of claim 1 , wherein the accumulated result in the secondary latch is a result of the logical operation claim 1 , and wherein the sensing circuitry is further configured to store the result of the logical operation in the array without enabling an input/output (I/O) line coupled to the sensing circuitry.3. The apparatus of claim 2 , wherein the logical operation is at least one of:an AND operation; andan OR operation.4. The apparatus of claim 1 , wherein the accumulated result in the secondary latch is an inverse of a result of the logical operation ...

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Номер записи: 47
12-02-2015 дата публикации

LEVEL SHIFTER

Номер: US20150042396A1
Автор: Koudate Kazuhiro
Принадлежит:

A level shifter includes high breakdown voltage first and second PMOS transistors, high breakdown voltage first and second depression NMOS transistors having gates respectively supplied with first and second control signals, low breakdown voltage first and second NMOS transistors having gates respectively supplied with third and fourth control signals, and a timing control unit that generates the first control signal and the third control signal different from the first control signal corresponding to an inverted signal of an input signal, and generates the second control signal and the fourth control signal different from the second control signal corresponding to a non-inverted signal of the input signal. 1. A level shifter comprising:high breakdown voltage first and second PMOS transistors placed in parallel between a first power supply voltage terminal and a reference voltage terminal, each transistor having a gate connected to a drain of the other transistor;high breakdown voltage first and second depression NMOS transistors placed between the first and second PMOS transistors and the reference voltage terminal and having gates respectively supplied with first and second control signals;low breakdown voltage first and second NMOS transistors placed between the first and second depression NMOS transistors and the reference voltage terminal and having gates respectively supplied with third and fourth control signals; anda timing control unit placed between a second power supply voltage terminal supplied with a second power supply voltage lower than a first power supply voltage supplied to the first power supply voltage terminal and the reference voltage terminal, that generates the first control signal and the third control signal different from the first control signal corresponding to an inverted signal of an input signal, and generates the second control signal and the fourth control signal different from the second control signal corresponding to a non- ...

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Номер записи: 48
11-02-2016 дата публикации

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Номер: US20160043720A1
Автор: Hayashi Yoshihiro, KUBOTA Shunsuke, Li Na, ODAWARA Tatsuya, YOSHIZAWA Hiroyasu
Принадлежит:

Provided is a semiconductor integrated circuit device that has a high-voltage analog switch circuit and is operable at a low power-supply voltage. 1. A semiconductor integrated circuit device , including a high-voltage MOSFET in a semiconductor region arranged on a main surface of a semiconductor substrate via an insulating substrate , the semiconductor integrated circuit device comprising:a first high-voltage MOSFET of a first conductive type having a source terminal, a drain terminal, and a gate terminal;a second high-voltage MOSFET of the first conductive type having a source terminal connected to the source terminal of the first high-voltage MOSFET, a gate terminal connected to the gate terminal of the first high-voltage MOSFET, and a drain terminal; anda first floating gate voltage control circuit configured to operate at a voltage within the range between a voltage exceeding a ground voltage and a voltage of 5 V or lower as a power-supply voltage and control on/off states of the first high-voltage MOSFET and the second high-voltage MOSFET according to a first control signal, the first floating gate voltage control circuit being connected to a source terminal of the first high-voltage MOSFET and a gate terminal of the first high-voltage MOSFET, andwhen turning on the first high-voltage MOSFET and the second high-voltage MOSFET, the first floating gate voltage control circuit setting a voltage in the source terminal of the first high-voltage MOSFET as a reference voltage, adding a floating voltage corresponding to the power-supply voltage to the reference voltage, and supplying the floating voltage to the gate terminals of the first high-voltage MOSFET and the second high-voltage MOSFET.2. The semiconductor integrated circuit device according to claim 1 , whereinthe first floating gate voltage control circuit includes a latch circuit that holds the voltage to be supplied to the gate terminals of the first high-voltage MOSFET and the second high-voltage MOSFET,a ...

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Номер записи: 49
19-02-2015 дата публикации

Semiconductor circuit

Номер: US20150048876A1
Автор: Min-Su Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Provided is a semiconductor circuit. The semiconductor circuit includes: an input node configured to receive an enable signal, a sense enable signal, and a clock signal; and a clock gating circuit configured to output an enable clock signal corresponding to the clock signal while a signal level of the enable signal is at a first level regardless of a signal level of the sense enable signal, when the semiconductor circuit is in a high-voltage mode, and output an enable clock signal corresponding to the clock signal while a signal level of at least one of the enable signal and the sense enable signal is at the first level, when the semiconductor circuit is in a low-voltage mode.

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Номер записи: 50
07-02-2019 дата публикации

LOW-POWER CLOCK GATE CIRCUIT

Номер: US20190044511A1
Автор: AGARWAL Amit, Hsu Steven, KRISHNAMURTHY Ram K., Rajwani Iqbal, Realov Simeon
Принадлежит: Intel Corporation

An apparatus is provided which comprises: a first inverter to receive a clock; a pass-gate coupled to the first inverter; a second inverter coupled to the pass-gate and to provide an output clock; and a device coupled to the second inverter and the pass-gate, wherein the transistor and the pass-gate are controllable by a logic that depends on logic values of at least two signals (e.g., an enable and the clock). 1. An apparatus comprising:a first inverter to receive a clock;a pass-gate coupled to the first inverter;a second inverter coupled to the pass-gate and to provide an output clock; anda transistor coupled to the second inverter and the pass-gate, wherein the transistor and the pass-gate are controllable by a logic that depends on logic values of at least two signals including an enable and the clock.2. The apparatus of claim 1 , wherein the pass-gate is a first pass-gate claim 1 , wherein the apparatus comprises a second pass-gate controllable by the clock claim 1 , and wherein the second pass-gate is coupled to an input of the second inverter.3. The apparatus of comprises a NOR gate coupled to the second pass-gate claim 2 , wherein the NOR gate is to provide an output to the second pass-gate according to a test mode and the enable.4. The apparatus of comprises a tristate-able inverter having an output coupled to the first pass-gate claim 2 , wherein the tristate-able inverter is controllable by the clock.5. The apparatus of claim 4 , wherein the second inverter is coupled to the tristate-able inverter.6. The apparatus of claim 1 , wherein the device is a p-type device.7. The apparatus of claim 1 , wherein the pass-gate is a first pass-gate claim 1 , and wherein the logic comprises a NOR gate claim 1 , a tristate-able inverter claim 1 , and a second pass-gate.8. An apparatus comprising:a first inverter to receive a clock;a second inverter coupled in series with the first inverter;a pass-gate coupled to the second inverter; anda device coupled to the pass-gate, ...

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Номер записи: 51
07-02-2019 дата публикации

CALIBRATED BIASING OF SLEEP TRANSISTOR IN INTEGRATED CIRCUITS

Номер: US20190044512A1
Автор: Augustine Charles, Bang Suyoung, CHO Minki, KHELLAH Muhammad, MEINERZHAGEN Pascal
Принадлежит:

Embodiments include apparatuses, methods, and systems associated with biasing a sleep transistor (also referred to as a power gate transistor) in an integrated circuit. The sleep transistor may be coupled between a load circuit and a power rail, the sleep transistor to be on in an active mode to provide the supply voltage to the load circuit, and to be off in a sleep mode to disconnect the load circuit from the power rail. The bias circuit may be coupled to the gate terminal of the sleep transistor to provide a calibrated gate voltage to the gate terminal during the sleep mode. The calibrated gate voltage may be based on a subthreshold leakage current and a gate-induced drain leakage (GIDL) current of the sleep transistor or a replica sleep transistor designed to replicate the leakage current of the sleep transistor. Other embodiments may be described and claimed. 1. A circuit comprising:a load circuit;a power rail to receive a supply voltage;a sleep transistor coupled between the load circuit and the power rail, the sleep transistor to be on in an active mode to provide the supply voltage to the load circuit, and to be off in a sleep mode to disconnect the load circuit from the power rail; and measure a total leakage current of the replica sleep transistor at a plurality of voltage levels of a gate voltage provided to the replica sleep transistor, wherein the total leakage current includes a subthreshold leakage current and a gate-induced drain leakage (GIDL) current of the replica sleep transistor; and', 'set the calibrated gate voltage to a calibrated voltage level that has a lowest measured total leakage current among the plurality of voltage levels., 'a bias circuit coupled to the sleep transistor to provide a calibrated gate voltage to a gate terminal of the sleep transistor during the sleep mode, wherein the bias circuit includes a replica sleep transistor and is to2. The circuit of claim 1 , wherein a source terminal of the replica sleep transistor is ...

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Номер записи: 52
18-02-2016 дата публикации

SEMICONDUCTOR DEVICE HAVING LOW POWER CONSUMPTION

Номер: US20160049936A1
Автор: Okamoto Atsushi
Принадлежит:

A semiconductor device includes a first power supply node and a second power supply node having a voltage value higher than the first power supply node. A first switch interrupts a power supplied from the first power supply node to a first circuit node. A second switch interrupts a power supplied from the second power supply node to a second circuit node. A driver drives the second switch by a third switch being driven. The third switch is connected between the second power supply node and the first circuit node. A controller outputs a control signal to drive the first and third switches. 1. A semiconductor device , comprising:a first power supply node;a second power supply node having a voltage value higher than the first power supply node;a first switch that interrupts a power supplied from the first power supply node to a first circuit node;a second switch that interrupts a power supplied from the second power supply node to a second circuit node;a driver that drives the second switch by a third switch being driven, the third switch connected between the second power supply node and the first circuit node; anda controller that outputs a control signal to drive the first and third switches.2. The semiconductor device as claimed in claim 1 , wherein the third switch is a CMOS inverter.3. The semiconductor device as claimed in claim 2 , wherein the CMOS inverter includes an NMOS transistor and a PMOS transistor having an absolute value of a gate threshold voltage higher than a gate threshold voltage of the NMOS transistor.4. The semiconductor device as claimed in claim 3 , wherein the driver includes a fourth switch that drives the second switch claim 3 , the fourth switch located between the second power supply node and a ground node.5. The semiconductor device as claimed in claim 4 , wherein the fourth switch is a CMOS inverter.6. The semiconductor device as claimed in claim 5 , wherein the second switch includes an NMOS transistor that is driven by the third ...

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Номер записи: 53
16-02-2017 дата публикации

DIAGNOSTIC MONITORING FOR ANALOG-TO-DIGITAL CONVERTERS

Номер: US20170047936A1
Автор: Duryea Timothy Paul, Garg Vaibhav
Принадлежит:

The present disclosure describes a channel selector for use in an analog-to-digital converter that has a sampling circuit for converting an analog input to a digital output within a fault tolerance range. The channel selector includes a reception channel, a diagnostic channel, and an impedance compensator. The reception channel receives an analog signal for delivery to the sampling circuit when it is selected for coupling with the sampling circuit. The diagnostic channel receives a diagnostic signal for verifying the digital output of the sampling circuit when it is selected for coupling with the sampling circuit. The impedance compensator is configured to offset a high channel impedance of the reception channel based on the fault tolerance range of the sampling circuit and when the diagnostic channel is selected. 1. An analog-to-digital converter (ADC) , comprising:a sampling circuit having a fault tolerance range; and a reception channel having a channel impedance;', 'a diagnostic channel;', 'a switch coupled with the reception channel and the diagnostic channel, and configured to select the reception channel or the diagnostic channel for the sampling circuit; and', 'an impedance compensator coupled with the switch, the impedance compensator having a compensatory impedance equal to or greater than a product of the channel impedance and the fault tolerance range., 'a channel selector having2. The ADC of claim 1 , wherein the impedance compensator is coupled in series between the switch and the sampling circuit.3. The ADC of claim 1 , wherein the impedance compensator is coupled in series between the diagnostic channel and the switch.4. The ADC of claim 1 , wherein the impedance compensator is configured to offset the channel impedance of the reception channel based on the fault tolerance range of the sampling circuit and when the diagnostic channel is selected.5. The ADC of claim 1 , wherein:the reception channel includes a first reception channel and a second ...

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Номер записи: 54
13-02-2020 дата публикации

ELECTRONIC DEVICE AND OPERATING METHOD THEREOF

Номер: US20200050254A1
Автор: LEE Sung-Ryong
Принадлежит:

An electronic device includes a resistance element coupled between a supply terminal of a first voltage and an output terminal of an output signal, a driving element coupled between the output terminal of the output signal and a supply terminal of a second voltage, and suitable for operating based on a control signal, and a controller suitable for generating the control signal based on an input signal of the controller to the driving element. The controller drives an output terminal of the control signal with a first driving force during an initial period of a first transition period of the control signal, and drives the output terminal of the control signal with a second driving force different from the first driving force during the remaining period of the first transition period. The initial period is determined depending on a threshold voltage of the driving element. 1. An electronic device including internal circuitry having an output terminal of an output signal , comprising:a resistance element coupled between a supply terminal of a first voltage and the output terminal of the output signal;a driving element coupled between the output terminal of the output signal and a supply terminal of a second voltage to selectively drive the output terminal of the output signal based on a control signal; anda controller coupled to the driving element provide the control signal generated based on an input signal of the controller to the driving element, the controller driving an output terminal of the control signal with a first driving force during an initial period of a first transition period of the control signal and driving the output terminal of the control signal with a second driving force different from the first driving force during a remaining period of the first transition period,wherein the initial period is determined depending on a threshold voltage of the driving element.2. The electronic device of claim 1 , wherein the first driving force is higher than ...

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Номер записи: 55
15-05-2014 дата публикации

Driving integrated circuit

Номер: US20140132310A1
Автор: Li-Tang Lin
Принадлежит: NOVATEK MICROELECTRONICS CORP

A driving integrated circuit (IC) is disclosed. The driving IC comprises a signal processing circuit, a receiver and a terminal resistance providing circuit. The receiver is coupled to a first transmission line and a second transmission line and is output to the signal processing circuit after receiving a transmission signal through the first transmission line and the second transmission line. The terminal resistance providing circuit is coupled to the receiver.

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Номер записи: 56
23-02-2017 дата публикации

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM

Номер: US20170054442A1
Автор: Kim Jae Il
Принадлежит:

A semiconductor system may include a first semiconductor device configured to output a test stop signal and a calibration control signal. The semiconductor system may include a second semiconductor device configured to generate a first state code from an external resistor, a second state code from an internal resistor, and a third state code from a fuse array in response to the calibration control signal, and to select one of the first to third state codes as a selection code in response to the test stop signal and the calibration control signal. 1. A semiconductor system comprising:a first semiconductor device configured to output a test stop signal and a calibration control signal; anda second semiconductor device configured to generate a first state code from an external resistor, a second state code from an internal resistor, and a third state code from a fuse array in response to the calibration control signal, and to select one of the first to third state codes as a selection code in response to the test stop signal and the calibration control signal.2. The semiconductor system of claim 1 , wherein the second semiconductor device includes a pad coupled to the external resistor.3. The semiconductor system of claim 2 , wherein the second semiconductor device comprises:a state code generation unit configured to compare a reference voltage generated in response to the calibration control signal with a voltage of the pad to generate a driving code for driving the voltage of the pad and a voltage of an internal node, and to compare the voltage of the internal node with the reference voltage to generate the first state code for driving the voltage of the internal node.4. The semiconductor system of claim 3 , wherein the state code generation unit comprises:a first comparator configured to compare the reference voltage with the voltage of the pad to generate the driving code; anda first pull-up driving section configured to pull-up drive the voltage of the pad in ...

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Номер записи: 57
13-02-2020 дата публикации

LEVEL SHIFTER

Номер: US20200052703A1
Автор: Lai Tzu-Neng
Принадлежит:

A level shifter includes a first output terminal and a second output terminal. After an output signal in a high level state is outputted from the first output terminal and an inverted output signal in a low level state is outputted from the second output terminal, a weak driving circuit is connected between the first output terminal and a power supply voltage, and a strong driving circuit is connected between the second output terminal and the power supply voltage. After the output signal in the low level state is outputted from the first output terminal and the inverted output signal in the high level state is outputted from the second output terminal, the strong driving circuit is connected between the first output terminal and the power supply voltage, and the weak driving circuit is connected between the second output terminal and the power supply voltage. 1. A level shifter , comprising:a first strong driving path;a first weak driving path;a second strong driving path;a second weak driving path;a selecting module comprising a first selecting circuit and a second selecting circuit, wherein the first strong driving path is connected between a power supply voltage and a first input terminal of the first selecting circuit, the first weak driving path is connected between the power supply voltage and a second input terminal of the first selecting circuit, the second strong driving path is connected between the power supply voltage and a first input terminal of the second selecting circuit, and the second weak driving path is connected between the power supply voltage and a second input terminal of the second selecting circuit;a first P-type transistor, wherein a source terminal of the first P-type transistor is connected with an output terminal of the second selecting circuit, a drain terminal of the first P-type transistor is connected with a first node, and a gate terminal of the first P-type transistor is connected with a second node;a second P-type transistor, ...

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Номер записи: 58
05-03-2015 дата публикации

Analog Signal Compatible CMOS Switch as an Integrated Peripheral to a Standard Microcontroller

Номер: US20150061727A1
Автор: Russell James K.
Принадлежит:

At least one analog signal compatible complementary metal oxide semiconductor (CMOS) switch circuit is incorporated with digital logic circuits in an integrated circuit. The integrated circuit may further comprise a digital processor and memory, e.g., microcontroller, microprocessor, digital signal processor (DSP), programmable logic array (PLA), application specific integrated circuit (ASIC), etc., for controlling operation of the at least one analog signal compatible CMOS switch for switching analog signals, e.g., audio, video, serial communications, etc. The at least one analog signal compatible CMOS switch may have first and second states, e.g., single throw “on” or “off”, or double throw common to a or b, controlled by a single digital control signal of either a logic “0” or a logic “1”. 1. An microcontroller , comprising:a plurality of external input/output connection;a digital processor;a memory coupled to the digital processor; andat least one analog signal compatible complementary metal oxide semiconductor (CMOS) switch coupled to and controlled by the digital processor, and configured to switch signals through a first and a second external input/output connection of said plurality of external input/output connections, wherein the at least one analog signal compatible CMOS switch comprises a first switching node coupled with the first external input/output connection of said plurality of external input/output connections and a second switching node coupled with the second external input/output connection of said plurality of external input/output connections, andwherein the at least one analog signal compatible CMOS switch providesa low impedance between the first external input/output connection and the second external input/output connection when the digital processor asserts a control signal at a first logic level thereto, anda high impedance between the first external input/output connection and the second external input/output connection when the ...

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Номер записи: 59
21-02-2019 дата публикации

IMPEDANCE CALIBRATION DEVICE AND METHOD THEREOF

Номер: US20190058472A1
Автор: CHAN CHENG-PANG, LEI Liang-Huan, Lin Jian-Ru, Wu Chien-Ming
Принадлежит:

An impedance calibration device provided includes a timing device, a first transmitter, a first variable resistor, a second variable resistor and a first receiver. The first variable resistor is used to receive a first adjustment code. The second variable resistor is used to receive a second adjustment code. The first receiver generates a first contact digital signal according to a first contact voltage. The first receiver generates a first terminate digital signal according to a first terminate voltage and the first adjustment code. The first receiver generates a first load digital signal according to a load voltage and the second adjustment. The timing device dynamically adjust the first adjustment code and the second adjustment code according to the first contact digital signal, the first terminate digital signal and the first load digital signal. 1. An impedance calibration device having a timing device , a first channel , a first switch , a first contact resistor and a load resistor , the timing device being coupled to the first channel , the load resistor having an end coupled to an end of the first switch , the load resistor having an uncoupled end connected to ground , the first switch having an uncoupled end coupled to an end of the first contact resistor and the first switch having a load voltage , the impedance calibration device comprising:a first transmitter;a first variable resistor having an end coupled to the first transmitter and having a first terminate voltage, the first variable resistor being used to receive a first adjustment code, the first contact resistor having an uncoupled end coupled to an uncoupled end of the first variable resistor and having a first contact voltage; anda first receiver having a first input terminal, a second input terminal, a third input terminal and a first output terminal, the first input terminal being coupled to an end of a second switch, the second switch having an uncoupled end connected to the first terminate ...

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Номер записи: 60
20-02-2020 дата публикации

CALIBRATION CIRCUIT AND CALIBRATION APPARATUS INCLUDING THE SAME

Номер: US20200059233A1
Автор: CHO Oung Sic, Oh Jong Hoon
Принадлежит: SK HYNIX INC.

A calibration circuit sharing a resistor for impedance matching includes a command decoder configured to receive a command signal and decode the command signal into a calibration enable signal; a selector configured to select one of the calibration enable signal and a start signal according to a select signal, and provide a driving signal; and a calibration driver configured to perform an impedance matching operation in response to the driving signal, and generate a completion signal when performance is completed, wherein the start signal corresponds to a completion signal provided from another calibration circuit which shares the resistor for the impedance matching. 1. A system comprising:a first semiconductor device;a second semiconductor device;a third semiconductor device; anda fourth semiconductor device,wherein the first semiconductor device to the fourth semiconductor device configured to share a resistor for impedance matching,wherein first semiconductor device to the fourth semiconductor device are coupled to have a chain shape,wherein the forth semiconductor device generate a completion signal when performance is completed and the first semiconductor device receive the completion signal provided from the fourth semiconductor device.2. The semiconductor device according to claim 1 , wherein at least one of the first semiconductor device to the fourth semiconductor device includes a volatile memory and at least one of the first semiconductor device to the fourth semiconductor device includes a non-volatile memory.3. The semiconductor device according to claim 1 , wherein each semiconductor device comprises:a first calibration driver configured to, based on a first calibration enable signal, perform an impedance matching operation according to the resistor, anda signal generator configured to generate a completion signal when performance is completed.4. A system comprising:a first semiconductor device to an eighth semiconductor device,wherein the first ...

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Номер записи: 61
01-03-2018 дата публикации

DATA TRANSMISSION DEVICE, AND SEMICONDUCTOR DEVICE AND SYSTEM INCLUDING THE SAME

Номер: US20180062651A1
Автор: JUNG Hae Kang
Принадлежит:

A data transmission device may include a calibration circuit and an output driver. The calibration circuit may generate a pull-up calibration voltage and a pull-down calibration voltage. The resistance value of the output driver may be changed based on the pull-up calibration voltage and the pull-down calibration voltage. 1. A data transmission device comprising:a calibration circuit configured to perform a calibration operation, and generate a pull-up calibration voltage and a pull-down calibration voltage; andan output driver configured to receive the pull-up calibration voltage and the pull-down calibration voltage, and to drive a data transmission line based on the pull-up calibration voltage, the pull-down calibration voltage, and data.2. The data transmission device according to claim 1 , wherein the pull-up calibration voltage and the pull-down calibration voltage are analog voltages.3. The data transmission device according to claim 1 , wherein the calibration circuit comprises:a calibration code generator coupled to an external reference resistor, and configured to generate a pull-up calibration code and a pull-down calibration code; anda calibration voltage generator configured to generate the pull-up calibration voltage based on the pull-up calibration code, and generate the pull-down calibration voltage based on the pull-down calibration code.4. The data transmission device according to claim 1 , wherein:the pull-up calibration voltage and the pull-down calibration voltage have voltage levels between a high voltage and a ground voltage; andthe high voltage has a level higher than a power supply voltage of the output driver.5. The data transmission device according to claim 1 , wherein the output driver comprises:a data driver configured to drive the data transmission line based on the data;a pull-up resistor coupled between the power supply voltage and the data driver, and having a resistance value that is changed based on the pull-up calibration voltage ...

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Номер записи: 62
01-03-2018 дата публикации

INTEGRATED CLOCK GATE CIRCUIT WITH EMBEDDED NOR

Номер: US20180062658A1
Автор: AGARWAL Amit, HSU Steven K., KRISHNAMURTHY Ram K., Rajwani Iqbal R., Realov Simeon
Принадлежит:

An apparatus is provided which comprises: a clock node; a test node; an enable node; and an AND-OR-INVERT (AOI) static latch coupled to the clock node, test node, and enable node, wherein the AOI static latch has embedded NOR functionality. Another apparatus comprises: a critical timing path having a pass-gate based integrated clock gate; and a non-critical timing path electrically coupled to the critical timing path, wherein the non-critical timing path includes an AND-OR-Inverter (AOI) based integrated clock gate with embedded NOR functionality. 1. An apparatus comprising:a clock node;a test node;an enable node; andan AND-OR-INVERT (AOI) static latch coupled to the clock node, test node, and enable node, wherein the AOI static latch has embedded NOR functionality;a NAND gate having a first input coupled to the clock node and a second input coupled to an output of the AOI static latch with embedded NOR functionality; andan inverter coupled to an output of the NAND gate, wherein the inverter is to provide an output.2. (canceled)3. (canceled)4. The apparatus of comprises a NOR gate having a first input coupled to the test node and a second input coupled to the enable node.5. The apparatus of claim 4 , wherein the AOI static latch with embedded NOR functionality comprises:a first p-type transistor having a gate terminal coupled to the test node and a source terminal coupled to a supply node;a second p-type transistor coupled in series with the first p-type transistor, wherein the second p-type transistor has a gate terminal coupled to the enable node; anda third p-type transistor coupled to the second p-type transistor, wherein the third p-type transistor has a gate terminal coupled to the clock node.6. The apparatus of claim 5 , wherein the AOI static latch with embedded NOR functionality comprises a fourth p-type transistor coupled to the third p-type transistor such that a drain terminal of the fourth p-type transistor is coupled to a drain terminal of the third p- ...

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Номер записи: 63
12-03-2015 дата публикации

APPARATUS AND METHODS FOR LEAKAGE CURRENT REDUCTION IN INTEGRATED CIRCUITS

Номер: US20150070049A1
Автор: Laurent Christophe Vincent Antoine
Принадлежит: MICRON TECHNOLOGY, INC.

This disclosure relates to leakage current reduction in integrated circuits (ICs). In one aspect, an IC can include a digital logic circuit and a polarization circuit. The digital logic circuit can have a plurality of inputs and can include a plurality of logic gates. The polarization circuit can receive a standby signal and a digital input signal comprising a plurality of bits. When the standby signal is deactivated, the polarization circuit can control the plurality of inputs of the digital logic circuit based on the digital input signal. However, when the standby signal is activated the polarization circuit can control the plurality of inputs of the digital logic circuit to a low power state associated with a smaller leakage current of the plurality of logic gates relative to at least one other state of the digital logic circuit. 1. An integrated circuit comprising:a digital logic circuit having a plurality of inputs, wherein the digital logic circuit comprises a plurality of logic gates; anda first polarization circuit configured to receive a standby signal and a digital input signal comprising a plurality of bits, wherein when the standby signal is deactivated, the first polarization circuit is configured to control the plurality of inputs of the digital logic circuit based on the digital input signal, and wherein when the standby signal is activated the first polarization circuit is configured to control the plurality of inputs of the digital logic circuit to a low power state associated with a smaller leakage current of the plurality of logic gates relative to at least one other state of the digital logic circuit.2. The integrated circuit of claim 1 , wherein the low power state is associated with the smallest leakage current of the plurality of logic gates relative to all other states of the digital logic circuit.3. The integrated circuit of claim 1 , wherein the plurality of logic gates comprises a plurality of standard cells.4. The integrated circuit of ...

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Номер записи: 64
29-05-2014 дата публикации

INTEGRATED CIRCUIT AND OPERATION METHOD THEREOF

Номер: US20140145754A1
Автор: Jung Jong-Ho
Принадлежит: SK HYNIX INC.

An integrated circuit of a multiple die package structure having a plurality of semiconductor devices, each of the plurality of semiconductor devices may include an active termination circuit configured to perform an active termination operation to the semiconductor device, and to be turned off in a disable state of an active termination setting code, a multiple die package information transfer unit configured to transfer a multiple die package information signal, and a compulsory termination unit configured to selectively convert the active termination setting code into the disable state in response to the multiple die package information signal. 1. An integrated circuit of a multiple die package structure having a plurality of semiconductor devices , each of the plurality of semiconductor devices comprising:an active termination circuit configured to perform an active termination operation to the semiconductor device, and to be turned off according to a disable state of an active termination setting code;a multiple die package information transfer unit configured to transfer a multiple die package information signal; anda compulsory termination unit configured to selectively convert the active termination setting code into the disable state in response to the multiple die package information signal.2. The Integrated circuit of claim 1 , wherein the active termination setting code indicates the disable state when the active termination setting code is set to a predetermined value.3. The Integrated circuit of claim 2 , wherein the compulsory termination unit converts the active termination setting code into the predetermined value in response to an enable state of the multiple die package information signal.4. The integrated circuit of claim 1 , wherein the multiple die package information signal transfer unit outputs the multiple die package information signal as a signal claim 1 , which is applied from a predetermined pad.5. The integrated circuit of claim 1 , ...

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Номер записи: 65
29-05-2014 дата публикации

LOW-POWER DUAL-EDGE-TRIGGERED STORAGE CELL WITH SCAN TEST SUPPORT AND CLOCK GATING CIRCUIT THEREFORE

Номер: US20140145761A1
Автор: Salling Jakob
Принадлежит:

A storage cell having a pulse generator and a storage element is proposed. The storage element input is connected to receive a data input signal. The storage element output is connected to provide a data output signal. The storage element is operable in one of a data retention state and a data transfer state in response to a storage control signal received from the pulse generator. The pulse generator is connected to receive a clock signal with rising and falling clock signal edges and is adapted to provide control pulses in the storage control signal. Each control pulse has a leading edge and a trailing edge. The control pulses have a polarity suited to invoke the data transfer state on their leading edges. The novel feature is that the pulse generator is adapted to initiate a rising-edge control pulse when receiving a rising clock signal edge and to initiate a falling-edge control pulse when receiving a falling clock signal edge. In this way, a dual-edge-triggered flip-flop may be made using only combinatorial logic circuitry and one level- or single-edge-triggered storage element. The storage cell has low power consumption, facilitates scan testing and can be used by existing design tools and test equipment. 1. A modified NOR-gate comprising first , second , third and fourth switch elements , a hold circuit , a clock input terminal , an enable input terminal , an output terminal , a positive supply terminal and a negative supply terminal , each switch element comprising a drain , a source and a gate , and configured to be switched between being in a closed state and being in an open state in response to a control voltage between the gate and the drain or between the gate and the source ,the switch elements being connected in series between a positive supply terminal and a negative supply terminal with the drain of the first switch element being connected to the positive supply terminal, the drain of the second switch element being connected to the source of the ...

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Номер записи: 66
28-02-2019 дата публикации

ALL-DIGITAL LOW VOLTAGE SWING CIRCUIT FOR INTRA-CHIP INTERCONNECTION

Номер: US20190068191A1
Автор: Liu Jack
Принадлежит:

A circuit includes a first driver unit and a second driver unit. The first driver unit is configured to generate a first output signal in response to a data signal and an enable signal, and drive the first output signal towards a power supply voltage, or towards a reference voltage, or hold the first output signal at a previous voltage level. The second driver unit is configured to generate a second output signal in response to the data signal and the enable signal, and drive the second output signal towards the power supply voltage, or towards the reference voltage, or hold the second output signal at a previous voltage level. The first output signal and the second output signal are complementary to each other. 1. A circuit , comprising:a first driver unit configured to generate a first output signal at a first output node in response to a data signal and an enable signal, the first driver unit driving the first output signal towards a power supply voltage, or towards a reference voltage, or holding the first output signal at a previous voltage level;a second driver unit configured to generate a second output signal at a second output node in response to the data signal and the enable signal, the second driver unit driving the second output signal towards the power supply voltage, or towards the reference voltage, or holding the second output signal at a previous voltage level, the first output signal and the second output signal being complementary to each other; andan equalizer connected between the first output node and the second output node, the equalizer configured to, before the data signal is output in a data transmission phase, equalize the first output signal at the first output node and the second output signal at the second output node towards a voltage level between the power supply voltage and the reference voltage in an equalization phase;during a period of time between the equalization phase and the data transmission phase, the first driver unit ...

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Номер записи: 67
28-02-2019 дата публикации

LEVEL SHIFT CIRCUIT AND FINGERPRINT IDENTIFICATION DEVICE

Номер: US20190068192A1
Автор: Li Bo
Принадлежит: Shenzhen Goodix Technology Co., Ltd.

A level shift circuit includes a complementary signal generating unit, a high voltage pulse generating unit, and a shift and latch uni. The high voltage pulse generating unit is connected to the complementary signal generating unit and the shift and latch unit. The complementary signal generating unit is used to receive a target signal at a low voltage domain and output a complementary signal of the target signal and the target signal. The high voltage pulse generating unit is used to generate a high voltage pulse according to the target signal and complementary signa. Tthe shift and latch unit is used to shift the target signal from the low voltage domain to a high voltage domain when a high voltage pulse is generated, and is used to latch and output the target signal at the high voltage domain. 1. A level shift circuit , comprising: a complementary signal generating unit , a high voltage pulse generating unit , and a shift and latch unit , wherein:the complementary signal generating unit is used to receive a target signal at a low voltage domain and output a complementary signal of the target signal and the target signal;the high voltage pulse generating unit comprises a first transistor, a second transistor, a first high voltage transistor, a second high voltage transistor, a first phase inverter, a first delay, a second phase inverter and a second delay; sources of the first transistor and second transistor are grounded, and gates thereof are used to receive the complementary signal and the target signal respectively; the first delay receives the complementary signal through the first phase inverter and the second delay receives the target signal the second phase inverter; sources of the first high voltage transistor and second high voltage transistor are respectively connected to drains of the first transistor and second transistor, gates thereof are respectively connected to the first delay to receive the target signal and the second delay to receive the ...

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Номер записи: 68
28-02-2019 дата публикации

ANALOG-TO-DIGITAL CONVERTER, ELECTRONIC DEVICE, AND METHOD OF CONTROLLING ANALOG-TO-DIGITAL CONVERTER

Номер: US20190068209A1
Автор: Yagishita Yuki
Принадлежит:

To reduce power consumption of an analog-to-digital converter in which a comparator is provided. An analog-to-digital converter includes a comparator and a mode control unit. The comparator is configured to generate a comparison result by comparing an analog signal to a threshold indicating a boundary of a predetermined range in a determination mode and convert the analog signal into a digital signal in a conversion mode. The mode control unit is configured to transition the determination mode to the conversion mode in a case in which the comparison result indicating that the analog signal is not within the predetermined range is generated. 1. An analog-to-digital converter comprising:a comparator configured to generate a comparison result by comparing an analog signal to a threshold indicating a boundary of a predetermined range in a determination mode and convert the analog signal into a digital signal in a conversion mode; anda mode control unit configured to transition the determination mode to the conversion mode in a case in which the comparison result indicating that the analog signal is not within the predetermined range is generated.2. The analog-to-digital converter according to claim 1 , comprising:a digital-to-analog conversion unit configured to generate a positive-side output signal and a negative-side output signal from the analog signal and a predetermined selection signal and output the positive-side output signal and the negative-side output signal to the comparator;a sequential comparison control unit configured to generate a predetermined control signal on a basis of the digital signal in the conversion mode; anda selection unit configured to select the predetermined threshold and supply the predetermined threshold as the predetermined selection signal to the digital-to-analog conversion unit in the conversion mode and to select the predetermined control signal and supply the predetermined control signal as the predetermined selection signal to ...

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Номер записи: 69
05-06-2014 дата публикации

OPERATING METHOD OF INPUT/OUTPUT INTERFACE

Номер: US20140152340A1
Автор: Cho Young Chul, Choi Jung Hwan, LEE Jung Bae
Принадлежит:

A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal. 1. A method of operating an input/output interface comprising:selecting, by an output block of the input/output interface, one of a plurality of output driver circuits according to a mode selection signal, the mode selection signal being a control signal for controlling an on-die termination (ODT) circuit included in the input/output interface; andoutputting a data signal using the selected one of the plurality of output driver circuits.2. The method of claim 1 , before the selecting claim 1 , further comprising:generating the mode selection signal according to memory latency.3. The method of claim 2 , wherein the memory latency is one of a read latency and a write latency.4. The method of claim 1 , before the selecting claim 1 , further comprising:generating the mode selection signal based on a mode register set (MRS) command, the MRS command being used to adjust an operation frequency of the ODT circuit.5. The method of claim 1 , wherein the selecting selects claim 1 ,one of the output driver circuits including a NMOS pull-up transistor when the mode selection signal indicates an operation mode for a high speed operation, andone of the output driver circuits including a PMOS pull-up transistor is selected when the mode selection signal indicates an operation mode for a ...

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Номер записи: 70
07-03-2019 дата публикации

APPARATUSES AND METHODS FOR LEVEL SHIFTING

Номер: US20190074838A1
Автор: Kitagawa Katsuhiro
Принадлежит: MICRON TECHNOLOGY, INC.

Apparatuses and methods for level shifting in a semiconductor device are described. An example apparatus includes: a splitter circuit that operates on a first voltage potential to produce a first signal having a first polarity and a second signal having a second polarity that is substantially opposite to the first polarity; an one-shot pulse circuit that operates on the first voltage potential to produce a first one-shot pulse signal responsive to the first signal and a second one-shot pulse signal responsive to the second signal; and a logic circuit configured to operate on a second voltage potential to produce a third signal responsive to the first and second one-shot pulse signals, the second voltage potential being different from the first voltage potential. 1. A level shifter circuit comprising:a splitter circuit configured to operate on a first voltage potential to provide a first signal having a first polarity and a second signal having a second polarity that is substantially opposite to the first polarity;a one-shot pulse generator circuit configured to operate on the first voltage potential to provide a first one-shot pulse signal responsive to the first signal and a second one-shot pulse signal responsive to the second signal; anda logic circuit configured to operate on a second voltage potential to provide a third signal responsive to the first and second one-shot pulse signals, the second voltage potential being different from the first voltage potential.2. The level shifter circuit of claim 1 , wherein the logic circuit comprises:a pulse generator configured to produce fourth and fifth signals responsive to the first and second one-shot pulse signals; andan XOR gate configured to produce the third signal responsive to the fourth and fifth signals.3. The level shifter circuit of claim 1 , wherein a cycle period of the fourth signal is twice a cycle period of the first signal claim 1 , andwherein a cycle period of the fifth signal is twice a cycle period ...

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Номер записи: 71
16-03-2017 дата публикации

Resistance calibration method and related calibration system

Номер: US20170077927A1
Автор: Chuang Yao-Cheng, Lee Chien-Hsi
Принадлежит:

A resistance calibration method for a first resistor of a first module includes performing resistance calibration on a calibration unit of a second module, wherein the first module is connected to the second module via a pad coupled to the first resistor and the calibration unit is coupled to the pad; obtaining a resistance value of the calibration unit after the resistance calibration; and calibrating a resistance value of the first resistor according to the resistance value of the calibration unit. 1. A resistance calibration method for a first resistor of a first module , the resistance calibration method comprising:performing resistance calibration on a calibration unit of a second module, wherein the first module is connected to the second module via a pad coupled to the first resistor, and the calibration unit is coupled to the pad;obtaining a resistance value of the calibration unit after the resistance calibration; andcalibrating a resistance value of the first resistor according to the resistance value of the calibration unit.2. The resistance calibration method of claim 1 , wherein the step of calibrating the resistance value of the first resistor according to the resistance value of the calibration unit comprises:determining a specific voltage value corresponding to a target resistance value of the first resistor;adjusting the resistance value of the first resistor, wherein a voltage value of an output voltage generated from the pad varies in response to variation of the resistance value of the first resistor; anddetermining that the resistance value of the first resistor reaches the target resistance value when the voltage value of the output voltage reaches the specific voltage value.3. The resistance calibration method of claim 2 , wherein the step of determining that the resistance value of the first resistor reaches the target resistance value when the voltage value of the output voltage reaches the specific voltage value comprises:comparing the ...

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Номер записи: 72
12-06-2014 дата публикации

PROGRAMMABLE EQUALIZATION WITH COMPENSATED IMPEDANCE

Номер: US20140159769A1
Автор: Hong Chan H., Hua My M., Strayer Jayson D.
Принадлежит:

Described is a chip comprising: a pull-up driver with a first impedance, the pull-up driver coupled to a node; a pull-down driver with a second impedance, the pull-down driver coupled to the node; and an equalizer coupled to the pull-up and pull-down drivers, wherein the equalizer is operable to be trained to deemphasize a signal driven on the node while maintaining the first and second impedances substantially constant. 1. A chip comprising:a pull-up driver with a first impedance, the pull-up driver coupled to a node;a pull-down driver with a second impedance, the pull-down driver coupled to the node; andan equalizer coupled to the pull-up and pull-down drivers, wherein the equalizer is operable to be trained to deemphasize a signal driven on the node while maintaining the first and second impedances substantially constant.2. The chip of claim 1 , wherein the equalizer is part of a parallel input-output (I/O) link.3. The chip of claim 1 , wherein the first impedance is independently controllable from control of the second impedance.4. The chip of further comprises:a pull-up driver compensation unit which is operable to determine a code for setting the first impedance for the pull-up driver, and a code for setting a pull-up granularity for de-emphasizing the signal by the equalizer.5. The chip of further comprises:a pull-down driver compensation unit which is operable to determine a code for setting the second impedance for the pull-down driver, and a code for setting a pull-down granularity for de-emphasizing the signal by the equalizer.6. The chip of claim 4 , wherein the equalizer is disabled when the pull-up driver compensation unit is determining the code for setting the first impedance for the pull-up driver.7. The chip of claim 5 , wherein the equalizer is disabled when the pull-down driver compensation unit is determining the code for setting the second impedance for the pull-up driver.8. The chip of claim 5 , wherein the pull-up driver compensation unit and ...

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Номер записи: 73
12-06-2014 дата публикации

Simplified Adaptive Voltage Scaling Using Lookup-Table and Analog Temperature Sensor to Improve Performance Prediction Across Temperature

Номер: US20140159800A1
Автор: Cano Francisco Adolfo, Flores Jose Luis, Hill Anthony Martin
Принадлежит:

A method of adaptive voltage scaling is shown incorporating a lookup table holding manufacturing characterization data in conjunction with one or more precision analog temperature sensors used for correcting for temperature effects. 1. A method of adaptive voltage scaling comprising the steps of:measuring minimum operating voltage at which a logic circuit operates within design limits at a given operating frequency and die temperature;repeating the voltage measurement at a range of given operating frequencies and temperatures;creating a lookup table of the measured voltages indexed by temperature;selecting the required operating frequency and measured die temperature;adjusting the voltage source to the to the operating voltage obtained from the lookup table.2. The method of adaptive voltage scaling of claim 1 , wherein:the voltage measurements and the creation of the lookup table is performed during manufacturing characterization of the die.3. The method of adaptive voltage scaling of claim 1 , wherein:the temperature data used to index into the lookup table is obtained from a temperature sensor incorporated in the die.4. The method of adaptive voltage scaling of claim 1 , wherein:the operating voltage is periodically adjusted dependant upon changes in the die temperature as measured by the temperature sensor to the voltage value given in the lookup table for the measured temperature and the specified operating frequency.5. The method of adaptive voltage scaling of claim 1 , wherein:a predefined hysteresis band is applied to the temperature measurements to avoid “hunting” caused by minor changes and measurement noise. The technical field of this invention is adaptive voltage scaling.Frequency and voltage scaling are common place in electronic processors. These devices are providing more and more functionality and demand the highest data processing efficiency. Adaptive Voltage Scaling (AVS) provides the lowest operation voltage for a given processing frequency by ...

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Номер записи: 74
14-03-2019 дата публикации

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Номер: US20190081029A1
Автор: Kitaura Tomoyasu, Okamoto Atsushi, TAKENO Hirotaka
Принадлежит:

A circuit block including standard cells () arranged therein is provided with switch cells () capable of switching between electrical connection and disconnection between power supply lines () extending in an X-direction and power supply straps () extending in a Y-direction. Each of the power supply straps () is provided with a single switch cell () arranged every M sets of power supply lines () (M is an integer of 3 or more). In the Y-direction, the switch cells () are arranged at different positions in the power supply straps () adjacent to each other, and are arranged at the same position every M power supply straps () in the X-direction. 1. A semiconductor integrated circuit device , comprising:a plurality of standard cell rows, each of which includes a plurality of standard cells arranged in a first direction, arranged in a second direction perpendicular to the first direction;a plurality of power supply lines extending in the first direction, and supplying power to the plurality of standard cells,a plurality of power supply straps extending in the second direction in a layer above the plurality of power supply lines;a plurality of sub-power supply straps extending in the second direction in a layer above the plurality of power supply lines and respectively connected to the plurality of power supply lines; anda plurality of switch cells provided between any one of the plurality of power supply straps and a set of N power supply line(s) (N is an integer of 1 or more) of the plurality of power supply lines, the switch cells being capable of switching between electrical connection and disconnection between the power supply strap and the power supply lines making the set in accordance with a control signal, whereineach of the plurality of power supply straps is provided with one of the plurality of switch cells arranged every M sets of power supply lines (M is an integer of 3 or more), andin the second direction, the switch cells are arranged at different positions ...

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Номер записи: 75
22-03-2018 дата публикации

TERMINATION CIRCUIT, RECEIVER AND ASSOCIATED TERMINATING METHOD CAPABLE OF SUPPRESSING CROSSTALK

Номер: US20180083623A1
Автор: Li An-Siou
Принадлежит:

A termination circuit, a receiver and associated terminating method are provided. The termination circuit is applied to a receiving terminal for receiving a channel transmission signal. Being coupled to a control module, the termination circuit includes an upper circuit and a lower circuit. The upper circuit selectively conducts the receiving terminal to a first voltage terminal, and the lower circuit selectively conducts the receiving terminal to a second voltage terminal. The control module detects a voltage level of the receiving terminal in response to a trigger signal, and accordingly controls the first switching signal and the second switching signal for a termination duration. The termination duration is corresponding to an n-th data bit carried by the channel transmission signal. 1. A termination circuit coupled to a control module and a receiving terminal for receiving a channel transmission signal , wherein the termination circuit comprises: a first termination component, coupled to a first voltage terminal; and', 'a first switch, coupled to the first termination component and the receiving terminal, for selectively conducting the receiving terminal to the first termination component according to a first switching signal; and, 'an upper circuit, comprising a second termination component, coupled to a second voltage terminal; and', 'wherein the control module detects a voltage level of the receiving terminal in response to a trigger signal, and accordingly controls the first and the second switching signals for a termination duration, wherein the termination duration is corresponding to an n-th data bit carried by the channel transmission signal.', 'a second switch, coupled to the second termination component and the receiving terminal, for selectively conducting the receiving terminal to the second termination component according to a second switching signal,'}], 'a lower circuit, comprising2. The termination circuit according to claim 1 , wherein the ...

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Номер записи: 76
22-03-2018 дата публикации

Techniques For Power Control Of Circuit Blocks

Номер: US20180083626A1
Автор: Tang Lai Guan
Принадлежит: Altera Corporation

An integrated circuit includes a circuit block, a storage circuit that stores a static power gating control signal, a logic gate circuit that receives a dynamic power gating control signal and the static power gating control signal from the storage circuit, and a transistor coupled between the circuit block and a supply node at a supply voltage. A conductive state of the transistor is determined by an output signal of the logic gate circuit. The transistor is turned off to provide power gating to the circuit block in response to a change in the output signal of the logic gate circuit that is caused by the static power gating control signal or by the dynamic power gating control signal. 1. An integrated circuit comprising:a circuit block;a first storage circuit to store a static power gating control signal;a first logic gate circuit to receive a dynamic power gating control signal and the static power gating control signal from the first storage circuit; anda transistor coupled between the circuit block and a supply node at a supply voltage, wherein a conductive state of the transistor is determined by an output signal of the first logic gate circuit, and wherein the transistor is turned off to provide power gating to the circuit block in response to a change in the output signal of the first logic gate circuit that is caused by the static power gating control signal or the dynamic power gating control signal.2. The integrated circuit of further comprising:a second storage circuit to store a static isolation control signal;a second logic gate circuit to receive a dynamic isolation control signal and the static isolation control signal from the second storage circuit; anda third logic gate circuit to receive an output signal of the circuit block and a signal that is based on an output signal of the second logic gate circuit, wherein the third logic gate circuit prevents the output signal of the circuit block from propagating to other circuits in the integrated circuit ...

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Номер записи: 77
24-03-2016 дата публикации

STORAGE CONTROLLERS, METHODS OF OPERATING THE SAME AND SOLID STATE DISKS INCLUDING THE SAME

Номер: US20160087630A1
Автор: Cho Jung-Hee, KIM Su-Jin, Park Kwang-Soo
Принадлежит:

A storage controller includes a first on-die termination (ODT) circuit, a second ODT circuit and an ODT control circuit. The first ODT circuit provides a first termination resistance with a strobe signal line transferring a data strobe signal. The second ODT circuit provides a second termination resistance with at least one data line transferring data. The ODT control circuit individually controls activation and deactivation of the first ODT circuit and the second ODT circuit. 1. A storage controller comprising:a first on-die termination (ODT) circuit that is configured to provide a first termination resistance with a strobe signal line that is configured to transfer a data strobe signal;a second ODT circuit that is configured to provide a second termination resistance with at least one data line that transfers data; andan ODT control circuit that is configured to individually control activation and deactivation of the first ODT circuit and the second ODT circuit.2. The storage controller of claim 1 , wherein the ODT control circuit activates the first ODT circuit and deactivates the second ODT circuit during a reception operation in which the storage controller receives the data from a nonvolatile memory device.3. The storage controller of claim 2 , wherein the ODT control circuit provides a first ODT control signal to the first ODT circuit to activate the first ODT circuit and provides a second ODT control signal to the second ODT circuit to deactivate the second ODT circuit claim 2 , in response to receiving a mode signal.4. The storage controller of claim 1 , further comprising:an I/O circuit that receives the data and the data strobe signal,wherein the I/O circuit determines a logic value of the data based on the data strobe signal.5. The storage controller of claim 4 , wherein the I/O circuit is connected with the first ODT circuit via the strobe signal line and is connected with the second ODT circuit via the at least one data line.6. The storage controller ...

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Номер записи: 78
12-03-2020 дата публикации

BODY BIASING FOR ULTRA-LOW VOLTAGE DIGITAL CIRCUITS

Номер: US20200081476A1
Автор: Abouzeid Fady, LALLEMENT Guenole
Принадлежит: STMICROELECTRONICS (CROLLES 2) SAS

A digital circuit includes logic circuitry formed by logic gates. Each logic gate includes a p-channel MOSFET and an n-channel MOSFET. A body bias generator circuit applies an n-body bias voltage to the n-body bias nodes of the p-channel MOSFETs and applies a p-body bias voltage to the p-body bias nodes of the n-channel MOSFETs. The body bias generator circuit operates in: a first mode to apply a ground supply voltage to the n-body bias nodes of the logic gates as the n-body bias voltage and apply a positive supply voltage to the p-body bias nodes of the logic gates as the p-body bias voltage; and a second mode to apply the positive supply voltage to the n-body bias nodes of the logic gates as the n-body bias voltage and apply the ground supply voltage to the p-body bias nodes of the logic gates as the p-body bias voltage. 1. A circuit , comprising:a digital circuit powered by a power domain having a positive supply voltage and a ground supply voltage, wherein the digital circuit includes logic circuitry formed by a plurality of logic gates, where each logic gate of the plurality of logic gates includes at least one p-channel MOSFET having an n-body connected to an n-body bias node and at least one n-channel MOSFET having a p-body connected to a p-body bias node; and in a first mode to apply the ground supply voltage to the n-body bias nodes in the plurality of logic gates as the n-body bias voltage and apply the positive supply voltage to the p-body bias nodes in the plurality of logic gates as the p-body bias voltage; and', 'in a second mode to apply the positive supply voltage to the n-body bias nodes in the plurality of logic gates as the n-body bias voltage and apply the ground supply voltage to the p-body bias nodes in the plurality of logic gates as the p-body bias voltage., 'a body bias generator circuit configured to apply an n-body bias voltage to the n-body bias nodes of the p-channel MOSFETs in the plurality of logic gates and apply a p-body bias voltage ...

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Номер записи: 79
12-03-2020 дата публикации

PROACTIVE CLOCK GATING SYSTEM TO MITIGATE SUPPLY VOLTAGE DROOPS

Номер: US20200081479A1
Автор: Kalyanam Vijay Kiran, MAHURIN Eric Wayne
Принадлежит:

A clock gating system (CGS) includes a digital power estimator configured to generate indications of a predicted energy consumption per cycle of a clock signal and a maximum energy consumption per cycle of the clock signal. The CGS further includes a voltage-clock gate (VCG) circuit coupled to the digital power estimator. The VCG circuit is configured to gate and un-gate the clock signal based on the indications prior to occurrence of a voltage droop event and using hardware voltage model circuitry of the VCG circuit. The VCG circuit is further configured to gate the clock signal based on an undershoot phase associated with the voltage droop event and to un-gate the clock signal based on an overshoot phase associated with the voltage droop event. 1. A clock gating system (CGS) comprising:a digital power estimator configured to generate indications of a predicted energy consumption per cycle of a clock signal and a maximum energy consumption per cycle of the clock signal; anda voltage-clock gate (VCG) circuit coupled to the digital power estimator and configured to gate and un-gate the clock signal based on the indications prior to occurrence of a voltage droop event and using hardware voltage model circuitry of the VCG circuit,wherein the VCG circuit is further configured to gate the clock signal based on an undershoot phase associated with the voltage droop event and to un-gate the clock signal based on an overshoot phase associated with the voltage droop event.2. The CGS of claim 1 , wherein the VCG circuit is configured to gate the clock signal to reduce or eliminate voltage droop in a supply voltage claim 1 , and further comprising a primary device and at least one other device configured to operate with or without monitoring a voltage level of the supply voltage claim 1 , wherein the primary device and at least one other device are configured to share a same power distribution network voltage supply or are each coupled to a respective dedicated and private ...

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Номер записи: 80
12-03-2020 дата публикации

PSEUDO-ASYNCHRONOUS DIGITAL CIRCUIT DESIGN

Номер: US20200082031A1
Автор: FISH Alexander, KEREN Osnat, LEVI Itamar
Принадлежит: Bar-llan University

A logic element includes a logic block, a supply voltage input, switchable power gates and a gate selector. The logic block implements a logic function on input data to obtain at least one output data signal. The switchable power gates transfer a supply voltage from the supply voltage input to the logic block in accordance with respective gate control signals. At least two of the power gates have different respective electrical properties. The gate selector switches on differing ones of the power gates in accordance with gate selection data. 1. A logic element comprising:a logic block, adapted to implement a logic function on input data to obtain at least one output data signal;a supply voltage input;a plurality of switchable power gates connected to said supply voltage input and to said logic block, adapted to transfer a supply voltage from said supply voltage input to said logic block in accordance with respective gate control signals, at least two of said power gates having a different respective electrical properties; anda gate selector associated with said power gates, adapted to switch on differing ones of said power gates in accordance with gate selection data.2. A logic element according to claim 1 , wherein claim 1 , for each set of gate selection data claim 1 , said gate selector is adapted to switch on a single one of said power gates.3. A logic element according to claim 1 , wherein said gate selection data comprises functions of said input data.4. A logic element according to claim 1 , wherein said gate selector is further adapted to switch on said differing ones of said power gates per cycle of a clock signal.5. A logic element according to claim 1 , wherein said gate selector is further adapted to switch on said differing ones of said power gates a plurality of times during a cycle of a clock signal.6. A logic element according to claim 1 , wherein at least two of said power gates have different respective voltage thresholds.7. (canceled)8. A logic ...

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Номер записи: 81
02-04-2015 дата публикации

SEQUENTIAL LOGIC CIRCUIT AND METHOD OF PROVIDING SETUP TIMING VIOLATION TOLERANCE THEREFOR

Номер: US20150091607A1
Автор: Fleshel Leonid, Priel Michael, Rozen Anton
Принадлежит: Freescale Semiconductor, Inc.

A sequential logic circuit comprising a first latch component comprising a data input arranged to receive an input signal, a data output arranged to output a current logical state of the first latch component and a clock input arranged to receive a clock signal; the first latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a first logical state, and to comprise a latched state upon the clock signal received thereby comprising a second logical state, and a second latch component comprising a data input arranged to receive an input signal, a data output operably coupled to an output of the sequential logic circuit and arranged to output a current state of the second latch component and a clock input arranged to receive a clock signal; the second latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a second logical state, and to comprise a latched state upon the clock signal received thereby comprising a first logical state. The sequential logic circuit is arranged to operate in at least a first operating mode in which the data input of the first latch component and the data input of the second latch component are operably coupled to a first input of the sequential logic circuit, and in which the clock signals provided to the first and second latch components are such that a transition of the second latch component from a transparent state to a latched state is delayed relative to a corresponding transition of the first latch component from a transparent state to a latched state for a time period for receiving late data. 1. A sequential logic circuit comprising:a first latch component comprising a data input arranged to receive an input signal, a data output arranged to output a current logical state of the first latch component and a clock input arranged to receive a clock signal; the first latch component being arranged to comprise a transparent ...

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Номер записи: 82
02-04-2015 дата публикации

IMPEDANCE CALIBRATION CIRCUITS

Номер: US20150091611A1
Автор: JEONG Hyun Sik
Принадлежит: SK HYNIX INC.

Impedance calibration circuits are provided. The impedance calibration circuit includes an operation control signal generator and an impedance calibrator. The operation control signal generator receives temperature code signals to generate an operation control signal enabled when an internal temperature is changed from a first temperature to a second temperature. The impedance calibrator receives an external command signal or the operation control signal to generate pull-up code signals for pulling up an output signal and pull-down code signals for pulling down the output signal according to an external resistor. 1. An impedance calibration circuit comprising:an operation control signal generator suitable for receiving temperature code signals to generate an operation control signal enabled when an internal temperature is changed from a first temperature to a second temperature; andan impedance calibrator suitable for receiving an external command signal or the operation control signal to generate pull-up code signals for pulling up an output signal and pull-down code signals for pulling down the output signal according to an external resistor.2. The impedance calibration circuit of claim 1 , wherein the operation control signal generator includes:a first logic unit suitable for generating a first reset signal enabled when at least one of the external command signal and an operation delay signal is enabled;a latch pulse generator suitable for generating a latch pulse signal enabled when the temperature code signals having a logic combination corresponding to the second temperature are inputted thereto after the temperature code signals having a logic combination corresponding to the first temperature are inputted thereto;a control signal generator suitable for generating the operation control signal which is initialized in response to the first reset signal and which is enabled in response to the latch pulse signal; anda first delay unit suitable for retarding the ...

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Номер записи: 83
19-06-2014 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20140167817A1
Автор: Ohmaru Takuro
Принадлежит: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

A programmable analog device and an analog device that can retain data even when supply of a power supply potential is interrupted and consumes less power. In a semiconductor device, first to fourth transistors are used as switches in a unit cell including an analog element, and the output of the unit cell switches between a conducting state, a non-conducting state, and a conducting state through the analog element by controlling the potential of a first node where the first transistor and the second transistor are connected and the potential of a second node where the third transistor and the fourth transistor are connected. 1. (canceled)2. A semiconductor device comprising:a programmable circuit comprising:a first unit cell;a second unit cell;a bit line;a first unit cell selection line;a first analog element selection line;a first input signal line;a first output signal line,a second unit cell selection line;a second analog element selection line;a second input signal line; anda second output signal line,wherein:the first unit cell comprises a first transistor, a second transistor, a third transistor, a fourth transistor, and a first analog element,the first unit cell selection line and a gate electrode of the first transistor are electrically connected to each other,the bit line, one of a source electrode and a drain electrode of the first transistor, and one of a source electrode and a drain electrode of the third transistor are electrically connected to each other,the first analog element selection line and a gate electrode of the third transistor are electrically connected to each other,the first input signal line, one of a source electrode and a drain electrode of the second transistor, and one of electrodes of the first analog element are electrically connected to each other,the other of the electrodes of the first analog element and one of a source electrode and a drain electrode of the fourth transistor are electrically connected to each other,the first ...

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Номер записи: 84
31-03-2016 дата публикации

LOW AREA FULL ADDER WITH SHARED TRANSISTORS

Номер: US20160092170A1
Автор: Nandi Suvam, Subbannavar Badarish Mohan
Принадлежит:

A full adder is disclosed that utilizes low area. The full adder includes an exclusive NOR logic circuit. The exclusive NOR logic circuit receives a first input and a second input. A first inverter receives an output of the exclusive NOR logic circuit and generates an exclusive OR output. A carry generation circuit receives the output of the exclusive NOR logic circuit, the exclusive OR output and a third input. The carry generation circuit generates an inverted carry. A second inverter is coupled to the carry generation circuit and generates a carry on receiving the inverted carry. A sum generation circuit receives the output of the exclusive NOR logic circuit, the exclusive OR output and the third input. The sum generation circuit generates an inverted sum. A third inverter is coupled to the sum generation circuit and generates a sum on receiving the inverted sum. 1. A full adder comprising:an exclusive NOR logic circuit configured to receive a first input and a second input;a first inverter configured to receive an output of the exclusive NOR logic circuit and configured to generate an exclusive OR output;a carry generation circuit configured to receive the output of the exclusive NOR logic circuit, the exclusive OR output and a third input, the carry generation circuit configured to generate an inverted carry; anda sum generation circuit configured to receive the output of the exclusive NOR logic circuit, the exclusive OR output and the third input, the sum generation circuit configured to generate an inverted sum.2. The full adder of further comprising:a second inverter coupled to the carry generation circuit and configured to generate a carry on receiving the inverted carry; anda third inverter coupled to the sum generation circuit and configured to generate a sum on receiving the inverted sum.3. The full adder of claim 1 , wherein the exclusive NOR logic circuit comprises:a first NAND logic circuit configured to receive the first input and the second input; ...

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Номер записи: 85
31-03-2016 дата публикации

CIRCUIT FOR LOW-POWER TERNARY DOMINO REVERSIBLE COUNTING UNIT

Номер: US20160094221A1
Автор: WANG Pengjun, ZHANG Yuejun, ZHENG Xuesong
Принадлежит:

A circuit for a ternary Domino reversible counting unit. The circuit includes a ternary adiabatic Domino D flip-flop, a ternary adiabatic Domino positive and negative circulation port, and a ternary adiabatic Domino T-operation circuit. The ternary adiabatic Domino T-operation circuit includes a first signal input end, a second signal input end, and a third signal input end, a selection signal input end, a signal output end, a first clock signal input end, and a second clock signal input end. The positive and negative circulation port includes a signal input end, a borrow terminal, a carry terminal, a first output end, a second output end, a first clock signal input end, a second clock signal input end, and a third clock signal input end. The D flip-flop includes a signal input end, a reset terminal, a set terminal, a reverse-phase set terminal, a signal output end. 1. A circuit for a ternary Domino reversible counting unit , the circuit comprising a ternary adiabatic Domino D flip-flop , a ternary adiabatic Domino positive and negative circulation port , and a ternary adiabatic Domino T-operation circuit; whereinthe ternary adiabatic Domino D flip-flop comprises a signal input end, a reset terminal, a set terminal, a reverse-phase set terminal, a signal output end, a first clock signal input end, a second clock signal input end, and a third clock signal input end; the first clock signal input end of the ternary adiabatic Domino D flip-flop receives a first clock signal, the second clock signal input end of the ternary adiabatic Domino D flip-flop receives a second clock signal, and the third clock signal input end of the ternary adiabatic Domino D flip-flop receives a third clock signal; amplitude levels of the first clock signal and the second clock signal correspond to Logic 2, and a phase difference of the first clock signal and the second clock signal is 180 degrees; an amplitude level of the third clock signal correspond to Logic 1, and a phase of the third ...

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Номер записи: 86
31-03-2016 дата публикации

ON-DIE TERMINATION/DRIVING CIRCUIT AND METHOD OF USING THE SAME

Номер: US20160094222A1
Автор: HUANG Tien-Chien
Принадлежит:

An on-die termination (ODT)/driving circuit includes a connection pad, and a sub-circuit. A first side of the sub-circuit is connected to the connection pad. The ODT/driving circuit further includes a first switch directly connected to a second side of the sub-circuit. The second side of the sub-circuit is opposite the first side of the sub-circuit. The first switch is configured to selectively connect the second side of the sub-circuit to a supply voltage. The ODT/driving circuit further includes a second switch directly connected to the second side of the sub-circuit. The second switch is configured to selectively connect the second side of the sub-circuit to a reference voltage. The ODT/driving circuit further includes a receiver connected to a node located between the connection pad and the first side of the sub-circuit. 1. An on-die termination (ODT)/driving circuit comprising:a connection pad;a sub-circuit, wherein a first side of the sub-circuit is connected to the connection pad;a first switch directly connected to a second side of the sub-circuit, wherein the second side of the sub-circuit is opposite the first side of the sub-circuit, and the first switch is configured to selectively connect the second side of the sub-circuit to a supply voltage;a second switch directly connected to the second side of the sub-circuit, wherein the second switch is configured to selectively connect the second side of the sub-circuit to a reference voltage; anda receiver connected to a node located between the connection pad and the first side of the sub-circuit.2. The ODT/driving circuit of claim 1 , wherein the sub-circuit is a single resistor.3. The ODT/driving circuit of claim 1 , wherein the sub-circuit is a variable resistor.4. The ODT/driving circuit of claim 1 , wherein the first switch includes a plurality of transistors claim 1 , wherein the plurality of transistors is configured to vary a resistance between the second side of the sub-circuit and the supply voltage ...

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Номер записи: 87
31-03-2016 дата публикации

LOGIC CIRCUIT, SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE

Номер: US20160094224A1
Автор: TAMURA Hikaru
Принадлежит:

A drive capability of a dynamic logic circuit is improved. A logic circuit includes a dynamic logic circuit, a first output node, a first transistor that is diode-connected, and a capacitor. The dynamic logic circuit includes a second output node. The first transistor and transistors in the dynamic logic circuit have an n-type conductivity or a p-type conductivity. The first output node is electrically connected to a first terminal of the capacitor, and the second output node is electrically connected to a second terminal of the capacitor. A first terminal of the first transistor is electrically connected to the first output node, and a first voltage is input to a second terminal of the first transistor. 1. A logic circuit comprising:a dynamic logic circuit comprising transistors;a first output node; anda capacitor,wherein the dynamic logic circuit includes a second output node,wherein the transistors have an n-type conductivity or a p-type conductivity,wherein the first output node is electrically connected to a first terminal of the capacitor, andwherein the second output node is electrically connected to a second terminal of the capacitor.2. The logic circuit according to claim 1 , wherein the transistors each include an oxide semiconductor comprising a channel formation region.3. A logic circuit comprising:a first output node;a first transistor;a capacitor; anda dynamic logic circuit comprising second transistors;wherein the dynamic logic circuit includes a second output node,wherein the first transistor and the second transistors have an n-type conductivity or a p-type conductivity,wherein the first output node is electrically connected to a first terminal of the capacitor,wherein the second output node is electrically connected to a second terminal of the capacitor,wherein the first transistor is diode-connected,wherein a first terminal of the first transistor is electrically connected to the first output node, andwherein a first voltage is input to a second ...

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Номер записи: 88
21-03-2019 дата публикации

Low Power Clock Gating Circuit

Номер: US20190089354A1
Автор: Bhatia Ajay, Seningen Michael R., Venugopal Vivekanandan
Принадлежит:

A clock gating circuit is disclosed. The clock gating circuit includes an input circuit configured to receive an enable signal and clock enable circuitry configured to receive an input clock signal. The clock gating circuit also includes a latch that captures and stores an enabled state of the enable signal when the enable signal is asserted. An output circuit is coupled to the latch, and provides an output signal corresponding to a state of the clock signal when the latch is storing the enabled state. The clock gating circuit is arranged such that, when the latch is not storing the enabled state, no dynamic power is consumed responsive to state changes of the input clock signal. 1. A circuit comprising:an input circuit configured to receive an enable signal;clock enable circuitry configured to receive a clock signal;a latch configured to capture and store an enabled state of the enable signal, wherein the enabled state corresponds to the enable signal being in an active state, wherein the latch comprises a feed forward circuit having a feed forward node and a feedback circuit having a feedback node, wherein the feedback circuit is coupled to provide a feedback signal to the feed forward circuit, wherein the feed forward circuit is configured to capture a current state of the enable signal when the clock signal is inactive, and wherein the feedback circuit is configured to cause the feed forward circuit to retain the enabled state of the enable signal when the clock signal transitions from a logic high state to a logic low state;an output circuit configured to provide an output signal corresponding to a state of the clock signal when the latch is storing the enabled state;wherein the circuit is configured such that dynamic power consumption does not change responsive to a change in the state of the clock signal when the latch is not storing the enabled state.2. The circuit as recited in claim 1 , wherein the input circuit is coupled to receive a test enable signal ...

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Номер записи: 89
30-03-2017 дата публикации

HIGH SPEED LOW CURRENT VOLTAGE COMPARATOR

Номер: US20170093399A1
Автор: Atkinson Nicholas Montgomery, Elsayed Mohamed Mostafa, Kallam Praveen
Принадлежит:

In one embodiment, a voltage comparator circuit includes a first comparator circuit to compare a first voltage and a second voltage and a second comparator circuit to compare the first voltage and the second voltage. The voltage comparator circuit may include charge storage circuitry and positive feedback circuitry. Such circuitry may boost current within the first and second comparator circuits to enable the voltage comparator circuit to output a comparison decision within a delay threshold in response to input transitions within a slew rate threshold. 1. An apparatus comprising:a first comparator having a first common gate input stage with a first input terminal to receive a first voltage and a second input terminal to receive a second voltage, a first capacitor coupled between the first input terminal and a common gate connection of the first common gate input stage, the first common gate input stage to output a first comparison signal, and a first feedback circuit to provide a first boost current to the first common gate input stage responsive to a first value of the first comparison signal and to pull down a level of the first comparison signal responsive to a first value of a second comparison output signal, the first comparator to output a first comparison output signal based on the first comparison signal; anda second comparator having a second common gate input stage with a first input terminal to receive the second voltage and a second input terminal to receive the first voltage, and a second capacitor coupled between the first input terminal of the second common gate input stage and a common gate connection of the second common gate input stage, the second common gate input stage to output a second comparison signal, the second comparator to output the second comparison output signal based on the second comparison signal.2. The apparatus of claim 1 , further comprising a second feedback circuit to provide a second boost current to the second common gate ...

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Номер записи: 90
30-03-2017 дата публикации

INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

Номер: US20170093401A1
Автор: LEE Dal-hee, SEO Jae-woo
Принадлежит:

An integrated circuit (IC) includes a first circuit, a first well and a second circuit. The first circuit is disposed on a substrate and configured to shift a first bit signal between a first voltage logic level and a second logic voltage level. The first well is disposed in a cell on the substrate and biased to a first voltage. The first well is spaced apart from a first edge of the cell. The second well is disposed in the cell and biased to a second voltage. The second well is disposed to contact a second edge of the cell opposite to the first edge. The first circuit includes a plurality of transistors respectively disposed in the first and second wells. 1. An integrated circuit (IC) comprising:at least one block including a first cell disposed on an edge of the at least one block, wherein the first cell comprises:a first circuit configured to shift a first bit signal between a first voltage logic level and a second logic voltage level;a first well biased to a first voltage, wherein the first well is spaced apart from a first edge of the first cell; anda second well biased to a second voltage, wherein the second well is disposed to contact a second edge of the first cell opposite to the first edge,wherein the first edge of the first cell contacts the edge of the at least one block, andwherein the first circuit comprises a plurality of transistors respectively disposed in the first and second wells.2. The IC of claim 1 , wherein a distance between the first well and the first edge is half or more of a distance based on a well-to-well space rule.3. The IC of claim 1 , wherein the at least one block further comprises a second cell disposed adjacent to the first cell with the second edge as a boundary.4. The IC of claim 1 , wherein the first cell further comprises a second circuit configured to shift a second bit signal between the first voltage logic level and the second voltage logic level claim 1 , and the second circuit comprises a plurality of transistors ...

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Номер записи: 91
26-06-2014 дата публикации

DYNAMIC VOLTAGE SCALING SYSTEM HAVING TIME BORROWING AND LOCAL BOOSTING CAPABILITY

Номер: US20140176189A1
Автор: Wang Jinn-Shyan
Принадлежит: NATIONAL CHUNG CHENG UNIVERSITY

A dynamic voltage scaling system having time borrowing and local boosting capability, including: a time borrowing circuit and a local boost circuit. The time borrowing circuit connected electrically between a primary stage logic circuit and a secondary stage logic circuit is activated by an all-domain clock signal, and then generates an output data to the secondary stage logic circuit based on input data to the primary stage logic circuit. The local boost circuit is connected to a low working voltage line, when input data of the time borrowing circuit lags behind a positive level of said all-domain clock signal, the time borrowing circuit delays fetching data by a flip flop and changes state to produce a warning signal, so that the local boost circuit disconnects its connection with said low working voltage line, and is connected electrically to a high working voltage line. 1. A dynamic voltage scaling system having time borrowing and local boosting capability , including:a time borrowing circuit, connected electrically between a primary stage logic circuit and a secondary stage logic circuit, said time borrowing circuit receives an all-domain clock signal, and generates an output data to said secondary stage logic circuit based on input data of said primary stage logic circuit; anda local boost circuit, connected electrically to said time borrowing circuit and said secondary stage logic circuit, and is connected to a low working voltage line, wherein, when said input data lags behind a positive level of said all-domain clock signal, said time borrowing circuit changes its state to produce a warning signal, so that said local boost circuit disconnects its connection to said low working voltage line based on said warning signal, and then is connected electrically to a high working voltage line.2. The dynamic voltage scaling system having time borrowing and local boosting capability as claimed in claim 1 , wherein said local boost circuit includes a first active ...

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Номер записи: 92
16-04-2015 дата публикации

LOW POWER INVERTER CIRCUIT

Номер: US20150102839A1
Автор: CHENG Zhihong, Dey Amit Kumar, Roy Amit, Tayal Vijay, Verma Chetan
Принадлежит: Freescale Semiconductor, Inc.

A low power inverter circuit includes first and second transistors that receive an input signal at their gate terminals. The first and second transistors are connected by way of their source terminals to third and fourth transistors, respectively. The third and fourth transistors are connected in parallel with fifth and sixth transistors, respectively. The third and fourth transistors are continuously switched on, and the fifth and sixth transistors are controlled in such a way to reduce short circuit current flowing through the first and second transistors when the input signal transitions from one state to another. 1. An inverter circuit , comprising:a first transistor having a source terminal for receiving a supply voltage, and a gate terminal shorted to ground;a second transistor having a source terminal for receiving the supply voltage, and a drain terminal connected to a drain terminal of the first transistor;a first inverter, connected to the drain terminals of the first and second transistors, for receiving an input signal and generating an output signal at an output terminal;a third transistor having a drain terminal connected to the first inverter, a source terminal shorted to ground, and a gate terminal for receiving the supply voltage;a fourth transistor having a drain terminal connected to the drain terminal of the third transistor, and a source terminal shorted to ground; anda second inverter having an input terminal connected to the output terminal of the first inverter for receiving the output signal, and an output terminal connected to gate terminals of the second and fourth transistors.2. The inverter circuit of claim 1 , wherein the first inverter comprises:a fifth transistor having a source terminal connected to the drain terminals of the first and second transistors, and a gate terminal for receiving the input signal; anda sixth transistor having a drain terminal connected to a drain terminal of the fifth transistor, a gate terminal connected to ...

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Номер записи: 93
05-04-2018 дата публикации

ADAPTIVE LEVEL SHIFTER

Номер: US20180097519A1
Автор: CHOU Mao-Hsuan, Peng Yung-Chow
Принадлежит:

A level shifter operating between a first power domain under a first supply voltage and a second power domain under a second supply voltage is provided. The level shifter includes a latch, formed by a first transistor and a second transistor, configured to store data and operate in the second power domain. The level shifter further includes a third transistor configured to be biased at the first supply voltage, and a current source configured to generate a current in response to the first supply voltage. The current flows towards the latch, and the magnitude of the current is positively correlated with the first supply voltage. In response to a first asserted state of the first supply voltage, the third transistor dominates over the current source in toggling the data and, in response to a second asserted state of the first supply voltage, the current source dominates over the third transistor in toggling the data. The second asserted state is lower in voltage level than the first asserted state. 1. A level shifter for operating between a first power domain under a first supply voltage and a second power domain under a second supply voltage , the level shifter comprising: a first transistor including a bulk terminal to receive the first supply voltage, the first supply being different from the second supply voltage; and', 'a second transistor including a bulk terminal to receive the first supply voltage; and, 'a latch configured to store data and operate in the second power domain, the latch includinga third transistor configured to be biased at the first supply voltage,wherein, in response to a first asserted state of the first supply voltage, the third transistor dominates over the latch in toggling the data and, in response to a second asserted state of the first supply voltage, the latch dominates over the third transistor in toggling the data, the second asserted state being lower in voltage level than the first asserted state.2. The level shifter according to ...

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Номер записи: 94
01-04-2021 дата публикации

SEMICONDUCTOR APPARATUS PERFORMING CALIBRATION OPERATION AND A SEMICONDUCTOR SYSTEM USING THE SAME

Номер: US20210099172A1
Автор: KANG Ji Hyo
Принадлежит: SK HYNIX INC.

A semiconductor apparatus includes a calibration circuit and a main driver. The calibration circuit is configured to generate a first calibration code when set to have a positive offset and generate a second calibration code when set to have a negative offset complementary to the positive offset. The main driver is configured to set a resistance value of the main driver based on the first and second calibration codes. 1. A semiconductor apparatus comprising:a calibration circuit including a comparator configured to compare a calibration voltage and a reference voltage to generate a comparison signal, and configured to generate a first calibration code based on the comparison signal when the comparator is set to have a positive offset and generate a second calibration code based on the comparison signal when the comparator is set to have a negative offset complementary to the positive offset; anda main driver configured to set a resistance value of the main driver based on the first calibration code and the second calibration code.2. The semiconductor apparatus of claim 1 , a first input node;', 'a second input node;', 'a third input node;', 'a fourth input node;', 'first differential output nodes configured to output a first amplified signal pair by differentially amplifying signals input to the first input node and the second input node; and', 'second differential output nodes configured to output a second amplified signal pair by differentially amplifying signals input to the third input node and the fourth input node,, 'wherein the comparator includeswherein, when an offset setting signal has a first logic level, the comparator is configured to receive the calibration voltage through the first input node and the fourth input node, receive the reference voltage through the second input node and the third input node, and generate the comparison signal based on one between the first amplified signal pair and one between the second amplified signal pair, andwherein, ...

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Номер записи: 95
01-04-2021 дата публикации

INTEGRATED CLOCK GATING CELL AND INTEGRATED CIRCUIT INCLUDING THE SAME

Номер: US20210099173A1
Автор: KIM Ahreum
Принадлежит:

A clock gating cell includes an input logic/latch circuit, a keeper logic/signal generating circuit, and an output driver. The input logic/latch circuit generates an internal enable signal based on first and second input enable signals, and generates a first internal signal provided to a first node based on the internal enable signal and an input clock signal. The keeper logic/signal generating circuit is connected between the first node and a second node, includes a feedback path feeding back the first internal signal, generates a second internal signal provided to the second node based on the first internal signal and the input clock signal, and includes first and second paths discharging the second node. The first and second paths are different. The second path is connected to the feedback path. The output driver generates an output clock signal based on the second internal signal. 1. An integrated clock gating cell , comprising:an input logic and latch circuit that generates an internal enable signal based on a first input enable signal and a second input enable signal, and that generates a first internal signal provided to a first node based on the internal enable signal and an input clock signal;a keeper logic and signal generating circuit connected between the first node and a second node,wherein the keeper logic and signal generating circuit comprises a feedback path that feeds back the first internal signal, generates a second internal signal provided to the second node based on the first internal signal and the input clock signal, and further comprises a first path and a second path that discharges the second node,wherein the first and second paths are different paths, and the second path is connected to the feedback path; andan output driver that generates an output clock signal based on the second internal signal.2. The integrated clock gating cell of claim 1 , wherein the second path simultaneously performs a feedback function and a discharge function.3 ...

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Номер записи: 96
06-04-2017 дата публикации

MEMORY SYSTEMS WITH ZQ GLOBAL MANAGEMENT AND METHODS OF OPERATING SAME

Номер: US20170099050A1
Автор: CHUNG Hoiju, Han YouKeun, Kim Seokil, Lee Sang-Yeol, Shin Yongjae
Принадлежит:

A memory system includes a memory module and a memory controller. The memory module includes a plurality of memory devices with corresponding ZQ calibration circuits therein. The memory controller, which is electrically coupled to the memory module, includes a ZQ global managing circuit therein. This ZQ global managing circuit is configured to determine a plurality of calibration values associated the corresponding ZQ calibration circuits in the plurality of memory devices, in response to calibration result data generated by the plurality of ZQ calibration circuits. The memory module is mounted within a memory slot. In addition, the plurality of calibration values account for signal loading characteristics of the memory module within the memory slot. 1. A memory system , comprising:a memory module mounted on a memory slot and comprising a plurality of semiconductor memory devices each having a ZQ calibration circuit; anda memory controller configured to control the memory module,wherein the memory controller comprises a ZQ global managing circuit configured to receive calibration result data of the ZQ calibration circuit through the memory slot and to determine a final calibration value of the ZQ calibration circuit based on a signal loading characteristic of the memory slot on which the memory module is mounted.2. The memory system of claim 1 , wherein the calibration result data comprises a pull-up calibration code and a pull-down calibration code.3. The memory system of claim 1 , wherein the final calibration value is transmitted to the ZQ calibration circuit to control the ZQ calibration circuit.4. The memory system of claim 1 , wherein the calibration result data changed by the final calibration value is applied to an on-die termination operation of an on-die termination circuit.5. The memory system of claim 1 , wherein the ZQ global managing circuit comprises:a signal integrity register configured to store signal integrity information based on a signal loading ...

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Номер записи: 97
28-03-2019 дата публикации

SYNCHRONIZING A SELF-TIMED PROCESSOR WITH AN EXTERNAL EVENT

Номер: US20190097634A1
Автор: Baker David, Murtagh Paul
Принадлежит:

There is disclosed a self-timed processor. The self-timed processor includes trigger logic having a trigger input to receive an event trigger signal, a data input set to data value 1, a trigger output to send a trigger output signal when the event trigger signal is received, and a reset input to reset the trigger output signal. The processor also has a delay insensitive asynchronous logic (DIAL) block with multi-rail DIAL inputs to receive a multi-rail DIAL input having a) the trigger output signal, and b) data value 0; and data phase completion logic to output a completion signal indicating an end of a data propagate phase of the DIAL block to reset the trigger output signal when multi-rail data DIAL data process values of the DIAL block reach a DIAL valid state. 1. A self-timed processor comprising: a trigger input to receive an event trigger signal, a data input set to a data value of 1, a trigger output to send a trigger output signal when the event trigger signal is received, and a reset input to reset the trigger output signal; a delay insensitive asynchronous logic (DIAL) block having:', 'multi-rail DIAL inputs to receive at least a first multi-rail DIAL input data signal having a) a first rail input that is the trigger output signal, and b) a second rail input that is set to a data value of 0;', 'multi-rail DIAL to process at least the first multi-rail DIAL input data signal using multi-rail DIAL data process values; and', 'data phase completion logic to output a completion signal indicating an end of a data propagate phase of the DIAL block to reset the trigger output signal when the multi-rail data DIAL data process values reach a DIAL valid state., 'trigger logic having2. The self-timed processor of claim 1 , wherein the trigger logic includes a Boolean logic flip flop (FF) having the trigger input claim 1 , the data input claim 1 , the trigger output claim 1 , and the reset input; wherein the trigger input is a clock input to be triggered by a clock edge ...

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Номер записи: 98
14-04-2016 дата публикации

POWER SEMICONDUCTOR DRIVE CIRCUIT, POWER SEMICONDUCTOR CIRCUIT, AND POWER MODULE CIRCUIT DEVICE

Номер: US20160105175A1
Автор: Ando Motohiro, ISHIMATSU Yuji
Принадлежит:

A power semiconductor drive circuit includes a parallel circuit connected to a gate of a power semiconductor element and constituted by two transistors for setting gate resistance of the power semiconductor element; a gate voltage monitoring circuit connected to the gate of the power semiconductor element and the parallel circuit, wherein a monitoring voltage is set in the gate voltage monitoring circuit to monitor a gate voltage of the power semiconductor element; a signal delay circuit to delay an output signal of the gate voltage monitoring circuit; and a gate control circuit to change the magnitude of combined resistance of the parallel circuit based on an output signal output from the signal delay circuit. 1. A power semiconductor drive circuit comprising:a parallel circuit which is connected to a gate of a power semiconductor element and is constituted by at least two transistors for setting gate resistance of the power semiconductor element;a gate voltage monitoring circuit connected to the gate of the power semiconductor element and the parallel circuit, wherein a predetermined monitoring voltage is set in the gate voltage monitoring circuit in order to monitor a gate voltage of the power semiconductor element;a signal delay circuit to delay an output signal of the gate voltage monitoring circuit; anda gate control circuit to change the magnitude of combined resistance of the parallel circuit based on an output signal output from the signal delay circuit.2. The power semiconductor drive circuit of claim 1 , wherein the combined resistance of the parallel circuit is changed when the power semiconductor element is turned off.3. The power semiconductor drive circuit of claim 2 , wherein the monitoring voltage is equal to or less than a mirror voltage of the power semiconductor element.4. The power semiconductor drive circuit of claim 3 , wherein the combined resistance of the parallel circuit when the power semiconductor element is turned off is larger than the ...

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Номер записи: 99
14-04-2016 дата публикации

CLOCK BUFFERS WITH PULSE DRIVE CAPABILITY FOR POWER EFFICIENCY

Номер: US20160105177A1
Автор: Bansal Aditya, BUCELOT THOMAS J., DRAKE ALAN J., RESTLE PHILLIP J., SHAN DAVID W., Sharad Mrigank
Принадлежит:

A clock driver is provided. The clock driver includes a multi-stage delay cell having an input, a positive pulse driving branch, a negative pulse driving branch, and an output. The input is for receiving an original version of a reference clock signal input to the clock driver and used to generate a global clock signal. The output is connected to the positive pulse driving branch and the negative pulse driving branch. The clock driver further includes a pulse generator having positive and negative pulse generator portions respectively connected to outputs of the positive and negative pulse driving branches. The pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification. 1. A clock driver for an integrated circuit , comprisinga multi-stage delay cell having an input, a positive pulse driving branch, a negative pulse driving branch, and an output, the input for receiving an original version of a reference clock signal input to the clock driver and used to generate a global clock signal for the integrated circuit, the output connected to the positive pulse driving branch and the negative pulse driving branch; anda pulse generator having a positive pulse generator portion that is connected to an output of the positive pulse driving branch of the multi-stage delay cell and a negative pulse generator portion that is connected to an output of the negative pulse driving branch of the multi-stage delay cell,wherein the pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification.2. The clock driver of claim 1 , wherein the ...

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Номер записи: 100