МНОГОПОРОГОВОЕ УСТРОЙСТВО

Изобретение относится к импульсной технике и может быть использовано в системах автоматики и вычислительной техники при управлении сложными технологическими объектами, функционирующими в нечеткой обстановке. Устройство содержит N пороговых элементов, два элемента ИЛИ, элемент задержки, регулятор порога, N+1 формирователи импульсов и преобразователь позиционного кода в последовательный двоичный, или двоично-десятичный, или числоимпульсный код. Технический результат изобретения - расширение функциональных возможностей за счет вывода информации в числоимпульсном и позиционном кодах об объекте с экстремальным значением контролируемого параметра, при параллельном обслуживании совокупностей однородных объектов. Устройство обладает расширенными функциональными возможностями (имеет числоимпульсный выход, группу двухпозиционных многоразрядных выходов, группу многопозиционных многоразрядных выходов). Его входное и выходное сопротивления могут быть повышены, а выходные сигналы унифицированы применительно ...

СПОСОБ ФОРМИРОВАНИЯ МЕТОК ВРЕМЕНИ И УСТРОЙСТВО ДЛЯ ЕГО РЕАЛИЗАЦИИ

Изобретение относится к вычислительной и импульсной технике и может быть использовано в системах, использующих программно-временные устройства. Техническим результатом изобретения является упрощение способа и устройства реализации за счет снижения объема преобразуемой информации. Технический результат достигается благодаря тому, что способ формирования меток времени основан на формировании «n» последовательностей импульсов, период следования которых τi (i=1, 2, … n), для каждой следующей последовательности уменьшается в к (к - целое число) раз, формировании каждой последующей временной метки Mj (j=1, 2, … m, m - число временных меток) по истечении интервала времени Tj=pj1τ1+pj2τ2+… …+pjiτi+…+pjnτn, где pji - целое число, образовании цифрового сигнала в виде суммы импульсов тех последовательностей, которые определяют интервал времени между соседними временными метками, и формировании каждой последующей метки времени Mj в моменты времени, когда цифровой сигнал равен сумме значений цифрового ...

ADAPTIVE DEVICE FOR LOGICAL PROTECTION AGAINST JITTER IN CONTACTS

TUNED GENERATOR OF PULSES IN LEADING AND TRAILING EDGES OF INPUT SIGNAL

СПОСОБ ФОРМИРОВАНИЯ ИМПУЛЬСОВ ИЗ СИГНАЛОВ ИНДУКЦИОННЫХ ДАТЧИКОВ ЧАСТОТЫ ВРАЩЕНИЯ

Предложенное изобретение относится к измерительной технике и может быть использовано в системах автоматического измерения, управления и аварийной защиты, в состав которых входят датчики, вырабатывающие двухполярные сигналы, в частности индукционные датчики частоты вращения и расхода. Технический результат заключается в повышении помехоустойчивости, точности и надежности повторения формируемыми импульсами длительности периодов следования сигналов индукционных датчиков частоты вращения. В способе измеряют и сравнивают вольт-секундные площади двух полуволн каждого двухполярного сигнала индукционного датчика частоты вращения, причем сначала измеряют площадь S1к первой полуволны и вырабатывают пороговое значение Sпор1=Q·S1к, где Q<1, затем измеряют площадь S2 второй полуволны и в процессе измерения S2: 1) сравнивают получаемые величины S2 с Snopl и при выполнении условия S2>Sпор1 формируют требуемый импульс или 2) вырабатывают дополнительный параметр Sx=(1+Q)·S2/2, сравнивают его с Sпор1, S1к ...

УСТРОЙСТВО ДЛЯ ПРИВЯЗКИ ШКАЛ ВРЕМЕНИ

Устройство для привязки шкал времени относится к частотно-временным измерениям и имеет расширенную область применения за счет измерения величин сдвигов шкал времени при их первоначальной привязке, при условии равенства величины сдвига и времени распространения сигналов между пунктами. Устройство содержит приемники 3, 6, передатчики 4, 5, образцовые часы 1, рабочие часы 2, измеритель 8 временных интервалов, состоящий из генератора 9 тактовых импульсов, управляемого делителя 10 частоты, счетчика 11 импульсов, а также разделитель 7 сигналов, временной различитель 13, устройство 14 установки счетчика, регистратор 12, три элемента ИЛИ 16, 17, 18 и управляемый ключ 15. 7 ил.

СПОСОБ RIAA-КОРРЕКЦИИ БЕЗ ИСПОЛЬЗОВАНИЯ КОНДЕНСАТОРОВ В ЦЕПЯХ КОРРЕКЦИИ

... 1. Способ RIAA-коррекции электрического сигнала без использования конденсаторов в цепи электрической коррекции, в котором используется трансформатор с двумя вторичными обмотками, каждая их которых нагружена на резистивную цепь для формирования частотной коррекции, отличающийся тем, что в цепях вторичных обмоток трансформатора последовательно с обмотками установлены один или два дополнительных дросселя. 2. Способ RIAA-коррекции электрического сигнала по п.1, отличающийся тем, что трансформатор имеет коэффициенты передачи сигнала от первичной к каждой из вторичных обмоток меньшие единицы. 3. Способ РИАА коррекции электрического сигнала по пп.1 и 2, отличающийся тем, что дроссель, отвечающий за постоянную времени коррекции 75 мкс, выполнен в виде катушки без сердечника.

ФОРМИРОВАТЕЛЬ ИМПУЛЬСОВ ИЗ СИГНАЛОВ ИНДУКЦИОННЫХ ДАТЧИКОВ ЧАСТОТЫ ВРАЩЕНИЯ

Изобретение относится к измерительной технике и может быть использовано в системах автоматического измерения, управления и аварийной защиты. Достигаемый технический результат - повышение точности формирования импульсов для различных приложений за счет обеспечения перенастройки параметров устройства. Формирователь импульсов из сигналов индукционных датчиков частоты вращения содержит компаратор, фильтр низкой частоты RC-типа, АЦП, два ЦАП, шунтирующий резистор, транзисторный ключ, центральный процессор, цифровой компаратор, сдвиговый регистр, таймер, при этом компаратор, транзисторный ключ, АЦП, оба ЦАП, центральный процессор, цифровой компаратор, сдвиговый регистр и таймер являются встроенными компонентами микроконтроллера. 1 ил.

СПОСОБ ФОРМИРОВАНИЯ ИМПУЛЬСОВ ИЗ СИГНАЛОВ ИНДУКЦИОННЫХ ДАТЧИКОВ ЧАСТОТЫ ВРАЩЕНИЯ

Способ формирования импульсов из сигналов индукционных датчиков частоты вращения, в котором измеряют и сравнивают вольт-секундные площади двух соседних полуволн двухполярных сигналов индукционного датчика частоты вращения, причем сначала измеряют вольт-секундную площадь Sпервой полуволны, запоминают ее максимальное значение S, вырабатывают пороговое значение S=Q∙S, где Q<1, сравнивают Sс пороговым значением S, равным предельной минимальной допустимой величине вольт-секундной площади исследуемых полуволн сигналов, затем измеряют вольт-секундную площадь Sвторой полуволны, в процессе измерения сравнивают получаемые величины Sс пороговым значением S, отличающийся тем, что при выполнении условий SS, S>Sвырабатывают сигнал разрешения переключения компаратора, а переключение компаратора и сброс сигнала разрешения переключения компаратора производят при переходе входного сигнала индукционного датчика через ноль.

СЕЛЕКТОР ИМПУЛЬСОВ С ДЛИТЕЛЬНОСТЬЮ, БОЛЬШЕЙ ЗАДАННОГО ЗНАЧЕНИЯ

Селектор импульсов с длительностью, большей заданного значения, содержащий формирователь импульса сброса, отличающийся тем, что в него введены заторможенный генератор прямоугольных импульсов с нулевым временем восстановления и принудительным сбросом и конъюнктор, один вход которого соединен с инверсным выходом заторможенного генератора прямоугольных импульсов с нулевым временем восстановления и принудительном сбросом, другой вход - с выходом формирователя импульса сброса и с динамическим входом сброса по срезу поступающего импульса заторможенного генератора прямоугольных импульсов с нулевым временем восстановления и принудительным сбросом, выход конъюнктора - с выходной клеммой устройства, а выход запуска заторможенного генератора прямоугольных импульсов с нулевым временем восстановления и принудительным сбросом соединен с динамическим входом запуска по срезу поступающего импульса формирователя импульса сброса и со входной клеммой устройства.

УСТРОЙСТВО ДЛЯ ВЫДЕЛЕНИЯ ПЕРВОГО ИМПУЛЬСА ИЗ СЕРИИ

Изобретение относится к импульсной технике и может быть использовано в устройствах автоматики, измерительных приборах. Цель изобретения - упрощение устройства и повышение надежности функционирования. Поставленная цель достигается тем, что в устройство для выделения первого импульса из серии, содержащее RS-триггер, шину сигналов управления и шину серии импульсов, дополнительно введен элемент задержки, на вход которого подключена шина входной последовательности, первый и второй элементы И, на первые входы которых также подключена шина входной последовательности, на вторые входы соответственно подключен обратный и прямой выходы RS-триггера, на R-вход которого подключена шина сигнала управления, на S-вход - выход элемента И, на прямой вход которого подключен выход элемента задержки, а на вход последнего - шина входной последовательности, с выхода первого элемента И снимается серия импульсов без первого импульса серии, а с выхода второго элемента И - первый импульс серии.

Устройство для формирования одиночных импульсов

Изобретение относится к импульсной технике и может быть использовано в устройствах автоматики и вычислительной техники. Цель изобретения - расширение функциональных возможностей за счет обеспечения возможности управления задержкой начала пачки и числом импульсов - достигается введением кольцевого счетчика 2 импульсов, элементов И-НЕ 4, 5, шины 8 начальной установки кодовой шины 11. Устройство также содержит счетчик 1 импульсов, элемент И 3, RS-триггер 6, шину 7 управления, шину 9 тактовых импульсов, выходную шину 10. 2 ил.

Устройство для подавления дребезга контактов @ выключателей

Изобретение может быть использовано для устранения дребезга контактов в много- контактных пультах управления, клавиатурах Цель изобретения - повышение надежности работы - достигается путем введения в устройство n-входового двоичного счетчика 9, п-1 формирователей 11 и многовходо- вого элемента ИЛИ 12, что позволяет контролировать работу каждого выключателя даже в случае одновременной коммутации четного числа выключателей, формирующих синхронные и синфазные (пароФазные) последовательности импульсов дребезга при включении и выключении. Устройство содержит также резисторы 2,3, конденсаторы 4 D-irwepB PS-триггер 13, выключатели б Ьорг- ирователь 10 двоичный счетчик 16, шину та товых ИМПУЛЬСОВ 14 кодовые шины 15, шину 8. 2 ил.

Генератор импульсов

Способ селекции импульсов по длительности и устройство для его осуществления

Изобретение относится к импульсной технике и может быть использовано в аппаратуре обработки импульсных сигналов. Сущность изобретения: согласно способу селекции импульсов по длительности фиксируют п мгновенных значений напряжения входного сигнала через определенные интервалы времени в течение временного промежутка Т, соответствующего порогу селектируемых длительностей, сравнивают зафиксированные значения между собой и выносят решение о длительности входных импульсов по результату сравнения, интервалы времени между отсчетами выбирают переменной длительности, изменяющейся во времени по периодическому закону с частотой повторения, равной или кратной величине 1 /Т, Устройство содержит регистр 1 сдвига, функциональный генератор 2, генератор 3 синхроимпульсов, одновибратор 4, элемент И 5 с соответствующими связями. 2 с. и 1 з.п.ф-лы, 1 ил. in ...

Цифровой фильтр

Изобретение относится к радиотехнике и цифровой автоматике и может быть использовано в цифровых видео-магнитофонах, устройствах регистрации и отображения информации. Цель изобретения - повышение точности фильтрации. Цифровой фильтр содержит первый резистор 3, первый конденсатор 4, RS - триггер 5. Цель достигается введением компаратора 1, первого диода 2, второго конденсатора 6, второго резистора 7, источника 8 опорного напряжения, второго диода 9. На выходе цифрового фильтра формируется задержанная на интервал времени Τ последовательность входных импульсов и пауз без помех. Длительности импульсов уровня логической единицы на выходе фильтра равны длительностям соответствующих входных импульсов длительности сигналов уровня логического нуля на выходе фильтра равны длительностям соответствующих пауз между входными импульсами. 2 ил.

Устройство для формирования частотно-импульсных последовательностей

Синхронизирующее устройство

Селектор биполярных импульсов

Цифровой пиковый детектор

Устройство для выделения импульсов

Изобретение относится к импульсной технике. Может использоваться в устройствах автоматики, вычислительной и измерительной техники. Цель изобретения - расширение функциональных возможностей, достигается за счет разделения входной последовательности импульсов на две последовательности . Поставленная цель достигается введением новых функциональных связей. Устройство содержит тактовую 1иину 1, счетчик 2, D-триггер 3, выходные шины 5, 6 и 9, элементы И-НЕ 4 и 7, информационную шину 8. Последовательность импульсов, поступающая на информационную шину, разделяется на две последовательности импульсов , при этом на выходной шине 6 выделяется последовательность тактовых импульсов , а на шине 9 - последовательность импульсов информации. 2 ил. (Л ND 05 сд ;о 00 ...

Устройство для преобразования импульсных сигналов,сформированных механическими контактами

Изобретение относится к импульсной технике. Может использоваться в автоматических измерительных устройствах , {апример при точном преобразовании импульсных сигналов, содержащих составляющую, обусловленную дребезгом механических контактов, в импульсные сигнала без дребезга. Цель изобретения - повьщ1ение точности преобразования сигналов - достигается введением в устройство двух формирователей 6 и 7 импульсов и двух логических элементов (ЛЭ) И-НЕ8 и 9. Кроме того устройство содержит инвертор 1, входную шину 2, ЛЭ ИЛИ- НЕ 3 и 4, включенные по схеме триггера , RS -триггер 5, выходную шину 10, Существенным преимуществом данного устройства является отсутствие необходимости подачи на его вход управляющей последовательности тактовых импульсов, что позволяет сократить обьем аппаратуры. 1 ил § (/) гчэ со СП со со ...

Устройство для защиты от дребезга контактов

Изобретение относится к устройствам защиты от дребезга контактов. Предназначено для использования в системах автоматики и телемеханики. Цель изобретения - повышение надежности работы устройства. В устройство , содержащее D-триггер 4, элемент И-НЕ 5, резисторы 2,8, для достижения цели введены ключ 1, одновибра- тор 6, элемент 7 задержки, элемент ИЛИ-НЕ 3, новые связи. Устройство отличается от известного устройства . тем, что не пропускает на выход начальные импульсы дребезга с любыми длительностями, что позволяет получить положительный эффект. 2 ил. Unum. (П Фиг.1 ...

Устройство для выделения синхронизированной пачки импульсов

Изобретение может быть использовано в устройствах автоматики и вычислительной техники. Устройство содержит шину управления (1), шину синхроимпульсов (2), четыре выходные шины (З-б), два коммутатора с запоминанием сигнала управления (7 и 8), RS-триггер 9, два D-триггера (10 и 11). логический элемент И (12) с соответствующими связями. 4 ил.

Устройство регулируемой задержки видеоимпульсов

Формирователь импульсов

Изобретение относится к импульсной технике, может использоваться в устройствах дискретной автоматики и является дополнительным изобретением к авторскому свидетельству № 966878. Цель изобретения - расширение функциональных возможностей - достигается за счет формирования импульсов при длительS л №оности входных импульсов больше заданной , возможности калибровки импульсов и начальной установки формирователя импульсов во всех ре- работы. Устройство содержит D-триггеры 1 и 2, R5-триггер 3, логический элемент (ЛЭ) И-НЕ 4, ЛЭ ИЛИ 12, шины: выходные 5, 7 и 11, синхроимпульсов 6, выбора режима 8 и 9, асинхронной последовательности импульсов 10, асинхронной случайной последовательности 13, управления 14, установки режима 17, кода начальной установки 18, сброса 19, выходного кода 20. Для достижения поставленной цели в устройство введены счетчик 11мпульсов 15, ЛЭ И-НЕ 16, шины 18, 19 и 20. 1. ил. с « ел gff ...

Устройство для устранения дребезга контактов

Изобретение относится к автоматизированным и вычислительным сметемам управления и вычислительной технике. Цель изобретения - повьшзение надежности работы в условиях постоянных импульсных помех и расширение области применения устройства. Оно содержит генератор 1 импульсов, элементы ИСКЛЮЧАНШЩЕ ИЛИ «2.1,..., 2.П и счетчики 3.1, ..., З.п. Для достижения цели дополнительно введены п-1 каналов формирования, каждый из которых содержит элемент И 4.1,, ..,4,п и элемент ИСКЛЮЧАЩЕЕ ИЛИ. Импульсные помехи, проходящие через элемент ИСКЛЮЧАЮТЩЕ ИЛИ 2, не оказывают влияния на работу схемы, т.к. счетчик 3 запрещает или разрешает производить счет импульсов, поступакщих на тактовый вход С. Поэтому любая приходящая помеха всегда устаО ) навливает на его входе V сигнал, запрещающий работу счетчика на время, равное длительности этой помехи,2 ил.

Многоканальный формирователь одиночных импульсов

Изобретение может быть использовано в автоматике, вычислительной технике, контрольно-испытательных системах. Цель изобретения - повышение быстродействия и расширение функциолальных возможностей устройства . Формирователь содержит генератор 4 импульсов стабильной частоты, делитель 8 частоты, синхронизаторы 12 и 13, формирователь 14 импульсов и D-триггер 21. Введение в устройство буферных регистров 1 кода программы, регистров 3 кода-программы, парафазт- ного блока 5 захвата команды, блока 7 фазировки частоты, блока 9 синхронизации , состоящего из N канальных синхронизаторов 10. 1-10.N и 11.1-11.N, блока 16 формирования готовности, блока 18 формирования длительности цикла, элемента ЩИ 22, элемента И 23 и D-триггера 24 формирования заднего фронта обеспечивает программируемое изменение временных параметров импульсов, формируемых в каждом канале . 9 ил .. с С/) to li оо ел ...

Устройство выделения первого и пос-лЕдНЕгО иМпульСОВ B пАчКЕ

Формирователь импульсов по фронту и спаду

Изобретение относится к импульсной технике и может использоваться в устройствах автоматики и вычислительной техники Цель изобретения - повышение надежности работы за счет формирования импульсов по фронту и спаду при любой длительности входного сигнала - достигается введением элемента ИЛИ 6, первого, второго, третьего, четвертого элементов ИЛИ НЕ 7,8,9,10. В устройстве имеются первый, второй, третий триггеры 1,2,3, первый, второй элементы ИЛИ 4,5, счетчик 11 импульсов, инвертор 12, шина 13 тактовых импульсов, входная шинз 16, первая выходная шина 14, вторая выходная шина 15. 2 ил.

Устройство выделения экстремумов сигнала

Изобретение может быть использовано при построении анализаторов функций распределения экстремумов. Цель изобретения - повьппение точности вьщеления экстремумов сигнала. Устройство содержит аналого-цифровой преобразователь 1,регистр памяти 2, цифровой компаратор 3,формирователи 6 и 7 импульсов и элемент ИЛИ 8.Введение D-триггеров 4 и 5 и образование новых функциональных: связей повышает точность вьзделения экстремумов сигнала путем повышения быстродействия ...

Устройство защиты от дребезга

Изобретение относится к импульсной технике. Цель - повышение надежности в работе за счет упрощения устройства . Устройство для защиты от дребезга содержит мажоритарный элемент 1, входную и выходную шины 2,3. Цель достигается тем, что в него введены инвертор и элемент 5 задержки (в простейшем случае - интегрирующая RC-цепочка), которая осуществляет задержку инвертированного выходного сигнала на время, заведомо большее времени переходного процесса при формировании фронта и среза сигнала, например времени дребезга механических контактов при их переключении. Устройство может быть использовано в системах обработки и формирования с импульсных сигналов. 2 ил. « ...

Пороговое устройство

Устройство регулирования уровня квантования

Переключатель

Переключатель относится к импульсной технике и предназначен для формирования на одном из двух выходов тех импульсов, передний фронт которых пришел первым во времени. Переключатель содержит транзисторы 1-4, диоды 5,6, резисторы 8-13. входные шины 14, 15 и выходные шины 16, 17. 2 ил.

Формирователь импульсов

Устройство для контроля наличия п-информационных сигналов

Изобретение относится к автоматике и вычислительной технике и может быть использовано в устройствах коммутации сигналов электрических цепей, содержащих электромеханические контакты. Целью изобретения является повьшение достоверности контроля.Устройство содержит селектор 1 импульсов по длительности, логические элементы ИЛИ-НЕ 2, И-НЕ З и И-НЕ 7, триггер 4, выключатели 5, инверторы 6, резисторы 8. При этом селектор 1 вьшолнен на инверторах 9-12 и конденсаторе 13, а триггер 4 - на элементах И-НЕ 14 и 15. Устройство обесп ечивает вьтолне- ние функции контроля наличия п-инфор- мационных сигналов, контролирует наличие информационной полноты о работе первичного п-канального сигнального устройства, что повышает достоверность контроля. На выходах элементов И-НЕ 7 устройством формируются нормализованные сигналы без дребезга как при замыкании, так и при размыкании контактов выключателя 5. 1 ил. (Л ...

Формирователь импульсов

Изобретение относится к импульсной технике и может быть использовано в программно-временных устройствах, предназначенных для формирования синхронных импульсных последовательностей в пространственно разнесенных устройствах, имеющих систему единого времени. Цель изобретения - повышение точности синхронизации путем привязки значащих моментов формируемых импульсов к текущему времени - достигается введением формирователя 13 кодов, стробируемого элеме. 1та 14 сравнения кодов, шины 8 импульсных меток шкалы времени, шины 9 кода времени начального пуска, шины 10 сигнала записи кода времени начального пуска, шины 11 кода периода, шины 12 кода текущего времени. Устройство также содержит генератор 1 импульсов , счетчик 2 импульсов, RS-триггер З, элемент ИЛИ 4, шину 5 начальной установки , шину б кода длительности импульса, выходную шину 7. 3 з,п. ф-лы, 4 ил. И СО ю ел ...

Устройство для синхронизации контрольного и эталонного цифровых измерительных сигналов

УСТРОЙСТВО ДЛЯ СИНХРОНИЗАЦИИ КОНТРОЛЬНОГО И ЭТАЛОННОГО ЦИФРОВЫХ ИЗМЕРИТЕЛЬНЫХ СИГНАЛОВ, содержащее генератор эталонного сигнала, информационный вход которого подключен к выходу блока переключения , тактовый вход генератора эталонного сигнала подключен к выходу блока выделения тактовой частоты, а выход генератора эталонного сигнала соединен с первым входом блока переключения и с первым входом блока несовпадения, второй вход которого подключен к входной шине, к входу блока выделения тактовой частоты и ко второму входу блока переключения, третий вход которого подключен к выходу синхрогенератора , а также первый накопитель, отличающееся тем, что, с целью повышения помехоустойчивости и расширения диапазона рабочих частот, в него введены четыре элемента И, два триггера, второй накопитель и регистр сдвига, тактовый вход которого подключен к первому входу первого элемента И, первому входу второго элемента И, к выходу блока выделения тактовой частоты и к счетному входу синхрогенератора, вход управления ...

Устройство временной привязки

Изобретение может быть использовано для точной фиксации временного положения электрических сигналов. Цель изобретения - повышение точности вре менной привязки - достигается введением в устройство генератора 8, схемы 14 совпадений, управляемого вентиля 15 и элемента ИЛИ 200 Устройство содержит также шину 3 начальной установки , дискриминаторы 4, 5, генераторы 6, 7, счетчик 19, входную и выходную шины 1 и 2 соответственно, элемент ИЛИ 18. 2 ил о ...

Устройство для допускового контроля временных интервалов

Селектор импульсов

Устройство синхронизации мультивибратора

Селектор импульсов по длительности

Цифровая регулируемая линия задержки

Изобретение относится к вычислительной и измерительной технике и может быть использовано в устройствах автоматики. Цель изобретения - расширение функциональных возможностей за счет динамического изменения задержки и заданного изменения длительности выходного сигнала. Это достигается введением в устройство элемента И - НЕ 6, регистра 7, шины 10 начальной установки с соответствующими связями. Цифровая регулируемая линия задержки содержит также генератор 1 тактовых импульсов, первый элемент И 2, первый счетчик 3, второй элемент И 4, второй счетчик 5, кодовые шины 8, входную шину 9 и выходную шину 11. В предлагаемом устройстве обеспечивается возможность формирования выходного импульса с различным временем задержки посредством динамического асинхронного изменения кода задержки на кодовых шинах 8. Кроме того, при длительности входного импульса меньше программного задаваемого времени задержки обеспечивается возможность заданного изменения длительности выходных импульсов Tвых= Tвх/M, где Tвых, ...

Формирователь одиночных импульсов

Устройство для формирования одиночного импульса

УСТРОЙСТВО ДЛЯ ФОРМИРОВАНИЯ ОДИНОЧНОГО ИМПУЛЬСА, содержащее первый тактируемый динамический триггер, информационный вход которого соединен с шиной управляющих сигналов , а выход подключен к информационному входу второго тактируемого динамического триггера, выход которого соединен с одним из входов первого элемента И, выход которого через элемент ИЛИ подключен к информационному входу третьего тактируемого динамического триггера, прямой выход которого через второй элемент И соединен с вторым входом элемента ИЛИ, при этом инверсный выход третьего тактируемого динамического триггера соединен с вторым входом первого элемента И, выход которого соединен с выходной шиной, а управляющий вход приема информации первого, второго и третьего триггеров соединен с шиной синхроимпульсов, .отличающееся тем, что, с целью повышения помехозащищенности и надежности устройства, в него дополнительно введены тактируемьй динамический триггер и элемент И, входы которого соединены с шиной управляющих сигналов и выходом ...

Формирователь напряжения

Устройство для выделения одиночного импульса

Устройство обработки импульсов

УСТРОЙСТВО ДЛЯ ВЫДЕЛЕНИЯ ИМПУЛЬСОВ В ПАЧКЕ

Устройство для обнаружения потери импульса

УСТРОЙСТВО ДЛЯ ОБНАРУЖЕНИЯ ПОТЕРИ ИМПУЛЬСА, содержащее элемент задержки, элемент ИСКЛЮЧАЮЩЕЕ ИЛИ, элемент И и триггер, причем выход элемента задержки соединен с первыми входами элемента ИСКЛЮЧАЮЩЕЕ ИЛИ и элемент И, второй вход которого подключен к выходу элемента ИСКЛЮЧАЮЩЕЕ ИЛИ, второй вход которого соединен с входом элемента задержки и с входной шиной, отличающееся тем, что, с целью расширения функциональных возможностей устройства, в него введен элемент ИЛИ, первый вход которого подключен к входу элемента задержки и к первому входу триггера, второй вход которого соединен с выходом элемента И и с вторым входом элемента ИЛИ.

Реле времени

Изобретение относится к автоматике и импульсной технике и может быть использовано в аппаратуре различного назначения, например в программно-временных устройствах,Целью СИ изобретения является повышение помехозащищенности реле времени при сохранении его точности. Реле времени содержит блок 1 управления, элементы ИЛИ 2 и 10, интегратор 3, пороговый элемент А, инверторы 5 и 8, элемент ИЛИ-НЕ 6, элементы И 7, 9 и 12,триггер 11, генератор 13, счетчик 14 импульсов , дешифратор 15, входную шину 16 и выходную шину 17, Предлагаемое реле времени позволяет формировать выходной сигнал с высокой точностью временной задержки и может быть использовано в системах с высоким уровнем помех. Возможная реализация блока управления приводится в описании изобретения, 5 ил. i (Л II 00 to О) о СХ) ...

Формирователь импульсов

Способ формирования частотно-импульсных сигналов датчика перемещения и устройство для его осуществления

Устройство для формирования синхроимпульсов

Устройство для измерения экстремумов временных интервалов

Изобретение относится к измерительной технике и может быть использовано в цифровых измерительных приборах и системах. Цель изобретения - расширение функциональных возможностей устройства. Устройство содержит генератор 1 тактовых импульсов , блок 2 синхронизации, счетчик 3, блок 4 сравнения, регистр 5 и блок 9 индикации. В устройство введен блок 16 запуска, включающий триггеры 22 и 23, элемент И 24, инвертор 25 и кнопку 26 Сброс. Блок 2 синхронизации содержит триггеры 17 и 18, элементы 20 и 21 задержки. Введены также регистр 7, блок 8 сравнения, элементы ИЛИ 10 и 11, элементы И 12-14 и триггер 15. Введенные элементы и образование новых функциональных связей дают возможность измерять абсолютные экстремальные значения временных интервалов. 2 з.п. ф-лы. 2 ил. (Л с to 00 00 00 ...

Полупроводниковая линия задержки

Дискриминатор временного интервала

Формирователь импульсов

Стробируемый формирователь

Формирователь временных интервалов

Устройство для синхронизации импульсов

Генератор синхроимпульсов

Устройство для задержки электрических импульсов

Бинарный амплитудно-временной квантователь

Устройство для регулирования уровня квантования

Устройство блокировки импульсного сигнала

Изобретение относится к импульсной технике и может быть использовано в устройствах автоматики для блокировки импульсного сигнала на входе ждущего генератора или счетчика команд программного устройства. .Целью изобретения является повышение надежности работы устройства и достоверности выходного сигнала. Устройство содержит элементы ИЛИ 1 и 2, Т-триггер 3, элемент И 4, элемент НЕ 5, входные шины 6 и 7, шину 8 начальной установки и выходную шину 9. В устройстве обеспечивается снятие уровня логической единицы с выходной шины 9 по заднему фронту первого импульса, поступившего на первую входную шину 6 после снятия сигнала бло- кщ)овки с второй входной шины 7. Вместо Т-триггера может быть использован асинхронный RS-триггер. Однако это наложит временные ограничения на вы-sg дачу сигналов начальной установки на время работы устройства. 2 ип. Сп с: ...

Устройство задержки импульсов

SYNC PULSE SHAPER

DEVICE FOR SELECTING SINGLE PULSE

Устройство для синхронизации измерительных последовательностей импульсов

Устройство формирования импульсов синхронизации

Устройство для получения разности частот двух импульсных последовательностей

Устройство обнаружения экстремума сигнала

Устройство для формирования импульсов переменной частоты

Устройство для преобразования импульсов

Изобретение относится к области импульсной техники и может быть использовано в устройствах для преобразования малых стохастических импульсов напряжения с различной шининой импульса в длительный сигнал. Устройство содержит усилитель 1, кондетша- тор 2, пороговый переключатель 4, .блок 3 задержки, входную и выходную шины. Лороговый переключатель 4 может быть выполнен в виде триггера Шмитта или компаратора. Устройство имеет расширенный диапазон длительностей входных импульсов и просто в конструкции, 2 ил.

Устройство для формирования одиночных импульсов

Сущность изобретения: устройство содержит счетчики 1, 2 импульсов, триггеры 3. 4, элементы И-НЕ 5, 6. элемент И 7. шину 8 тактовых импульсов, шину 9 управления, шину 10 начальной установки, кодовые шины 11, 12, выходную шину 13. 2 ил.

Устройство для формирования одиночного импульса

Сущность изобретения: устройство содержит 4 RS-триггера 1,4,7,10,5 элементов И-НЕ 13, 14, 15, 16, 17, инвертор 18, шину тактовых импульсов 19, шину сигналов управления 20, выходную шину 21 с соответствующими связями. 3 ил.

Цифровая регулируемая линия задержки

Изобретение относится к вычислительной и измерительной технике и может быть использовано в устройствах автоматики. Цель изобретения - повышение надежности устройства. Для этого в устройстве, содержащем генератор 1 тактовых импульсов, элементы И 2 и 4, счетчики (С) 3 и 5, первый вход элемента И 4 соединен с выходом генератора 1 тактовых импульсов. Управляющий вход С 3 и выход заема С 5 подключены соответственно к входной и выходной шинам 6 и 8. Управляющий вход С 5 соединен с выходом заема С 3 , а их информационные входы объединены и подключены к кодовым шинам 7. 2 ил. IND СО о t со ФигЛ ...

Формирователь импульсов

Изобретение может быть использовано в устройствах автоматики и вычислительной техники и позволяет повысить надежность работы формирователя . Устройство содержит триггеры 1... 3 и элемент И-НЕ 4. Введение элемента И-НЕ 5, элемента И 6, инвертора 7 позволяет формирователю в режиме синхронизатора приходить в устойчивое состояние до поступления очередного отрицательного импульса на входную шину 12. При этом исключается выдача ложных сигналов и осколков на выходную шину II, а длительность полезного сигнала на последней строго соответствует длительности сигнала на шине 10 тактовых импульсов. 1 ил. ЕЬ (Л 1Г ...

Устройство для корректировки числа импульсов по переменному параметру

Устройство для исключения влияния дребезга контакта

Устройство для исключения влияния дребезга контакта содержит механический контакт 1, резисторы (Р) 2, 8, 9 и 11, конденсаторы 3 и 12, подвижный контакт 4, исполнительное реле 5, ключевой транзистор 6, RS-триггер 7 и диод 10. Введение Р 8 и 9 и новых электрических связей между функциональными элементами расширяет область использования устройства и повышает надежность его работы. 2 ил. + (Л со О со ьо 00 со и,г.1 ...

Устройство бездребезгового ввода сигналов от контактных клавиатур

Изобретение может быть использовано в устройствах автоматики, телемеханики и вычислительной техники. Цель изобретения - повышение надежности устройства путем его упрощения. Устройство содержит элемент ИСКЛЮЧАЮЩЕЕ ИЛИ 2, резисторы 5-1,...,5-К и D-триггеры 6-1,...,6-К. Введение элементов И 1 и 4 и одновибратора 3 позволяет уменьшить число элементов ИСКЛЮЧАЮЩЕЕ ИЛИ и упростить элемент формирования импульса записи в D-триггеры . 2 нл. h со со vi ...

Устройство задержки импульсов

Изобретение может быть использовано в радиоэлектронной и измерительной аппаратуре и позволяет расширить функциональные возможности устройст- -ва задержки импульсов. Устройство содержит формирователь 2 импульсов, Т-триггер 5, элементы И 8-11, одно18 вибраторы 12 и 13 и элемент ИЛИ 14. В устройство введены элемент ИЛИ 18, элементы И 19 и 20, одновибраторы 21 и 22 Н формирователи 23 и 24 импульсов по срезу. Это позволяет по окончании входной серии импульсов Т-триг- гер 5 перебрасывать дополнительно сформированным импульсом, фронт которого соответствует временному положению следующего тактового импульса синхронизации, в соответствии с которым сформирована входная серия импульсов . Это исключает возможность потери последнего импульса серии, т.е. возможность искажения входной информации, а также позволяет производить задержку одиночных импульсов на время, равное тактовому интервалу. 2 ил. с (Л С 13 21 12 гз 10 г- tn 4 Г7 ОО СО 00 о. со 70 И 22 П 24фие ...

Формирователь импульсов

Изобретение относится к импульсной технике и может быть использовано в устройствах обработки импульсных сигналов. Цель - повышение точности за счет уменьшения отставания выходного импульса относительно входного. Формирователь импульсов содержит входную шину 1, D-триг- гер 2, счетчик 3, шину 4 тактовых импульсов , блок 5 сравнения чисел, одно- вибратор 6 и выходную шину 7. 2 ил. O § (Л я 1МВ С тз Вь/х. 7 СО СО ьо 05 4 ФигЛ ...

Устройство для синхронизации генератора развертки

УСТРОЙСТВО СИНХРОНИЗАЦИИ ГЕНЕРАТОРА РАЗВЕРТКИ, содержащее триггер запуска, первый вход которого соединен с входной шиной, первый выход соединен с входом элемента задержки и перзьм входом триггера блокировки , отличающееся тем, что, с целью повьшения надежности работы устройства, в него введены второй элемент эадержки и элемент ИЛИ, первый вход которого соединен с вторьм выходом триггера запуска, второй вход - с выходом триггера блокировки, второй вход которого соединен с выходом второго элемента задержки, вход которого соединен с первьм входом триггера запуска, второй вход которого соеди§ нен с выходом первого элемента эадержки .

Формирователь импульсов

Формирователь импульсов

Изобретение относится к импульсной технике и может быть использовано в устройствах автоматики и вычислительной техники. Цель изобретения - расширение функциональных возможностей - достигается путем дополнительного формирования парных одиночных импульсов. Формирователь импульсов содержит триггеры 1,2 и 3, вентили 4 и 5, шину 6 тактовых импульсов, шину 7 управления, выходные шины 9÷11. Второй и третий триггеры выполнены JK-типа с соответствующими функциональными связями между ними. В качестве первого триггера использован триггер D-типа. 1 ил.

Устройство задержки прямоугольных импульсов

Устройство выделения сигнала

Изобретение относится к области электро- и радиотехники и может быть использовано при выделении сигнала с заданными частотными и амплитудными признаками на фоне помех и шумов. Цель изобретения - повышение точности и помехоустойчивости. Устройство содержит пороговый элемент 6, запоминающий элемент 7 (например, Д-триггер). Введение парафазного усилителя 2, дополнительного порогового элемента 3, блока 4 задержки и элемента И 5 позволяет резко повысить помехоустойчивость за счет реализации дополнительной функции сверхузкополосного фильтра и организации встречного движения сигналов на входах порогового элемента, что дополнительно повышает точность срабатывания устройства. 2 ил.

Формирователь импульсов

Изобретение относится к цифровой технике и может быть использовано при построении устройств первичной обработки радиолокационной информации. Цель изобретения - повышение надежности - достигается за счет исключения пропусков в обработке входных сигналов в случае появления их смежных интервалах временного квантования. Формирователь импульсов содержит элемент И 1, Д - триггеры 2, 3, входную шину 5, шину 6 тактовых импульсов. Введение Д - триггеров 7, 8, счетного триггера 9, элемента ИЛИ 10 обеспечивает за счет поочередного (через такт) управления работой каждой из двух пар Д - триггеров временной синхронизации и элемента ИЛИ исключение пропусков обрабатываемых импульсов превышения порога при их нахождении в смежных интервалах временного квантования, что повышает достоверность работы. 2 ил.

Устройство для выделения тактового импульса

Изобретение может использоваться в устройствах автоматики, вычислительной и измерительной техники. Цель изобретения - повышение надежности функционирования - достигается за счет введения двух формирователей 3 и 4 коротких импульсов низкого уровня. Очередной входной импульс на шину 2 может поступать до окончания формирования выходного импульса на выходе триггера 6. Триггер 5 устанавливается в нулевое состояние фронтом импульса с шины 1 после начала формирования выходного импульса на шине 7. Приведен пример электрической функциональной схемы устройства, выполненного на элементах И-НЕ. 2 ил.

Реле времени

Изобретение может быть использовано в аппаратуре различного назначения, например в программно-временных устройствах. Цель изобретения - расширение области применения за счет использования реле в условиях интенсивных помех. В реле времени введены ключ 6 и элемент 10 с соответствующими связями. В состав реле входят также генератор 1 импульсов, блок 2 управления, элемент ИЛИ 3, интегратор 4, пороговый элемент 5, элемент НЕ 7, элементы И 8,9, триггер 11, элемент 2И-2 ИЛИ 12, счетчик 13 импульсов, дешифратор 14. Изобретение исключает сбои при поступлении помех на этапе подготовки реле к работе. Кроме того, отпадает необходимость регулировочных работ при практической реализации устройства. 5 ил.

Устройство для устранения дребезга контактов

Изобретение может быть использовано в автоматике, телемеханике и вычислительной технике для защиты от дребезга контактов механических переключателей. Цель изобретения - повышение надежности за счет исключения сбоев в условиях постоянных импульсных помех - достигается за счет введения в каждый из N каналов формирователей счетного триггера 4. Устройство содержит также генератор 1, элементы ИСКЛЮЧАЮЩЕЕ ИЛИ 2 и двоичные счетчики 3. 2 ил.

Устройство временной привязки

Изобретение относится к импульсной технике и предназначено для расширения динамического диапазона длительностей входного сигнала устройства временной привязки и повьшения точности работы устройства. Цель изобретения достигается за счет введения элементов ИЛИ 6 и 7 и новых функциональных связей. Помимо перечисленных элементов устройство содержит дискриминатор 3 верхнего уровня, дискриминатор 4 нижнего уровня, RS- триггеры 8 и 9, генераторы 10 и 11 тока, формирователь 12 импульсов и диод 13 с накоплением заряда. За счет введенных элементов и связей достигается исключение в устройстве линии задержки, что повышает точность работы устройства за счет устранения влияния искажений задержанного сигнала . Одновременно снимаются ограничения на длительность входного сигнала, накладываемые линией задержки. 2 кл. (Л ...

Формирователь одиночных импульсов

Устройство для синхронизации импульсов

Изобретение относится к импульсной технике и может быть использовано в устройствах обработки импульсной информации. Устройство содержит генератор 1 импульсов, группу 2 элементов И, синхронизатор 3, регистры 4, 5. 6, элемент ИЛИ 7. группу 8 элементов сравнения, элементы 9, 10 сравнения, счетчики 11, 12 импульсов, элемент И 13, триггер 14. дешифратор 15. группу 16 счетчиков, входную шину 17, кодовые шины 18, 19. установленные установочные шины 20. выходные шины 21. 22 о соответствующими связями. 1 ил.

Устройство защиты от дребезга контактов

Использование: устройства клавишного ввода информации в ЭВМ. Сущность: устройство содержит 3 одновибратора (1, 2, 3), 2 триггера (4, 5), 1 элемент И (6). 1-5-4, 2-6-4, 3-6. 3 ил.

Устройство для выделения первого и последнего импульсов в пачке

УСТРОЙСТВО ДЛЯ ВЫДЕЛЕНИЯ ПЕРВОГО И ПОСЛЕДНЕГО ИМПУЛЬСОВ В ПАЧКЕ , содержащее первый элемент И, один из входов которого соединен с входной шиной, а другой вход подключен к шине тактовых иьшульсов и первым . входам второго и третьего элементов И, выход первого из которых соединен с первой выходной шиной, а второй вход подключен к выходу триггера и второму входу третьего элемента И, третий вход которого через элемент Н соединен с выходом первого элемейта И, -а выход третьего элемента И подкл чен к второй выходной шине и первому входу первого элемента ИЛИ, второй вход которого соединен с третьей выходной шиной, а выход череэ формирователь импульсов подключен к четвертой выходной шине, а также второй элемент ИЛИ, отличающееся тем, что, с целью расширения частотного диапазона устройства, в него дополнительно введены два элемента И, триггер и злетлент ИСКЛЮЧАЮОШЕ ИЛИ, один из входов которого соединен с второй выходной шиной, а другой подключен к третьей выходной шине и выходу первого дополнительного ...

Rfid access method using an indirect memory pointer

A method of operating a memory in an RFID application includes locating a memory pointer at a fixed read/writeable memory location in the memory, determining a range of a pedigree buffer, initializing the memory pointer to a lowest value in the range, providing a second memory location that serves as a trigger address for an indirect write, and writing to a next location in the pedigree buffer by directing write data to the trigger address, which is then automatically written at a location pointed to by the memory pointer.

Circuit with passive components for high-speed drive of an optoelectronic device

A circuit for the ultra-quick control of an optoelectronic device, includes a generator of voltage pulses having a pulse duration of less than 400 ps, and a circuit ( 17 ) for shaping control pulses including: an output suitable for being connected in series to a line terminal ( 13 ) of the optoelectronic device, and an input connected to the voltage-pulse generator and receiving the voltage pulses formed by the latter, between a terminal of the input and a terminal of the output, mounted in parallel in relation to one another: a first branch ( 20 ) made up of a passive rectifier circuit ( 22 a, 22 b ) having non-zero threshold voltage and, in series in the first branch in forward direction relative to the line terminal ( 13 ) of the optoelectronic device, a second capacitive branch ( 21 ).

Clock generation circuit, display device drive circuit, and control method of clock generation circuit

A clock generation circuit that can reliably recover from a state in which generation of a clock is stopped even during a power-on process and a normal operation. The clock generation circuit includes a clock extraction circuit that extracts an extracted clock from an embedded signal on which a clock and data are superimposed, and a stop detection circuit that detects a stop of the extracted clock on the basis of the embedded signal and the extracted clock and outputs a reset signal that resets the clock extraction circuit to an initial state.

Sample and hold circuit and the method thereof

A sample and hold circuit and the method thereof are disclosed. The sample and hold circuit may be applied in voltage regulators or other circuits. The sample and hold circuit comprises: an input terminal configured to receive an input signal; an output terminal configured to provide an output signal; a control circuit configured to receive the input signal and the output signal, and wherein based on the input signal and the output signal, the control circuit generates a digital signal, and wherein the digital signal increases when the output signal is lower than the input signal, and maintains when the output signal is larger than or equal to the input signal; a digital-to-analog converter (DAC) configured to convert the digital signal to the output signal.

Active clamp circuit

According to one embodiment, an active clamp circuit includes a first switch element, a first diode, a first resistance, a first control circuit and a second control circuit. The first diode is connected to the first switch element and breaks down by an overvoltage applied to the first switch element. The first resistance is connected to the first diode and detects a current through the first diode. The first control circuit is configured to amplify a voltage across the first resistance and controls a current through the first switch element. The second control circuit is configured to control a conduction of the first switch element in accordance with the voltage across the first resistance.

Power analysis module for monitoring an electrical power source

A method of analyzing the characteristics of a power source includes receiving a power source having at least one phase and sensing voltage signals of each phase of the at least one phase. The method includes detecting a zero crossing event of a selected phase of the at least one phase based on the sensed voltage signals of the selected phase. The method also includes determining, using a processor, voltage information for each phase of the at least one phase based on the corresponding sensed voltage signals. The method further includes outputting a series of pulses via a galvanic isolator in response to the zero crossing event. Respective lengths of some or all of the pulses in the series are based on the corresponding voltage information for each of the at least one phase.

INPUT BUFFER CIRCUIT OF SEMICONDUCTOR APPARATUS

The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal. 1. An input buffer circuit of a semiconductor apparatus , comprising:a bias voltage level control unit configured to output a control bias voltage by decreasing a bias voltage, when a level of the bias voltage becomes higher than a target level;a first buffering unit configured to generate a compare signal by comparing a voltage level of an input signal with a level of a reference voltage, when being activated by receiving the control bias voltage; anda second buffering unit configured to generate an output signal by comparing the voltage levels of the input signal and the compare signal.2. The input buffer circuit of a semiconductor apparatus according to claim 1 , wherein the bias voltage level control unit outputs the bias voltage as the control bias voltage claim 1 , when the bias voltage level is lower than the target voltage level.3. The input buffer circuit of a semiconductor apparatus according to claim 2 , wherein the bias voltage level control unit includes:a level detector configured to generate a detection signal by detecting the bias voltage level;a voltage dropper configured to generate a down voltage by decreasing the bias voltage; anda selector configured to selectively output the bias voltage or the down voltage as the control bias voltage, in response to the detection ...

CONTROL OF INPUTS TO A MEMORY DEVICE

A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode. 1. A semiconductor integrated circuit device comprising:a command decoder configured to control a memory system by decoding a memory system input signal;interface logic electrically coupled to the command decoder and configured to receive the memory system input signal and a control signal, the interface logic further configured to disable the memory system input signal based at least in part on the control signal;self-refresh logic configured to provide a self-refresh signal based at least in part on an external clock enable signal, the control signal based at least in part on the self-refresh signal; anda path-gate electrically coupled to the self-refresh logic and configured to receive the external clock enable signal and provide the external clock enable signal to the self-refresh logic, the path-gate receiving power from a main voltage generator and a secondary voltage generator in the event that the main voltage generator powers off.2. The semiconductor integrated circuit device of wherein the main voltage generator is configured to provide a generator state signal indicating a voltage level of the main voltage generator.3. The semiconductor integrated circuit device of wherein the control signal is based at least in part on the self refresh signal and the generator state signal.4. The semiconductor integrated circuit device of wherein the control signal causes the interface logic to disable the memory system input signal when the main voltage generator ...

GATE DRIVER ON ARRAY, SHIFTING REGESTER AND DISPLAY SCREEN

The embodiment of the present disclosure relates to a technical field of liquid crystal display, and particularly, to a gate driver on array, a shifting register and a display screen. The gate driver on array comprises: a first TFT, a second TFT, a third TFT, a fourth TFT, a capacitor and a pulling-down module, the pulling-down module is connected among a first clock signal input terminal, a second clock signal input terminal, a first node and an output terminal, and is connected with a low voltage signal terminal, for maintaining the first node and the output terminal being in a low level during a non-operation period of the gate driver on array. Thus, the gate driver on array may achieve a bidirectional scan by designing the functions of the input terminal and the reset terminal in the gate driver on array as being implemented symmetrically, without changing a charging-discharging characteristic of nodes, which ensures a reliability and stabilization of the circuit. 1. A gate driver on array , comprising:a first thin film field effect transistor TFT, a gate of which is connected with an input terminal of the gate driver on array, a drain of which is connected with a power supply voltage terminal VDD, and a source of which is connected with a first node being a pulling-up node;a second TFT, a gate of which is connected with a reset terminal of the gate driver on array, a source of which is connected with a common connection voltage terminal VSS, and a drain of which is connected with the first node;a third TFT, a gate of which is connected with the first node, a drain of which is connected with a first clock signal input terminal, and a source of which is connected with an output terminal;a fourth TFT, a gate of which is connected with a second clock signal input terminal, a drain of which is connected with the output terminal, and a source of which is connected with a low voltage signal terminal;a capacitor which is connected between the first node and the output ...

Peak Detector with Extended Range

According to one embodiment, a peak detector having extended dynamic range comprises a first differential output coupled to a supply voltage of the peak detector by a first load and coupled to ground by first and second switching devices, and a second differential output coupled to the supply voltage by a second load and coupled to ground by third and fourth switching devices. The control terminals of the first, second, third, and fourth switching devices receive a common bias voltage, and the respective first and second control terminals are configured as differential inputs of the peak detector. In some embodiments, corresponding first power terminals of the first and second switching to devices share a first common node further shared by the first differential output, and corresponding first power terminals of the third and fourth switching devices share a second common node further shared by the second differential output.

MEMORY SYSTEM AND DATA TRANSMISSION METHOD

A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade. Between the DRAMs and the buffer on the memory module, high-speed data transmission is implemented using data phase signals synchronous with clocks. 1. A memory system comprising:a substrate;a plurality of memory chips mounted over the substrate, the plurality of memory chips receiving a first signal and a second signal;a memory buffer mounted over the substrate, the memory buffer including a detection circuit which detects a skew between the first signal and the second signal, and the memory buffer including an adjustment circuit which adjusts a relationship between the first signal and the second signal based on the skew.a first wiring configured to commonly couple each of the plurality of memory chips for transferring the first signal to the each of the plurality of memory chips in common; anda plurality of second wirings corresponding with the plurality of memory chips, each first end of the plurality of second wirings configured to couple to an associated one of the plurality of memory chips independently for transferring the second signal to an associated one of the plurality of memory chips.2. ...

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME

A semiconductor memory device includes first and second write driving blocks to perform a data write operation on first and second memory banks in response to first and second bank strobe signals, respectively, and a common input driving block to transmit data to the first and second write driving blocks through a common data line in response to access information of the first and second memory banks. 14-. (canceled)5. A semiconductor memory device , comprising:first and second memory banks each of which includes a plurality of sub-memory banks corresponding to data width option information;a plurality of write driving blocks each of which performs a data write operation on each of the sub-memory banks in response to a first or second bank strobe signal;a control signal generating block to generate a plurality of input control signals dependent on access information of the first and second memory banks the data width option information; anda plurality of common input driving blocks each of which transmits data through a common data line to a write driving block, among the plurality of write driving blocks, for each of the first and second memory banks, wherein the plurality of common input driving blocks are activated in response to the plurality of input control signals.6. The semiconductor memory device of claim 5 , wherein enable periods of the plurality of input control signals are defined by enable periods of the first and second bank strobe signals.7. The semiconductor memory device of claim 5 , wherein the first and second memory banks are stacked with each other.8. The semiconductor memory device of claim 5 , wherein the access information of the first and second memory banks corresponds to the first and second bank strobe signals.9. The semiconductor memory device of claim 5 , wherein the common data lines are disposed to cross one of the first and second memory banks.10. The semiconductor memory device of claim 5 , further comprising an activation signal ...

Power quality monitoring apparatus and method thereof

The present invention includes a calculating unit for calculating an absolute value of an applied commercial voltage, an accumulating unit for accumulating the absolute value of the applied commercial voltage per a constant period to output, an extracting unit for sampling an absolute value accumulative maximum value of the commercial voltage for each period and a determining unit for determining a quality of the commercial voltage by using the absolute value accumulative maximum value of the sampled commercial voltage. It has an advantage that the power quality can be monitored at high speed.

PEAK VOLTAGE DETECTOR AND RELATED METHOD OF GENERATING AN ENVELOPE VOLTAGE

A peak detector circuit receives an oscillating power supply signal. A capacitor is selectably coupled to the signal and charged to a value corresponding to a peak value of the signal. A switch is then opened to isolate the capacitor. A comparator continually compares the signal with the value stored on the capacitor. When the signal rises to within a selected threshold, relative to the stored value, the comparator produces a command signal to close the switch, again coupling the capacitor to the signal. The peak detector can also include a tracking circuit that controls the capacitor to track the oscillating signal while the switch is closed, a timer circuit configured to close the switch and activate the tracking circuit if more than a selected time passes without production of a command signal, and a circuit configured to control the polarity of a leakage current of the capacitor. 1. An integrated detector of peaks of an oscillating voltage , comprising:a rectifying circuit, having an input and an output, configured to generate an rectified voltage at the output corresponding to an oscillating voltage at the input;an integrated capacitor configured to store an envelope voltage representing a last detected peak value of the oscillating voltage;a first switch configured to electrically couple said integrated capacitor to the output of the rectifying circuit when the first switch is closed, and to isolate the integrated capacitor from the rectifying circuit when the first switch is open;a comparator configured to compare the envelope voltage with the oscillating voltage, and to generate a command signal that closes said first switch when a difference between the envelope voltage and the oscillating voltage is smaller than a first offset voltage.2. The detector of claim 1 , comprising a clamping circuit configured to clamp said envelope voltage to an instantaneous value of the oscillating voltage claim 1 , the clamping circuit including:a timer configured to be ...

PEAK VOLTAGE DETECTOR AND RELATED METHOD OF GENERATING AN ENVELOPE VOLTAGE

A peak detector circuit receives an oscillating power supply signal. A capacitor is selectably coupled to the signal and charged to a value corresponding to a peak value of the signal. A switch is then opened to isolate the capacitor. A comparator continually compares the signal with the value stored on the capacitor. When the signal rises to within a selected threshold, relative to the stored value, the comparator produces a command signal to close the switch, again coupling the capacitor to the signal. The peak detector can also include a tracking circuit that controls the capacitor to track the oscillating signal while the switch is closed, a timer circuit configured to close the switch and activate the tracking circuit if more than a selected time passes without production of a command signal, and a circuit configured to control the polarity of a leakage current of the capacitor. 1. An integrated detector of peaks of an oscillating voltage , comprising:a rectifying circuit, having an input and an output, configured to generate an rectified voltage at the output corresponding to an oscillating voltage at the input;an integrated capacitor configured to store an envelope voltage representing a last detected peak value of the oscillating voltage;a first switch configured to electrically couple said integrated capacitor to the output of the rectifying circuit when the first switch is closed, and to isolate the integrated capacitor from the rectifying circuit when the first switch is open;a comparator configured to compare the envelope voltage with the oscillating voltage, and to generate a command signal that closes said first switch when a difference between the envelope voltage and the oscillating voltage is smaller than a first offset voltage.2. The detector of claim 1 , comprising a clamping circuit configured to clamp said envelope voltage to an instantaneous value of the oscillating voltage claim 1 , the clamping circuit including:a timer configured to be ...

MEMORY CONTROLLER HAVING A WRITE-TIMING CALIBRATION MODE

A memory controller outputs address bits and a first timing signal to a DRAM, each address bit being associated with an edge of the first timing signal and the first timing signal requiring a first propagation delay time to propagate to the DRAM. The memory controller further outputs write data bits and a second timing signal to the DRAM in association with the address bits, each of the write data bits being associated with an edge of the second timing signal and the second timing signal requiring a second propagation delay time to propagate to the DRAM. The memory controller includes a plurality of series-coupled delay elements to provide respective, differently-delayed internal delayed timing signals and a multiplexer to select one of the delayed timing signals to be output as the second timing signal based on a difference between the first propagation delay time and the second propagation delay time. 120-. (canceled)21. A memory controller comprising: address information indicating a storage address for first write data; and', 'a first timing signal to time reception of the address information within a first dynamic random access memory (DRAM), the first timing signal requiring a first propagation time to propagate from the memory controller to the first DRAM;, 'first circuitry to output a chain of delay elements to generate a plurality of delayed timing signals, and', 'first select circuitry to select, as a transmission timing source of the second timing signal, a first one of the delayed timing signals, wherein the memory controller is operable in a calibration mode to enable the first select circuitry to select the first one of the delayed timing signals to time transmission of the second timing signal, wherein, during the calibration mode, the second circuitry outputs multiple delayed versions of the timing signals and selects, as the first one of the delayed timing signals, one of the delayed timing signals that compensates for mismatch between the first and ...

SELF CLOCKING FOR DATA EXTRACTION

A self clocking data extraction method is shown that is tolerant of timing jitter, data skew and the presence of multiple edges per data bit. The data is sampled when the following criterion are met: There is at least one edge across any track (the clock assures this criteria is met), followed by no edges in any track for a defined period of time (T), and all edge activity must occur in a period of time less than T (to keep from detecting false samples). This method enables the handling of trace data signals with poor electrical characteristics that can not be recorded by methods known in the prior art. 1. A method of data extraction of data in a plurality of signal channels , comprising the steps of:for each signal channel taking a group of samples distributed throughout a bit period interval; determining an edge in said signal channel at said sample if said sample differs from said prior sample, and', 'determining no edge in said signal channel at said sample if said sample equals said prior sample;, 'for each signal channel comparing each sample of said group of samples with a prior sample'} (1) a sample during which an edge is determined in at least one signal channel, followed by', '(2) a second predetermined time Y during which no edge is determined for any signal channel., 'extracting data from all signal channels at a sample of said group of samples following detection of'}2. The method of claim 1 , wherein:said first predetermined time X is a first number of sampled of said group of samples.3. The method of claim 1 , wherein:said second predetermined time Y is a second number of sampled of said group of samples.4. The method of claim 1 , wherein:said group of samples is m samples n through n+m−1;sample data [(m/2)−1:00] is used to extract data within a window A; ansample data [m−1;m/2] is used to extract data within a window B.5. The method of claim 4 , wherein: calculating the logical AND of data [n] with a delayed version of sample value [n], and', ' ...

Analog peak hold circuits

A peak hold circuit includes an input node configured to receive an input waveform, a peak hold component coupled to the input node and configured to sample and hold a peak value of the input waveform at a peak value node, a reset node configured to receive a reset signal, a reset circuit coupled to the peak hold component and the reset node, the reset circuit configured to reset the peak hold value, and a voltage clamp coupled to the input node, the reset circuit, and the reset node, the voltage clamp configured to clamp the input node in response to the reset signal.

SEMICONDUCTOR MEMORY DEVICES HAVING INTERNAL CLOCK SIGNALS AND MEMORY SYSTEMS INCLUDING SUCH MEMORY DEVICES

A semiconductor memory device has a clock input buffer that is turned ‘on’ or ‘off’ in response to a first control signal. The clock input buffer is configured to buffer an external clock signal in order to output a buffered clock signal. The memory device further includes an internal clock generator that is configured to generate an internal clock signal in response to the buffered clock signal. The generation of the internal clock signal is started in response to a second control signal. 1. A semiconductor memory device comprising:a clock input buffer that is turned ‘on’ or ‘off’ in response to a first control signal, the clock input buffer configured to buffer a clock signal in order to output a buffered clock signal; andan internal clock generator that is configured to generate an internal clock signal in response to the buffered clock signal, wherein the generation of the internal clock signal is started in response to a second control signal.2. The semiconductor memory device of claim 1 , wherein the first control signal is a clock enable signal claim 1 , the second control signal is a chip selection signal claim 1 , and wherein the internal clock generator generates the internal clock signal by starting a division of the buffered clock signal in response to a first pulse of the chip selection signal being input to the internal clock generator.3. The semiconductor memory device of claim 2 , wherein a pulse width of the first pulse of the chip selection signal is greater than one clock cycle of the clock signal.4. The semiconductor memory device of claim 1 , wherein claim 1 , the internal clock generator is configured to start to generate the internal clock signal by dividing the buffered clock signal in response to the first pulse of the second control signal being input to the internal clock generator while the first control signal is activated.5. The semiconductor memory device of claim 1 , wherein the clock input buffer buffers the clock signal in response ...

MONITORING DEVICE AND METHOD FOR MONITORING A LINE SECTION USING A MONITORING DEVICE

A monitoring device is provided that includes a first line section with a first connection point and a second connection point spaced apart from the first connection point in the direction of the line, and with a control unit and with a first current sensing unit, having a current source. A first switch is inserted into the first connecting line and connects the first current source to the first connection point or disconnects it therefrom. In a first state the first switch is closed and the first current is impressed on the first line section and a first voltage determined by the amplitude of the actual current, and in a second state the first switch is open and a second voltage is determined, and the control unit is configured to ascertain the amplitude of the first actual current from the two voltages. 1. A monitoring device comprising:a first line section with a first connection point and a second connection point spaced apart from the first connection point in a direction of the line;a control unit; a first current source connectable to the first connection point via a first connecting line and connectable to the second connection point via a second connecting line, the first current source being configured to output a first current;', 'a first switch having a control input, the first switch being inserted into the second connecting line and being configured to connect or disconnect the first current source to the second connection point; and', 'a first differential amplifier having a first input, a second input, and an output, the first input being connectable to the first connection point via a third connecting line, the second input being connectable to the second connection point by a fourth connecting line;, 'a first current sensing unit comprisingwherein the control unit is inserted between the output of the first differential amplifier and the control input of the first switch,wherein an actual current is passed through the first line section,wherein, in ...

ELECTRONIC APPARATUS, DRAM CONTROLLER, AND DRAM

The invention provides an electronic apparatus. The electronic apparatus includes a Dynamic Random Access Memory (DRAM) and a DRAM controller. The DRAM receives at least one control and address signal and a clock signal, delays the clock signal by a predetermined value to obtain a delayed clock signal, samples the control and address signal according to the clock signal to obtain a first sample signal, samples the control and address signal according to the delayed clock signal to obtain a second sample signal, and compares the first sample signal with the second sample signal to obtain a status signal. The DRAM controller sends the control and address signal and the clock signal to the DRAM, receives the status signal from the DRAM, and adjusts a phase difference between the clock signal and the control and address signal according to the status signal. 1. An electronic apparatus , comprising:a Dynamic Random Access Memory (DRAM), receiving at least one control and address signal and a clock signal, delaying the clock signal by a predetermined value to obtain a delayed clock signal, sampling the control and address signal according to the clock signal to obtain a first sample signal, sampling the control and address signal according to the delayed clock signal to obtain a second sample signal, and comparing the first sample signal with the second sample signal to obtain a status signal; anda DRAM controller, sending the at least one control and address signal and the clock signal to the DRAM, receiving the status signal from the DRAM, and adjusting a phase difference between the clock signal and the at least one control and address signal according to the status signal.2. The electronic apparatus as claimed in claim 1 , wherein the DRAM comprises:a delay unit, delaying the clock signal by the predetermined value to obtain the delayed clock signal;a first latch, sampling the control and address signal according to the clock signal to obtain the first sample signal;a ...

LATENCY CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE COMPRISING SAME

A latency control circuit is configured to delay a read information signal in response to a CAS latency signal and an internal clock signal to generate a delayed read information signal, and is further configured to generate a latency control signal based on the delayed read information signal in response to a plurality of sampling control signals and a plurality of transfer control signals. 1. A latency control circuit , comprising:a sampling clock signal generating circuit configured to generate a plurality of sampling clock signals having different phases from each other based on an internal clock signal;a multiplexer configured to multiplex the sampling clock signals in response to a column address strobe (CAS) latency signal to generate a plurality of sampling control signals;a transfer control signal generating circuit configured to generate a plurality of transfer control signals having different phases from each other based on an output clock signal; anda latency control signal generating circuit configured to delay a read information signal in response to the CAS latency signal and the internal clock signal to generate a delayed read information signal, and further configured to generate a latency control signal based on the delayed read information signal in response to the sampling control signals and the transfer control signals.2. The latency control circuit of claim 1 , wherein the sampling clock signals are configured to have a phase difference of an integer multiple of a clock cycle of the internal clock signal.3. The latency control circuit of claim 2 , wherein the sampling clock signal generating circuit comprises:a shift register synchronized with the internal clock signal and configured to generate the sampling clock signals that are sequentially enabled with a delay time of the clock cycle.4. The latency control circuit of claim 1 , wherein the latency control signal generating circuit comprises:a delay circuit configured to delay the read ...

COMPARATOR, ANALOG-TO-DIGITAL CONVERTOR, SOLID-STATE IMAGING DEVICE, CAMERA SYSTEM, AND ELECTRONIC APPARATUS

A comparator includes a first amplifier, a second amplifier, and a level holding part. The first amplifier includes differential-pair transistors and outputs a signal of a level corresponding to a comparison result from a first output node. The differential-pair transistors compare a reference voltage with a potential of an input signal. The second amplifier gain up the signal output from the first output node of the first amplifier and outputs the signal from a second output node. The level holding part holds a level of the second output node at a predetermined level. The second amplifier includes a transistor for amplification and a transistor for a current source. The level holding part holds the level of the second output node of the second amplifier such that the transistor for the current source does not fall into a level at which a saturated operation condition is not satisfied. 1. A comparator , comprising: 'the differential-pair transistors serving as a comparison part configured to compare a reference voltage with a potential of an input signal;', 'a first amplifier including differential-pair transistors and configured to output a signal of a level corresponding to a comparison result from a first output node,'}a second amplifier configured to gain up the signal output from the first output node of the first amplifier and output the signal from a second output node; and the second amplifier including', 'a transistor for amplification connected between the second output node and a power supply or a reference potential source and', 'a transistor for a current source connected between the second output node and the reference potential source or the power supply,', 'the level holding part holding the level of the second output node of the second amplifier such that the transistor for the current source of the second amplifier does not fall into a level at which a saturated operation condition is not satisfied., 'a level holding part configured to hold a level ...

Physical unclonable function cell and array

A function cell comprising a first field effect transistor (FET) device, a second FET device, a first node connected to a gate terminal of the first FET device and a gate terminal of the second FET device, wherein the first node is operative to receive a voltage signal from an alternating current (AC) voltage source, an amplifier portion connected to the first FET device and the second FET device, the amplifier portion operative to receive a signal from the first FET device and the second FET device, a phase comparator portion having a first input terminal connected to an output terminal of the amplifier and a second input terminal operative to receive the voltage signal from the AC voltage source, the phase comparator portion operative to output a voltage indicative of a bit of a binary value.

SEMICONDUCTOR MEMORY DEVICE, METHOD OF CONTROLLING READ PREAMBLE SIGNAL THEREOF, AND DATA TRANSMISSION SYSTEM

A system, includes a controller including a plurality of first external terminals configured to supply a command, a clock signal and an address, and communicate a data, and communicate a strobe signal related to the data, and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, one of the plurality of first external terminals and one of the plurality of second external terminals transferring an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data, 1. A system , comprising:a controller comprising a plurality of first external terminals configured to supply a command and an address, to communicate data, and to communicate a strobe signal related to the data; anda semiconductor memory device comprising a plurality of second external terminals corresponding to the plurality of first external terminals,the semiconductor memory device further comprising a system clock external terminal provided to receive a system clock with a first frequency or a second frequency,one of the plurality of first external terminals and one of the plurality of second external terminals transferring an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data, the length of the preamble including first and second lengths corresponding to the first and second frequencies, respectively.2. The system as claimed in claim 1 , the device further comprising:a data strobe signal output control circuit configured to output the preamble of the strobe signal and then output a toggle transition of the data strobe signal to communicate the data.3. The system as claimed in claim 1 , wherein the more the frequency of the system clock is increased claim 1 , the longer the length of the preamble is.4. The system as claimed in claim 3 , wherein the larger a CAS latency is claim 3 , ...

SEMICONDUCTOR MEMORY DEVICE AND ACCESS METHOD THEREOF

Example embodiments provide a semiconductor memory device that may include: a cell array arranged in pluralities of rows and columns; and a sense amplifier conducting writing and reading operations to the cell array in response to writing and reading commands in correspondence with an access time, which may be variable in period. The sense amplifier adjusts pulse widths of write-in and read-out data in accordance with a period of the access time. 1. (canceled)2. A method of accessing memory banks in a cell array , the cell array including a plurality of bank groups , wherein each bank group includes at least two banks , the method comprising:receiving a first command to access a first bank of a first bank group;receiving a second command to access a first bank of a second bank group; andreceiving a third command to access a second bank of the first bank group,wherein the third command is received after a first delay time from the received first command,the second command is received after a second delay time from the received first command, andwherein the first and second delay times are different.3. The method of claim 2 , wherein the first delay time is programmed by a mode register setting.4. The method of claim 2 , wherein the first delay time is a first command delay for accesses within a same bank group claim 2 , and the second delay time is a second command delay for accesses within different bank groups.5. The method of claim 2 , wherein the first delay time is greater than the second delay time.6. The method of claim 2 , wherein each of the first claim 2 , second and third commands is a write command or a read command.7. The method of claim 2 , wherein the first claim 2 , second or third command includes a column address strobe signal. This application is a continuation of U.S. application Ser. No. 13/360,093 filed on Jan. 27, 2012, which is a Continuation of U.S. Pat. No. 8,125,847, issued on Feb. 28, 2012, which claims priority to Korean Patent ...

RECEIVER WITH TIME-VARYING THRESHOLD VOLTAGE

A system for communicating information between circuits is described. A transmit circuit provides pulse-amplitude-modulation (PAM) signals via a communication channel to a receiver. A circuit in the receiver determines digital values from the received signals using a time-varying threshold voltage, which varies during the bit-time. This approach may compensate for inter-symbol interference (ISI) to increase the voltage and timing margins of the system. 1. An apparatus , comprising:an input node to receive a signal representing a series of logical values, wherein a given logical value is within a corresponding bit-duration;a threshold generator circuit to generate a time-varying threshold voltage during the bit-duration; anda slicer, coupled to the input node and the threshold generator circuit, to resolve the logical values from the signal based at least on the time-varying threshold voltage.2. The apparatus of claim 1 , wherein the time-varying threshold voltage varies linearly with time during the bit-duration.3. The apparatus of claim 1 , wherein the time-varying threshold voltage varies non-linearly as a function of time.4. The apparatus of claim 1 , wherein a waveform of the time-varying threshold voltage is configured to match portion of a pulse response of a communication channel to which the slicer is coupled.5. The apparatus of claim 1 , further comprising: a clock input node claim 1 , coupled to the threshold generator circuit claim 1 , to receive a clock signal; wherein the threshold generator circuit generates the time-varying threshold voltage based on the clock signal.6. The apparatus of claim 5 , wherein the clock signal includes a source-synchronous clock signal that is communicated in a communication channel to which the slicer is coupled.7. The apparatus of claim 1 , further comprising:a register to store an activation bit; andcontrol logic, coupled to the register, to selectively enable or disable the time-varying threshold voltage based at least ...

MEMORY MODULE

A memory module having memory components, a termination structure, an address/control signal path, a clock signal path, multiple data signal paths and multiple strobe signal paths. The strobe signal paths and data signal paths are coupled to respective memory components, and the address/control signal path and clock signal path are coupled in common to all the memory components. The address/control signal path extends along the memory components to the termination structure such that control signals propagating toward the termination structure arrive at address/control inputs of respective memory components at progressively later times corresponding to relative positions of the memory components. 1. A memory module comprising:a circuit board;a first plurality of memory components disposed on the circuit board, each of the memory components having an address/control input, a clock input, a data input and a strobe input;a termination structure disposed on the circuit board;an address/control signal path that extends from an edge of the circuit board to the termination structure, the address/control signal path being coupled along its length to the address/control input of each of the memory components such that control signals propagating toward the termination structure on the address/control signal path arrive at the address/control inputs of respective memory components at progressively later times corresponding to relative positions of the memory components;a clock signal path extending from the circuit board edge and coupled along its length to the clock input of each of the memory components such that a clock signal propagating on the clock signal path arrives at the clock inputs of respective memory components at progressively later times corresponding to the times at which the control signals arrive at the address/control inputs of the memory components, the clock signal indicating to the memory components respective times at which to sample the control ...

SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME

A semiconductor memory apparatus includes: a memory cell area including a plurality of banks each having a plurality of octet banks corresponding to a first group and a plurality of octet banks corresponding to a second group; and a control unit configured to generate a plurality of control signals to input a data signal to any one octet bank of the first group and any one octet bank of the second group with a predetermined margin. 1. A semiconductor memory apparatus comprising:a memory cell area comprising a plurality of banks each having a plurality of octet banks corresponding to a first group and a plurality of octet banks corresponding to a second group; anda control unit configured to generate a plurality of control signals to input a data signal to any one octet bank of the first group and any one octet bank of the second group with a predetermined margin.2. The semiconductor memory apparatus according to claim 1 , wherein the control unit generates the plurality of control signals using a command signal and an address signal which are outputted in synchronization with the same clock claim 1 , andthe plurality of control signals are generated at substantially the same time.3. The semiconductor memory apparatus according to claim 2 , wherein the control unit comprises:a command address signal shifter configured to shift the command signal and the address signal, inputted from outside, such that the shifted signals have a predetermined margin;a data enable signal generator configured to generate a data enable signal having a predetermined margin, using the command signal and the address signal;a first latch signal generator configured to generate a first latch signal to latch a data signal inputted to the octet banks of the first group, using the command signal and the address signal;a second latch signal generator configured to generate a second latch signal for latching a data signal inputted to the octet banks of the second group, using the command signal ...

PROXIMITY SWITCH ASSEMBLY AND CALIBRATION METHOD THEREFOR

A proximity switch assembly and method for detecting activation of a proximity switch assembly and calibrating the switch assembly. The assembly includes proximity switches each having a proximity sensor providing a sense activation field and control circuitry processing the activation field to sense activation. The control circuitry generates an activation output when a differential change in the signal exceeds a threshold and distinguishes an activation from an exploration of the plurality of switches. The control circuit further determines a rate of change and generates an output when the rate of change exceeds a threshold rate to enable activation of a switch and performs a calibration of the signals to reduce effects caused by changes in condensation. 1. A method of calibrating a proximity switch comprising:generating an activation field with a proximity sensor;monitoring amplitude of a signal generated in response to the activation field;detecting the signal amplitude exceeding a threshold for a time period; andcalibrating the signal by adjusting the signal to a predefined level when the signal amplitude exceeds the threshold for the time period and reaches a peak value.2. The method of claim 1 , wherein the method comprises generating an activation field for each of a plurality of proximity sensors and monitoring amplitude of signals generated in response to the activation fields claim 1 , wherein the step of calibrating comprises calibrating all signals when a maximum signal is above a first threshold for a first time period and the maximum signal reaches a peak value.3. The method of claim 2 , wherein the method determines when all signals are negative and detects when a lowest signal is below a second threshold for a second time period claim 2 , wherein the step of calibrating comprises calibrating all signals when the lowest signal is below the second threshold for the second time period and the lowest signal reaches a bottom value.4. The method of claim ...

Proximity switch assembly and activation method using rate monitoring

A proximity switch assembly and method for detecting activation of a proximity switch assembly is provided. The assembly includes a plurality of proximity switches each having a proximity sensor providing a sense activation field and control circuitry processing the activation field of each proximity switch to sense activation. The control circuitry monitors the signal responsive to the activation field and determines a differential change in generated signal, and further generates an activation output when the differential signal exceeds a threshold. The control circuitry further distinguishes an activation from an exploration of the plurality of switches and determines activation upon detection of a stable signal. The control circuit further determines a rate of change and generates an output when the rate of change exceeds a threshold rate to enable activation of a switch.

ZERO CROSSING DETECTOR (ZCD) CIRCUIT

A system for detecting a Zero Crossing point is provided. The system includes: a coupling unit connected between a high voltage side and a low voltage side of the system; and a zero crossing detector connected to the high voltage side and configured to divide a filtered mains voltage signal and to generate an output signal that indicates a zero crossing point of the filtered mains voltage signal. 1. A method comprising:filtering noise in a mains voltage signal;dividing the mains voltage signal in order to obtain a low voltage signal; andgenerating an output signal from the low voltage signal, wherein the output signal indicates a zero crossing point of the mains voltage signal.2. The method of claim 1 , wherein the zero crossing point is used to provide synchronization of additional voltage signals with the mains voltage signal.3. The method of claim 1 , wherein the low voltage signal comprises a first low voltage signal and a second low voltage signal.4. The method of claim 1 , wherein generating the output signal comprises:generating a first low voltage signal and a second low voltage signal;comparing the first and second low voltage signals;outputting a positive pulse if the first low voltage signal is greater than the second low voltage signal; andoutputting a negative pulse if the first low voltage signal is less than the second low voltage signal.5. The method of claim 1 , further comprising:providing a given amount of voltage biasing to the low voltage signal prior to generating the output signal from the low voltage signal.6. The method of claim 5 , wherein providing the given amount of voltage biasing comprises: controlling an impedance value that is presented to the low voltage signal.7. The method of claim 5 , wherein providing the given amount of voltage biasing further comprises: controlling a DC value of the voltage biasing that is presented to the low voltage signal.8. The method of claim 5 , wherein providing the given amount of voltage biasing ...

SYSTEMS AND METHODS FOR COMPENSATING THE INPUT OFFSET VOLTAGE OF A COMPARATOR

Systems and methods of actively compensating for the input offset voltage of a comparator are provided. A compensation circuit may include a compensation comparator for comparing the comparison signal generated using the output signal of a comparator, to a reference voltage. A first voltage accumulator is coupled to the compensation comparator and produces a first voltage that is related to a first amount of time that the comparison signal spends above the reference voltage. A second voltage accumulator is coupled to the compensation comparator, and produces a second voltage that is related to the second amount of time that the comparison signal spends below the reference voltage. The first voltage and/or the second voltage may be used to provide one or more compensation signals to one or more of the two input terminals of the comparator. 110-. (canceled)11. A system to compensate for an input offset voltage of a zero crossing detection circuit for a power stealing circuit , the system comprising:an input configured to connect to an AC power source that provides power to a load;a zero crossing detection circuit responsive to the input, the zero crossing detection circuit configured to determine a zero crossing of an input signal provided by the ac power source, and wherein the zero crossing detection circuit includes a comparator having an input offset voltage; anda compensation circuit responsive to the zero crossing detection circuit, wherein the compensation circuit is configured to provide a first compensation signal to an inverting input of the comparator of the zero crossing detection circuit, and a second compensation signal to a non-inverting input of the comparator of the zero crossing detection circuit, wherein the polarity of the first compensation signal is opposite to the polarity of the second compensation signal.12. The system of claim 11 , further comprising a switch to activate the power stealing circuit claim 11 , the switch activated by an output ...

Driver circuits for dimmable solid state lighting apparatus

A voltage regulator for generating a housekeeping voltage in a high voltage power supply circuit includes a charging switch coupled to a high voltage node and to a storage device at an output node, and a control voltage regulation circuit coupled to the charging switch and configured to cause the charging switch to generate a current pulse for charging the storage device.

CONTROL DEVICE

A control device that comprises a first data strobe input terminal to be connected in common to data strobe terminals that are included respectively in first memory devices, and a plurality of first sub-units each coupled to the first data strobe input terminal and each holding a data strobe delay value corresponding to an associated one of the first memory devices, and the data strobe delay values of the sub-units being independent from each other. 1. A control device comprising:a first data strobe input terminal to be connected in common to data strobe terminals that are included respectively in first memory devices; anda plurality of first sub-units each coupled to the first data strobe input terminal and each holding a data strobe delay value corresponding to an associated one of the first memory devices, and the data strobe delay values of the sub-units being independent from each other.2. The control device according to claim 1 , further comprising:a first data input terminal to be connected in common to data terminals that are included respectively in the first memory devices;a first phase detector coupled to the first data input terminal and a common output terminal of the first sub-units,the first phase detector detecting a phase of a data strobe signal supplied via the first data strobe input terminal in response to a data signal supplied via the first data input terminal, so that each of the sub-units holds the data strobe delay value corresponding to the associated one of the first memory devices.3. The control device according to claim 2 , wherein the phase detector comprises:a latch circuit coupled to the first data input terminal and latching the data signal supplied via the data input terminal in response to the data strobe signal supplied via the output terminal of the first sub-units.4. The control device according to claim 1 , whereinthe first memory devices to which the first data strobe input terminal is connected in common are ranked ...

Zero-Crossing Detector for Industrial Control with Low Heat Dissipation

An I/O circuit for use with an industrial controller provides a zero-crossing detector circuit with low power dissipation through the use of a zero-crossing circuit that activates a light emitting diode of a photo coupler only for a very brief period of time at the zero-crossing (as opposed to at all times other than the zero-crossing). The circuit is coupled with a power supply circuit that uses a reactive element for voltage dropping as opposed to a resistive voltage drop element further reducing power consumption possible with the low power consumption of the photo coupler.

INPUT DECISION CIRCUIT

An input decision circuit includes a comparator outputting either one of a high voltage or a low voltage on the basis of the result of a comparison between a reference voltage and an input voltage, a base voltage source acting as a base common to the reference voltage and the input voltage, a constant current source supplying a constant current to a constant current path from a DC power supply to the base voltage source, and a resistor inserted in the constant current path. A constant voltage is produced across the resistor for the reference voltage with the electric potential of the base voltage source acting as a base. This provides an input decision circuit in which a threshold voltage is hard to shift even when the driving voltage of the comparator or the electric potential of the ground acting as the base voltage source is varied. 1. An input decision circuit , comprising:a comparator that outputs one of a high voltage or a low voltage on the basis of a result of a comparison between a reference voltage and an input voltage;a base voltage source that acts as a base common to the reference voltage and the input voltage;a constant current source that supplies a constant current to a constant current path formed between a DC power supply and the base voltage source; anda resistor inserted in the constant current path, wherein with an electric potential of the base voltage source as a base, a constant voltage produced across the resistor acts as the reference voltage.2. The input decision circuit of claim 1 , wherein the input decision circuit further comprises:a first constant current source that makes a constant current flow in a first constant current path;a second constant current source that makes a constant current flow in a second constant current path;a switching device inserted in the second constant current path; anda third constant current path from a joining point of the first constant current path and the second constant current path to the base ...

SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME AND OPERATING METHOD THEREOF

A semiconductor memory device includes an input/output circuit configured to receive an address and data from an exterior, and a peripheral circuit configured to receive the address through the input/output circuit and generate a chip selection signal based on the address. The input/output circuit may include a control pad circuit configured to apply or block at least one data strobe signal in response to the chip selection signal, and one or more input/output pad circuits configured to transfer the data to the peripheral circuits in response to the at least one data strobe signal. 1. A semiconductor memory device , comprising:an input/output circuit configured to receive an address and data from an exterior; anda peripheral circuit configured to receive the address through the input/output circuit and generate a chip selection signal based on the address,wherein the input/output circuit comprises:a control pad circuit configured to apply or block at least one data strobe signal in response to the chip selection signal; andone or more input/output pad circuits configured to transfer the data to the peripheral circuit in response to the at least one data strobe signal.2. The semiconductor memory device of claim 1 , wherein the input/output pad circuits are configured to transfer the data to the peripheral circuit when the at least one data strobe signal is applied and block the data to the peripheral circuit when the at least one data strobe signal is blocked.3. The semiconductor memory device of claim 1 , wherein the control pad circuit is configured to receive an original data strobe signal from the exterior and apply the at least one data strobe signal based on the original data strobe signal.4. The semiconductor memory device of claim 3 , wherein the at least one data strobe signal includes a first data strobe signal that is substantially the same as the original data strobe signal and a second data strobe signal obtained by inverting the original data strobe ...

Method Of Controlling Electronic Device And Electronic Device

A control method and an electronic device are described. The method is applied in an electronic device which includes a first body, a second body and a rotary apparatus. On at least one body of the first body and the second body, there are provided M number of input apparatuses; the first body and the second body are rotatably connected together, where M is an integer greater than or equal to 1. The state-information of the first body and/or the second body is detected, to obtain a detection result; when the detection result indicates that the first body and/or the second body are/is in a motion state, a disable command is generated; the disable command is executed, so that N number of input apparatuses from the M number of input apparatuses are in a disabled state, where N is an integer less than or equal to M. 1. A method of controlling an electronic device , applied in an electronic device that comprises a first body , a second body and a rotary apparatus; on at least one body of the first body and the second body , there are provided M number of input apparatuses; the first body and the second body are rotatably connected together through the rotary apparatus , where M is an integer greater than or equal to 1; wherein the method comprises:detecting a state-information of the first body and/or the second body to obtain a detection result;generating a disable command when the detection result indicates that the first body and/or the second body are/is in a motion state;wherein the disable command is executed, so that N number of input apparatuses from the M number of input apparatuses are in a disabled state, where N is an integer less than or equal to M.2. The method according to claim 1 , wherein said step of detecting the state-information of the first body and/or the second body comprises:a first absolute included-angle between the first body and a first reference plane is detected, and/or, a second absolute included-angle between the second body and a second ...

MAXIMUM VOLTAGE SELECTION CIRCUIT AND METHOD AND SUB-SELECTION CIRCUIT

A maximum voltage selection circuit and method and a sub-selection circuit are provided. The maximum voltage selection circuit includes a peripheral signal circuit and a selection circuit with N channels of input voltages. The peripheral signal circuit provides an operating mode signal and a reference voltage to the selection circuit including N sub-selection circuits coupled to the N channels of input voltages respectively. A sub-selection circuit determines its operating mode according to the operating mode signal. In the operating mode, when an input voltage of a sub-selection circuit is larger than the reference voltage, the sub-selection circuit sets itself to the output enable state and sets other sub-selection circuits to the output disable state, and outputs its input voltage as a maximum voltage through a PMOS. 1. A sub-selection circuit , comprising an enable mode circuit and a disable mode circuit ,wherein the enable mode circuit includes a comparator, and is configured to operate when an operating mode signal is an enable signal, and to set itself to an output enable state, set other sub-selection circuits to an output disable state, and output its input voltage as a maximum voltage through a P-type metal oxide semiconductor field effect transistor (PMOS transistor) when its input voltage is larger than a reference voltage, andwherein the disable mode circuit includes a power latch, and is configured to operate when the operating mode signal is a disable signal, and to set itself to the output enable state, set other sub-selection circuits to the output disable state, and output its input voltage as the maximum voltage through the PMOS transistor when its input voltage is larger than the reference voltage.2. The sub-selection circuit according to claim 1 , wherein when there is a bias current in the sub-selection circuit claim 1 , the operating mode signal having a high level is used as the enable signal claim 1 , and when there is no bias current in the ...

MEMORIES AND METHODS FOR SHARING A SIGNAL NODE FOR THE RECEIPT AND PROVISION OF NON-DATA SIGNALS

Memories and methods for providing and receiving non-data signals at a signal node are disclosed. One such memory includes first and second signal nodes, and first and second signal buffer. The first signal buffer is configured to be operative responsive to a first data strobe signal and further configured to be operative responsive to a non-data signal. The second signal buffer is configured to be operative responsive to a second data strobe signal. An example first data strobe signal is a read data strobe signal provided by the memory. In another example, the first data strobe signal is a write data strobe signal received by the memory. Examples of non-data signals include a data mask signal, data valid signal, error correction signal, as well as other signals. 1. A memory , comprising:a first signal node;a second signal node;a first signal buffer coupled to the first signal node and configured to provide a first data strobe signal to the first signal node, wherein the first data strobe signal pertains to a first memory operation, and wherein the first signal buffer is configured to receive a first non-data signal from the first signal node during a time the first data strobe signal is not provided by the first signal buffer to the first signal node, and wherein the first non-data signal pertains to a second memory operation different from the first memory operation; anda second signal buffer coupled to the second signal node, wherein the second signal buffer is configured to provide a second data strobe signal to the second signal node, and wherein the second signal buffer is configured to receive a second non-data signal from the second signal node during a time the second data strobe signal is not provided by the second signal buffer to the second signal node.2. The memory of claim 1 , wherein at least one of the first non-data signal or the second non-data signal is a data mask signal.3. The memory of claim 1 , wherein the first data strobe signal comprises:a ...

Phase correction circuit and phase correction method

A variable delay circuit outputs a first delay signal obtained by variably adding a delay value to a first signal having a predetermined phase. A mixer receives the first delay signal and a second signal having a phase different from the predetermined phase, and outputs a synthesized signal of the first delay signal and the second signal. A peak voltage detection unit detects the maximum value of an amplitude voltage of the synthesized signal output from the mixer. A comparator controls the delay value added by the variable delay circuit to match the maximum value detected by the peak voltage detection unit and a predetermined voltage.

High speed signal detecting circuit and system

A high speed signal detecting circuit includes an input terminal, a reference terminal, an output terminal, a power source terminal, a ground terminal, a front-end receiver which is connected to the input terminal, the reference terminal and the ground terminal, a secondary amplifier which is connected to the front-end receiver and the ground terminal, a final amplifier which is connected to the secondary receiver, the output terminal, the power source terminal and the ground terminal, and a biasing circuit which is connected to the front-end receiver, the secondary amplifier, the final amplifier, the power source terminal and the ground terminal. A high speed signal detecting method is also provided to precisely detect high speed signal and change a detection threshold value of the high speed signals by changing a voltage value of the reference terminal and thus has a great flexibility. 1. A high speed signal detecting circuit , comprising an input terminal , a reference terminal , an output terminal , a power source terminal , a ground terminal , a front-end receiver which is connected to said input terminal , said reference terminal and said ground terminal , a secondary amplifier which is connected to said front-end receiver and said ground terminal , a final amplifier which is connected to said secondary amplifier , said output terminal , said power source terminal and said ground terminal , and a biasing circuit which is connected to said front-end receiver , said secondary amplifier , said final amplifier , said power source terminal and said ground terminal.2. The high speed signal detecting circuit claim 1 , as recited in claim 1 , wherein said front-end receiver comprises a first FET which is connected to said input terminal and said ground terminal claim 1 , and a second FET which is connected to said reference terminal and said ground terminal; said secondary amplifier comprises a third FET connected to said first FET claim 1 , a fourth FET connected to ...

ZERO-CROSSING DETECTION METHOD AND CIRCUIT

Embodiments of the present invention disclose a zero-crossing detection method and circuit. The zero-crossing detection method includes: detecting a time point t0 when a mains voltage jumps from a low electrical level to a high electrical level and an adjacent time point t1 when the mains voltage jumps from a high electrical level to a low electrical level at a port of a detection end; and determining, according to the detected time points t0 and t1, a time point t when the mains voltage crosses zero. 1. A zero-crossing detection method , comprising:detecting a time point t0 when a mains voltage jumps from a low electrical level to a high electrical level and an adjacent time point t1 when the mains voltage jumps from a high electrical level to a low electrical level at a port of a detection end; anddetermining, according to the detected time points t0 and t1, a time point t when the mains voltage crosses zero.2. The zero-crossing detection method according to claim 1 , wherein the determining claim 1 , according to the detected time points t0 and t1 claim 1 , the time point t when the mains voltage crosses zero comprises:t=t0+0.5(t1−t0)−5.3. A zero-crossing detection circuit for implementing the zero-crossing detection method according to claim 1 , comprising a live line and a zero line of the mains claim 1 , wherein the live line and the zero line of the mains are connected to a rectifier circuit claim 1 , the rectifier circuit is connected to an output circuit claim 1 , and a current-limiting circuit is connected between the live line and the zero line of the mains and the rectifier circuit.4. The zero-crossing detection circuit according to claim 3 , wherein the current-limiting circuit comprises a first current-limiting resistor and a second current-limiting resistor claim 3 , the first current-limiting resistor is connected in the live line claim 3 , and the second current-limiting resistor is connected in the zero line.5. The zero-crossing detection circuit ...

TRANSIENT RECOVERY VOLTAGE MEASURING DEVICE, TRANSIENT RECOVERY VOLTAGE MEASURING METHOD, AND TRANSIENT RECOVERY VOLTAGE MEASURING PROGRAM

A common tangent line drawn between a rise portion present from the origin to a second reference voltage and a rise portion corresponding to the second reference voltage can be easily generated through a waveform conversion. A transient recovery voltage measuring device includes a memory storing a transient recovery voltage waveform of a multiple frequency, a waveform conversion unit converting the transient recovery voltage waveform, a wave height determination unit determining two points having the same maximum value on the converted waveform, an adjustment unit adjusting the proportional constant of the waveform conversion unit to determine those two points by the wave height determination unit, a contact point detection unit obtaining two points corresponding to the determined two points determined by the wave height determination unit, and a tangent line generation unit generating a first tangent line passing through the detected two points on the transient recovery voltage waveform. 1. A transient recovery voltage measuring device comprising:a waveform memory that stores a transient recovery voltage waveform of a multiple frequency;a waveform conversion unit that converts the transient recovery voltage waveform based on a proportional value obtained by multiplying a time from an origin by a proportional constant;a wave height determination unit that determines two points having a same maximum value on a converted waveform;an adjustment unit that adjusts the proportional constant of the waveform conversion unit until two points having the same maximum value are determined by the wave height determination unit;a contact point detection unit that detects two points on the transient recovery voltage waveform corresponding to two points determined by the wave height determination unit; anda first tangent line generation unit that generates a first tangent line passing through the two points detected by the contact point detection unit.2. The transient recovery ...

COMPARATOR WITH TRANSITION THRESHOLD TRACKING CAPABILITY

A comparator is provided having a voltage generator, having an output terminal for providing a reference voltage. The comparator also has a buffer unit, providing an output signal according to a first input signal and the reference voltage; wherein the voltage generator provides the reference voltage according to a second input signal, and the output signal represents a compare result of the first and second input signals. 1. A comparator , comprising:a voltage generator, having an output terminal for providing a reference voltage;a buffer unit, providing an output signal according to a first input signal and a bias signal; anda threshold control loop, providing the bias signal to the buffer unit according to a second input signal, so as to regulate a transition threshold of the buffer unit to close to the second input signal,wherein the output signal represents a compare result of the first and second input signals,wherein the buffer unit and the threshold control loop are powered by the reference voltage.2. The comparator as claimed in claim 1 , wherein the buffer unit comprises:a first PMOS transistor coupled between the output terminal of the voltage generator and a first node, having a gate for receiving the first input signal;a first NMOS transistor coupled to a ground, having a gate for receiving the bias signal;a second NMOS transistor coupled between the first NMOS transistor and the first node, having a gate for receiving the first input signal;a second PMOS transistor coupled between the output terminal of the voltage generator and a second node, having a gate coupled to the first node;a third NMOS transistor coupled to the ground, having a gate for receiving the bias signal; anda fourth NMOS transistor coupled between the third NMOS transistor and the second node, having a gate coupled to the first node,wherein a voltage of the second node represents the compare result of the first and second input signals.3. The comparator as claimed in claim 2 , ...

Techniques for Aligning and Reducing Skew in Serial Data Signals

A circuit includes first and second aligner circuits and a deskew circuit. The first aligner circuit is operable to align a first input serial data signal with a control signal to generate a first aligned serial data signal. The second aligner circuit is operable to align a second input serial data signal with the control signal to generate a second aligned serial data signal. The deskew circuit is operable to reduce skew between the first and the second aligned serial data signals to generate first and second output serial data signals. 1. A circuit comprising:a first aligner circuit operable to align a first input serial data signal with a first control signal to generate a first aligned serial data signal;a second aligner circuit operable to align a second input serial data signal with the first control signal to generate a second aligned serial data signal; anda deskew circuit operable to reduce skew between the first and the second aligned serial data signals to generate first and second output serial data signals.2. The circuit of claim 1 , wherein the first aligner circuit comprises:first storage circuits operable to store values of the first input serial data signal as first stored signals in response to the first control signal and a second control signal;second storage circuits operable to store values of the first stored signals as second stored signals in response to the first and the second control signals;a first multiplexer circuit operable to receive the second stored signals at multiplexing inputs and to select a first selected signal based on the first and the second stored signals; anda third storage circuit operable to store the first selected signal as the first aligned serial data signal in response to the first control signal.3. The circuit of claim 2 , wherein the second aligner circuit comprises:fourth storage circuits operable to store values of the second input serial data signal as third stored signals in response to the first and the ...

INTEGRATED CIRCUIT

There is disclosed an integrated circuit comprising a management unit for managing the occurrence of predetermined events in the integrated circuit. The management unit comprises: a processing unit adapted to determine the occurrence of a predetermined event in the integrated circuit; a data storage unit adapted to store information regarding the determined event occurrence; an output interface adapted to output a signal based on the stored information regarding the determined event occurrence; and an output generating unit adapted to analyse the stored information and to generate a signal to be output by the output interface based on results of the analysis. 1. An integrated circuit comprising a management unit for managing the occurrence of predetermined events in the integrated circuit , wherein the management unit comprises:a processing unit adapted to determine the occurrence of a predetermined event in the integrated circuit;a data storage unit adapted to store information regarding the determined event occurrence;an output interface adapted to output a signal based on the stored information regarding the determined event occurrence; andan output generating unit adapted to analyse the stored information and to generate a signal to be output by the output interface based on results of the analysis.2. The integrated circuit of claim 1 , wherein the management unit further comprises an input interface adapted to receive a signal from the integrated circuit and to pass the received signal to the processing unit.3. The integrated circuit of claim 1 , wherein the signal to be output by the output interface comprises information regarding at least one occurrence of the predetermined event.4. The integrated circuit of claim wherein the output generating unit is adapted to determine a number of occurrences of a predetermined event and to generate the signal to be output if the determined number of occurrences of the predetermined event exceeds a predetermined threshold ...

PEAK DETECTOR AND AUTO GAIN CONTROLLER USING THE SAME

Disclosed herein is a peak detector including: a operation time point providing unit outputting a certain time point before the maximum value in an interval in which a driving displacement increases as an operation time point, when a raising edge of an operation interval signal is detected; and a holding circuit unit, when a reset signal is input, starting an operation at the operation time point provided from the operation time point providing unit after an operation standby state and sensing and outputting a driving displacement of a driving mass. 1. A peak detector comprising:a operation time point providing unit outputting a certain time point before the maximum value in an interval in which a driving displacement increases as an operation time point, when a raising edge of an operation interval signal is detected; anda holding circuit unit, when a reset signal is input, starting an operation at the operation time point provided from the operation time point providing unit after an operation standby state and sensing and outputting a driving displacement of a driving mass.2. The peak detector as set forth in claim 1 , wherein an operation interval signal (READ) provided to the operation time point providing unit is a step waveform having a raising edge at a falling edge of the reset signal and holding a high level during a certain time.3. The peak detector as set forth in claim 1 , wherein the operation time point providing unit claim 1 , when the operation interval signal (READ) is input claim 1 , starts the operation from a time point of detecting the raising edge claim 1 , compares between reference voltage and the driving displacement of the driving mass to recognize a certain time point before the difference therebetween becomes the maximum value in an interval at which the driving displacement increases claim 1 , thereby providing the recognized certain time point as the operation time point.4. The peak detector as set forth in claim 1 , wherein the ...

ACCESS METHODS AND CIRCUITS FOR MEMORY DEVICES HAVING MULTIPLE BANKS

A method can include storing bank addresses, if received, on at least rising and falling edges of a same clock cycle; and if addresses stored on the rising and falling edges of the same clock cycle correspond to different banks of a memory device, starting accesses to both banks after the falling edge of the clock cycle; wherein any of the banks can be accessed in response to an address stored on a rising edge of a next clock cycle. Devices and additional methods are also disclosed. 1. A method , comprising:storing bank addresses of first and second banks of a memory device, if received, on at least first and second edges of a same clock cycle, respectively; andif the first and second bank addresses correspond to different banks, starting at the same time the first accesses to each bank in response to said storing that occurs after the second edge of the clock cycle, whereinany one of the banks of the memory device can be accessed in response to an address stored on a first edge of a next clock cycle.2. The method of claim 1 , wherein:the first edge is a rising edge and the second edge is a falling edge.3. The method of claim 1 , wherein:bank addresses stored on first edges of the clock signal correspond to read operations; andbank addresses stored on second edges of the clock signal correspond to write operations.4. The method of claim 1 , further including:allowing access to any of the banks in response to the address stored on a second edge of the clock cycle if no bank address is stored on the first edge of the same clock cycle.5. The method of claim 1 , wherein:preventing an access to the bank corresponding to at least one of the addresses if bank addresses for the same bank are stored on the first and second edges of the same clock cycle.6. The method of claim 1 , further including:comparing the bank address stored on the first edge of the clock cycle to the bank address stored on the second edge of the clock cycle, after the second edge of the clock cycle to ...

PROPAGATION SIMULATION BUFFER

Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay. 129-. (canceled)30. An integrated circuit , comprising:a path between a source register and a destination register;a buffer within the path, wherein the buffer is configured to propagate a buffer input signal along the path responsive to a buffer enable signal being asserted; andwherein the integrated circuit is configured to assert the buffer enable signal after a predetermined number of clock cycles have occurred since the buffer received the buffer input signal.31. The integrated circuit of claim 30 , wherein the source register resides in a first clock domain and the destination register resides in a second clock domain.32. The integrated circuit of claim 31 , wherein the integrated circuit is configured to supply the buffer enable signal from logic within the second clock domain.33. The integrated circuit of claim 30 , wherein the buffer includes a NAND gate configured to receive the buffer input signal and the buffer enable signal.34. The integrated circuit of claim 30 , wherein the buffer includes an AND gate configured to receive the buffer input signal and the buffer enable signal.35. The ...

INTEGRITY CHECK OF MEASURED SIGNAL TRACE DATA

A method of monitoring signals is disclosed, wherein a plurality of command signals and address signals are consecutively expressed, as a measurement target. The method includes setting a strobe timing that has a predetermined initial value; calculating an error rate by monitoring the plurality of command signals, in accordance with the strobe timing; monitoring the plurality of address signals, and calculating a burst rate from a difference between the consecutive plurality of address signals, in accordance with the strobe timing; identifying timing where the calculated error rate and calculated burst rate are both optimized; and in the event the timing where both the calculated error rate and calculated burst rate are optimized cannot be identified, altering a predetermined value of the set strobe timing, and repeating the calculating, monitoring, and identifying. 1. A method of monitoring signals , wherein a plurality of command signals and address signals are consecutively expressed , as a measurement target , the method comprising:setting a strobe timing that has a predetermined initial value;calculating an error rate by monitoring the plurality of command signals, in accordance with the strobe timing;monitoring the plurality of address signals, and calculating a burst rate from a difference between the consecutive plurality of address signals, in accordance with the strobe timing;identifying timing where the calculated error rate and calculated burst rate are both optimized; andin the event the timing where both the calculated error rate and calculated burst rate are optimized cannot be identified, altering a predetermined value of the set strobe timing, and repeating the calculating, monitoring, and identifying.2. The method according to claim 1 , wherein the determination of whether or not the error rate is optimized is made using a bathtub curve with the strobe timing value on the lateral axis claim 1 , by determining whether the error rate is minimized at ...

Method and Apparatus for Analog Pulse Pile-Up Rejection

A method and apparatus for pulse pile-up rejection are disclosed. The apparatus comprises a delay value application constituent configured to receive a threshold-crossing time value, and provide an adjustable value according to a delay value and the threshold-crossing time value; and a comparison constituent configured to receive a peak-occurrence time value and the adjustable value, compare the peak-occurrence time value with the adjustable value, indicate pulse acceptance if the peak-occurrence time value is less than or equal to the adjustable value, and indicate pulse rejection if the peak-occurrence time value is greater than the adjustable value. 1. An apparatus for pulse pile-up rejection , comprising:a discriminator circuit, configured to output a pulse threshold-crossing time signal in response to a received signal of a single pulse if the signal of the single pulse exceeds a threshold;a time delay circuit configured to receive the pulse threshold-crossing time signal, and output an adjustable delayed time signal according to a delay value and the pulse threshold-crossing time signal; anda comparator circuit that receives a pulse peak-occurrence time signal indicative of the peak-occurrence time of the single pulse, receives the adjustable delayed time signal, compares the pulse peak-occurrence time signal with the adjustable delayed time signal, indicates pulse acceptance if the pulse peak-occurrence time signal occurs before the adjustable delayed time signal, and indicates pulse rejection if the pulse peak-occurrence time signal occurs after the adjustable delayed time signal.2. The apparatus of claim 1 , wherein the delay value is calculated from a time jitter of the pulse threshold-crossing time signal claim 1 , a time walk of the pulse threshold-crossing time signal claim 1 , a time jitter of the pulse peak-occurrence time signal claim 1 , a time walk of the pulse peak-occurrence time signal claim 1 , or a combination thereof.3. The apparatus of claim ...

SEMICONDUCTOR MEMORY DEVICE AND DETECTION CLOCK PATTERN GENERATING METHOD THEREOF

A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state. 1. A clock pattern generating method of a semiconductor memory device , comprising:generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state; andgenerating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.2. The clock pattern generating method of claim 1 , wherein in the second state claim 1 , first clock patterns are output via a first group of the detection clock output pins claim 1 , and second clock patterns are output via a second group of the detection clock output pins.3. The clock pattern generating method of claim 2 , wherein the first clock patterns include pseudo random binary pattern signals.4. The clock pattern generating method of claim 3 , wherein the pseudo random binary pattern signals have the same phase or have phases different from each other.5. The clock pattern generating method of claim 2 , wherein the second clock patterns include pseudo random binary pattern signals.6. The clock pattern generating method of claim 5 , wherein the pseudo random binary pattern signals have the same phase or have phases different from each other.7. The clock pattern generating method of claim 1 , wherein the plurality of detection clock output pins are error detection code pins.8. The clock pattern generating method of claim 1 , wherein the clock patterns different from each other are error detection ...

MULTIPLE DEVICE APPARATUS, SYSTEMS, AND METHODS

Apparatus, systems, and methods are disclosed that operate to generate a clock signal in a die in a stack and to receive the clock signal in another die in the stack. Additional apparatus, systems, and methods are disclosed. 1. An apparatus comprising:a plurality of dies coupled together through a plurality of channels wherein each of the plurality of dies comprises a respective clock generator circuit that is coupled to the plurality of channels for distributing a clock signal from a first clock generator circuit on a first die of the plurality of dies to the other dies of the plurality of dies, wherein the first clock generator circuit is enabled by a clock enable signal received from less than all of the other dies of the plurality of dies and each respective clock generator circuit of each of the other dies of the plurality of dies is shut off while the first clock generator circuit is enabled.2. The apparatus of wherein the first die is a generator die.3. The apparatus of wherein the clock generator circuits are one of a phase-locked loop or a delay-locked loop.4. The apparatus of wherein each die comprises a plurality of clock distribution terminals.5. The apparatus of wherein the clock enable signal is part of the plurality of channels.6. The apparatus of wherein clock generator circuits are phase-locked loops and delay-locked loops.7. The apparatus of further comprising each die of the plurality of dies is configured to generate the clock enable signal.8. The apparatus of wherein the first die is configured to generate the clock enable signal to enable the first die to use the clock signal.9. A method for operating a plurality of dies claim 7 , the method comprising:enabling a plurality of clock generator circuits to generate a plurality of clock signals, each of the plurality of clock generator circuits located on a respective die of the plurality of dies;distributing the plurality of clock signals to each die of the plurality of dies that has generated a ...

Method and compensator for stabilizing an encoder signal

Aspects of the disclosure relate to a method and a compensator via which the input edges of the encoder signal of an encoder may be transformed into a compensated encoder signal such that requirements with regard to a dot resolution of a printing device and with regard to a maximum activation frequency of the dot generators of the printing device are satisfied.

Contactless Device for Characterising An Electric Signal

A contactless device for characterising the electrical signal passing through an electrical conductor, comprising an inductive electromagnetic coupling means able to surround the conductor, the inductive electromagnetic coupling means further comprising means for short-circuiting the output of the inductive electromagnetic coupling means, the output being connected to an electronic circuit for measuring the potential difference with respect to a floating earth configured to deliver a signal representing the voltage between the segment of the conductor passing through the device, and a fixed potential reference. 111-. (canceled)12. A contactless device for characterising the electrical signal passing through an electrical conductor , comprising an inductive electromagnetic coupling means able to surround said conductor , said inductive electromagnetic coupling means further comprising means for short-circuiting the output of said inductive electromagnetic coupling means , said output being connected to an electronic circuit for measuring the potential difference with respect to a floating earth configured to deliver a signal representing the voltage between the segment of said conductor passing through the device , and a fixed potential reference.13. The contactless device for characterising the electrical signal passing through an electrical conductor according to claim 12 , wherein said electrical circuit comprises means for conditioning the signal measured between the short-circuited output and the floating earth claim 12 , configured to amplify the signal and adapt the impedance according to the means for measuring the potential difference.14. The contactless device for characterising the electrical signal passing through an electrical conductor according to claim 12 , further comprising an energy-storage circuit supplied by the output of said inductive coupling means when it is not in a short-circuit state.15. The contactless device for characterising the ...

CIRCUIT AND METHOD FOR REDUCING MISMATCH FOR COMBINED CLOCK SIGNAL

A circuit comprises a cycle-cycle detector, configured to receive a synthesized clock signal, and detect a cycle difference index signal between any two neighboring cycles of the synthesized clock signal, wherein the synthesized clock signal is combined by a plurality of phase shifted signals; a demultiplexer connected to the cycle-cycle detector, configured to convert the cycle difference index signal into a plurality of parallel data signals; and a first state machine, connected to both the demultiplexer and the cycle-cycle detector, configured to generate a tuning signal based on the parallel data signals, and feed the tuning signal back to the cycle-cycle detector; wherein the cycle-cycle detector is further configured to adjust delay time of the synthesized clock signal according to the tuning signal. 1. A circuit comprising: a digital-time converter configured to receive a synthesized clock signal and generate a delayed clock signal according to a tuning signal;', 'a first DFF connected to the digital-time converter, and configured to detect a cycle difference index signal between any two neighboring cycles of the synthesized clock signal according to the delayed clock signal, wherein the synthesized clock signal is combined by a plurality of phase shifted signals, and the cycle difference index signal indicates difference between two neighboring cycles for the synthesized clock signal;, 'a cycle-cycle detector, comprising'}a demultiplexer connected to the cycle-cycle detector, configured to convert the cycle difference index signal into a plurality of parallel data signals; anda first state machine, connected to both the demultiplexer and the cycle-cycle detector, configured to generate a tuning signal based on the parallel data signals, and feed the tuning signal back to the cycle-cycle detector;wherein the cycle-cycle detector is further configured to adjust delay time of the synthesized clock signal according to the tuning signal.2. The circuit according ...

PEAK DETECTION METHODS, APPARATUS, AND CIRCUITS

Peak detection methods, apparatus, and circuits are disclosed. An example peak detector includes a first peak-hold circuit having a first input terminal and a first output terminal, the first peak-hold circuit to determine a first peak of a rectified input voltage at the first input terminal during a first time interval, and to track a second peak of the rectified input voltage during a second time interval, the second time interval distinct from the first time interval, and a second peak-hold circuit having a second input terminal and a second output terminal, the second peak-hold circuit to determine, during the second time interval, a greater of the first peak and the second peak, the first output terminal coupled to the second input terminal, the greater of the first peak and the second peak output at the second output terminal. 1. A peak detector , comprising:a first peak-hold circuit having a first input terminal and a first output terminal, the first peak-hold circuit to determine a first peak of a rectified input voltage at the first input terminal during a first time interval, and to track a second peak of the rectified input voltage during a second time interval, the second time interval distinct from the first time interval; anda second peak-hold circuit having a second input terminal and a second output terminal, the second peak-hold circuit to determine, during the second time interval, a greater of the first peak and the second peak, the first output terminal coupled to the second input terminal to convey the first peak and the second peak to the second peak-hold circuit, the greater of the first peak and the second peak output at the second output terminal.2. The peak detector of claim 1 , further including a control signal generator to claim 1 , when the rectified input voltage satisfies a threshold claim 1 , set an output of the second peak-hold circuit at the second output terminal to an output of the first peak-hold circuit at the first output ...

SIGNAL ENVELOPE PROCESSING

Methods and apparatus for detection and tracking of a signal envelope. The circuit comprises absolute value circuitry configured to receive data samples and output a first value corresponding to the magnitude of said data samples. An envelope tracker maintains an envelope output value and compares the first value to the current envelope output value and modifies the envelope output value based on said comparison to provide the envelope output value with predetermined attack and decay characteristics. The absolute value circuitry has a first input for receiving a first digital signal at a first sample rate and a second input for receiving an interpolated version of the first digital signal at a second sample rate which is higher than the first sample rate and outputs the first value based on the magnitudes of the samples received at the first input and the samples received at the second input. Using the first digital signal provides an early indication of any increases in signal envelope whereas the second digital signal can allow a more accurate estimation. 1. An envelope detection circuit comprising:absolute value circuitry configured to receive data samples and output a first value corresponding to the magnitude of said data samples; andan envelope tracker configured to maintain an envelope output value and to compare the first value to the current envelope output value and modify the envelope output value based on said comparison to provide the envelope output value with predetermined attack and decay characteristics;wherein the absolute value circuitry comprises a first input for receiving a first digital signal at a first sample rate and a second input for receiving an interpolated version of the first digital signal at a second sample rate which is higher than the first sample rate and is configured to output said first value based on the magnitudes of the samples received at the first input and the samples received at the second input.2. An envelope detection ...

INFORMATION PROCESSING APPARATUS, METHOD FOR MANAGING, NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM HAVING STORED THEREIN MANAGEMENT PROGRAM, AND METHOD FOR SPECIFYING INSTALLING POSITION OF ELECTRONIC DEVICE

An information processing apparatus includes an applier that applies an alternating voltage to a lead provided for a frame of a rack that stores one or more electronic devices along a direction of arrangement of the electronic devices, the lead being in contact with a fixing part when the electronic devices are installed; a measure that measures an alternating wave of the alternating voltage flowing through the lead; and a specifier that specifies an installing position of an electronic device by referring to reference waveform information with a waveform of the measure alternating wave, the reference waveform information associating an installing state of the electronic device in the rack with a waveform pattern of the alternating wave measured under the installing state. This configuration reduces steps needed for managing a token, an archive, a token password and enhances the security level of the terminal device. 1. An information processing apparatus comprising:an applier that applies an alternating voltage to a lead being provided for a frame of a rack that stores one or more electronic devices along a direction of arrangement of the one or more electronic devices, the lead being in contact with a fixing part when the one or more electronic devices are installed;a measure that measures an alternating wave of the alternating voltage flowing through the lead; anda specifier that specifies an installing position of an electronic device by referring to reference waveform information with a waveform of the alternating wave measured by the measure, the reference waveform information associating an installing state of installing the one or more electronic devices in the rack with a waveform pattern of the alternating wave measured under the installing state.2. The information processing apparatus according to claim 1 , wherein:the applier applies the alternating voltage to the lead from a first end of the lead; andthe measure measures a superimposed wave of an ...

SYSTEMS AND METHODS FOR DETECTING AND IDENTIFYING ARCING BASED ON NUMERICAL ANALYSIS

Method and system allowing more accurate detection and identification of unwanted arcing include novel processing of signal voltage representing recovered power-line current. In one implementation, arc-faults are detected based on numerical analysis where individual cycles of line voltage and current are observed and data collected during each cycle is processed to estimate likelihood of presence of arc-event within each individual cycle based on pre-defined number of arc-events occurring within pre-defined number of contiguous cycles. In another implementation, fast transient current spikes detection can be done by: computing difference values between consecutive line-current samples collected over a cycle, average of differences, and peak-to-peak value of line-current; comparing each difference value to average of difference; comparing each difference value to peak-to-peak value; and, based on calculation of composite of two comparisons, using thresholds to determine if arcing is present within processed cycle. 1. A method of detecting and identifying arcing comprising:obtaining first data indicative of line voltage and line current for a first cycle of a voltage waveform;obtaining second data indicative of line voltage and current for a second cycle of the voltage waveform subsequent to the first cycle;correlating the first data with data representative of a known arc reference cycle;correlating the second data with the data representative of the known arc reference cycle;correlating the first data with the second data; anddetermining presence of monotonic behavior in the root-mean-square (RMS) amplitude of the line current from data indicative of line voltage and line current for a plurality of cycle of a voltage waveform, the data comprising at least the first and second data.2. The method of detecting and identifying arcing of claim 1 , wherein the first and second cycles of the line voltage and current are observed with reference to zero-crossings on the ...

METHODS AND APPARATUSES FOR CHARACTERISTIC MANAGEMENT WITH SIDE-CHANNEL SIGNATURE ANALYSIS

Some embodiments described herein include an apparatus having a processor communicatively coupled to a memory. The processor is configured to monitor, at a characteristic controller, a first characteristic of an electronic device. The processor is then configured to receive side-channel signature analysis of the electronic device from a signature analyzer. The processor is configured to determine if the first characteristic of the electronic device has changed or will change in a predefined period of time based on the side-channel signature analysis. The processor is then configured to adjust a second characteristic of the electronic device and/or filtering characteristics such that the side-channel signature analysis reflects predefined side-channel behavior. 1. An apparatus; comprising:a memory; anda processor communicatively coupled to the memory,the processor configured to monitor a first characteristic of an electronic device,the processor configured to perform side-channel signature analysis of the electronic device,the processor configured to determine if the first characteristic of the electronic device has changed or will change in a predefined period of time based on the side-channel signature analysis,the processor configured to adjust a second characteristic of the electronic device in response to determining that the first characteristic has changed or will change in the predefined period of time such that the side-channel signature analysis corresponds to predefined side-channel behavior, the second characteristic being different from the first characteristic.2. The apparatus of claim 1 , wherein the processor is configured to monitor the first characteristic of the electronic device that is physically collocated with the apparatus.3. The apparatus of claim 1 , wherein the processor is configured to monitor the first characteristic of the electronic device that is physically remote from the apparatus.4. The apparatus of claim 1 , wherein:the processor ...

ENERGIZATION CONTROL DEVICE AND IMAGE FORMING APPARATUS

An energization control device includes a voltage detection unit, a control portion, and an energization switching unit. The control portion to which the first detection signal and the second detection signal are input from the voltage detection unit is configured to output a first energization signal if the first detection signal is input and output a second energization signal if the second detection signal is input. The control portion is configured to obtain a correction value based on a difference between a first period in which the first detection signal is input to the control portion and a second period in which the second detection signal is input to the control portion and to correct a timing of switching between the first energization signal and the second energization signal with the correction value. 1. An energization control device that executes energization control for an energization object included in an image forming apparatus , the energization control device comprising:a voltage detection unit connected to a commercial power source and comprising a switching element configured to output a first detection signal if a voltage of the commercial power source is higher than a threshold and output a second detection signal if the voltage is lower than the threshold;a control portion to which the first detection signal and the second detection signal are input from the voltage detection unit and configured to output a first energization signal if the first detection signal is input and output a second energization signal if the second detection signal is input; andan energization switching unit connected to the commercial power source and configured to supply electric power of the commercial power source to the energization object if the first energization signal is input and not to supply the electric power of the commercial power source to the energization object if the second energization signal is input,wherein the control portion is configured to ...

Controller IC with Zero-Crossing Detector and Capacitor Discharge Switching Element

An integrated circuit (IC) for controlling the discharge of a capacitor coupled across first and second input terminals of a power converter circuit, wherein the first and second terminals for receiving an ac line voltage. The IC includes a switching element coupled across the first and second input terminals and a detector circuit. The detector circuit including first and second comparators that produce first and second output signals responsive to a zero-crossing event of the ac line voltage. The first and second output signals being used to generate a reset signal coupled to a timer circuit responsive to the zero-crossing event. When the reset signal is not received within a delay time period, the timer circuit outputs a discharge signal that turns the switching element on, thereby discharging the capacitor. 1. An integrated circuit (IC) comprising:a power converter controller to regulate an output of a power converter, the power converter having first and second input terminals to receive an ac line voltage, an x-capacitor being coupled across the first and second input terminals;a regulator circuit configured to regulate a supply voltage provided to the power converter controller; a switching element for coupling across the first and second input terminals; and', first and second comparators, each having a first input respectively coupled to the first and second input terminals, the first and second comparators respectively producing first and second output signals responsive to a zero-crossing event of the ac line voltage;', 'circuitry coupled to receive the first and second output signals, the circuitry outputting a discharge signal when neither the first nor second output signals are received within a delay time period, the discharge signal being coupled to activate the switching element, when activated, the switching element providing a discharge path to discharge a voltage across the x-capacitor., 'a detector Circuit coupled to the switching element the ...

HIGH-RESOLUTION FET VDS ZERO-VOLT-CROSSING TIMING DETECTION SCHEME IN A WIRELESS POWER TRANSFER SYSTEM

Methods and apparatus for detecting zero-volt crossing in a field-effect transistor. A comparator compares a drain-to source voltage of the transistor to a threshold voltage. A gate voltage signal of the transistor is provided to a clock input of the comparator such that said gate voltage signal is used to latch a result of said comparison to an output of the comparator. A control function with respect to the transistor is performed based on the value of the comparator output. 1. Comparator circuitry comprising:{'sub': 'ds', '(a) a metal oxide semiconductor field effect transistor drain to source voltage, V, input;'}{'sub': 'TH-ds', '(b) a metal oxide semiconductor field effect transistor drain to source threshold voltage, V, input;'}{'sub': 'gs', '(c) a metal oxide semiconductor field effect transistor gate to source voltage, V, clock input;'}{'sub': 'TH-gs', '(d) a metal oxide semiconductor field effect transistor gate to source threshold voltage, V, input; and'}(e) an ON_LATE output; and(f) an OFF_LATE output.2. The comparator circuitry of including:{'sub': ds', 'ds', 'TH-ds, 'Vcomparator circuitry having inputs coupled to the metal oxide semiconductor field effect transistor drain to source voltage, V, input and the metal oxide semiconductor field effect transistor drain to source threshold voltage, V, input, and having a RISE_P output and a FALL_P output.'}3. The comparator circuitry of including:(a) first delay circuitry having an input coupled to the RISE_P output and a RISE_P_DLY output; and(b) second delay circuitry having an input coupled to the FALL_P output and a FALL_P_DLY output.4. The comparator circuitry of including a first flip flop having an input coupled to the RISE_P output claim 2 , a clock input claim 2 , and an output coupled to the OFF_LATE output.5. The comparator circuitry of including a second flip flop having an input coupled to the FALL_P output claim 2 , a clock input claim 2 , and an output coupled to the ON_LATE output.6. The ...

ADAPTIVE LEADING-EDGE BLANKING

In some examples, a control circuit is configured to control a transistor, and the control circuit includes a leading-edge detection unit configured to detect a time interval that corresponds to a leading-edge current spike through the transistor, wherein the time interval is independent of temperature. In some examples, the control circuit also includes a blanking unit configured to prevent the control circuit from turning off the transistor during the time interval. 1. A control circuit configured to control a transistor , the control circuit comprising:a leading-edge detection unit configured to detect a time interval that corresponds to a leading-edge current spike through the transistor, wherein the time interval is independent of temperature; anda blanking unit configured to prevent the control circuit from turning off the transistor during the time interval.2. The control circuit of claim 1 , a rising phase during which an electrical current through the transistor increases; and', 'a falling phase during which the electrical current through the transistor decreases, and, 'wherein the leading-edge current spike through the transistor comprises starting the time interval when the control circuit turns on the transistor; and', 'ending the time interval when the electrical current through the transistor increases after the falling phase., 'wherein the leading-edge detection unit is configured to detect the time interval by at least3. The control circuit of claim 1 , wherein the leading-edge detection unit is configured to detect the time interval of less than or equal to a predetermined time duration.4. The control circuit of claim 3 ,wherein the control circuit is configured to control the transistor by at least turning on the transistor to initiate the leading-edge current spike, start a timer when the control circuit turns on the transistor; and', 'stop the timer after the predetermined time duration, and, 'wherein the leading-edge detection unit is further ...

APPARATUSES AND METHODS FOR PARTIAL BIT DE-EMPHASIS

Apparatuses and methods for partial bit de-emphasis are provided. An example apparatus includes an output driver and control circuit. The output driver includes a pull-up circuit including one or more pull-up legs, and a pull-down circuit including one or more pull-down legs. The control circuit may be coupled to the output driver and configured to receive an input signal having a first logical value and a second logical value, and in response to determining the logical transition has occurred from the second logic value to the first logic value, cause the pull-up circuit and pull-down circuit respectively to enter a first state for a duration of a first portion of a bit period and to enter a second state for a duration of a second portion of the bit period preceding the first portion. 1. An apparatus comprising:an external terminal; and receive a first signal having a first logical value,', 'receive a second signal following the first signal, the second signal having a second logical value different from the first logical value, and', 'drive, in response to receiving the second signal, the external terminal from a first voltage to a second voltage by way of a third voltage, wherein the third voltage is a de-emphasized first voltage based at least in part on a de-emphasis time., 'an output driver coupled to the external terminal, the output driver configured to2. The apparatus of claim 1 , wherein the output driver de-emphasizes the first voltage for two bit periods.3. The apparatus of claim 1 , further comprising a variable delay circuit to introduce a delay interval claim 1 , wherein the delay interval determines the de-emphasis time.4. The apparatus of claim 3 , wherein the delay interval comprises a half bit period to produce a half bit period de-emphasis.5. The apparatus of claim 3 , wherein the variable delay circuit is configured to receive an input signal having first and second logic values claim 3 , and generate a delayed signal that is delayed relative to ...

PEAK SAMPLE CIRCUIT FOR AC VOLTAGE AND METHOD THEREOF

A peak sample circuit for AC voltage, including: a rectifier coupled to receive an AC voltage and to rectify the AC voltage to generate a rectified signal; a delay circuit coupled to receive the rectified signal and to delay the rectified signal to generate a delayed rectified signal; a comparison circuit coupled to receive the delayed rectified signal and to generate a square signal based on the comparison of the rectified signal and the delayed rectified signal; and a sample output circuit coupled to receive the rectified signal, wherein the sample output circuit samples the rectified signal under the control of the square signal and provides a peak sample signal representative of the peak value of the AC voltage. 1. A peak sample circuit for AC voltage , the peak sample circuit comprising:a rectifier having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal and the second input terminal are coupled to receive an AC voltage, the rectifier rectifies the AC voltage and provides a rectified signal at the output terminal;a delay circuit having an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the rectifier to receive the rectified signal, the delay circuit delays the rectified signal and provides a delayed rectified signal at the output terminal;a comparison circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the rectifier to receive the rectified signal, the second input terminal is coupled to the output terminal of the delay circuit to receive the delayed rectified signal, the comparison circuit compares the rectified signal with the delayed rectified signal and provides a square signal at the output terminal; anda sample output circuit has an input terminal, an output terminal and a control terminal, wherein the input terminal is coupled to the output ...

Control circuit and control method for outputting pulse width modulation control signal with zero-crossing detection

The present disclosure provides a control circuit, where the control circuit includes: a signal detection unit, a zero-crossing detection (ZCD) signal acquisition unit, a pulse width modulation (PWM) control signal generation unit, and a signal processing unit; where the signal detection unit, the ZCD signal acquisition unit, the PWM control signal generation unit and the signal processing unit are connected in cascade. The control circuit provided in the present disclosure reduces processing delay of a ZCD signal and improve signal a processing accuracy of a power factor correction (PFC) system.

ZERO-CROSSING DETECTION CIRCUIT

A zero-crossing detection circuit includes a zero-crossing detection unit arranged to compare a first monitoring target signal and a second monitoring target signal respectively input through diodes from a first node and a second node between which an AC signal is applied, so as to generate a first comparison signal, and a logic unit arranged to estimate a zero cross of the AC signal from the first comparison signal so as to generate a zero-crossing detection signal. The zero-crossing detection circuit preferably includes a monitoring unit arranged to adjust the first monitoring target signal and the second monitoring target signal to be suitable for input to the zero-crossing detection unit. The logic unit preferably counts a period of the first comparison signal and estimates a zero cross of the AC signal using a count value thereof. 1. A zero-crossing detection circuit comprising:a peak detection unit configured to detect a peak of a monitoring target signal input through a diode from an AC signal input terminal so as to generate a peak detection signal, anda zero-crossing detection unit configured to estimate a zero cross of the AC signal from the peak detection signal so as to generate a zero-crossing detection signal.2. The zero-crossing detection circuit according to claim 1 , further comprising a monitoring unit configured to adjust the monitoring target signal to be suitable for input to the peak detection unit.3. The zero-crossing detection circuit according to claim 1 , wherein the zero-crossing detection unit counts a period of the peak detection signal and estimates a zero cross of the AC signal using a count value thereof.4. The zero-crossing detection circuit according to claim 1 , further comprising:a comparing unit configured to compare the monitoring target signal with a plurality of threshold values so as to generate a plurality of comparison signals, anda waveform determination unit configured to detect whether or not both a rising edge and a ...

TIME DOMAIN INTEGRATED TEMPERATURE SENSOR

A time domain integrated temperature sensor described by the present invention adopts a shaped clock signal to control the charging time of capacitors, so that the capacitors generate charging time delay signals related to the cycle of an input clock, and a pulse signal related to pulse width, temperature and the cycle of the input clock is generated through logical XOR (Exclusive OR) operation on a time delay signal generated when the capacitors are charged by one way of PTAT (Proportional To Absolute Temperature) current in an above control manner and a time delay signal generated when the capacitors are charged by one way of CTAT (Complementary To Absolute Temperature) current in the same manner; then, the same input clock signal is adopted for quantifying the pulse width of the pulse signal, the relevance of the obtained quantization result and the cycle of the input clock is completely offset, namely, an output value of the temperature sensor is unrelated to the input clock signal, thereby solving the problem that the reading of the existing time domain integrated temperature sensor is inconsistent as the cycle of the clock signal changes and improving the precision of the time domain integrated temperature sensor to a certain degree. 1. A time domain integrated temperature sensor , comprising a PTAT (Proportional To Absolute Temperature) time delay circuit , a CTAT (Complementary To Absolute Temperature) time delay circuit , an XOR (Exclusive OR) gate and a counter , wherein two input ends of the XOR gate are respectively connected to an output end of the PTAT time delay circuit and an output end of the CTAT time delay circuit , an output end of the XOR gate is connected with an enable end of the counter , and a clock signal input end of the counter is connected to a clock input port of the temperature sensor;the PTAT time delay circuit comprises a PTAT current generation circuit, a first capacitor, a first switch and a first level-detection circuit, an output ...

LOW-ENERGY ACTUATOR (LEA) DIODE DETECTION

A circuit comprises a CLVS, a LEA coupled to the CLVS, and a peak detector coupled to the CLVS and the LEA, wherein the peak detector is a switch-based peak detector. A method comprises closing a first switch for a period of time to provide a current to an actuator, opening the first switch after the period, measuring, after the opening, a voltage associated with the actuator, and determining, based on the measuring and using an ADC, whether a diode is present in the actuator and coupled with a correct polarity, is missing, or is present in the actuator and coupled with an incorrect polarity. 1. A circuit comprising:a current-limited voltage source (CLVS);a low-energy actuator (LEA) coupled to the CLVS; anda peak detector coupled to the CLVS and the LEA, wherein the peak detector is a switch-based peak detector.2. The circuit of claim 1 , wherein the CLVS is a low-side CLVS.3. The circuit of claim 2 , wherein the CLVS comprises only one operational transconductance amplifier (OTA).4. The circuit of claim 3 , wherein the CLVS comprises a compensation capacitor coupled to the OTA claim 3 , wherein the compensation capacitor is a low-voltage compensation capacitor.5. The circuit of claim 1 , wherein the peak detector comprises a plurality of switches.6. The circuit of claim 5 , wherein the peak detector comprises two switches.7. The circuit of claim 1 , wherein the LEA comprises an inductor claim 1 , a resistor claim 1 , and a diode.8. The circuit of claim 7 , wherein the inductor and the resistor are coupled in series with each other claim 7 , and wherein the diode is coupled in parallel with the inductor and the resistor.9. The circuit of claim 8 , wherein the diode is a freewheeling Schottky diode.10. A diode detection circuit comprising:an actuator comprising an inductor and a resistor; anda peak detector coupled to the actuator, comprising a plurality of switches and a capacitor, and configured to couple to an analog-to-digital converter (ADC) to determine whether ...

METHOD FOR DETECTING SHORT-CIRCUITS IN A COIL

Method for detecting short-circuits in a coil in an electric machine, includes: a) arranging a coil in an air gap between the rotor and stator; c) recording signal curves generated by the coil; d) determining zero crossings of the curve and storing the times thereof; e) determining zero crossings of the curve corrected by an offset c, identifying a pair of immediately consecutive zero crossings, the time separation of which is longer than the minimum duration; f) in no pair is identified, repeating step e) until identified, wherein the offset c is varied from the zero point to a global extreme value of the curve; g) identifying at least one of the two stored times, which lies between and closest in time to the pair and; h) extracting two half-waves from the curve using times identified in step g), wherein each half-wave corresponds to half a revolution of the rotor. 1. A method for detecting winding short-circuits in an electric machine comprising:a) arranging a coil in an air gap arranged between the rotor and the stator of the electric machine;{'sub': 'min', 'b) calculating a minimum duration (t) of two immediately sequential zero crossings of a signal curve U(t) generated by means of the coil, taking the rotational frequency and the number of pole pairs of the electric machine into account;'}c) recording the signal curve U(t) generated by means of the coil during operation of the electric machine, having at least the duration of one revolution of the rotor;d) determining the zero crossings of the signal curve U(t) and storing the times of said zero crossings;{'sub': 'min', 'e) determining the zero crossings of the signal curve U(t)-c corrected by an offset c, and identifying at least one pair of immediately sequential zero crossings, the time interval of which is longer than the minimum duration (t), where c is not equal to zero;'}f) in the event that a pair is not identified in step e), repeating step e) until a pair is identified, wherein the offset c is varied ...

INVERTER DEVICE

An inverter device includes: a simulation output voltage generation unit that generates a simulation output voltage that corresponds to an instantaneous value of an alternating current output voltage and that has a waveform whose peak value is smaller than a peak value of the output voltage; a circuit that generates a peak value detection voltage by rectifying and smoothing the simulation output voltage; and a monitor circuit that compares the peak value detection voltage, or a voltage obtained by dividing the peak value detection voltage, with a reference voltage and transmits a feedback signal according to the result of the comparison to the control circuit. The control circuit changes a duty ratio of a switching signal for performing on/off control on the switching element in accordance with the feedback signal and controls the peak value detection voltage to keep a given value. 1. An inverter device that switches an input voltage by using a switching element on which on/off control is performed by a control circuit , flows an excitation current into an excitation winding of a resonance transformer during a period in which the switching element is on , and outputs an alternating current output voltage from an output winding of the resonance transformer during a period in which the switching element is off , the inverter device comprising:a simulation output voltage generation unit that generates a simulation output voltage that corresponds to an instantaneous value of the output voltage and that has a waveform whose peak value is smaller than a peak value of the output voltage;a circuit that generates a peak value detection voltage by rectifying and smoothing the simulation output voltage; anda monitor circuit that compares the peak value detection voltage, or a voltage obtained by dividing the peak value detection voltage, with a reference voltage and transmits a feedback signal according to the result of the comparison to the control circuit,wherein the control ...

POWER MANAGEMENT DEVICE AND POWER MANAGEMENT METHOD OF TOUCHABLE CONTROL SYSTEM

A power management device of a touchable control system includes a boost circuit boosting an output voltage according to an input voltage, a controlling signal for ballasting charging, and a controlling signal for boosting charging, a detection circuit detecting a predetermined value of the output voltage, a modulation circuit, and a loading circuit. The modulation circuit separately modulates the output voltage by the controlling signal for ballasting charging after the output voltage reaches the predetermined value and by the controlling signal for boosting charging before the output voltage reaches the predetermined value according to the detecting of the detection circuit. The loading circuit receives the reached predetermined value of the output voltage according to the modulation of the modulation circuit, wherein the controlling signal for boosting charging modulating the output voltage is more rapid than the controlling signal for ballasting charging modulating the output voltage. 1. A power management device of a touchable control system , comprising:a boost circuit boosting an output voltage according to an input voltage, a controlling signal for ballasting charging, and a controlling signal for boosting charging;a detection circuit detecting a predetermined value of the output voltage;a modulation circuit separately modulating the output voltage by the controlling signal for ballasting charging after the output voltage reaches the predetermined value and by the controlling signal for boosting charging before the output voltage reaches the predetermined value according to the detecting of the detection circuit;a loading circuit receiving the reached predetermined value of the output voltage according to the modulation of the modulation circuit; anda change-over switch electrically disconnecting the boost circuit and the loading circuit before the output voltage reaches the predetermined value;wherein the controlling signal for boosting charging modulating ...

DUAL CLOCK SIGNAL TO PULSE-WIDTH MODULATED SIGNAL CONVERSION CIRCUIT

Disclosed is a dual clock signal to pulse-width modulated signal conversion circuit, comprising: a first counter, an input end of which inputs a first clock signal, and an output end of which outputs a divided signal; an edge reset circuit, an input end of which inputs the divided signal, the output end of which outputs a first reset pulse signal and a second reset pulse signal, the first reset pulse signal being configured for resetting a second counter, and the second reset pulse signal being configured for resetting a third counter; a second counter, an input end of which inputs the second clock signal and the first reset pulse signal, and an output end of which outputs the first pulse-width modulated signal; a third counter, an input end of which inputs the second clock signal and the second reset pulse signal, and an output end of which outputs the second pulse-width modulated signal; a logic processing circuit, an input end of which inputs the first pulse-width modulated signal and the second pulse-width modulated signal, and an output end of which outputs a pulse-width modulated signal PWM_OUT. The disclosure offers high precision, system stability, and good anti-interference. 1. A dual clock signal to pulse-width modulated signal conversion circuit comprising:an input end configured to receive a first clock signal and a second clock signal, andan output end configured to provide a pulse-width modulated signal;wherein a first clock cycle of the first clock signal is greater than or equal to a second clock cycle of the second clock signal; and {'br': None, 'K×(T0/T1); and'}, 'a high level average duty cycle of the first pulse-width modulated signal is equal to at least one of a ratio of the second clock cycle of the second clock signal to the first clock cycle of the first clock signal cycle, multiplied by a proportionality coefficient, and 1 minus the ratio of the second clock cycle of the second clock signal to the first clock cycle of the first clock signal ...

MONITORING DEVICE AND METHOD FOR MONITORING A LINE SECTION USING A MONITORING DEVICE

A monitoring device is provided that includes a first line section with a first connection point and a second connection point spaced apart from the first connection point in the direction of the line, and with a control unit and with a first current sensing unit, having a current source. A first switch is inserted into the first connecting line and connects the first current source to the first connection point or disconnects it therefrom. In a first state the first switch is closed and the first current is impressed on the first line section and a first voltage determined by the amplitude of the actual current, and in a second state the first switch is open and a second voltage is determined, and the control unit is configured to ascertain the amplitude of the first actual current from the two voltages. 1. A monitoring device comprising:a first line section with a first connection point and a second connection point spaced apart from the first connection point in a direction of the line;a control unit;a first current sensing unit comprising:a first current source connectable to the first connection point via a first connecting line and connectable to the second connection point via a second connecting line, the first current source being configured to output a first current;a first switch having a control input, the first switch being inserted into the second connecting line and being configured to connect or disconnect the first current source to the second connection point; anda first differential amplifier having a first input, a second input, and an output, the first input being connectable to the first connection point via a third connecting line, the second input being connectable to the second connection point by a fourth connecting line;wherein the control unit is inserted between the output of the first differential amplifier and the control input of the first switch,wherein an actual current is passed through the first line section,wherein, in a first ...

POWER SUPPLY VOLTAGE TRANSITION COMPARISON CIRCUIT, POWER SUPPLY VOLTAGE TRANSITION COMPARISON METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT

The power supply voltage transition comparison circuit includes a comparator evaluation voltage setting circuit, a comparator, a voltage evaluation circuit, and an evaluation voltage setting value output circuit. The comparator evaluation voltage setting circuit generates a divided voltage of one of a power supply voltage and a reference voltage. The comparator compares the other of the power supply voltage and the reference voltage with the divided voltage. The voltage evaluation circuit evaluates the power supply voltage based on a result of a comparison between the other voltage and the divided voltage. The evaluation voltage setting value output circuit changes a ratio between the one voltage and the divided voltage based on a result of an evaluation of the power supply voltage. 1. A power supply voltage transition comparison circuit comprising:a comparator evaluation voltage setting circuit that generates a divided voltage of one of a power supply voltage and a reference voltage;a comparator that compares the other of the power supply voltage and the reference voltage with the divided voltage;a voltage evaluation circuit that evaluates the power supply voltage based on a result of a comparison between the other voltage and the divided voltage; andan evaluation voltage setting value output circuit that changes a ratio between the one voltage and the divided voltage based on a result of an evaluation of the power supply voltage.2. The power supply voltage transition comparison circuit according to claim 1 , further comprising:a voltage evaluation control circuit that determines whether or not a power supply voltage transition matches an expected voltage transition based on the result of the evaluation of the power supply voltage; anda setting circuit that holds a setting value of the expected voltage transition, the setting circuit being able to change the setting value.3. The power supply voltage transition comparison circuit according to claim 1 , further ...

Clock edge detection device and method

The present invention discloses a clock edge detection device capable of detecting the positive and negative edges of a target clock, comprising: a delay circuit for receiving the target clock and transmitting it; a register circuit coupled to the delay circuit for recording and outputting plural target clock levels in accordance with a working clock; a positive edge detection circuit including a plurality of positive edge detectors coupled to the register circuit for detecting the positive edge of the target clock; and a negative edge detection circuit including a plurality of negative edge detectors coupled to the register circuit for detecting the negative edge of the target clock, wherein the positive edge detection circuit is operable to perform a logic operation to the target clock levels while the negative edge detection circuit is operable to perform a different logic operation to the target clock levels. 1. A clock edge detection device capable of detecting the positive and negative edges of a target clock , comprising:a delay circuit including a plurality of delay units connected in series for receiving and transmitting the target clock;a register circuit including a plurality of registers coupled to the delay circuit for recording and outputting target clock levels of the target clock in accordance with a working clock, wherein each of the registers includes a data input end for receiving the target clock from one of the delay units, a data output end, and a working clock reception end for receiving the working clock;a positive edge detection circuit including a plurality of positive edge detectors coupled to the data output ends of the register circuit for detecting the positive edge of the target clock, wherein each of the positive edge detectors includes a positive edge detection unit for generating a positive edge detection value according to the target clock levels from adjacent two of the registers; anda negative edge detection circuit including a ...

Methods and Apparatus for Peak-Voltage Measurement of AC Signals

In described examples, an apparatus includes: an input terminal for receiving an alternating current voltage signal; a clamping circuit coupled to the input terminal outputting a clamped voltage signal that is constrained in magnitude; a first comparator coupled to the clamped voltage signal outputting a first compare signal when the clamped voltage signal is a positive voltage that exceeds a positive threshold; and a second comparator coupled to the clamped voltage signal outputting a second compare signal when the clamped voltage signal is a negative voltage that exceeds a negative threshold. The apparatus includes a timer circuit coupled to the first and second compare signal outputting a time duration signal corresponding to a time between the first and second compare signals; and a logic circuit coupled to the time duration output signal determining a peak voltage of the alternative current voltage signal responsive to the time duration output signal. 1. An apparatus , comprising:an input terminal for receiving an alternating current voltage signal;a clamping circuit coupled to the input terminal, the clamping circuit configured to output a clamped voltage signal that is constrained between a positive voltage magnitude and a negative voltage magnitude;a first comparator coupled to the clamped voltage signal, and configured to output a first compare signal when the clamped voltage signal is a positive voltage that exceeds a positive threshold reference voltage;a second comparator coupled to the clamped voltage signal and configured to output a second compare signal when the clamped voltage signal is a negative voltage that exceeds a negative threshold reference voltage;a timer circuit coupled to the first compare signal and coupled to the second compare signal and coupled to a clock signal, and configured to output a time duration output signal corresponding to a time interval between the first and second compare signals; anda logic circuit coupled to the time ...

REFRIGERATOR

A refrigerator according to an embodiment of the present invention includes a power input part through which power is input from a UPS device connected to a commercial power source and an auxiliary power source; a voltage sensor configured to sense a voltage of the power input through the power input part; and a control part configured to analyze a voltage signal sensed by the voltage sensor and to determine whether the input power is commercial power or auxiliary power. 137-. (canceled)38. A refrigerator comprising:a power input part connected to a UPS device which is connected to an auxiliary power source and a commercial power source and selectively supplies power;a compressor;a voltage sensor configured to sense a voltage input through the power input part; anda control part configured to analyze a voltage signal sensed by the voltage sensor and to determine whether the input power is commercial power or auxiliary power,wherein the control part performs a primary determination through an analysis of the sensed voltage signal, performs a secondary determination through the analysis of the voltage signal sensed before and after driving of the compressor when it is determined that the power is not the auxiliary power, and determines whether the input power is the commercial power or the auxiliary power.39. The refrigerator of claim 38 , wherein claim 38 , in the primary determination claim 38 , when a waveform of the voltage signal sensed by the voltage sensor is a square wave claim 38 , the control part determines that the input power is the auxiliary power.40. The refrigerator of claim 39 , wherein claim 39 , in the secondary determination claim 39 , when a peak value of a voltage waveform of the compressor is dropped claim 39 , the control part determines that the input power is the auxiliary power.41. The refrigerator of claim 39 , wherein claim 39 , in the secondary determination claim 39 , when amplitude of a third harmonic wave after the driving of the ...

SEMICONDUCTOR MEMORY APPARATUS

A semiconductor memory apparatus includes a bank; a temperature sensor configured to generate a temperature voltage of which voltage level is changed according to a temperature variation of the bank; and a timing control block configured to control a timing of a signal to be inputted to the bank, according to the voltage level of the temperature voltage. 1. A semiconductor comprising:a first circuit;a second circuit;a first temperature sensor configured to generate a first temperature voltage in response to a temperature of the first circuit;a second temperature sensor configured to generate a second temperature voltage in response to a temperature of the second to circuit;a signal transfer block configured to output a signal to one of the first circuit and the second circuit in response to an circuit select signal; anda timing control block configured to control a timing of the signal in response to the first and second temperature information.2. The semiconductor according to claim 1 ,wherein the first temperature sensor generates the first temperature voltage of which voltage level increases as a temperature of the first circuit increases, andwherein the second temperature sensor generates the second temperature voltage of which voltage level increases as a temperature of the second circuit increases.3. The semiconductor according to claim 1 ,wherein the timing control block determines whether to delay the signal, according to the voltage level of the first temperature voltage, and outputs the signal which is determined in terms of whether to be delayed or not, to the first circuit, andwherein the timing control block determines whether to delay the signal, according to the voltage level of the second temperature voltage, and outputs the signal which is determined in terms of whether to be delayed or not, to the second circuit.4. The semiconductor memory apparatus according to claim 3 , wherein the timing control block comprises:a comparison signal generation ...

Measuring delay between signal edges of different signals using an undersampling clock

A system may measure a first sample, of a first signal, using an undersampling signal. The system may measure a second sample, of a second signal, using the undersampling signal. The undersampling signal may have a frequency that is based on a frequency of the first signal or a frequency of the second signal. The system may detect, based on measuring the first sample, a first edge of the first signal. The system may detect, based on measuring the second sample, a second edge of the second signal. The system may determine a delay, associated with the first signal and the second signal, based on detecting the first edge, based on detecting the second edge, based on a first cycle time of the undersampling signal, and based on a second cycle time of the first signal or the second signal.

SEMICONDUCTOR DEVICE

A semiconductor device includes an input determination circuit. The input determination circuit includes: a comparator that is driven based on a first reference potential and includes an input voltage terminal and a reference voltage terminal; a reference voltage generation circuit that inputs a reference voltage that is generated from a connection point between a constant current source and a resistor to the reference voltage terminal of the comparator, the constant current source and the resistor being interposed between a second reference potential that is separated from the first reference potential and a third potential that is higher than the first reference potential and the second reference potential; and a first low pass filter that is interposed between a signal input system that is connected to the input voltage terminal of the comparator and the second reference potential. 1. A semiconductor device comprising a comparator that is driven based on a first reference potential and includes an input voltage terminal and a reference voltage terminal;', 'a reference voltage generation circuit that inputs a reference voltage that is generated from a connection point between a constant current source and a resistor to the reference voltage terminal of the comparator, the constant current source and the resistor being interposed between a second reference potential that is separated from the first reference potential and a third potential that is higher than the first reference potential and the second reference potential; and', 'a first low pass filter that is interposed between a signal input system that is connected to the input voltage terminal of the comparator and the second reference potential., 'an input determination circuit including2. A semiconductor device comprising a comparator that is driven based on a first reference potential and includes an input voltage terminal and a reference voltage terminal;', 'a reference voltage generation circuit that ...

SLOPE DETECTOR FOR VOLTAGE DROOP MONITORING

Techniques for a slope detector for voltage droop monitoring are described herein. An aspect includes receiving an input voltage by a circuit. Another aspect includes producing, by the circuit, a filtered offset voltage based on the input voltage. Another aspect includes determining whether the input voltage is lower than the filtered offset voltage. Yet another aspect includes, based on the input voltage being lower than the filtered offset voltage, indicating an imminent voltage droop condition in the input voltage. 1. A method comprising:receiving an input voltage by a circuit;producing, by the circuit, a filtered offset voltage based on the input voltage;determining whether the input voltage is lower than the filtered offset voltage; andbased on the input voltage being lower than the filtered offset voltage, indicating, by the circuit, an imminent voltage droop condition in the input voltage.2. The method of claim 1 , wherein producing the filtered offset voltage based on the input voltage comprises:introducing an offset into the input voltage by an offset circuit comprising a resistor and a current source; andfiltering the input voltage including the offset by a low pass filter comprising the resistor and a capacitor.3. The method of claim 1 , the method comprising:based on the input voltage being higher than the filtered offset voltage, indicating, by the circuit, no imminent voltage droop condition in the input voltage.4. The method of claim 1 , the circuit comprising:a comparator, the comparator comprising a first terminal and a second terminal, and a comparator output that outputs a voltage droop detection signal based on whether the input voltage is lower than the filtered offset voltage; anda switch that is connected to the second terminal.5. The method of claim 4 , wherein determining whether the input voltage is lower than the filtered offset voltage comprises connecting the first terminal to the input voltage claim 4 , and connecting the second ...

METHOD AND APPARATUS FOR MODULATING AMPLIFIER SUPPLY VOLTAGE FOR REDUCING POWER DISSIPATION

A circuit to modulate the power supply to track input or output voltages provided to or output by a plurality of amplifiers to reduce power dissipation is provided. The circuit may include a peak detection circuit configured to receive a plurality of voltages respectively corresponding to the plurality of amplifiers, and to detect and output information regarding a maximum instantaneous voltage from the received plurality of voltages, and a summing circuit configured to output a sum of the information regarding the maximum instantaneous voltage and an amplifier headroom voltage. A reference voltage may be provided for the supply voltage responsive to the output sum. The circuit may also include a scaling circuit configured to scale the output sum, and the reference voltage may be a scaled reference voltage output by the scaling circuit. 1. A circuit for modulating a power supply voltage provided to a plurality of amplifiers , the circuit comprising:a peak detection circuit configured to receive respective analog input voltages provided to the plurality of amplifiers, and to detect and output information regarding a maximum instantaneous analog input voltage from the received respective analog input voltages; anda summing circuit configured to output a sum of the information regarding the maximum instantaneous analog input voltage output from the peak detection circuit and an amplifier headroom voltage,wherein a reference voltage is provided for the power supply voltage responsive to the output sum.2. The circuit of claim 1 , further comprising a scaling circuit configured to scale the output sum claim 1 , wherein the reference voltage provided for the power supply voltage is responsive to an output of the scaling circuit.3. The circuit of claim 1 , wherein the information regarding the maximum instantaneous analog input voltage is the maximum instantaneous analog input voltage.4. The circuit of claim 1 , wherein the amplifier headroom voltage is a predetermined ...

Dead Time Control Circuit for a Level Shifter

Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors. Timing of control signals can be adjusted via internal and/or external components so as to minimize shoot trough currents in the high voltage devices. A DC/DC power conversion implementation from high input voltage to low output voltage using a novel level shifter which uses only low voltage transistors is also provided. Also presented is a level shifter in which floating nodes and high voltage capacitive coupling and control enable the high voltage control with low voltage transistors. 1. (canceled)2. A dead time control circuit configured to generate , from an input square wave signal , a high side (HS) timing control signal and a low side (LS) timing control signal for respective control of a high side (HS) device and a low side (LS) device arranged in a stacked configuration , the dead time control circuit comprising:a first processing path comprising respective two edge delay circuits arranged in series connection, each edge delay circuit of the first processing path configured to delay a respective one of a rising edge and a falling edge of the input square wave signal to generate therefrom a first edge adjusted pulse signal of the HS timing control signal; anda second processing path comprising respective two edge delay circuits arranged in series connection, each edge delay circuit of the second processing path configured to delay a respective one of the rising edge and the falling edge of the input square wave signal independently from the first processing path to generate therefrom a second ...

Mixed-Mode Circuits

An apparatus for processing signals, arranged on an integrated circuit, comprises at least one analog input port that receives an input signal from outside of the integrated circuit, and a detector that detects an operation state of the apparatus based on the input signal. The detector provides at least one digital control/enable signal, which is dependent on the operation state of the apparatus, to another apparatus arranged on the integrated circuit. 1. An apparatus for processing signals , the apparatus being arranged on an integrated circuit , the apparatus comprising:at least one analog input port for receiving an input signal from outside of the integrated circuit; anda detector arranged to detect an operation state of the apparatus based on the input signal,wherein the detector is arranged to provide at least one digital control/enable signal,the at least one digital control/enable signal being dependent on the operation state of the apparatus, andwherein the detector is arranged to provide the at least one digital control/enable signal to another apparatus arranged on the integrated circuit.2. The apparatus of claim 1 , whereinthe at least one analog input port is arranged to be connectable to different sources outside of the integrated circuit in accordance with the operation state of the apparatus, and/orthe detector is arranged to detect a signal level from the input signal, and provide the at least one digital control/enable signal dependent on the signal level, on at least one output path of the detector, within the integrated circuit, to the other apparatus.3. The apparatus of claim 1 , wherein the detector is arranged to convert the input signal to a DC voltage signal claim 1 , detect a level of the DC voltage signal claim 1 , and provide the at least one digital control/enable signal dependent on the level of the DC voltage signal.4. The apparatus of claim 1 , further comprising:a driving circuit for processing signals input from a signal source, the ...

HIGH-PERFORMANCE ZERO-CROSSING DETECTOR

A zero-crossing detection circuit includes a comparator and circuitry. The comparator produces an output signal that is indicative of zero-crossing events in an input Alternating Current (AC) waveform. The circuitry may be configured to feed the comparator with first and second rails voltages, and to progressively increase the rails voltages during time intervals derived from the input AC waveform, so as to feed the comparator with target values of the rails voltages in time-proximity to the zero-crossing events. The circuitry may be configured to compensate for an error in detecting the zero crossing events caused by differences in amplitude of the input AC waveform, by correcting the input AC waveform provided to the comparator. The circuitry may be configured to activate the comparator during time intervals preceding respective anticipated times of the zero-crossing events, and to deactivate the comparator at least once during time periods other than the time intervals. 1. A zero-crossing detection circuit , comprising:a comparator, which is configured to produce an output signal that is indicative of zero-crossing events in an input Alternating Current (AC) waveform; andcircuitry, which is configured to feed the comparator with first and second rails voltages, and to progressively increase the rails voltages during time intervals that are derived from the input AC waveform, so as to feed the comparator with target values of the rails voltages in time-proximity to the zero-crossing events.2. The circuit according to claim 1 , wherein the circuitry comprises:a short-term power supply for producing the rails voltages; anda control circuit that is configured to charge the short-term power source during time periods that precede the respective time intervals, and to cause the short-term power supply to increase the rails voltages during the time intervals.3. The circuit according to claim 2 , wherein the circuitry is configured to consume energy from the short-term ...

HIGH VOLTAGE OFFSET DETECTION CIRCUIT

A high voltage half-bridge driver circuit has a high voltage terminal and a floating node to be connected with a high side switch therebetween. When turning on the high side switch, a high voltage offset detection circuit detects a voltage related to the voltage at the floating node for triggering a zero voltage switching signal. 1. A high voltage offset detection circuit for detecting a voltage at a floating node of a high voltage half-bridge driver circuit which includes a high voltage terminal for a high side switch to be connected between the high voltage terminal and the floating node , a low voltage terminal for a low side switch to be connected between the low voltage terminal and the floating node , a bootstrap capacitor connected between a high side power source and the floating node , a high voltage driver to provide a first control signal to control the high side switch , and a low voltage driver to provide a second control signal to control the low side switch , the high voltage offset detection circuit comprising:a high voltage device having an input terminal to receive a first voltage related to the voltage at the floating node, an output terminal having a second voltage, a control terminal, and a parasitic capacitance existing between the input terminal and the output terminal of the high voltage device;a zero voltage switching generator connected to the output terminal of the high voltage device, operative to detect the second voltage when turning on the high side switch or turning off the low side switch, for triggering a zero voltage switching signal according to the detected second voltage and a threshold related to a power source voltage of the low voltage driver; anda controller connected to the control terminal of the high voltage device, operative to provide a third control signal for selectively turning off the high voltage device when the zero voltage switching generator detects the second voltage;wherein the input terminal of the high ...

COMMUNICATION CIRCUIT APPARATUS AND TRANSCEIVER HAVING THE SAME

A communication circuit apparatus includes: multiple level shift circuits, each of which receives an input signal corresponding to a respective communication bus; an activation comparator for generating an activation signal when the input signal is input into one of the level shift circuits, and a level of the input signal exceeds a predetermined threshold; multiple input current voltage conversion circuits, each of which is arranged together with a respective level shift circuit, converts the input signal to a voltage signal, and outputs the voltage signal as an identification signal; and an identification circuit for identifying one of the communication busses based on the identification signal, which is output from one of the input current voltage conversion circuits. The one of the communication busses corresponds to the one of the level shift circuits, in which the input signal is input. 1. A communication circuit apparatus comprising:a plurality of level shift circuits, each of which receives an input signal corresponding to a respective communication bus;an activation comparator for generating an activation signal when the input signal is input into one of the level shift circuits, and a level of the input signal exceeds a predetermined threshold;a plurality of input current voltage conversion circuits, each of which is arranged together with a respective level shift circuit, converts an input current of the input signal to a voltage signal when the input signal is input into the respective level shift circuit, and outputs the voltage signal as an identification signal; andan identification circuit for identifying one of the communication busses based on the identification signal, which is output from one of the input current voltage conversion circuits,wherein the one of the communication busses corresponds to the one of the level shift circuits, in which the input signal is input.2. The communication circuit apparatus according to claim 1 , further ...

VOLTAGE PEAK DETECTION CIRCUIT AND DETECTION METHOD

In one embodiment, a voltage peak detection circuit can include: (i) a voltage coupling circuit configured to inductively couple an input inductor voltage of a switching power supply, and to generate a first voltage that represents a DC input voltage of the switching power supply; (ii) a voltage conversion circuit configured to receive the first voltage, and to generate a second voltage that is proportional to the first voltage; and (iii) a holding circuit configured to hold a peak of the second voltage to generate a peak voltage signal that represents peak information of the DC input voltage. 1. A voltage peak detection circuit , comprising:a) a voltage coupling circuit configured to inductively couple an input inductor voltage of a switching power supply, and to generate a first voltage that represents a DC input voltage of said switching power supply;b) a voltage conversion circuit configured to receive said first voltage, and to generate a second voltage that is proportional to said first voltage; andc) a holding circuit configured to hold a peak value of said second voltage to generate a peak voltage signal that represents a peak value of said DC input voltage, wherein a time constant of said holding circuit is configured to meet a transient response requirement of said peak value of said DC input voltage.2. The voltage peak detection circuit of claim 1 , wherein said voltage coupling circuit comprises an auxiliary inductor coupled to an input inductor of said switching power supply claim 1 , and said first voltage is generated based on an induced voltage of said auxiliary inductor.3. The voltage peak detection circuit of claim 1 , wherein said voltage conversion circuit comprises:a) a voltage-current conversion circuit configured to receive said first voltage, and to generate a first current based on said first voltage;b) said voltage-current conversion circuit being configured to generate a mirror current by mirroring said first current; andc) a current- ...

BUFFER CONTROL CIRCUIT AND MULTI-CHIP PACKAGE INCLUDING THE SAME

A buffer control circuit includes: an activation control block suitable for generating a buffer activation control signal by detecting a first input of a repeatedly provided chip select signal; and a buffer suitable for buffering the chip select signal in response to the buffer activation control signal after the generation of the buffer activation control signal. 1. A buffer control circuit , comprising:an activation control block suitable for generating a buffer activation control signal by detecting a first input of a repeatedly provided chip select signal; anda buffer suitable for buffering the chip select signal in response to the buffer activation control signal after the generation of the buffer activation control signal.2. The buffer control circuit of claim 1 , wherein the activation control block generates the buffer activation control signal claim 1 , which is enabled a predetermined time after the first input of the chip select signal.3. The buffer control circuit of claim 2 , wherein the activation control block includes:a shift unit suitable for generating a plurality of control signals in response to a clock signal by sequentially shifting the chip select signal;a latch unit suitable for latching the chip select signal and the control signals in response to a last one among the control signals;a clock control unit suitable for generating a plurality of clock signals having different enabling time sections in response to an output signal of the latching unit;an input control signal generation unit suitable for generating a plurality of input control signals by sequentially shifting the chip select signal in response to the plurality of dock signals; andan activation control signal generation unit suitable for generating the buffer activation control signal by detecting rising and falling edges of each of the input control signals.4. The buffer control circuit of claim 3 , wherein the activation control signal generation unit includes a toggle ...

ELECTRIC WORKING MACHINE AND METHOD FOR SMOOTHING AC POWER SUPPLIED THERETO

An electric working machine according to one aspect of the present disclosure comprises a motor, a rectifier circuit, a capacitor, a series switching element, a resistive element, a drive circuit, a peak voltage value acquirer, and a controller. The capacitor smooths power rectified by the rectifier circuit. The series switching element is coupled in series with the capacitor. The resistive element is coupled in parallel with the series switching element. The controller brings the series switching element into conduction in a case where AC power is inputted to the rectifier circuit and where a specified conducting condition based on a peak voltage value acquired by the peak voltage value acquirer is satisfied. 1. An electric working machine comprising:a motor;a rectifier circuit configured to rectify an AC power inputted from an AC power supply and to output a rectified power, the AC power fluctuating periodically;a capacitor configured to be charged by the rectified power outputted from the rectifier circuit and to smooth the rectified power;a series switching element, which is a switching element coupled in series with the capacitor;a resistive element coupled in parallel with the series switching element;a drive circuit configured to drive the motor based on a power smoothed by the capacitor;a peak voltage value acquirer configured to acquire a peak voltage value, which is a maximum absolute value of a voltage of the AC power; anda controller configured to bring the series switching element into conduction in a case where the AC power is inputted to the rectifier circuit and where a specified conducting condition based on the peak voltage value acquired by the peak voltage value acquirer is satisfied.2. The electric working machine according to claim 1 , further comprising a capacitor voltage value acquirer configured to acquire a capacitor voltage value claim 1 , which is a value of a charging voltage across the capacitor claim 1 ,wherein the conducting ...

Low loss current sensor and power converter using the same

A low-loss current sensor for use with a circuit containing a capacitor to sense a current flowing into a node in the circuit is provided. The current sensor includes a differentiator circuit having an input connected to the circuit capacitor and adapted to generate an output which is proportional to the current flowing through the circuit capacitor. The novel use of a capacitive current divider allows the sensor to sense current with virtually no power dissipation.

SWITCHING MODE POWER AMPLIFIER WITH LOAD ISOLATION

A power amplifier device includes first and second pairs of semiconductor switches, transformers, and a zero-crossing detection circuit for detecting a zero voltage crossing of an analog input signal. The switches of the first pair receive a respective positive and negative component of the input signal. The transformers store energy from the positive and negative components, respectively. Each transformer releases accumulated energy when the respective switch of the first pair turns off The switches of the second pair have opposite switching states and are connected between a respective transformer and a load, e.g., a transducer, speak, or motor. Each switch receives released energy from the respective transformer. A switching state of each switch of the second pair changes in response to a detected zero voltage crossing of the input signal to transfer the released energy to the load. A system includes the device and the load. 1. A switching mode power amplifier device for delivering power to a load , the switching mode power amplifier device comprising:a first pair of semiconductor switches, including first and second semiconductor switches each configured to receive a respective positive and negative component of a modulated input signal, wherein a switching rate of the first and second semiconductor switches equals or exceeds a carrier frequency of the modulated input signal;first and second transformers respectively connected to the first and second semiconductor switches;a second pair of semiconductor switches, including third and fourth semiconductor switches having opposite switching states, wherein the third and fourth semiconductor switches are electrically connected between a respective one of the first and second transformers and the load, and are operable for receiving released energy from the respective transformer, wherein a switching state of the third and fourth semiconductor switches changes in response to a detected zero voltage crossing of the ...

SEMICONDUCTOR DEVICE

A semiconductor device detects an edge of input data input into a data retention circuit to which a clock signal is supplied, resets a first count value obtained by counting an edge detection frequency with a clock signal, resets a second count value obtained by counting the edge detection frequency with an inverted clock signal, and thereby detects an abnormality of the clock signal in accordance with a situation that either of the first count value and the second count value has reached a value indicative of an overflow state. 1. A semiconductor device , comprising:an edge detection circuit that detects an edge of input data;a first counter that is reset with a clock signal used to fetch the input data in a data retention circuit and counts an edge detection frequency of the edge detection circuit;a second counter that is reset with an inverted clock signal that is inverted from the clock signal and counts the edge detection frequency of the edge detection circuit, anda clock signal stop decision circuit that outputs a clock signal stop detection signal in accordance with a situation that one of the first counter and the second counter has reached an overflow state.2. The semiconductor device according to claim 1 ,wherein the second counter is larger by about 3 or more than the first counter in count value with which the second counter reaches the overflow state.3. The semiconductor device according to claim 1 ,wherein the edge detection circuit detects the edge of the input data in accordance with occurrence of a difference in logical level between signals at input and output terminals of the data retention circuit.4. The semiconductor device according to claim 1 ,wherein when the count value has reached a value that causes the overflow state, the first counter and the second counter each retains the logical level of the clock signal stop detection signal until supply of the clock signal is resumed.5. The semiconductor device according to claim 1 ,wherein the ...

Phase Shifter Chip Radio Frequency Self-Test

A method for operating a phase shifter chip RF self-test. The method includes outputting, by control hardware, a first signal from a phased locked loop to a pre-amplifier and an input peak detector, outputting, by the control hardware, a second signal from the pre-amplifier to a device under test, selecting, by the control hardware, a target level, and adjusting, by the control hardware, a pre-amplifier gain of the pre-amplifier to cause the input peak detector value to approximately match the target level. The input peak detector is configured to output an input peak detector value based on the first signal. 1. A method comprising:outputting, by control hardware, a first signal from a phased locked loop to a pre-amplifier and an input peak detector, wherein the input peak detector is configured to output an input peak detector value based on the first signal;outputting, by the control hardware, a second signal from the pre-amplifier to a device under test;selecting, by the control hardware, a target level; andadjusting, by the control hardware, a pre-amplifier gain of the pre-amplifier to cause the input peak detector value to approximately match the target level.2. The method of claim 1 , further comprising:adjusting, by the control hardware, a precision variable gain adjuster connected to the pre-amplifier; andmeasuring an output peak detector value of an output peak detector connected to an output of the device under test.3. The method of claim 2 , further comprising adjusting claim 2 , by the control hardware claim 2 , a device under test gain of the device under test until the output peak detector value approximately matches the target level.4. The method of claim 3 , further comprising:stopping, by the control hardware, all signals to the pre-amplifier and the device under test;measuring, by the control hardware, a current input peak detector value of the input peak detector as an input peak detector offset; andmeasuring a current output peak detector value ...

CONTROL CIRCUIT FOR BUCK-BOOST POWER CONVERTER WITH STABLE BOOTSTRAP VOLTAGE REFRESH

A buck-boost power converter and a control circuit for the buck-boost converter. The buck-boost power converter includes a first power switch and a second power switch coupled in series between an input port and a reference ground, and a third power switch and a fourth power switch coupled in series between an output port and the reference ground. The control circuit receives a pulse skipping control signal and a zero-crossing indication signal, and controls the second power switch and/or the third power switch to turn on when the pulse skipping control signal controls the buck-boost power converter to enter into a pulse skipping mode and the zero-crossing indication signal indicates that an output inductor current of the buck-boost power converter crosses zero. 1. A control circuit for a buck-boost power converter having a first power switch and a second power switch coupled in series between an input port and a reference ground and a third power switch and a fourth power switch coupled in series between an output port and the reference ground , comprising:a logic control module configured to receive a pulse skipping control signal and a zero-crossing indication signal, and to control the second power switch to turn on or to control the third power switch to turn on or to control both the second power switch and the third power switch to turn on when the pulse skipping control signal controls the buck-boost power converter to enter into a pulse skipping mode and the zero-crossing indication signal indicates that an output inductor current of the buck-boost power converter crosses zero.2. The control circuit of claim 1 , further comprising:a pulse skipping control module configured to receive a load indication signal indicative of the load status of the buck-boost power converter, and to compare the load indication signal with a pulse skipping threshold to provide the pulse skipping control signal, wherein the pulse skipping control signal is configured to control ...