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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 5620. Отображено 200.
27-12-1999 дата публикации

СПОСОБ ФОРМИРОВАНИЯ ИМПУЛЬСОВ КАЧАЮЩЕЙСЯ ЧАСТОТЫ И УСТРОЙСТВО ДЛЯ ЕГО ОСУЩЕСТВЛЕНИЯ

Номер: RU2143779C1

Изобретение относится к радиотехнике и может быть использовано в широкополосных приемопередающих системах, а также в измерителях частотных характеристик радиоустройств. Техническим результатом предлагаемого способа формирования импульсов качающейся частоты является расширение верхнего частотного диапазона изменения выходной частоты и функциональных возможностей путем создания новых режимов работы, в которых обеспечивается низкочастотная модуляция и исключение прохождения выходного сигнала. Расширение верхнего частотного диапазона решается за счет выполнения задающего генератора в виде программируемой линии задержки с положительной обратной связью. Цифровой генератор качающейся частоты содержит задающий генератор, два управляемых делителя частоты, реверсивный счетчик, первый счетчик, который выполнен реверсивным, дифференцирующую цепь, счетчик, четыре цифровых компаратора, мультиплексор, счетный триггер, три схемы И, RS-триггер, память констант и усилитель мощности. 2 с.п. ф-лы, 1 ил.

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27-10-2009 дата публикации

ФОРМИРОВАТЕЛЬ ИМПУЛЬСОВ

Номер: RU2371843C1

Изобретение относится к телекоммуникациям и позволяет формировать ультракороткие (менее 1 нс) электромагнитные импульсы в моно- и биполярном режимах при помощи сегнетоэлектрической линии передачи. Формирователь импульсов содержит нелинейную линию передачи и закороченный отрезок линейной линии передачи на ее выходе. В качестве материала нелинейной линии использован сегнетоэлектрик в параэлектрическом состоянии с нанесенными металлическими электродами, а закороченный отрезок линейной линии передачи содержит сегнетоэлектрический конденсатор. К нелинейной линии через фильтры нижних частот подключен источник постоянного напряжения смещения. Технический результат - расширение номенклатуры и функциональных возможностей формирователя УК импульсов, за счет создания формирователя УК импульсов на основе сегнетоэлектрика, способного формировать импульсы как в моно-, так и в биполярном режимах. 3 з.п. ф-лы, 15 ил.

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10-07-2001 дата публикации

ГЕНЕРАТОР ИМПУЛЬСОВ С ЦИФРОВОЙ ПЕРЕСТРОЙКОЙ ПЕРИОДА

Номер: RU2170490C1
Автор: Чулков В.А.

Изобретение относится к генерированию импульсов и может использоваться в цифровых устройствах фазовой синхронизации. Генератор импульсов с цифровой перестройкой периода содержит инвертор, секционированную линию задержки, мультиплексор, блок преобразования цифрового кода периода. Достигаемый технический результат - расширение диапазона перестройки частоты. 1 з.п. ф-лы, 1 ил.

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10-01-1998 дата публикации

МУЛЬТИПЛЕКСНАЯ СИНХРОННАЯ/АСИНХРОННАЯ ШИНА ДАННЫХ

Номер: RU2101865C1
Принадлежит: Моторола, Инк. (US)

Мультиплексная синхронная/асинхронная шина данных, которая имеет три линии связи (T, R, С 109), используемые для передачи двунаправленных синхронных данных между по крайней мере двух устройств данных с относительно низкой скоростью передачи. Полудуплексные асинхронные данные передаются на более высокой скорости передачи данных по одной из трех линий (R) шины, когда другие линии шины (T, C) удерживаются в состоянии логического высокого потенциала. 4 с. и 16 з.п. ф-лы, 12 ил.

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10-01-1998 дата публикации

УСТРОЙСТВО УДВОЕНИЯ ЧАСТОТЫ СЛЕДОВАНИЯ ИМПУЛЬСОВ

Номер: RU2101856C1

Изобретение относится к радиотехнике, а именно к измерительной технике, и в частности может быть использовано в технике радиосвязи, например в синтезаторах частоты приемопередающих установок с программной перестройкой рабочей частоты (ППРЧ) в качестве умножителей частоты следования импульсов. Целью изобретения является создание устройства удвоения частоты следования импульсов, обеспечивающее повышение стабильности и уменьшение времени на формирование удвоенной частоты следования импульсов. Поставленная цель достигается тем, что устройство включает первый 1 и второй 2 элементы НЕ, первый 3 и второй 4 элементы И, одновибратор 5 и элемент ИЛИ 6. При такой схеме удвоение входной последовательности импульсов осуществляется только путем последовательного выполнения логических операций - умножения, сложения и отрицания, что позволяет избавиться от поддержания регулируемых характеристик устройства на требуемом уровне и от цепи обратной связи в целом. 3 ил.

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27-02-1997 дата публикации

ФОРМИРОВАТЕЛЬ ИМПУЛЬСНОЙ ПОСЛЕДОВАТЕЛЬНОСТИ

Номер: RU2074512C1
Автор: Юдин А.В.

Применения: формирователь импульсной последовательности может найти применение в устройствах преобразования формы сигналов, умножителях и делителях частоты. Сущность изобретения: устройство содержит: счетчик 1, генератор 2, формирователь синхроимпульсов 3, регистр 4, постоянное запоминающее устройство 5, вычитающий счетчик 6. 2 ил.

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20-09-1995 дата публикации

УМНОЖИТЕЛЬ ЧАСТОТЫ

Номер: RU2044405C1

Использование: умножитель частоты следования импульсов может использоваться в измерительной технике, в устройствах автоматической подстройки частоты. Сущность изобретения: устройство содержит генератор импульсов, делитель частоты, элементы И и ИЛИ, триггер, счетчики импульсов, регистр сдвига и шины управления, входную, выходную. 2 ил.

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27-02-2004 дата публикации

Преобразователь пачки импульсов в пр моугольный импульс

Номер: RU2001132312A
Принадлежит:

Преобразователь пачки импульсов в прямоугольный импульс, содержащий источник импульсного сигнала, выход которого соединен с S-входом RS-триггера, элемент И, компаратор, источник опорного напряжения и выходную шину, связанную с первым выходом RS-триггера, отличающийся тем, что в него дополнительно введены элемент задержки, элемент НЕ и одновибратор, последовательно соединенные формирователь ступенчатого сигнала и инвертор, выход которого подключен к первому входу компаратора, второй вход последнего соединен с источником опорного напряжения, выход компаратора соединен со вторым входом элемента И, первый вход которого соединен с первым входом формирователя ступенчатого сигнала и выходом источника импульсного сигнала, выход элемента И последовательно через элемент НЕ и одновибратор соединен с R-входом RS-триггера и входом элемента задержки, выход которого подключен ко второму входу формирователя ступенчатого сигнала.

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10-08-2005 дата публикации

ПРЕОБРАЗОВАТЕЛЬ СЕРИИ ИМПУЛЬСОВ В ПРЯМОУГОЛЬНЫЙ ИМПУЛЬС

Номер: SU1651747A1
Принадлежит:

Преобразователь серии импульсов в прямоугольный импульс, содержащий первый элемент И, первый вход которого через первый формирователь импульсов соединен с входной шиной, второй вход - с первым входом первого элемента И-НЕ, с прямым выходом триггера, с выходной шиной и с управляющим входом регистра сдвига, информационные входы которого соединены с соответствующими выходами счетчика импульсов, первый выход - с первым информационным входом счетчика импульсов и первым входом второго элемента И-НЕ, второй выход - с вторым информационным входом счетчика импульсов, третий выход - с третьим информационным входом счетчика импульсов и с первым входом триггера, а остальные выходы - с соответствующими информационными входами счетчика импульсов, вход записи которого соединен с выходом первого элемента И, суммирующий вход - с выходом второго элемента И-НЕ, вычитающий вход - с выходом первого элемента И-НЕ, второй вход которого соединен с выходом генератора импульсов и с вторым входом второго элемента ...

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20-08-2005 дата публикации

ГЕНЕРАТОР ИМПУЛЬСОВ С ПРОЦЕНТНЫМ ФАЗОВЫМ ШУМОМ

Номер: RU2004103842A
Принадлежит:

Генератор импульсов с процентным фазовым шумом, содержащий генератор псевдослучайных чисел, входом подключенный к выходному зажиму устройства и выходу последовательной цепи первых элементов задержки, снабженных управляющими входами, соединенными с выходами группы смежных разрядов генератора псевдослучайных чисел, и опорными входами, соединенными с общим зажимом управляющего напряжения, отличающийся тем, что между выходным зажимом устройства и входом последовательной цепи первых элементов задержки введены последовательно соединенные инвертор и второй элемент задержки, имеющий подключенный к зажиму управляющего напряжения опорный вход.

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15-08-1991 дата публикации

Устройство для формирования одиночных импульсов

Номер: SU1670779A1
Принадлежит:

Изобретение относится к импульсной технике и может быть использовано в устройствах автоматики и вычислительной техники. Цель изобретения - расширение функциональных возможностей за счет обеспечения возможности управления задержкой начала пачки и числом импульсов - достигается введением кольцевого счетчика 2 импульсов, элементов И-НЕ 4, 5, шины 8 начальной установки кодовой шины 11. Устройство также содержит счетчик 1 импульсов, элемент И 3, RS-триггер 6, шину 7 управления, шину 9 тактовых импульсов, выходную шину 10. 2 ил.

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15-07-1992 дата публикации

Формирователь импульсов

Номер: SU1748235A1
Принадлежит:

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15-05-1983 дата публикации

Накопитель импульсных сигналов

Номер: SU1018220A2
Принадлежит:

НАКОПИТЕЛЬ ИМПУЛЬСНЫХ СИГНАЛОВ по авт.св. 886230, отличающийся тем, что, с целью увеличения отношения сигнал/шум цепь обратной связи выполнена на п , где п 7/ 1, линиях задержки на поверхностных акустических волнах с секционированными преобразователями, состоящими из отдельных секций встречно-штыревых электродов, расположенных последовательно на рабочей поверхности звукопровода перпендикулярно и симметрично относительно его продольной оси.

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23-09-1992 дата публикации

Устройство для выделения синхронизированной пачки импульсов

Номер: SU1764155A1
Принадлежит:

Изобретение может быть использовано в устройствах автоматики и вычислительной техники. Устройство содержит шину управления (1), шину синхроимпульсов (2), четыре выходные шины (З-б), два коммутатора с запоминанием сигнала управления (7 и 8), RS-триггер 9, два D-триггера (10 и 11). логический элемент И (12) с соответствующими связями. 4 ил.

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07-07-1991 дата публикации

Умножитель частоты следования импульсов

Номер: SU1661981A1
Принадлежит:

Изобретение может использоваться в технике измерения низких частот и в синтезаторах частот. Цель изобретения - повышение точности при одновременном повышении точности при одновременном повышении надежности работы - достигается за счет введения управляемого делителя 14 частоты, счетчика 2 импульсов, мультиплексора 3, триггера 10 и формирователя 6 импульсов по фронту и срезу входного импульса и организации новых функциональных связей. Устройство также содержит счетчик 1 импульсов, вычитающий счетчик 4 импульсов, элементы И 5, 7, делитель 12 частоты, генератор 13 тактовых импульсов, формирователь 9 установочных импульсов, кодовую шину 15 и входную и выходную шины 11 и 8. Устройство обеспечивает возможность получения дробного коэффициента деления. За счет блокировки выходным импульсом формирователя 6 перезаписи кодов с выхода мультиплексора 3 исключаются сбойные ситуации в устройстве. 1 з.п. ф-лы, 1 ил.

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26-09-1962 дата публикации

Генератор прямоугольных импульсов

Номер: SU150132A1
Автор: Курт Шёпс
Принадлежит:

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01-01-1962 дата публикации

Полупроводниковый широтно-импульсный модулятор

Номер: SU143868A1
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23-06-1986 дата публикации

Формирователь огибающей серии импульсов

Номер: SU1239851A1
Принадлежит:

Изобретение относится к импульсной и измерительной технике и может быть использовано для формирования огибающей серии импульсов в устройствах автоматики, в измерительной технике связи. Цель изобретения повышение точности формирования. Для этого в формирователь, содержащий блок 1 задержки, выходной триггер 2, формирователь 3 коротких импульсов, вход 4 формирователя, элемент И 5, введены дополнительный триггер 7 и элемент 8 задержки. Формирователь в своем частном решении позволяет работать с длинными входными импульсами , значительно превьшающими интервал ожидания. Б этом случае выходной триггер 2 имеет третий вход - информационный, соединенный с входом селектора. Вторым входом 13 триггера является тактовый вход, т.е. триггером 2 должен быть D-триггер, 1К-триг- гер и др. 1 з.п.ф-лы, 3 нп. i (Л ...

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15-06-1986 дата публикации

Умножитель частоты импульсов

Номер: SU1238222A1
Принадлежит:

Изобретение относится к импульсной технике. Может быть использовано в устройствах автоматики и измерительной техники . Цель изобретения - повышение точности измерений :- достигается введением в умножитель второго логического элемента (ЛЭ) И 7, формирователя разностной частоты 9, блока управления 11 и шины 12 начальной установки. Кроме того, умножитель содержит реверсивный счетчик 1, счетный блок 2, шины - выходную 3 и умножаемой частоты 10, делитель частоты 4, генератор импульсов 5, первый ЛЭ И 6, ЛЭ ИЛИ 8. В счетный блок 2 входят элемент 13 сравнения кодов, счетчик импульсов 14 и формирователь импульсов 15. Состав формирователя разностной частоты 9 и блока управления 11 показан на функциональных схемах, приведенных в описании изобретения . Данный умножитель частоты устойчиво работает в диапазоне умножаемых частот , ограниченном снизу величиной Рвхмин- fni/K и сверху Fex.Mat«; fm/3K, где f ги - частота импульсов генератора 5; К - коэффициент деления делителя 4. Частота появления фазовых ...

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23-06-1986 дата публикации

Устройство для формирования импульсов

Номер: SU1239848A1
Принадлежит:

Изобретение относится к импульсной технике и может быть использовано в системах автоматического управления и регулирования. Целью изобретения является расширение диапазона частот входных импульсных последовательностей . В устройство, содерЛ жащее элементы И 1-4, элементы ИЛИ 5 и 6, счетчики 7 и 8, генератор 9 импульсов, инвертор 10, триггер II, элемент 2 задержки, формирователь 13 одиночных импульсов, входные шины 14 и 15 устройства, выходную шину 16, введены пятый элемент И 17, третий элемент ИЛИ 18, постоянное запоминающее устройство 19, цифро- аналоговый -преобразователь 20, управляющий транзистор 21, второй генератор 22, сдвиговый регистр 23, мультиплексор 24, входная шина 25 Сброс и шина 26. Это позволило расширить диапазон частит входных импульсных последовательностей. В качестве формирователя 13 можно использовать одностабильный мультивибратор К i 55АГ1, в качестве мультиплексора 24 - микросхему К 155КП1, в качестве генераторов 9 и 22 - микросхему К22 и ГТ2. 2 ил. с « (Л ...

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30-08-1988 дата публикации

Устройство для вычитания импульсных последовательностей

Номер: SU1420655A1
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Использование: умножитель частоты относится к импульсной технике и может использоваться в устройствах автоматики и измерительной технике. Сущность изобретения: устройство содержит: входную шину 1, шину 2 опорной частоты, выходную шину 3. триггеры 4,5, элемент 6 ИСКЛЮЧАЮЩЕЕ ИЛИ, реверсивный счетчик 7, счетчик 8, делители 9, 10 частоты, элемент И 11, 7 ил.

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УСТРОЙСТВО ДЛЯ ПРЕОБРАЗОВАНИЯ СЕРИИ ИМПУЛЬСОВ В ПРЯМОУГОЛЬНЫЙ ИМПУЛЬС, содержащее последовательно соединенные входную шину, формирователь импульсов, элемент задержки, триггер и выходную шину, отличающееся тем, что, с целью повышения точности преобразования, в него введен элемент И, первый вход которого соединен с выходом триггера, второй вход подключен к второму выходу формирователя импульсов , а выход элемента И соединен с входом сброса элемента задержки.

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УСТРОЙСТВО ДЛЯ ФОРМИРОВАНИЯ ЛОГАРИФМИЧЕСКОГО РЯДА ЧАСТОТ, содержащее первый двоичный счетчик, последовательно соединенные второй двоичный счетчик, детектор нуля и блок ключей, выходы которого соединены с входами установки второго двоичного счетчика, синхронизирующий вход которого соединен с шиной тактовых импульсов, отличающееся тем, что, с целью расширения функциональных возможностей устройства за счет уменьшения основания логарифма формируемого ряда частот, в него введены шифратор и последовательно соединенные шина импульсов смены частоты, счетчик частот, счетчик октав и коммутатор, первый информационный вход которого соединен с выходом детектора нуля и с входом первого двоичного счетчика, выходы разрядов которого соединены с остальными информационными входами коммутатора соответственно, врходы разрядов счетчика частот соединены со входами шифратора , вы (Л ходы которого соединены с соответствующими входами блока клюс чей.

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Изобретение может быть использовано в измерителях и преобразователях частоты. Цель изобретения - повышение помехоустойчивости путем адаптивной временной селекции импульсов входного сигнала. Эта цель достигается введением временного селектора 19 и организацией новых структурных связей Умножитель содержит регистры 1, 8, 9 и 13 хранения, делитель 2 с переменным коэффициентом деления, делитель 4 частоты, элемент И 5, счетчики 6 и 16 импульсов, сумматоры 10, 12 и 14, вычи- татель 11 генератор 15 тактовых импульсов, дешифратор 17, триггер 18 и входную 20. выходную 3 и кодовую 7 шины. 1 з п.ф-лы, 2 ил.

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... 1. УСТРОЙСТВО ДЛЯ ФОРМИРОВАНИЯ ИМПУЛЬСОВ РАЗНОСТНОЙ ЧАСТОТЫ , содержащее три триггера, причем информационный вход первого триггера соединен с первой входной шиной и с информационным входом второго триггера, вход синхронизации которого подключен к второй входной шине, отличающееся тем, что, с целью повышения надежности работы устройства , в него введены два элемента И, элемент задержки и блок определения знака разности частот, первый вход которого соединен с информационным входом второго триггера, вход синхронизации которого подключен к второму входу блока определения знака разности частот и через элемент задержки - к входу синхронизации первого триггера, прямые выходы первого и второго триггеров соединены с первыми входами соответственно первого и второго элементов И, а инверсные выходы первого и второго триггеров подключены к вторым входам соответственно второго и первого элементов И, выходы которых соединены соответственно с единичным и нулевым входами третьего триггера, прямой и инверсный ...

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УСТРОЙСТВО ДЛЯ ФОРМИРОВАНИЯ РАЗНОСТНОЙ ЧАСТОТЫ ИМПУЛЬСОВ, содержащее два триггера и три элемента И, первый и второй выходы первого триггера соединены с первыми входами первого и второго элементов И соответственно , вторые входы которых соединены между собой, а выходы под-. ключены соответственно к первому и второму входам второго триггера, первый выход которого соединен с. первым входом третьего элемента И, выход которсэго подключен к первому входу первого триггера, отличающееся тем, что, с целью расширения функциональных возможностей , в него введены два формирователя импульсов и дополнительный элемент И, первый вход которого соединен с вторым выходом второго триггера , а второй вход подключен к второму входу третьего элемента. И и к выходу первого формирователя импульсов , вход которого соединен с вторым входом первого элемента И, g выход второго формирователя импуль (П к второму входу перво.сов подключен го триггера. f,1чЭ О. 2 К) ...

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Изобретение относится к области импульсной техники и может быть использовано в устройствах для преобразования малых стохастических импульсов напряжения с различной шининой импульса в длительный сигнал. Устройство содержит усилитель 1, кондетша- тор 2, пороговый переключатель 4, .блок 3 задержки, входную и выходную шины. Лороговый переключатель 4 может быть выполнен в виде триггера Шмитта или компаратора. Устройство имеет расширенный диапазон длительностей входных импульсов и просто в конструкции, 2 ил.

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Изобретение относится к радиотехнике и может быть использовано в устройствах для сравнения двух импульсных последовательностей по частоте . Устройство для получения разности частот двух импульсных последовательностей содержит входные шины 1,2, элементы НЕ 3,4, элементы И 5,j 6 с инверсными входами, триггеры 7,8 и триггер 9 1К-типа, что позволяет увеличить функциональную надежность устройства. 2 ил. т с ...

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УСТРОЙСТВО ДЛЯ ПРЕОБРАЗОВАНИЯ СЕРИИ ИМПУЛЬСОВ В ПРЯМОУГОЛЬНЫЙ ИМПУЛЬС, содержащее последовательно соединенные генератор тактовых импульсов, счетчик импульсов, триггер и элемент И-НЕ, отличающееся тем, что, с целью г повышения точности преобразования, в него введены элемент НЕ, элемент ИЛИ и элемент И, первый вход которс го подключен к входной шине, а выход элемента И соединен с установоч ным входом счетчика импульсов, с первым входом элемента ИЛИ и через элемент НЕ с первым входом генератс ра тактовых импульсов, второй вход которого подключен к выходу элемента И-НЕ, второй вход которого соедр ней с вторым входом элемента ИЛИ и с входом триггера, второй выход которого подключен к выходной щине и к третьему входу элемента ИЛИ, выхс которого соединен с вторым входом сл элемента И. с ц ...

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УМНОЖИТЕЛЬ ЧАСТОТЫ, содер жащий интегратор, вход которого соединен с входной шиной, источник опорного напряжения, резистивиый делитель напряжения и четыре компапатсфа , отличающийся тем, что, с целью расширения диапазона умножаеких частот при сохра нении постоянной скважности выходных импульсов, в него введены четыре сумматора по модулю 2 и инвертор , вход которого соединен с выходом интегратора, управляющим входом источника опорного напряжения, первыми входами первого и второго ком-. параторов, а выход - с первыми входами третьего и четвертого компараторов , при этом резистивный делитель напрясж ния подключен между выходом источника опорного напряжения и нулевой шиной, его первый отвод соеj динен с вто{Я:)ми входами первого и третьего компараторов, а второй отвод - с вторыми входами второго и четвертого компараторов, причём первый и второй входы первого сумматора по модулю 2 соединены с выходамисобтветственно первого и второго компараторов, первый и второй входы второго сумматора по модулю ...

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Изобретение предназначено для использования в импульсной технике, например в полиграфических машинах и устройствах, в частности для управления механизмом прерывания сплошного газетного потока в счет- но-комплектующих устройствах СКУ, Цель изобретения - упрощение конструкции, повышение надежности и снижение потребляемой МОШ1НОСТИ. Фсрмироватепь временной задержки для управления прерывания содержит пересчетный блок 1. клавиатуру 2 задания задержки, блок 3 запуска, блок 4 ззляси козффициеига пересчета, входную шину 5, шину 6 запуска, шину 7 установки в исходное состояние, первую и вторую выходную шины 8 и &. 9 ил. ^'Лf2!^1!SПfr^fe^fe-^^larpr^Zl'. ^r-j7.

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Номер: SU1780163A1
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Устройство для коррекции фазы в схемах синхронизации относится к технике связи и может быть использовано для коррекции фазы процесса за счет добавления в корректирующую последовательность. Устройство содержит 5 триггеров ...

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Устройство для преобразования частоты последовательности импульсов

Номер: SU1443152A1
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Изобретение относится к импульсной технике и может быть использовано в импульсных устройствах с коррекцией числа импульсов в последовательности , например в аппаратуре наземной навигации. Цель изобретения расширение функциогсальных возможностей устройства - достигается за счет обеспечения реализации режима добавления импульсов в последовательность входящих импульсов. Устройство содержит счетчик 1 импульсов, элементы И 2, 6 и 10, счетчик 3 Джонсона, элементы ИЛИ 4, 7 и 8, элемент ИЛИ-НЕ 5, инвертор 9, шины входную 11, кода 12, преобразования, 13 импульсов сброса, 14 частоты заполнения, 15 знака преобразования и выходную 16. Изобретение может быть использовано в наземной навигационной аппаратуре одномет- рического типа для корректировки числа путевых импульсов в зависимости от рельефа и дорожных условий пути, а также в любых импульсных системах с поимпульсной обработкой информации. 1 ил. § СЛ С ...

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Номер: SU1403356A1
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Изобретение может быть использовано для восстановления и синтеза частот в системах автоматики и обработки данных, а также в измеритель ных устройствах. Умножитель частоты с следования импульсов содержит фазовый детектор , элементы И 2,3, реверсивный счетчик 12, триггеры 9, 20, инверторы 8,10,19, регистр 13 хранения , цифроаналоговый преобразователь 14, генератор 15 импульсов, делитель 6 частоты, деоичный счетик 7, элемент ИЛИ 4, формирователи 17, 18 выходную и входную шины 16 и 21 соответственно, Умножитель частоты имеет првьшенные точность отработки фазы выходного сигнала и надежность J з.п. ф-лы, 2 ил.

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Изобретение относится к импульсной технике и может быть использовано в устройствах формирования сетки частот . Цель изобретения - повышение быстродействия - достигается за счет исключения влияния задержек в дешифраторе и в реверсивном счетчике импульсов . Другая цель - расширение функциональных возможностей - достигается за счет получения дополнительной импульсной последовательности, которая сдвинута по фазе относительно основной. На чертеже показаны генератор 1 опорной частоты, программный блок 2, формирователь 3 импульсов, фазосдвигающая цепочка 4, блок 5 управления фазовым сдвигом, элементы И 6-9, элемент ИЛИ 10, дешифратор 11, реверсивный счетчик 12 импульсов, регистр 13. Блок 5 управления фазовым сдвигом содержит злементы И 14-17 и элемент ИЛИ 18. Входные шины 19 и 20 соединены соответственно с выходом элемента ИЛИ 10 и с выходом блока 5. Блок 2 может быть выполнен в виде коммутируемого переключателя управляемого делителя или умножителя частоты с равномерной выходной импульсной последовательностью ...

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Номер: SU1200400A1
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ФОРМИРОВАТЕЛЬ ИШУЛЬСОВ, содержащий генератор, счетчик импульсов и триггер, отличающийся тем, что, с целью повышения помехоустойчивости, в него введены регистр .сдвига, элемент ИЛИ, информационный и контрольный регистры сдвига, элемент И, сумматор по модуш два и блок сравнения, причем тактовый вход регистра сдвига соединен с тактовыми входами триггера, счетчика импульсов и с выходом генератора, выход регистра сдвига соединен с входами элемента ИЛИ, выход которого соединен с Информационным входом триггера, прямой выход триггера соединен с выходами информационного и контрольного регистров сдвига, а инверсный выход с первым входом элемента И, второй вход которого соединен с тактовыми входами информационного и контрольного регистров сдвига и с выходом счетчика импульсов, выход элемента И соединен с управляющим входом блока сравнения, первый выход .которого соединен с управляющим входом сумматора по модулю два, а второй выход - с установочным входом контрольного регистра сдвига, информационные ...

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Номер: SU1243118A1
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Изобретение относится к импульсной технике и может быть использовано в радиоприемных и передакщих устройствах , в измерительной аппаратуре, в частотно-преобразующих узлах хранителей времени. Целью изобретения является повышение кратковременной стабильности частоты следования выходND 4ib 00 rff фиг.1 ...

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Номер: SU1018219A1
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УМНОЖИТЕЛЬ ЧАСТОТЫ СЛЕДОВАНИЯ . ИМПУЛЬСОВ , содержащий пять элементов ИЛИ, шесть элементов И, регистр сдвига, выходы которого соединены с первой группой входов первого элемента сравнения, вторая группа входов которого соединена.с единичными выходс1ми реверсивного счетчика импульсов, обнуляющий вход которого соединен с выходом первого элемента ИЛИ, первый вход которого соединен с первым входом второго элемента ИЛИ и первым выходом дешифратора, а ВТОРОЙ вход - с выходом первого элемента.сравнения и первым входом первого элемента И, выход которого соединен со счетным входом первого счетчика импульсов, выходы которого соединены с первой группой входов второго элемента сравнения, вторая группа входов которого соединена с выходами второго счетчика импульсов, обнуляющий вход которого соединен с выходом второго элемента ИЛИ а счетный вход - с выходом второго-элемента И., первый вход которого подключен к выходу генератора опорной частоты, первый вход третьего элемента И соединен с входной шиной, ...

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Номер: SU1598134A1
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Изобретение относится к измерительной технике и может быть использовано в вычислительных и измерительных устройствах в системах контроля и автоматики. Цель изобретения - расширение области рабочих частот устройства. Измерительный усилитель содержит входной формирователь 2 импульсов, селектор 5 частот и элемент ИЛИ 8. Для достижения цели в него введены электронный ключ 3, пиковый детектор 6, формирователь 4 импульса и аналого-цифровой преобразователь 7. Это позволяет осуществлять измерение амплитудного значения входного сигнала при изменении периода его следования независимо от частоты этого сигнала. 4 ил.

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Номер: SU1599978A1
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Изобретение относится к импульсной технике и может быть использовано в цепях фазовой автоподстройки или в фазовых преобразователях для управления приводами роботов и станков с числовым программным управлением с фазовой системой управления. Цель изобретения - повышение помехозащищенности и надежности устройства с одновременным его упрощением. Устройство содержит первый 2 и второй 3 D-триггеры, делитель 1, первый 4 и второй 5 элементы ИЛИ, первый 6, второй 7 и третий 8 элементы И и инветор 9. 2 ил.

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Номер: SU1598135A1
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Изобретение может использоваться в измерительной технике для повышения точности процесса преобразования частоты при работе с низкочастотными датчиками. Цель изобретения - повышение точности за счет снижения влияния помех - достигается введением триггеров 8 и 9, элементов И 5 и 10, регистра 17 хранения, счетчиков 19 и 20 импульсов, элемента 16 задержки и организацией новых функциональных связей. Устройство, кроме того, содержит блок 1 управления, делитель 2 частоты, счетчики 3, 7 и 11 импульсов, генератор 4 опорной частоты, регистр 6 хранения, дешифраторы 12 - 14, блок 15 памяти, блок 18 элементов И, входную, выходную и кодовую шины 21, 22 и 23. Приведена схема блока 15 памяти. Повышение точности обеспечивается допусковым контролем примыкающих периодов входных импульсов, осуществляемым с учетом как целой, так и дробной частей изменения величины периода входных импульсов. 3 ил.

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Номер: SU1019615A1
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УДВОИТЕЛЬ tJAGTOTli C НЙЯ ИМШГЛЬ(:ЮВ содержаир1й; 1юрвый и BTQpoiR элементь И, первые входы кот рых средйиены соотве:т :твеннЬ непосредстйаеннЬ и чёрез: инвертор с вхо;1{{ Ой, шнмой;, а выхогды V- с входами Элё1«ента ЙЛИ и ;интегра1торыу о т л и ч а ю щ и и с Я; тем, что, с целью иолучения равнЬмерного распредедеяяя Ш(«пульсов на выходе устррйс-гва в Hifepo введены два делителя на пряжеви я на два и первмй;и агорой элемента сравнения еыхожл последних подключены к вторЕа входам соответствукндйх элемё ( И, ; Первые входы г- к ВЕаходам соответственно первого : и второго интеграторов , вторые входы - к вьпсодак сбответстве но первого и второго делителей напряжения на два , входы которых со едйнены с вьосода 4И соответственно второго к первого интеграторов , входы которых подклкмены соот ётствейНо к; выходу инвертора и к вхойной 1яйне, а взсоды сброса т с выходам соответственно первого, и второго элементов И. , - te.j5 ...

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Номер: SU1555839A1
Принадлежит:

Изобретение может использоваться в системах автоматического регулирования для обработки низкочастотных сигналов, а также в цифровой измерительной аппаратуре инфранизких частот. Цель изобретения - повышение быстродействия за счет удвоения частоты обновления входной информации - достигается введением дополнительного счетчика 6 импульсов и организацией новых функциональных связей. Устройство также содержит формирователь 1 импульсов, регистр 2 хранения, элементы 3, 5 задержки, счетчик 4 импульсов, делитель 7 частоты, генератор 8 тактовых импульсов, делитель 9 частоты с переменным коэффициентом деления, входную 11 и выходную 10 шины. 1 ил.

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Номер: SU1584096A1
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Изобретение может быть использовано в системах обработки и формирования импульсных сигналов. Целью изобретения является повышение относительной точности формирования выходного импульса. Устройство содержит входную шину 1, формирователь 2 импульсов, генератор 3 тактовых импульсов, ключ 4, счетчик 5 импульсов, триггер 7, измеритель 8 периода, блок 9 переписи, выходную шину 10. Введение элемента ИЛИ 6 и генератора 11 одиночных импульсов и формирование в блоке 9 переписи величины добавки, пропорциональной величине нестабильности периода следования входных импульсов, позволяет уменьшить относительную погрешность формирования выходного импульса. 1 ил.

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Номер: SU427460A1
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Номер: SU1241445A2
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Номер: SU1667238A2
Принадлежит:

Изобретение относится к импульсной технике и может быть использовано в устройствах управления электроприводами постоянного тока. Цель изобретения - повышение надежности работы за счет устранения сквозных токов в режиме обрыва нагрузки, для чего в устройство введены усилитель 18 и сумматор 19. Устройство содержит силовые транзисторы 1 и 2, управляющие транзисторы 16, 17, управляемые ключи 3, 4, диоды 5 - 8, датчик 9 тока, пороговые элементы 10 - 12, логический блок 13, резисторы 14, 15. 1 ил.

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Номер: SU1328931A1
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Изобретение может быть использовано в устройствах преобразования временных интервалов в цифровой код, в частности в аммплитудных и временных анализаторах, в которых используется принцип преобразования временного интервала путем его заполнения тактовыми импульсами большой частоты. Изобретение позволяет исключить искажения первого и последнего из фази- руемых импульсов .при периоде их следования , соизмеримом с продолжительностью переходных процессов в устройстве . Устройство содержит формирователь 1 сдвинутых одна относительно другой по времени импульсных последовательностей , N D-триггеров 2, N элементов И 3, элемент ИЛИ 4, выходной элемент И 5, элемент 6 задержки, шину 7источника импульсов временного интервала , вход 8 тактовых импульсов, вход 9 начальной установки, выход 10. 8.устройстве опрос D-триггеров производится по окончании переходных процессов на них через время от момента I срабатывания, равное Т(Я-1), где Т- Iпериод тактовых импульсов. 2 ил. (Л со to 00 со со ...

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Номер: SU403041A1
Автор: Зайдман Г.И.
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Номер: SU1450096A1
Принадлежит:

Изобретение относится к импульсной технике и может быть использовано в устройствах синхронизации цифровых систем передачи данных. Цель изобретения - расширение функциональных возможностей - достигается путем обеспечения получения любых целочисленных коэффициентов умножения, задав а- емых программно изменением входного кода. Для этого в устройство дополнительно введены программируемый счетчик 8 импульсов, элемент И 6, формирователь 3 короткого импульса, кодовая шина 9 и блок 2 сравнения и коммутации . Кроме того, устройство содержит N последовательно соединенных элементов 1-1...1-N задержки, входную шину 4, элемент ИЛИ 5, выходную шину 7. Операция сравнения и коммутации осуществляется при наличии на (N+2)--M входе блока 2 сигнала разре- шения. Схема выполнения блока 2 приводится в описании изобретения. 1 3.п. ф-лы, 2 ил. i (Л 42ь 01 СО О) (plLZ.I ...

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Номер: SU873398A1
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Номер: SU741443A1
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Емкостное накопительное устройство

Номер: SU555540A1
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Duty cycle correction

Номер: US20120256669A1
Принадлежит: Icera LLC

Method and circuitry for controlling duty cycle of an input signal towards a desired value comprising a sequence of at least two inverters arranged in series and feedback circuitry. A first inverter is arranged to receive the input signal and a last inverter is arranged to output a signal having the same frequency as the input signal. The output signal is an adjusted version of the input signal. The feedback circuitry is arranged to receive the output signal and comprises a comparing and supplying means. The comparing means compares the output signal with a reference signal indicative of a desired value and generates a feedback signal based on the comparison of the output and reference signal. The supplying means supplies the feedback signal to adjust operating conditions of at least one of the inverters, such that the duty cycle of the output signal is controlled towards the desired value.

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Clock signal generators having a reduced power feedback clock path and methods for generating clocks

Номер: US20120268171A1
Автор: Aaron Willey, Yantao Ma
Принадлежит: Micron Technology Inc

Memories, clock generators and methods for providing an output clock signal are disclosed. One such method includes delaying a buffered clock signal by a adjustable delay to provide an output clock signal, providing a feedback clock signal from the output clock signal, and adjusting a duty cycle of the buffered clock signal based at least in part on the feedback clock signal. An example clock generator includes a forward clock path configured to provide a delayed output clock signal from a clock driver circuit, and further includes a feedback clock path configured to provide a feedback clock signal based at least in part on the delayed output clock signal, for example, frequency dividing the delayed output clock signal. The feedback clock path further configured to control adjustment a duty cycle of the buffered input clock signal based at least in part on the feedback clock signal.

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27-12-2012 дата публикации

Duty cycle based phase interpolators and methods for use

Номер: US20120326750A1
Автор: Gideon Yong
Принадлежит: Individual

Duty cycle based phase interpolators, and methods for implementing duty cycle based phase interpolators are disclosed. One such phase interpolator includes a first pulse width modulator configured to generate a first duty cycle signal, and a second pulse width modulator configured to generate a second duty cycle signal. The phase interpolator further includes a logic unit configured to merge the first duty cycle signal and the second duty cycle signal to produce a periodic digital signal with a controllable phase depending on the first and second duty cycle signals.

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10-01-2013 дата публикации

Data transfer circuit and method with compensated clock jitter

Номер: US20130009685A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A data I/O interface for an integrated circuit device includes a noise detector receiving a power supply voltage, detecting a power supply voltage noise component, and providing a clock delay control signal in response to detected power supply voltage noise component. The data I/O interface also includes a clock delay circuit providing a delayed clock signal in response to the clock delay control signal, and a data transfer circuit powered by the power supply voltage and providing output data synchronously with the delayed clock signal.

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07-02-2013 дата публикации

Automatic blade leveler right tilt-left tilt-null control and method

Номер: US20130032367A1
Автор: Herbert S. Kobayashi
Принадлежит: Individual

In one embodiment a dozer blade controller, which may comprise two-way, four-way, or six-way dozer blade position control such as, for example, a two-way control only for blade tilt. In one embodiment, a pulse width control is provided for use in a blade tilt electronic controller, which controls blade tilt independently of movement of the body of the bull dozer. And in another embodiment, a pulse width controller is operable to multiply and/or divide the width of a variable pulse by a preset multiplier factor or divider factor, e.g. by 100 or dividing by 100.

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28-03-2013 дата публикации

DIGITALLY CONTROLLED PULSE WIDTH MODULATOR UTILIZING REAL TIME CALIBRATION

Номер: US20130076420A1

A system and method for controlling pulse width for electronic devices in real time is disclosed. The system includes a Digital Pulse Width Modulator (DPWM), a real time calibration circuit and a delay line circuit. The real time calibration circuit is configured to ensure proper fractional delay is applied to yield correct duty cycle of the DPWM. The delay line circuit comprising a multiplexer delay line with built in decoders, modulates the pulse width for fractional clock cycle delay. 1. A system for controlling pulse width for electronic devices in real time comprising:a digitally controlled pulse width modulator; anda real time calibration circuit configured to ensure proper fractional delay which is applied to yield a correct duty cycle of said digitally controlled pulse width modulator.2. The system of wherein a defy line circuit is configured to modulate pulse width for a fractional clock cycle delay.3. The system of claim 2 , wherein the delay line circuit comprises a multiplexer delay line with built in decoders.4. The system of claim 1 , wherein said digitally controlled pulse width modulator provides proper duty cycle pulse to a plurality of gate drivers.5. The system of claim 2 , wherein said delay line circuit allows modulation of pulse width for said fractional clock cycle delay.6. The system of claim 2 , wherein said fractional clock cycle delay comprises an upper delay claim 2 , a lower delay and a very fine resolution delay.7. The system of claim 1 , wherein said digitally controlled pulse width modulator allows for digital filtering and programmable resolution.8. The system of claim 1 , wherein digital pulse width modulation is performed with real time calibration to compensate for environmental variations due to radiation claim 1 , aging claim 1 , temperature claim 1 , and voltage changes.9. A method for controlling pulse width for electronic devices in real time comprising:configuring a real time calibration circuit to ensure proper fractional ...

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11-04-2013 дата публикации

Method and apparatus for determining duty cycle of a clock in a circuit using a configurable phase locked loop

Номер: US20130088270A1
Принадлежит: Tellabs Operations Inc

An embodiment of the invention discloses phase shifting a second clock signal by a phase increment with respect to a first clock signal, where the first clock signal and the second clock signal have the same periods. The first clock signal is sampled with the second clock signal, and the output of the sample indicates whether the sample of the first clock signal is at a logic one state or a logic zero state. A count of logic one samples is incremented if the sample of the first clock signal is at a logic one state. The process of phase shifting the second clock signal and sampling the first clock signal is repetitively performed to a maximum number of samples.

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02-05-2013 дата публикации

High-speed duty cycle correction circuit

Номер: US20130106479A1
Автор: Soo-Won Kim, Young-Jae MIN

A circuit for correcting a duty-cycle comprises a duty-cycle adjuster for changing a duty-rate of an input clock signal according to a duty control signal; a duty-cycle detector for detecting a duty-rate of an output clock signal based on the input clock signal and the output clock signal from the duty-cycle adjuster; and an algorithm-based digital controller for performing an algorithm according to a duty-rate detection signal outputted from the duty-cycle detector to generate the duty control signal.

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06-06-2013 дата публикации

PULSE WIDTH ADJUSTING CIRCUIT AND METHOD

Номер: US20130141147A1

The pulse width adjusting circuit includes a pulse delaying circuit for inputting an inputted pulse signal a and for outputting a plurality of different delayed pulse signals b, b, . . . , a transmission gate for inputting an inputted pulse signal a and controlling the passage of the inputted pulse signal a in response to the application of two delayed pulse signals from among the plurality of different delayed pulse signals b, b, . . . , and a pulse width setting circuit connected to the transmission gate for setting the pulse width of an outputted pulse signal c generated on the basis of the inputted pulse signal a passing through the transmission gate. 1. A pulse width adjusting circuit comprising:a pulse delaying circuit for inputting an inputted pulse signal and for outputting a plurality of different delayed pulse signals;a transmission gate for inputting an inputted pulse signal and controlling the passage of the inputted pulse signal in response to the application of two delayed pulse signals from among the plurality of different delayed pulse signals; anda pulse width setting circuit connected to the transmission gate for setting the pulse width of an outputted pulse signal generated on the basis of the inputted pulse signal passing through the transmission gate.2. A pulse width adjusting circuit according to claim 1 , wherein the transmission gate is turned on until the leading edge of the inputted pulse signal passes by applying the two delayed pulse signals claim 1 , is turned off before passage of the trailing edge of the inputted pulse signal claim 1 , and is turned off when the outputted pulse signal reaches a predetermined pulse width or thereafter.3. A pulse width adjusting circuit according to claim 2 , wherein the pulse width setting circuit is maintained in a state displaced by the leading edge of the inputted pulse signal while the outputted pulse signal is a predetermined pulse width when the transmission gate has been turned off.4. A pulse ...

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06-06-2013 дата публикации

PULSE STRETCHING CIRCUIT AND METHOD

Номер: US20130141148A1

A pulse stretching circuit having a pulse delay circuit for receiving an input pulse signal and for outputting a delay pulse signal, and a pulse adjustment circuit, connected to the pulse delay circuit, receiving the input pulse signal and the delay pulse signal and for outputting an output pulse signal having a pulse width longer than a pulse width of the input pulse signal. The pulse adjustment circuit causes a leading edge of the output pulse signal in response to a leading edge of the input pulse signal, keeps a state in which the output pulse signal is displaced with the leading edge thus caused longer than a total time of times for both pulse widths of the input pulse signal and the delay pulse signal, and causes a trailing edge of the output pulse signal in response to a trailing edge of the delay pulse signal. 1. A pulse stretching circuit , comprising:a pulse delay circuit for receiving an input pulse signal and for outputting a delay pulse signal; anda pulse adjustment circuit connected to the pulse delay circuit, the pulse adjustment circuit receiving the input pulse signal and the delay pulse signal and outputting an output pulse signal having a pulse width longer than a pulse width of the input pulse signal, wherein the pulse adjustment circuit causes a leading edge of the output pulse signal in response to a leading edge of the input pulse signal, and a trailing edge of the output pulse signal in response to a trailing edge of the delay pulse signal.2. The pulse stretching circuit according to claim 1 , wherein the pulse adjustment circuit includes:a latch circuit set by a set signal generated from the input pulse signal, reset by a reset signal generated from the delay pulse signal, and causing an output; andan OR circuit connected to the pulse delay circuit and the latch circuit, the OR circuit outputting a logical sum of the input pulse signal, the delay pulse signal, and the output pulse signal of the latch circuit.3. The pulse stretching circuit ...

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06-06-2013 дата публикации

APPARATUS AND METHOD FOR DUTY CYCLE CALIBRATION

Номер: US20130141149A1
Принадлежит: MEDIATEK INC.

An apparatus for duty cycle calibration includes an input calibration circuit, a delay chain, a first comparator, and a second comparator. The input calibration circuit calibrates an input clock signal according to a first control signal so as to generate an input calibration clock signal. The delay chain includes a plurality of delay units coupled in series, and delays the input calibration clock signal so as to generate a first delay clock signal and a second delay clock signal. At least two of the delay units each have an adjustable delay time which is controlled according to a second control signal. The first comparator compares the input calibration clock signal with the first delay clock signal so as to generate the first control signal. The second comparator compares the input calibration clock signal with the second delay clock signal so as to generate the second control signal. 1. An apparatus for duty cycle calibration , comprising:an input calibration circuit, calibrating an input clock signal according to a first control signal so as to generate an input calibration clock signal;a delay chain, comprising a plurality of delay units coupled in series, and delaying the input calibration clock signal so as to generate a first delay clock signal at a first node of the delay chain and generate a second delay clock signal at a second node of the delay chain, wherein at least two of the plurality of delay units each have an adjustable delay time which is controlled according to a second control signal;a first comparator, comparing the input calibration clock signal with the first delay clock signal so as to generate the first control signal; anda second comparator, comparing the input calibration clock signal with the second delay clock signal so as to generate the second control signal.2. The apparatus as claimed in claim 1 , wherein the input calibration clock has a duty cycle of about 50%.3. The apparatus as claimed in claim 1 , further comprising:a ...

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06-06-2013 дата публикации

METHOD FOR GENERATING A MULTIPHASE PWM SIGNAL

Номер: US20130141150A1
Принадлежит:

A method and a circuit configuration are provided for generating a multiphase PWM signal. For this purpose a number of PWM generators are provided, which respectively have one counter, two comparators and one state memory, each PWM generator outputting a PWM signal, which represents a phase of the multiphase PWM signal, the PWM generators being coupled with one another via multiplexers such that the counters of the PWM generators that are coupled with one another are clocked identically. 110-. (canceled)11. A method for generating at least a multiphase PWM signal , comprising:providing multiple PWM generators which each have one counter, two comparators, and one state memory, wherein the PWM generators are coupled with one another via multiplexers such that the counters of the PWM generators are clocked identically; andgenerating multiple PWM signals using the multiple PWM generators, wherein each PWM generator outputs a respective PWM signal which represents a phase of the multiphase PWM12. The method as recited in claim 11 , wherein all the comparators of the PWM generators are updated simultaneously when the counters are reset.13. The method as recited in claim 12 , wherein the reset of all the comparators is ensured by a synchronization logic circuit.14. The method as recited in claim 12 , wherein the multiphase PWM signal is generated to control an H bridge circuit with arbitrary timeouts.15. The method as recited in claim 12 , wherein a single-phase PWM signal is additionally generated.16. A circuit configuration for generating a multiphase PWM signal claim 12 , comprising:multiple PWM generators which each contain one counter, two comparators, one state memory, and a multiplexer, wherein the multiple PWM generators are coupled with one another via the multiplexers.17. The circuit configuration as recited in claim 16 , wherein a flipflop is used as the state memory.18. The circuit configuration as recited in claim 16 , wherein the multiplexer is a 1-bit ...

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22-08-2013 дата публикации

CIRCUIT FOR FILTERING NARROW PULSE AND COMPENSATING WIDE PULSE, AND MOTOR CONTROLLER COMPRISING THE CIRCUIT

Номер: US20130214715A1
Принадлежит: BROAD-OCEAN MOTOR EV CO., LTD.

A circuit for filtering narrow pulse and compensating wide pulse, including a signal shaping circuit, a filter circuit, and a pulse width compensating circuit. The signal shaping circuit processes an input signal and transmits the input signal to the filter circuit. The filter circuit filters off narrow pulses of the input signal. The pulse width compensating circuit compensates the wide pulses of the input signal and outputs an output signal. 22. The circuit of claim 1 , wherein the filter circuit () is an RC filter circuit.311. The circuit of claim 1 , wherein the signal shaping circuit () comprises a first Schmitt trigger (ICA).411. The circuit of claim 2 , wherein the signal shaping circuit () comprises a first Schmitt trigger (ICA).5. The circuit of claim 3 , wherein{'b': 3', '1', '1', '3', '4', '2, 'the pulse width compensating circuit () comprises a second Schmitt trigger (ICB), a triode (Q), a first resistor (R), a second resistor (R), and a capacitor (C);'}{'b': 2', '1, 'the input signal processed through the filter circuit () is connected with the second Schmitt trigger (ICB);'}{'b': '1', 'the signal is output from an output end of the second Schmitt trigger (ICB);'}{'b': 2', '4', '1, 'the capacitor (C) and the second resistor (R) are connected in series and connected to the output end and a grounded end of the Second Schmitt trigger (ICB), respectively;'}{'b': 2', '4', '1', '3, 'a node between the capacitor (C) and the second resistor R is connected with a base electrode of the triode (Q) after being connected with the first resistor (R);'}{'b': '1', 'an emitting electrode of the triode (Q) is grounded; and'}{'b': 1', '1, 'a collecting electrode of the triode (Q) is connected with an input end of the Second Schmitt trigger (ICB).'}6. The circuit of claim 4 , wherein{'b': 3', '1', '1', '3', '4', '2, 'the pulse width compensating circuit () comprises a second Schmitt trigger (ICB), a triode (Q), a first resistor (R), a second resistor (R), and a capacitor ( ...

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29-08-2013 дата публикации

Physical unclonable function cell and array

Номер: US20130222013A1
Принадлежит: International Business Machines Corp

A function cell comprising a first field effect transistor (FET) device, a second FET device, a first node connected to a gate terminal of the first FET device and a gate terminal of the second FET device, wherein the first node is operative to receive a voltage signal from an alternating current (AC) voltage source, an amplifier portion connected to the first FET device and the second FET device, the amplifier portion operative to receive a signal from the first FET device and the second FET device, a phase comparator portion having a first input terminal connected to an output terminal of the amplifier and a second input terminal operative to receive the voltage signal from the AC voltage source, the phase comparator portion operative to output a voltage indicative of a bit of a binary value.

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05-09-2013 дата публикации

Signal duty cycle detector and calibration system

Номер: US20130229216A1
Принадлежит: Mediatek Singapore Pte Ltd

A duty cycle detector and calibration system is disclosed. In some embodiments, a duty cycle calibration system includes a first tuning circuit operative to receive an input signal, tune a duty cycle of the input signal to within a first error range, and provide a first output signal. A second tuning circuit tunes a duty cycle of the first output signal to within a second error range and provides a second output signal, where the second error range has more precision than the first error range. A duty cycle detector provides a duty cycle detection signal indicative of a duty cycle of the second output signal, and logic controls the first and second tuning circuits based upon the duty cycle detection signal.

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12-09-2013 дата публикации

PWM DUTY CYCLE CONVERTER

Номер: US20130234769A1
Автор: Senda Yasutaka
Принадлежит: Denso Corporation

A PWM duty cycle converter includes a PWM signal generator, a timing signal generator, a limit signal generator, and a duty cycle limiter. The PWM signal generator generates a first PWM signal by comparing a triangular carrier wave with a duty command from a signal source. The timing signal generator generates a timing signal synchronously with at least one of a maximum value and a minimum value of the amplitude of the carrier wave. The limit signal generator generates a limit signal in response to the timing signal. The limit signal sets at least one of an upper limit and a lower limit on a duty cycle of the first PWM signal. The duty cycle limiter combines the first PWM signal and the limit signal to output a second PWM signal having a limited duty cycle. 1. A pulse width modulation (PWM) duty cycle converter comprising:a PWM signal generator configured to generate a first PWM signal by comparing a triangular carrier wave with at least one duty command from at least one signal source;a timing signal generator configured to generate a timing signal synchronously with at least one of a maximum value and a minimum value of an amplitude of the carrier wave;a limit signal generator configured to generate a limit signal in response to the timing signal, the limit signal setting at least one of an upper limit and a lower limit on a duty cycle of the first PWM signal, anda duty cycle limiter configured to combine the first PWM signal and the limit signal to output a second PWM signal having a limited duty cycle.2. The PWM duty cycle converter according to claim 1 , whereinthe PWM signal generator serially arranges a plurality of duty commands from a plurality of signal sources and generates the first PWM signal by comparing the carrier wave with the serially-arranged plurality of duty commands.3. The PWM duty cycle converter according to claim 2 , whereinthe duty cycle limiter adds a 100% duty cycle pulse to the second PWM signal, anda width of the 100% duty cycle pulse ...

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26-09-2013 дата публикации

Correction Circuit for Output Duty of Hall Element, Hall Sensor and Method of Correcting Output Duty of Hall Element

Номер: US20130249543A1
Автор: Lee Soo Woong
Принадлежит: SAMSUNG ELECTRO-MECHANICS CO., LTD

Disclosed herein are a correction circuit for output duty of a Hall element, a Hall sensor, and a method of correcting the output duty of the Hall element. According to an exemplary embodiment of the present invention, the correction circuit includes an amplification and output unit for amplifying an output of the Hall element and outputting a sqaure wave signal; a duty detection unit for detecting a duty ratio of the sqaure wave signal output by the amplification and output unit; and a duty correction unit for applying a feedback correction signal to the amplification and output unit accoring to the detected duty ratio. 1. A correction circuit for output duty of a Hall element , the correction circit comprising:an amplification and output unit for amplifying an output of the Hall element and outputting a sqaure wave signal;a duty detection unit for detecting a duty ratio of the sqaure wave signal output by the amplification and output unit; anda duty correction unit for applying a feedback correction signal to the amplification and output unit accoring to the detected duty ratio.2. The correction circit according to claim 1 , wherein the duty detection unit calculates the duty ratio by counting high sections and low sections according to previously set clocks during one cycle of the square wave signal.3. The correction circit according to claim 1 , wherein the duty correction unit includes:a state machine for generating a duty ratio correction bit according to the duty ratio detected by the duty detection unit; anda hysteresis section control unit for feeding back and controlling a width of a hysteresis section for outputting the square wave signal, according to the duty ratio correction bit generated by the state machine.4. The correction circit according to claim 2 , wherein the duty correction unit includes:a state machine for generating a duty ratio correction bit according to the duty ratio detected by the duty detection unit; anda hysteresis section control ...

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03-10-2013 дата публикации

High speed duty cycle correction and double to single ended conversion circuit for pll

Номер: US20130257499A1

The present invention pertains to a high speed duty cycle correction and double to single ended conversion circuit for PLL, comprising a reshaper stage, a single-edge detection circuit and a duty cycle restorer. The present invention introduces a way to convert double-ended output of PLL VCO into single-ended signal and adjust duty cycle of PLL VCO's output waveform by 50%, so that the circuit can output single ended clock signal with 50% duty cycle.

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10-10-2013 дата публикации

Frequency multiplier circuit with function of automatically adjusting duty cycle of output signal and system thereof

Номер: US20130265087A1
Автор: Fan Fangping
Принадлежит: IP Microelectronics (Sichuan) Co., Ltd.

A frequency multiplier circuit with a function of automatically adjusting a duty cycle of an output signal includes an input terminal, a first detecting unit, a second detection unit, a duty cycle adjusting unit and a ground terminal; wherein the frequency multiplier control unit includes a first buffer, an AND gate, a first NOR gate and a second NOR gate; wherein the first detecting unit includes an inverter, a first resistance and a first capacitance; wherein the second detecting unit includes a second buffer, a second resistance and a second capacitance; wherein the duty cycle adjusting unit includes a comparator connected to the first resistance, the first capacitance, the second resistance, the second capacitance and the first buffer. The present invention also provides a frequency multiplier system thereof. The present invention is capable of automatically adjusting a duty cycle of an output signal to 50%. 1. A frequency multiplier circuit with a function of automatically adjusting a duty cycle of an output signal , comprising:an input terminal,a frequency multiplier control unit connected to said input terminal,an output terminal connected to said frequency multiplier control unit,a first detecting unit connected to said frequency multiplier control unit and said output terminal,a second detection unit connected to said frequency multiplier control unit and said output terminal,a duty cycle adjusting unit connected to said first detecting unit, said second detecting unit and said frequency multiplier control unit, anda ground terminal connected to said first detecting unit and said second detecting unit;wherein said frequency multiplier control unit comprises:a first buffer connected to said input terminal,an AND gate connected to said input terminal and said first buffer,a first NOR gate connected to said input terminal and said first buffer, anda second NOR gate connected to said AND gate and said first NOR gate;wherein said first detecting unit comprises: ...

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31-10-2013 дата публикации

DUTY CYCLE DISTORTION CORRECTION CIRCUITRY

Номер: US20130285725A1
Принадлежит:

Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high. 1. A circuit , comprising:an input that receives a control signal having a duty cycle; andan output on which an output clock signal is generated, wherein the output clock signal has a duty cycle that is set by the control signal and that is different than the duty cycle of the control signal.2. The circuit defined in claim 1 , wherein the control signal received at the input comprises an input clock signal.3. The circuit defined in claim 1 , further comprising:an additional input that receives another control signal, wherein the control signal is a delayed version of the another control signal.4. The circuit defined in claim 1 , further comprising:an additional input that receives another control signal, wherein the control signal is a delayed version of the another control signal, and wherein the control signal is delayed by an amount with respect to the another control signal that sets the duty cycle of the output clock signal.5. The circuit defined in claim 1 , further comprising:a first additional input that receives a first additional ...

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31-10-2013 дата публикации

FORWARDED CLOCK JITTER REDUCTION

Номер: US20130285726A1
Принадлежит:

In some embodiments, a differential amplifier with duty cycle correction is provided. 1. A chip , comprising:a differential amplifier to receive a differential clock; andan offset compensation circuit coupled to the amplifier to adjust offset in the differential clock, the offset compensation circuit to be digitally controlled based on offset in the differential clock.2. The chip of claim 1 , in which the differential clock is a forwarded clock from another chip.3. The chip of claim 1 , in which the offset compensation circuit is disposed between the amplifier and electrical contacts for receiving the clock from off of the chip.4. The chip of claim 1 , in which the offset compensation circuit is part of an active filter circuit.5. The chip of claim 4 , in which the active filter circuit implements a continuous time linear equalizer circuit.6. The chip of claim 1 , comprising a variable offset comparator to receive a low-pass filtered version of the differential clock to generate a digital value representing whether or not a duty cycle of the clock is above or below a threshold.7. The chip of claim 6 , in which the duty cycle threshold is 50%.8. The chip of claim 1 , comprising a switch to receive a failover clock to be used as the differential clock.9. A chip claim 1 , comprising:a differential amplifier having an input to receive a differential clock and an output to provide a duty cycle adjusted clock; andan offset adjustment circuit coupled between the input and output, said offset adjustment circuit including a variable offset comparator (VOC) with self offset correction, a differential offset compensation (DOC) circuit having an output coupled to the input of the differential amplifier, and a control circuit coupled between the VOC and DOC to control output clock duty cycle.10. The chip of claim 9 , in which the differential clock is a forwarded clock from another chip.11. The chip of claim 9 , in which the offset compensation circuit is disposed between the ...

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14-11-2013 дата публикации

METHOD AND DEVICE FOR GENERATING SHORT PULSES

Номер: US20130300479A1
Автор: Thibault Pierre F.
Принадлежит:

There is described a method and corresponding pulse generating device, for generating an output pulse signal having an output pulse duration. The method comprises: receiving at an input port an input pulse signal comprising an input pulse duration; duplicating the input pulse signal into a first digital pulse signal and a second digital pulse signal each comprising the input pulse duration; delaying at least one of the first and the second digital pulse signals by a time delay to obtain respectively a first and a second delayed digital pulse signal, a time delay difference between the first and the second delayed digital pulse signals being substantially equal to the output pulse duration; logically combining the first and the second delayed digital pulse signals to generate the output pulse signal with the output pulse duration smaller than the input pulse duration; and outputting the output pulse signal at an output port. 1. A pulse generating device for generating an output pulse signal having an output pulse duration , the device comprising:a signal duplicator for receiving an input pulse signal comprising an input pulse duration, the signal duplicator for duplicating the input pulse signal into a first digital pulse signal and a second digital pulse signal each comprising the input pulse duration;a delay component operatively coupled to the signal duplicator, the delay component for delaying at least one of the first and the second digital pulse signals by a time delay to obtain respectively a first and a second delayed digital pulse signal, a time delay difference between the first and the second delayed digital pulse signals being substantially equal to the output pulse duration; anda logic circuit coupled to the delay component, the logic circuit for combining logically the first and the second delayed digital pulse signals to generate the output pulse signal with the output pulse duration smaller than the input pulse duration, the logic circuit for ...

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14-11-2013 дата публикации

EDGE SELECTION TECHNIQUES FOR CORRECTING CLOCK DUTY CYCLE

Номер: US20130300481A1

Circuits and methods are provided for generating clock signals and correcting duty cycle distortion in clock signals. A circuit for generating a clock signal includes a multiplexer circuit and an edge-triggered flip-flop circuit. The multiplexer circuit selectively outputs one of a plurality of input clock signals. The edge-triggered flip-flop detects a transitioning edge of the input clock signal that is selectively output from the multiplexer circuit, and in response to the detection, samples a logic level of a received data signal, and generates a transition of an output clock signal at an output port of the edge-triggered flip-flop. The multiplexer circuit selectively outputs one of the plurality of input clock signals to a clock signal port of the edge-triggered flip-flop, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop, which is input to a select control port of the multiplexer circuit. 1. A circuit for generating a clock signal , comprising:a multiplexer circuit to selectively output one of a plurality of input clock signals; andan edge-triggered flip-flop circuit comprising a clock signal port, a data signal port, and an output port, wherein the clock signal port is connected to an output of the multiplexer circuit, wherein the data signal port receives a data signal, and wherein the output port of the edge-triggered flip-flop is connected to a select control port of the multiplexer circuit,wherein the edge-triggered flip-flop detects a transitioning edge of an input clock signal that is selectively output from the multiplexer circuit, and in response to said detection, samples a logic level of the received data signal, and generates a transition of an output clock signal at the output port, andwherein the multiplexer circuit selectively outputs one of the plurality of input clock signals to the clock signal port of the edge-triggered flip-flop, based on a logic level of the output clock signal at the ...

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21-11-2013 дата публикации

PULSE WIDTH MODULATION CIRCUIT AND PULSE WIDTH MODULATION SIGNAL GENERATING METHOD HAVING TWO FRESH RATES

Номер: US20130307634A1
Принадлежит: SILICON TOUCH TECHNOLOGY INC.

A PWM circuit that can have two fresh rates, including: a first PWM signal generator and a second PWM signal generator; wherein the first PWM signal generator and the second PWM signal generator respectively control refresh rates in two dimensions of an output data generated from a target apparatus. A PWM signal generation method that can have two fresh rates, including: generating a first PWM signal; generating a second PWM signal; and controlling refresh rates in different dimensions of an output data generated from a target apparatus respectively by using the first PWM signal and the second PWM signal. 1. A pulse width modulation (PWM) circuit having two fresh rates , comprising:a first PWM signal generator; anda second PWM signal generator;wherein the first PWM signal generator and the second PWM signal generator control refresh rates in different dimensions of an output data generated from a target apparatus, respectively.2. The PWM circuit of claim 1 , wherein the target apparatus is a light processing device claim 1 , and the first PWM signal generator and the second PWM signal generator are arranged to control brightness of the output data in the different dimensions claim 1 , respectively.3. A pulse width modulation (PWM) circuit having two fresh rates claim 1 , the PWM circuit being employed in a target apparatus to make the target apparatus generate an output data claim 1 , the output data comprising a plurality of data units claim 1 , the PWM circuit comprising:a first PWM signal generator; anda second PWM signal generator;wherein the first PWM signal generator controls a first part of each of the data units, and the second PWM signal generator controls a second part of each of the data units, such that the output data has two refresh rates.4. The PWM circuit of claim 3 , wherein the second part is located in a same position in each of the data units.5. The PWM circuit of claim 3 , wherein a position of the second part of each of the data units meets a ...

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28-11-2013 дата публикации

DUTY CYCLE CORRECTOR

Номер: US20130314137A1
Автор: CHANG Chun-Chi
Принадлежит:

A duty cycle corrector includes an SR latch, a first switch and a second switch. The SR latch is configured to generate first and second control signals according to first and second clocks. The first switch is coupled between a work voltage and an output node, and selectively closes and opens according to the first control signal. The second switch is coupled between the output node and a ground voltage, and selectively closes and opens according to the second control signal. The output node is used to output an output clock. 1. A duty cycle corrector , comprising:an SR latch, generating a first control signal and a second control signal according to a first clock and a second clock;a first switch, coupled between a work voltage and an output node, and selectively closing and opening according to the first control signal; anda second switch, coupled between the output node and a ground voltage, and selectively closing and opening according to the second control signal,wherein the output node is used to output an output clock.2. The duty cycle corrector as claimed in claim 1 , wherein a phase difference between the first clock and the second clock is equal to 180 degrees.3. The duty cycle corrector as claimed in claim 1 , wherein the SR latch comprises: a first input terminal, receiving the first clock;', 'a second input terminal; and', 'a first output terminal, outputting the first control signal; and, 'a first NAND gate, having a third input terminal, coupled to the first output terminal;', 'a fourth input terminal, receiving the second clock; and', 'a second output terminal, coupled to the second input terminal, and outputting the second control signal., 'a second NAND gate, having4. The duty cycle corrector as claimed in claim 3 , wherein the first switch comprises:a first transistor, coupled between the work voltage and the output node, anda second transistor, coupled between the work voltage and the output node, and having a second gate coupled to the first ...

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12-12-2013 дата публикации

DUTY RATIO CORRECTION CIRCUIT, DOUBLE-EDGED DEVICE, AND METHOD OF CORRECTING DUTY RATIO

Номер: US20130328602A1
Автор: KIBUNE Masaya
Принадлежит:

A duty ratio correction circuit, includes: a frequency divider configured to output a second clock signal having a first level that is inverted at a timing of a first edge of a first clock signal and a third clock signal having a second level that is inverted at a timing of a second edge of the first clock signal; phase interpolator configured to generate a fourth clock signal and a fifth clock signal based on phase interpolation of any two of the second clock signal, the third clock signal, a first inverted signal that is obtained by inverting the second clock signal, or a second inverted signal that is obtained by inverting the third clock signal; and a multiplier configured to output an exclusive OR signal of the fourth clock signal and the fifth clock signal as a sixth clock signal. 1. A duty ratio correction circuit , comprising:a frequency divider configured to output a second clock signal having a first level that is inverted at a timing of a first edge of a first clock signal and a third clock signal having a second level that is inverted at a timing of a second edge of the first clock signal;a phase interpolator configured to generate a fourth clock signal and a fifth clock signal based on phase interpolation of any two of the second clock signal, the third clock signal, a first inverted signal that is obtained by inverting the second clock signal, or a second inverted signal that is obtained by inverting the third clock signal; anda multiplier configured to output an exclusive OR signal of the fourth clock signal and the fifth clock signal as a sixth clock signal.2. The duty ratio correction circuit according to claim 1 , whereinthe first edge corresponds to a rising edge of the first clock signal, andthe second edge corresponds to a falling edge of the first clock signal.3. The duty ratio correction circuit according to claim 1 , whereinthe phase interpolator generates the fourth clock signal by phase interpolation of the second clock signal and the third ...

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12-12-2013 дата публикации

INTEGRATED CIRCUITS WITH DUAL-EDGE CLOCKING

Номер: US20130328606A1
Автор: Lewis David, Ravi Ajay K.
Принадлежит: Altera Corporation

Integrated circuits that support dual-edge clocking are provided. Integrated circuits may include phase-locked loops that generate square-wave clock signals. The clock signals may be provided from off-chip equipment through input-output pins. The clock signals may be routed through a clock distribution network to provide local clock signals to pulse generators that generate clock pulses on rising and falling clock edges. The pulse generators may generate clock pulses that are triggered by the rising and falling clock edges with a common pulse width for optimum performance. Duty cycle distortion introduced by the clock network may be minimized for optimum performance. Adaptive duty cycle distortion circuitry may be used to control the pull-up/pull-down drive strengths of the clock buffer so that the high clock phase of the local clock signals is approximately a half clock cycle. 1. Duty cycle distortion correction circuitry , comprising:a driver circuit that outputs a first clock signal;an input that receives a second clock signal, wherein the second clock signal is generated based on the first clock signal;a first register transfer circuit that receives the second clock signal and generates a first error signal;a second register transfer circuit that receives the second clock signal and generates a second error signal; andcontrol circuitry that receives the first and second error signals and that controls the driver circuit so that the second clock signal exhibits a predetermined duty cycle.2. The duty cycle distortion correction circuitry defined in claim 1 , wherein the first register transfer circuit includes a test data generation circuit.3. The duty cycle distortion correction circuitry defined in claim 2 , wherein the test data generation circuit includes a flip-flop coupled to an inverter.4. The duty cycle distortion correction circuitry defined in claim 2 , wherein the first register transfer circuit further includes a delay circuit coupled to the test data ...

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26-12-2013 дата публикации

METHOD FOR GENERATING PWM SIGNALS AND A PULSE WIDTH MODULATION POWER CONVERTER

Номер: US20130342179A1
Принадлежит: ZENTRUM MIKROELEKTRONIK DRESDEN AG

A method and an apparatus for generating PWM signals is provided. Upon detection of a load transient, a new PWM period is started if the load transient occurs during the off-time of a PWM signal and exceeds a specific magnitude. 1. A method for generating PWM signals , wherein an output voltage is generated according to a pulse width modulation signal and an input voltage;an error signal is generated by sampling the output voltage and differencing the sampled output voltage and an output voltage reference;a duty ratio that defines a duty cycle of a pulse width modulation signal is determined by a PID controlling algorithm;the pulse width modulation signal is generated by providing the duty ratio to a pulse width modulator; andthe duty ratio is continuously monitored within one PWM period and compared to its predecessor by computing a duty ratio difference and in case the duty ratio difference exceeds a threshold during an off-time of the pulse width modulation signal, the pulse width modulator is triggered to start a new nominal pulse width modulation period.2. The method according to wherein the duty ratio is monitored in case a load transient is detected.3. The method according to wherein the load transient is detected by continuously monitoring the error signal.4. The method according to claim 1 , wherein the output voltage and/or the error signal is oversampled by sampling a plurality of error signals within one PWM period.5. The method according to claim 1 ,wherein a moving average of the sampled error signal is computed.6. The method according to claim 1 , wherein a first set of PID coefficients is selected in case a steady state is detected and a second set of PID coefficients is selected in case a load transient is detected.7. The control method according to claim 6 , wherein a nonlinear gain KP is selected in case of load transient detection.8. A pulse width modulation power converter claim 6 , comprising:an output stage generating an output voltage ...

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26-12-2013 дата публикации

Real Time Automatic and Background Calibration at Embedded Duty Cycle Correlation

Номер: US20130342252A1

The present disclosure relates to a clock generation system. The system includes a clock source, a tuning buffer, an output buffer, a duty cycle measurement circuit and an automatic calibration component. The clock source generates a clock signal. The tuning buffer is configured to generate a corrected clock signal from the clock signal according to adjustment values. The output buffer is configured to generate an output clock signal from the corrected clock signal. The duty cycle measurement circuit is configured measure a duty cycle of the output clock signal. The automatic calibration component is configured to generate the adjustment values according to the duty cycle measurement and the specification values.

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02-01-2014 дата публикации

Clock correction circuit and clock correction method

Номер: US20140002147A1
Принадлежит: Renesas Electronics Corp

An operation clock generation circuit performs a calculation on the basis of the frequency errors of a fundamental clock and the clock pulses of the fundamental clock, and generates an operation clock obtained by correcting the frequency errors at first intervals. A correction clock generation circuit converts a lower-bit value that is a value represented by the bits lower than the predefined bit used for judging the change of the state of the operation clock into a count number of the clock pulses of a second clock whose frequency is higher than that of the operation clock, generates a correction clock obtained by correcting the operation clock on the basis of a time required for counting the count number of the clock pulses and the clock pulses of the operation clock.

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02-01-2014 дата публикации

DUTY CYCLE ERROR ACCUMULATION CIRCUIT AND DUTY CYCLE CORRECTION CIRCUIT HAVING THE SAME

Номер: US20140002157A1
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A duty cycle error accumulation circuit includes first to nth delay units and a feedback unit. The first to nth delay units receive a clock signal, a first input signal and a second input signal, respectively, to generate a first output signal and a second output signal by delaying one signal selected from first and second input signals based on a logic level of the clock signal. The feedback unit supplies second input signal to a kth delay unit based on second output signal of a (k+1)th delay unit. The first output signal of the kth delay unit is supplied to the (k+1)th delay unit as first input signal, and the clock signal is supplied to the first delay unit as first input signal and to the nth delay unit as second input signal. The duty cycle error accumulation circuit effectively corrects a duty cycle of a clock signal. 1. A duty cycle error accumulation circuit , comprising:{'sup': 'th', 'first to ndelay units (n is an integer of 2 or more) to receive a clock signal, a first input signal and a second input signal, respectively, to generate a first output signal and a second output signal by delaying one signal selected from the first and second input signals based on a logic level of the clock signal; and'}{'sup': th', 'th, 'a feedback unit to supply the second input signal to a kdelay unit based on the second output signal of a (k+1)delay unit (k is a positive integer of (n−1) or less),'}{'sup': th', 'th', 'th, 'wherein the first output signal of the kdelay unit is supplied to the (k+1)delay unit as the first input signal, and the clock signal is supplied to the first delay unit as the first input signal and to the ndelay unit as the second input signal.'}2. The duty cycle error accumulation circuit of claim 1 , wherein each of the first to ndelay units generates the first output signal by delaying the first input signal for a first time when the clock signal has a logic low level claim 1 , and generates the second output signal by delaying the second input ...

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02-01-2014 дата публикации

HIGH-SPEED FULLY-DIFFERENTIAL CLOCK DUTY CYCLE CALIBRATION CIRCUIT

Номер: US20140002158A1
Принадлежит: SOUTHEAST UNIVERSITY

A high-speed fully differential clock duty cycle calibration circuit applied to calibrating the clock duty cycle in a high-speed system. The circuit detects the duty cycle with a continuous time integrator, and directly adjusts the duty cycle on a clock transmission link so as to increase the working speed. Being of a fully differential circuit structure, the circuit can calibrate the duty cycle under a designated process within a higher and wider frequency range, and has relatively good constraining force for process mismatch and common mode noise. The circuit comprises adjustment level ADJ and ADJ, a first buffer level BUF, a second buffer level BUF and a duty cycle detection level DCD. 11122. A duty cycle calibration circuit for a high-speed full-differential clock , comprising: a first adjustment stage ADJ , a first buffer stage BUF , a second adjustment stage ADJ , a second buffer stage BUF , and a duty cycle detection stage DCD , wherein:{'b': '1', 'a first and a second signal input terminal at the left side of the first adjustment stage ADJ are connected to raw differential input signals (CLK+ and CLK−) to be calibrated;'}{'b': 1', '1', '1', '1, 'output signals OUT− and OUT+ from a first and a second output terminal of the first adjustment stage ADJ are connected to a first and a second signal input terminal of the first buffer stage BUF;'}{'b': 1', '1', '1', '2, 'output signals OUTB+ and OUTB− from a first and second signal output terminal of the first buffer stage BUF are connected to a first and a second signal input terminal of the second adjustment stage ADJ, to continue to calibrate the duty cycle further;'}{'b': 2', '2', '2', '2, 'output signals OUT− and OUT+ from a first and a second signal output terminal of the second adjustment stage ADJ are connected to a first and a second signal input terminal of the second buffer stage BUF;'}{'b': 2', '2, 'output signals CKO+ and CKO− from a first and a second signal output terminal of the second buffer stage ...

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13-02-2014 дата публикации

Pulsed Gate Driver

Номер: US20140043076A1
Автор: Hesener Alfred
Принадлежит: Fairchild Semiconductor Corporation

A gate driver includes a control input receiving a control signal, an output to provide an amplified output signal to the gate, and controller. The controller produces an adaptive pulse train varying with the control signal. An adaptive incrementer produces a sequence of numbers that set a slew rate of the switch, and a look-up table is fed with the sequence of numbers, and associates the numbers produced by the adaptive incrementer with values representing the duty cycle of the output signal to control the slew rate of the switch. The switch can be driven at various intermediate levels, and allows gate drive conditions to adapted to abnormal system states by varying the control input signal. The adaptive response allows the slew rate to vary without replacing any gate driver circuit components. Because the gate current is provided adaptively, the delivery of gate current results in low power dissipation. 1. A gate driver for driving a gate of a switch , the gate driver comprising:a control input which is adapted to receive a control signal;an output which is adapted to provide an amplified output signal to be fed to the gate of the switch for driving the switch; anda controller comprising an adaptive incrementer and a look-up table,wherein the controller is connected between the control input and the output, and is adapted to produce an adaptive pulse train that varies depending on a characteristic of the control signal,wherein the adaptive incrementer is adapted to produce a sequence of numbers, the values of which allow a slew rate of the switch to be set, andwherein the look-up table is adapted to be fed with the sequence of numbers, and to associate the numbers produced by the adaptive incrementer with values representing the duty cycle of the output signal so as to control the slew rate of the switch.2. The gate driver of claim 1 , wherein the controller is adapted to vary the adaptive pulse train according to the characteristic of the control signal so as to ...

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13-02-2014 дата публикации

Integrated circuit having a multiplying injection-locked oscillator

Номер: US20140043105A1
Принадлежит: RAMBUS INC

Methods and apparatuses featuring a multiplying injection-locked oscillator are described. Some embodiments include a pulse-generator-and-injector and one or more injection-locked oscillators. The outputs of the pulse-generator-and-injector can be injected into corresponding injection points of an injection-locked oscillator. In embodiments that include multiple injection-locked oscillators, the outputs of each injection-locked oscillator can be injected into the corresponding injection points of the next injection-locked oscillator. Some embodiments reduce deterministic jitter by dynamically modifying the loop length of an injection-locked oscillator, and/or by using a duty cycle corrector, and/or by multiplexing/blending the outputs from multiple delay elements of an injection-locked oscillator.

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27-02-2014 дата публикации

Systems and methods for improving the time alignment of non-overlapping waveforms

Номер: US20140057586A1
Автор: Alford Ronald C.
Принадлежит: CSR TECHNOLOGY

Systems and methods for improving the timing alignment of non-overlapping waveforms are provided. In this regard, a representative system, among others, includes a waveform synthesizer that generates a plurality of input waveforms and inverters having inputs and outputs, wherein the inverters receive the input waveforms at the inputs of the inverters and invert the input waveforms, producing a plurality of inverted waveforms at the outputs of the inverters. The system also includes NOR gates having inputs and outputs, wherein the NOR gates receive the plurality of inverted waveforms at the inputs of the NOR gates and pass through one of the inverted waveforms at the outputs of the NOR gates. 120-. (canceled)21. A system for improving the timing alignment of a non-overlapping waveforms comprising:a waveform synthesizer that generates a plurality of input waveforms;inverters having inputs and outputs, wherein the inverters receive the input waveforms at the inputs of the inverters and invert the input waveforms, producing a plurality of inverted waveforms at the outputs of the inverters; andNOR gates having inputs and outputs, wherein the NOR gates receive the plurality of inverted waveforms at the inputs of the NOR gates and pass through one of the inverted waveforms at the outputs of the NOR gates.22. The system as defined in claim 21 , wherein the NOR gates de-skew the received plurality of inverted waveforms.23. The system as defined in claim 21 , wherein the waveform synthesizer generates a plurality of duty cycle input waveforms that are in various degrees out of phase.24. The system as defined in claim 23 , wherein the inverters include a plurality of inverters that invert the plurality of duty cycle input waveforms claim 23 , producing a plurality of duty cycle inverted waveforms that are in various degrees out of phase claim 23 , respectively.25. The system as defined in claim 24 , wherein the NOR gates receive the plurality of duty cycle inverted waveforms ...

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06-03-2014 дата публикации

METHOD AND SYSTEMS FOR HIGH-PRECISION PULSE-WIDTH MODULATION

Номер: US20140062551A1
Принадлежит:

In various embodiments, systems and methods for generating high-precision pulse-width modulation include a delay-locked loop comprising multiple delay units having time-variable delays, control logic for selecting a subset S of the multiple delay units to thereby generate a time-invariant shift amount having a precision finer than that of a system clock and circuitry for applying the shift amount to rising and falling edges of a pulse-width modulation waveform to thereby generate a high-precision pulse-width modulation waveform. 1. A method for generating high-precision pulse-width modulation , the method comprising:calibrating a delay line comprising a plurality of delay units to a system clock, each delay unit having a delay that may vary with time;determining a desired number of partitions of the system clock;mathematically selecting a subset of the partitions, wherein the subset of the partitions corresponds to a desired amount to shift rising and falling edges of a low-precision pulse-width modulation waveform;generating the desired shift amount by applying, to the subset of partitions, a calibration code corresponding to the calibrated delay line, wherein the shift amount is less than a period of the system clock; andapplying the shift amount to rising and falling edges of a low-precision pulse-width modulation waveform to thereby generate a high-precision pulse-width modulation waveform having a precision finer than that of the system clock.2. The method of claim 1 , wherein a number of the subset of partitions is P out of 2possible partitions claim 1 , wherein M is an integer greater than or equal to 1 and P is an integer greater than or equal to 1 but less than or equal to 2.3. The method of claim 1 , wherein the desired shift amount of P out of 2partitions of the system clock is represented using a M-bit digital word stored in a hardware register.4. The method of claim 1 , wherein the desired shift amount of P out of 2partitions of the system clock is ...

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06-03-2014 дата публикации

SYSTEM AND METHOD OF ADJUSTING A CLOCK SIGNAL

Номер: US20140062559A1
Принадлежит: QUALCOMM INCORPORATED

A method includes receiving an input clock signal at a programmable buffer. The method further includes filtering an output signal from the programmable buffer to generate a filtered signal having a voltage level, where the voltage level indicates a duty cycle of the output signal. The method further includes comparing the voltage level to a reference voltage. The method further includes modifying at least one operating parameter of the programmable buffer to adjust the duty cycle of the output signal. 1. A method comprising:receiving an input clock signal at a programmable buffer;filtering an output signal from the programmable buffer to generate a filtered signal having a voltage level, the voltage level indicating a duty cycle of the output signal;comparing the voltage level to a reference voltage; andmodifying at least one operating parameter of the programmable buffer to adjust the duty cycle of the output signal.2. The method of claim 1 , wherein the programmable buffer is configured to selectively charge and discharge a node based on a digital voltage level of the input clock signal and based on the at least one operating parameter claim 1 , wherein the duty cycle of the output signal is responsive to a charging rate and a discharging rate of the node.3. The method of claim 2 , wherein charging the node includes selectively activating at least one p-type metal oxide semiconductor (PMOS) transistor based on the at least one operating parameter.4. The method of claim 2 , wherein discharging the node includes selectively activating at least one n-type metal oxide semiconductor (NMOS) transistor based on the at least one operating parameter.5. The method of claim 1 , wherein the output signal is an output clock signal.6. The method of claim 1 , wherein the output signal has a duty cycle of fifty percent in response to modifying the at least one operating parameter.7. The method of claim 6 , wherein a duty cycle of the input clock signal is not fifty percent.8. ...

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27-03-2014 дата публикации

SELF-ADJUSTING DUTY CYCLE TUNER

Номер: US20140084979A1
Автор: Yasuda Takeo

A duty cycle tuner measures high and low periods of a signal, calculates an actual duty cycle, generates duty control signals based on the actual duty cycle and a desired duty cycle, and adjusts the duty cycle responsive to the duty control signals. The high and low periods are measured using high-speed counters to provide a high count for the high period and a low count for the low period. The actual duty cycle value is then computed from the high and low counts, and compared to the desired duty cycle value to generate increment and decrement signals which may be positive or zero, to increase, decrease or maintain the actual duty cycle. In this manner, even if the high and low counts are subject to variations due to process, temperature or power supply voltage, their ratio is independent of such variations, so the tuner is immune to those effects. 1. A method of tuning the duty cycle of a target signal comprising:measuring a high period of the target signal;measuring a low period of the target signal;calculating an actual duty cycle value of the target signal based on measurements of the high period and the low period;generating one or more duty control signals based on the actual duty cycle value and a desired duty cycle value; andautomatically adjusting the duty cycle of the target signal using a duty cycle controller responsive to the one or more duty control signals.2. The method of wherein:the one or more duty control signals include an increment signal and a decrement signal; andthe duty cycle controller increases the duty cycle of the target signal when the increment signal has a positive value, decreases the duty cycle of the target signal when the decrement signal has a positive value, and does not change the duty cycle of the target signal when both the increment and decrement signals are set to zero.3. The method of wherein:the high period is measured by counting a number of first high-speed pulses occurring during a high state of the target signal to ...

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01-01-2015 дата публикации

Semiconductor device having duty correction circuit

Номер: US20150002201A1
Принадлежит: Micron Technology Inc

Disclosed herein is a device includes a duty correction circuit adjusting a duty ratio of a first clock signal based on a duty control signal to generate a second clock signal; a delay line delaying the second clock signal to generate a third clock signal; and a duty cycle detector detecting the duty ratio of the second clock signal to generate the duty control signal in a first mode, and detecting the duty ratio of the third clock signal to generate the duty control signal in a second mode.

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05-01-2017 дата публикации

EFFICIENT HIGH VOLTAGE SQUARE WAVE GENERATOR

Номер: US20170005646A1
Автор: Hargreaves Kirk
Принадлежит: SYNAPTICS INCORPORATED

This disclosure generally provides a system, active input device, and method for generating an amplified square wave signal based on an input signal. The method comprises generating a pulse signal based on the input signal, and driving a switching signal based on the pulse signal to control a first switch. A pulse width of the pulse signal is adaptively controlled using a control signal generated based on the amplified square wave signal. An output terminal of the first switch is coupled with a second switch, and the switching signal controls current entering into the second switch. The method further comprises driving the input signal to control a third switch coupled with the second switch. The amplified square wave signal is generated at the second output terminal based on the switching signal and on the input signal. 1. A system for generating an amplified square wave signal based on an input signal , the system comprising:a variable-width pulse generator configured to generate, based on the input signal, a pulse signal having a pulse width;a feedback module configured to generate a control signal based on the amplified square wave signal, the pulse width of the pulse signal based on the control signal;a first switch having a first control terminal and a first output terminal;a second switch having a second control terminal and a second output terminal, the second output terminal coupled with the first control terminal of the first switch, wherein the second switch is configured to receive at the second control terminal a first switching signal based on the pulse signal; anda third switch having a third control terminal and a third output terminal, the third output terminal coupled with the first output terminal of the first switch, wherein the third switch is configured to receive a second switching signal at the third control terminal,wherein in response to the first and second switching signals provided to the second and third switches, the amplified square ...

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04-01-2018 дата публикации

APPARATUSES AND METHODS FOR PHASE INTERPOLATING CLOCK SIGNALS AND FOR PROVIDING DUTY CYCLE CORRECTED CLOCK SIGNALS

Номер: US20180006636A1
Автор: Ma Yantao
Принадлежит: MICRON TECHNOLOGY, INC.

Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes a clock generator circuit configured to provide first and second clock signals responsive to an input clock signal. A duty phase interpolator circuit may be coupled to the clock generator circuit and configured to provide a first and second duty cycle corrected interpolated clock signals. A duty cycle adjuster circuit may be coupled to the duty phase interpolator circuit and configured to receive the first and second duty cycle corrected interpolated clock signals and provide a duty cycle corrected clock signal responsive thereto. A duty cycle detector may be coupled to the duty cycle adjuster circuit and configured to detect duty cycle error of the duty cycle corrected clock signal and provide the adjustment signals to correct the duty cycle error. 1. An apparatus , comprising: a delay generator circuit configured to provide a start signal and further configured to provide a stop signal following the start signal after one cycle of the input clock signal;', 'a first delay line coupled to the delay generator circuit and configured to delay the start signal through a plurality of first delay stages;', 'a delay control logic circuit coupled to the delay generator circuit and the first delay line, the delay control logic configured to activate the first delay line to delay the start signal, and the delay control logic further configured to determine a number of first delay stages of the plurality of first delay stages through which the start signal propagates responsive to the stop signal and to provide control signals representing the number of first delay stages of the plurality of delay stages;', 'a second delay line coupled to the delay control logic and configured to delay the input clock signal through a plurality of second delay stages to provide the second clock signal, a number of second delay stages of ...

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07-01-2021 дата публикации

ERROR DETECTION AND COMPENSATION FOR A MULTIPLEXING TRANSMITTER

Номер: US20210006238A1
Принадлежит:

Various aspects provide for error detection and compensation for a multiplexing transmitter. For example, a system can include an error detector circuit and a duty cycle correction circuit. The error detector circuit is configured to measure duty cycle error for a clock associated with a transmitter to generate error detector output based on a clock pattern for output generated by the transmitter in response to a defined bit pattern. The duty cycle correction circuit is configured to adjust the clock associated with the transmitter based on the error detector output. Additionally or alternatively, the error detector circuit is configured to measure quadrature error between an in-phase clock and a quadrature clock in response to the defined bit pattern. Additionally or alternatively, the system can include a quadrature error correction circuit configured to adjust phase shift between the in-phase clock and the quadrature clock based on quadrature error. 1. A system for reducing error associated with a multiplexing transmitter , comprising:an error detector circuit configured to measure a quadrature error for a clock associated with a transmitter to generate first error detector information based on a first clock pattern for a first output generated by the transmitter in response to a defined bit pattern, and generate second error detector information based on a second clock pattern for a second output generated by the transmitter in response to an inverted version of the defined bit pattern, wherein the error detector circuit is further configured to determine a first average value of the first error detector information and a second average value of the second error detector information, determine a differential average value of the first average value and the second average value based on a comparison of the first average value to the second average value, and determine an error detector output based on the differential average value; anda duty cycle correction ...

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03-01-2019 дата публикации

Clock Duty Cycle Calibration and Frequency Multiplier Circuit

Номер: US20190007036A1
Автор: FU Zhuojian
Принадлежит:

Provided is a clock duty cycle calibration and frequency multiplier circuit used in a square wave frequency multiplier, comprising: a multiplexing module (), which performs a phase-inversion operation on a clock signal according to a control signal; a calibration module () which adjusts the duty cycle according to a control signal, and outputs a clock signal with a 50% duty cycle; a delay module (), which performs a delay operation on the clock signal according to a control signal; a detection module (), which compares the clock signal and outputs a feedback signal; a control module (), which outputs a control signal according to the feedback signal; a frequency multiplication module (), which performs a frequency multiplication operation on the clock signal. Therefore, high-precision clock signal frequency multiplication is implemented with relatively low circuit complexity and low cost. 1. A clock duty cycle calibration and frequency multiplier circuit , comprising:{'b': 2', '1, 'a multiplexing module, configured to output a second clock signal (CK) after inverting an input first clock signal (CKin) based on a first control signal (V);'}{'b': 2', '2', '3, 'a calibration module, configured to adjust a duty cycle of the second clock signal (CK) based on a second control signal (V), and finally output a third clock signal (CK) with a 50% duty cycle;'}{'b': 4', '3', '3, 'a delay module, configured to output a fourth clock signal (CK) after performing a delay operation on the third clock signal (CK) based on a third control signal (V);'}{'b': 3', '4, 'a detection module, configured to compare the third clock signal (CK) and the fourth clock signal (CK) that are input thereto, and output a feedback signal (Va) based on a comparison result;'}{'b': 1', '2', '3, 'a control module, configured to output the first control signal (V), the second control signal (V), and the third control signal (V) based on the input feedback signal (Va); and'}{'b': '3', 'a frequency ...

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03-01-2019 дата публикации

FREQUENCY DIVIDER CIRCUIT, DEMULTIPLEXER CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT

Номер: US20190007056A1
Автор: KANO Hideki, SAKAE Tatsuya
Принадлежит:

A frequency divider circuit includes: a first frequency dividing circuit configured to divide a first clock signal to generate a first frequency-divided clock signal; a second frequency dividing circuit configured to divide a second clock signal having the same frequency as the first clock signal and having a first phase difference with respect to the first clock signal to generate a second frequency-divided clock signal; a detection circuit configured to detect a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; and a selection circuit configured to select and output one of the second frequency-divided clock signal and an inverted signal of the second frequency-divided clock signal which are generated by the second frequency dividing circuit, based on the phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal detected by the detection circuit 1. A frequency divider circuit comprising:a first frequency dividing circuit configured to divide a first clock signal to generate a first frequency-divide clock signal;a second frequency dividing circuit configured to divide a second clock signal having the same frequency as the first clock signal and having a first phase difference with respect to the first clock signal to generate a second frequency-divided clock signal;a detection circuit configured to detect a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; anda first selection circuit configured to select and output one of the second frequency-divided clock signal and an inverted signal of the second frequency-divided clock signal which are generated by the second frequency dividing circuit, based on the phase relationship detected by the detection circuit.2. The frequency divider circuit according to claim 1 , whereinthe detection circuit is configured to detect whether the phase ...

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02-01-2020 дата публикации

TIME-TO-VOLTAGE CONVERTER WITH EXTENDED OUTPUT RANGE

Номер: US20200007138A1
Автор: Caffee Aaron J.
Принадлежит:

A time-to-voltage converter includes a switched-capacitor circuit configured to charge an output node to a reset voltage level in a first interval of a conversion period and configured to shift a voltage on the output node from the reset voltage level to a shifted reset voltage level in a second interval of the conversion period. The time-to-voltage converter includes a current source selectively coupled to the output node. The current source is configured to provide a constant current to the output node in a third interval of the conversion period. The shifted reset voltage level is outside a voltage range defined by a first power supply voltage level on a first voltage reference node and a second power supply voltage level on a second voltage reference node. 1. An apparatus comprising:a first voltage reference node;a second voltage reference node; and a switched-capacitor circuit configured to charge an output node to a reset voltage level in a first interval of a conversion period and configured to shift a voltage on the output node from the reset voltage level to a shifted reset voltage level in a second interval of the conversion period,', 'wherein the shifted reset voltage level is outside a voltage range of the voltage on the output node defined by a first power supply voltage level on the first voltage reference node and a second power supply voltage level on the second voltage reference node., 'a time-to-voltage converter comprising2. The apparatus claim 1 , as recited in claim 1 , wherein the second voltage reference node is a positive power supply node or a ground node claim 1 , the shifted reset voltage level is less than the second power supply voltage level if the second voltage reference node is a ground node claim 1 , and the shifted reset voltage level is greater than the second power supply voltage level if the second voltage reference node is the positive power supply node.3. The apparatus claim 1 , as recited in claim 1 , wherein the shifted ...

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08-01-2015 дата публикации

APPARATUSES AND METHODS FOR PHASE INTERPOLATING CLOCK SIGNALS AND FOR PROVIDING DUTY CYCLE CORRECTED CLOCK SIGNALS

Номер: US20150008968A1
Автор: Ma Yantao
Принадлежит:

Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes a first inverter configured to receive first and second clock signals and further includes a second inverter configured to receive the first and second clock signals. The first inverter is configured to provide to an output node an inverted first clock signal as controlled by the second clock signal. The second inverter is configured to provide to the output node an inverted second clock signal as controlled by the first clock signal. Another example apparatus includes a clock generator circuit to provide first and second clock signals responsive to an input clock signal, and further includes a duty phase interpolator circuit, a duty cycle adjuster and a duty cycle detector.

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11-01-2018 дата публикации

Clock jitter measurement circuit and semiconductor device including the same

Номер: US20180011142A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A circuit for measuring clock jitter includes: an internal signal generator configured to generate an internal clock signal and a single pulse signal, respectively synchronized with an input clock signal; a plurality of delay units being connected in series with each other and configured to generate respective delayed clock signals; a plurality of latch circuits configured to latch the single pulse signal in synchronization with the respective delayed clock signals, and output sampling signals; and a count sub-circuit configured to output a count value resulting from counting a number of active sampling signals of the sampling signals.

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12-01-2017 дата публикации

CLOCK SIGNAL GENERATION DEVICE AND MEMORY DEVICE INCLUDING THE SAME

Номер: US20170011806A1
Принадлежит:

A clock signal generation device includes a variable voltage providing circuit, a fixed voltage providing circuit and a clock signal generating circuit. The variable voltage providing circuit provides a variable reference voltage based on a selection signal, a reference voltage and a temperature coefficient. The variable reference voltage is varied according to temperature. The fixed voltage providing circuit provides a fixed reference voltage that is determined according to the selection signal. The fixed reference voltage is a constant voltage. The clock signal generating circuit provides a clock signal based on the fixed reference voltage and the variable reference voltage. The performance of the clock signal generation device may be increased by providing the clock signal based on the variable reference voltage that is varied according to the temperature and based on the fixed reference voltage. 1. A clock signal generation device comprising:a variable voltage providing circuit configured to provide a variable reference voltage based on a selection signal, a reference voltage and a temperature coefficient, the variable reference voltage being varied according to temperature;a fixed voltage providing circuit configured to provide a fixed reference voltage that is determined according to the selection signal, the fixed reference voltage being a constant voltage; anda clock signal generating circuit configured to provide a clock signal based on the fixed reference voltage and the variable reference voltage.2. The clock signal generation device of claim 1 , wherein the variable voltage providing circuit comprises:a voltage provider configured to provide a temperature-variable voltage and a temperature-fixed voltage, the temperature-variable voltage being varied according to the temperature, and the temperature-fixed voltage being fixed according to the temperature; anda voltage regulator configured to provide the variable reference voltage based on the temperature- ...

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12-01-2017 дата публикации

ADAPTIVE SLEW RATE CONTROL FOR SWITCHING POWER DEVICES

Номер: US20170012618A1
Автор: Krishna Kannan
Принадлежит:

An adaptive driver includes a gate driver having at least one driving transistor for driving a control node of switching transistor(s) that includes an output node (OUT) which provides Vout. An adjustable current source is in series with the driving transistor, a high pass filter (HPF) is between OUT and ground for detecting a slew rate of the switching transistor and outputting a voltage pulse (Vslp) output having a peak voltage amplitude at least monotonically reflecting a slope of Vout during switching. Detection signal processing circuitry is coupled to the output of the HPF for processing Vslp and slew rate control circuitry has an input coupled to the output of the detection signal processing circuitry. The output of the slew rate control circuitry is coupled to the current source for controlling its current level for changing the slew rate of the switching transistor to provide a desired slew rate range. 1. A driver with adaptive slew rate control (adaptive driver) , comprising:a gate driver including at least one driving transistor for driving a control node of at least one switching transistor within an output stage that includes an output node (OUT) which provides a voltage output (Vout);an adjustable current source in series with said driving transistor;a high pass filter (HPF) coupled between said OUT and a ground for detecting a slew rate of said switching transistor by outputting a voltage pulse (Vslp) at an output of said HPF having a peak voltage amplitude at least monotonically reflecting a slope of Vout during its switching transition;detection signal processing circuitry coupled to said output of said HPF for processing said Vslp and outputting a processed detection signal;slew rate control circuitry having an input coupled to said output of said detection signal processing circuitry for receiving said processed detection signal, wherein an output of said slew rate control circuitry is coupled to said adjustable current source for controlling a ...

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14-01-2016 дата публикации

DUTY CYCLE CORRECTION CIRCUIT AND SEMICONDUCTOR DEVICE

Номер: US20160013785A1
Автор: Nakata Masashi
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to one embodiment, there is provided a duty cycle correction circuit including an input inverter, an output inverter, a charge distribution unit, and a drawing-off unit. The input inverter includes a PMOS transistor and an NMOS transistor and receives a clock signal. The output inverter outputs a clock signal according to a signal transmitted via a signal line from the input inverter. The charge distribution unit distributes, when one transistor of the PMOS transistor and the NMOS transistor is turned on, charge to capacitance elements selected from among one or more first capacitance elements placed on side of the signal line and among a plurality of second capacitance elements disposed on side of source of the one transistor. The drawing-off unit draws off the distributed charge from the selected capacitance elements while the one transistor is maintained to be on. 1. A duty cycle correction circuit comprising:an input inverter that includes a PMOS transistor and an NMOS transistor and receives a clock signal;an output inverter that outputs a clock signal according to a signal transmitted via a signal line from the input inverter;a charge distribution unit that distributes, when one transistor of the PMOS transistor and the NMOS transistor is turned on, charge to capacitance elements selected from among one or more first capacitance elements placed on side of the signal line and among a plurality of second capacitance elements disposed on side of source of the one transistor; anda drawing-off unit that draws off the distributed charge from the selected capacitance elements while the one transistor is maintained to be on.2. The duty cycle correction circuit according to claim 1 , wherein the charge distribution unit has:a plurality of the first capacitance elements disposed on the side of the signal line;a first selecting unit that selects first capacitance elements to be used for duty cycle adjustment from among the plurality of first capacitance ...

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14-01-2021 дата публикации

Frequency Multiplier, Digital Phase-Locked Loop Circuit, and Frequency Multiplication Method

Номер: US20210013892A1
Автор: PENG Gao
Принадлежит: Huawei Technologies Co Ltd

A frequency multiplier, a digital phase-locked loop circuit, and a frequency multiplication method, where the frequency multiplier includes a clock controller configured to: receive an output signal from a time-to-digital converter in the digital phase-locked loop circuit, and generate a control signal based on a duty cycle error of the output signal, a clock calibration circuit configured to: receive a reference clock signal, calibrate a duty cycle of the reference clock signal based on the control signal, and output a calibrated clock signal, and a clock frequency multiplier configured to: receive the calibrated clock signal, multiply a frequency of the calibrated clock signal, and output a frequency multiplied signal to the time-to-digital converter.

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19-01-2017 дата публикации

SIGNAL GENERATOR ADJUSTING A DUTY CYCLE AND SEMICONDUCTOR APPARATUS USING THE SAME

Номер: US20170019091A1
Автор: SHON Kwan Su
Принадлежит:

A semiconductor apparatus may include a signal generator, and may operate by receiving two or more external power voltages. The signal generator may include a duty cycle circuit. The duty cycle circuit may include a duty control circuit and a duty cycle adjustment circuit. The duty cycle adjustment circuit may be configured to compensate a duty change of an output signal when a power voltage domain changes. 1. A signal generator comprising:a first buffer configured to amplify an input signal to a level of a first power voltage and generate a first output signal;a second buffer configured to amplify the first output signal to a level of a second power voltage and generate a second output signal;a duty control circuit configured to generate a duty control signal by comparing the levels of the first power voltage and the second power voltage; anda duty cycle adjustment circuit configured to change a voltage level of the first output signal based on the input signal and the duty control signal.2. The signal generator of claim 1 , wherein the first buffer generates the first output signal having a voltage level between the first power voltage and a first ground voltage based on the input signal.3. The signal generator of claim 2 , wherein the second buffer generates the second output signal having a voltage level between the second power voltage and a second ground voltage based on the input signal.4. The signal generator of claim 3 , wherein the first ground voltage has substantially the same level as the second ground voltage.5. The signal generator of claim 1 ,wherein the duty control signal includes a duty up signal and a duty down signal, andwherein the duty control circuit generates the duty up signal when the level of the first power voltage is higher than the level of the second power voltage, and generates the duty down signal when the level of the first power voltage is lower than the level of the second power voltage.6. The signal generator of claim 1 , ...

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17-04-2014 дата публикации

DUTY CYCLE PROTECTION CIRCUIT

Номер: US20140103972A1
Принадлежит:

A duty cycle protection circuit including a first synchronous device adapted to receive a first clock signal on an input line and to generate a first clock transition of a second clock signal in response to a first clock transition of the first clock signal; and reset circuitry coupled to the input line and adapted to generate a second clock transition of the second clock signal by resetting the first synchronous device a time delay after the first clock transition of the first clock signal. 1. A duty cycle protection circuit comprising:a first synchronous device adapted to receive a first clock signal on an input line and to generate a first clock transition of a second clock signal in response to a first clock transition of said first clock signal; andreset circuitry coupled to said input line and adapted to generate a second clock transition of said second clock signal by resetting said first synchronous device a time delay after said first clock transition of said first clock signal.2. The duty cycle protection circuit of claim 1 , wherein said reset circuitry comprises pulse generation circuitry adapted to generate a pulse for resetting said first synchronous device based on said first clock transition of said first clock signal.3. The duty cycle protection circuit of claim 2 , wherein said reset circuitry comprises a NAND gate having a first input coupled to an input node of the reset circuitry and a second input coupled to the input node of the reset circuitry via an inverter claim 2 , said NAND gate generating said pulse for resetting said first synchronous device.4. The duty cycle protection circuit of claim 1 , wherein said reset circuitry comprises a delay element adapted to provide a delayed version of said first clock signal.5. The duty cycle protection circuit of claim 1 , wherein said reset circuitry is coupled to said input line via said first synchronous device or via a second synchronous device.6. The duty cycle protection circuit of claim 1 , ...

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17-04-2014 дата публикации

COUNTING CIRCUIT OF SEMICONDUCTOR DEVICE AND DUTY CORRECTION CIRCUIT OF SEMICONDUCTOR DEVICE USING THE SAME

Номер: US20140103981A1
Автор: Choi Hae-Rang, Kim Yong-Ju
Принадлежит: SK HYNIX INC.

A counting circuit of a semiconductor device includes a plurality of counting units configured to count respective bits of counting codes in response to a plurality of counting clocks, respectively, and to control in a counting direction in response to a counting control signal; a clock toggling control unit configured to control the number of counting clocks that toggle among the plurality of counting clocks in response to clock control signals; and a counting operation control unit configured to compare a value of target codes and a value of the counting codes, and to determine a value of the counting control signal according to a comparison result. 115-. (canceled)16. A duty correction circuit of a semiconductor device , comprising:a duty cycle error detection unit configured to detect a duty cycle error of a source clock;a plurality of counting units configured to count respective bits of duty correction codes in response to a plurality of counting clocks, respectively, and a counting direction of the plurality of counting units is controlled in response to an output signal of the duty cycle error detection unit;a clock toggling control unit configured to control the number of counting clocks that toggle among the plurality of counting clocks in response to clock control signals; anda duty cycle control unit configured to control a duty cycle of the source clock in response to the duty correction codes.17. The duty correction circuit of claim 16 , wherein the plurality of counting units respectively count the plurality of bits included in the duty correction codes in one-to-one correspondence to toggling of the plurality of counting clocks.18. The duty correction circuit of claim 17 , wherein the plurality of counting units respectively perform counting operations by combining carry information between adjoining units.19. The duty correction circuit of claim 16 ,wherein the clock toggling control unit determines the number of counting clocks to toggle in an ...

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03-02-2022 дата публикации

ELECTRONIC CURRENT-SWITCHING SYSTEM PROVIDED WITH A REDUNDANT CONTROL SOLUTION

Номер: US20220038096A1
Автор: LINK Benoît
Принадлежит: SAFRAN ELECTRICAL & POWER

An electronic current-switching system comprising a driver unit and a current-switching device with one controlled transistor, a control unit coupled to said transistor, a power supply unit of the control unit and a digital communication bus transmitting to the control unit a first control signal of the driver unit. The power supply unit comprises: a transformer, an integrated circuit including a clock input coupled to a second output of the driver unit delivering a second control signal having the form of a pulsed signal with an adjustable duty cycle, and an output delivering to the transformer a primary voltage signal dependent on the second control signal, and a voltage divider bridge measuring the frequency-domain signal delivered by the transformer. 2. The electronic current-switching system as claimed in claim 1 , wherein the driver unit comprises a computing unit configured to formulate a command of the electronic current-switching device claim 1 , and a first control signal and a second control signal on the basis of said formulated command claim 1 , the computing unit of the driver unit comprising:a first output delivering the first control signal to the electronic control unit, via the first output of the driver unit, the communication bus and the communication unit, anda second output delivering the second control signal to the electronic control unit via the second output of the driver unit and the power supply unites, the second control signal having the form of a pulsed signal with an adjustable duty cycle.3. The electronic current-switching system as claimed in claim 1 , wherein said at least one controlled transistor of the electronic current-switching device is an insulated-gate field effect transistor.4. The electronic current-switching system as claimed in claim 1 , wherein the electronic control unit of the electronic current-switching device is a microcontroller.5. The electronic current-switching system as claimed in claim 1 , wherein the ...

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18-01-2018 дата публикации

DRIVER CIRCUIT ABLE TO MONITOR USAGE OF A SURGE PROTECTION ARRANGEMENT

Номер: US20180019588A1
Автор: Chen Hong, CHEN HONGXIN
Принадлежит: PHILIPS LIGHTING HOLDING B.V.

A driver circuit comprises a mains input and a switch mode power converter for delivering an output derived from the mains input by switching using a pulse width modulation signal. The switch mode power converter comprises a pulse width controller for controlling the pulse width of the pulse width modulation signal. A monitor is used for monitoring the pulse width of the pulse width modulation signal and for detecting a surge event from the pulse width, wherein the monitor is for detecting the surge event from changes in the pulse width and/or duty cycle over time, and comprises a monitor circuit for detecting a surge event based on the pulse width and/or duty cycle reducing to correspond to a first pulse from a second pulse, remaining at the first pulse for a time period falling within a first threshold range and then returning to the second pulse, wherein the width of the first pulse is narrower than the second pulse. 1. A driver circuit comprising:a mains input;a switch mode power converter for delivering an output derived from the mains input by switching using a pulse width modulation signal, wherein the switch mode power converter comprises a pulse width controller for controlling the pulse width and/or duty cycle of the pulse width modulation signal; anda monitor for monitoring the pulse width and/or duty cycle of the pulse width modulation signal and for detecting a surge event from the pulse width and/or duty cycle, wherein the monitor is for detecting the surge event from changes in the pulse width and/or duty cycle over time, and comprises a monitor circuit for detecting a surge event based on:a second pulse width changing to a first pulse width, remaining at the first pulse width for a time period falling within a first threshold range and then returning to the second pulse width, wherein the first pulse width is narrower than the second pulse width; ora second duty cycle changing to a first duty cycle, remaining at the first duty cycle for a time period ...

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18-01-2018 дата публикации

SIGNAL PROCESSING APPARATUS AND METHOD

Номер: US20180019707A1
Автор: Matsumoto Tomohiro
Принадлежит:

The present technology relates to a signal processing apparatus and method capable of increasing a harmonic rejection ratio while suppressing an increase in power consumption. 1. A signal processing apparatus , comprisinga mixing section that has a differential configuration, mixes two local signals with each signal of a differential signal, and calculates a difference between results of the mixing of the two local signals, the two local signals having a 1/3 duty ratio and phases mutually shifted by a 1/2 period.2. The signal processing apparatus according to claim 1 , further comprisinga resonance section that resonates with the differential signal, with which the local signals are mixed by the mixing section, at a predetermined resonant frequency.3. The signal processing apparatus according to claim 2 , whereinthe resonance section resonates at a sixfold frequency of a frequency of the local signals.4. The signal processing apparatus according to claim 2 , whereinthe resonance section includes a parallel LC circuit.5. The signal processing apparatus according to claim 2 , whereinthe resonant frequency is variable.6. The signal processing apparatus according to claim 2 , further comprisinga voltage/current conversion section that converts a voltage into a current with respect to the differential signal, whereinthe mixing section mixes the local signals with the differential signal output from the voltage/current conversion section.7. The signal processing apparatus according to claim 6 , further comprisinga capacitor between an output of the voltage/current conversion section and a ground potential.8. The signal processing apparatus according to claim 1 , further comprisinga differential amplification section that amplifies the differential signal, with which the local signals are mixed by the mixing section.9. The signal processing apparatus according to claim 1 , whereinthe mixing section includes a path of an I channel and a path of a Q channel and mixes the ...

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22-01-2015 дата публикации

SWITCHING POWER SUPPLY DEVICE AND PULSE WIDTH MODULATION CIRCUIT USED THEREIN

Номер: US20150022165A1
Автор: Sato Terukazu
Принадлежит:

A problem of the present invention is to provide a switching power supply device and a pulse width modulation circuit capable of operating stably in synchronization with a clock signal. To solve the problem, a pulse width modulation circuit A in a switching power supply device A includes square-wave voltage output means A for, when an integrated voltage Vrises to an upper threshold voltage or more, shifting a square-wave voltage Vto L level, or when the voltage Vdrops to a lower threshold voltage or less, shifting the voltage Vto H level, and clock means A for outputting a first clock signal Vand a second clock signal V, which are 180° out of phase from each other. The square-wave voltage output means A is adapted to: (1) if the clock signal Vchanges while the voltage Vis dropping, shift the voltage Vto H level even when the voltage Vhas not yet reached the lower threshold voltage; and (2) if the clock signal Vchanges while the voltage Vis rising, shift the voltage Vto L level even when the voltage Vhas not yet reached the upper threshold voltage. 1. A pulse width modulation circuit for generating a square-wave voltage taking two states at L and H levels to drive switching elements included in a converter portion , the circuit comprising:square-wave voltage output means for shifting the square-wave voltage to L level when an integrated voltage obtained by integrating the square-wave voltage rises to an upper threshold voltage or more, or shifting the square-wave voltage to H level when the integrated voltage falls to a lower threshold voltage or less; andclock means for outputting a first clock signal and a second clock signal to the square-wave voltage output means, the first clock signal and the second clock signal being 180° out of phase from each other, wherein,the square-wave voltage output means is adapted to: (1) when the first clock signal changes while the integrated voltage is dropping, shift the square-wave voltage to H level even if the integrated ...

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16-01-2020 дата публикации

METHODS AND SYSTEMS OF PEAK PRIMARY CURRENT CONTROL ON THE SECONDARY SIDE

Номер: US20200021197A1
Автор: HARI Ajay Karthik

Peak primary current control on the secondary side. In a power converter having a primary side and a secondary side separated by a main transformer, example methods include: driving primary current through a primary winding of the main transformer; creating, on the secondary side of the main transformer, a signal indicative of current through the primary winding of the main transformer; and ceasing the driving of primary current through the primary winding when the signal indicative of primary current reaches a predetermined value. 1. A method comprising:driving primary current through a primary winding of a main transformer of a power converter;creating, on a secondary side of the main transformer, a signal proportional to primary current; andceasing the driving of primary current through the primary winding when the signal proportional to primary current reaches a predetermined value.2. The method of wherein driving the primary current further comprises:sending, from the secondary side to a primary side, an asserted control signal; andmaking a main switch on the primary side conductive responsive to the asserted control signal.3. The method of wherein ceasing the driving of the primary current further comprises:sending, from the secondary side to the primary side, a de-asserted control signal; andmaking the main switch on the primary side non-conductive responsive to the de-asserted control signal.4. The method of wherein sending the asserted control signal further comprises sending through a system that provides galvanic isolation between the primary side and the secondary side.5. The method of wherein sending through the system that provides galvanic isolation further comprises at least one selected from the group comprising: sending through a gate-drive transformer distinct from the main transformer; sending through an optocoupler; and sending through the main transformer.6. The method of wherein creating claim 1 , on the secondary side of the main transformer ...

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16-01-2020 дата публикации

CRYSTAL OSCILLATOR AND REFERENCE CLOCK GENERATOR INCLUDING SAME

Номер: US20200021245A1
Принадлежит:

A crystal oscillator including a feedback circuit, and a reference clock generating circuit including the crystal oscillator. The crystal oscillator is configured to generate an oscillating signal based on a natural frequency of a crystal. The crystal oscillator may include: a current generating circuit connected to a first node having a first voltage and a second node having a second voltage, and configured to output a first current to the second node; a feedback circuit connected to the generating circuit via the first and second nodes and configured to adjust a level of the second voltage by controlling a level of the first voltage; and a crystal circuit connected to the second node and configured to generate the oscillating signal based on the second voltage. 1. A crystal oscillator configured to generate an oscillating signal based on a natural frequency of a crystal , the crystal oscillator comprising:a current generating circuit connected to a first node having a first voltage and a second node having a second voltage, the current generating circuit being configured to output a first current to the second node;a feedback circuit connected to the current generating circuit via the first node and the second node and configured to adjust a level of the second voltage by controlling a level of the first voltage; anda crystal circuit connected to the second node and configured to generate the oscillating signal based on the second voltage.2. The crystal oscillator of claim 1 , whereinthe feedback circuit comprises an operational amplifier (OPAMP) comprising an output terminal connected to the first node, a first input terminal connected to the second node, and a second input terminal connected to a third node,a third voltage is applied to the third node, andthe OPAMP, by controlling the first voltage of the first node, adjusts the level of the second voltage to be approximately equal to a level of the third voltage.3. The crystal oscillator of claim 2 , further ...

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16-01-2020 дата публикации

SIGNAL TRANSMISSION DEVICE AND DRIVE DEVICE

Номер: US20200021293A1
Автор: ARARAGI Akifumi
Принадлежит: Denso Corporation

In a signal transmission device having a pulse generator, a RS F/F circuit and a detector, the generator generates a set pulse signal and/or a reset pulse signal when a state of a PWM signal is changed. After the generation of the set pulse signal, the generator continuously generates following pulse signals after elapse of a predetermined period of time counted from the generation of the set pulse signal. The generator adjusts, based on a selector signal, the predetermined period of time counted to a time when the following pulse signal is transmitted at a first time. The detector detects the state of the selector signal based on the predetermined period of time counted from a time when the RS F/F circuit receives the set pulse signal or the reset pulse signal to a time when receiving the following pulse signal at a first time. 1. A signal transmission device comprising a pulse generator , an output circuit and a detector , whereinthe pulse generator comprises a first output terminal and a second output terminal, the pulse generator receives a first signal which has either a High voltage level or a Low voltage level, the pulse generator generates a set pulse signal based on a voltage level change of the first signal from the High voltage level to the Low voltage level, and transmits the set pulse signal through the first output terminal, and the pulse generator generates a reset pulse signal based on the voltage level change of the first signal from the Low voltage level to the High voltage level and transmits the reset pulse signal through the second output terminal,the output circuit comprises a first input terminal, a second input terminal and a third output terminal,the output circuit transmits a first output signal, which corresponds to the High voltage level of the first signal, through the third output terminal when the first input terminal receives the set pulse signal transmitted from the pulse generator, andthe output circuit transmits a second output ...

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28-01-2016 дата публикации

SIGNAL PROCESSING

Номер: US20160028380A1
Автор: Townsend Kevin
Принадлежит:

A method of processing an amplitude-modulated analogue signal at a carrier frequency Fcomprises: digitising the analogue signal to produce an input bit stream that represents the amplitude of the analogue signal; generating an in-phase reference bit stream that is synchronous to the carrier frequency Fand represents an in-phase digital reference signal substantially in the form of a sine and/or cosine wave; and multiplying the input bit stream with the in-phase reference bit stream to produce an output bit stream representing the amplitude modulation of the analogue signal. 1. A method of processing an amplitude-modulated analogue signal at a carrier frequency F , comprising:digitising the analogue signal to produce an input bit stream that represents the amplitude of the analogue signal;{'sub': 'c', 'generating an in-phase reference bit stream that is synchronous to the carrier frequency Fand represents an in-phase digital reference signal substantially in the form of a sine and/or cosine wave; and'}multiplying the input bit stream with the in-phase reference bit stream to produce an output bit stream representing the amplitude modulation of the analogue signal.2. The method of claim 1 , comprising digitising the analogue signal at a sampling rate R that is synchronous to the carrier frequency Faccording to R=2*(1*3*5 . . . N)*For R=4*(1*3*5 . . . N)*F claim 1 , where N>1 is an odd number representing odd harmonics in the analogue signal.3. The method of claim 1 , comprising digitising the analogue signal at a sampling rate R=4*3*F=12F claim 1 , or R=4*3*5*F=60F.4. The method of claim 1 , wherein digitising the analogue signal is performed using pulse-density modulation (PDM) or pulse-width modulation (PWM).5. The method of claim 1 , wherein digitising the analogue signal comprises carrying out delta-sigma modulation to produce a one-bit input bit stream.6. The method of claim 1 , wherein digitising the analogue signal is performed using pulse-code modulation (PCM ...

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24-01-2019 дата публикации

Duty Cycle Detection

Номер: US20190028090A1
Принадлежит: Invecas Inc

A pulse-width-to-voltage (“PWV”) converter, comprises: a switch, a capacitor, a current source, and a current sink. The switch is operable by a signal. The current source, the current sink, and the switch are serially connected across a high voltage potential and a low voltage potential. An output node is coupled to a serial connection between the current source and the current sink. An end of the capacitor is coupled to the output node for converting a current into a control voltage indicative of a duty cycle of the signal.

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24-01-2019 дата публикации

PHASE INTERPOLATOR, TIMING GENERATOR, AND SEMICONDUCTOR INTEGRATED CIRCUIT

Номер: US20190028093A1
Автор: TSUJI Masanobu
Принадлежит:

During a period in which a first signal Sand second signal Sare both set to a first level, an initializing circuit initializes a capacitor voltage. Multiple circuit units are coupled in parallel between an intermediate line and a second line. An output circuit generates an output signal Sour that changes level when the capacitor voltage crosses a predetermined threshold value V. Each circuit unit includes a resistor Rand first path arranged in series between the intermediate and second lines and a second path parallel to the first path. The first path is configured to turn on when the first signal Sis the second level and the corresponding bit of an input code is a first value. The second path is configured to turn on when the second signal Sis the second level and the corresponding bit of the input code is a second value. 1. A phase interpolator comprising:a first input node couled to receive a first signal that transits from a first level to a second level;a second input node coupled to receive a second signal that transits from the first level to the second level with a delay with respect to the first signal;a first line coupled to receive a first voltage;a second line coupled to receive a second voltage;an intermediate line;a capacitor having one end coupled to the intermediate line;an initializing circuit structured to initialize a voltage across the capacitor during a period in which the first signal and the second signal are both set to the first level;a plurality of circuit units that correspond to a plurality of bits of an input code, and coupled in parallel between the intermediate line and the second line; andan output circuit structured to generate an output signal having a level that changes when the voltage across the capacitor crosses a predetermined threshold value, a resistor and a first path arranged in series between the intermediate line and the second line; and', 'a second path arranged in parallel with the first path,, 'wherein each circuit ...

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28-01-2021 дата публикации

APPARATUSES AND METHODS FOR SETTING A DUTY CYCLE ADJUSTER FOR IMPROVING CLOCK DUTY CYCLE

Номер: US20210027819A1
Автор: Kim Kang-Yong
Принадлежит: MICRON TECHNOLOGY, INC.

Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset. 1. A method , comprising:issuing commands to a memory to perform a first duty cycle monitor sequence to determine a first duty cycle result;changing a duty cycle adjuster code of the memory to decrease the duty cycle adjuster code to decrease a high duty cycle based on the first duty cycle result;issuing commands to a memory to perform a second duty cycle monitor sequence to determine a second duty cycle result; andchanging the duty cycle adjuster code of the memory to increase the duty cycle adjuster code to increase the high duty cycle based on the second duty cycle result, wherein a magnitude of the increase is different than a magnitude of the decrease.2. The method of claim 1 , wherein the first duty cycle result comprises: a first result from a first duty cycle input flip condition; anda second result from a second duty cycle input flip condition that is different than the first duty cycle input flip condition.3. The method of claim 1 , wherein the first duty cycle result indicates a first high duty cycle greater than 50% and the second duty cycle result indicates a second high duty cycle less than 50%.4. The method of claim 1 , further comprising issuing commands to the memory to perform a third duty cycle monitor sequence to determine a third duty cycle result.5. The method of claim 4 , wherein issuing commands to the memory to perform the third duty cycle monitor sequence is ...

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28-01-2021 дата публикации

Apparatus and Method of Generating a Waveform

Номер: US20210027990A1
Принадлежит:

Some embodiments include a high voltage waveform generator comprising: a generator inductor; a high voltage nanosecond pulser having one or more solid state switches electrically and/or inductively coupled with the generator inductor, the high voltage nanosecond pulser configured to produce a pulse burst having a burst period, the pulse burst comprising a plurality of pulses having different pulse widths; and a load electrically and/or inductively coupled with the high voltage nanosecond pulser, the generator inductor, and the generator capacitor, the voltage across the load having an output pulse with a pulse width substantially equal to the burst period and the voltage across the load varying in a manner that is substantially proportional with the pulse widths of the plurality of pulses. 1. A high voltage waveform generator comprising:a generator inductor; a first pulse burst comprising a first plurality of high voltage pulses, each pulse of the first plurality of pulses having a pulse width, the first pulse burst having a first burst period; and', 'a second pulse burst comprising a second plurality of high voltage pulses, each pulse of the second plurality of pulses having a pulse width, the second pulse burst having a second burst period; and, 'a high voltage nanosecond pulser electrically and/or inductively coupled with the generator inductor, the high voltage nanosecond pulser configured to charge the generator inductor with a first plasma pulse having a first output pulse width and a first output voltage, the first output pulse width being substantially equal to the first burst period and the first output voltage being substantially proportional to a pulse width of each of the pulses of the first plurality of pulses, and', 'a second plasma pulse having a second output pulse width and a second output voltage, the second output pulse width being substantially equal to the second burst period and the second output voltage being substantially proportional to a ...

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23-01-2020 дата публикации

GATE DRIVER POWER SUPPLY

Номер: US20200028497A1
Автор: Carvell Paul
Принадлежит: BAE SYSTEMS CONTROLS INC.

A power supply for a gate driver circuit is provided. The power supply is configured to supply a logic voltage, a positive voltage and a negative voltage to the gate driver circuit such that a gated semiconductor driven by the gate driver circuit does not inadvertently turn on. The gate driver power supply is configured such that the logic voltage becomes a steady-state voltage prior to the positive voltage becoming a steady-state voltage and remains above a first voltage value until the positive voltage is less than a second voltage value. 1. A gate driver power supply for outputting a positive voltage , a negative voltage and a logic voltage , the gate driver power supply comprising:a power source coupled to a primary winding of a transformer via at least two complementary switches;a full bridge rectifier coupled to a secondary winding of the transformer;a first shunt regulating circuit coupled to a logic supply line and the full bridge rectifier;a series linear regulating circuit coupled to the logic supply line, the first shunt regulating circuit and the full bridge rectifier, the first shunt regulating circuit and the series linear regulating circuit regulating the logic voltage on the logic supply line;a second shunt regulating circuit coupled to the full bridge rectifier, a ground and a positive voltage line; anda diode having a first terminal coupled to the logic supply line and a second terminal coupled to a negative supply line.2. The gate driver power supply of claim 1 ,wherein the series linear regulating circuit comprises a transistor, a first resistive divider and a MOSFET or a bipolar junction transistor (BJT), the base of the transistor is coupled to the logic supply line, the collector of the transistor is coupled to the gate of the MOSFET or base of the BJT, andwherein the source of the MOSFET or the emitter of the BJT is coupled to the logic supply line.3. The gate driver power supply of claim 2 , further comprising a first capacitor coupled to ...

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02-02-2017 дата публикации

FIELD REGULATOR

Номер: US20170032878A1
Принадлежит:

The invention generally relates to a field regulator, particularly a field regulator for a resonant circuit, a transmitter including such a field regulator, a proximity detection system including such a transmitter, and a method of regulating a resonant circuit. In one aspect the invention provides a field regulator for a resonant circuit, the resonant circuit including an inductor coil around a core, the field regulator including a DC bias circuit configured to apply a DC bias current to the inductor coil for regulating an electromagnetic field generated by the inductor. The DC bias circuit can be used to selectively change the inductance of the inductor in the resonant circuit so as to maintain a consistent field strength in a changing environment, particularly to take into account the presence of large metal bodies which might otherwise adversely impact on operation. In particular, the DC bias current may be used to selectively change the natural frequency of the resonant circuit so as to shift the resonant circuit towards a desired resonance point. 1. A field regulator for a resonant circuit , the resonant circuit including an inductor coil around a core , the field regulator including a DC bias circuit configured to apply a DC bias current to the inductor coil for regulating an electromagnetic field generated by the inductor.2. The field regulator of claim 1 , including a feedback control system in which the level of the applied DC bias current is determined based on a current measured in the resonant circuit.3. The field regulator of including:a current detector for detecting a current flow of the resonant circuit; anda bias current controller for controlling the DC bias current based on the detected current flow of the resonant circuit.4. The field regulator of claim 3 , configured to adjust the DC bias current based on a resonant circuit response to an incremental change in the DC bias current.5. The field regulator of claim 4 , wherein the bias current ...

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01-05-2014 дата публикации

DUTY CYCLE TUNING CIRCUIT AND METHOD THEREOF

Номер: US20140118044A1
Автор: Liu Ye
Принадлежит: Realtek Semiconductor Corp.

A duty cycle tuning circuit and a method thereof are provided, in which the duty cycle tuning circuit includes multiple interpolation circuits, an edge detection circuit, and a delay chain. Each interpolation circuit receives multiple phase clocks, and interpolates an interpolation clock from two of the phase clocks. The phase clocks have the same frequency but different phases. The edge detection circuit is connected electrically to the delay chain, and generates an output clock according to an edge of the interpolation clock. 1. A duty cycle tuning circuit , comprising:a plurality of interpolation circuits, each for receiving a plurality of phase clocks, and interpolating an interpolation clock from two of the phase clocks, wherein the phase clocks have the same frequency but different phases;an edge detection circuit, for generating an output clock according to an edge of the interpolation clocks; anda delay chain, connected electrically to the edge detection circuit.2. The duty cycle tuning circuit according to claim 1 , wherein each interpolation circuit comprises:a selection unit, for selecting two phase signals from the phase clocks according to a control signal; anda phase interpolator, for interpolating the interpolation clock by using the two selected phase clocks.3. The duty cycle tuning circuit according to claim 2 , wherein the phases of the two selected phase clocks are adjacent.4. The duty cycle tuning circuit according to claim l claim 2 , wherein the edge detection circuit comprises:a plurality of logic circuits, corresponding to the interpolation circuits, respectively, for detecting one of a rising edge and a falling edge of the corresponding interpolation clock, respectively; anda latch, for generating the output clock based on output of the logic circuits5. The duty cycle tuning circuit according to claim 4 , wherein the delay chain is connected electrically to an output end of the latch claim 4 , to delay the output clock.6. The duty cycle ...

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01-05-2014 дата публикации

APPARATUS FOR CONTROLLING DUTY RATIO OF SIGNAL

Номер: US20140118045A1

Disclosed is an apparatus for controlling a duty ratio of a signal that includes a clock control unit configured to generate a plurality of control signals based on an input signal, a half-cycle generation unit configured to generate a multiplied signal by use of the input signal and a delay signal that is obtained by delaying the input signal based on a delay control voltage, and divide the multiplied signal to generate a first division signal and a second division signal that are in inverse relation to each other, a comparator unit configured to compare a pulse width of the first division signal with a pulse width of the second division signal based on the control signal provided by the clock control unit, and output a delay control signal corresponding to a result of the comparison, and a control voltage generation unit configured to output a delay control voltage. 1. An apparatus for controlling a duty ratio , the apparatus comprising:a clock control unit configured to generate a plurality of control signals for controlling a duty ratio based on an input signal;a half-cycle generation unit configured to generate a multiplied signal by use of the input signal and a delay signal that is obtained by delaying the input signal based on a delay control voltage, and divide the multiplied signal to generate a first division signal and a second division signal that are in inverse relation to each other;a comparator unit configured to compare a pulse width of the first division signal with a pulse width of the second division signal based on the control signal provided by the clock control unit, and output a delay control signal corresponding to a result of the comparison; anda control voltage generation unit configured to output a delay control voltage corresponding to the delay control signal.2. The apparatus of claim 1 , wherein the half-cycle generation unit comprises:a delay element configured to output the delay signal by adjusting a delay time of the input signal ...

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05-02-2015 дата публикации

CLOCK DOUBLER INCLUDING DUTY CYCLE CORRECTION

Номер: US20150035570A1
Автор: Hinrichs Jeffrey Mark
Принадлежит: QUALCOMM INCORPORATED

Exemplary embodiments are related to a clock doubler. A device may include a duty cycle correction circuit configured to receive an input clock signal and convey a corrected clock signal. The duty cycle correction circuit may include a first circuit to convey an output voltage during a first cycle of the input clock signal and correct a current mismatch of the first circuit during a second cycle of the input clock signal. The duty cycle correction circuit may also include a second circuit to convey the output voltage during the second cycle and correct a current mismatch of the second circuit during the first cycle. Further, the device may include a clock generator for receiving the corrected clock signal and generating an output clock. 1. A device , comprising: a first circuit to convey an output voltage during a first cycle of the input clock signal and correct a current mismatch of the first circuit during a second cycle of the input clock signal; and', 'a second circuit to convey the output voltage during the second cycle and correct a current mismatch of the second circuit during the first cycle; and, 'a duty cycle correction circuit configured to receive an input clock signal and convey a corrected clock signal, the duty cycle correction circuit includinga clock generator for receiving the corrected clock signal and generating an output clock.2. The device of claim 1 , further comprising an output capacitor configured to receive the output voltage during each of the first and second cycles.3. The device of claim 1 , the output clock having a duty cycle of substantially 50% and a frequency that is increased relative to a frequency of the corrected clock signal.4. The device of claim 1 , the first circuit including a differential pair of transistors for comparing a reference voltage to a voltage across a capacitor configured to receive a first and second current during the second cycle.5. The device of claim 4 , further comprising a feedback loop for correcting ...

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17-02-2022 дата публикации

CONTROL OF PRINTER HEATING ELEMENTS BASED ON INPUT VOLTAGES

Номер: US20220050413A1

An apparatus may include a power connection to receive an input power and a volt meter coupled to the power connection. The volt meter may be to measure an input voltage of the input power. A controller may be coupled to a heating element and the volt meter. The controller may control the heating element based on the input voltage measured by the volt meter. 1. An apparatus comprising:a power connection to receive an input power;a volt meter coupled to the power connection, the volt meter to measure an input voltage of the input power;a heating element to heat a printer; anda controller coupled to the volt meter and the heating element, wherein the controller is to control the heating element based on the input voltage.2. The apparatus of comprising:a switch to couple the heating element to the power connection; anda pulse width modulator to provide a drive signal to the switch, the drive signal to control a state of the switch, wherein the control of the heating element by the controller includes control of the pulse width modulator.3. The apparatus of claim 2 , wherein the controller is to determine whether the input voltage is greater than a predetermined voltage value claim 2 , the control of the pulse width modulator includes application of a pulse width scaling factor to adjust a maximum pulse width of the drive signal when the input voltage is greater than the predetermined voltage value claim 2 , and wherein the pulse width scaling factor is based on the input voltage.4. The apparatus of claim 1 , wherein claim 1 , to control the heating element claim 1 , the controller is to limit a current draw of the heating element.5. The apparatus of comprising a temperature sensor to measure a temperature claim 1 , wherein the control of the heating element is based on the temperature.6. An apparatus comprising:a volt meter to measure an input voltage of an input power;a heating element to generate heat; anda pulse width modulator coupled to the heating element, the ...

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02-02-2017 дата публикации

OFFSET INSENSITIVE QUADRATURE CLOCK ERROR CORRECTION AND DUTY CYCLE CALIBRATION FOR HIGH-SPEED CLOCKING

Номер: US20170033774A1
Автор: Frans Yohan, Hedayati Hiva
Принадлежит: XILINX, INC.

Techniques for correcting clock distortion. The techniques include use of circuitry for detecting and correcting duty cycle distortion and quadrature clock phase distortion. For phase detection, detection circuitry is made simpler and more accurate through the use of a sampling operation in which device mismatch within detection circuitry is accounted for by sampling charge associated with an ideal clock signal across sampling capacitors. When phase detection is performed with the detection circuitry, the stored charge compensates for the device mismatch, improving the accuracy of the detection circuit. The sampling operation is used for duty cycle distortion detection as well. Specifically, a common mode voltage is applied to sampling capacitors, which effectively zeroes the voltage differential between the sampling capacitors, compensating for offset that might exist due to operation of other components of the detection circuit. A digital value is used by a feedback algorithm to correct the clock distortion. 1. A distortion detection unit for detecting distortion of a clock signal , comprising:a duty cycle distortion detection unit;a quadrature clock error detection unit; andone or more sampling capacitors coupled to the duty cycle distortion detection unit and the quadrature clock error detection unit,wherein the duty cycle distortion detection unit and the quadrature clock error detection unit are operable to provide device mismatch-related voltages to the one or more sampling capacitors to charge the one or more sampling capacitors for mismatch correction,wherein the duty cycle distortion detection unit is operable to output a first differential value via the one or more sampling capacitors to indicate a duty cycle distortion polarity of the clock signal, andwherein the quadrature clock error detection unit is operable to output a second differential value via the one or more sampling capacitors to indicate a quadrature clock error polarity of the clock signal. ...

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02-02-2017 дата публикации

PULSE WIDTH WIDENER AND A MEMORY SYSTEM INCLUDING THE SAME

Номер: US20170033779A1
Принадлежит:

A pulse width widener includes a delay circuit, a processing circuit, and a latch circuit. The delay circuit generates a first signal by delaying an input signal including a first pulse by a delay time. The processing circuit generates a second signal, and the second signal includes information of a second pulse that is temporally extended from the first pulse when a width of the first pulse is smaller than the delay time, based on the first and second signals. The latch circuit stores the second signal and outputs the second pulse as an output signal. 1. A pulse width widener comprising:a delay circuit configured to generate a first signal by delaying a first pulse of an input signal by a delay time;a processing circuit configured to generate a second signal, the second signal including information of a second pulse that is temporally extended from the first pulse when a width of the first pulse is smaller than the delay time; anda latch circuit configured to store the second signal and configured to output the second pulse as an output signal.2. The pulse width widener of claim 1 , wherein a width of the second pulse is the same as the delay time.3. The pulse width widener of claim 1 , wherein the processing circuit generates the second signal including information of a third pulse when the input signal includes the third pulse and a width of the third pulse is equal to or larger than the delay time.4. The pulse width widener of claim 1 , wherein the delay time is fixed.5. The pulse width widener of claim 1 , wherein the delay time is modified by a user.6. The pulse width widener of claim 1 , wherein the first pulse is a portion of the input signal and the portion is from a first time point of the input signal claim 1 , at the first time point the input signal moves from an activation level to a deactivation level claim 1 , to a second time point of the input signal claim 1 , at the second time point the input signal moves from the deactivation level to the ...

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01-02-2018 дата публикации

CIRCUIT TECHNIQUE TO TRACK CMOS DEVICE THRESHOLD VARIATION

Номер: US20180034452A1
Автор: Chen Min, Chen Nan, Lu Shan
Принадлежит:

Methods and systems for independently tracking NMOS device process variation and PMOS device process variation are described herein. In one embodiment, a method for tracking process variation includes measuring a frequency of an NMOS-based ring oscillator on a chip, and determining a threshold voltage or switching speed for NMOS transistors on the chip based on the measured frequency of the NMOS-based ring oscillator. The method also includes measuring a frequency of a PMOS-based ring oscillator on the chip, and determining a threshold voltage or switching speed for PMOS transistors on the chip based on the measured frequency of the PMOS-based ring oscillator. 1. A method for tracking process variation , comprising:measuring a frequency of an NMOS-based ring oscillator on a chip;determining a threshold voltage or switching speed for NMOS transistors on the chip based on the measured frequency of the NMOS-based ring oscillator;measuring a frequency of a PMOS-based ring oscillator on the chip; anddetermining a threshold voltage or switching speed for PMOS transistors on the chip based on the measured frequency of the PMOS-based ring oscillator.2. The method of claim 1 , wherein the NMOS-based ring oscillator includes a plurality of inverters coupled in a closed loop claim 1 , each of the inverters comprising:a first NMOS transistor, wherein the NMOS transistor is diode-connected; anda second NMOS transistor having a gate coupled to an input of the inverter, and a drain coupled to a source of the first NMOS transistor and an output of the inverter.3. The method of claim 1 , wherein the PMOS-based ring oscillator includes a plurality of inverters coupled in a closed loop claim 1 , each of the inverters comprising:a first PMOS transistor, wherein the PMOS transistor is diode-connected; anda second PMOS transistor having a gate coupled to an input of the inverter, and a drain coupled to a source of the first PMOS transistor and an output of the inverter.4. The method of ...

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30-01-2020 дата публикации

Duty cycle for inductive position sensors

Номер: US20200033161A9
Автор: Ryan W. Elliott
Принадлежит: KSR IP Holdings LLC

A duty cycle is used in conjunction with a powered oscillator to electronically reduce the current draw by reducing the average current and thus reducing the sensor radiated emissions without altering an inductive position sensor. The duty cycle and the switching of the oscillation drive enable an on and an off cycling of the inductive position sensor such that an oversampling may occur without altering the hardware, but providing the improvements. As such, the inductive position sensor may only have an oscillation signal long enough to capture a stable sample and remain off for the duration of the sampling period. As such, a reduction in radiated emissions is achieved.

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30-01-2020 дата публикации

DEVICE FOR DETECTING A FAULT IN CIRCUIT PROPAGATING A CLOCK SIGNAL, AND CORRESPONDING METHOD

Номер: US20200033907A1
Принадлежит:

An electronic circuit includes a clock signal generator configured to deliver a clock signal. A propagation circuit is configured to propagate the clock signal on a plurality of propagation branches. A number of timers are coupled to at least some of the branches. The timers are clocked by corresponding replicas of the clock signal and configured to generate a pulse signal every N pulses of the corresponding replica of the clock signal. A comparator is configured to generate an alarm signal having a first state when two of the pulse signals are phase-offset with respect to one another. 1. An electronic circuit comprising:a clock signal generator configured to deliver a clock signal;a propagation circuit configured to propagate the clock signal on a plurality of propagation branches;a plurality of timers coupled to at least some of the branches, the timers clocked by corresponding replicas of the clock signal and configured to generate a pulse signal every N pulses of the corresponding replica of the clock signal; anda comparator configured to generate an alarm signal having a first state when two of the pulse signals are phase-offset with respect to one another.2. The circuit according to claim 1 , wherein the comparator comprises:a plurality of input terminals;a single output terminal that is configured to deliver the alarm signal; anda plurality of logic circuits connected in cascade, each input terminal of the comparator being coupled to a separate input of a logic circuit.3. The circuit according to claim 2 , wherein each logic circuit includes a single output claim 2 , the logic circuits being connected in series such that an initial logic circuit has inputs coupled to two separate timers claim 2 , and that the other logic circuits have one input coupled to the output of a separate logic circuit and a second input coupled to a separate timer claim 2 , a terminal logic circuit having an output coupled to the output terminal.4. The circuit according to claim 3 , ...

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17-02-2022 дата публикации

Current Mode Control Modulator Including Ramp Signal Generator Providing Slope Compensation

Номер: US20220052675A1
Принадлежит:

A current mode control modulation includes a ramp signal generator generating a slope compensated ramp signal with slope compensation. In some embodiments, the ramp signal generator generates a ramp signal for the current control loop having a first ramp portion with slope compensation and a second ramp portion that matches the expected current mode signal. In some embodiments, the ramp signal generator includes a switched capacitor circuit supplied by a current circuit to charge or discharge nodes in the switched capacitor circuit to generate the ramp signal with slope compensation. 1. A current mode control modulator generating a pulse width modulation (PWM) signal in response to a feedback voltage signal indicative of a regulated output voltage generated from an input voltage , the current mode control modulator comprising:a first error amplifier receiving the feedback voltage signal indicative of the regulated output voltage and a target voltage, the first error amplifier generating a signal indicative of a difference between the feedback voltage signal and the target voltage on an output terminal;a modulating comparator having a first input terminal receiving the signal indicative of the difference and a second input terminal receiving a current loop signal indicative of an expected current level, the modulating comparator having an output terminal generating a reset signal;a latch circuit having a reset input terminal coupled to receive the reset signal from the modulating comparator, a set input terminal coupled to receive a clock signal, and an output terminal generating the PWM signal, the PWM signal having an on-duration defining a duty cycle of the PWM signal and an off-duration, wherein the set signal initiates the on-duration of the PWM signal and the reset signal terminates the on-duration of the PWM signal; anda ramp signal generator circuit receiving the PWM signal and generating a slope compensated ramp signal as the current loop signal, the ramp ...

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17-02-2022 дата публикации

DUTY ADJUSTMENT CIRCUIT, AND DELAY LOCKED LOOP CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME

Номер: US20220052678A1
Автор: CHOI GARAM, CHOI HUNDAE
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A duty adjustment circuit, and a delay locked loop circuit and a semiconductor memory device including the same are provided. The duty adjustment circuit includes a pulse generator configured to generate a pulse signal at a constant pulse width regardless of a frequency of a reference clock signal, based on frequency information, a code generator configured to generate a first predetermined number of delayed pulse signals by delaying the pulse signal, as a first code in response to the pulse signal, and a duty adjuster configured to receive a delay clock signal, and generate a duty correction clock signal by adjusting a slope of rising transition and a slope of falling transition of the delay clock signal in response to the first code and a second code. 1. A duty adjustment circuit comprising:a pulse generator configured to generate a pulse signal at a constant pulse width regardless of a frequency of a reference clock signal, based on frequency information;a code generator configured to generate a first predetermined number of delayed pulse signals by delaying the pulse signal, as a first code in response to the pulse signal; anda duty adjuster configured to receive a delay clock signal, and generate a duty correction clock signal by adjusting a slope of rising transition and a slope of falling transition of the delay clock signal based on the first code and a second code.2. The duty adjustment circuit of claim 1 , wherein the pulse generator comprises:{'claim-text': ['receive the reference clock signal and generate an inverted reference clock signal by inverting the reference clock signal; and', 'generate a 2-divided reference clock signal, a 4-divided reference clock signal, an inverted 4-divided reference clock signal, and an inverted 8-divided reference clock signal by dividing the reference clock signal; and'], '#text': 'a first logic circuit unit configured to:'}{'claim-text': ['generate a first signal using the inverted 8-divided reference clock signal, the ...

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04-02-2021 дата публикации

MULTIPLEXED POWER GENERATOR OUTPUT WITH CHANNEL OFFSETS FOR PULSED DRIVING OF MULTIPLE LOADS

Номер: US20210035778A1
Принадлежит:

This disclosure describes systems, methods, and apparatus for a pulsed power supply assembly that distributes pulsed power to two or more loads using a single pulsed power supply. A pulsed power supply of the assembly can phase shift pulses to the different loads to ensure that there is no overlap between pulses at the outputs even where target frequencies and/or duty cycles for the different loads would otherwise call for such pulse overlaps. Variances applied by the pulsed power supply can be limited by attempts to keep average parameters of the pulse trains provided to the different loads to within predetermined variances. 1. A pulsed power supply assembly configured to couple to and drive two or more loads , the pulsed power supply assembly comprising: two or more pulsed outputs each configured for coupling to one of the two or more loads;', 'a power distribution switching assembly coupled to an input of the multiplexing unit and the two or more pulsed outputs and configured to split pulses from a pulse train received at the input into distributed pulses at the two or more pulsed outputs;, 'a multiplexing unit comprising a periodic pulse generator;', 'phase shift circuitry coupled to an output of the periodic pulse generator and coupled to an output of the pulsed power supply;', 'a memory storing target parameters for each of the two or more loads; and', access the target parameters in the memory;', 'generate a schedule of distributed pulses for the multiplexing unit;', 'predict instances of overlap between the distributed pulses in the schedule;', 'generate a new schedule that avoids the instances of overlap; and', 'instruct the phase shift circuitry to modify a periodic pulse train from the periodic pulse generator to generate the pulse train such that the pulse train aligns with the new schedule., 'a processing portion coupled to the memory and reading processor executable instructions on the memory, that when executed, cause the processing portion to], 'a ...

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04-02-2021 дата публикации

Boost dc-dc converter using dsm, duty controller for boost dc-dc converter, and method for configuring duty controller

Номер: US20210036613A1

A boost direct current-to-direct current (DC-DC) converter using a delta-sigma modulator (DSM), the boost DC-DC converter may comprise a boost driving circuit outputting an output voltage to output terminals by boosting an input voltage, a resistance distribution circuit outputting a feedback voltage by distributing the output voltage of the boost driving circuit, a compensator outputting a compensated feedback voltage by compensating for the feedback voltage outputted by the resistance distribution circuit based on a reference voltage, a delta-sigma modulator outputting a digital signal by modulating the compensated feedback voltage and a duty controller outputting a duty control signal for controlling a switching duty of the boost driving circuit by receiving the output of the delta-sigma modulator.

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04-02-2021 дата публикации

AUTONOMOUS DUTY CYCLE CALIBRATION

Номер: US20210036690A1
Автор: TANG Qiang
Принадлежит:

Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to determine when one or more duty cycle calibration (DCC) conditions are met. When the DCC condition(s) are met, the clock distortion calibration circuitry is configured adjust a trim value associated with at least one of first and second duty cycles of first and second voltage signals, respectively. In some embodiments, the clock distortion calibration circuitry is configured to calibrate at least one of the first and the second duty cycles of the first and the second voltage signals using the adjusted trim value to account for duty cycle distortion encountered across various voltages and/or temperatures while the electrical circuit devices and/or systems remain in a powered on state. 1. A memory device comprising clock distortion calibration circuitry configured to:in response to determining that a duty cycle calibration (DCC) condition is met, execute a DCC operation to adjust a trim value associated with a duty cycle of a voltage signal;while executing the DCC operation, determine that the DCC condition is no longer met; andinterrupt the DCC operation such that the clock distortion calibration circuitry (i) does not adjust the trim value or (ii) does not use an adjusted trim value to calibrate the duty cycle of the voltage signal.2. The memory device of claim 1 , wherein claim 1 , to interrupt the DCC operation claim 1 , the clock distortion calibration circuitry is configured to pause or stop the DCC operation.3. The memory device of claim 1 , wherein the clock distortion calibration circuitry is configured to execute the DCC operation only when the DCC condition is met.4. The memory device of claim 1 , wherein the DCC condition includes enablement of the ...

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09-02-2017 дата публикации

APPARATUSES AND METHODS FOR PHASE INTERPOLATING CLOCK SIGNALS AND FOR PROVIDING DUTY CYCLE CORRECTED CLOCK SIGNALS

Номер: US20170040986A1
Автор: Ma Yantao
Принадлежит: MICRON TECHNOLOGY, INC.

Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes a clock generator circuit configured to provide first and second clock signals responsive to an input dock signal. A duty phase interpolator circuit may be coupled to the dock generator circuit and configured to provide a first and second duty cycle corrected interpolated clock signals. A duty cycle adjuster circuit may be coupled to the duty phase interpolator circuit and configured to receive the first and second duty cycle corrected interpolated clock signals and provide a duty cycle corrected dock signal responsive thereto. A duty cycle detector may be coupled to the duty cycle adjuster circuit and configured to detect duty cycle error of the duty cycle corrected clock signal and provide the adjustment signals to correct the duty cycle error. 1. An apparatus comprising:a clock generator circuit configured to provide first and second clock signals responsive to an input clock signal;a duty phase interpolator circuit coupled to the clock generator circuit and configured to provide a first and second duty cycle corrected interpolated clock signals, the first and second duty cycle corrected interpolated clock signals approximately 180 degrees out of phase relative to one another;a duty cycle adjuster circuit coupled to the duty phase interpolator circuit and configured to receive the first and second duty cycle corrected interpolated clock signals and provide a duty cycle corrected dock signal responsive thereto, and further configured to adjust a duty cycle responsive to adjustment signals; anda duty cycle detector coupled to the duty cycle adjuster circuit and configured to detect duty cycle error of the duty cycle corrected clock signal and provide the adjustment signals to the duty cycle adjuster circuit to adjust the duty cycle to correct the duty cycle error.2. The apparatus of wherein the duty phase ...

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08-02-2018 дата публикации

SUPPRESSION OF ELECTROMAGNETIC INTERFERENCE IN SENSOR SIGNALS

Номер: US20180041198A1
Принадлежит: ANALOG DEVICES, INC.

Circuits and techniques are described for reducing the impact of environmental noise and interference on the output signal of a capacitive sensor. The output signal is sampled randomly in some situations by generating a random sampling instant within a fixed clock period. The sampling is performed by a sampling or demodulation circuit. The demodulation circuit may be part of a larger circuit with various components that operate based on a fixed period clock signal. 1. An apparatus , comprising:a capacitive sensor;a sampling circuit coupled to an output of the capacitive sensor;a clock edge randomization circuit coupled to an input of the sampling circuit and configured to provide to the sampling circuit a sampling signal with a fixed clock period and a randomly varying duty cycle.2. The apparatus of claim 1 , further comprising a modulation circuit coupled to an input of the capacitive sensor claim 1 , the modulation circuit configured to receive a clock signal having the fixed clock period and to provide a modulated signal to the capacitive sensor.3. The apparatus of claim 2 , further comprising a clock circuit configured to generate the clock signal with the fixed clock period claim 2 , wherein the modulation circuit and the clock edge randomization circuit are coupled to an output of the clock circuit to receive the clock signal.4. The apparatus of claim 2 , further comprising a feedback circuit coupled to an output of the sampling circuit and coupled to an input of the modulation circuit.5. The apparatus of claim 1 , wherein the sampling circuit is configured to produce a half-wave sampled signal.6. The apparatus of claim 1 , wherein the apparatus lacks a signal chopper coupled to the capacitive sensor.7. The apparatus of claim 1 , wherein the capacitive sensor claim 1 , sampling circuit claim 1 , and clock edge randomization circuit are part of an electronic control unit claim 1 , the apparatus further comprising an onboard vehicle computer and a wire coupling ...

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08-02-2018 дата публикации

SOLID STATE LIGHTING FIXTURES AND IMAGE CAPTURE SYSTEMS

Номер: US20180041681A1
Принадлежит:

An LED-based lighting fixture sets or adjusts a parameter of a drive signal that is used to drive its LEDs to be more compatible with the camera system; the camera system sets or adjusts an image capture parameter to be more compatible with the LED-based lighting fixture, or a combination thereof. The drive signal may be a PWM signal with a variable PWM frequency and/or duty cycle, a variable DC signal, or any combination thereof. The parameter of the drive signal that may be set or adjusted includes, but is not limited to, a PWM period, PWM frequency, PWM duty cycle, amplitude of the active and inactive portions of the PWM signal, and the like. The image capture parameter that may be adjusted includes, but is not limited to, frame rate, frame period, integration time, gain, shutter type (i.e. rolling shutter, global shutter, etc.), and the like. 1. A lighting fixture comprising:a plurality of LEDs providing a light source for general illumination of an environment; andfixture control circuitry configured to provide a pulse width modulated (PWM) drive signal having a PWM period and a variable duty cycle wherein varying the duty cycle varies an intensity of light emitted from the plurality of LEDs, and the PWM period is an integer multiple of a frame period of a camera operating in the environment.2. The lighting fixture of further comprising a communication interface associated with the fixture control circuitry and configured to receive information bearing on the frame period claim 1 , wherein the fixture control circuitry sets the PWM period to be an integer multiple of the frame period based on the information.3. The lighting fixture of wherein the information identifies a frame rate corresponding to the frame period.4. The lighting fixture of wherein the information is received from a camera system that operates at a frame rate corresponding to the frame period.5. The lighting fixture of wherein the integer multiple of the frame period is at least ten (10).6. ...

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24-02-2022 дата публикации

DIGITALLY CALIBRATED SAWTOOTH GENERATOR FOR PWM BASED BUCK CONVERTERS

Номер: US20220060180A1
Принадлежит:

Embodiments herein relate to a circuit which generates a sawtooth waveform based on an adaptive feedback loop that self-corrects the ramp up rate to account for variations in a device. The sawtooth waveform is obtained by repeatedly charging and discharging a capacitor according to a clock signal. The sawtooth waveform can be sampled once per clock period at a comparator which provides a corresponding binary output to a state machine. If the binary output indicates the amplitude of the sawtooth waveform is below a desired maximum voltage, the state machine outputs a code word to a digitally-controlled variable current source to increase the output current. The sawtooth waveform can be used to provide a pulse-width modulated (PWM) waveform such as for a DC-DC converter. 1. An apparatus , comprising:a variable current source;a capacitor coupled to the variable current source via a node and a first switch and to a discharge point via a second switch, wherein to provide a sawtooth waveform at the node, the capacitor is to be charged by the variable current source when the first switch is closed and the second switch is opened, and the capacitor is to discharge to the discharge point when the second switch is closed and the first switch is opened; anda comparator comprising an inverting input terminal coupled to the node and a non-inverting input terminal coupled to a first reference voltage;wherein the variable current source is to adjust a respective output current in response to a sample of an output signal from the comparator.2. The apparatus of claim 1 , further comprising:a pulse-width modulated (PWM) waveform generator coupled to the node and to a second reference voltage, wherein the PWM waveform generator is to generate a PWM waveform based on a comparison between a voltage of the sawtooth waveform and the second reference voltage.3. The apparatus of claim 2 , wherein:the PWM waveform generator is to change a level of the PWM waveform when the voltage of the ...

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24-02-2022 дата публикации

Pre-charge techniques for a multi-level flying capacitor converter

Номер: US20220060183A1
Принадлежит: Texas Instruments Inc

A circuit includes first and second transistors, a capacitor, and a controller. The controller is coupled to the control inputs of the first and second transistors. The controller configured to, during a first mode and in accordance with a first time-varying duty cycle, turn on and off the first transistor while turning on the second transistor when the first transistor is off. The controller is also configured to, during a second mode following the first mode, and in accordance with a second time-varying duty cycle, turn on and off the first transistor while turning on the second transistor when the first transistor is off.

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07-02-2019 дата публикации

COMPACT HIGH SPEED DUTY CYCLE CORRECTOR

Номер: US20190044521A1
Принадлежит:

Embodiments of the present invention provide techniques for duty cycle correction of clock signals. An input clock signal passes through a pair of output transistors, which provides an output clock signal based on the input clock signal. A duty cycle sensor generates a first correction signal based on the output clock signal. The first correction signal is at least partially opposite of the output clock signal. A duty cycle corrector generates a second correction signal based on the first correction signal. The duty cycle corrector includes two or more transistors for generating the second correction signal. The second correction signal is applied to the output clock signal. There are other embodiments as well. 1. A duty cycle correction device comprising:a first pair of transistors being configured to receive a first clock signal and output a second clock signal, the first clock signal being characterized by a first duty cycle and a signal frequency;an output terminal for outputting a corrected clock signal, the output terminal being coupled to the first pair of transistors, the corrected clock signal being characterized by a second duty cycle, the second duty cycle being closer to 50% than the first duty cycle;a duty cycle sensor coupled to the output terminal and being configured to generate a first correction signal, the first correction signal being substantially inverted relative to the first clock signal; anda duty cycle corrector being configured to generate a second correction signal using at least the first correction signal, the second correction signal being coupled to the output terminal, the duty cycle corrector comprising a second pair of transistors.2. The device of wherein the first pair of transistors comprises a PMOS transistor and an NMOS transistor.3. The device of wherein the duty cycle comprises a first inverter and a second inverter.4. The device of wherein further comprising an input terminal for receiving the first clock signal from a clock ...

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18-02-2021 дата публикации

SIGNAL GENERATION CIRCUIT SYNCHRONIZED WITH A CLOCK SIGNAL AND A SEMICONDUCTOR APPARATUS USING THE SAME

Номер: US20210050855A1
Автор: KIM Young Ouk
Принадлежит: SK HYNIX INC.

A signal generation circuit includes a clock divider circuit, an off-pulse generation circuit, and an output signal generation circuit. The on-pulse generation circuit delays an input signal in synchronization with the first and second divided clock signals and generates an even on-pulse signal and an odd on-pulse signal. The off-pulse generation circuit delays the even on-pulse signal and the odd-on pulse signal in synchronization with the first divided clock signal and the second divided clock signal and generates a plurality of delay signals. The output signal generation circuit generates a first pre-output signal based on the delay signals delayed in synchronization with the first divided clock signal, generate a second pre-output signal based on the delay signals delayed in synchronization with the second divided clock signal, and generate an output signal based on the first and second pre-output signals. 1. A signal generation circuit comprising:a clock divider circuit configured to generate a first divided clock signal, a second divided clock signal, a third divided clock signal, and a fourth divided clock signal based on a clock signal;an on-pulse generation circuit configured to delay an input signal in synchronization with the first and second divided clock signals to generate an even on-pulse signal and an odd on-pulse signal, based on first delay information;an off-pulse generation circuit configured to sequentially delay the even on-pulse signal alternately in synchronization with the second divided clock signal and the first divided clock signal to generate a plurality of even delay signals, based on second delay information, and to sequentially delay the odd on-pulse signal alternately in synchronization with the first divided clock signal and the second divided clock signal to generate a plurality of odd delay signals, based on the second delay information; andan output signal generation circuit configured to generate a first pre-output signal based ...

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06-02-2020 дата публикации

Per Lane Duty Cycle Correction

Номер: US20200044640A1
Принадлежит:

The present disclosure relates generally to improved systems and methods for control of one or more timing signals in a memory device. More specifically, the present disclosure relates to configurable duty cycle correction at one or more DQ pins (e.g., data input/output (I/O) pins) of the memory device. For example, the memory device may include a configurable phase splitter and/or selective capacitive loading circuitry implemented to adjust the duty cycle of a timing signal at one or more DQ pins during and/or after manufacture of the memory device. Accordingly, the memory device may include increased flexibility and granularity of control over the one or more timing signals. 1. A device , comprising:configurable logic circuitry configured to be adjusted during manufacture of the device, during runtime of the device, after a reset of the device, or a combination thereof;configurable timing circuitry communicatively coupled to the configurable logic circuitry and configured to adjust a duty cycle of a timing signal based at least in part on an input signal produced at the configurable logic circuitry, wherein adjusting the duty cycle of the timing signal comprises delaying a first phase of the timing signal with respect to a second phase of the timing signal or advancing the first phase of the timing signal with respect to the second phase of the timing signal; anda DQ pin communicatively coupled to the configurable timing circuitry and configured to control output of a DQ signal based at least in part on the duty cycle of the timing signal.2. The device of claim 1 , wherein the configurable logic circuitry comprises a mode register claim 1 , a fuse claim 1 , an antifuse claim 1 , or a combination thereof.3. The device of claim 1 , wherein the configurable logic circuitry is configured to adjust the input signal in response to an adjustment to the configurable logic circuitry during the manufacture of the device claim 1 , during the runtime of the device claim 1 , ...

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08-05-2014 дата публикации

DUTY CYCLE CORRECTION APPARATUS

Номер: US20140125391A1
Автор: SEON Jong Kug
Принадлежит: LSIS CO., LTD.

Disclosed is a duty cycle correction apparatus. The apparatus of the present invention adjusts signal widths of an input signal, averages the widths of the signal, and inverts the signal, then averages the widths of the inverted signal, compares the two averaged signals, and outputs the difference between the two averaged signals. 1. An apparatus for correcting duty cycle , the apparatus configured to correct a duty ratio of an input signal , the apparatus comprising:an alert clock configured to adjust a signal width of the input signal;a first equalization unit configured to equalize a width of an output signal of the alert clock;an inverter configured to reverse the output signal of the alert clock;a second equalization unit configured to equalize a width of an output signal of the inverter; anda comparator configured to compare the output signals of the first and second equalization units, and output a difference between the output signals of the first and second equalization units.2. The apparatus of claim 1 , wherein the alert clock is configured to adjust the width of the input signal using an output of the comparator.3. The apparatus of claim 1 , further comprising:a selector configured to select a ratio of the output signals of the first and second equalization units to allow the comparator to output the difference in response to the ratio.4. The apparatus of claim 1 , further comprising:a first buffer configured to temporarily store an output of the alert clock and output the output of the alert clock to the first equalization unit.5. The apparatus of claim 4 , wherein the inverter is configured to reverse an output of the first buffer.6. The apparatus of claim 4 , further comprising:a second buffer configured to temporarily store and output an output of the first buffer.7. The apparatus of claim 2 , wherein the output of the comparator is inputted to the alert clock until the output of the comparator substantially becomes zero claim 2 , when a duty ratio ...

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03-03-2022 дата публикации

Duty adjustment circuit, semiconductor storage device, and memory system

Номер: US20220068405A1
Автор: Masashi Nakata
Принадлежит: Kioxia Corp

According to one embodiment, a duty adjustment circuit includes: a first delay circuit including a plurality of first delay elements connected in series, each of the first delay elements has a first delay amount; a second delay circuit having a first variable delay unit configured to set a second delay amount smaller than the first delay amount; and a third delay circuit having a second variable delay unit configured to set a third delay amount smaller than the first delay amount. An output terminal of the second delay circuit is connected to an even numbered one of the first delay elements, and an output terminal of the third delay circuit is connected to an odd numbered one of the first delay elements.

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03-03-2022 дата публикации

FREQUENCY MULTIPLIER AND DELAY-REUSED DUTY CYCLE CALIBRATION METHOD THEREOF

Номер: US20220069809A1
Принадлежит:

A frequency multiplier and a delay-reused duty cycle calibration method thereof are provided. The frequency multiplier includes a first calibration circuit, a second calibration circuit and a controller. In a calibration mode of the frequency multiplier, an output terminal of a delay cell is coupled to an input terminal of the delay cell. The first calibration circuit repeatedly uses the delay cell M times for generating a first delayed signal. The controller controls the delay cell according to the first delayed signal, to find a delay of the delay cell which makes M times the delay be equal to one cycle period of an input clock signal. After the delay is found, the delay cell is repeatedly used M/2 times for generating a second delayed signal. The controller controls the second calibration circuit according to the second delayed signal to make an input calibration signal have a target duty cycle.

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25-02-2016 дата публикации

APPARATUS, SYSTEM, AND METHOD FOR RE-SYNTHESIZING A CLOCK SIGNAL

Номер: US20160056807A1
Принадлежит:

Described herein are apparatus, method, and system for re-synthesizing a clock signal. The apparatus comprises: a first logic unit to detect a rising edge of an input clock signal and for generating a rising edge of an output clock signal based on the detected rising edge of the input clock signal, the input clock signal having a non-50% duty cycle and a first period; and a second logic unit to compute a falling edge of the output clock signal according to the detected rising edge of the input clock signal, the falling edge of the output clock signal being near half of the first period. 1. An apparatus comprising:a first logic unit to detect a rising edge of an input clock signal and to generate a set signal for generating a rising edge of an output clock signal based on the detected rising edge of the input clock signal; anda second logic unit comprising a first counter to count to a first count that represents a halfway mark of a first period of the input clock signal to generate a reset signal for generating a falling edge of the output clock signal according to the first count, the falling edge of the output clock signal being near half of the first period.2. The apparatus of further comprises:a logic unit to generate a voltage supply identity (VID) signal by applying the output clock signal as a sampling clock signal; anda voltage regulator module to generate a regulated power supply according to the VID signal.3. The apparatus of further comprises:an output sequential logic unit; and set itself in response to a set signal which is an output of the first logic unit, the set signal based on the detected rising edge of the input clock signal; and', 'reset itself in response to a reset set signal which is an output of the second logic unit., 'a ring oscillator to provide a sampling clock signal for the first and second logic units and the output sequential logic unit, wherein the output sequential logic unit is operable to4. The apparatus of claim 1 , wherein the ...

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14-02-2019 дата публикации

FUNCTIONAL SAFETY CLOCKING FRAMEWORK FOR REAL TIME SYSTEMS

Номер: US20190052277A1
Принадлежит: Intel Corporation

Methods and apparatus relating to functional safety clocking framework for real time systems are described. In an embodiment, clock monitoring logic circuitry monitors a plurality of clock signals. Safety island logic circuitry receives an error status signal from the clock monitoring logic circuitry based at least in part on a determination of whether an error exists for at least one of the plurality of clock signals. Safety logic circuitry to receive an interrupt signal from the safety island logic circuitry in response to a determination that the error status signal indicates existence of an error for at least one of the plurality of clock signals. Other embodiments are also disclosed and claimed. 1. An apparatus comprising:clock monitoring logic circuitry to monitor a plurality of clock signals;safety island logic circuitry to receive an error status signal from the clock monitoring logic circuitry based at least in part on a determination of whether an error exists for at least one of the plurality of clock signals; andsafety logic circuitry to receive an interrupt signal from the safety island logic circuitry in response to a determination that the error status signal indicates existence of an error for at least one of the plurality of clock signals, wherein the plurality of clock signals comprises one or more of: a base clock signal or a derived clock signal, wherein the derived clock signal is to be generated based on the base clock signal.2. The apparatus of claim 1 , wherein the clock monitoring logic circuitry is to determine whether the error exists based on a cross check of two of the plurality of clock signals.3. The apparatus of claim 1 , wherein the clock monitoring logic circuitry is to determine whether the error exists for the base clock signal before the derived clock signal.4. The apparatus of claim 1 , wherein the error is one or more of: an frequency error claim 1 , an aging error claim 1 , a duty cycle error claim 1 , a clock lock error claim ...

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25-02-2021 дата публикации

PWM SIGNAL GENERATION AND ERROR CALIBRATION CIRCUIT

Номер: US20210058072A1
Автор: Zhao Dongshi
Принадлежит:

A PWM signal generation and error calibration circuit includes an amplifier OP, an amplifier OP, a comparator CMP, a comparator CMP, PMOS field-effect transistors M-M, a resistor R, a resistor R_FRE, variable resistors R-R, a resistor R, a capacitor C, a matched resistance module circuit, a current drain IDC, and a 14-bit counter. The PWM signal generation and error calibration circuit saves chip costs and supports a wide PWM signal frequency range, while being able to calibrate all duty cycle errors of PWM signals in the range between 0% and 100% with improved accuracy. 1. A PWM signal generation and error calibration circuit , comprising a first amplifier , a second amplifier , a first comparator , a second comparator , a first , a second , a third , a fourth , a fifth , a sixth , a seventh , an eighth , a ninth , a tenth , an eleventh , a twelfth , a thirteenth , a fourteenth , a fifteenth , and a sixteenth PMOS field-effect transistors , a first resistor , a second resistor , a first and a second variable resistors , a third resistor , a first capacitor , a matched resistance module circuit , a current drain , and a 14-bit counter;the first amplifier having a positive input terminal thereof connected to a reference voltage and having an output terminal thereof connected to a gate of the fifteenth PMOS field-effect transistor; the first, second and fifteenth PMOS field-effect transistors and the first resistor being connected in series between a power source and a ground; the first amplifier having a negative input terminal thereof connected between the fifteenth PMOS field-effect transistor and the first resistor;the third and the fourth PMOS field-effect transistors and the first variable resistor being connected in series between the power source and the ground;the fifth and sixth PMOS field-effect transistors and the second variable resistor being connected in series between the power source and the ground;the seventh PMOS field-effect transistor and the ...

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25-02-2021 дата публикации

CIRCUIT HAVING A PLURALITY OF MODES

Номер: US20210058079A1
Автор: Chang Szu-Yang
Принадлежит:

The present invention provides a circuit having a plurality of modes, wherein the circuit includes a first circuit, a second circuit, a first multiplexer, a second multiplexer and a specific flip-flop. In the operations of the circuit, the first circuit is configured to generate a first signal, the second circuit is configured to generate a second signal, the first multiplexer is configured to output one of the first signal and the second signal according to a mode selection signal, the second multiplexer is configured to output one of a first clock signal and a second clock signal according to the mode selection signal, and the specific flip-flop is configured to sample the first signal or the second signal outputted by the first multiplexer by using the first clock signal or the second clock signal outputted by the second multiplexer to generate an output signal. 1. A circuit having a plurality of modes , comprising:a first circuit, arranged to generate a first signal;a second circuit, arranged to generate a second signal;a first multiplexer, coupled to the first circuit and the second circuit, arranged to output one of the first signal and the second signal according to a mode selection signal;a second multiplexer, arranged to output one of a first clock signal and a second clock signal according to the mode selection signal; anda specific flip-flop, coupled to the first multiplexer and the second multiplexer, arranged to sample the first signal or the second signal outputted by the first multiplexer by using the first clock signal or the second clock signal outputted by the second multiplexer to generate an output signal.2. The circuit of claim 1 , wherein the first clock signal and the second clock signal have different phases.3. The circuit of claim 2 , wherein the first circuit comprises:a first flip-flop; anda logical circuit, arranged to generate the first signal according to an output signal of the first flip-flop; and 'a second flip-flip, arranged to ...

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13-02-2020 дата публикации

CLOCK CIRCUIT HAVING A PULSE WIDTH ADJUSTMENT MODULE

Номер: US20200052681A1
Принадлежит:

A clock circuit has a clock input terminal, a first clock output terminal, and a second clock output terminal. The clock circuit includes a pulse width adjustment module, a sampling module, a comparing module, and a differential signal converting module. A differential input terminal is electrically connected to a pulse width output terminal of the pulse width adjustment module. A positive differential signal output terminal and a negative differential signal output terminal are electrically connected to the first clock output terminal of the clock circuit and the second clock output terminal to output two clock signals with a phase difference of 180 degrees, respectively. A second input terminal of the sampling module is electrically connected to the second clock output terminal. 1. A clock circuit having a clock input terminal and a clock output terminal , wherein the clock input terminal receives an input clock signal , and the clock output terminal outputs an output clock signal , the clock circuit comprising:a pulse width adjustment module including a pulse width input terminal, a control terminal, a power terminal, a ground terminal, and a pulse width output terminal, the pulse width input terminal electrically connected to the clock input terminal to receive the input clock signal, the power terminal electrically connected to a first reference voltage, and the ground terminal electrically connected to a ground voltage;a sampling module including a first input terminal, a second input terminal, and a first output terminal, the first input terminal of the sampling module electrically connected to the clock output terminal of the clock circuit, the sampling module used for sampling an output voltage of the clock output terminal of the clock circuit to generate a first sampling voltage, and the first output terminal used to output the first sampling voltage;a comparing module including a first comparing input, a second comparing input terminal, and a comparing ...

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20-02-2020 дата публикации

DELAY-LOCKED LOOP CIRCUIT, SEMICONDUCTOR MEMORY DEVICE, AND METHODS OF OPERATING DELAY-LOCKED LOOP CIRCUIT

Номер: US20200059226A1
Принадлежит:

A delay-locked loop circuit includes first and second duty cycle correctors, and first and second duty cycle detectors. The first duty cycle corrector adjusts duties of some of first through fourth divided clock signals to provide first through fourth corrected clock signals, in response to a first correction code. The second duty cycle corrector adjusts delays of some of second through fourth delayed clock signals to provide first through fourth source clock signals, in response to a second correction code. The first duty cycle detector detects a duty of first propagation clock signal to generate a first sub-correction code of the first correction code, and duties of first and second recovered clock signals to generate the second correction code. The second duty cycle detector detects a duty of second propagation clock signal to generate a second sub-correction code of the first correction code. 1. A delay-locked loop (DLL) circuit of a semiconductor memory device , the DLL circuit comprising:a first duty cycle corrector to adjust duties of at least some of first through fourth divided clock signals to provide first through fourth corrected clock signals, in response to a first correction code, wherein the first through fourth divided clock signals are generated based on a reference clock signal, have a phase difference of 90 degrees with respect to each other;a second duty cycle corrector to adjust delays of at least some of second through fourth delayed clock signals of first through fourth delayed clock signals to provide first through fourth source clock signals, in response to a second correction code, wherein the first through fourth delayed clock signals are generated by delaying the first through fourth corrected clock signals;a clock tree to provide the first through fourth source clock signals to an inside of the semiconductor memory device as first through fourth propagation clock signals;a first duty cycle detector to detect a duty of the first ...

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02-03-2017 дата публикации

DIGITAL CURRENT SENSING IN POWER CONTROLLER

Номер: US20170063360A1
Принадлежит:

Some embodiments include apparatus and methods having a node to provide a signal, and a control unit arranged to control a value of an output voltage at an output node on an output path based on a duty cycle of the signal and a value of an input voltage. The control unit can also be arranged to cause a change in a resistance on the output path in order to determine a value of a current on the output path based at least on the change in the resistance. 1. An apparatus comprising:a node to provide a signal; anda control unit to determine a value of a current on an output p based at least on a duty cycle of the signal and a value of an input voltage.2. The apparatus of claim 1 , wherein the control unit is to cause a change in a resistance on the output path in order to cause a change in the duty cycle of the signal.3. The apparatus of claim 1 , wherein the control unit includes a current calculator to calculate the value of the current based on the value of the input voltage claim 1 , a value of a change in the duty cycle of the signal claim 1 , and a value of the change in the resistance.4. The apparatus of claim 3 , wherein the control unit is included in an integrated circuit die claim 3 , and the current calculator is to obtain the value of the change in the resistance from a memory included in the integrated circuit die.5. The apparatus of claim 2 , wherein the control unit is to cause the change in the resistance during a time interval of an operation of the apparatus claim 2 , and the control unit includes a generator to generate the signal such that the time interval occurs during multiple cycles of the signal.6. The apparatus of claim 2 , wherein the control unit is to cause the change in the resistance during a time interval of an operation of the apparatus claim 2 , and the control unit is to switch a transistor on the output path from a first state to a second state during the time interval in order to cause the change in the resistance.7. The apparatus of ...

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