УСТРОЙСТВО ОБРАБОТКИ ДАННЫХ И СПОСОБ ОБРАБОТКИ ДАННЫХ

Группа изобретений относится к области обработки данных и может быть использована для кодирования/декодирования с использованием LDPC-кода. Техническим результатом является повышение устойчивости LDPC-кода к возникновению ошибок. LDPC-код включает в себя бит информации и бит четности. Матрица контроля четности включает в себя часть информационной матрицы, соответствующую битам информации, и часть матрицы четности, соответствующую битам четности. Часть информационной матрицы представлена таблицей начальных значений матрицы контроля четности. Таблица начальных значений матрицы контроля четности представляет собой таблицу, показывающую позиции элементов 1 части информационной матрицы каждые 360 столбцов. 12 н. и 60 з.п. ф-лы, 130 ил.

СПОСОБ ПЕРЕДАЧИ ДАННЫХ, СПОСОБ ПРИЕМА ДАННЫХ, УСТРОЙСТВО МОДУЛЯЦИИ ДАННЫХ, УСТРОЙСТВО ДЕМОДУЛЯЦИИ ДАННЫХ

Изобретение относится к способам передачи и приема данных и устройствам модуляции и демодуляции данных. Технический результат состоит в возможности достижения решения, превосходного по характеристикам нелинейных искажений. Для этого посредством использования сигнальных точек с круговой компоновкой, полученных перекомпоновкой части сигнальных точек, скомпонованных в прямоугольной форме или крестообразной форме, средняя мощность сигнала и пиковая энергия сигнала уменьшаются для улучшения характеристик нелинейных искажений. Предусмотрен способ битового отображения, в котором среднее значение расстояния Хемминга в показателях предписанной порции из младших битов между соседними сигнальными точками невелико, а евклидово расстояние между сигнальными точками, в которых порции из младших битов, назначенные на них, совпадают друг с другом, становится максимальным. Посредством применения кода с исправлением ошибок только к порции из младших битов, предоставлен способ передачи данных, превосходный ...

СПОСОБ И УСТРОЙСТВО ДЛЯ ИСПРАВЛЕНИЯ ОШИБОК ДАННЫХВ КАНАЛЕ СВЯЗИ

... 1. Устройство передачи, содержащее модуль прибавления избыточных битов, предназначенный для прибавления избыточных битов к последовательности конкретных битов в пределах множества битов, составляющих обеспеченные данные для формирования кодированных данных, причем упомянутые конкретные биты имеют значимость высокого уровня; и модуль модуляции, предназначенный для передачи модулированного волнового сигнала, сформированного на основе кодированных данных, сформированных упомянутым модулем прибавления избыточных битов. 2. Устройство передачи по п.1, в котором упомянутый модуль прибавления избыточных битов упорядочивает символы с добавленными избыточными битовыми данными так, что Евклидово расстояние данных с добавленными избыточными битовыми данными становится большим. 3. Устройство передачи по п.1, в котором упомянутый модуль прибавления избыточных битов прибавляет избыточные биты к упомянутой последовательности конкретных битов их упомянутых обеспеченных данных так, что формируется код Грея ...

Устройство для статистического обнаружения дискретных сигналов в каналах связи с межсимвольной интерференцией

Устройство для статистического обнаружения дискретных сигналов в каналах связи с межсимвольной интерференцией относится к технике электросвязи и может быть использовано в системах передачи данных контроля и управления. Цель изобретения - повышение помехоустойчивости при действии нестационарных помех. Цель достигается введением в устройство блока анализа помех, на выходе которого вырабатывается воздействие, управляющее порогом решающего порогового блока в зависимости от интенсивности нестационарных помех в канале связи, что увеличивает вероятность принятия правильного решения решающим блоком и помехоустойчивость устройства в целом. 1 3. п. ф-лы, 2 ил. ю (Л с 00 о: со Nj: СЮ Сд ю ...

Übertragung mit mehreren Auflösungen bei Verwendung von Mehrträgersignalen

Übertragung mit mehreren Auflösungen, insbesondere für Mehrträgersysteme

Vorrichtung und Verfahren zur Datenübertragung und zum Datenempfang in einem mobilen Kommunikationssystem mittels punktierten Raum-Zeit-Trellis-Kodes

Iterative Demodulation und Dekodierungeines Mehrpegel-Signals

EFFIZIENTE NORMALISIERUNG VOM TRELLISZUSTANDSMETRISCHEM WERT

VERFAHREN UND VORRICHTUNG ZUR DIGITALEN DATENÜBERTRAGUNG

VERFAHREN UND VORRICHTUNG ZUR DIGITALEN DATENÜBERTRAGUNG

Trelliscodierte Modulation

Trelliscodierter Modulator und Verfahren zur Erzeugung eines codierten Worts aus einem Eingangswort. Der TCM hat einen ersten logischen Zweig, der konfiguriert ist, einen Datenteil des codierten Worts zu erzeugen; und einen zweiten logischen Zweig, der mit dem ersten logischen Zweig parallelgeschaltet und konfiguriert ist, einen entsprechenden Paritätsteil des codierten Worts sequenziell nach der Erzeugung des Datenteils des codierten Worts zu erzeugen.

TERMINIERUNG VON KODIERTER ODER UNKODIERTER MODULATION MIT PFAD-ORIENTIERTEM DEKODIERER

Verfahren und Einrichtung zum Empfang von durch Intersymbolinterferenz getroffenen Signalen

Detektion einer Kodesequenz in einem Trellisdekoder

Detection of data bits in a slow frequency hopping communication system

In the detecting process, the carrier to interference (C/I) power ratio of the hop of a slow frequency hopping spread spectrum signal (112), is estimated (124) by using the data samples (120) of the hop. Subsequently, a data bit (130) is detected by using the estimated C/I power ratio (126). The detection process (128) may include utilizing maximum likelihood decoding techniques to derive a data bit (130) from decision metrics and the estimated C/I power ratio (126). The decision metrics correspond to a measurement of the distance of data samples (120) from constellation points within a constellation space representing data samples (120) previously used to generate decision metrics. The detection process (128) also may include utilizing the estimated C/I power ratio (126) in combining data samples (120) of the hop as received from two or more diversity receiver branches. ...

Binary data error correction using hint signal

An error detection and correction method and apparatus is described which permits the correction of double errors using a (15, 11) Hamming code and a parity bit. The Hamming code and parity bit allows the detection of double errors. A modulated waveform carrying the binary data is examined for anomalies such as noise pulses. A hint signal is generated based on the anomalies which points to a suspect bit. The state of this bit is changed to correct for double errors. ...

TRELLIS CODING METHOD AND ARRANGEMENT FOR FRACTIONAL BIT RATES

A signal coding technique for use with fractional bit rates is disclosed which, for a given dimensionality, allows the use of smaller constellations, and thus provides greater robustness in the presence of various impairments, than would otherwise be the case yet entails essentially no decoding delay penalty. In this technique, one or more of the input bits are trellis encoded and the trellis-encoded bits identify one of a predetermined plurality of subsets of the signal constellation and the particular symbols selected for transmission from two or more identified subsets are chosen by the non-trellis-encoded bits interdependently.

full-rank error correction coder using weighted non-binary repeat accumulate and space-time coding

An apparatus and method for weighted non-binary Repeat Accumulate RA coding and space-time coding are disclosed. Transmission data is divided in the units of frames each having mN bits, and each frame is further segmented into N blocks, each block containing m bits. The N blocks are converted to N non-binary GF(2m) elements. These N non-binary symbols are repeated, using a repeater 202, by a repetition factor r. The rN symbols are multiplied by weighting factors, using a weighter 204, being GF(2m) elements other than zero. The rN weighted symbols are interleaved, using an interleaver 206, and accumulated by an accumulator 212. The rN accumulated symbols are transmitted to a receiver, or each of the rN accumulated symbols is demapped to m bits prior to transmission. Therefore, information can be transmitted reliably in a wireless communication system. The method achieves unity data rate and maximum antenna diversity by providing a full-rank error correction coder using ...

A multilevel trellis coding method

A decoder for trellis-based channel encoding

A system and method for decoding a channel bit stream efficiently performs trellis-based operations. The system includes a butterfly coprocessor and a digital signal processor. For trellis-based encoders, the system decodes a channel bit stream by performing operations in parallel in the butterfly coprocessor, at the direction of the digital signal processor. The operations are used in implementing the MAP algorithm, the Viterbi algorithm, and other soft- or hard-output encoding algorithms. The DSP may perform memory management and algorithmic scheduling on behalf of the butterfly coprocessor. The butterfly coprocessor may perform parallel butterfly operations for increased throughput. The system maintains flexibility, for use in a number of possible decoding environments.

Decoding an input signal

CODING AND DECODING OF TRELLIS CODES WITH TRELLIS SECTIONS BASED ON BLOCK CODES WITH GOOD DISTANCE CHARACTERISTICS

NEW ARRANGEMENT OF THE SIGNAL CONSTELLATION FOR ARQ TRANSMISSION DIVERSITY PATTERN

DECODING SYSTEM AND PROCEDURE FOR DIGITAL COMMUNICATION

LOG MAP DECODING

BIT-INTERLOCKED CODED MODULATION WITH LOW DENSITY PARITY CHECK (LDPC) CODES

PROCEDURE AND DEVICE FOR THE EFFICIENT COMPUTATION OF LOGARITHMIC WARSCHEINLICHKEITSVERHÄLTNISSEN

MULTI-CARRIER TRANSMISSION WITH VARIABLE SYMBOL PART AND PROTECTION INTERVAL

PROCEDURE FOR THE BINARY CODING OF POINTS OF CONSTELLATION USED IN A OFDMTYP CARRIER MODULATION.

TRANSMISSION WITH SEVERAL DISSOLUTIONS, IN PARTICULAR FOR MULTI-CARRIER SYSTEMS

TRANSMISSION WITH SEVERAL DISSOLUTIONS, IN PARTICULAR FOR MULTI-CARRIER SYSTEMS

�BERTRAGUNG WITH SEVERAL AUFL�SUNGEN

TRANSMISSION WITH SEVERAL DISSOLUTIONS WHEN USING MULTI-CARRIER SIGNALS

�BERTRAGUNG WITH SEVERAL AUFL�SUNGEN, IN PARTICULAR WHEN MEHRTR�GERSIGNALEN

TRANSMISSION WITH SEVERAL DISSOLUTIONS WITH MULTI-CARRIER SIGNALS

TRANSMISSION WITH SEVERAL DISSOLUTIONS AS WELL AS ERRORCORRECTING CODING, WITH MULTI-CARRIER SIGNALS

TRANSMISSION WITH SEVERAL DISSOLUTIONS WITH MULTI-CARRIER SIGNALS

SYSTEM FOR TRANSMISSION AND DEVICE TO THE RECEIPT OF DIGITAL TELEVISION SIGNALS

PROCEDURE AND EQUIPMENT FOR THE SUPPLY FROM BITS TO SYMBOL ILLUSTRATION FOR AREA TIME KODEN

TRANSMISSION SYSTEM WITH LATTICE-CODED QAM

CODING AND DECODING OF TRELLIS CODES WITH TRELLIS SECTIONS BASED ON BLOCK CODES WITH GOOD DISTANCE CHARACTERISTICS

CODING AND DECODING OF TRELLIS CODES WITH TRELLIS SECTIONS BASED ON BLOCK CODES WITH GOOD DISTANCE CHARACTERISTICS

CODING AND DECODING OF TRELLIS CODES WITH TRELLIS SECTIONS BASED ON BLOCK CODES WITH GOOD DISTANCE CHARACTERISTICS

CODING AND DECODING OF TRELLIS CODES WITH TRELLIS SECTIONS BASED ON BLOCK CODES WITH GOOD DISTANCE CHARACTERISTICS

CODING AND DECODING OF TRELLIS CODES WITH TRELLIS SECTIONS BASED ON BLOCK CODES WITH GOOD DISTANCE CHARACTERISTICS

CODING AND DECODING OF TRELLIS CODES WITH TRELLIS SECTIONS BASED ON BLOCK CODES WITH GOOD DISTANCE CHARACTERISTICS

Apparatus and methods employing distribution preserving tomlinson precoding in transmission of digital data signals

A method and coding apparatus using low density parity check codes for data storage or data transmission

Data processing device and data processing method

The present technique relates to a data processing device that can improve tolerance of data errors, and to a data processing method. When a predetermined LDPC code having a coded rate of 8/15 is mapped with a code length of 16200 bits over 256 signal points, and when a demultiplexer designates the code bits of 8×1 bits and bits #i+1 from the highest of the symbol bits of the 8×1 bits of one symbol as bits b#i and y#i, respectively, replacements are performed for allocating b0 to y2, b1 to y6, b2 to y1, b3 to y0, b4 to y7, b5 to y5, b6 to y3, and b7 to y4. The present technique can be applied to a transfer system or the like for transferring LDPC code, for example.

Terrestrial digitial multimedia/television broadcasting system

Apparatus, and associated method, for forming a signal exhibiting space-time redundancy

Optimized code table signaling

In various embodiments, computer-implemented methods, systems, and non-transitory computer-readable memory media are disclosed. In one aspect, the computer-implemented method comprises receiving, by a processor, a digital bit stream; transforming, by the processor, the digital bit stream to an encoded digital bit stream, wherein the encoded digital bit stream comprises at least one of a gateway channel, a composite channel, or a data channel, and any combination thereof; and providing, by the processor, the encoded digital bit stream to a transmission system for transmission.

METHOD AND APPARATUS FOR COMMUNICATING DIGITAL DATA USING TRELLIS CODED QAM

Qam signal encoding/decoding system

METHOD AND APPARATUS FOR COMMUNICATIONS USING TURBO LIKE CODES

The present invention relates to methods, apparatuses, and systems for performing data encoding involving encoding data bits according to an outer convolutional code to produce outer encoded bits processing the outer encoded bits using an interleaver and a logical unit to produce intermediate bits, wherein the logical unit receives a first number of input bits and produces a second number of corresponding output bits, the second number being less than the first number, and wherein the logical unit takes each of the first number of input bits into account in producing the second number of output bits, encoding the intermediate bits according to an inner convolutional code to produce inner encoded bits, wherein the inner convolutional code is characterized by at least two states, and combining the data bits and the inner encoded bits to produce encoded outputs.

DIGITAL TELEVISION TRANSMITTER/RECEIVER AND METHOD OF PROCESSING DATA IN DIGITAL TELEVISION TRANSMITTER/RECEIVER

A digital television (DTV) transmitter and a method of processing known data in the DTV transmitter are disclosed. The method of processing known data in a digital television (DTV) transmitter includes generating a known data sequence, trellis-encoding the known data sequence, the trellis-encoded known data sequence having upper, middle, and lower bits, wherein at least one of the upper, middle, and lower bits has an m-sequence property, and mapping the trellis-encoded known data sequence into one of 2-level, 4-level, and 8-level data sequences, wherein the mapped data sequence has substantially an m-sequence property, wherein a data sequence has an m--sequence property when a peak value among auto-correlation values of the data sequence having a length of N is 1 and all the off-peak auto-correlation values are -1/N.

DECISION FEEDBACK EQUALIZER FOR DIGITAL TV AND METHOD THEREOF

... ²²The conventional decision feedback equalizer has a drawback that can't decide ²symbols correctly because a simple²slicer is used as a symbol detector. A decision feedback equalizer as a symbol ²detector uses a Trellis Coded Modulation (TCM)²decoder whose Trace Back depth is 1 (TBD=1), to thereby decide symbols ²correctly without decoding delay.² ...

METHOD OF PROCESSING DATA IN DIGITAL TELEVISION TRANSMITTER

A digital television (DTV) transmitter and a method of coding data in the DTV transmitter method are disclosed. A pre-processes enhanced data by coding the enhanced data for forward error correction (FEC) and expanding the FEC-coded enhanced data. A data formatter generates enhanced data packets including the pre-processed enhanced data and inserting known data to at least one of the enhanced data packets. A first multiplexer multiplexes main data packets with the enhanced data packets, and a data randomizer randomizes the multiplexed data packets. A Reed-Solomon (RS) encoder RS-codes the randomized data packets by adding first parity data, and a data interleaver interleaves the RS-coded data packets. A trellis encoder trellis-encodes the interleaved data packets, wherein the trellis encoder may be initialized when a known data sequence is inputted thereto.

VSB RECEPTION SYSTEM WITH ENHANCED SIGNAL DETECTION FOR PROCESSING SUPPLEMENTAL DATA

A digital television (DTV) receiver comprises a demodulator configured to demodulate a DTV signal containing first service data multiplexed with second service data. A first decoder is configured to decode the demodulated DTV signal for first error correction, in order to correct errors in the first and second service data that occurred during reception of the DTV signal. A data separator is configured to separate the first service data and the second service data from the decoded DTV signal and a second decoder is configured to further decode the separated first service data for second error correction in order to additionally correct errors in the first service data that occurred during the reception of the DTV signal.

METHOD AND APPARATUS FOR DETERMINING THE LOG-LIKELIHOOD RATIO WITH PRECODING

An apparatus and method for recovering data transmitted in a wireless communication system is claim. A plurality of signal points, the signal point comprising a plurality of modulation symbols from a plurality of coded bits, is received (604). A first subset of signal points for which a bit is equal to a first value and a second subset of signal points for which the bit is equal to a second value is determined (608). The first and second subset are signal points from an expanded signal constelation. The probability of that the bit is equal to the first value or the second value is determined as a function of the received signal point (612). A soft decision symbol may then be determined, based on the probability that the bit is equal to the first value or the second value. The soft decision symbols may be represented as log likelihood ratios (616).

MULTIDIMENSIONAL, CONVOLUTIONALLY CODED COMMUNICATION SYSTEMS

DEMODULATION APPARATUS AND METHOD IN A COMMUNICATION SYSTEM EMPLOYING 8-ARY PSK MODULATION

An 8-Ary PSK demodulation apparatus for receiving an input signal Rk(Xk, YK) comprised of a kth quadrature-phase component Yk and a kth in-phase component Xk, and for generating soft decision values .LAMBDA.(SK,0), .LAMBDA.(SK,1), and .LAMBDA.(SK,2). A calculator calculates Zk by subtracting a level │Y│ of the quadrature-phase signal component YK from a level │XK│ of the in-phase signal component Xk. A first selector selects the Zk, according to an MSB of the quadrature-phase signal component Yk. A second selector selects the Zk or the reverse ZK according to an MSB of the in-phase signal component Xk. A third selector selects an output of the second selector or a value "0" according to an MSB of the ZK.

FORWARD ERROR CORRECTION WITH OUTER MULTI-LEVEL CODE AND INNER CONTRAST CODE

In data communications, a suitably designed contrast coding scheme, comprising a process of contrast encoding (108) at a transmitter end (101) and a process of contrast decoding (120) at a receiver end (103), may be used to create contrast between the bit error rates 'BERs' experienced by different classes of bits. Contrast coding may be used to tune the BERs experienced by different subsets of bits, relative to each other, to better match a plurality of forward error correction 'FEC' schemes (104, 124) used for transmission of information bits (102), which may ultimately provide a communications system (100) having a higher noise tolerance, or greater data capacity, or smaller size, or lower heat.

COMMUNICATION SYSTEM

At the transmitter side, carrier waves are modulated according to an input signal for producing relevant signal points in a signal space diagram. The input signal is divided into, two, first and second, data streams. The signal points are divided into signal point groups to which data of the first data stream are assigned. Also, data of the second data stream are assigned to the signal points of each signal point group. A difference in the transmission error rate between first and second data streams is developed by shifting the signal points to other positions in the space diagram expressed at least in the polar coordinate system. At the receiver side, the first and/or second data streams can be reconstructed from a received signal. In TV broadcast service, a TV signal is divided by a transmitter into, low and high, frequency band components which are designated as a first and a second data streams respectively. Upon receiving the TV signal, a receiver can reproduce only the low frequency ...

METHOD AND APPARATUS FOR TRANSMISSION AND RECEPTION OF IN-BAND ON-CHANNEL RADIO SIGNALS INCLUDING COMPLEMENTARY LOW DENSITY PARITY CHECK CODING

A method of transmitting digital information includes: receiving a plurality of information bits representing audio information and/or data; encoding the information bits using complementary low density parity check coding to produce a composite codeword and a plurality of independently decodable semi-codewords; modulating at least one carrier signal with the forward error corrected bits; and transmitting the carrier signal(s). Transmitters that implement the method, and receivers that receive signals produced by the method, are also provided.

METHOD FOR THE BINARY CODING OF POINTS OF A CONSTEMETHOD FOR THE BINARY CODING OF POINTS OF A CONSTELLATION USED IN A MULTICARRIER MODULATION OF THE OLLATION USED IN A MULTICARRIER MODULATION OF THE OFDM TYPE FDM TYPE

... 2079999 9214316 PCTABS00130 La présente invention concerne un procédé de codage en binaire des N points d'une constellation correspondant aux positions discrètes en amplitude et en phase associées au codage de mots binaires dans le cas d'une modulation multiporteuse de type OFDM (Orthogonal Frequency Division Multiplexing en langue anglaise) d'un signal numérisé. Selon le procédé, deux points adjacents de la constellation correspondent à des mots binaires qui diffèrent l'un de l'autre d'au plus deux bits. La présente invention s'applique notamment à la télévision numérique.

INTERSYMBOL INTERFERENCE CHANNEL CODING SCHEME

Intersymbol interference and precoding loss are minimized by combining the preco ding and coding operations. An intersymbol interference coder uses a feedback loop to apply a dither sequence to a sequence of input signal points. The dither signal applied to each input signal point is a function of the previous signal points in the sequence. The i ntersymbol interference coder implements, for example, a trellis coding operation by select ing one of several different modulo operations to determine the magnitude of the dither sig nal, the selection being made in response to the current trellis state. The sequence of s ignal points output from the intersymbol interference coder generates a valid sequence of the trellis code input to the Viterbi decoder.

METHOD AND DEVICE FOR THE RECEPTION OF SIGNALS AFFECTED BY INTER-SYMBOL INTERFERENCE

For the reception of TCM modulated signals a receiver is used which comprises two cascaded Viterbi decoders (1, 2). The first decoder (1) operates according to a soft output Viterbi algorithm (SOVA), and its output comprises a hard decision on the transmitted symbols as well as a reliability parameter. The output of the first decoder (1), which is intended essentially totake into account the memory effects of the channel by contrasting the influence of inter-symbol interference, is fed, possibly after a de-interleavingaction, to the second Viterbi decoder (2) which carries out the actual decision.Preferred application to digital communication systems such as microwave radio links.

CODED MODULATION WITH UNEQUAL ERROR PROTECTION FORCODED MODULATION WITH UNEQUAL ERROR PROTECTION FOR FADING CHANNELS FADING CHANNELS

Information is transmitted in digital form over fading channels using DPSK coded modulation incorporating multi-level coding in order to provide unequal error protection for different classes of data such as generated by CELP or other speech encoders.

COMMUNICATION SYSTEM

CYCLIC TRELLIS CODED MODULATION

The use of certain 5-arylpyrazolo¢4,3-d!pyrimidin-7-ones, 6-arylpyrazolo¢3,4-d!pyrimidin-4-ones, 2-arylquinazolin-4-ones, 2-arylpurin-6-ones and 2arylpyrido¢3,2-d!pyrimidin-4-ones, or a pharmaceutically acceptable salt thereof, or a pharmaceutical composition containing either entity, for the manufacture of a medicament for the curative or prophylactic treatment of erectile dysfunction in a male animal, including man; a pharmaceutical composition for said treatment; and a method of said treatment of said animal with said pharmaceutical composition or with said either entity.

APPARATUS AND METHOD FOR DIGITAL DATA TRANSMISSION

A method and apparatus for carrying out synchronous co-division multiple access (SCDMA) communication of multiple channels of digital data over a shared transmission media (1162). The system includes modems at remote units (1164) and a central unit (1160) to receive time division multiplexed digital data arranged into timeslots or channels and uses orthogonal codes to encode each channel of multiple data and spread the energy of each channel data over a frame of data transmitted in a code domain. Frames are synchronized as between remote (1164) and central units (1160) using a ranging scheme which is also useful in any other system transmitting data by frames in a distributed system where synchronizing the frames as between all units regardless of differences in propagation delays is necessary. Each frame in the SCDMA modulation scheme includes a gap or guardband containing no other data.

INTERMEDIATE RATE APPLICATIONS OF PUNCTURED CONVOLUTIONAL CODES FOR 8PSK TRELLIS MODULATION OVER SATELLITE CHANNELS

A method and apparatus are provided for convolutionally encoding digital data with a rate 5/8 convolutional code. A standard rate 1/2 convolutional code is punctured to rate 5/8 using a puncture map of and octal generators 133, 171 wherein the constraint length K = 7. An incoming data stream is processed using the rate 5/8 code. In another embodiment, a rate 1/3 convolutional code is punctured to rate 5/8 using a puncture map of and octal generators 117, 135, 161 wherein the constraint length K = 7.

TRANSMITTER AND METHOD FOR GENERATING ADDITIONAL PARITY THEREOF

使用结构化奇偶校验矩阵的低密度奇偶校验码的编码

... 为对结构化低密度奇偶校验(LDPC)码进行编码的方法提供了方案。在编码处理期间访问存储表示低密度奇偶校验(LDPC)码的结构化奇偶校验矩阵的信息的存储器(1605，1607)。信息被组织成表格形成，其中每个行表示数值1在奇偶校验矩阵的列组的第一列内的存在。各个行对应于奇偶校验矩阵的各个列组，其中根据预定操作导出每个分组内的后续列。根据所存储的表示奇偶校验矩阵的信息输出LDPC编码信号。 ...

Link self adaptation method based on self adaptation coded modulation and automatic retransmission request

This invention discloses a link adaptive method based on adaptive code modulation and automatic retransmission request which is to select proper channel code modulation scheme and maximum retransmission times under said channel by determining downstream channel transmission conditions then to transmit the data packet to make judgement if the said data packet needs to be retransmitted according tothe mentioned information after receiving confirmation of the said data packet, if so, to judge if its retransmission times surpass the allowable maximum value at the present channel condition, if soto stop the operation, or reselect proper channel code modulation scheme and the maximum retransmission times, then to continue to transmit the data packet.

Procédé et dispositif de codage en treillis pour des taux d'émission fractionnaires

L'invention concerne les techniques de codage pour la transmission de signaux numériques. Une technique de codage conforme à l'invention, prévue pour l'utilisation avec des taux d'émission fractionnaires, permet d'utiliser de plus petites constellations, pour un nombre de dimensions donné, et procure donc une plus grande robustesse en présence de diverses perturbations, avec pratiquement aucune pénalité de retard au décodage. Un ou plusieurs des bits d'entrée sont codés dans un codeur en treillis 170 et les bits codés en treillis identifient l'un des sous-ensembles de la constellation de signal, tandis que les symboles particuliers qui sont sélectionnés pour l'émission à partir d'au moins deux sous-ensembles identifiés, sont choisis de façon interdépendante par les bits non codés en treillis. Application aux modems téléphoniques.

PULSE CODE MODULATION TRELLIS.

PULSE CODE MODULATION TRELLIS.

PULSE CODE MODULATION TRELLIS.

PULSE CODE MODULATION TRELLIS.

PULSE CODE MODULATION TRELLIS.

PULSE CODE MODULATION TRELLIS.

PULSE CODE MODULATION TRELLIS.

PULSE CODE MODULATION TRELLIS.

DATA TRANSMISSION AND RECEPTION METHOD FOR MOBILE COMMUNICATION SYSTEM

Trellis encoder and trellis encoding device comprising the trellis encoder

LDPC 코드워드 인터리빙 매핑 방법 및 디인터리빙 디매핑 방법

... 일종의 LDPC 코드워드 인터리빙 매핑 방법 및 디인터리빙 디매핑 방법으로서, LDPC 코드워드 중 검증 부분에 대해 제1차 비트 인터리빙을 수행하여 검증 비트 스트림을 얻는 절차; 당해 코드워드 중 정보 비트 부분과 검증 비트 스트림을 결합하여 제1차비트 인터리빙 후의 LDPC 코드워드를 얻는 절차; 제1차 비트 인터리빙 후의 코드워드를 예정된 길이로 연속된 복수의 비트 서브 블록으로 분리하고, 대응하는 비트 교환 패턴으로 상기 비트 서브 블록의 배열순서를 변화시켜 제2차 비트 인터리빙 후의 코드워드를 형성하는 절차; 제2차 비트 인터리빙 후의 코드워드를 2개 부분으로 분리하고, 이 2개 부분을 모두 열 순서로 기록하고 행 순서로 판독하여 제3차비트 인터리빙 후의 코드워드를 얻는 절차; 제3차 비트 인터리빙 후의 코드워드를 대응하는 성상도에 따라 성상도 매핑을 수행하여 심볼 스트림을 얻으며, 그 중, 상이한 코드 길이 및 코드 레이트의 LDPC 코드 테이블에 대하여 이론 분석 및 최적화를 통해 디자인한 비트 교환 패턴과 성상도를 이용하여 인터리빙 매핑 처리를 수행하는 절차를 포함하는 LDPC 코드워드의 인터리빙 매핑 방법. 본 기술방안은 수신단의 수신 임계값을 저하시킨다.

데이터 처리 장치, 및, 데이터 처리 방법

... 본 기술은, LDPC 부호를 사용한 데이터 전송에 있어서, 양호한 통신 품질을 확보할 수 있도록 하는 데이터 처리 장치, 및, 데이터 처리 방법에 관한 것이다. 그룹 와이즈 인터리브에서는, 부호 길이 N이 64800비트이며, 부호화율 r이 11/15인 LDPC 부호가, 360비트의 비트 그룹 단위로 인터리브된다. 그룹 와이즈 디인터리브에서는, 그룹 와이즈 인터리브 후의 LDPC 부호의 배열이 원래의 배열로 복귀된다. 본 기술은, 예를 들어, LDPC 부호를 사용한 데이터 전송 등을 행하는 경우에 적용할 수 있다.

터보 부호 복호화 장치

... 터보 코드의 디코딩을 고속으로 수행할 수 있는 디코딩 장치 및 방법이 개시된다. 개시된 디코딩 장치는 복수의 디코더를 동시에 사용하여 입력 시퀀스의 디코딩 속도를 향상시킬 수 있으며, 또한 시간이 많이 소모되는 연산의 일부를 생략하여 전체 연산 속도를 향상시키는 방법을 적용할 수 있다.

데이터 처리 장치, 및, 데이터 처리 방법

... 본 기술은, LDPC 부호를 사용한 데이터 전송에 있어서, 양호한 통신 품질을 확보할 수 있도록 하는 데이터 처리 장치, 및, 데이터 처리 방법에 관한 것이다. 그룹 와이즈 인터리브에서는, 부호 길이 N이 64800비트이며, 부호화율 r이 13/15인 LDPC 부호가, 360비트의 비트 그룹 단위로 인터리브된다. 그룹 와이즈 디인터리브에서는, 그룹 와이즈 인터리브 후의 LDPC 부호의 배열이 원래의 배열로 복귀된다. 본 기술은, 예를 들어, LDPC 부호를 사용한 데이터 전송 등을 행하는 경우에 적용할 수 있다.

데이터 처리 장치 및 데이터 처리 방법

... 본 기술은, 양호한 에러율의 LDPC 부호를 제공할 수 있도록 하는 데이터 처리 장치 및 데이터 처리 방법에 관한 것이다. LDPC 인코더는, 부호 길이가 16200비트이고, 부호화율이 10/15인 LDPC 부호에 의한 부호화를 행한다. LDPC 부호는, 정보 비트와 패리티 비트를 포함하고, 검사 행렬 H는, LDPC 부호의 정보 비트에 대응하는 정보 행렬부와 패리티 비트에 대응하는 패리티 행렬부로 구성된다. 검사 행렬 H의 정보 행렬부는, 그 정보 행렬부의 1의 요소의 위치를 360열마다 나타내는 검사 행렬 초기값 테이블에 의해 표시된다. 본 기술은, LDPC 부호화 및 LDPC 복호를 행하는 경우에 적용할 수 있다.

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

METHOD AND SYSTEM FOR GENERATING LOW DENSITY PARITY CHECK CODES

PURPOSE: A method and a system for generating low density parity check codes are provided to enable a very simple encoding method without requiring a generator matrix of a code by restricting a certain part of a parity check matrix to be lower triangular. CONSTITUTION: A digital communications system(100) includes a transmitter(101) that generates signal waveforms across a communication channel(103) to a receiver(105). In the digital communications system, the transmitter has a message source that produces a discrete set of possible messages. Each of the possible messages has a corresponding signal waveform. These signal waveforms are attenuated, or otherwise altered, by communications channel. To combat the noise channel, LDPC codes are utilized. The transmitter generates, using a relatively simple encoding technique, LDPC codes based on parity check matrices to communicate with the receiver. © KIPO 2004 ...

OFDM TRANSMITTER CAPABLE OF IMPROVING TRANSMISSION EFFICIENCY OF DIGITAL BROADCASTING SIGNAL AND SIGNAL PROCESSING METHOD THEREOF

PURPOSE: An OFDM transmitter capable of improving transmission efficiency of a digital broadcasting signal and a signal processing method of the transmitter are provided to prevent a digital broadcasting signal from being distorted by an analog broadcasting signal. CONSTITUTION: An OFDM transmitter includes a forward error correction unit(100), a null signal generator(200), a frame format unit(400), and an inverse discrete Fourier transformer(500). The forward error correction unit outputs a coded OFDM signal for correcting an error generated while an OFDM signal is transmitted. The null signal generator generates a null signal. The frame format unit inserts the null signal into frequency bands occupied by analog broadcasting signal. The inverse discrete Fourier transformer inverse-discrete-Fourier-transforms the coded OFDM signal into which the null signal has been inserted. The OFDM transmitter further includes a multiplexer(300) for selectively outputting the null signal and the coded ...

System and method for joint voice and data transmission

A method for multiplexing voice and data communication using a communications network is presented. In the method, at least one voice bit from a voice bit stream is retrieved, and at least one data bit from at least one data bit stream is retrieved. When the voice bit stream is not in a discontinuous transmission (DTX) period, the at least one voice bit and the at least one data bit are used to generate a modulated symbol. The method includes transmitting the modulated symbol using the communications network.

Techniques To Control Power Consumption In An Iterative Decoder By Control Of Node Configurations

A method for controlling power consumption of an iterative decoder based on one or more criteria is described. The method may include progressively enabling and disabling nodes of the iterative decoder to perform iterative decoding on a demodulated signal to provide a decoded signal with minimal variation of a supply voltage.

Wireless communication device and wireless communication method

A data alignment method capable of preventing degradation in demodulation performance due to variation in signal qualities when a data signal to which a Turbo code is applied is transmitted simultaneously from a plurality of cells. The method divides signal components to be used for data alignment into resources common to all the cells and resources dependent on the cells and transmits encoded and rate-matched data with the first half thereof aligned to the resources common to all the cells and the second half thereof aligned to the resources dependent on the cells.

Apparatus and method for transmitting and receiving data in a communication or broadcasting system using linear block code

Provided is a method for transmitting data in a communication or broadcasting system using a linear block code by generating a codeword by encoding input information data bits, interleaving the codeword; outputting modulation signal-constituting bits by bit-mapping the interleaved codeword using a bit-mapping table predetermined depending on a modulation scheme and a coding rate, outputting a modulation signal by modulating the modulation signal-constituting bits and transmitting the modulation signal via a transmit antenna.

Modulation method and device implementing a differential modulation, corresponding demodulation method and device, signal and computer software products

A method and apparatus are provided for modulating a binary source sequence including of a plurality of source words to generate modulated symbols. The method implements error-correction encoding of the plurality of source words, implementing one or more encoding modules, each implementing a separate error-correction code to generate a plurality of code words, the source words being encoded in series. The code words are interlaced to generate an interlaced sequence. The interlaced sequence is differentially modulated to generate modulated symbols. Each code word is broken down into at least one group with a number of bits equal to the base-2 logarithm of a number of states of a modulation implemented by the step of differentially modulating. The interlacing step distributes the groups such that two adjacent groups in the interlaced sequence belong to separate code words.

Method for scheduling distributed virtual resource blocks

A method for transmitting downlink data using resource blocks at a base station in a wireless mobile communication system includes transmitting downlink data mapped to physical resource blocks (PRBs) to a user equipment, wherein indexes of virtual resource blocks (VRBs) are mapped to indexes of the PRBs for a first slot and a second slot of a subframe, and the indexes of the PRBs for the second slot are shifted with respect to the indexes of the PRBs for the first slot based on a predetermined gap, and wherein a predetermined offset is applied to an index of a PRB when the index of the PRB is equal to or greater than a predetermined threshold.

Apparatus and method for wireless communication

In a wireless communication method, a first wireless communication apparatus transmits through a first wireless resource to a second wireless communication apparatus a first signal generated from a second signal for use in processing performed by the second wireless communication apparatus and a third signal for use in error checking of the second signal. The second wireless communication apparatus detects a second wireless resource to be used in the processing on the basis of the first signal, and performs the processing by using the second signal and the detected second wireless resource. For the detection, a section of the first signal corresponding to the second wireless resource is scrambled, or the first signal is scrambled with a scrambling sequence corresponding to the second wireless resource, or the bit order in at least part of the first signal is changed in a manner corresponding to the second wireless resource.

Soft-decision non-binary ldpc coding for ultra-long-haul optical transoceanic transmissions

Methods and systems for soft-decision non-binary low-density parity-check (LDPC) coding for ultra-long-haul optical transoceanic transmissions are provided. A receiver includes one or more maximum a posteriori (MAP) equalizers configured to decode one or more symbols of an encoded input stream to provide one or more symbol log-likelihood ratios (LLRs). One or more LLR estimators are configured to estimate the log-likelihood ratios of the one or more symbol LLRs to provide one or more bit LLRs. One or more non-binary LDPC decoders are configured to decode the input stream using the one or more bit LLRs to recover an original input stream.

Readdressing decoder for quasi-cyclic low-density parity-check and method thereof

A readdressing decoder for QC-LDPC decoding including a memory, a controller and parallel processors is provided. The memory stores a QC-LDPC matrix including sub-matrices respectively addressed with a corresponding address. The controller readdresses each of the sub-matrices into divided matrices and defines each of the divided matrices into a first address group and a second address group. The controller further respectively transmits the divided matrices of the first address group and the second address group to the parallel processors to perform correction algorithm.

Modulator and modulation method

A transmitter apparatus wherein a relatively simple structure is used to suppress burst errors without changing the block sizes of encoded blocks even when the number of modulation multi-values is increased. An encoding part subjects transport data to a block encoding process to form block encoded data. A modulating part modulates the block encoded data to form data symbols; and an arranging (interleaving) part arranges (interleaves) the block encoded data in such a manner that the intra-block encoded data of the encoded blocks, which include their respective single different data symbol, get together, and then supplies the arranged (interleaved) block encoded data to the modulating part. In this way, there can be provided a transmitter apparatus wherein a relatively simple structure is used to suppress burst errors without changing the block sizes of encoded blocks even when the number of modulation multi-values is increased.

Four-dimensional non-binary ldpc-coded modulation schemes for ultra high-speed optical fiber communication

Systems and methods are disclosed for communicating signals, by receiving a K-symbol-long input block from a 2 m -ary source channel; encoding the input block into a 2 m -ary non-binary low-density parity-check (LDPC) codeword of length N; and mapping each 2 m -ary symbol to a point in a signal constellation comprised of 2 m points, wherein a non-binary LDPC code is used as the component code for forward error correction in a coded modulation scheme capable of achieving optical fiber communication at rates beyond 100 Gb/s.

Method of error floor mitigation in low-density parity-check codes

A digital communication decoding method for low-density parity-check coded messages. The decoding method decodes the low-density parity-check coded messages within a bipartite graph having check nodes and variable nodes. Messages from check nodes are partially hard limited, so that every message which would otherwise have a magnitude at or above a certain level is re-assigned to a maximum magnitude.

Systems and Methods for Non-Binary Decoding

Various embodiments of the present invention provide systems and methods for data processing. A data processing circuit is disclosed that includes: a data detector circuit, a first symbol constrained arrangement circuit, and a second symbol constrained arrangement circuit. The data detector circuit is operable to apply a data detection algorithm to a combination of a first input data set and a decoded data set to yield a detected output that includes a number of non-binary symbols. The first symbol constrained arrangement circuit is operable to receive the detected output and to re-arrange the detected output in accordance with a first arrangement algorithm to yield a re-arranged output. The bits for at least one non-binary symbol from the detected output are maintained together in the re-arranged output. The second symbol constrained arrangement circuit is operable to receive a second input data set and to re-arrange the second data input in accordance with a second arrangement algorithm to yield the decoded data set. The bits for at least one non-binary symbol from the second input data set are maintained together in the decoded data set output.

Method for transmitting downlink control channel in a mobile communication system and a method for mapping the control channel to physical resource using block interleaver in a mobile communication system

A method for transmitting a downlink control channel in a mobile communication system and a method for mapping the control channel to physical resources using a block interleaver are provided. In order to transmit a downlink control channel in a mobile communication system, information bits are modulated to generate one or more modulation symbols according to a specific modulation scheme, the modulation symbols are interleaved using a block interleaver, and the interleaved modulated symbols are mapped to resource elements allocated for transmission of at least one control channel in a subframe, thereby transmitting the at least one control channel.

Communications system using adaptive orthogonal frequency division multiplexing

In a communications device a grouping unit uses channel state information when mapping data bits to a plurality of different constellation groups. Each constellation group is assigned to another modulation scheme. A plurality of sub-carriers is assigned to none or one of the constellation groups and each modulation uses another one of the constellation groups. The communications device includes at least one scalable interleaver unit, wherein each interleaver unit is assigned to one of the constellation groups and interleaves the assignment of data bits mapped to each constellation group and the sub-carriers that carry a symbol information derived from the data bits. As an example, the interleaver unit performs frequency interleaving by interleaving, at constellation level, the sub-carriers that carry the symbol information.

Two Low Complexity Decoding Algorithms for LDPC Codes

In the present invention, two improved variants of the reliability-based iterative majority-logic decoding algorithm for regular low-density parity-check (LDPC) codes are presented. The new algorithms are obtained by introducing a different reliability measure for each check-sum of the parity-check matrix, and taking it into account in the computation of the extrinsic information that is used to update the reliability measure of each received bit in each iteration. In contrast to the first algorithm, the second algorithm includes check reliability that changes at each iteration. For the tested random and structured LDPC codes, both algorithms, while requiring very little additional computational complexities, achieve a considerable error performance gain over the standard one. More importantly, for short and medium block length LDPC codes of relatively large column weight, both algorithms outperform or perform just as well as the iterative decoding based on belief propagation (IDBP) with less decoding complexity.

Virtualized optical transport network systems and methods

The present disclosure provides an optical transceiver, method of mapping, and method of management utilizing a plurality of Optical Channel Transport Unit layer k (OTUk) links to form an aggregate signal, such as, for example, 10 OTU2s to provide a single 100 Gigabit Ethernet (100 GbE) signal. Specifically, the present invention enables use of existing circuitry and methods at lower speed signals, e.g. 10 G, to support higher speed aggregate signals, e.g. 100 G. The present invention may be utilized to support carrier-grade OTN applications with optical transceivers such as, for example, pluggable optical transceivers. In an exemplary embodiment, the present invention includes a method which receives a plurality of signals, frames each of the plurality of signals into an OTUk frame, and manages/monitors each of the plurality of signals in an OTUk frame in the aggregate.

Multiple transmit antenna interleaver design

An arrangement of interleavers allocates bits from an input symbol across sub-symbols transmitted via sub-carriers of multiple orthogonal frequency division multiplex (OFDM) carriers. The input bits are allocated in a fashion to provide separation across subcarriers, and rotation of sub-symbols across the OFDM carriers provides additional robustness in the present of signal path impairments.

Interleaving, modulation, and layer mapping in an lte physical control channel

In described embodiments, a physical downlink control channel of a device operating in accordance with a 3GPP LTE standard is processed to provide interleaving, modulation and multi-layer mapping and pre-coding. A Resource Element Group interleaver applies interleaving to an input signal representing an input bitstream, and a modulator modulates the input signal. After interleaving and modulating the signal, a multi-layer mapper and pre-coder layer-maps and pre-codes the interleaved and modulated input signal into a plurality of different layers.

Downlink indicator channel processing in a wireless system base station

A transmitter comprises indicator channel processing circuitry configured to process indicator channel codewords for transmission in a base station of a wireless system. The indicator channel processing circuitry performs a plurality of processing operations on the indicator channel codewords in a specified processing sequence, with the plurality of processing operations comprising at least modulation, scrambling, spreading and combining. In the specified processing sequence, the scrambling operation is performed for at least a given one of the indicator channel codewords prior to the modulation and spreading operations for that codeword or subsequent to the combining operation for that codeword. For example, the specified processing sequence may comprise the scrambling, modulation, spreading and combining operations performed in that order for at least the given codeword, or the modulation, spreading, combining and scrambling operations performed in that order for at least the given codeword.

Soft decision value generation circuit

A soft decision value generation circuit capable of reducing amount of calculation and hardware scale for generating a soft decision value. The soft decision value generation circuit includes: a phase rotation unit rotating phases of received symbols after coherent detection; addition units calculating, by using the phase-rotated received symbols, absolute values of soft decision values for soft decision value candidates restricted in advance; minimum value selection units selecting minimum values out of the absolute values of the soft decision values; sign reflection units reflecting, based on the phases of the received symbols after the phase rotation, sign information to the minimum values; and soft decision value correction units multiplying outputs of the sign reflection units by a coefficient depending on a noise variance value and an amplitude value of a modulation symbol.

Reduced complexity non-binary ldpc decoding algorithm

A custom decoding algorithm is introduced, in connection with a corresponding decoding structure, to resolve many complexity and large memory requirements of known decoders. A system. A variable node forms a confidence vector of four components, one component for each state of a memory cell, and passes the current primary component (e.g., the largest) to one or more check nodes. The check nodes calculate a temporary component and corresponding index based on all components received from the variable nodes, which they pass back to the respective variable nodes. The variable node updates the confidence vector based on the temporary nodes received from respective check nodes, and determines the correct state for corresponding memory cell based on which component in the confidence vector is currently the primary component.

Interleaving method and deinterleaving method

An interleaving method performed by a transmitter for a communication system with quasi-cyclic low-density parity-check codes, spatial multiplexing, and T transmit antennas is used for applying permutation to N cyclic blocks of a codeword in order to map bits of the permutated cyclic blocks onto T constellation words constituting multiple spatial-multiplexing blocks from the codeword. Each cyclic block consists of Q bits.

System and Method Including Modified Bit-Interleaved Coded Modulation

A system and method with a modified bit-interleaved coded modulation with iterative decoding (BICM-ID). Coded and interleaved bits are combined and coded with a second FEC code that is then mapped to a modulation format. The second FEC code may be a single parity check (SPC) and the scheme may be referred to as a SPC-BICM-ID scheme.

Efficient control signaling over shared communication channels with wide dynamic range

Embodiments provide methods, apparatuses, and systems for efficient control signaling over shared communication channels with wide dynamic range. Some embodiments includes a gateway configured to encode and to transmit multiple physical layer headers, including a first physical layer header and a second physical layer header. The first physical layer header may span a first length and represent a first modcode; the second physical layer header may span a second length and represent a second modcode. The second length may be longer than the first length. Embodiments may include multiple terminals in wireless communication with the gateway via satellite, including a first terminal configured to decode the first physical layer header and to determine the first modcode. Embodiments may include a second terminal configured to decode the second physical layer header and determine the second modcode.

Discrete multi-tone systems for half-duplex ip links

A DMT system for a half-duplex two-way link carries Internet protocol encoded video stream on a coaxial cable that also carries a baseband rendition of the same video stream. A plurality of downlink symbols modulated on a subband of subcarriers in a downlink signal are decoded. The symbols may carry data encoded on a subband using a constellation of QAM symbols assigned to the subband. Other subbands may be associated with different QAM constellations. Lower-order constellations of QAM symbols may be assigned to subbands that include higher-frequency subcarriers and higher-order constellations of QAM symbols may be assigned to subbands that include lower-frequency subcarriers. A block error correction decoder may be synchronized based on an identification of the first constellation of QAM symbols and information identifying boundaries between the plurality of downlink symbols.

Methods, systems, and computer readable media for integrated sub-block interleaving and rate matching

Methods, systems, and computer readable media for fast, reduced memory and integrated sub-block interleaving and rate matching are disclosed. According to one aspect, the subject matter described herein includes a system for integrated sub-block interleaving and rate matching, which includes a buffer memory for storing sub-block data that has been encoded according to a channel encoding algorithm and a rate matching module for reading the sub-block data from the buffer memory using a sequence of addresses according to an interleaving algorithm, such that data is transferred from the buffer memory to the rate matching module in an order that emulates the order that the data would be produced by the interleaving algorithm or in the order that the data would be produced by the interleaving algorithm as modified by a rate matching algorithm.

Apparatuses and methods for combining error coding and modulation schemes

Methods and apparatuses for combining error coding and modulation schemes are described herein. One or more methods include encoding data using linear error correcting code, modulating the encoded data, writing the modulated data to memory, and decoding the written data using a Viterbi algorithm and a linear error correcting code decoder.

Data processing device and data processing method

A data processing device and a data processing method that can readily process control data having its PAPR improved. In a transmission device, a padder pads control data necessary for demodulation with zeros as dummy data, and a scrambler scrambles the padded control data (post-padding control data). A replacement unit replaces scrambled dummy data in the scrambled post-padding control data with the dummy data, and a BCH encoder and an LDPC encoder perform BCH encoding and LDPC encoding as error correction encoding on the replacement data obtained through the replacement. A shortening unit performs shortening by deleting the dummy data contained in the LDPC code and puncturing the parity bits of the LDPC code. The device can be applied in cases where control data is subjected to error correction encoding and is then transmitted, for example.

Encoder, decoder, transmitting apparatus, and receiving apparatus

There is provided an encoder that provides a termination sequence with a simple structure for LDPC-CC encoding and reduces an amount of the termination sequence transmitted to a transmission line. The LDPC-CC encoder connects a first encoder to a second encoder to perform encoding and thereby carry out LDPC-CC encoding, the first encoder performing encoding based on an partial parity check matrix for information bits obtained by extracting a sequence corresponding to the information bits in a parity check matrix and the second encoder performing encoding based on a partial parity check matrix for parity bits obtained by extracting a sequence corresponding to the parity bits in the parity check matrix. A termination sequence generator generates a termination sequence including the same number of bits as the memory length of the first encoder and provides the generated termination sequence as an input sequence.

Receiver, receiving method and computer program

Deinterleaving and cyclic deshifting of the PDCCH are processed at the same time as the demodulation for de-mapping. As such, the receiving device has: a deinterleaver unit which uses a row counter and a column counter to calculate a location number in a deinterleave matrix; a cyclic shift amount calculation unit which calculates the cyclic shift amount applied to demodulation data, before that demodulation data is acquired; a counter initial value calculation unit which calculates the initial values of the row counter and the column counter from the calculated cyclic shift amount and sends the results to the deinterleaver unit; and an address changing unit which changes the address of the destination to which the demodulation data is to be written to the location number calculated by the deinterleaver unit.

Method and system for hybrid automatic repeat request using multiple receiver-coordinated transmitters

A method and a receiving device, the method receiving an indication of pending data from an access network, the pending data including a sequence number for every unit of the pending data; and sending transmission instructions to a first transmitter within the access network, the transmission instructions including a range of sequence numbers desired by the receiving device and an error correction and coding scheme to be used by the first transmitter. Further, a receiving device having a processor; and a communications subsystem, wherein the processor and communications subsystem cooperate to receive a first stream from a first transmitter; receive a second stream from a second transmitter; and soft combine the first stream and the second stream at the receiving device.

Variable Interleave Data Transmission

In cable modem termination systems (CMTS) and other information transmission systems, a method for changing the interleave depth associated with each data stream is provided. This may be done dynamically, and for any subset of downstream devices such as modems. The interleave depth may be set on an individual device level. Embodiments may decrease data receiving latency on devices that do not suffer from error rates, such as caused by burst noise, while maintaining throughput on devices with high error rates. 1. A method , comprising:receiving a first map indicative of a plurality of first timeslots based on a plurality of interleave depths associated with a plurality of data streams destined for a plurality of devices, wherein the plurality of interleave depths includes a first interleave depth and a second interleave depth different from the first interleave depth;modifying one or more of the plurality of first timeslots to form a plurality of second time slots;constructing a second map indicative of the plurality of second timeslots; andtransmitting the second map to at least one of the plurality of devices.2. The method of claim 1 , further comprising:determining that one of the plurality of interleave depths is changed,wherein the modifying comprises modifying the one or more of the plurality of first timeslots to form the plurality of second timeslots based on the determining.3. The method of claim 1 , further comprising:receiving, from the at least one of the plurality of devices, an error count,wherein the modifying comprises modifying the one or more of the plurality of first timeslots to form the plurality of second timeslots based on the receiving the error count.4. The method of claim 3 , further comprising:determining that the error count exceeds a threshold value,wherein the modifying comprises modifying the one or more of the plurality of first timeslots to form the plurality of second timeslots based on the determining that the error count exceeds ...

METHOD FOR SIGNALING INFORAMTION BY MODIFYING MODULATION CONSTELLATIONS

Methods and systems for communicating in a wireless network may distinguish different types of packet structures by modifying the phase of a modulation constellation, such as a binary phase shift keying (BPSK) constellation, in a signal field. Receiving devices may identify the type of packet structure associated with a transmission or whether the signal field is present by the phase of the modulation constellation used for mapping for the signal field. In one embodiment, the phase of the modulation constellation may be determined by examining the energy of the I and Q components after Fast Fourier Transform. Various specific embodiments and variations are also disclosed. 125-. (canceled)26. A method of decoding encoded information by a wireless communication device , comprising:receiving a data unit including encoded information comprising one or more variable length low density parity check (LDPC) codewords from a network device;decoding a length of the encoded information from a header of the data unit; determining, based at least in part on the decoded length, the length of each of the one or more LDPC codewords; anddecoding the one or more LDPC codewords.27. The method of claim 26 , wherein decoding the one or more LDPC codewords comprises claim 26 , for each of the one or more LDPC codewords:determining a plurality of variable node values; anddetermining a plurality of check node values, corresponding to parity check relationships, based on the variable node values and a parity check matrix.28. The method of claim 26 , wherein decoding the one or more LDPC codewords comprises using a Bahl claim 26 , Cocke claim 26 , Jelinek and Raviv (BCJR) algorithm.29. The method of claim 26 , wherein decoding the one or more LDPC codewords comprises using a min-sum algorithm.30. The method of claim 26 , wherein decoding the one or more LDPC codewords comprises using a plurality of decoding iterations.31. The method of claim 30 , wherein the plurality of decoding iterations ...

Receiver and receiving method

According to an embodiment, a receiver includes a generation unit and a scheduler. The generation unit generates a convergence indicator for evaluating a convergence status of the iterative decoding process based on reliability information. The scheduler controls execution of local iteration includes the iterative decoding process terminates and controls execution of global iteration includes alternation between a symbol de-mapping process and an iterative decoding process, based on the convergence indicator.

SYMBOL FLIPPING DECODERS OF NON-BINARY LOW-DENSITY PARITY CHECK (LDPC) CODES

Systems and methods are provided for decoding data. A decoder retrieves data related to a symbol and identifies a plurality of candidate values for the symbol. The decoder determines a distance between each of the plurality of candidate values and a reference value associated with the symbol to obtain a plurality of distances, and the decoder determines whether to update a value of the symbol based at least in part on the plurality of distances. 1. A method for decoding data , the method comprising:retrieving data related to a symbol;identifying a plurality of candidate values for the symbol;determining a distance between each of the plurality of candidate values and a reference value associated with the symbol to obtain a plurality of distances; anddetermining whether to update a value of the symbol based at least in part on the plurality of distances.2. The method of claim 1 , wherein the plurality of distances form a distance distribution claim 1 , wherein the distance distribution includes a number of check nodes associated with at least one distance in the plurality of distances.3. The method of claim 1 , wherein determining whether to update a value of the symbol is further based at least in part on a comparison between a threshold and a number of check nodes associated with a first distance in the plurality of distances.4. The method of claim 3 , further comprising modifying the threshold at a further iteration of the decoding.5. The method of claim 1 , wherein determining whether to update the value of the symbol comprises:identifying a plurality of thresholds, wherein each threshold in the plurality of thresholds corresponds to a distance in the plurality of distances, and wherein the threshold is modified as the corresponding distance is modified; andcomparing each threshold in the plurality of thresholds to the corresponding distance in the plurality of distances.6. The method of claim 1 , further comprising updating the value of the symbol when a number ...

Apparatus and method for low density parity check (ldpc) encoding

Provided is a low density parity check (LDPC) encoding apparatus and method that may store M registers each including N bits, obtain N×M parity bits by performing a partial parallel operation an N×M number of times with respect to the M registers, and mutually invert subsequent N parity bits periodically, based on previous parity bits for each Nth parity bit of the N×M parity bits, respectively.

DATA PROCESSING APPARATUS AND METHOD

A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. 1. (canceled)2. A data processing apparatus configured to map input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol into an output symbol stream , the data processing apparatus comprising:an interleaver configured to read-into a memory the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals, and to read-out of the memory the data symbols for the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved onto the sub-carrier signals, and a linear feedback shift register including a predetermined number of register stages and being configured to generate a pseudo-random bit sequence in accordance with a generator polynomial,', 'a permutation circuit configured to receive the content of the shift register stages and to permute the order of the bits present in the register stages in accordance with a permutation code to form an address, and', 'a control unit configured in combination with an address check circuit to re-generate an address when a generated ...

OUTPUT SIGNAL GENERATING METHOD, DECODED DATA GENERATING METHOD, OUTPUT SIGNAL GENERATING APPARATUS, AND DECODED DATA GENERATING APPARATUS

A transmitter apparatus wherein a simple structure is used to successfully suppress the degradation of error rate performance that otherwise would be caused by fading or the like. There are included encoding parts that encode transport data; a mapping part that performs such a mapping that encoded data sequentially formed by the encoding parts are not successively included in the same symbol, thereby forming data symbols; and a symbol interleaver that interleaves the data symbols. In this way, a low computational complexity can be used to perform an interleaving process equivalent to a bit interleaving process to effectively improve the reception quality at a receiving end. 1. An output signal generating method comprising:generating, by a processor, a plurality of encoded data sequences configured by a predetermined number of bits, by encoding transmit data configured by a plurality of bits;generating one symbol sequence by one modulating process, selected from a plurality of modulating processes, on the encoded data sequences; andoutputting one baseband signal sequence generated by using an OFDM scheme, for the one symbol sequence, wherein:the one modulating process generates the one symbol sequence configured by QPSK symbols generated by using a QPSK scheme or 16QAM symbols generated by using a 16QAM scheme;the one symbol sequence generated by using the QPSK scheme is configured with first two encoded data sequences in the plurality of encoded data sequences;the one symbol sequence generated by using the 16QAM scheme is configured with the first two encoded data sequences and second two encoded data sequences in the plurality of encoded data sequences;a number of the 16QAM symbols is the same as a number of the QPSK symbols in the one symbol sequence;specific two bits extracted from a plurality of bits configuring the QPSK symbols and the 16QAM symbols in the one symbol sequence are bits belonging to the first two encoded data sequences;a number of the encoded ...

Receiver

Provided is a BICM-ID technique which suppresses deterioration of decoding characteristics and reduces a calculation amount. A receiver includes a demodulator, a deinterleaver, a decoder, and an interleaver. The demodulator outputs first extrinsic information by using a received signal encoded and interleaved and a priori information. The deinterleaver performs deinterleave processing on the first extrinsic information and outputs second extrinsic information. The decoder outputs third extrinsic information by using the second extrinsic information. The interleaver performs interleave processing on the third extrinsic information and outputs fourth extrinsic information. In the receiver that performs iterative decoding processing by using the fourth extrinsic information as the a priori information, the demodulator includes a generator, a received signal point candidate narrowing-down unit, and a likelihood calculation unit. The generator generates a plurality of received signal point candidates. The received signal point candidate narrowing-down unit narrows received signal point candidates down to those to be used to create the first extrinsic information based on a magnitude of the a priori information and a distance between the plurality of the received signal point candidates and the received signal. The likelihood calculation unit creates the first extrinsic information based on the narrowed-down received signal point candidates, the a priori information, and the received signal. 1. A receiver , comprising:a demodulator configured to receive a signal encoded and interleaved on a transmission side, create first extrinsic information by using the received signal and a priori information, and output the first extrinsic information;a deinterleaver configured to perform deinterleave processing inverse to the interleave processing on the first extrinsic information and output second extrinsic information;a decoder configured to create third extrinsic information by ...

DATA PROCESSING METHOD, PRECODING METHOD, AND COMMUNICATION DEVICE

An encoder outputs a first bit sequence having N bits. A mapper generates a first complex signal s and a second complex signal s with use of bit sequence having X+Y bits included in an input second bit sequence, where X indicates the number of bits used to generate the first complex signal s, and Y indicates the number of bits used to generate the second complex signal s. A bit length adjuster is provided after the encoder, and performs bit length adjustment on the first bit sequence such that the second bit sequence has a bit length that is a multiple of X+Y, and outputs the first bit sequence after the bit length adjustment as the second bit sequence. As a result, a problem between a codeword length of a block code and the number of bits necessary to perform mapping by a set of modulation schemes is solved. 1. A transmission device comprising:error correction encoding circuitry which, in operation, generates a first encoded data sequence from an input data sequence using a first coding rate and a first code length, and generates a second encoded data sequence from a control information sequence using a second coding rate and a second code length;mapping circuitry which, in operation, generates a first modulation symbol sequence by applying a first mapping pattern of a first modulation scheme to the first encoded data sequence, and generates a second modulation symbol sequence by applying a second mapping pattern of a second modulation scheme to the second encoded data sequence; andtransmitting circuitry which, in operation, transmits the first modulation symbol sequence and the second modulation symbol sequence, whereinthe first mapping pattern and the second mapping pattern are different from each other,the first code length and the second code length are different from each other,the first modulation scheme and the second modulation scheme are the same in the number of transmission bits per symbol, andthe first coding rate and the second coding rate are the same ...

POLAR CODE RATE MATCHING METHOD AND RATE MATCHING APPARATUS

A Polar code rate matching method and a rate matching apparatus are disclosed. The method includes: dividing a system Polar code output by a Polar code encoder into system bits and parity bits; interleaving the system bits to obtain a first group of interleaved bits, and interleaving the parity bits to obtain a second group of interleaved bits; and determining a rate-matched output sequence based on the first group of interleaved bits and the second group of interleaved bits. System bits and parity bits are separately interleaved, to obtain a rate-matched output sequence, so that a sequence structure after interleaving is more random, which can reduce an FER, thereby improving HARQ performance, and ensuring reliability of data transmission. 1. A polar code rate matching method , comprising:dividing a system polar code output by a polar code encoder into system bits and parity bits;interleaving the system bits to obtain a first group of interleaved bits, and interleaving the parity bits to obtain a second group of interleaved bits; anddetermining a rate-matched output sequence based on the first group of interleaved bits and the second group of interleaved bits.2. The method according to claim 1 , wherein the interleaving the system bits to obtain a first group of interleaved bits comprises:performing quadratic interleaving on the system bits to obtain the first group of interleaved bits.3. The method according to claim 1 , wherein the interleaving the parity bits to obtain a second group of interleaved bits comprises:performing quadratic interleaving on the parity bits to obtain the second group of interleaved bits.4. The method according to claim 1 , wherein the determining a rate-matched output sequence based on the first group of interleaved bits and the second group of interleaved bits comprises:sequentially writing the first group of interleaved bits and the second group of interleaved bits to a circular buffer;determining a start position of the rate-matched ...

Method, Apparatus and System for Transmitting Information Bits

A method, an apparatus, and a system for transmitting information bits, where the method for transmitting information bits includes: dividing the information bits to be transmitted into at least two groups; encoding the information bits to be transmitted in each group; modulating the coded bits obtained by the encoding to obtain modulation symbols, in which each modulation symbol is obtained by using the modulation of the coded bits in the same group; and mapping and transmitting the modulation symbols. In this way, the receiving end easily reduces the algorithm complexity, thereby ensuring the performance of the receiving end. 1. A method for transmitting information bits , comprising:dividing information bits to be transmitted into a first group and a second group;encoding the information bits in the first group to obtain a first group of coded bits and the information bits in the second group to obtain a second group of coded bits;modulating the coded bits of first group to obtain modulation symbols of first group, and modulating the coded bits of second group to obtain modulation symbols of second group;alternately ordering one modulation symbol in first group and one modulation symbol in second group to obtain a modulation symbol sequence; andmapping and transmitting the modulation symbols.2. The method according to claim 1 , wherein the modulating the coded bits of first group to obtain modulation symbols of first group and modulating the coded bits of second group to obtain modulation symbols of second group respectively according to a predetermined modulation manner.3. The method according to claim 2 , wherein the predetermined modulation manner comprises one of: Quaternary Phase Shift Keying (QPSK) modulation and 16-Quadrature Amplitude Modulation (16QAM).4. The method according to claim 1 , wherein the information bits to be transmitted comprise at least one of the following: a Channel Quality Indicator (CQI) claim 1 , a Precoding Matrix Index (PMI) claim ...

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 4/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). 2. The LDPC encoding method of claim 1 , wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 17280 claim 1 , a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 1800 claim 1 , and a second parity part corresponding to an identity matrix included in the PCM and having a length of 45720.3. The LDPC encoding method of claim 2 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part claim 2 , that is claim 2 , 17280 claim 2 , by a circulant permutation matrix (CPM) size corresponding to the PCM claim 2 , that is claim 2 , 360 claim 2 , and a value obtained by dividing a length of the first parity part claim 2 , that is claim 2 , 1800 claim 2 , by the CPM size.4. The LDPC encoding method of claim 3 , wherein the accumulation is performed at parity bit addresses that are updated using the sequence.5. The LDPC encoding method of claim 4 , wherein the accumulation is performed while the rows of the sequence are being repeatedly changed by the CPM size of the PCM. This application is a continuation of U.S. patent application Ser. No. 14/496,654, filed on Sep. 25, 2014, which claims the benefit of Korean Patent Application Nos. 10-2014-0106180 and 10-2014-0120014, filed Aug. 14, 2014 and Sep. 11, 2014, respectively, which are hereby incorporated by reference herein in their entirety.The present ...

TRANSMITTING APPARATUS AND MAPPING METHOD THEREOF

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme. 2. The method as claimed in claim 1 , wherein the interleaving comprises:splitting the codeword into a plurality of bit groups; andinterleaving the plurality of bit group.3. The method as claimed in claim 1 , wherein the mapping comprises:demultiplexing the bits of the interleaved codeword into parallel streams to generate cells; andmapping the cells onto the constellation points. This application is a Continuation of application Ser. No. 14/716,222 filed May 19, 2015, the disclosure of which is incorporated herein by reference in its entirety.Apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to transmitting and receiving date using broadcasting, more particularly, to the design of non-uniform constellations used in a Bit Interleaved Coded Modulation (BICM) mapping bits at an output of an encoder and interleaver to complex constellations.The current broadcasting systems consistent with the Digital Video Broadcasting Second Generation Terrestrial (DVB-T2) use a Bit Interleaved and Coded Modulation (BICM) chain in order to encode bits to be transmitted. The BICM chain includes a channel encoder like a Low Density Parity Check (LDPC) encoder followed by a Bit Interleaver and a Quadrature Amplitude Modulation (QAM) mapper. The role of the QAM mapper is to map different bits output from the channel encoder and interleaved using the Bit Interleaver to QAM cells. Each cell represents a complex number having real and imaginary part. The QAM mapper groups M bits into one cell. Each cell is ...

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 3/15 AND QUADRATURE PHASE SHIFT KEYING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation. 1. A bit-interleaved coded modulation (BICM) reception method , comprising:performing demodulation corresponding to quadrature phase shift keying (QPSK);performing group-unit deinterleaving on interleaved values, the interleaved values generated after the demodulation; andrestoring information bits by low-density parity check (LDPC) decoding deinterleaved values generated based on the group-unit deinterleaving, the deinterleaved values corresponding to a LDPC codeword having a length of 16200 and a code rate of 3/15,wherein the group-unit deinterleaving is performed on a group basis, the size of the group corresponding to a parallel factor of the LDPC codeword.2. The BICM reception method of claim 1 , wherein the group-unit deinterleaving corresponds to a reverse process of interleaving performed by using a permutation order claim 1 , andthe permutation order corresponds to an interleaving sequence represented by the following interleaving sequence:{15 22 34 19 7 17 28 43 30 32 14 1 11 0 3 9 10 38 24 4 23 18 27 39 29 33 8 2 40 21 20 36 44 12 37 13 35 6 31 26 16 25 42 5 41}.3. The BICM reception method of claim 2 , wherein the parallel factor is 360 claim 2 , and the group includes 360 values.5. An apparatus for transmitting a broadcast signal claim 2 , comprising:a low-density parity check (LDPC) encoder configured to encode a low-density parity check (LDPC ...

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 5/15 AND 4096-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 5/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping. 1. A bit-interleaved coded modulation (BICM) reception device , comprising:a demodulator configured to perform demodulation corresponding to 4096-symbol mapping;a bit deinterleaver configured to perform group-unit deinterleaving on interleaved values, the interleaved values generated after the demodulation; anda decoder configured to restore information bits by LDPC-decoding deinterleaved values generated based on the group-unit deinterleaving, the deinterleaved values corresponding to a LDPC codeword having a length of 64800 and a code rate of 5/15,wherein the group-unit deinterleaving is performed on a group basis, the size of the group corresponding to a parallel factor of the LDPC codeword.2. The BICM reception device of claim 1 , wherein the group-unit deinterleaving corresponds to a reverse process of interleaving performed by using permutation order claim 1 , and {'br': None, 'interleaving sequence={146 89 57 16 164 138 91 78 90 66 122 12 9 157 14 68 112 128 74 45 28 87 158 56 61 168 18 161 95 99 139 22 65 130 166 118 150 49 142 44 36 1 121 6 46 29 88 47 0 58 105 43 80 64 107 21 55 151 8 145 163 7 98 123 17 11 153 136 52 3 13 34 160 102 125 114 152 84 32 97 33 60 62 79 37 129 38 165 71 75 59 144 127 132 104 53 162 103 120 54 155 116 48 77 76 73 113 119 179 177 41 19 92 109 31 143 178 108 39 140 106 40 5 25 81 176 101 124 126 72 111 4 173 156 134 86 174 2 170 35 175 137 15 24 69 ...

SYSTEMS, METHODS AND APPARATUSES FOR MODULATION-AGNOSTIC UNITARY BRAID DIVISION MULTIPLEXING SIGNAL TRANSFORMATION

A method includes selecting a block size, via a processor of a communications system, and identifying a set of constellation points of a constellation diagram, based on a received set of bits and the constellation diagram. The constellation diagram is associated with a modulation scheme. A set of symbol blocks, based on the set of constellation points, is generated. Each symbol block from the set of symbol blocks has a size equal to the block size and includes a subset of constellation points from the set of constellation points. A unitary braid division multiplexing (UBDM) transformation is applied to each symbol block from the set of symbol blocks to produce a set of complex numbers. The set of complex numbers is then sent via the processor. 1. A method , comprising:selecting, via a processor of a communications system, a block size;identifying, via the processor, a set of constellation points associated with a constellation diagram, based on a plurality of bits, the constellation diagram associated with a modulation scheme;generating, via the processor, a plurality of symbol blocks based on the set of constellation points, each symbol block from the plurality of symbol blocks having a size equal to the block size and including a subset of constellation points from the set of constellation points;applying, via the processor, a unitary braid division multiplexing (UBDM) transformation to each symbol block from the plurality of symbol blocks to produce a plurality of complex numbers; andsending, via the processor, the plurality of complex numbers.2. The method of claim 1 , wherein the communications system is configured to perform at least one of Quadrature Amplitude Modulation (QAM) claim 1 , Amplitude Phase Shift Keying (APSK) modulation claim 1 , or Orthogonal Frequency-Division Multiplexing.3. The method of claim 1 , wherein the communications system is a wireless communication system.4. The method of claim 1 , wherein the communications system is a wired ...

DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD

A data processing apparatus and a data processing method which enable provision of an LDPC code that achieves good error-rate performance. An LDPC encoding unit performs encoding using an LDPC code having a code length of 64800 bits and a code rate of 24/30, 25/30, 26/30, 27/30, 28/30, or 29/30. The LDPC code includes information bits and parity bits, and a parity check matrix H is composed of an information matrix portion corresponding to the information bits of the LDPC code, and a parity matrix portion corresponding to the parity bits. The information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table that shows positions of elements of 1 in the information matrix portion in units of 360 columns. The present technology apparatus and method may be applied to LDPC encoding and LDPC decoding. 1an encoding unit configured to encode information bits into an LDPC (Low Density Parity Check) code having a code length of 64800 bits and a code rate of 24/30 on the basis of a parity check matrix of the LDPC code, whereinthe LDPC code includes information bits and parity bits,the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,the information matrix portion is represented by a parity check matrix initial value table, andthe parity check matrix initial value table is a table showing positions of elements of 1 in the information matrix portion in units of 360 columns, including{'b': 1504', '2103', '2621', '2840', '3869', '4594', '5246', '6314', '7327', '7364', '10425', '11934', '12898', '12954}{'b': 27', '1903', '3923', '4513', '7812', '8098', '8428', '9789', '10519', '11345', '12032', '12157', '12573', '12930}{'b': 17', '191', '660', '2451', '2475', '2976', '3398', '3616', '5769', '6724', '8641', '10046', '11552', '12842}{'b': 13', '1366', '4993', '6468', '7689', '8563', '9131', '10012', '10914', '11574', '11837', ' ...

TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol. 2. The receiving apparatus of claim 1 , wherein each of the plurality of groups comprises 360 values.3. The receiving apparatus of claim 1 , wherein π(j) is determined based on at least one of the code length claim 1 , a modulation method and the code rate. This is a continuation of U.S. patent application Ser. No. 15/435,042, filed Feb. 16, 2017, which is a continuation of U.S. patent application Ser. No. 15/130,204, filed on Apr. 15, 2016, issued as U.S. Pat. No. 9,692,454 on Jun. 27, 2017, which is a continuation of U.S. patent application Ser. No. 14/625,862, filed Feb. 19, 2015, issued as U.S. Pat. No. 9,602,137 on Mar. 21, 2017, which claims priority from U.S. Provisional Application No. 61/941,676 filed on Feb. 19, 2014, U.S. Provisional Application No. 62/001,170 filed on May 21, 2014, and Korean Patent Application No. 10-2015-0000671 filed on Jan. 5, 2015. The entire disclosures of the prior applications are considered part of the disclosure of this continuation application, and are hereby incorporated by reference.Apparatuses and methods consistent with exemplary embodiments relate to a transmitting apparatus and an interleaving method thereof, and more particularly, to a transmitting apparatus which processes data and transmits the data, and an interleaving method thereof.In the 21st century information-oriented society, broadcasting communication services are moving into the era of digitalization, ...

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 2/15 AND 16-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping. 1. A BICM reception device , comprising:a demodulator configured to perform demodulation corresponding to 16-symbol mapping;a bit deinterleaver configured to perform group-unit deinterleaving on interleaved values, the interleaved values generated after the demodulation; anda decoder configured to restore information bits by LDPC-decoding deinterleaved values generated based on the group-unit deinterleaving, the deinterleaved values corresponding to a LDPC codeword having a length of 16200 and a code rate of 2/15,wherein the group-unit deinterleaving is performed on a group basis, the size of the group corresponding to a parallel factor of the LDPC codeword.2. The BICM reception device of claim 1 , wherein the group-unit deinterleaving corresponds to interleaving performed by using permutation order claim 1 , and {'br': None, 'interleaving sequence={5 33 18 8 29 10 21 14 30 26 11 23 27 4 7 6 24 44 38 31 34 43 13 0 15 42 17 2 20 12 40 39 35 32 1 3 41 37 9 25 19 22 16 28 36}.'}, 'the permutation order corresponds to an interleaving sequence represented by the following'}3. The BICM reception device of claim 2 , wherein the 16-symbol mapping is a Non-Uniform Constellation (NUC) symbol mapping which corresponds to 16 constellations.4. The BICM reception device of claim 2 , wherein the parallel factor is 360 claim 2 , and the group includes 360 values.5. The BICM reception device of claim 4 ...

INTERLEAVING AND MAPPING METHOD AND DEINTERLEAVING AND DEMAPPING METHOD FOR LDPC CODEWORD

An interleaving and mapping method and a deinterleaving and demapping method for an LDPC codeword are provided. The interleaving and mapping method comprises: performing first bit interleaving on a parity bits part of the LDPC codeword to obtain interleaved parity bits; splicing an information bit part of the codeword and the interleaved parity bits into a codeword after the first bit interleaving; dividing the codeword after the first bit interleaving into multiple consecutive bit subblocks in a predetermined length, and changing the order of the bit subblocks according to a corresponding permutation order (bit-swapping pattern) to form a codeword after second bit interleaving; dividing the codeword after the second bit interleaving into two parts, and writing the two parts into storage space in a column order respectively and reading the two parts from the storage space in a row order respectively to obtain a codeword after third bit interleaving. 1. A transmitter , comprising:an interleaver performing a first bit interleaving on parity bits in an LDPC codeword to obtain interleaved parity bits, wherein the parity bits contain a first parity bits part and a second parity bits part, and the first bit interleaving is performed on the first parity bits part and the second parity bits part respectively;the interleaver splicing the information bits part in the LDPC codeword and the interleaved parity bits into an LDPC codeword having undergone the first bit interleaving;the interleaver dividing the LDPC codeword having undergone the first bit interleaving into multiple consecutive bit subblocks in a predetermined length, and changing the order of the bit subblocks according to a corresponding bit interleaving pattern to form an LDPC codeword having undergone second bit interleaving; andthe interleaver dividing the LDPC codeword having undergone the second bit interleaving into two parts, writing the first part into a storage space in order and reading the first part ...

INTERLEAVING AND MAPPING METHOD AND DEINTERLEAVING AND DEMAPPING METHOD FOR LDPC CODEWORD

An interleaving and mapping method and a deinterleaving and demapping method for an LDPC codeword are provided. The interleaving and mapping method comprises: performing first bit interleaving on a parity bits part of the LDPC codeword to obtain interleaved parity bits; splicing an information bit part of the codeword and the interleaved parity bits into a codeword after the first bit interleaving; dividing the codeword after the first bit interleaving into multiple consecutive bit subblocks in a predetermined length, and changing the order of the bit subblocks according to a corresponding permutation order (bit-swapping pattern) to form a codeword after second bit interleaving; dividing the codeword after the second bit interleaving into two parts, and writing the two parts into storage space in a column order respectively and reading the two parts from the storage space in a row order respectively to obtain a codeword after third bit interleaving. 1. A transmitter , comprising:a constellation mapper performing, according to a corresponding constellation diagram, constellation mapping on an LDPC codeword which is bit interleaved according to a bit interleaving pattern,wherein for LDPC codewords with different code lengths, code rates and LDPC code matrices tables, such that the capacity of bit interleaved coding and modulation is maximized, matched constellation diagrams and bit interleaving patterns are designed by means of theoretical analysis and optimization.2. The transmitter of claim 1 , whereinthe constellation diagram is distributed non-uniformly in a two-dimensional manner in a single quadrant, and distributed symmetrically in four quadrants.4. The transmitter of claim 3 , whereinthe constellation diagram is applicable to 16-QAM non-uniform constellation mapping,the constellation diagram is applicable to an LDPC codeword with a code length of 16200 bits or 64800 bits, andthe constellation diagram is applicable to an LDPC codeword with a code rate of 4/15 ...

Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 2/15 and 256-symbol mapping, and bit interleaving method using same

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

OAM BASED PHYSICAL LAYER SECURITY USING HYBRID FREE-SPACE OPTICAL-TERAHERTZ TECHNOLOGY

Aspects of the present disclosure describe systems, methods, and structures for physical layer security using hybrid free-space optical and terahertz transmission technologies that advantageously overcome atmospheric characteristics that infirmed the prior art. 1. A communications system employing a hybrid free-space optical (FSO) terahertz (THz) physical layer security scheme comprising: a binary-to-nonbinary converter that converts an input binary sequence;', 'a non-binary LDPC encoder that encodes the nonbinary symbols and provides parity symbols to a mapper/modulator;', 'a multidimensional mapper that maps the nonbinary symbols; and', 'a free space optical and THz transmitter for transmitting the symbols via a FSO and THz channel(s) respectively;, 'a transmitter including a FSO and a THz receiver for receiving transmissions on the FSO and THz channel(s) respectively;', 'a nonbinary a posteriori probability (APP) demapper which receives any data from the FSO and THz receivers and the mapped/modulated parity symbols from the mapper/demodulator, said APP calculates symbol log-likelihood ratios (LLRs); and', 'a nonbinary LDPC decoder that receives the LLRs and outputs any corrected symbols transmitted., 'a receiver including2. The system of wherein the system employs N orbital angular momentum (OAM) modes in an optical domain and N OAM modes in a THz domain.3. The system of wherein nonbinary LDPC codes are chosen such that any information symbols remain intact while generalized parity-symbols are algebraically related to the information symbols.4. The system of wherein the information symbols are transmitted over the FSO and THz channels while the generalized parity symbols are transmitted over classical channel(s).5. The system of wherein multidimensional signaling is used exclusively over the FSO channels and THz channels.6. The system of wherein operating wavelength of the FSO is one selected from the group consisting of: 1550 nm claim 5 , 2 μm claim 5 , 3.85 μm ...

TRANSMITTING APPARATUS AND NON-UNIFORM CONSTELLATION MAPPING METHOD THEREOF

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme. 2. The apparatus as claimed in claim 1 , wherein the constellation points as defined in the list comprises constellation points in one quadrant claim 1 , andwherein constellation points in remaining quadrants are obtained by indicating each constellation point a which is defined in the list as a*, −a*, and −a, respectively, * indicating complex conjugation. This is a continuation of U.S. application Ser. No. 15/726,806 filed Oct. 6, 2017, which is a continuation of U.S. application Ser. No. 14/715,817 filed on May 19, 2015, now U.S. Pat. No. 9,847,851, the disclosures of which is incorporated herein by reference in its entirety.Apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to transmitting and receiving date using broadcasting, more particularly, to the design of non-uniform constellations used in a Bit Interleaved Coded Modulation (BICM) mapping bits at an output of an encoder and interleaver to complex constellations.The current broadcasting systems consistent with the Digital Video Broadcasting Second Generation Terrestrial (DVB-T2) use a Bit Interleaved and Coded Modulation (BICM) chain in order to encode bits to be transmitted. The BICM chain includes a channel encoder like a Low Density Parity Check (LDPC) encoder followed by a Bit Interleaver and a Quadrature Amplitude Modulation (QAM) mapper. The role of the QAM mapper is to map different bits output from the channel encoder and interleaved using the Bit Interleaver to QAM cells. Each cell represents a complex number having real ...

DEVICE FOR GENERATING BROADCAST SIGNAL FRAME AND METHOD FOR GENERATING BROADCAST SIGNAL FRAME CORRESPONDING TO TIME INTERLEAVER FOR SUPPORTING PLURALITY OF OPERATION MODES

An apparatus and method for generating a broadcast signal frame corresponding to a time interleaver supporting a plurality of operation modes are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling time interleaver information corresponding to the time interleaver, the time interleaver uses one of time interleaver groups, and the time interleaver performs the interleaving by using one of a plurality of operation modes. 1. An apparatus for generating broadcast signal frame , comprising:a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels;a power normalizer configured to reduce power of the multiplexed signal to a power level corresponding to the core layer signal;a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; anda frame builder configured to generate a broadcast signal frame including a preamble for signaling time interleaver information corresponding to the time interleaver,wherein the time interleaver performs the interleaving by using one of a plurality of operation modes.2. The apparatus of claim 1 , wherein the operations modes include a first mode corresponding to no time interleaving claim 1 , a second mode for performing a Convolutional ...

METHOD FOR TRANSMITTING AND RECEIVING PHYSICAL SIGNALS AND/OR CHANNELS IN WIRELESS COMMUNICATION SYSTEM AND APPARATUS THEREFOR

The present specification provides a method for transmitting and receiving physical signals and/or channels in a wireless communication system and an apparatus therefor. Specifically, a method for a terminal to receive a wireless signal and/or a channel in a wireless communication system may comprise the steps of: receiving, from a base station, downlink control information (DCI) for scheduling for one or more wireless signals and/or channels; and cross-receiving the one or more wireless signals and/or channels on a sub-block basis from the base station on the basis of the DCI. 1. A method for receiving a signal by a user equipment (UE) in a wireless communication system , the method comprising:receiving, from a base station, single downlink control information (DCI) scheduling a plurality of physical downlink shared channels (PDSCHs), wherein each of the plurality of PDSCHs is repeatedly transmitted within a block of time, the block of time comprising a plurality of sub-blocks in a time domain; andreceiving, based on the DCI and from the base station, the plurality of PDSCHs by interleaving the sub-blocks of the plurality of PDSCHs in the time domain.2. The method of claim 1 , wherein the single DCI comprises information about a number of the plurality of sub-blocks claim 1 , and each sub-block has a fixed-length claim 1 , andwherein a total transmission length of the plurality of PDSCHs is determined as a sum of lengths of the sub-blocks of the plurality of PDSCHs.3. The method of claim 1 , further comprising:receiving, from the base station, information indicating a pattern for the interleaved and repeated reception,wherein the interleaved and repeated reception is performed based on the indicated pattern.4. The method of claim 3 , wherein the information indicating the pattern is configured in a bitmap form.5. The method of claim 3 , wherein the information indicating the pattern includes information about a number of consecutive sub-blocks.6. The method of ...

Method and Apparatus for Downlink Control Information Communication and Interpretation

Methods and apparatus are provided for wireless communication in which a downlink control information (DCI) is transmitted in a physical downlink control channel (PDCCH) in a first bandwidth part (BWP). A UE is responsible for determining a starting resource block (RB) for a data transmission allocated by the DCI based on a value of a frequency domain resource allocation field in the DCI, a reference RB, and a reference size of a second BWP. The data transmission can then be transmitted, in the case of, for example, PUSCH, by a UE or received, in the case of, for example, PDSCH. 1. A method for wireless communication , the method comprising:receiving, by a user equipment (UE), a downlink control information (DCI) in a second control resource set (CORESET), the DCI comprising a frequency domain resource allocation field for indicating frequency resources allocated to a data transmission; andreceiving, by the UE, the data transmission in a frequency resource based on a value of the frequency domain resource allocation field, a number of resource blocks (RBs) of a first CORESET, and a reference RB defined by a lowest-numbered physical resource block (PRB) in the second CORESET.2. The method of claim 1 , wherein the receiving the data transmission comprises receiving the data transmission in the frequency resource based on a starting RB and a length of contiguously allocated RBs claim 1 , the starting RB based on: the value of the frequency domain resource allocation field in the DCI claim 1 , the reference RB claim 1 , and the number of RBs of the first CORESET claim 1 , and the length of contiguously allocated RBs based on: the value of the frequency domain resource allocation field in the DCI and the number of RBs of the first CORESET.3. The method of claim 2 , further comprising claim 2 , determining claim 2 , by the UE claim 2 , that:the DCI is a fallback DCI for the data transmission with a non-interleaved virtual resource block (VRB)-to-PRB mapping;the fallback ...

DATA PROCESSING METHOD, PRECODING METHOD, AND COMMUNICATION DEVICE

An encoder outputs a first bit sequence having N bits. A mapper generates a first complex signal s and a second complex signal s with use of bit sequence having X+Y bits included in an input second bit sequence, where X indicates the number of bits used to generate the first complex signal s, and Y indicates the number of bits used to generate the second complex signal s. A bit length adjuster is provided after the encoder, and performs bit length adjustment on the first bit sequence such that the second bit sequence has a bit length that is a multiple of X+Y, and outputs the first bit sequence after the bit length adjustment as the second bit sequence. As a result, a problem between a codeword length of a block code and the number of bits necessary to perform mapping by a set of modulation schemes is solved. 1. A data processing scheme comprising:an encoding step of outputting a first bit sequence that is an N-bit codeword from a K-bit information bit sequence;{'b': 1', '2', '1', '2, 'a mapping step of generating a first complex signal s and a second complex signal s with use of a bit sequence having X+Y bits included in an input second bit sequence, where X indicates the number of bits used to generate the first complex signal s, and Y indicates the number of bits used to generate the second complex signal s; and'}a bit length adjustment step of, after the encoding step and before the mapping step, performing bit length adjustment on the first bit sequence such that the second bit sequence has a bit length that is a multiple of X+Y, and outputting the first bit sequence after the bit length adjustment as the second bit sequence.2. The data processing scheme of claim 1 , whereinthe encoding step performs accumulate processing on a bit sequence of a parity portion of N−K bits that is generated by performing a systematic LDPC coding, andthe bit length adjustment step generates an adjustment bit sequence by performing at least one repetition of a bit value of a ...

APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING SIGNAL IN BROADCASTING AND COMMUNICATION SYSTEMS

A method for transmitting a signal in broadcasting and communication systems is provided. The method includes dividing source data into two or more streams and respectively coding the two or more streams through coders, selecting two or more symbols from among coded codeword symbols, mapping the selected two or more symbols to one signal constellation for modulation, and transmitting a modulated signal, in which the codeword symbols include one or more non-binary codewords, and a product of orders of finite fields on which the codeword symbols are defined is equal to an order of the signal constellation. 1. A method for transmitting a signal in broadcasting and communication systems , the method comprising:dividing source data into two or more streams and respectively coding the two or more streams to codeword symbols;selecting two or more symbols from among the coded codeword symbols;modulating the selected two or more symbols by mapping the selected two or more symbols to one signal constellation for modulation; andtransmitting a modulated signal,wherein the codeword symbols comprise one or more non-binary codewords, and a product of orders of finite fields on which the codeword symbols are defined is equal to an order of the signal constellation.2. The method of claim 1 , further comprising:interleaving the coded codeword symbols after the coding of the two or more streams,wherein the interleaving of the coded codeword symbols is performed symbol-by-symbol.3. A method for receiving a signal in broadcasting and communication systems claim 1 , the method comprising:demodulating a received signal to calculate finite-field-symbol-wise Likelihood Ratio (LR) values or signal-constellation-specific reception probabilities; anddecoding the calculated values or probabilities to obtain codewords comprising at least one non-binary codeword,wherein a product of orders of finite fields on which codeword symbols are defined is equal to an order of the signal constellation.4. ...

Resource Mapping Method, Resource Determination Method, Network Side Device And User Equipment

The present disclosure provides a resource mapping method, a resource determination method, a network side device and a UE., The resource mapping method for the network side device includes: determining resource mapping configuration information about a PDCCH; and mapping each VRB to a corresponding PRB in accordance with the resource mapping configuration information, and transmitting the resource mapping configuration information to a UE, so as to enable the UE to acquire a bandwidth to which VRBs map in a distributed manner in accordance with one or more configuration parameters in the resource mapping configuration information. 1. A resource mapping method for a network side device , comprising:determining resource mapping configuration information about a Physical Downlink Control Channel (PDCCH); andmapping each Virtual Resource Block (VRB) to a corresponding Physical Resource Block (PRB) in accordance with the resource mapping configuration information, and transmitting the resource mapping configuration information to a User Equipment (UE), so as to enable the UE to acquire a bandwidth to which VRBs map in a distributed manner in accordance with one or more configuration parameters in the resource mapping configuration information,{'sub': 'VRB', 'sup': 'DL', 'wherein the one or more configuration parameters in the resource mapping configuration information comprise at least one of the quantity Nof the VRBs available for a downlink bandwidth, a frequency gap of PRBs to which adjacent VRBs map, a transmission bandwidth where the UE is located, and a bandwidth occupied by scheduled data.'}2. The resource mapping method according to claim 1 , wherein the resource mapping configuration information comprises mapping functions from serial numbers of the VRBs to serial numbers of the PRBs or serial numbers of the mapping functions claim 1 , independent variables of each mapping function at least comprise the serial numbers of the VRBs and serial numbers of slots ...

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 16200 AND CODE RATE OF 2/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). 2. The transmitter of claim 1 , wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 2160 claim 1 , a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 3240 claim 1 , and a second parity part corresponding to an identity matrix included in the PCM and having a length of 10800.3. The transmitter of claim 2 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part claim 2 , that is claim 2 , 2160 claim 2 , by a circulant permutation matrix (CPM) size corresponding to the PCM claim 2 , that is claim 2 , 360 claim 2 , and a value obtained by dividing a length of the first parity part claim 2 , that is claim 2 , 3240 claim 2 , by the CPM size.4. The transmitter of claim 3 , wherein the accumulation is performed at parity bit addresses that are updated using the sequence.5. The transmitter of claim 4 , wherein the accumulation is performed while the rows of the sequence are being repeatedly changed by the CPM size of the PCM. This application is a continuation of U.S. application Ser. No. 15/018,762, filed Feb. 8, 2016, which is divisional of U.S. application Ser. No. 14/496,304, filed Sep. 25, 2014, which claims the benefit of Korean Patent Application Nos. 10-2014-0106173 and 10-2014-0120008, filed Aug. 14, 2014 and Sep. 11, 2014, respectively, which are hereby incorporated by reference herein in ...

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 2/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). 2. The LDPC encoding method of claim 1 , wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 8640 claim 1 , a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 1800 claim 1 , and a second parity part corresponding to an identity matrix included in the PCM and having a length of 54360.3. The LDPC encoding method of claim 2 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part claim 2 , that is claim 2 , 8640 claim 2 , by a circulant permutation matrix (CPM) size corresponding to the PCM claim 2 , that is claim 2 , 360 claim 2 , and a value obtained by dividing a length of the first parity part claim 2 , that is claim 2 , 1800 claim 2 , by the CPM size.4. The LDPC encoding method of claim 3 , wherein the accumulation is performed at parity bit addresses that are updated using the sequence.5. The LDPC encoding method of claim 4 , wherein the accumulation is performed while the rows of the sequence are being repeatedly changed by the CPM size of the PCM. This application is a continuation of U.S. patent application Ser. No. 14/496,457, filed on Sep. 25, 2014, which claims the benefit of Korean Patent Application Nos. 10-2014-0106178 and 10-2014-0120012, filed Aug. 14, 2014 and Sep. 11, 2014, respectively, which are hereby incorporated by reference herein in their entirety.1. Technical FieldThe ...

Low density parity check encoder having length of 64800 and code rate of 5/15, and low density parity check encoding method using the same

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 16200 AND CODE RATE OF 5/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). 2. The LDPC encoding method of claim 1 , wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 5400 claim 1 , a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 720 claim 1 , and a second parity part corresponding to an identity matrix included in the PCM and having a length of 10080.3. The LDPC encoding method of claim 2 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part claim 2 , that is claim 2 , 5400 claim 2 , by a circulant permutation matrix (CPM) size corresponding to the PCM claim 2 , that is claim 2 , 360 claim 2 , and a value obtained by dividing a length of the first parity part claim 2 , that is claim 2 , 720 claim 2 , by the CPM size.4. The LDPC encoding method of claim 3 , wherein the accumulation is performed at parity bit addresses that are updated using the sequence.5. The LDPC encoding method of claim 4 , wherein the accumulation is performed while the rows of the sequence are being repeatedly changed by the CPM size of the PCM. This application is a continuation of U.S. application Ser. No. 14/496,432, filed Sep. 25, 2014, which claims the benefit of Korean Patent Application Nos. 10-2014-0106176 and 10-2014-0120011, filed Aug. 14, 2014 and Sep. 11, 2014, respectively, which are hereby incorporated by reference herein in their entirety.1. Technical FieldThe present ...

POLAR CODE RATE MATCHING METHOD AND APPARATUS

A polar code rate matching method and apparatus are provided. The method includes: performing bit reversal order interleaving on a polar code output by a polar code encoder, to obtain interleaved bits; and determining, based the interleaved bits, a rate-matched output sequence. By performing bit reversal order interleaving on a polar code, a rate-matched output sequence is obtained, which can reduce an FER, thereby improving HARQ performance and ensuring reliability of data transmission. 1. A polar polar code rate matching method , comprising:performing bit reversal order (BRO) interleaving on a polar code output by a polar code encoder, to obtain interleaved bits; anddetermining, based on the interleaved bits, a rate-matched output sequence.2. The method according to claim 1 , wherein performing BRO interleaving on a polar code output by a polar code encoder claim 1 , to obtain interleaved bits comprises:{'sup': th', 'th, 'sub': M', 'M, 'performing BRO interleaving on the polar code by using a BRO interleaver, to obtain the interleaved bits, wherein a length of input bits of the BRO interleaver is N, and the BRO interleaver maps the iinput bit onto the Π(i+Δ mod N)output bit, wherein i=0, 1, . . . , and N−1, Δ is an offset, Π(i) is obtained from BRO(j), BRO(j) indicates that a bit reversal order operation is performed on an index j, and M is a positive integer.'}3. The method according to claim 2 , wherein:{'sub': B', 'M, 'Π(i) is defined as follows: Π(j)=BRO(j), wherein'}{'sub': 'B', 'j=0, 1, . . . , and B−1, and B indicates a size of Π(j).'}4. The method according to claim 2 , wherein:{'sub': 'B', 'claim-text': {'br': None, 'sub': B', 'M, 'i': j', 'j', 'J', 'j/J, 'sup': 'M', 'Π()=2(mod )+BRO(└┘), wherein'}, 'Π(i) is obtained by means of pruning by Π(j); and'}{'sub': 'B', 'j=0, 1, . . . , B−1, B indicates a size of the interleaver Π(j), B=M×J, and J is a positive integer.'}5. The method according to claim 1 , wherein determining claim 1 , based on the interleaved ...

POLAR CODE RATE MATCHING METHOD AND POLAR CODE RATE MATCHING APPARATUS

Embodiments of the present invention provide a polar code rate matching method and a polar code rate matching apparatus. The method includes: performing matrix-based BRO interleaving on a non-systematic polar code output by a polar code encoder, to obtain interleaved bits; and determining, based on the interleaved bits, a rate-matched output sequence. According to the embodiments of the present invention, matrix-based BRO interleaving is performed on a non-systematic polar code, to obtain a rate-matched output sequence, so that a sequence structure after interleaving is more random, which can reduce an FER, thereby improving HARQ performance and ensuring reliability of data transmission. 1. A polar polar code rate matching method , comprising:performing matrix-based bit reversal order (BRO) interleaving on a non-systematic polar code output by a polar code encoder, to obtain interleaved bits; anddetermining, based on the interleaved bits, a rate-matched output sequence.2. The method according to claim 1 , wherein performing matrix-based BRO interleaving on the non-systematic polar code output by the polar code encoder claim 1 , to obtain interleaved bits comprises:{'b': 1', '2', '1', '2, 'writing bits of the non-systematic polar code by row to form a first matrix of M rows×M columns wherein M and M are positive integers;'}{'b': '2', 'performing a first substitution operation on a column of the first matrix to obtain a second matrix, wherein the first substitution operation is a BRO operation with a size of M;'}{'b': '1', 'performing a second substitution operation on a row of the second matrix to obtain a third matrix, wherein the second substitution operation is a BRO operation with a size of M; and'}reading bits according to a column of the third matrix, and using the bits as the interleaved bits.3. The method according to claim 1 , wherein performing matrix-based BRO interleaving on a polar code output by a polar code encoder claim 1 , to obtain interleaved bits ...

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 4/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping. 1. A bit interleaving method , comprising:storing a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15;generating an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword; andoutputting the interleaved codeword, {'br': None, 'i': Y', '=X', 'j≦N, 'sub': j', 'π(j)', 'group, '0≦'}, 'wherein the interleaving is performed using the following equation using permutation order{'sub': π(j)', 'j, 'where λis a π(j)th bit group, Yis an interleaved j-th bit group, and π(j) is a permutation order for bit group-based interleaving.'}2. The bit interleaving method of claim 1 , wherein the permutation order corresponds to an interleaving sequence represented by the following{'br': None, 'interleaving sequence={41 34 32 37 5 8 13 15 30 31 22 25 42 20 23 17 1 40 44 12 6 43 7 29 33 16 11 0 35 4 14 28 21 3 24 19 18 36 10 38 26 2 39 27 9},'}wherein the interleaving sequence is for a case where 64-symbol mapping is employed.3. The bit interleaving method of claim 2 , wherein the 64-symbol mapping is a Non-Uniform Constellation (NUC) symbol mapping which corresponds to 64 constellations.4. The bit interleaving method of claim 3 , wherein the parallel factor is 360 claim 3 , and the bit group includes 360 bits. This application is a continuation of U.S. application Ser. ...

PARALLEL BIT INTERLEAVER

A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each imade up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section. 1. A transmitting method for transmitting a codeword generated based on a quasi-cyclic low-density parity check coding scheme , the transmitting method comprising:a cyclic block permutation step of applying a cyclic block permutation process to a codeword made up of N cyclic blocks each consisting of Q bits, to reorder the cyclic blocks in accordance with a cyclic block permutation rule defining a reordering of the cyclic blocks;a bit permutation step of applying a bit permutation process to the codeword after the cyclic block permutation process, to reorder the bits of the codeword in accordance with a bit permutation rule defining a reordering of the bits;a dividing step of dividing the codeword after the bit permutation process into a plurality of constellation words, each of the constellation words being made up of M bits,a modulating step of mapping each constellation word to a modulated signal, anda transmitting step of transmitting a transmitting signal generated from the constellation words, whereinN is a multiple of M,the bit permutation rule defines the reordering of the bits of the codeword after the cyclic block permutation process, the reordering of the bit permutation rule being equivalent to a column-row permutation process including a writing process and a reading process, the bits of the N cyclic blocks being written into a matrix row-by-row during the writing process, the written bits being ...

DATA PROCESSING METHOD, PRECODING METHOD, AND COMMUNICATION DEVICE

An encoder outputs a first bit sequence having N bits. A mapper generates a first complex signal s and a second complex signal s with use of bit sequence having X+Y bits included in an input second bit sequence, where X indicates the number of bits used to generate the first complex signal s, and Y indicates the number of bits used to generate the second complex signal s. A bit length adjuster is provided after the encoder, and performs bit length adjustment on the first bit sequence such that the second bit sequence has a bit length that is a multiple of X+Y, and outputs the first bit sequence after the bit length adjustment as the second bit sequence. As a result, a problem between a codeword length of a block code and the number of bits necessary to perform mapping by a set of modulation schemes is solved. 1. A transmission signal generation device , comprising:an encoder configured to generate a first bit sequence that is an N-bit codeword from a K-bit information bit sequence, where K and N are each an integer greater than or equal to 1:a bit adjuster configured to (i) judge whether or not to add a known bit sequence to the first bit sequence, and (ii) when judging negatively, output the first bit sequence, and when judging affirmatively, output a second bit sequence that is obtained by adding the known bit sequence to the first bit sequence; anda mapper configured to modulate the first bit sequence of N bits or the second bit sequence using a modulation scheme selected from among a plurality of modulation schemes, whereina modulation symbol of the selected modulation scheme has X bits, where X is an integer greater than or equal to 1,when N is an integral multiple of X, the bit adjuster does not add the known bit, andwhen N is not the integral multiple of X, the bit adjuster adds the known bit of α×X−N bits to the first bit sequence, where α and α×X−N are each an integer greater than or equal to 1.2. The transmission signal generation device of claim 1 , ...

DATA PROCESSING METHOD, PRECODING METHOD, AND COMMUNICATION DEVICE

An encoder outputs a first bit sequence having N bits. A mapper generates a first complex signal s and a second complex signal s with use of bit sequence having X+Y bits included in an input second bit sequence, where X indicates the number of bits used to generate the first complex signal s, and Y indicates the number of bits used to generate the second complex signal s. A bit length adjuster is provided after the encoder, and performs bit length adjustment on the first bit sequence such that the second bit sequence has a bit length that is a multiple of X+Y, and outputs the first bit sequence after the bit length adjustment as the second bit sequence. As a result, a problem between a codeword length of a block code and the number of bits necessary to perform mapping by a set of modulation schemes is solved. 1. A transmission device comprising:an error correction encoder configured to generate a first encoded data sequence from an input data sequence using a first coding rate and a first code length, and generate a second encoded data sequence using a second coding rate and a second code length;a mapper configured to generate a first modulation symbol sequence by applying a first mapping pattern of a first modulation scheme to the first encoded data sequence, and generate a second modulation symbol sequence by applying a second mapping pattern of a second modulation scheme to the second encoded data sequence; anda transmitter configured to transmit the first modulation symbol sequence and the second modulation symbol sequence, whereinthe mapper uses the first mapping pattern and the second mapping pattern that are different from each other for mapping, when (i) the first code length and the second code length are different from each other, (ii) the first modulation scheme and the second modulation scheme are the same in the number of transmission bits per symbol, and (iii) the first coding rate and the second coding rate are the same.2. A reception device ...

APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS

A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for transmitting broadcast signals comprises an encoder for encoding service data, a mapper for mapping the encoded service data into a plurality of OFDM (Orthogonal Frequency Division Multiplex) symbols to build at least one signal frame, a frequency interleaver for frequency interleaving data in the at least one signal frame by using a different interleaving-seed which is used for every OFDM symbol pair comprised of two sequential OFDM symbols, a modulator for modulating the frequency interleaved data by an OFDM scheme and a transmitter for transmitting the broadcast signals having the modulated data, wherein the different interleaving-seed is generated based on a cyclic shifting value and wherein an interleaving seed is variable based on an FFT size of the modulating. 120-. (canceled)21. A method comprising:at an electronic device with one or more processors for processing broadcast signals:encoding data for one or more services of the broadcast signals;building a signal frame carrying the encoded data; generating a main sequence, a same main sequence being used for two consecutive symbols to be processed by an OFDM (Orthogonal Frequency Division Multiplexing) scheme;', 'generating a symbol offset, a value of the symbol offset being constant for the two consecutive symbols;', 'generating a sequence based on the main sequence and the symbol offset; and', 'checking a validity of address of the generated sequence to output the interleaving sequence that corresponds to one or more valid addresses;, 'frequency interleaving data in the signal frame by a interleaving sequence that applies to a symbol in the data signal, wherein the interleaving sequence is generated bymodulating frequency interleaved data by the OFDM scheme; andtransmitting broadcast signals carrying modulated data.22. The method of claim 21 , wherein when the frequency interleaving applies to a signal ...

INTERLEAVING AND MAPPING METHOD AND DEINTERLEAVING AND DEMAPPING METHOD FOR LDPC CODEWORD

An interleaving and mapping method and a deinterleaving and demapping method for an LDPC codeword are provided. The interleaving and mapping method comprises: performing first bit interleaving on a parity bits part of the LDPC codeword to obtain interleaved parity bits; splicing an information bit part of the codeword and the interleaved parity bits into a codeword after the first bit interleaving; dividing the codeword after the first bit interleaving into multiple consecutive bit subblocks in a predetermined length, and changing the order of the bit subblocks according to a corresponding permutation order (bit-swapping pattern) to form a codeword after second bit interleaving; dividing the codeword after the second bit interleaving into two parts, and writing the two parts into storage space in a column order respectively and reading the two parts from the storage space in a row order respectively to obtain a codeword after third bit interleaving. 1. A transmitter , comprising:an encoder configured to encode, based on a low-density parity-check (LDPC) code with a code rate of 4/15 and a code length of 64,800 bits, input information bits to generate an LDPC codeword, wherein the LDPC codeword comprises an information bit part and a check bit part;an interleaver dividing the LDPC codeword into multiple bit subblocks, and changing an order of the bit subblocks according to a permutation order, so as to provide a bit-interleaved LDPC codeword; anda modulator mapping bits of the bit-interleaved LDPC codeword onto constellation points for irregular 16-quadrature amplitude modulation (QAM);the permutation order is defined as follows:165 8 136 2 58 30 127 64 38 164 123 45 78 17 47 105 159 134 124 147 148 109 67 98 157 57 156 170 46 12 172 29 9 3 144 97 83 151 26 52 10 39 50 104 92 163 72 125 36 14 55 48 1 149 33 110 6 130 140 89 77 22 171 139 112 113 152 16 7 85 11 28 153 73 62 44 135 116 4 61 117 53 111 178 94 81 68 114 173 75 101 88 65 99 126 141 43 15 18 90 35 24 142 ...

Polar Code Interleaving and Bit Selection

Apparatus and methods are provided for polar code sub-block interleaving and bit selection. In one novel aspect, middle-part interlaced sub-block interleaving is provided for polar code interleaving. In one embodiment, the middle part of the polar code is interlaced and generates the interleaved polar code. In another embodiment, the lower part and the upper part are also sub-block interleaved with the middle-part interlaced method. In another novel, rate-dependent unified bit selection is provided. The bit selection is categorized into three operation categories of repetition, puncturing and the shortening. Each category follows unified bit selection rule with different categories differ only in the access scheme. In one embodiment, the circular buffer is used for bit selection. 1. A method comprising:dividing in sequence a polar code into a lower part, a middle part, and an upper part by a base station, wherein the system polar code has a polar code length N;performing a rate-independent interlaced interleaving for the middle part of the polar code to obtain an interleaved bit sequence; andtransmitting a transmission bit sequence, wherein the transmission bit sequence is generated by a rate-dependent bit selection from the interleaved bit sequence based on an output length E to obtain a transmission bit sequence.2. The method of claim 1 , the bit selection is categorized to bit-selection operations comprising: a repetition operation with E greater than or equal to N claim 1 , a puncturing operation with E smaller than N and a targeted code rate smaller than or equal to a predefined threshold T claim 1 , and a shortening operation with E smaller than N and a targeted code rate greater than T.3. The method of claim 2 , wherein the bit selection operation is the repetition operation claim 2 , and wherein the transmission bit sequence from index 0 to E is selected starting from a lowest index of the interleaved bit sequence and repeated from the lowest index of the ...

COMMUNICATION METHOD AND SYSTEM WITH ON DEMAND TEMPORAL DIVERSITY

The disclosure may provide for a communication method and system. A transmitter of the communication system may include an interleaver and a first encoder for determining parity bits. The transmitter also may include a multiplexer for joining the parity bits with the data. A second encoder may be positioned after the multiplexer for implementing an error correcting code. A receiver of the communication system may include a decoder followed by an interleaver. When errors are detected in received data at the decoder, one or more processors of the receiver may be configured to correct portions of the received data and combine the corrected portions with the received data. 1. A method comprising:receiving, by one or more second processors of a communication device, an input signal;decoding, by the one or more second processors, the input signal to obtain second data;identifying, by the one or more second processors, one or more errors in the input signal and locations of the one or more errors;producing, by the one or more second processors, one or more erasures in the data at the locations of the one or more errors;de-interleaving, by the one or more second processors, the data in the input signal;correcting, by the one or more second processors, the one or more erasures to obtain corrected data; andcombining, by the one or more second processors, the corrected data and the data to form complete corrected data.2. The method of claim 1 , wherein the input signal is an error-corrected claim 1 , multiplexed signal.3. The method of claim 2 , wherein the multiplexed signal includes parity bits multiplexed with second data.4. The method of claim 1 , wherein the corrected data and the data are combined by:receiving an index indicating a location of the one or more erasures; andreplacing portions of the data with portions of the corrected data according to the index.5. The method of claim 1 , wherein correcting the data includes reordering the de-interleaved data.6. The method ...

HIGH SPEED INTERLEAVER/DEINTERLEAVER DEVICE SUPPORTING LINE RATE, AND METHOD THEREOF

A deinterleaver device, a method for deinterleaving, an interleaver device, and a method for interleaving are disclosed. The method for deinterleaving includes: providing a memory and a stream count for a frame; virtually dividing the memory into equal sections, wherein a section count equals the stream count; calculating a write address for a sample of the samples based on a location of the sample in the frame and a correspondence of the location to one of the sections; receiving the sample; and writing the received sample to the write address, wherein the calculating and the write address corresponds to a correct deinterleaving location in one of the sections for the sample. 121-. (canceled)22. A method for interleaving soft decisions for a frame , the method comprising:providing a memory and a stream count selected from n-different supported stream counts;virtually dividing the memory into x-rows, y-columns and the y-columns into equal sections, wherein y is calculated as a common denominator of a majority of the n-different counts, x is at least a length of samples divided by y, and the y-columns are subdivided into equal sections wherein a section count equals the stream count;collecting soft decisions sequentially, wherein the soft decisions number less than or equal to a frame size of the frame;calculating, for each respective soft decision, a write address comprising a row of the x-rows and a column of the y-columns based on a location of the respective soft decision, wherein a next column of the y-columns is set as the column every x soft decisions; andwriting the respective soft decision to a respective write address of the memory.23. The method of claim 22 , wherein a frame length of the soft-decisions in the frame is variable.24. The method of claim 22 , wherein the frame comprises 64 claim 22 ,800 soft-decisions claim 22 , each soft decision of the soft decisions is 6-bits claim 22 , the frame is modulated using a modulation type having 1 claim 22 , 2 ...

MULTI-ELEMENT CODE MODULATION MAPPING METHOD, DEVICE AND COMPUTER STORAGE MEDIUM

Disclosed is a multi-element code modulation mapping method and device, relating to communications and designed to improve communication reliability. The method includes that: multi-element domain coding is performed on a first sequence including K multi-element codes to obtain a second sequence including N multi-element codes; Kand Kare calculated according to a multi-element domain element number q and a modulation order M, wherein K*logq=K*logM, both Kand Kare integers not smaller than 2, and both q and M are power of 2; the second sequence is divided into z groups of multi-element codes with each group including Kmulti-element codes, wherein C=formula (I), and formula (II) represents rounding up; each group of multi-element codes is mapped to a constellation diagram to form KMth-order modulation symbols; and z groups of Mth-order modulation symbols are sequentially cascaded to form a modulation symbol to be sent. The present disclosure further discloses a computer storage medium. 1. A multi-element code modulation mapping method , comprising:performing multi-element domain coding on a first sequence comprising K multi-element codes to obtain a second sequence comprising N multi-element codes;{'sub': 1', '2', '1', '2', '2', '2', '1', '2, 'calculating Kand Kaccording to a multi-element domain element number q and a modulation order M, wherein K*logq=K*logM, Kand Kare both integers not smaller than 2, and q and M are both power of 2;'}{'sub': 1', '1, 'dividing the second sequence into z groups of multi-element codes with each group comprising Kmulti-element codes, wherein z=┌N/K┐, and ┌ ┐ represents rounding up;'}{'sub': '2', 'mapping each group of multi-element codes to a constellation diagram to form KMth-order modulation symbols, wherein each group of multi-element codes is mapped to at least two Mth-order modulation symbols; and'}sequentially cascading z groups of Mth-order modulation symbols to form a modulation symbol to be sent.2. The method according to ...

WIRELESS COMMUNICATION DEVICE AND WIRELESS COMMUNICATION METHOD

According to one aspect of the present invention, there is provided a wireless communication device that transmits a first wireless signal representing a bit sequence to a reception device, in which the first wireless signal is transmitted concurrently with a second wireless signal representing the bit sequence described above, and in which between the first wireless signal and the second wireless signal, components with a prescribed ratio are mapped to a different frequency or to a different time between the first wireless signal and the second wireless signal and remaining components are mapped to the same frequency and to the same time between the first wireless signal and the second wireless signal. 1. A wireless communication device that transmits a first wireless signal representing a bit sequence to a reception device ,wherein the first wireless signal is transmitted concurrently with a second wireless signal representing the bit sequence, andwherein, between the first wireless signal and the second wireless signal, components with a prescribed ratio are mapped to a different frequency or to a different time between the first wireless signal and the second wireless signal and remaining components are mapped to an identical frequency and to an identical time between the first wireless signal and the second wireless signal.2. The wireless communication device according to claim 1 , further comprising:an interleave module that, in the bit sequence, performs first interleave on bits with a prescribed ratio, and performs second interleave on remaining bits; anda transmission module that generates the first wireless signal from a bit sequence that is output by the interleave module, and transmits the generated first wireless signal,wherein the second wireless signal is a wireless signal that is generated from a bit sequence resulted from performing third interleave different from the first interleave on the bits with the prescribed ratio and from a bit sequence ...

TRANSMITTING APPARATUS AND MAPPING METHOD THEREOF

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme. 2. The method as claimed in claim 1 , wherein the interleaving comprises:splitting the codeword into a plurality of bit groups; andinterleaving the plurality of bit group.3. The method as claimed in claim 1 , wherein the mapping comprises:demultiplexing the bits of the interleaved codeword into parallel streams to generate cells; andmapping the cells onto the constellation points. This application is a Continuation of application Ser. No. 14/716,283 filed May 19, 2015, the disclosure of which is incorporated herein by reference in its entirety.Apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to transmitting and receiving date using broadcasting, more particularly, to the design of non-uniform constellations used in a Bit Interleaved Coded Modulation (BICM) mapping bits at an output of an encoder and interleaver to complex constellations.The current broadcasting systems consistent with the Digital Video Broadcasting Second Generation Terrestrial (DVB-T2) use a Bit Interleaved and Coded Modulation (BICM) chain in order to encode bits to be transmitted. The BICM chain includes a channel encoder like a Low Density Parity Check (LDPC) encoder followed by a Bit Interleaver and a Quadrature Amplitude Modulation (QAM) mapper. The role of the QAM mapper is to map different bits output from the channel encoder and interleaved using the Bit Interleaver to QAM cells. Each cell represents a complex number having real and imaginary part. The QAM mapper groups M bits into one cell. Each cell is ...

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 2/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping. 1. A bit interleaving method , comprising:storing a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15;generating an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword; andoutputting the interleaved codeword,wherein the interleaving is performed using the following equation using permutation order:{'sub': j', 'j, 'where Xis the j-th bit group, Yis an interleaved j-th bit group, and π(j) is a permutation order for bit group-based interleaving.'}2. The bit interleaving method of claim 1 , wherein the permutation order corresponds to an interleaving sequence represented by the following{'br': None, 'interleaving sequence={7 11 4 38 19 25 2 43 15 26 18 14 9 29 44 32 0 5 35 10 1 12 6 36 21 33 37 34 3 31 20 16 40 23 41 22 30 39 13 24 17 42 28 8 27},'}wherein the interleaving sequence is for a case where 64-symbol mapping is employed.3. The bit interleaving method of claim 2 , wherein the 64-symbol mapping is a Non-Uniform Constellation (NUC) symbol mapping which corresponds to 64 constellations.4. The bit interleaving method of claim 3 , wherein the parallel factor is 360 claim 3 , and the bit group includes 360 bits.5. The bit interleaving method of claim 4 , wherein the LDPC codeword is represented by (u claim 4 , u claim 4 , . . . claim 4 , u) ( ...

DUAL STAGE CHANNEL INTERLEAVING FOR DATA TRANSMISSION

Methods, systems, and devices for wireless communication are described that may perform dual stage channel interleaving in which code blocks are interleaved at the code block level and at a symbol level. The interleaved code block data may provide time diversity for the code block data, and the interleaved symbol data may provide frequency diversity for the code block data, thus helping to mitigate narrowband and/or bursty interference. The interleaving within the code block and interleaving within the symbols, in some examples, may allow pipelined implementation of decoding of the code blocks at the receiver, for faster processing. In some cases, systematic data and parity data may be interleaved within the code block data to provide a uniform distribution of the systematic data in time within the code block. 1. A method for wireless communication , comprising:identifying code block data to be transmitted in a code block to a receiver;interleaving the code block data to generate interleaved code block data;concatenating interleaved code block data from different code blocks sequentially;allocating the concatenated interleaved code block data into orthogonal frequency division multiplexing (OFDM) symbols sequentially;interleaving the concatenated interleaved code block data allocated into each OFDM symbol to generate interleaved OFDM symbol data to be transmitted in each OFDM symbol; andtransmitting the OFDM symbols to the receiver.2. The method of claim 1 , wherein interleaving the code block data comprises:interleaving the code block data comprises interleaving systematic data and parity data within the code block data to provide a uniform distribution of the systematic data in time within the code block.3. The method of claim 1 , wherein the interleaved code block data provides time diversity for the code block data and the interleaved OFDM symbol data provides frequency diversity for the code block data.4. The method of claim 1 , wherein the code block data ...

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF10/15 AND 256-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 10/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping. 1. A bit-interleaved coded modulation (BICM) reception device , comprising:a demodulator configured to perform demodulation corresponding to 256-symbol mapping;a bit deinterleaver configured to perform group-unit deinterleaving on interleaved values, the interleaved values generated after the demodulation; anda decoder configured to restore information bits by LDPC-decoding deinterleaved values generated based on the group-unit deinterleaving, the deinterleaved values corresponding to a LDPC codeword having a length of 16200 and a code rate of 10/15, wherein the group-unit deinterleaving is performed on a group basis, the size of the group corresponding to a parallel factor of the LDPC codeword.2. The BICM reception device of claim 1 , wherein the group-unit deinterleaving corresponds to a reverse process of interleaving performed by using permutation order claim 1 , and the permutation order corresponds to an interleaving sequence represented by the followinginterleaving sequence ={128 20 18 38 39 2 3 30 19 4 14 36 7 0 25 17 10 6 33 15 8 26 42 24 11 21 23 5 40 41 29 32 37 44 43 31 35 34 22 1 16 27 9 13 12}.3. The BICM reception device of claim 2 , wherein the 256-symbol mapping is a Non-Uniform Constellation (NUC) symbol mapping which corresponds to 256 constellations.4. The BICM reception device of claim 2 , wherein the parallel factor is 360 claim 2 , and the group includes 360 ...

Apparatus for transmitting and receiving a signal and method of transmitting and receiving a signal

According to one embodiment, a transmitter for transmitting at least one broadcast signal having PLP (Physical Layer Pipe) data includes: a BCH (Bose-Chadhuri-Hocquenghem) encoder configured to BCH encode the PLP data; an LDPC (Low Density Parity Check) encoder configured to LDPC encode the BCH encoded PLP data and output FECFrames (Forward Error Correction Frames); a mapper configured to map data in the FECFrames onto constellations by QAM (Quadrature Amplitude Modulation) schemes; a time-interleaver configured to time-interleave the mapped data; a frame builder configured to build a signal frame including preamble symbols and data symbols; and an OFDM (Orthogonal Frequency Division Multiplexing) modulator configured to modulate data in the signal frame by an OFDM scheme. The PLP data are processed by an LDPC scheme for a long or a short LDPC FECframe. The preamble symbols include signaling information for the time-interleaved PLP data. The data symbols include the time-interleaved PLP data.

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 3/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). 1. A low density parity check (LDPC) decoder , comprising:a receiving unit configured to receive a signal corresponding to an LDPC codeword having a length of 64800 and a code rate of 3/15, the LDPC codeword encoded using a sequence corresponding to a parity check matrix (PCM); anda decoding unit configured to perform decoding the received signal, the decoding corresponding to the parity check matrix.3. The LDPC decoder of claim 2 , wherein the LDPC codeword comprises a systematic part corresponding to information bits and having a length of 12960 claim 2 , a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 1800 claim 2 , and a second parity part corresponding to an identity matrix included in the PCM and having a length of 50040.4. The LDPC decoder of claim 3 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part claim 3 , that is claim 3 , 12960 claim 3 , by a circulant permutation matrix (CPM) size corresponding to the PCM claim 3 , that is claim 3 , 360 claim 3 , and a value obtained by dividing a length of the first parity part claim 3 , that is claim 3 , 1800 claim 3 , by the CPM size.5. The LDPC decoder of claim 2 , wherein the LDPC codeword is generated by performing accumulation with respect to a memory and the accumulation is performed at parity bit addresses that are updated using the sequence.6. The LDPC decoder of claim 5 , wherein the ...

Transmitting method including bit group interleaving

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

TIME VARYING DATA PERMUTATION APPARATUS AND METHODS

Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations. 1. A data encoder system comprising:a first permutation apparatus comprising a first time-varying permutation element, the first permutation apparatus being configured to generate a first time-varying stream;a Forward Error Correction (FEC) encoder configured to encode the first time-varying stream to generate an encoded stream; anda second permutation apparatus comprising a second time-varying permutation element, the second time-varying permutation element being configured to generate a second time-varying stream based on the encoded stream.2. The data encoder system of wherein the first permutation apparatus further comprising a block interleaver configured to generate an interleaved data stream claim 1 , the first-time varying stream being generated based on the interleaved data stream.3. The data encoder of wherein the second permutation apparatus comprises a de-interleaver configured to de-interleave the second time-varying stream.4. The data encoder of wherein the first permutation apparatus is configured to process an input data stream.5. The data encoder of wherein the second permutation apparatus is configured to generate an encoded output data stream based on the second-time varying stream.6. The data encoder of wherein the second permutation apparatus further comprises a third time-varying permutation element for performing inverse permutation.7. The data encoder of wherein the first time-varying permutation ...

ERROR CORRECTION DEVICE AND ERROR CORRECTION METHOD

Provided is an error correction device including an encoding circuit configured to encode a plurality of error correction code sequences, in which the encoding circuit includes a plurality of encoding circuits connected in parallel, and is configured to execute encoding processing for the plurality of error correction code sequences through use of all the plurality of encoding circuits by adjusting an output bus width and a frequency of an operation clock with respect to a difference in transmission rate for any payloads input in one or more systems. 1. An error correction device , comprising at least one of:an encoder configured to encode a plurality of error correction code sequences; anda decoder configured to decode the plurality of error correction code sequences,wherein the encoder includes a predetermined plurality of encoders connected in parallel, and is configured to execute encoding processing for the plurality of error correction code sequences through use of all the predetermined plurality of encoders by adjusting an output bus width and a frequency of an operation clock with respect to a difference in transmission rate for any one of a payload input in one system and payloads input in two or more systems, andwherein the decoder includes a predetermined plurality of decoders connected in parallel, and is configured to execute decoding processing for the plurality of error correction code sequences through use of all the predetermined plurality of decoders by adjusting an output bus width and a frequency of an operation clock with respect to a difference in transmission rate for any one of a payload input in one system and payloads input in two or more systems.2. The error correction device according to claim 1 , wherein the plurality of error correction code sequences are subjected to interleaving in units of bit or symbol with respect to a transmission order among data buses to which the plurality of error correction code sequences are input.3. The ...

TRANSMITTING APPARATUS AND SIGNAL PROCESSING METHOD THEREOF

A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method. 1. An interleaving method of a transmitting apparatus , the method comprising:splitting bits into a plurality of bit groups;interleaving the plurality of bit groups;interleaving the interleaved plurality of bit groups using a plurality of containers to provide an interleaved codeword, each of the plurality of containers comprising a first part and a second part;demultiplexing bits of the interleaved codeword to generate cells;mapping the cells onto constellation points, andtransmitting a signal which is based on the constellation points,wherein a number of bits to be written in the first part is determined based on a number of the plurality of containers and a number of bits of each of the plurality of bit groups, andwherein a number of bits to be written in the second part is determined based on the number of the plurality of containers and the number of the bits of each of the plurality of bit groups.2. The method as claimed in claim 1 , wherein the each of the plurality of bit groups comprises 360 bits.3. The method as claimed in claim 1 , wherein the number of the plurality of containers is equal to a modulation order for the mapping.4. A transmitting apparatus comprising:a group interleaver configured to split bits into a plurality of bit groups and interleave the plurality of bit groups;a block ...

Apparatus and Method for Multi-Code Distributed Storage

Systems and techniques described herein include jointly decoding coded data of different codes, including different coding algorithms, finite fields, and/or source blocks sizes. The techniques described herein can be used to improve existing distributed storage systems by allowing gradual data migration. The techniques can further be used within existing storage clients to allow application data to be stored within diverse different distributed storage systems. 1. A method for use in a multi-code storage system , the method comprising:receiving a first set of symbols associated with a file, wherein the first set of symbols comprises a first set of source symbols or a first set of coded symbols encoded using the first set of source symbols;receiving a second set of symbols associated with the file, wherein the second set of symbols comprises a second set of source symbols or a second set of coded symbols encoded using the second set of source symbols with the first set of source symbols being different than the second set of source symbols, and wherein either the first set of symbols or the second set of symbols are a set of coded symbols; andjointly decoding the first and second symbols to recover the file.2. The method of whereinreceiving the first set of symbols includes receiving first coded symbols encoded using a first code;receiving the second set of symbols includes receiving second coded symbols encoded using a second code, wherein the first and second codes differ in at least one of generator matrices, finite fields, or block sizes, or combinations thereof; andjointly decoding the first and second symbols includes jointly decoding the first and second coded symbols.3. The method of wherein:receiving the first set of symbols comprises receiving the first set of symbols from a first distributed storage system; andreceiving the second set of symbols comprises receiving the second set of symbols from a second distributed storage system.4. The method of wherein ...

MAPPING DATA TO OFDM SYMBOLS

Apparatuses, methods, and systems are disclosed for mapping data to OFDM symbols. One apparatus () includes a receiver () that receives () data. In some embodiments, consecutive modulation symbols corresponding to the data are mapped to orthogonal frequency-division multiplexing symbols in a time domain that are separated by one or more orthogonal frequency-division multiplexing symbols. 1. An apparatus comprising:a receiver that receives data, wherein consecutive modulation symbols corresponding to the data are mapped to orthogonal frequency-division multiplexing symbols in a time domain that are separated by one or more orthogonal frequency-division multiplexing symbols.2. The apparatus of claim 1 , wherein modulation symbols corresponding to the data are mapped to orthogonal frequency-division multiplexing symbols in a frequency domain.3. The apparatus of claim 1 , wherein spatial layers of a resource element are not mapped to consecutive modulation symbols corresponding to the data.4. The apparatus of claim 1 , wherein consecutive modulation symbols corresponding to the data are mapped to orthogonal frequency-division multiplexing symbols in the time domain that are separated by two or more orthogonal frequency-division multiplexing symbols.5. The apparatus of claim 1 , wherein consecutive modulation symbols corresponding to the data are mapped to orthogonal frequency-division multiplexing symbols in the time domain that are separated by three or more orthogonal frequency-division multiplexing symbols.6. A method comprising:receiving data, wherein consecutive modulation symbols corresponding to the data are mapped to orthogonal frequency-division multiplexing symbols in a time domain that are separated by one or more orthogonal frequency-division multiplexing symbols.7. The method of claim 6 , wherein modulation symbols corresponding to the data are mapped to orthogonal frequency-division multiplexing symbols in a frequency domain.8. The method of claim 6 , ...

METHOD OF SIGNAL GENERATION AND SIGNAL GENERATING DEVICE

A transmission method simultaneously transmitting a first modulated signal and a second modulated signal at a common frequency performs precoding on both signals using a fixed precoding matrix and regularly changes the phase of at least one of the signals, thereby improving received data signal quality for a reception device. 1. A signal generation method comprising:phase-changing baseband signals with respective phase changing patterns to generate respective phase-changed signals, each of the phase changing patterns being different from each other; andinverse-fast-Fourier-transforming the phase-changed signals to respective OFDM transmission signals, whereineach phase changing pattern has N candidates for an amount of change in a phase, N being an integer greater than two,each candidate is periodically selected from the N candidates based on subcarriers of the OFDM transmission signal, a phase of the baseband signal being changed by the each candidate.2. A signal generation apparatus comprising:phase change circuit configured to phase-change baseband signals with respective phase changing patterns to generate respective phase-changed signals, each of the phase changing patterns being different from each other; andinverse fast Fourier transform circuit configured to inverse-fast-Fourier-transform the phase-changed signals to respective OFDM transmission signals, whereineach phase changing pattern has N candidates for an amount of change in a phase, N being an integer greater than two,each candidate is periodically selected from the N candidates based on subcarriers of the OFDM transmission signal, a phase of the baseband signal being changed by the each candidate. This application is a continuation of U.S. application Ser. No. 16/239,145, filed Jan. 3, 2019, which is a continuation of U.S. application Ser. No. 15/987,016, filed May 23, 2018, now U.S. Pat. No. 10,225,123, which is a continuation of application Ser. No. 15/496,406, filed Apr. 25, 2017, now U.S. Pat. ...

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 3/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping. 1. A bit interleaver , comprising:a first memory configured to store a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15;a processor configured to generate an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword; anda second memory configured to provide the interleaved codeword to a modulator for 64-symbol mapping.2. The bit interleaver of claim 1 , wherein the 64-symbol mapping is a Non-Uniform Constellation (NUC) symbol mapping which corresponds to 64 constellations.3. The bit interleaver of claim 2 , wherein the parallel factor is 360 claim 2 , and the bit group includes 360 bits.6. The bit interleaver of claim 5 , wherein the permutation order corresponds to an interleaving sequence represented by the following equation:{'br': None, 'interleaving sequence={19 34 22 6 29 25 23 36 7 8 24 16 27 43 11 35 5 28 13 4 3 17 15 38 20 0 26 12 1 39 31 41 44 30 9 21 42 18 14 32 10 2 37 33 40}'} This application is a continuation of U.S. application Ser. No. 14/717,174, filed May 20, 2015, which claims the benefit of Korean Patent Application Nos. 10-2014-0061874 and 10-2015-0009141, filed May 22, 2014 and Jan. 20, 2015, which are hereby incorporated by reference herein in their entirety.The present disclosure relates generally to an interleaver and, ...

TRANSMITTER APPARATUS AND BIT INTERLEAVING METHOD THEREOF

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding of input bits based on a parity check matrix including information word bits and parity bits, the LDPC codeword including a plurality of bit groups each including a plurality of bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the interleaver is further configured to interleave the LDPC codeword such that a bit included in a predetermined bit group from among the plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol. 2. The transmitting method of claim 1 , wherein each of the plurality of bit groups comprises 360 bits.3. The transmitting method of claim 1 , wherein the interleaving further comprises:interleaving the interleaved plurality of bit groups.4. The transmitting method of claim 1 , wherein the π(j) is determined based on at least one of the code length claim 1 , a modulation method for the mapping claim 1 , and the code rate.6. The method of claim 5 , wherein each of the plurality of groups comprises 360 values.7. The method of claim 5 , wherein the π(j) is determined based on at least one of the code length claim 5 , a modulation method for the mapping claim 5 , and the code rate. This is a Continuation of U.S. application Ser. No. 16/460,305 filed Jul. 2, 2019, which is a Continuation of U.S. application Ser. No. 15/686,280 filed Aug. 25, 2017, which is a Continuation of application Ser. No. 14/716,503 filed May 19, 2015, and claims priority from U.S. Provisional Application No. 62/001,160 filed on May 21, 2014 and Korean Patent Application No. 10-2015-0069924 filed on May 19, 2015, the disclosures of which are incorporated herein by reference in their entirety.Apparatuses and methods consistent with exemplary embodiments ...

APPARATUS FOR TIME INTERLEAVING AND METHOD USING THE SAME

An apparatus and method for time interleaving corresponding to hybrid time interleaving mode are disclosed. An apparatus for time interleaving according to an embodiment of the present invention includes a twisted block interleaver configured to perform intra-subframe interleaving corresponding to time interleaving blocks; and a convolutional delay line configured to perform inter-subframe interleaving using an output of the twisted block interleaver. 1. An apparatus for time deinterleaving , comprising:an inverse convolutional delay line configured to perform an inverse process of inter-subframe interleaving which is performed by a convolutional delay line of a transmitter; anda twisted block deinterleaver configured to perform an inverse process of intra-subframe interleaving which is performed by a twisted block interleaver of the transmitter,wherein the inter-subframe interleaving is performed by using an output of the intra-subframe interleaving at the transmitter.2. The apparatus of claim 1 , wherein the intra-subframe interleaving is performed by a column-wise writing operation and a diagonal-wise reading operation.3. The apparatus of claim 1 , wherein the convolutional delay line reads only data cells except for virtual cells from the twisted block interleaver.4. The apparatus of claim 3 , wherein after each row of the data cells is written from the twisted block interleaver claim 3 , the convolutional delay line generates new virtual cells prior to switches moving to a next branch.5. The apparatus of claim 4 , wherein the new virtual cells correspond to a number obtained by subtracting a number (N) of FEC blocks in a time interleaving block of an interleaving frame from a maximum number (N) of the FEC blocks corresponding to the time interleaving block of the interleaving frame for each branch.6. The apparatus of claim 5 , wherein the new virtual cells are not outputted from a time interleaver of the transmitter.7. The apparatus of claim 6 , wherein the ...

TWO-STAGE INTERLEAVING TECHNIQUES FOR WIRELESS COMMUNICATIONS

Methods, systems, and devices for wireless communications are described in which a two-stage interleaving pattern may be provided for communication of coded information via a channel. The channel may have a channel bandwidth within a bandwidth part (BWP) of a total frequency bandwidth, and the two-stage interleaving pattern may provide a first interleaving pattern of resource blocks within an allocated set of user equipment (UE) resources and a second interleaving pattern of resource blocks within the BWP. The two-stage interleaving pattern may be based on the first interleaving pattern being initially applied to resource blocks within the allocated set of UE resources, and the second interleaving pattern being subsequently applied to resource blocks within the BWP. Signaling to indicate a type of interleaving to be applied to a communication may be provided in semi-static signaling, dynamic signaling, or combinations thereof. 1. A method for wireless communications at a user equipment (UE) , comprising:determining a two-stage interleaving pattern for receiving coded information from a base station via a channel having a channel bandwidth within a bandwidth part of a total frequency bandwidth, wherein the two-stage interleaving pattern indicates a first interleaving pattern of resource blocks within an allocated set of UE resources and a second interleaving pattern of resource blocks within the bandwidth part;receiving the coded information via the channel; anddecoding one or more resource blocks of the coded information based at least in part on the two-stage interleaving pattern.2. The method of claim 1 , wherein the two-stage interleaving pattern is based on the first interleaving pattern being initially applied to resource blocks within the allocated set of UE resources claim 1 , and the second interleaving pattern being subsequently applied to resource blocks within the bandwidth part claim 1 , and wherein the bandwidth part spans a larger bandwidth than the ...

METHOD AND APPARATUS FOR FACILITATING RELIABLE TRANSMISSION OF A CONTROL REGION SIZE AND DETECTION OF CROSS-CARRIER SIGNALING

Methods, apparatuses, and computer program products are disclosed for facilitating indicating and detecting control region sizes. A multi-carrier communication between a wireless terminal and a base station is facilitated by a first carrier having a first control region size and a second carrier having a second control region size. Embodiments are disclosed in which control region sizes are ascertained from a control signal, wherein the control is generated by either scrambling an aspect of the control signal based on the second control region size, or relating the second control region size with the first control region size. Other disclosed embodiments for ascertaining control region sizes include a reverse interleaver embodiment, wherein a set of modulation symbols is mapped beginning from a last data symbol and ending with a first available data symbol. 1. A method that facilitates indicating a size of a control region , the method comprising:establishing a multi-carrier communication with at least one user equipment, the multi-carrier communication facilitated by a first carrier and a second carrier;implementing a reverse interleaver, wherein the reverse interleaver is configured to map a set of modulation symbols beginning from a last data symbol and ending with a first available data symbol; andtransmitting the set of modulation symbols to the at least one user equipment.2. The method of claim 1 , wherein the set of modulation symbols is associated with a Physical Downlink Shared Channel.3. The method of claim 1 , the reverse interleaver mapping the set of modulation symbols according to a frequency first claim 1 , time second claim 1 , interleaving scheme.4. A method that facilitates determining a size of a control region comprising:configuring a user equipment (UE) to monitor a first carrier and a second carrier, the first carrier having a first control region size, the second carrier having a second control region size;receiving a set of reverse ...

APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS

A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for transmitting broadcast signals, the apparatus comprises an encoder for encoding service data corresponding to each of a plurality of data transmission path, wherein each of the data transmission path carries at least one service component for broadcast services, an encoder for encoding signaling data, wherein the signaling data includes static data and dynamic data, a frame builder for building signal frames, wherein each of signal frames includes the encoded service data and the encoded signaling data, wherein each of signal frames belongs to one of the broadcast services, wherein the static data remain constant in the signal frames belonging to the broadcast service in a duration of a super frame and the dynamic data changes by the signal frames, a modulator for modulating the signal frames by an OFDM (Orthogonal Frequency Division Multiplex) scheme and a transmitter for transmitting the broadcast signals carrying the modulated signal frames. 120-. (canceled)21. A Method For Transmitting Broadcast Signals , Comprising:encoding service data corresponding to each of a plurality of data transmission paths;encoding signaling data;padding zero bits to the encoded signaling data, wherein a size of the padded zero bits is related to the variable size of the signaling data;LDPC encoding the zero padded signaling data by appending parity bits;building signal frames, wherein each of signal frames includes the encoded service data and the LDPC encoded signaling data;modulating the signal frames by an OFDM (Orthogonal Frequency Division Multiplex) scheme; andtransmitting the broadcast signals carrying the modulated signal frames.22. The method of claim 21 , wherein the method further comprises:segmenting the signaling data for the encoding.23. The method of claim 22 , wherein the method further comprises:scrambling the segmented signaling data.24. The method of claim 21 , ...

APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS

A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for transmitting broadcast signals comprises an encoder for encoding DP (Data Pipe) data corresponding to each of a plurality of DPs, a mapper for mapping the encoded DP data onto constellations, a time interleaver for time interleaving the mapped DP data at DP level, a frame builder for building at least one signal frame including the time interleaved DP data, a modulator for modulating data in the built at least one signal frame by an OFDM (Orthogonal Frequency Division Multiplex) scheme and a transmitter for transmitting the broadcast signals having the modulated data. 114-. (canceled)15. A method for transmitting broadcast signals , the method comprising:encoding service data;mapping the encoded service data to output cells, wherein the cells are included in at least one forward error correction (FEC) block;time interleaving the mapped service data, wherein the time interleaving includes:a column-wise writing the at least one FEC block into at least one TI block,wherein the at least one TI block includes at least one virtual FEC block,wherein a number of FEC blocks varies depending on cell rate; anddiagonal-wise reading the at least one TI block based on a diagonal-wise reading parameter,wherein cells in the at least one virtual FEC block are skipped during the diagonal-wise reading based on cell position;building at least one signal frame including the time interleaved service data;modulating data in the built at least one signal frame by an Orthogonal Frequency Division Multiplex (OFDM) scheme; andtransmitting the broadcast signals having the modulated data.16. The method of claim 15 , wherein the method further includes:wherein the diagonal-wise reading is performed by calculating the cell position based on row and column indexes of TI memory, andwherein slope for the diagonal wise reading is based on the diagonal-wise reading parameter.17. The method of claim 15 ...

SIGNAL PROCESSING METHOD

A signal method of processing in a receiver a signal that has been encoded and interleaved in a transmitter comprising: receiving a signal, process the signal to obtain a stream of soft metrics representing bit probability of symbols in a predetermined constellation; applying to said soft metric a compression operation that preserves the total length of each group of soft metrics relative to a same constellation symbol; rearranging the stream of compressed soft metrics so as to inverse the interleaving done in the transmitter. 1. A method of compressing a stream of fixed-point representations of soft metrics in a receiver , comprisingdemultiplexing the soft metrics so as to obtain a plurality sub-streams having distinct statistics distributions.applying to each sub-stream an entropy code adapted to its statistic distribution.2. The method of claim 1 , further comprisingreconstruct a transmitted message according to each of the sub-stream which is applied with the entropy code adapted to its statistic distribution.3. The method of claim 1 , comprising a step of quantizing the soft metrics prior to the step of demultiplexing the soft metrics.4. The method of claim 1 , wherein said soft metrics are represented as fixed-point numbers.5. The method of claim 3 , wherein the quantizing operation generates a constant number of bits for each group of soft metrics relative to a same constellation symbol.6. The method of claim 3 , wherein the quantizing operation generates different number of bits for each soft metric relative to a same constellation symbol. This application is a divisional application of and claims the priority benefits of U.S. non-provisional application Ser. No. 14/422,149, filed on Feb. 17, 2015, now allowed. The prior U.S. non-provisional application Ser. No. 14/422,149 is a 371 application of the International PCT application serial no. PCT/EP2012/066286, filed on Aug. 21, 2012. The entirety of each of the above-mentioned patent applications is hereby ...