СТАРТСТОПНАЯ СИСТЕМА СВЯЗИ

Изобретение относится к электро- и радиосвязи и может использоваться для передачи многоканальных и одноканальных сообщений в стартстопном и непрерывном режимах по радио-, радиорелейным, оптическим и космическим линиям связи. Технический результат состоит в импульсной мощности передатчика и обеспечении стартстопного режима работы. Для этого в многоканальную систему связи введены на передающей стороне последовательно соединенные счетчик импульсов и мультиплексор, а на приемной стороне - последовательно соединенные накопитель и пороговый блок. Этим достигается вероятность ложной тревоги за сутки порядка 10-3, что соответствует одному ложному срабатыванию приемника за 1000 суток. 3 ил.

МНОГОКАНАЛЬНАЯ СИСТЕМА СВЯЗИ

Изобретение относится к электро- и радиосвязи и может использоваться для передачи многоканальных и одноканальных сообщений в стартстопном и непрерывном режимах по радио-, радиорелейным, оптическим и космическим линиям связи. Технический результат состоит в снижении импульсной мощности передатчика и обеспечении стартстопного режима работы. Для этого в многоканальную систему связи введены на передающей стороне - последовательно соединенные счетчик импульсов и мультиплексор, на приемной стороне - последовательно соединенные накопитель и пороговый блок. Этим достигается вероятность ложной тревоги за сутки порядка 10-3, что соответствует одному ложному срабатыванию приемника за 1000 суток. 2 ил.

ЦИФРОВОЙ СЕТЕВОЙ КОМПЛЕКС

Изобретение относится к системам передачи информации, в частности к радиосистемам обмена цифровой информацией в группе абонентов, имеющей иерархическую структуру. Достигаемый технический результат - повышение надежности и минимизация времени доставки срочных сообщений в системе связи группы иерархически соединенных абонентов. Поставленная задача достигается тем, что в цифровом сетевом комплексе узлы связи ранжированы на три уровня, причем первый уровень содержит один главный узел связи, второй уровень содержит опорные узлы связи, третий уровень содержит исполнительные узлы связи. Каждый узел связи имеет два приемопередатчика, подключенных к устройству обработки сигнала. Узлы связи соединены каналами связи, причем основной канал связывает первые приемопередатчики узлов связи первого и второго уровней, вспомогательный канал связывает вторые приемопередатчики первого и третьего уровней, а каждый автономный канал связи связывает второй приемопередатчик одного из опорных узлов с первыми приемопередатчиками ...

УСТРОЙСТВО И СПОСОБ ПЕРЕДАЧИ И ПРИЕМА В СИСТЕМЕ ПЕРЕДАЧИ С МНОЖЕСТВОМ НЕСУЩИХ

Изобретение относится к системе передачи цифровых сигналов с множеством несущих и позволяет приемнику премного устройства получать требуемую информацию для настройки на требуемую частоту. Изобретение раскрывает, в частности, передающее устройство (400), содержащее модулятор (410) для модулирования каждого из множества потоков данных на поднесущих частотах соответствующей полосы частот в одной группе из одного или более частотных каналов, причем каждая из полос частот занимает не более заданной максимальной полосы пропускания, меньшей или равной ширине полосы пропускания канала, генератор (420) информации о полосе для генерирования информацию о полосе, определяющей полосы частот, соответствующие всем потокам данных, переносимым упомянутым частотным каналом, причем информация о полосе включает в себя индикатор о частоте настройки, указывающий частоту настройки, и индикатор типа частоты настройки, указывающий тип частоты настройки, указанный упомянутым индикатором частоты настройки, где упомянутый ...

СПОСОБ И СИСТЕМА ОБРАБОТКИ СООБЩЕНИЙ В УСЛУГЕ МУЛЬТИМЕДИЙНЫХ СООБЩЕНИЙ

... 1. Способ обработки сообщений в Услуге Мультимедийных Сообщений (MMS), содержащий следующий шаг: после получения сообщения от стороны пользователя Центр MMS (ЦУМС (MMSC)) отправляет уведомление на домашний Сервер Приложений Дополнительных Платных Услуг получателей этого сообщения о необходимости обработать данное сообщение в соответствии с каждым содержащемся в данном сообщении идентификатором получателя, принадлежащего к этому Серверу Приложений Дополнительных Платных Услуг. 2. Способ по п.1, отличающийся тем, что шаг, на котором центр ЦУМС (MMSC) отправляет уведомление на домашний Сервер Приложений Дополнительных Платных Услуг, соответствующий получателям этого сообщения, о необходимости обработать сообщение в соответствии с каждым содержащемся в данном сообщении идентификатором получателя, принадлежащего к этому Серверу Приложений Дополнительных Платных Услуг, содержит следующие шаги: Для каждого Сервера Приложений Дополнительных Платных Услуг, центр ЦУМС (MMSC) доставляет сообщение ...

УСТРОЙСТВО ПРИЕМА, СПОСОБ ПРИЕМА, ПРОГРАММА И СИСТЕМА ПРИЕМА

Изобретение относится к устройству приема, способу и программе в системе приема. Изобретение предназначено для улучшения точности обработки сигналов демодуляции, передаваемых в соответствии со схемой MICO. Приемник включает в себя: блок получения, выполненный с возможностью получения сигнала мультиплексирования с ортогональным частотным разделением, состоящего в результате из сигналов, переданных в соответствии со способом мультиплексирования с ортогональным частотным разделением из множества устройств передачи; блок расчета значения коррекции, выполненный с возможностью расчета значения коррекции для коррекции величины дрейфа сигнала мультиплексирования с ортогональным частотным разделением, используя фазу либо первого пилотного сигнала, или второго пилотного сигнала, выделенных из полученного сигнала мультиплексирования с ортогональным частотным разделением, первый пилотный сигнал получают из пилотных сигналов, которые являются синфазными друг с другом, поступающих из множества устройств ...

СПОСОБ ИЗГОТОВЛЕНИЯ ПРОГРАММИРУЕМЫХ ЭЛЕМЕНТОВ

... 1. Способ изготовления прогаммируемых элементов, включающий формирование на полупроводниковой подложке с элементами ИС, покрытыми диэлектрическим слоем с контактными окнами проводников нижнего уровня и нижних электродов программируемых элементов методом нанесения и локального травления первого проводящего слоя из материала на основе алюминия, формирование методом нанесения и локального травления локальных областей первого барьерного слоя, контактирующих с нижними электродами, локальных областей слоя материала программируемых элементов, контактирующих с первым барьерным слоем, локальных областей второго барьерного слоя над локальными областями слоя материала программируемых элементов, формирование изолирующего слоя, формирование окон в изолирующем слое, формирование проводников верхнего уровня и верхних электродов методом нанесения и локального травления второго проводящего слоя из материала на основе алюминия, отличающийся тем, что после нанесения первого проводящего слоя из материала на ...

СТАРТСТОПНАЯ СИСТЕМА СВЯЗИ

Стартстопная система связи, содержащая на передающей стороне последовательно соединенные источник информации, регистр сдвига, мультиплексор, относительно фазовый манипулятор (ОФМ), и передатчик, а также последовательно соединенные генератор несущей частоты (ГНЧ) и ключ, выход которого соединен с сигнальным входом ОФМ, последовательно соединенные генератор псевдослучайной последовательности (ГПСП) и перемножитель, выход которого соединен с управляющими входами ОФМ, ключа и двоичного счетчика, выход которого соединен с управляющим входом мультиплексора, кроме того, синхровыход источника информации соединен с входом генератора тактовых импульсов (ГТИ), первый выход которого соединен с установочным входом двоичного счетчика, второй выход ГТИ соединен с тактовым входом регистра сдвига, а третий выход ГТИ - с тактовым входом ГПСП и вторым входом перемножителя, выход которого соединен с установочным входом ОФМ, на приемной стороне последовательно соединенные приемник, согласованный фильтр и первый ...

СПОСОБ И УСТРОЙСТВО ДЛЯ ГИБРИДНОЙ КОРРЕКЦИИ С РЕШАЮЩЕЙ ОБРАТНОЙ СВЯЗЬЮ

... 1. Способ гибридной коррекции с решающей обратной связью посредством определения коэффициентов фильтров в эквалайзере с решающей обратной связью, содержащем фильтр с прямой связью и фильтр с обратной связью, каждый их которых характеризуется множеством коэффициентов, заключающийся в том, что выбирают функцию стоимости для эквалайзера с решающей обратной связью, причем функция стоимости представляет собой среднеквадратическую ошибку (MSE) между выходным сигналом эквалайзера в предположении безошибочной обратной связи и целевым выходным сигналом эквалайзера плюс модифицированная мера энергии коэффициентов фильтра с обратной связью, и корректируют множество коэффициентов до тех пор, пока не будет удовлетворено условие сходимости, нацеленное на минимизацию функции стоимости. 2. Способ по п.1, отличающийся тем, что множество коэффициентов соответствует множеству отводов фильтра, а модифицированная мера энергии является функцией по меньшей мере одного из отводов фильтра. 3. Способ по п.1, отличающийся ...

СИСТЕМА ПЕРЕДАЧИ И ПРИЕМА ДИСКРЕТНОЙ ИНФОРМАЦИИ ПО РАДИОКАНАЛАМ ИМПУЛЬСНО-ФАЗОВОЙ РАДИОНАВИГАЦИОННОЙ СИСТЕМЫ

Изобретение относится к технике радиосвязи, передачи данных, а также к радионавигационной технике, в частности может быть использовано в технике импульсно-фазовых радионавигационных систем длинноволнового диапазона, для устранения влияния передачи дискретной информации на качество приема радионавигационных сигналов в передающую аппаратуру системы передачи и приема дискретной информации по радиоканалам ИФРНС (СПДИ), содержащую последовательно соединенные наборное устройство, шифратор, запоминающее устройство и кодирующее устройство, а также последовательно соединенные генератор опорного напряжения, формирователь импульсов запуска, фазовые модулятор, схему ИЛИ, радиопередающее устройство и передающую антенну, дополнительно введен генератор псевдослучайной последовательности (ГПСП), содержащий последовательно соединенный первый и второй сумматор по модулю 2, схему ИЛИ и регистр сдвига, а также детектор кодовых комбинаций с соответствующими связями. В приемную аппаратуру СПДИ, содержащую последовательно ...

Устройство передачи данных

УСТРОЙСТВО ПЕРЕДАЧИ ДАННЫХ по авт. св. № 745002, отличающееся тем, что, с целью повышения скорости передачи информации при увеличении числа обслуживаемых абонентов, в него введены первый и второй блоки контроля, пятый и шестой ключи, блок адреса, оперативный запоминающий блок и блок каналов , первый вход которого соединен с информационным выходом преобразователя сдвигов, информационный вход которого подключен к выходу блока каналов, второй вход которого соединен с первым выходом блока адреса, второй выход которого соединен с адресным входом блока управления , адресный выход которого соединен о первым входом блока адреса, второй вход которого соединен с адресным выходом дешифратора , второй вход которого соединен с первым входом оперативного запоминающего блока, второй вход которого соединен с дополнительным выходом блока управления , второй выход которого соединен с дополнительным входом первого ключа и с первыми входами пятого и шестого ключей, вторые входы которых объединены и подключены ...

Ретранслятор

Изобретение относится к технике связи и может использоваться в синхронных сетях обмена дискретной информацией. Цель изобретения - повышение достоверности регистрации путем двунаправленной ретрансляции. С этой целью в устройство введены блок 3 установки, корреляционный приемник 3, буферные регистры 4, 20, фазируемый делитель 5, блоки 6, 23 кодирования сигнала информации, смесители 8. 25, 26, блоки 9. 10. 24 формирования синхропоследователь ...

Система передачи информациибииМпульСНыМ СигНАлОМ

Устройство для передачи и приема дискретной информации с коррекцией ошибок

Регенератор необслуживаемого пункта

TELECOMMUNICATION SYSTEM FOR TRANSMITTING DATA INFORMATION BY MEANS OF A DIGITAL EXCHANGE

Verfahren und Schaltungsanordnungen zur Datenuebertragung

UEBERTRAGUNGSSYSTEM FUER TELEGRAPHISCHE KOMMUNIKATIONEN.

SCHALTUNGSANORDNUNG ZUM WIEDERGEWINNEN VON IN BINAEREN DATENSIGNALEN ENTHALTENDEN DATEN

Zusatzgerät-Steuerschnittstelle

Schnittstelle zwischen einem Master- und einem Slavegerät, mit einer bitseriellen, bidirektionalen Signalleitung zum Übertragen von Befehlen und zugehörigen Daten vom Master- zum Slavegerät, wobei die bitserielle, bidirektionale Signalleitung ferner andere Signale überträgt, zu denen ein Rücksetzsignal, ein Interruptsignal und ein Lernsequenzsignal zum Spezifizieren der Dauer einer Bitzeit für vom Slave- zum Mastergerät übertragene Daten gehören.

Improvements in Automatic Resistance Regulators for Telegraph Lines and the like.

... 25,158. Belin, E. April 19. Regulation, automatic systems and apparatus for.-The resistance of a telegraph or like line 1 is regulated automatically by means of a galvanometer 4, the needle of which carries two contacts 42, 43 in circuits arranged to drive the motor 49 to move the rheostat contact 40. It is arranged that the normal strength of current is such as to close the contact 42, 45 and open the contact 43, 47. Any deviation from this condition either opens the one contact or closes the other, and the relays 44, 46 bring the motor 49 into circuit to move the contact 40 and thus to restore the normal conditions. The resistance 39 may be placed in shunt to the galvanometer or in an arm of a Wheatstone bridge. When alternating current is used, the galvanometer is placed in circuit synchronously with the alternations of the current.

Improvements in and relating to telegraph apparatus

... 381,643. Telegraphy. GILL, H. A., 51, Chancery Lane, London.-(Fuld & Co. Telephonund Telegraphemverke Akt.-Ges., H. ; Frankfort-on-Main, Germany.) Aug. 5, 1931, No. 22187. [Class 40 (iii).] In a double-current telegraph transmitter the contacts are so arranged that the current in the line can be reversed without being interrupted by the operation of keying. In a start-stop transmitter the starting signal is given by the line L being connected to negative battery B1 and disconnected from positive battery B. To this end, contact is first made at k0 and then, 'after a brief interval, which may be one-tenth of a signal period, contact is broken at K0. During the brief period when both contacts are closed, current flows from both batteries through an inductive resistance r, which checks the flow of current in the local circuit and is dimensioned to suit the line. Preferably battery B1 is one-fifth stronger than B, and resistance r is one-fifth of the resistance of the line L. After.the starting ...

UEBERTRAGUNGSSYSTEM FUER BREITBANDIGE SIGNALE UEBER SYMMETRISCHE ODER UNSYMETRISCHE LEITUNGEN

PROCEDURE AND DEVICE FOR BLOCK-BASED SIGNAL DEMODULATION

SWITCHING CONFIGURATION FOR RECOVERING DATA CONTAINED IN BINARY DATA SIGNALS.

SYSTEM AND PROCEDURE FOR ACTIVE LEITUNGSABSCHLUSS

SWITCHING CONFIGURATION FOR THE LEVEL-DEPENDENT CONTROLLING OF THE RECEIPT EVALUATION OVER A CHANNEL OF TRANSFERRING AND AFTERWARDS EVALUATIONS BINARY OF CODINGS OF DIRECT CURRENT SIGNALS

DATA COMMUNICATION OF MEANS OF SWITCHED RESONANCE.

METHOD AND APPARATUS FOR DESYNCHRONIZING A DS-3 SIGNAL AND/OR AN E3 SIGNAL FROM THE DATA PORTION OF AN STS/STM PAYLOAD

Non-linear transmission line using varactors and non-parallel waveguide

Data communication system

A communication system (100) is configurable to operate in either a transparent mode or a data streaming mode. In the transparent mode data is transferred to a data requesting component (112) from a data source (102) using a request-response protocol. In the data streaming mode a second data transfer component (106) is configured to obtain data from the data source component via a third data link (104), and to transfer the data to a first data transfer component (110) via a second data link (108), which has a relatively higher latency, without using the request-response protocol. The first data transfer component is configured to store the transferred data and to transfer the stored data to the data requesting component via a first data link (114) upon receiving a request for the stored data from the data requesting component.

SYSTEM AND METHOD FOR TRANSMISSION-LINE TERMINATION BY SIGNAL CANCELLATION, AND APPLICATIONS THEREOF

An active terminating device (30) for an electrical transmission line with optional line-receiving and line-driving capabilities is disclosed. The basic device is a two-terminal unit, denoted as a Signal Canceling Unit (SCU), which senses the signal available at its terminals (34a, 34b), and applies negative feedback in order to cancel and absorb the signal. When applied to the end of a transmission line (15a, 15b) as part of wired communication network, the SCU functions as a terminator. When connected in the middle of such wired transmission line, the SCU splits the transmission line into two separate and isolated segments. In such a configuration, the SCU can be used to isolate a portion of a network from signal degradation due to noise or bridge-tap. Furthermore, the two isolated segments may each employ independent communications, such that no interference exists between the segments. In another embodiment, line receiver functionality is integrated into the SCU, designated as a Signal ...

DIGITAL INFORMATION TRANSMISSION SYSTEM

Digital information transmission system components including at least one unit arranged to transmit signal elements in parallel, at least one unit arranged to receive signal elements in parallel, and a corresponding plurality of signal transmission paths connected between such units to each convey a respective one of the signal elements, in which a unit serving to transmit such signal elements is constructed for selectively creating, in each path, a signal element in the form of a signal state representing either one of two binary values or a signal state different from that representing either such binary value; and a unit serving to receive such signals is constructed for producing a response which distinguishes between the appearance, in each path, of either binary value state or the different state.

TELECOMMUNICATION SYSTEM FOR TRANSMITTING DATA INFORMATION BY MEANS OF A DIGITAL EXCHANGE

MULTICONFIGURABLE INTERFACE FOR A COMPUTER PRINTER

MULTICHANNEL SOFTWARE DEFINED RADIO RECEIVER WITH OPTICALLY ISOLATED ADC

A high speed split receiver interface system for sensing a series of external signals, the system including: a series of remote radio head units for receiving a sensed signal in an analog electric form, each of the remote radio head units converting their sensed signal to a corresponding digital electrical form and then to a corresponding optical data form for dispatch over an optical data interconnection; at least one optical interconnect interconnecting each remote radio head unit with a baseband unit; a first baseband unit interconnecting the series of remote head units corresponding optical interconnects, and including a converter for conversion of the received optical signals to corresponding electrical digital form and down sampling the optical signals to corresponding down sampled signals, a memory store for storing the down sampled signals, and an external network interface for transmission of the saved signals to an external device.

METHOD AND SYSTEM FOR REDUCING A TIME SKEW BETWEEN TWO POLARITIES OF A DIFFERENTIAL SIGNAL

A method and system for reducing a time skew between two polarities of a differential signal representing a digital bit stream are provided. The system has a variable delay for inserting a variable time delay into polarities of the differential signal to produce a deskewed signal; a multi-phase clock for generating a number M of clock phases per bit of the digital bit stream for oversampling the deskewed signal into a digital representation of the deskewed signal; a logic circuit for estimating the quality of the digital representation of the deskewed signal; and a means for adjusting the variable delay in response to the estimated quality of the digital representation of the deskewed signal to improve the quality. A corresponding method is also provided.

METHOD OF SIGNAL GENERATION AND SIGNAL GENERATING DEVICE

A transmission method simultaneously transmitting a first modulated signal and a second modulated signal at a common frequency performs precoding on both signals using a fixed precoding matrix and regularly changes the phase of at least one of the signals, thereby improving received data signal quality for a reception device.

METHOD AND DEVICE FOR TRANSMITTING SIGNALS IN DIGITAL FORM

Pour simplifier la transmission à une station éloignée de signaux reçus par des capteurs divers, on leur associe un module électronique local transformant les signaux analogiques reçus en un train de bits codés qui est émis sans aucun formatage préalable sur une voie de transmission, et, à la station éloignée, on les décode avant de les appliquer à un filtre numérique reconstituant les signaux reçus sous la forme de séries d'échantillons numérisés. Application à la transmission de données sismiques par exemple.

Telegraphenanlage.

Verfahren zur Aussendung binärer Signale über einen gleichstromundurchlässigen Übertragungsweg

Anlage zur Übertragung von impulsförmigen Informationen

Anordnung zur Uebertragung von Impulsen

PROCEDURE FOR THE UMKODIEREN OF A CONSEQUENCE OF DATA BITS INTO A CONSEQUENCE OF CHANNEL BITS.

METHOD OF PRELIMINARY CODING AND TRANSMITTING DEVICE

СИСТЕМА И СПОСОБ ВНУТРИПОЛОСОВОГО МОДЕМА ДЛЯ ПЕРЕДАЧИ ДАННЫХ ПО ЦИФРОВЫМ БЕСПРОВОДНЫМ СЕТЯМ

Обеспечивается система для передачи информации с помощью речевого кодека (внутри полосы пропускания), например, который проявляется в беспроводной сети связи. Модулятор преобразует данные в спектрально шумоподобный сигнал на основе преобразования формируемого импульса в заранее заданные позиции в пределах кадра модуляции, и данный сигнал эффективно кодируется с помощью речевого кодека. Последовательность синхронизации обеспечивает временное распределение кадра модуляции в приемнике и выявляется на основе анализа схемы пиков корреляции. Протокол запроса / ответа обеспечивает надежную передачу данных с использованием избыточности сообщения, повторной передачи и / или устойчивых режимов модуляции в зависимости от условий канала связи.

УСТРОЙСТВО ДЛЯ АВТОМАТИЧЕСКОЙ ИДЕНТИФИКАЦИИ РАДИОТЕЛЕФОННЫХ ПЕРЕДАЧ С ПОВЫШЕННОЙ УСТОЙЧИВОСТЬЮ К МЕЖСИМВОЛЬНЫМ ИСКАЖЕНИЯМ

Изобретение относится к области радиосвязи и может применяться в судовых и авиационных УКВ радиостанциях связи для автоматической идентификации сотовых передач. Содержит передатчик, приемник, блок хранения данных идентификации, блок кодирования, блок встраивания информации, блок декодирования, блок выделения информации и мини-дисплей данных идентификации. Работа устройства основана на встраивании в звуковой сигнал данных идентификации передающего судна в виде цифрового водяного знака. Для повышения помехоустойчивости межсимвольных искажений используют технологию OFDM. Обеспечивает повышенную надежность и достоверность идентификации в автоматическом режиме за время 1,25 секунды без изменения базового состава радиоаппаратуры и эксплуатационных процедур радиосвязи.

СПОСОБ РЕГУЛИРОВАНИЯ ПОЛОСЫ ПРОХОЖДЕНИЯ АКТИВНОГО ПОЛОСОВОГО LRC-ФИЛЬТРА

Способ регулирования полосы прохождения активного полосового LRC-фильтра для получения определенной полосы частот использует активный полосовой LRC-фильтр. Индуктивности и емкости, включенные в параллельном и цепном резонансном контурах, не равны, соответственно, друг другу, а изменяются в пределах широкого диапазона значений, выдерживая условие равенства друг другу резонансных частот параллельного и цепного резонансных контуров при всех новых значениях индуктивности и емкости. Изобретение касается отрасли радиотехники и автоматики, в частности, автоматических систем управления.

СПОСІБ ТА ПРИЙМАЧ ДЛЯ МОНІТОРИНГУ ЯКОСТІ ІНФОРМАЦІЇ У БЕЗПРОВІДНОМУ КАНАЛІ ЗВЯЗКУ, СПОСІБ ВИЗНАЧЕННЯ ПОЛЯРНОСТІ БІТІВ КЕРУВАННЯ ПОТУЖНІСТЮ, А ТАКОЖ СПОСІБ МОНІТОРИНГУ ЯКОСТІ СУБКАНАЛУ КЕРУВАННЯ ПОТУЖНІСТЮ ТА ПРИСТРІЙ КОНТРОЛЮ ЧАСТОТИ ПОЯВИ ПОМИЛОК У ТАКОМУ СУБКАНАЛІ

Спосіб та приймач для моніторингу якості інформації у безпровідному каналі зв'язку, спосіб визначення полярності бітів керування потужністю а також спосіб моніторингу якості субканалу керування потужністю та пристрій контролю частоти появи помилок у такому субканалі використовуються в умовах безпровідного зв'язку, коли необхідно вести моніторинг якості передачі каналів зв'язку для підтримання ефективності роботи системи. Винахід стосується способу вимірювання частоти появи хибних бітів при прийомі без зниження пропускної здатності каналу доданням даних для моніторингу якості у сигнал при його передачі. Використовуючи відому інформацію, наприклад пілотні символи, для обчислення частоти появи хибних бітів, винахід забезпечує моніторинг якості передачі без витрати для цього частотної смуги каналу. Щоб виконати моніторинг без фактичного вимірювання помилок, можливе генерування наближеної частоти появи хибних бітів шляхом обробки відомої інформації про канал подібно до обробки каналу, що знаходиться ...

Радиочастотное устройство связи, способ и система связи

Изобретение относится к энергетике, в частности к радиочастотным устройствам связи для линий электропередач. Радиочастотное (РЧ) устройство связи соединено с шунтовым устройством и РЧ модемом для передачи РЧ сигнала. РЧ сигнал производится между линией электропередач и РЧ модемом посредством шунтового устройства и устройства связи. Шунтовое устройство снабжено клеммой высокого напряжения, подключенной к электрическому проводу линии электропередач и к клемме низкого напряжения. Устройство связи содержит проводник сигнала, подключенный к клемме низкого напряжения шунтового устройства, заземляющий проводник, соединенный с заземлителем, и связующий трансформатор. П. формулы: 23 Фиг.: 8 ...

СИСТЕМА ВЫЗОВА СЕРВИСНОГО ПЕРСОНАЛА

Система вызова обслуживающего персонала, в которой для связи между клиентским постом и центральным блоком используют радиоканал.

System and method for transmission and detection of frame including bursts of pulses

Jitter compensation and generation in testing communication devices

Methods, system, and computer programs for compensating for jitter in a communication system are described. A transfer function of a transmission medium is measured and an output signal that results from propagating an input signal through the transmission medium is calculated. Data dependent jitter is determined in the output signal. In memory, compensated edge positions of the input signal are stored. The compensated edge positions are arranged such that the data dependent jitter causes edge positions of the output signal to move closer to ideal edge positions.

Methods and apparatus for adapting channel estimation in a communication system

Methods and apparatus for adapting a channel estimation scheme in a transceiver in a communication system are disclosed to adapt channel estimation to the transceiver environment, particularly for high Doppler environments. The disclosed methods and apparatus effect determination of an estimate of a power delay profile of a channel or a time correlation of the channel, or both. A channel estimation scheme is then determined based on at least one of the determined power delay profile and time correlation of the channel. By basing determination of a channel estimation scheme on the power delay profile and/or the time correlation of the channel, the channel estimation scheme is adapted to the particular environment of the transceiver by accounting for the delay spread of the channel and/or the speed of the transceiver.

Channel state information reference signal (CSI-RS) handling for network assisted interference cancellation

METHOD Of ESTIMATE PLUGS PARAMETERS OF MODULATION OFDM ACCORDING TO a CRITERION OF MAXIMUN OF PROBABILITY.

Telegraphic transmission of processor information - employs electronic switching circuit to transmit binary information to distant peripheral

MICROWAVE RADIO MODEM MULTI-CHANNEL BASED ON MULTI-CARRIER MODULATION

METHOD OF TRANSMITTING DATA THROUGH A TELECOMMUNICATION NETWORK

CIRCUIT Of ATTACK FOR LINE OF TRANSMISSION

DATA TRANSMISSION SYSTEM

METHOD OF TRANSMITTING DATA THROUGH A TELECOMMUNICATION NETWORK

L'invention concerne un procédé de contrôle des échanges de flux de données entre au moins une source connectée à un réseau de télécommunication étendu hybride via un réseau d'accès local et au moins un destinataire connecté audit réseau de télécommunication étendu via un réseau d'accès distant. Ce procédé comporte les étapes consistant à : établir de nouvelles règles de transfert par l'analyse des flux, créer dynamiquement au moins un chemin supplémentaire d'échange des flux à partir de nouvelles règles de transfert et des règles d'accès en vigueur, à appliquer sur ledit chemin supplémentaire des mécanismes de fiabilisation, de sécurisation et d'optimisation des transferts des flux entre le réseau d'accès local et le réseau d'accès distant, et, transférer chaque nouveau flux au destinataire via le chemin supplémentaire selon les nouvelles règles de transfert.

Assembly for telegraphic apparatuses with commutation of batteries

PULSE TRANSFER SYSTEM

ACTIVE TERMINATING DEVICE WITH OPTIONAL LINE-RECEIVING AND LINE-DRIVING CAPABILITIES

Accessory control interface

TELECOMMUNICATION SYSTEM TO TRANSMIT INFORMATION VIA A DATA EXCHANGE THE DIGITAL

Block-based principal component analysis transformation method and device thereof

The present invention provides a block-based principal component analysis transformation method and a device thereof. The principal component analysis transformation method includes: obtaining an input signal; dividing the input signal and obtaining a plurality of one-dimension vectors corresponding to the divided input signal, wherein a number of the one-dimension vectors is a division number; after arranging the one-dimension vectors to a two-dimension vector, subtracting an average value of the one-dimension vectors of the division number to obtain a zero-mean vector; calculating a covariance matrix of the zero-mean vector; calculating an eigenvector of the covariance matrix; multiplying the eigenvector by the covariance matrix to obtain a projection coefficient.

Baseband processing apparatus and baseband processing method based on orthogonal frequency-division multiplexing

Embodiments relate to a baseband processing apparatus and a baseband processing method based on orthogonal frequency-division multiplexing (OFDM). In order to solve the problem of high PAPR in OFDM systems, the baseband processing apparatus and method generate a plurality of data with different peak to average power ratios (PAPRs) by modifying bit representations of the frozen bits used by a polar encoder, and then select the one of the plurality of data with the smallest PAPR as an OFDM signal.

Digital data transmission apparatus

To provide a digital data transmission apparatus possessing transmission rate more than 1 Gbit/sec per communication channel. The digital data transmission apparatus 20 comprises a transmission circuit, a hybrid circuit, an adjustable echo-cancel circuit, a receiving circuit, and an adjustment circuit. The transmission circuit 10 possesses an adjustable pre-emphasis circuit in the digital data transmission apparatus formed in the way of multi-valued transmission. The resistive-matrix circuit forms the hybrid circuit 12 to adjust the balance. The receiving circuit 15 possesses the distortion-correction circuit for analog signal processing. According to the genetic algorithm, the adjustment circuit 18 adjusts each circuit. Eventually, the digital data transmission apparatus possesses the transmission rate more than 1 Gbit/sec per communication channel.

STOCHASTIC INTERFERENCE CANCELLATION

Apparatuses, systems, and methods are disclosed for stochastic interference cancellation. A digital signal processor (150) decodes a set of transmitted signals based on a set of received signals. A projection module (202) updates a subset of a set of estimated signals based on error information and on a corresponding subset of mapping information. Error information is based on the received signals and the set of estimated signals. Mapping information indicates how the received signals are affected by the transmitted signals. A stochastic update module (204) adjusts the set of estimated signals based on generated noise. An interference cancellation module (206) updates the error information based on the adjusted estimated signals.

DIGITAL BASEBAND PROCESSING CONTROLLER AND BASEBAND REAL TIME CONTROL METHOD

A digital baseband processing controller, which is used in a digital baseband processing system to real-time control digital baseband, includes: a counter unit, for providing basic time and frame count for said digital baseband processing system; a register unit connected to said counter unit and an event processing unit, for deploying control information required by said counter unit and event processing unit ,and preserving status information and/ or data generated in course of event processing unit executing event; the event processing unit including event memory for preserving event microcode, operation and control module. according to said count value and control information, at specified time the operation and control module begin reading said event microcode, carry out decoding and execute corresponding event, complete control on other hardware module operation in system. Present invention could realize real-time control for digital baseband, and does not need the cost of DSP or ...

SYSTEM AND METHOD FOR TRANSMISSION AND DETECTION OF FRAME INCLUDING BURSTS OF PULSES

A method of transmitting and receiving data frames using pulses is disclosed. According to the transmitting method, a first signal is transmitted including one or more bursts of pulses during a first portion of a transmission frame, and not transmitting the first signal during a second portion of the transmission frame. The not transmitting the first signal may include maintaining one or more silence periods for the second portion of the transmission frame, or transmitting a second signal distinct from the first signal. According to the receiving method, a signal including one or more bursts of pulses is received during a first portion of a transmission frame, an analysis of the one or more bursts of pulses is performed, and the transmission frame is detected based on the analysis of the one or more bursts of pulses.

CHANNEL ESTIMATION IN A WIRELESS COMMUNICATION NETWORK

A wireless device (14) receives a downlink reference signal (24) from a radio network node (12) over a downlink channel (16), and determines channel information (28) based on measurement of the downlink reference signal (24). The wireless device (14) then transmits, to the radio network node (12) over an uplink channel (18), an uplink signal (30) that implicitly conveys the determined channel information (28). The radio network node (12)jointly (i) identifies which candidate uplink signal in a set (32) of candidate uplink signals (30-1...30-N) is received; and (ii) determines an estimate (42) of the uplink channel (18) from the received uplink signal (30). The radio network node (12) determines the channel information (28) implicitly conveyed by the identified candidate uplink signal, and then determines an estimate (22) of the downlink channel (16) based on the determined channel information (28)and the determined estimate (42) of the uplink channel (18).

Detection arrangement, counter unit, phase locked loop, detection method and method for generating an oscillator signal

A detection arrangement includes a counter unit which receives a first clock signal and a reference clock signal. The counter unit derives a first data word as a function of a time deviation between clock edges of the first clock signal and the reference clock signal. The detection arrangement further includes a signal processing unit to determine a phase deviation word as a function of the first data word and a second data word, the second data word based on the duration of a clock period of the reference clock signal.

Power Line Communication System and Method

A power line communications system for providing communications for one or more user devices via one or more low voltage power line is provided. In one embodiment the system includes a plurality of first communication devices, each comprising a first modem configured to communicate using a DOCSIS protocol, and a first low voltage power line interface configured to communicate with a plurality of user devices via a low voltage power line. A second communication device includes a backhaul link interface configured to communicate over a backhaul link and a downstream interface configured to communicate with the first modems of the plurality of first communication devices. The plurality of first communication devices transmit upstream data signals in a first frequency band and receive downstream data signals in a second frequency band different from the first frequency band.

Analog circuit for baseband modem

So as to be directly connected to the predefined logic circuit PLC to form a baseband modem, the analog circuit BBAC is monolithically integrated in accordance with the CMOS technology, using switched-capacitor filters which are driven by only one clock. The automatic equalizer EGA is likewise designed from switched-capacitor filters, equalization being obtained by variable and symmetrical clipping of the signals. In these conditions the modem can operate automatically in a very wide range of data rates.

Phase synchronization method for extended partial response, and phase synchronization circuit and read channel circuit using this method

... “100”, which is one of the (1, 7) RLL codes, is used as a clock acquisition pattern. After temporarily judging the sample output to be one of (1, −1), the phase error computing result for three samples (symbols) is added so as to cancel the errors of phase computing. Therefore the number of judgment states can be decreased, and phase can be acquired at high-speed even if the amplitude at acquisition has not been defined. At tracking, the sample output is judged to be one of three groups, [1+a, 1], 0, and [−1, −1−a]. Using the state transition of (1, 7) RLL codes, [1+a, 1] and [−1, −1−a] are distinguished. Since the number of judgment states decreases, judgment accuracy improves.

Method for solving high PAPR problem of MCM communication system using unitary transform

The method contains the following steps. First, in a MCM system with N sub-carriers, the baseband signal blocks Xj, j=1, 2, . . . ,B are supplemented with zeros and processed with LN-point IFFT, respectively, to obtain L-time oversampled time-domain signal blocks xj, j=1,2, . . . ,B. Then, xj undergoes Q Time Domain Circular Shifts or Frequency Domain Circular Shifts to obtain Q signal blocks {tilde over (x)}j(ij), ij=1, , Q. Subsequently, a B×B unitary transform is performed against ( x1, {tilde over (x)}2(i2), . . . , {tilde over (x)}B(iB)). After the unitary transform, for each (i2, . . . , iB) a combination having B time-domain signal blocks is obtained as follows: ({tilde over (y)}1(i2, . . . , iB), {tilde over (y)}2(i2, . . . , iB), . . . , {tilde over (y)}B(i2, . . . ,iB))=( x1, {tilde over (x)}2(i2), . . . , {tilde over (x)}B(iB)) cU where U is the B×B unitary matrix, and c is an arbitrary constant (c0). Finally, the total QB1 combinations are compared against each other to select ...

Replica driver mismatch correction using a variable offset comparator

A number of data symbols are driven into a transmission line while simultaneously driving the data symbols into another node. A difference between a signal level from the transmission line and a signal level from the other node while driving the symbols is determined. The difference is applied to a signal input of a variable offset comparator. One of a number of binary values (offset codes) are applied to an offset control input of the comparator, to adjust an implied, variable reference level of the comparator, prior to the comparator performing a comparison between the input signal and the implied reference level.

Sequential frequency band acquisition apparatus for test and measurement instruments

An acquisition apparatus for a test and measurement instrument includes an input to receive an input signal, a digitizer to digitize a selected signal, a bypass path to selectively couple the input to the digitizer, a frequency shift path to frequency shift the input signal and selectively couple the frequency-shifted input signal to the digitizer, the frequency shift path including a means for frequency shifting, an input switch to switch the input signal to one of the bypass path and the frequency shift path, and an output switch to provide the selected signal to the digitizer by selectively coupling an output of one of the frequency shift path and the bypass path to the digitizer.

Circuit to reduce power supply fluctuations in high frequency/high power circuits

A circuit for transitioning clocking speeds, or frequencies, is provided. With this circuit, a clocking circuit providing a first clock signal at a first clock frequency is coupled to a counter. A comparator and a first divider are coupled to an output of the counter. The first divider outputs a second clock signal at a second clock frequency. A second divider is interposed between the clocking circuit and the counter. A processor is coupled to an output of the first divider.

Bit slip circuitry for serial data signals

Circuitry for use in aligning bytes in a serial data signal (e.g., with deserializer circuitry that operates in part in response to a byte rate clock signal) includes a multistage shift register for shifting the serial data signal through a number of stages at least equal to (and in many cases, preferably more than) the number of bits in a byte. The output signal of any shift register stage can be selected as the output of this bit slipping circuitry so that any number of bits over a fairly wide range can be slipped to produce or help produce appropriately aligned bytes. The disclosed bit slipping circuitry is alternatively or additionally usable in helping to align (deskew) two or more serial data signals that are received via separate communication channels.

4-20 mA interface circuit

A valve controller is disclosed. The valve controller includes an interface circuit having an input for connection to a controller, a processor in data communication with the interface circuit which is operable to generate a control signal for controlling a valve position, and a control device operable to control the valve position in response to the control signal from the processor. The interface circuit includes a power extraction circuit connected to the controller and is further operable to generate a DC operating voltage for use in powering the interface circuit and the processor. The interface circuit includes a current sensor connected to the controller and is further operable to generate a measure of a current from the controller, the measure being used in controlling a device associated with the interface circuit. The interface circuit also includes a digital communications circuit connected to the controller and is further operable to transmit and receive communication signals ...

RECEIVER AND METHOD OF OPERATING THE SAME

СПОСОБ И УСТРОЙСТВО ДЛЯ ГИБРИДНОЙ КОРРЕКЦИИ С РЕШАЮЩЕЙ ОБРАТНОЙ СВЯЗЬЮ

Изобретение относится к области беспроводной связи для коррекции принятого сигнала. Технический результат: уменьшение линейных искажений, распространения ошибок в эквалайзере с решающей обратной связью. Предложены способ и устройство для эквалайзера с решающей обратной связью, в которых используется поправочный член для компенсации ошибок ограничителя, чтобы исключить распространение ошибок. Коэффициенты фильтров для эквалайзера выбираются таким образом, чтобы минимизировать функцию стоимости для эквалайзера, включая поправочный член как функцию энергии коэффициентов фильтров. Эквалайзер содержит генератор коэффициентов, чувствительный к поправочному члену. В одном варианте переданный символ из принятой выборки оценивается как функция отношения сигнал/помеха + шум (SINR) принятой выборки. Принятая выборка квантуется и отображается в области сигнальной совокупности на сетке, наложенной на переданную совокупность символов. Эта область может соответствовать оценочному значению символа или ...

СПОСОБ ПЕРЕДАЧИ ДАННЫХ И СИСТЕМА ДЛЯ ОСУЩЕСТВЛЕНИЯ СПОСОБА

... 1. Способ передачи информации, при котором в состав передающего сигнала входят по меньшей мере одна несущая частота в качестве опорной компоненты (ВК) и по меньшей мере одна несущая частота в качестве информационной компоненты (I1; I2; . . . ; IN), причем по меньшей мере одна из этих несущих частот испытывает непрерывное изменение своего значения в процессе передачи порции информации и, кроме того, опорная компонента (ВК) и информационная компонента (I1; I2; . . . ; IN) формируют соответствующие дискретные состояния для формирования битового шаблона. 2. Способ по п. 1, отличающийся тем, что по меньшей мере одна опорная компонента и по меньшей мере одна информационная компонента испытывают непрерывное изменение частоты во времени, причем между частотами опорной и информационной компонент задается определенное соотношение в соответствии с заранее заданной функцией времени. 3. Способ по п. 2, отличающийся тем, что частотные расстояния между компонентами являются постоянными или испытывают ...

РЕКОНФИГУРИРУЕМОЕ КОДИРОВАНИЕ ДЛЯ НЕСКОЛЬКИХ СТАНДАРТОВ СВЯЗИ

... 1. Устройство для реконфигурируемого кодирования для нескольких стандартов связи, содержащее: ! первую схему, сконфигурированную для (i) получения сигнала конфигурации, который идентифицирует текущий из множества стандартов связи и (ii) генерирования множества матричных элементов на основе вышеупомянутого сигнала конфигурации; и ! вторую схему, включающую в себя множество матриц и сконфигурированную для (i) заполнения указанных матриц матричными элементами и (ii) генерирования закодированного сигнала посредством кодирования входного сигнала с упреждающим исправлением ошибок с использованием названных матриц, где названный закодированный сигнал соответствует вышеупомянутому текущему стандарту связи. ! 2. Устройство по п.1, отличающееся тем, что названная первая схема дополнительно сконфигурирована для изменения конфигурации названной второй схемы среди названных стандартов связи в ответ на изменение вышеупомянутого сигнала конфигурации. ! 3. Устройство по п.2, отличающееся тем, что названное ...

МОДЕМНОЕ ОБОРУДОВАНИЕ ДЛЯ ПЕРЕДАЧИ И ПРИЕМА ШИРОКОПОЛОСНЫХ СИГНАЛОВ С КВАДРАТУРНО-АМПЛИТУДНОЙ МОДУЛЯЦИЕЙ С ПРИМЕНЕНИЕМ ТУРБОКОДЕКА

Модемное оборудование для передачи и приема широкополосных сигналов с квадратурно-амплитудной модуляцией с применением турбокодирования, состоящее из модулятора и демодулятора и блоков формирования опорной частоты, синтезатора и микропроцессора управления, отличающееся тем, что, с целью ! - повышения помехоустойчивости (понижения отношения Eb/No достаточного для достижения заданной достоверности, где Eb - энергия бита; No - спектральная плотность мощности аддитивного белого шума); ! - снижения полосы занимаемой сигналом в эфире; ! - возможности работы с модуляцией QAM, в том числе с многоуровневыми QAM (т.е. QAM 16, QAM 64, QAM 128, QAM 256) в схему введены: ! - дополнительный фазовращатель (деротатор), на вход которого подается выходной сигнал согласованного фильтра, а выход подсоединен к входу турбодекодера и к входу фазового дискриминатора ФАП, исполнительным стройством которой является упомянутый фазовращатель; ! - дополнительный генератор тактов, выход которого подсоединен к выходу ...

СПОСОБ МОДУЛЯЦИИ СИГНАЛА, ПРИЕМНО-ПЕРЕДАЮЩЕЕ УСТРОЙСТВО, СИСТЕМА ПЕРЕДАЧИ ИНФОРМАЦИИ

... 1. Способ модуляции радиоимпульсов s(t), описываемых выражением s(t)=sin(α0· ln(t)), где параметр α0>0, t∈[τ1, τ2] - время, τ1 - время начала радиоимпульса, τ2 - время окончания радиоимпульса, позволяет работать в занятых частотных диапазонах радиоэфира и не создавать помех в работе других систем и устройств, использующих в своей работе радиосигналы. 2. Устройство передачи последовательности радиоимпульсов s(t), описываемых выражением s(t)=sin(α0· ln(t)), где параметр α0>0, t∈[τ1, τ2] - время, τ1 - время начала радиоимпульса, τ2 - время окончания радиоимпульса. 3. Устройство приема радиоимпульсов вида s(t)=sin(α0·ln(t)) представляет собой корреляционный приемник, в котором входной радиосигнал без его частотного преобразования перемножается с опорным сигналом son(t), описываемым выражением , где параметр α0>0, значение которого совпадает со значением параметра α0 в передаваемом радиоимпульсе, t∈[0, τ] - время, τ - длительность опорного сигнала, равная длительности передаваемого радиоимпульса ...

Устройство для преобразования формата телеграмм

Изобретение относится к технике телеграфной связи. По отношению к авт. ев, № 1197126 достигается цель изобретения -- повышение верности передачи . содержит ленточный телеграфный аппарат 1, вызывной узел 2, два элемента ИЛИ 3 и 21, пуско- остановочный узел 4, входной и выходной согласующие блоки 5 и 7, стартстопный распределитель 6, накопитель 8, счетчик 9 знаков, пять дешифраторов 10, 11,15, 16 и 17 комбинаций, три элемента И 12, 13 и 19, Фриггер 14, датчик 18 комбинаций , инвертор 20 и блок 22 управления . Цель достигается введением эл- та И 19, инвертора 20 и эл-та ИЛИ 21, с помощью которых при обнаружении в передаваемой информации комбинаций цифрового, латинского или русского регистров устр-во не фиксирует их как переданный информационный знак. В результате этого счетчик 9 подсчитывает только информационные знаки. I ил. i (Л ...

Устройство передачи и приема дискретной информации

Изобретение относится к технике электросвязи . Цель изобретения - сокращение времени передачи и приема. На передающей стороне дополнительно введены формирователь 8 сигнала, анализатор 10 информации, блок 11 памяти пакета квитанций , регистр 13 и генератор 14 последовательности двоичных сигналов, а на приемной стороне - дешифратор 22, регистр 23, анализатор 24 сигналов и таймер 25. На передающей стороне информация от источника 1 записывается во входной накопитель 2. Если информация есть, то анализатор 10 управляет через коммутатор 3 передачей этой информации в канал через выходной согласующий блок 5. При этом блок 9 формирует разряды, относящиеся к служебной информации, которая информирует потребителя о запросе информации на приемной стороне. Если информация прекращается , то анализатор 10 управляет включением режима повтора. На приемной стороне информация поступает на вход декодирующего блока 16. После обработки информация передается потребителю 21 информации. 1 ил. ё ...

Объединенная сеть документальной связи

Изобретение относится к телеграфной связи. Цель изобретения - расширение функциональных возможностей путем увеличения номенклатуры сетей и числа абонентов. Сеть содержит центральный узел 1 коммутации, станции 2 и 3 коммутации, преобразователь 4 сигналов, выходной преобразователь 5 телеграфных сигналов, входной преобразователь 6 телеграфных сигналов, преобразователь 7 фиксимильных сигналов, оконечные блоки 8, 9, 10 и 13, выходной 11 и входной 12 преобразователи телеграфных сигналов. Передача осуществляется с помощью коммутационной станции 3 коммутации, которая реализует принцип коммутации каналов. В основе его - предварительное по адресу соединение корреспондентов с последующей передачей сообщения. С оконечного блока 9 сети телекс вызывающего корреспондента производится выдача сигнала вызова, который по каналу связи поступает на станцию 3 коммутации, с которой по обратному каналу поступает сигнал "Приглашение к набору". Станция 3 производит по принятому адресу коммутацию, соединяя выход ...

Verfahren und Vorrichtung zur Verwendung bei einer Entscheidungsrückgekoppelten Entzerrung

Method and Device of Sending and Receiving Precoding Information

The present invention discloses a method and a device of sending and receiving precoding information. A terminal terminal obtains a wideband precoding matrix indicator PMI. The terminal encodes an MSB of the wideband PMI to obtain encoded information. The MSB of the wideband PMI is encoded separately or jointly with other information and the MSB is a part of the wideband PMI. The terminal sends encoded information to a data sending end. 1. A method of sending precoding information , the method comprising:obtaining, by a terminal, a wideband precoding matrix indicator (PMI);encoding, by the terminal, an MSB of the wideband PMI to obtain encoded information, wherein the MSB of the wideband PMI is encoded separately or is encoded jointly with other information of N bits, wherein the MSB is a part of the wideband PMI and N is a natural number; andsending, by the terminal, the encoded information to a data sending end.2. The method according to claim 1 , wherein the encoding comprises jointly encoding the MSB of the wideband PMI and a rank indication RI.3. The method according to claim 1 , wherein the encoding comprises jointly encoding the MSB of the wideband PMI and acknowledgment information of a hybrid automatic retransmission request HARQ.4. The method according to claim 1 , wherein sending the encoded information to the data sending end comprises sending the the encoded information through a physical uplink control channel PUCCH or a physical uplink shared channel PUSCH.5. The method according to claim 4 , wherein the terminal sends the encoded information through the physical uplink shared channel PUSCH and the encoded information is mapped to a position that is on two sides of a demodulation pilot or reference signal and is adjacent to the demodulation pilot or reference signal through a channel interleaver.6. The method according to claim 4 , wherein the PUSCH adopts multiple input multiple output MIMO multi-layer transmission and the encoded information is ...

Apparatus, systems, methods, and computer products suitable for use in an advanced digital baseband processor

The present disclosure relates to an advanced digital baseband processor for a base station in a cellular communications network. In general, the advanced digital baseband processor integrates multiple Radio Access Technologies (RATs). As used herein, a RAT is a radio access technology as defined by a corresponding standard. For example, in one embodiment, RATs integrated by the advanced digital baseband processor include a Code Division Multiple Access (CDMA) voice RAT (e.g., 3GPP2 CDMA 1xRTT or 3GPP2 CDMA 1xAdvanced) as well as a CDMA Data Only, or Data Optimized, (DO) RAT (e.g., 3GPP2 CDMA EV-DO or 3GPP2 CDMA EV-DO Rev B). In another embodiment, the RATs integrated by the advanced digital baseband processor also include 3GPP Long Term Evolution (LTE). The RATs given above are only examples. The advanced digital baseband processor may integrate additional or alternative RATs.

DRIVING DATA OF MULTIPLE PROTOCOLS THROUGH A SINGLE SET OF PINS

Embodiments of the invention are generally directed driving data of multiple protocols through a single set of pins. An embodiment of an apparatus includes a transmitter connected to two pads on an IC the transmitter including a differential driver to transmit a differential signal, wherein the differential driver has a first branch and a second branch, each branch of the differential driver including a protection device connected to one of the pads; and a common mode driver to transmit a common mode signal, the common mode driver having a first branch and a second branch, each of the branches of the common mode driver including a protection device connected to one of the pads. The first and second switch devices are not turned on simultaneously, based on data to be transmitted, one of the switch devices being turned on and the other being turned off. The third and fourth switch devices are both turned on when the common mode signal is one of a logic HIGH or logic LOW and both turned off when the common mode signal is the other of a logic HIGH or logic LOW. 127-. (canceled)28. An apparatus comprising: a differential driver to transmit a differential signal, wherein the differential driver has a first branch and a second branch, wherein each branch of the differential driver includes a protection device connected to one of the pads, the first branch of the differential driver having a first protection device and the second branch of the differential driver having a second protection device, each of the first and second protection devices having at least two terminals; and', 'a common mode driver to transmit a common mode signal, wherein the common mode driver has a first branch and a second branch, each of the first and second branches of the common mode driver including a protection device connected to one of the pads, the first branch of the common mode driver including a third protection device and the second branch of the common mode driver including a fourth ...

Low Power Based LTE Receiver Architecture

Providing a power-saving mode for control channel monitoring in discontinuous reception (DRX) scenarios. Upon waking from a sleep mode at the conclusion of a DRX off period, a baseband modem may transition to a low-power mode configured to receive and decode only a control channel, such as a physical downlink control channel (PDCCH). If the control channel indicates during a DRX on period that communication traffic will be transmitted to the baseband modem, then the baseband modem may transition to a full-power mode to receive the communication traffic. Otherwise, the baseband modem may transition back to the sleep mode. The low-power mode may be implemented by a dedicated set of hardware configured to draw less power than a full set of hardware configured to implement the high-power mode. 1. A baseband modem comprising: a first processor;', 'a first memory; and', 'first baseband processing circuitry; and, 'a first subsystem configured to operate when the baseband modem is in a high-power mode and to not operate when the baseband modem is in a low-power mode, the first subsystem comprising a second processor, different from the first processor;', 'a second memory, different from the first memory; and', 'second baseband processing circuitry, different from the first baseband processing circuitry., 'a second subsystem configured to operate when the baseband modem is in the low-power mode and to not operate when the baseband modem is in the high-power mode, the second subsystem comprising2. The baseband modem of claim 1 , further comprising third baseband processing circuitry configured to operate when the baseband modem is in the high-power mode and when the baseband modem is in the low-power mode.3. The baseband modem of claim 1 , further comprising a third memory configured to operate when the baseband modem is in the high-power mode and when the baseband modem is in the low-power mode.4. The baseband modem of claim 1 , wherein the first subsystem and the second ...

METHODS AND APPARATUS FOR LOW POWER OPERATION UTILIZING MULTIPLE ADCs WITH DIFFERENT PRECISIONS

An electronic device includes processing circuitry configured to detect a presence of a packet transmission via a channel, establish communication parameters and operational settings of an analog-to-digital conversion (ADC) operation using a training field (TF) of the packet if the packet comprises the TF, and utilize a channel estimation (CE) portion of the packet to perform channel estimation of the channel. The processing circuitry is also configured to utilize the channel estimates to compensate for distortions introduced by the channel with respect to portions of the packet subsequent to the CE portion, obtain a modulation order and coding scheme used for the data portion of the packet, select an analog-to-digital converter (ADC) to be used for a recovery of the data portion of the packet, and recover the information in the data portion of the packet using ADC output samples corresponding to the data portion of the packet.

METHODS AND APPARATUS FOR SCHEDULING TIME SENSITIVE OPERATIONS AMONG INDEPENDENT PROCESSORS

Methods and apparatus for scheduling time sensitive operations among independent processors. In one embodiment, an application processor (AP) determines transmission timing parameters for a baseband processor (BB). Thereafter, the AP can generate and transact generic time-sensitive RTP data with the BB in time for transmission via a Long Term Evolution (LTE) communication stack. In this manner, the AP's scheduler can coordinate/accommodate digital audio tasks within the context of its other tasks (e.g., to enable intelligent sleep and wake-up operation, load balancing, memory usage, and/or any number of other processor management functions). 120.-. (canceled)21. A method for scheduling time-sensitive operations via first and second independently operable processors , the method comprising:obtaining, at a first independently operable processor, data relating to a temporal parameter associated with a wireless network, the obtaining of the data occurring via the second independently operable processor;generating, using at least the first independently operable processor, data for transmission over the wireless network via the second independently operable processor, the generating being based at least on (i) the temporal parameter associated with the wireless network, and (ii) a signal associated with the second independently operable processor.22. The method of claim 21 , wherein the obtaining the data relating to the temporal parameter comprises:requesting, from the second independently operable processor, data relating to one or more scheduling parameters associated with the wireless network; andreceiving at the first independently operable processor the data relating to the one or more scheduling parameters, the one or more scheduling parameters previously issued from an entity of the wireless network via the second independently operable processor.23. The method of claim 21 , wherein the obtaining the data relating to the temporal parameter comprises transferring ...

SIMULTANEOUS LVDS I/O SIGNALING METHOD AND APPARATUS

First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half. 1. A LVDS input circuit comprising:(a) a serial data out input;(b) a first, serial data in, low voltage differential signal lead;(c) a second, serial data in, low voltage differential signal lead;(d) a serial data in output;(e) an inverter having an input connected to the serial data out input and having an output; i. a first comparator having a non-inverting input connected to the first low voltage differential signal lead, an inverting input connected to the second low voltage differential signal lead, and a first control output, the first comparator requiring a voltage on the non-inverting input to be greater than a certain offset from a voltage on the inverting input before producing a logic high on the first control output; and', 'ii. a second comparator having a non-inverting input connected to the second low voltage differential signal lead, an inverting input connected to the first low voltage differential signal lead, and a second control output, the second comparator requiring a voltage on the non-inverting input to be greater than a certain offset from a voltage on the inverting input before producing a logic high on the second control output;, '(f) a window comparator including(g) a multiplexer having a first input coupled to a fixed logic high, a second ...

FACILITATION OF RANK AND PRECODING MATRIX INDICATION DETERMINATIONS FOR MULTIPLE ANTENNA SYSTEMS WITH APERIODIC CHANNEL STATE INFORMATION REPORTING IN 5G OR OTHER NEXT GENERATION NETWORKS

Facilitating rank and precoding matrix indication determinations for multiple antennas systems with aperiodic channel state information reporting in a wireless communications system is provided herein. A method can comprise determining, by a mobile device comprising a processor, first channel state data of a channel based on a periodic configuration of the mobile device for first transmissions of the first channel state data periodically. The method can also comprise in response to receiving, from the network node device, reference signal data associated with a reference signal, determining, by the mobile device, second channel state data of the channel based on an aperiodic configuration of the mobile device for second transmissions of the second channel state data aperiodically. Further, the method can comprise transmitting, by the mobile device, the aperiodic configuration of the mobile device to the network node device. 1. A user equipment device , comprising:a processor; and based on data selected from first channel state data for a channel, determining second channel state data for the channel; and', 'sending, to a network device, the second channel state data as an aperiodic configuration of the user equipment device., 'a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, comprising2. The user equipment device of claim 1 , wherein the determining the first channel state data of the channel based on the data selected from the second channel state data of the channel comprises reducing a complexity associated with aperiodic reporting according to a defined complexity criterion.3. The user equipment device of claim 2 , wherein the data selected from the first channel state data comprises first rank information of the second channel state data and a first precoding matrix index of the second channel state data claim 2 , and wherein the reducing the complexity comprises:determining second rank ...

N-PHASE PHASE AND POLARITY ENCODED SERIAL INTERFACE

System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Data is encoded in multi-bit symbols, and the multi-bit symbols are transmitted on a plurality of connectors. The multi-bit symbols may be transmitted by mapping the symbols to a sequence of states of the plurality of connectors, and driving the connectors in accordance with the sequence of states. The timing of the sequence of states is determinable at a receiver at each transition between sequential states. The state of each connector may be defined by polarity and direction of rotation of a multi-phase signal transmitted on the each connector. 1. A method for data communications , comprising:encoding data in multi-bit symbols; and mapping the multi-bit symbols to a sequence of states of the plurality of connectors, and', 'driving the connectors in accordance with the sequence of states, wherein timing of the sequence of states is determinable at a receiver at each transition between sequential states,, 'transmitting the multi-bit symbols on a plurality of connectors, wherein transmitting the multi-bit symbols includes'}wherein the state of each connector is defined by polarity and direction of rotation of a multi-phase signal transmitted on the each connector.2. The method of claim 1 , wherein for each state in the sequence of states claim 1 , the multi-phase signal carried on each connector is phase-shifted with respect to the multi-phase signal carried on the other connectors.3. The method of claim 1 , wherein the state of at least one of the plurality of connectors changes at each transition between the sequence of states.4. The method of claim 1 , wherein the plurality of connectors include a plurality of wires claim 1 , and wherein transmitting the multi-bit symbols on the plurality of connectors includes: leaving a first wire undriven, and', ' ...

SIGNAL TRANSMISSION SYSTEM, TRANSMITTER ENCODING APPARATUS AND RECEIVER DECODING APPARATUS

A transmitter encoding apparatus includes a multiplexer and a first transmitter encoder. The multiplexer receives a first digital signal and a second signal and to generate an output, in which the output of the multiplexer includes M-bit code words of the first digital signal and M-bit code words of the second digital signal arranged in an interleaved manner. The first transmitter encoder receives the output of the multiplexer and generates N-bit code words, and N is not equal to M. The first transmitter encoder determines a current N-bit code word of the N-bit code words according to the output of the multiplexer and a disparity of a previous N-bit code word of the N-bit code words. The first transmitter encoder transmits the N-bit code words to a receiver decoding apparatus including a demultiplexer and a first receiver decoder configured to decode the N-bit code words. 1. A signal transmission system , comprising: a multiplexer, configured to receive a first digital signal and a second digital signal and generate an output, wherein the output of the multiplexer comprises a plurality of M-bit code words of the first digital signal and a plurality of M-bit code words of the second digital signal, wherein the plurality of M-bit code words of the first digital signal and the plurality of M-bit code words of the second digital signal are arranged in an interleaved manner, and M is a positive integer; and', 'a first transmitter encoder, configured to encode the output of the multiplexer to generate a plurality of N-bit code words, wherein N is a positive integer and N is not equal to M, wherein the first transmitter encoder is configured to determine a current N-bit code word of the plurality of N-bit code words according to the output of the multiplexer and a disparity of a previous N-bit code word of the plurality of N-bit code words; and, 'a transmitter encoding apparatus comprising a first receiver decoder, configured to decode the plurality of N-bit code words to ...

NON-RECIPROCAL COMPONENTS WITH BALANCED DISTRIBUTEDLY MODULATED CAPACITORS (DMC)

A non-reciprocal radio frequency transceiver front end utilizing multiple time-varying transmission lines (TVTLs) implemented using distributed modulated capacitors (DMC) to exploit time-varying properties of transmission line structures to isolate the transmit and receive signals. The TVTLs are coupled at an input side to an antenna and ground through a first 90 degree coupler, and the outputs of the TVTLs are coupled through a second 90 degree coupler for connection to a receiver and transmit circuit, respectively. The apparatus allows simultaneously operating a transmitter and receiver sharing a single antenna (or single antenna array). 1. A non-reciprocal radio frequency transceiver front end apparatus , comprising:at least two time-varying transmission lines (TVTLs) connected between first and second 90 degree couplers in a balanced structure, with said first 90 degree coupler connected to antenna side ports, and said second 90 degree coupler connected to a transmitter port and a receiver port;wherein each of said TVTLs have first and second inputs and an output, and said TVTLs comprise distributed modulated capacitors (DMC) that perform upconversion in frequency, having upper and lower sidebands, in response to high frequency pumping from a carrier source;wherein the combination of said TVTLs and said couplers physically separate an upconverted received signal and transmitted signal into different ports for canceling upconverted transmitted signals at the receiver port while adding upconverted received signals at the receiver port so that a transmitter and receiver can share an antenna.2. A non-reciprocal radio frequency transceiver front end apparatus , comprising:at least a first and second time-varying transmission line (TVTL) providing two TVTL paths, each TVTL having first and second inputs and an output;wherein each TVTL comprises a transmission line of distributed modulated capacitors (DMC);wherein said second input is configured for connection to ...

SIMULTANEOUS LVDS I/O SIGNALING METHOD AND APPARATUS

First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half. 1. An LVDS input circuit comprising:(a) a data input lead;(b) a first LVDS signal path;(c) a second LVDS signal path;(d) an inverter having an input connected to the data input lead and an inverting output;(e) an LVDS receiver having a non-inverting input connected to the first LVDS signal path, an inverting input connected to the second LVDS signal path, and an output; (i) a first comparator having a non-inverting input connected to the first LVDS signal path, an inverting input connected to the second LVDS signal path, and an output;', '(ii) a second comparator having a non-inverting input connected to the second LVDS signal path, an inverting input connected to the first LVDS signal path, and an output;', '(iii) an OR gate having one input connected to the output of the first comparator, another input connected to the output of the second comparator, and an output; and, '(f) window comparator circuitry including(g) a multiplexer having one input connected to the inverting output of the inverter, another input connected to the output of the LVDS receiver, a control input connected to the output of the window comparator, and an output.2. The LVDS input circuit of including an LVDS driver having a non-inverting output connected to the first LVDS signal path claim 1 , ...

HIGH-FREQUENCY SWITCH

A high-frequency switch configured to transmit differential signals including first and second signals, has first and second switches each comprising an input terminal configured to receive a signal and two output terminals configured to output the signal, and a substrate comprising a first surface mounted with the first and second switches. The input terminal is arranged between the two output terminals. The first and second switches are arranged on the substrate along a direction intersecting with a direction in which the input terminal and the two output terminals are placed side by side. One terminal of the first switch and one terminal of the second switch are placed side by side along the direction in which the first and second switches are arranged.

POWER LINE COMMUNICATION SYSTEM

A disclosed PLC system includes a PLC modem electrically connected to a transmission medium that transmits or carries medium or high voltage without electrical isolation. The PLC system further includes a voltage divider that draws power from the transmission medium to the PLC modem, thereby eliminating a need of a separate power source for operating the PLC modem. Since the PLC modem is electrically connected to the transmission, the PLC modem or communication connections of the PLC modem may be located at a same potential level as the transmission medium and thus the PLC modem does not see a surge during a surge event occurs in the transmission medium. Therefore, the disclosed PLC system eliminates the use of a line coupler and a surge protection component for providing high-voltage isolation and surge protection to the PLC modem. 1. A system comprising:a power line communication (PLC) modem electrically connected to a transmission medium configured to transmit a medium or high voltage,wherein the PLC modem is electrically connected to the transmission medium without a line coupler.2. The system as recited in claim 1 , wherein the PLC modem is electrically connected to the transmission medium without electrical isolation between the PLC modem and the transmission medium.3. The system as recited in claim 1 , wherein the PLC modem is ungrounded and is allowed to float at a voltage of the transmission medium.4. The system as recited in claim 1 , further comprising a voltage divider that delivers DC (direct current) power to the PLC modem.5. The system as recited in claim 4 , wherein the voltage divider comprises an AC/DC (alternating current/direct current) voltage divider claim 4 , a solid state distribution transformer claim 4 , a solid state power supply claim 4 , an offline power supply or a magnetic harvester.6. The system as recited in claim 5 , wherein the voltage divider draws medium or high voltage AC power from the transmission medium and delivers DC power ...

Multi-wire single-ended push-pull link with data symbol transition based clocking

System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A sequence of data bits is converted into M transition numbers, which are then converted into a sequence of symbols. The sequence of symbols is transmitted received over N wires. A clock signal may be effectively embedded in the transmission of the sequence of symbols. Each of the sequence of symbols may be selected based on a corresponding one of the M transition numbers and a value of a preceding one of the sequence of symbols.

DIFFERENTIAL SIGNAL TRANSMITTERS

A differential signal transmitter circuit includes an output driver circuit and a leakage current preventing circuit. The output driver circuit is configured to transmit a pair of differential signals according to a supply power. The leakage current preventing circuit is coupled to the supply power and configured to couple the supply power to the output driver circuit in a power on state and decouple the supply power from the output driver circuit in a power off state. 1. A differential signal transmitter circuit , comprising:an output driver circuit, configured to transmit a pair of differential signals according to a supply power; anda leakage current preventing circuit, coupled to the supply power and configured to couple the supply power to the output driver circuit in a power on state and decouple the supply power from the output driver circuit in a power off state.2. The differential signal transmitter circuit as claimed in claim 1 , wherein the leakage current preventing circuit comprises:a first switching element, coupled between the supply power and the output driver circuit;a second switching element, coupled to the first switching element at a connection node and a ground node; anda resistor, coupled between the output driver circuit and the connection node.3. The differential signal transmitter circuit as claimed in claim 2 , wherein the first switching element is a transistor comprising a first electrode coupled to the supply power claim 2 , a second electrode coupled to the output driver circuit and a control electrode coupled to the connection node claim 2 , and the second switching element is a transistor comprising a first electrode coupled to the ground node claim 2 , a second electrode coupled to the connection node and a control electrode coupled to a power signal claim 2 , wherein the power signal has a high voltage level in the power on state and a low voltage level in the power off state.4. The differential signal transmitter circuit as ...

LONG TRAINING FIELD SEQUENCE CONSTRUCTION

In wireless communications for a 20 megahertz (MHz) channel bandwidth, a first device may determine a high efficiency long training field (HE-LTF) mode. The first device may generate an HE-LTF symbol by using a portion or an entirety of an HE-LTF sequence corresponding to the channel bandwidth and HE-LTF mode. The first device may transmit, in the channel bandwidth, a high efficiency physical layer protocol data unit (HE PPDU) that includes the HE-LTF symbol. A second device may receive, in the 20 MHz channel bandwidth, a downlink HE PPDU that includes an HE-LTF symbol. The second device may obtain, from the HE-LTF symbol, a portion or an entirety of an HE-LTF sequence corresponding to the channel bandwidth and an HE-LTF mode of the HE-LTF symbol. The downlink HE PPDU may be the HE PPDU from the first device. Other methods, apparatus, and computer-readable media are also disclosed. 1. An apparatus for facilitating wireless communication in a 20 megahertz (MHz) channel bandwidth , the apparatus comprising:one or more memories; and determining a high efficiency long training field (HE-LTF) mode among a plurality of HE-LTF modes including a 4×HE-LTF mode and a 2×HE-LTF mode;', 'generating an HE-LTF symbol by using a portion or an entirety of an HE-LTF sequence corresponding to the 20 MHz channel bandwidth and the determined HE-LTF mode, wherein the HE-LTF sequence is among a plurality of HE-LTF sequences for the plurality of bandwidths and the plurality of HE-LTF modes; and', 'transmitting a high efficiency physical layer protocol data unit (HE PPDU) including the HE-LTF symbol, in the 20 MHz channel bandwidth., 'one or more processors coupled to the one or more memories, the one or more processors configured to cause2. The apparatus of claim 1 , wherein the plurality of HE-LTF sequences includes a first HE-LTF sequence for the 20 MHz channel bandwidth and the 4×HE-LTF mode claim 1 , and a second HE-LTF sequence for the 20 MHz channel bandwidth and the 2×HE-LTF mode.3. ...

EQUALIZER CONTROL METHOD AND ASSOCIATED APPARATUS

An equalizer control method is provided, where the method may write a plurality of parameters into a programmable filter pattern register file of a receiver to set up the programmable filter pattern register file. The receiver includes a plurality of equalization settings for selection, and the method may further perform selection between the equalization settings of the receiver according to the parameters of the programmable filter pattern register file and a signal sequence received by the receiver. An associated equalizer control apparatus is also provided, where the equalizer control apparatus is disposed in a receiver. The receiver includes a plurality of equalization settings, and the equalizer control apparatus applies the equalizer control method to perform selection between the equalization settings of the receiver. 1. An equalizer control method , comprising:writing a plurality of parameters to a programmable filter pattern register file of a receiver to set up the programmable filter pattern register file, wherein the receiver possesses a plurality of equalization settings for selection; andperforming selection upon the plurality of equalization settings of the receiver according to the plurality of parameters of the programmable filter pattern register file and a signal sequence received by the receiver.2. The equalizer control method of claim 1 , wherein the receiver is applied to a high speed serial link (HSSL).3. The equalizer control method of claim 1 , wherein the plurality of parameters comprises at least one filter pattern claim 1 , at least one filter edge pattern corresponding to the at least one filter pattern claim 1 , and at least one filter adjustment value corresponding to the at least one filter edge pattern.4. The equalizer control method of claim 3 , wherein the signal sequence comprises a central signal sequence and an edge signal sequence claim 3 , and the step of performing selection upon the plurality of equalization settings of the ...

METHODS AND APPARATUS FOR TRANSMITTING TIME SENSITIVE DATA OVER A TUNNELED BUS INTERFACE

Methods and apparatus for time sensitive data transfer between logical domains. In one embodiment, an user equipment (UE) device has an application processor (AP) coupled to a baseband processor (BB) that operate independently of one another normally, but may cooperate in limited hybrid use scenarios. For example, the BB receives audio packets via a cellular network that are converted to pulse code modulated (PCM) digital audio to be played by the AP. Unfortunately, since the AP and the BB are independently clocked, they will experience some clock drift. As a result, the audio playback may have undesirable artifacts if the drift is not otherwise compensated for. To these ends, the AP and/or BB determine a relative clock drift and compensate for playback by e.g., adding, padding, or deleting audio samples and/or audio packets. Techniques for handover scenarios are also disclosed.

Surge protection device for multi-protection mode communications

The present invention relates to a surge protection device for multi-protection mode communications, comprising: an input line into which a voltage is introduced; an output line connected to an external line; a surge discharge part provided with a ground terminal; a surge protection circuit part provided between the input line and the output line and having at least two or more surge protection circuits provided in parallel and discharging the introduced voltage to the ground terminal if the introduced voltage is a surge voltage; circuit conversion parts for selectively connecting the input line and the output line to any one of the surge protection circuits; a condition measuring part for measuring an input voltage introduced into an input terminal of the input line and a second discharge voltage from the surge protection circuit to the ground terminal and comparing each of the input voltage and the second discharge voltage with preset reference voltages; and a control circuit part for detecting abnormality of the connected surge protection circuit by using the comparison result of the input voltage and the comparison result of the second discharge voltage and converting the connected surge protection circuit into another one of the connected surge protection circuits through the circuit conversion parts if the abnormality of the connected surge protection circuit is detected. By the surge protection device for multi-protection mode communications, the damage to the surge protection circuits can be detected using the input surge voltage and no voltage is required to be additionally applied for detecting the damage to the surge protection circuits.

TRANSCEIVER BASEBAND PROCESSING

A buffer circuit includes a first feedback buffer to receive a first component of a current-mode signal and a second feedback buffer to receive a second component of the current-mode signal. The buffer circuit also including a first inverter having a first input coupled to an output of the second feedback buffer and to an input of a first current circuit through a first filter, a first output coupled to an input of the first feedback buffer. The buffer circuit also includes a second inverter having a second input coupled to an output of the first feedback buffer and to an input of a second current circuit through a second filter, and a second output coupled to an input of the second feedback buffer. 166.-. (canceled)67. A buffer circuit , comprising:a first feedback buffer to receive a first component of a current-mode signal and a second feedback buffer to receive a second component of the current-mode signal; a first input coupled to an output of the second feedback buffer and to an input of a first current gain circuit through a first filter, and', 'a first output coupled to an input of the first feedback buffer; and, 'a first inverter comprising a second input coupled to an output of the first feedback buffer and to an input of a second current gain circuit through a second filter, and', 'a second output coupled to an input of the second feedback buffer., 'a second inverter comprising68. The buffer circuit of claim 67 , wherein at least one of the first current amplifier and the second amplifier comprises a plurality of N-type field-effect-transistors (NFETs) coupled in parallel.69. The buffer circuit of claim 68 , wherein a size of the plurality of NFETs matches a size of an NFET in at least one of the first inverter and the second inverter.70. The buffer circuit of claim 67 , wherein at least one of the first filter and the second filter is a low-pass resistor-capacitor (RC) filter claim 67 , the low-pass RC filter being configured to reject out of band noise ...

Digital signal transfer using integrated transformers with electrical isolation

An isolator includes a transmitter, a coupling module and a receiver. The transmitter drives an input of the coupling module in response to a digital signal, such that in response to a first type of digital data value in the digital signal, a signal of a first predetermined type is supplied to the input and in response to a second type of digital data value in the digital signal, a signal of a second predetermined type is supplied to the input, the signals of the first type and the second type each including an initiation signal that announces a time window during which another portion of the signals representing a digital data value of the first type or the second type will be valid. The receiver is coupled to an output of the coupling module to receive and to decode signals in correspondence to the signals provided to the input.

Signal transmission reducing coupling caused delay variation

A signaling bus having a plurality of adjacent logical lanes, each logical lane having an odd signal path and an even signal path. Driving circuitry drives each logical lane by transmitting, if data has changed from an immediately preceding cycle, a one cycle signal having a first transition direction on the even signal path on even cycles and transmitting a one cycle signal having the first transition direction on odd cycles. If data has not changed, transmitting a two cycle signal having a second transition direction on the even signal path on even cycles and transmitting a two cycle signal on the odd path having the second transition direction on odd cycles. Receiver circuitry alternates selection of the even cycle path and the odd cycle path to determine if data has changed from the immediately preceding cycle.

Baseband processor with peak suppression function, transmitter with the same and method of transmitting signal

본 발명은 피크 억제 기능을 갖는 베이스 밴드 처리기, 송신 장치 및 송신 방법에 관한 것이다. 본 발명의 일 실시예에 따른 베이스 밴드 처리기는 디지털 신호를 생성하는 신호 생성부; 실시간으로 변하는 신호 대역폭의 크기에 따라 실시간으로 샘플링 비율을 가변하고, 상기 샘플링 비율에 따라 상기 신호 생성부로부터의 디지털 신호를 샘플링하는 가변 업/다운 샘플링부; 상기 가변 업/다운 샘플링부로부터의 샘플 신호의 피크 파워를, 피크가 존재하는 구간별로 검출하고, 상기 구간별 피크 파워에 따라 결정되는 억제 팩터를 이용하여 상기 샘플 신호의 해당 피크 파워를 억제하는 피크 억제 처리부; 및 상기 피크 억제 처리부로부터의 디지털 신호를 아날로그 신호로 변환하는 신호 변환부를 포함하고, 상기 피크 억제 처리부는, 상기 억제 팩터에 따라 생성되는 클리핑 윈도우를 통해 상기 샘플 신호의 해당 피크 파워를 억제할 수 있다. The present invention relates to a baseband processor having a peak suppression function, a transmission apparatus, and a transmission method. A baseband processor according to an embodiment of the present invention includes: a signal generator for generating a digital signal; A variable up / down sampling unit for varying a sampling rate in real time according to a size of a signal bandwidth varying in real time and sampling a digital signal from the signal generating unit according to the sampling rate; A peak detector for detecting the peak power of the sample signal from the variable up / down sampling unit for each section in which the peak exists, and for suppressing the peak power of the sample signal using an inhibition factor determined according to the section peak power, Suppression processing unit; And a signal conversion unit for converting a digital signal from the peak suppression processing unit into an analog signal, wherein the peak suppression processing unit can suppress the corresponding peak power of the sample signal through a clipping window generated according to the suppression factor .

Semiconductor integrated circuit

Semiconductor integrated circuit

소진폭의 차동신호를 외부로 출력하기 위한 라인 드라이버에 있어서, 연산증폭기의 수를 늘리는 일없이 출력신호의 진폭 및 오프셋전위를 안정화시킬 수 있는 반도체 집적회로. 이 반도체 집적회로는 차동신호가 공급되어 스위칭동작을 행하는 복수의 트랜지스터를 포함하는 출력회로와, 제1전원전위와 출력회로 사이에 접속된 제1트랜지스터와, 출력회로와 제2전원전위 사이에 접속된 제2트랜지스터와, 제1전원전위에 접속된 제3트랜지스터와, 제2트랜지스터와 함께 커런트미러회로를 구성하고, 제2트랜지스터에 흐르는 전류에 비례하는 전류를 흐르게 하는 제4트랜지스터와, 제3트랜지스터와 제4트랜지스터 사이에 흐르는 전류의 경로에 배치된 제1저항 및 제2저항과, 제1저항과 제2저항의 접속점에 있어서의 전위가 소정의 전위에 접근하도록 제1 및 제3트랜지스터의 게이트전위를 제어하는 차동증폭기를 구비한다. A line driver for outputting a small amplitude differential signal to the outside, wherein the semiconductor integrated circuit can stabilize the amplitude and offset potential of the output signal without increasing the number of operational amplifiers. The semiconductor integrated circuit includes an output circuit including a plurality of transistors to which a differential signal is supplied to perform a switching operation, a first transistor connected between the first power supply potential and the output circuit, and a connection between the output circuit and the second power supply potential. A second transistor, a third transistor connected to the first power supply potential, a fourth mirror for forming a current mirror circuit together with the second transistor, and allowing a current proportional to the current flowing through the second transistor; The first and third transistors are arranged so that the potential at the connection point of the first and second resistors disposed in the path of the current flowing between the transistor and the fourth transistor and the potential at the connection point of the first and second resistors approach a predetermined potential. A differential amplifier controls the gate potential.

Arrangement for selecting variable communication systems

The circuit for transmitting the data regardless the computer type equips a RS232C type (1), a RS422 type (2), and a current loop type transmission circuits. Each circuit comprises a line driver and a line receiver placed between a connector (CON) connected to a MODEM and a microprocessor (MP). A transmission data output terminal (TDD) of the microprocessor is connected to transmission data input terminals (TDI1-3) corresponding to each transmission type through line drivers (U1,U7,U9). A receiving data input terminal (RDI) is connect to each receiving data output terminal (RDO1-3) connected to an AND gate (AND) through line receivers (U3,U6,U10).

Discriminator for synchronization by delay of a b-frequency discretely encoded signal

FIELD: radio engineering. SUBSTANCE: invention relates to the field of radio engineering and communications, in particular to devices for quasi-coherent reception of discretely encoded multi-frequency radio signals. To ensure the result, a second amplifier 19, a third adder 20 and a fourth filter 21 are connected in series to the discriminator for delay synchronization of a B-frequency discretely encoded signal between the output of the first adder 8 and the second input of the second adder 11, the output of the second filter 10 is connected to the second input of the third adder 20, and the output of the fourth filter 21 is the second additional output of the device. EFFECT: increase in the accuracy of discriminator synchronization under conditions of changes in the relative acceleration between objects by using an a priori delay equation adequate to the processes taking place. 1 cl, 1 dwg РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 2 762 717 C1 (51) МПК H04L 7/02 (2006.01) H04W 8/00 (2009.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ИЗОБРЕТЕНИЯ К ПАТЕНТУ (52) СПК H04L 7/02 (2021.08); H04L 25/00 (2021.08); H04B 7/19 (2021.08); H04W 8/00 (2021.08) (21)(22) Заявка: 2021109192, 02.04.2021 (24) Дата начала отсчета срока действия патента: Дата регистрации: 22.12.2021 2 7 6 2 7 1 7 R U Адрес для переписки: 197045, Санкт-Петербург, Ушаковская наб., 17/ 1, Федеральное государственное казенное военное образовательное учреждение высшего образования "Военный учебно-научный центр Военно-Морского Флота "Военно-морская академия им. Адмирала Флота Советского Союза Н.Г. Кузнецова" (56) Список документов, цитированных в отчете о поиске: RU 2479139 C1, 10.04.2013. RU 2223607 C1, 10.02.2004. RU 2065253 С1, 10.08.1996. RU 2431919 C1, 20.10.2011. SU 915264 A1, 23.03.1982. RU 2079855 C1, 20.05.1997. US 4229821 A, 21.10.1980. US 8036307 B2, 11.10.2011. (54) Дискриминатор для синхронизации по задержке В-частотного дискретно-кодированного сигнала (57) Реферат: ...

Digital signal transfer method

The invention relates to a digital signal transfer method in which a first transfer channel and a second transfer channel are provided. An announcement signal including at least one pulse is transferred via the first transfer channel. A data signal is transferred via the second transfer channel within a data signal time window lasting for a prescribed period after the announcement signal.

Digital signal transmission method

Digitales Signalübertragungsverfahren, das folgende Verfahrensschritte umfasst: – Bereitstellen eines Übertragungskanals mit einem planaren integrierten Transformator, – Übertragen eines wenigstens einen Impuls umfassenden Ankündigungssignals über den Übertragungskanal, – Übertragen eines Datensignals innerhalb eines Datensignal-Zeitfensters einer vorgegebenen Zeitdauer nach dem Ankündigungssignal über den Übertragungskanal, – wobei empfängerseitig nach Erhalt eines Ankündigungssignals ein Zeitfenster erzeugt wird, innerhalb dessen Impulse, die empfängerseitig auf dem Datenkanal empfangen werden, als Datensignal akzeptiert werden. Digital signal transmission method, comprising the following method steps: Providing a transmission channel with a planar integrated transformer, Transmitting an announcement signal comprising at least one pulse over the transmission channel, Transmitting a data signal within a data signal time window of a predetermined period of time after the advertisement signal via the transmission channel, - Receiving side after receipt of an announcement signal, a time window is generated within which pulses received on the receiver side of the data channel are accepted as a data signal.

Digital signal transmission method

Digitales Signalübertragungsverfahren für eine Datenübertragung zwischen einem Sender und einem elektrisch von dem Sender getrennten Empfänger, das folgende Verfahrensschritte umfasst: – Bereitstellen eines ersten Übertragungskanals und eines zweiten Übertragungskanals, die jeweils einen planaren integrierten Transformator als magnetisches Kopplungselement (TR1, TR2) umfassen, – Übertragen eines wenigstens einen Impuls umfassenden Ankündigungssignals (S1) über den ersten Übertragungskanal (TR1), – Übertragen eines Datensignals (S2) innerhalb eines Datensignal-Zeitfensters einer vorgegebenen Zeitdauer (tf) nach dem Ankündigungssignal (S1) über den zweiten Übertragungskanal (TR2), – wobei empfängerseitig nach Erhalt eines Ankündigungssignals ein Zeitfenster (tf) erzeugt wird und wobei empfängerseitig nur solche Signalimpulse als Datensignal (S2) akzeptiert werden, die innerhalb dieses Zeitfensters (tf) auf dem zweiten Übertragungskanal (TR2) empfangen werden. Digital signal transmission method for data transmission between a transmitter and a receiver electrically separate from the transmitter, comprising the following method steps: Providing a first transmission channel and a second transmission channel, each comprising a planar integrated transformer as a magnetic coupling element (TR1, TR2), Transmitting an announcement signal (S1) comprising at least one pulse over the first transmission channel (TR1), Transmitting a data signal (S2) within a data signal time window of a predetermined time duration (tf) after the announcement signal (S1) via the second transmission channel (TR2), - Receiving side after receipt of an announcement signal, a time window (tf) is generated and receiving side only those signal pulses are accepted as data signal (S2) received within this time window (tf) on the second transmission channel (TR2).

Wireless network and transceiving base station and wireless network device used therein

FIELD: radio engineering, communication. SUBSTANCE: invention relates to wireless communication networks using modulation frequency allocation in transceiving base stations. Sampling and processing of a subset of discretised signals are performed to determine mismatch (error) signals for each of the discretised signals. Said error signals are multiplied by an estimated symbol and summed to obtain one error signal. That error signal is used to adjust a set of discretised signals to be used and processed with respect to subsequent symbols. The error signal is also used to interpolate discretised signals in an infinitely small approximation to the point of maximum opening of the eye diagram. EFFECT: fewer synchronisation symbols, thereby enabling wireless communication devices to use a relatively low signal sampling rate and computational power for clock extraction. 18 cl, 15 dwg РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (51) МПК H04W 28/06 (13) 2 518 204 C2 (2009.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ (21)(22) Заявка: ИЗОБРЕТЕНИЯ К ПАТЕНТУ 2011120056/07, 19.11.2009 (24) Дата начала отсчета срока действия патента: 19.11.2009 (72) Автор(ы): КУЭЧЛЕР Тим (CA) (73) Патентообладатель(и): ЭППЛ ИНК (US) Приоритет(ы): (30) Конвенционный приоритет: (43) Дата публикации заявки: 10.02.2013 Бюл. № 4 R U 26.12.2008 US 12/344,398 (45) Опубликовано: 10.06.2014 Бюл. № 16 C 2 C 2 2006280266 A, 14.12.2006 . US 2008151940 A1, 26.06.2008. US 6501810 B1, 31.12.2002 . US 2005147194 A1, 07.07.2005. US 2002181633 A1, 05.12. 2002. US 2003143951 A1, 31.07.2003. US 5566213 A, 15.10.1996. US 2008101515 A1, 01.05.2008. US 6347127 B1, 12.02.2002. US 6795410 B1, 21.09.2004. RU 2000132215 А, 27.11.2002 (85) Дата начала рассмотрения заявки PCT на национальной фазе: 26.07.2011 2 5 1 8 2 0 4 (86) Заявка PCT: R U 2 5 1 8 2 0 4 (56) Список документов, цитированных в отчете о поиске: WO 9927671 A1, 03.06.1999. US CA 2009/001673 (19.11.2009) (87) Публикация заявки PCT: WO 2010/071977 ...

A communications system and a system control method

A communications system has a plurality of stations interconnected by a two-line circuit, which two-line circuit consists of a data bus circuit for transmitting a series of data bits between at least one sending station and at least one receiving station of the plurality of stations and a clock bus circuit for transmitting clock signals in synchronism with each of the data bits. The data bus circuit sends a signal or a command requesting the receiving station to enter a standby or an execute state after taking in data supplied, while a logic value on the clock bus circuit is fixed. In more detail, the sending station transmits signals to make at least one of the receiving stations enter the standby state after taking in data and then sends data to another receiving station, after which the sending station sends a signal or command to make both the first and second receiving stations simultaneously enter the execute state. The signal or command requesting the standby or execute state is added at the end of a data packet containing a series of data. The data packet includes data to be transferred to the receiving station and an address of the receiving station.

Method and apparatus for transmitting signal in communication system

본 개시는 LTE와 같은 4G 통신 시스템 이후 보다 높은 데이터 전송률을 지원하기 위한 5G 또는 pre-5G 통신 시스템에 관련된 것이다. 본 개시의 일 실시예에서 제안하는 방법은; 통신 시스템에서 참조 신호를 송신하는 방법에 있어서, 미리 생성된송신 행렬을 기반으로 생성된 상기 참조 신호를 송신하는 과정을 포함하며, 상기 미리 생성된송신 행렬은, 제로 엘리먼트(zero element)들과 넌-제로 엘리먼트(non-zero element)들을를 포함하는 하나의기준 행렬이 미리 결정된 수만큼 반복되어 생성된 것이며, 기준 시퀀스는 상기 송신미리 생성된 행렬에 포함된 상기 넌-제로 엘리먼트(non-zero element)들에는 특정 시퀀스가 할당되고,되어 있음 상기 기준 행렬에 포함된 복수의 엘리먼트들의 하나는 상기 송신 행렬에서 제1 열에 포함된 넌-제로 엘리먼트들 각각에 할당되고, 상기 기준 시퀀스에 포함된 하나의 엘리먼트로부터 순환 쉬프트된 엘리먼트는 상기 제1 열로부터 미리 정해진 열 간격에 위치하는 상기 송신 행렬에서 제2 열에 포함된 넌-제로 엘리먼트들 각각에 할당됨을 특징으로 한다. The present disclosure relates to a 5G or pre-5G communication system for supporting a higher data rate after a 4G communication system such as LTE. A method proposed in an embodiment of the present disclosure includes; A method for transmitting a reference signal in a communication system, comprising: transmitting the reference signal generated based on a pre-generated transmission matrix, wherein the pre-generated transmission matrix includes zero elements and non - One reference matrix including zero elements (non-zero elements) is generated by repeating a predetermined number, and the reference sequence is the non-zero element included in the transmission pre-generated matrix. are assigned a specific sequence, wherein one of a plurality of elements included in the reference matrix is assigned to each of the non-zero elements included in a first column in the transmission matrix, and one element included in the reference sequence An element cyclically shifted from is allocated to each of the non-zero elements included in the second column in the transmission matrix positioned at a predetermined column interval from the first column.

Apparatus for common input and output ports

본 발명은, 입/출력 단자 공용화 장치에 관한 것으로, 예를 들어 디브이디 레코더(DVD-Recorder) 또는 셋탑 박스(Set Top Box) 등과 같은 다양한 유형의 전자기기에서, 컴포지트 입/출력 모드 또는 컴포넌트 출력 모드 중, 임의의 한 입/출력 모드를 선택 사용할 수 있도록 하되, 입/출력 단자들의 개수를 축소함과 아울러, 사용자가 원하는 입/출력 모드를 보다 간편하게 선택 지정할 수 있도록 함으로써, 장치의 간소화가 가능해지고, 또한 사용상의 편리성이 향상되는 매우 유용한 발명인 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output terminal sharing device, for example, in a composite input / output mode or a component output mode in various types of electronic devices such as a DVD-Recorder or a Set Top Box. Among them, any one input / output mode can be selected and used, but the number of input / output terminals can be reduced, and the user can easily select and specify a desired input / output mode, thereby simplifying the device. In addition, it is a very useful invention which improves the convenience of use. 입/출력 단자, 입/출력 모드, 컴포지트 입력 모드, 컴포지트 출력 모드, 컴포넌트 출력 모드, 슬라이드 스위치, 공용화, 간소화 Input / Output Terminal, Input / Output Mode, Composite Input Mode, Composite Output Mode, Component Output Mode, Slide Switch, Common Use, Simplification

Wireless transceiver device integrated with common clock phase-locked loop

Embodiments of the present application disclose a wireless transceiver device. The device comprises: a radio frequency receiver, a radio frequency transmitter, a first parallel-to-serial and serial-to-parallel converter, and a common clock phase-locked loop. The radio frequency receiver, the radio frequency transmitter, the first parallel-to-serial and serial-to-parallel converter, and the common clock phase-locked loop are integrated in a radio frequency chip. The radio frequency receiver comprises a downconverter and an analog-to-digital converter. The radio frequency transmitter comprises an upconverter and a digital-to-analog converter. The first parallel-to-serial and serial-to-parallel converter provides the radio frequency chip with a digital interface to a baseband chip. The common clock phase-locked loop is respectively coupled to the analog-to-digital converter, the digital-to-analog converter, and the first parallel-to-serial and serial-to-parallel converter, and provides a clock signal to the analog-to-digital converter, the digital-to-analog converter, and the first parallel-to-serial and serial-to-parallel converter. The wireless transceiver device allows a chip to have a reduced area, and/or allows a chip to have reduced power consumption.

Data transmission device and method for reducing the number of wires

데이터 전송 장치가 개시된다. 이 데이터 전송 장치는 이진 논리 기반의 이진 논리 신호를 출력하는 센더 및 입력 도선을 통해 입력 받은 상기 이진 논리 신호를 다치 논리 기반의 다치 논리 신호로 인코딩하고, 상기 인코딩된 다치 논리 신호를 출력 도선을 통해 디코더로 전송하는 인코더를 포함한다. 여기서, 상기 인코더는 상기 입력 도선의 개수 및 상기 입력 도선의 개수보다 작은 상기 출력 도선의 개수를 포함하는 입력 변수와 상기 입력 변수에 대응하는 상기 다치 논리 신호를 저장한 맵핑 테이블을 포함하고, 상기 맵핑 테이블을 참조하여 상기 이진 논리 신호를 상기 다치 논리 신호로 인코딩함을 특징으로 한다. A data transmission device is disclosed. The data transmission apparatus encodes the binary logic signal received through a sender and an input lead outputting a binary logic signal based on a binary logic into a multivalued logic signal based on a multivalued logic, and encodes the encoded multivalued logic signal through an output lead. It includes an encoder for transmitting to the decoder. The encoder may include an input variable including the number of the input lead and the number of the output lead smaller than the number of the input lead, and a mapping table storing the multi-valued logic signal corresponding to the input variable. The binary logic signal is encoded into the multivalued logic signal by referring to a table.

ANALOG CIRCUIT FOR BASEBAND MODEM

Improvements to automatic telegraphy systems

Method and device for digitally transmitting signals.

Data transmission system

1,222,493. Electric selective signalling. INTERNATIONAL BUSINESS MACHINES CORP. 18 July, 1969 [3 Sept., 1968], No. 36312/69. Heading G4H. A data transmission system comprises a central station 11 and at least one sub-section 12 connected by a two-wire line 13, the sub-station comprising a plurality of bi-stable circuits all connected in parallel to the two wires, successive alternate bi-stable circuits assuming one stable state in response to a signal of one polarity and the other circuits successively assuming the same stable state in response to a signal of the other polarity. The power supply 4 at the central station is applied by switch 5 to the wires 13. A resistance meter 7 connected to the wires 13 passes a signal via a decoder 8 to a data register 9. The switch 5 and decoder 8 are controlled by unit 6. The sub-station comprises a stepping scanner formed of a number of thyristor stages S0-Sn. In the first stage SO the cathode of thyristor T0 is connected to the input terminal L2, and the anode is connected via resistor RA0 to input L2. The gate electrode is connected via resistor R20, and via diode D10 and resistor R10 to terminal L2. Parallel to resistor R10 is a series circuit formed of normally-closed push-button contact G0, capacitor C0 and resistor R40. The normallyopen contact is connected via resistor R30 to terminal L1. In the second stage the cathode of thyristor T1 is connected to terminal L1 and the anode via resistor RA1 to terminal L2. The gate electrode is connected via resistor R21, and via diode D11 and resistor R11 to terminal L1. It is also connected via capacitor C1 to the junction between resistor RAO and thyristor T0. Stage S2 resembles stage S0 except for the contacts G0 and stage S3 resembles stage S1. Resistors RA are settable to high or low values representing binary "0" and "1". Data transmission from the sub-station to the central station is initiated by pressing pushbutton GO to change capacitor C0 gates thyristor ...

Termination apparatus, termination control method, and storage medium on which termination control program has been stored

[Problem] To provide a termination control apparatus that can provide an optimum termination state. [Solution] Included are: an input terminal to which an input signal is inputted; a termination resistance unit that terminates the input terminal by use of a variable resistor the resistance value of which can be set; a voltage measurement unit that measures the voltage of the input signal; and a control unit that changes the resistance value or a target voltage range when the voltage is not within the target voltage range having been set for the input signal on the basis of both an absolute maximum rated value and an operation-guaranteed voltage.

Active terminating device with optional line-receiving and line-driving capabilities

An active terminating device (30) for an electrical transmission line with optional line-receiving and line-driving capabilities. The basic device is a two-terminal unit, denoted as a Signal Canceling Unit (SCU), which senses the signal available at its terminals (34a, 34b), and applies negative feedback in order to cancel and absorb the signal. When applied to the end of a transmission line (15a, 15b) as part of wired communication network, the SCU functions as a terminator. When connected in the middle of such wired transmission line, the SCU splits the transmission line into two separate and isolated segments. In such a configuration, the SCU can be used to isolate a portion of a network from signal degradation due to noise or bridge-tap. Furthermore, the two isolated segments may each employ independent communications, such that no interference exists between the segments. In another embodiment, line receiver functionality is integrated into the SCU, designated as a Signal Canceling and Receiving Unit (SCRU) (90). The SCRU can perform all the SCU functions, and also serves as a line receiver in the communication network. In yet another embodiment, line driver functionality is integrated into the SCRU, designated as a Signal Canceling, Receiving and Transmitting Unit (SCRTU) (120). The SCRTU can perform all the SCRU functions, and also serves as a line driver in the communication network. Upon connecting multiple SCRTU's to a continuous transmission line, terminated independent point-to-point communication segments are formed.

Active terminating device with optional line-receiving and line-driving capabilities

Transmitter having voltage driver and current driver

A circuit includes a first power node at a first voltage level, a second power node at a second voltage level, a first voltage driver, a first current driver, and a control unit. The first voltage driver is configured to electrically couple a first output node to the first power node when a first input signal at the first input node is at a first logic state, and electrically couple a first output node to the second power node when the first input signal is at a second logic state. The first current driver is configured to inject or extract a first adjustment current into or out of a first output node. The control unit is configured to generate a measurement result of the first voltage level, and to set the first adjustment current according to the measurement result.

Radiation hardened differential output buffer

A radiation hardened differential output buffer (300) is partitioned into multiple stages (302, 304, 306, 308), each including at least one current source (310, 312) and a bridge circuit (314, 316, 318, 320). Each stage receives substantially the same inputs at substantially the same time, and provides substantially the same output (Outp, Outn). The outputs of each stage are connected together. As a result, if one of the stages is disrupted by SEE, the disrupted stage does not contribute enough current to the output of the differential output buffer (Outp, Outn) to disrupt the output signal.

Macrocell, integrated circuit device, and electronic device

Method and device for digitized transmission of signals

- Pour simplifier la transmission à une station éloignée de signaux reçus par des capteurs divers, on leur associe un module électronique local transformant les signaux analogiques reçus en un train de bits codés qui est émis sans aucun formatage préalable sur une voie de transmission (V), et, à la station éloignée, on les décode avant de les appliquer à un filtre numérique reconstituant les signaux reçus sous la forme de séries d'échantillons numérisés. - Application à la transmission de données sismiques par exemple. - To simplify the transmission to a remote station of signals received by various sensors, they are associated with a local electronic module transforming the analog signals received into a coded bit stream which is transmitted without any prior formatting on a transmission channel (V) , and, at the remote station, they are decoded before applying them to a digital filter reconstructing the signals received in the form of series of digitized samples. - Application to the transmission of seismic data for example.

Wlan nodes, and methods therein for efficient usage of wlan resources

Termination circuits and methods therefor

An active termination circuit having a selective DC power consumption for clamping signals on a bus in an electronic device is described. The active termination circuit is configured to clamp the signals on the bus to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes bottom clamping transistors coupled to a first potential having bottom clamping transistor control nodes arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes top clamping transistors coupled to a second potential having top clamping transistor control nodes arranged for clamping the signal at about a second reference voltage. The circuit also has a variable current supply coupled to said first threshold reference transistor and said second threshold reference transistor arranged to reduce the DC power consumption of the active termination circuit as needed.

Automatic switching between DSL and analog on a single RJ-11 DSL/analog combo modem

A modem for providing both DSL and analog signal connection capability with a single RJ-11 jack via an automatic switching mechanism. The switching mechanism is controlled by software, which is responsive to user connection preference (i.e., for DSL or analog connection) and/or the detection that a DSL service is available. Dependent on whether DSL is detected on the signal line coupled to the jack and/or whether the user selects a DSL connection, the switching mechanism routes the signal received on the RJ-11 jack through either a path having the DSL modem circuitry or a path having analog modem circuitry.

Ultrafast sampler with non-parallel shockline

An ultrafast sampling system includes an interposer and a sampler that include series of Schottky diodes configured with a non-parallel waveguide to form shocklines or nonlinear transmission line (NLTLs) that produce a differential strobe pulse. The shocklines are defined by non-parallel conductors that are configured as, for example, triangular, dentate, arcuate, or other shapes, or as conductors that have edges that are triangular, dentate, arcuate, or the like. The conductors are defined with respect to a substrate, and are airbridged so that at least some portions of the conductors are displaced from the substrate to reduce waveguide capacitance. Electrical connection to the sampler is made with airline having a inner conductor that is deformable to contact an input pad defined on the sampler.

Signal digitalized transmission method and equipment

本发明为简化将各个传感器接收的信号传输至 远端站，传感器与一个当地电子模块相关联，该模块 将所接收的模拟信号变换为编码的位流，位流不进行 任何预先的格式化就发送到传输通道上，在远端站在 信号被送到一数字滤波器之前被译码，数字滤波器以 数字样本串的形式存储所接收的信号。本发明用于 例如地震数据的传输。

Memory system with a scheme capable of stably terminating a pair of differential signals transmitted via a pair of transmission lines

Provided is a memory system in which a pair of differential signals transmitted via a pair of transmission lines are prevented from being terminated at the same voltage during a standby mode, thereby preventing a receiver from entering an unstable state. The memory system includes a pair of transmission lines, a transmitter that outputs a pair of differential signals to the pair of transmission lines, and a receiver that receives the pair of differential signals via the pair of transmission lines. A first termination voltage is applied to one of the pair of transmission lines, and a second termination voltage is applied to the other transmission line. The first termination voltage is determined to be different from the second termination voltage.

Low-voltage differential signal driver for high-speed digital transmission

A low-voltage differential signal driver for high-speed digital transmission includes a first converter operable to receive a signal in a first type and convert the signal into a second type, wherein a resistance of the first converter is variable. A second converter couples to the first converter, the second converter is operable to receive a signal in the second type and convert the signal into the first type, wherein a resistance of the second converter is variable. The driver is operable to scale the resistance of the first and second converters to provide a constant ratio between the resistance of the first and second converters.

Data transfer system and method of transferring data

Communication system and communication method

According to one embodiment of the present disclosure, a communication system is provided with a transmission device and a reception device. The transmission device outputs a clock signal at a clock frequency corresponding to transfer mode, and also outputs a data signal corresponding to transmission mode. The reception device receives the clock signal and the data signal, and determines the transfer mode on the basis of the level of the clock frequency of the received clock signal.

Printing telegraph system

Signaling system

High-speed digital data source - input transistor controls two output transistors with floating collectors

Macrocell, integrated circuit device, and electronic instrument

A macrocell including a physical layer circuit includes a transmitter circuit and a receiver circuit connected with pads for differential signals DP and DM. The transmitter circuit includes a transmission driver which drives a signal line for the DP and a transmission driver which drives a signal line for the DM. When a direction from a side SD 1 to a side SD 3 of the macrocell is defined as a first direction, the transmission drivers are disposed on the side of the pads for the DP and DM in the first direction and are disposed line-symmetrically about a line SYL, and the receiver circuit is disposed on the side of the transmitter circuit in the first direction. A routing region of signal lines SLR 1 and SLR 2 for connecting the receiver circuit with the pads for the DP and DM is provided in the region between the transmission drivers.

Line driver with linear transitions

A cable driver is disclosed which provides a substantially linear output signal corresponding to an input signal received by the cable driver on a transmission line. The cable driver includes a number of switches coupled by delay elements which cause the switches to operate in a sequential order in response to an input signal. Each of the switches couples an associated current source to an output port, producing a substantially linear output signal on a transmission line connected to the output port. The substantially linearity of the output signal increases the rate at which data may be transmitted over the transmission line, while permitting the rise and fall time of a specified portion of the output signal to be controlled to ensure that electro-magnetic interference is not produced.

Apparatus and method for digital frequency down-conversion

Disclosed is an apparatus and a method for down-converting frequencies of an input signal by separating the signal to which at least two frequencies are allocated according to each frequency, and then outputting at least two digital IF signals in a communication system. The digital down-converting apparatus includes a band-pass filter, an analog-to-digital converter, down-converters, up-converters, and Serializer/Deserializeres, etc. First, the signal to which at least two frequencies are allocated is down-converted into baseband signals respectively. Then, the baseband signals are up-converted into signals of a predetermined frequency respectively.

High speed serial link systems

High speed serial link techniques are provided. A system applying the high speed serial link technique comprises a relay unit and an amplifier. The relay unit receives a first pair of differential signals provided by a high speed transmitter of a first device, and provides the amplifier with at least one signal that is generated based on the first pair of differential signals. The amplifier amplifies and converts the signal provided by the relay unit to a second pair of differential signals to be received by a high speed receiver of a second device.

High speed differential pre-driver using common mode pre-charge

In general, the embodiments introduce a pre-charge state between an idle state (when no data in being transmitted) and an active state (when data is being transmitted). In the pre-charge state, both differential signals are pre-charged to the common mode voltage, which is also the crossover voltage. Similarly, an additional pre-charge state is inserted between the active state and the idle state when the signals transition from active to idle. Because both signals for each bit, including the first and last bits, are being driven from the same voltage level, the quality of the first and last bits are improved to be similar in quality to the middle bits.

Communication system and communication means

根据本公开的一个实施方式，通信系统设置有发送装置和接收装置。所述发送装置以与发送模式对应的时钟频率输出时钟信号，并且还输出与发送模式对应的数据信号。所述接收装置接收时钟信号和数据信号，并且基于接收的时钟信号的时钟频率的水平来确定发送模式。

Semiconductor integrated circuit device

In order to transfer data at high speed over a long distance, a current mode logic output circuit (CML) having a large number of taps, high accuracy, and a wide switchable range of the amount of pre-emphasis is needed. However, when the amount of emphasis is set by adding unit source-coupled pair circuits, a problem will arise that the output capacitance of the current mode logic output circuit would increase, thus hampering high-speed transmission. An output circuit of the invention is constructed from unit source-coupled pair circuits 501 , which are obtained by dividing a current mode logic output circuit (CML) into m groups, terminal resistors 502 , and a data selector 504 . The amount of emphasis of each tap is determined by the ratio of the number of unit source-coupled pair circuits, which have been obtained by dividing the CML into m groups, allocated to each tap. Thus, the amount of emphasis can be set to be any arbitrary amount without a change in the output amplitude of 1. As a result, the transmission speed can be increased and the transmission distance can be extended.

Active terminating device with optional line-receiving and line-driving capabilities

An active terminating device (30) for an electrical transmission line with optional line-receiving and line-driving capabilities. The basic device is a two-terminal unit, denoted as a Signal Canceling Unit (SCU), which senses th e signal available at its terminals (34a, 34b), and applies negative feedback in order to cancel and absorb the signal. When applied to the end of a transmission line (15a, 15b) as part of wired communication network, the SCU functions as a terminator. When connected in the middle of such wired transmission line, the SCU splits the transmission line into two separate an d isolated segments. In such a configuration, the SCU can be used to isolate a portion of a network from signal degradation due to noise or bridge-tap. Furthermore, the two isolated segments may each employ independent communications, such that no interference exists between the segments. In another embodiment, line receiver functionality is integrated into the SCU, designated as a Signal Canceling and Receiving Unit (SCRU) (90). The SCRU ca n perform all the SCU functions, and also serves as a line receiver in the communication network. In yet another embodiment, line driver functionality is integrated into the SCRU, designated as a Signal Canceling, Receiving and Transmitting Unit (SCRTU) (120). TheSCRTU can perform all the SCRU functions , and also serves as a line driver in the communication network. Upon connecti ng multiple SCRTU's to a continuous transmission line, terminated independent point-to-point communication segments are formed.

System and method for actively terminating a transmission line

A communication system (50) for concurrently carrying multiple distinct signals over multiple transmission-line segments, each having at least two conductors, comprises a first (15a, 15b) transmission-line segment carrying a first signal and a second (15c, 15d) transmission-line segment carrying a second signal distinct from the first signal. The first and second transmission-line segments are connected to each other at a single connection point (51a, 51b) to which a termination device (30) is connected. The termination device is operative to stop the first signal to pass to the second transmission-line segment, and to stop the second signal to pass to the first transmission-line segment.

Pre-emphasis circuit

A pre-emphasis circuit which can improve a communication quality of a data transmission at low cost is provided. A current switch circuit, a current adder circuit, and transition detection circuits are provided in a transmitter of a data transmission system. The transition detection circuits detect transitions of transmission data signals which are a differential pair. The current switch circuit receives the transmission data signals, carries driving currents in accordance with the transmission data signals, and outputs output data signals which are a differential pair. The current adder circuit receives detection signals from the transition detection circuits, and adds driving currents in accordance with the detection signals to load resistors. By this means, output data signals in which the transitions are emphasized are inputted to a transmission line.

Input buffer circuit including boosting capacitor

입력신호의 변화폭이 작더라도 지연시간과 스큐가 작은 입력버퍼 회로가 개시된다. An input buffer circuit having a small delay time and a small skew even if a change range of an input signal is small is disclosed. 상기 입력버퍼 회로는, 제1입력단을 통해 입력되는 기준전압을 기준으로하여 제2입력단을 통해 입력되는 신호의 레벨을 증폭하여 출력하는 차동증폭기와, 상기 차동증폭기의 제2입력단에 접속되는 부스팅 커패시터를 구비한다. 또한 상기 입력버퍼 회로는, 상기 차동증폭기의 출력신호의 천이를 검출하는 에지 검출기와, 상기 차동증폭기의 제1 및 제2입력단 사이에 접속되고 상기 에지 검출기의 출력신호에 응답하는 스위칭부를 더 구비한다. 따라서 상기 입력버퍼 회로에서는, 입력신호의 천이시 실제로 상기 제2입력단을 통해 입력되는 신호의 레벨이 상기 부스팅 커패시터에 의해 상기 입력신호의 레벨의 두배로 부스팅됨으로써, 상기 입력버퍼 회로의 출력전류가 두배가 되어 상기 입력버퍼 회로의 출력신호가 변화하는 경사가 샤프해지게 되며 결국 지연시간과 스큐가 크게 감소된다. The input buffer circuit may include a differential amplifier configured to amplify and output a level of a signal input through a second input terminal based on a reference voltage input through a first input terminal, and a boosting capacitor connected to a second input terminal of the differential amplifier. It is provided. The input buffer circuit further includes an edge detector for detecting a transition of the output signal of the differential amplifier, and a switching unit connected between first and second input terminals of the differential amplifier and responsive to the output signal of the edge detector. . Therefore, in the input buffer circuit, the level of the signal actually input through the second input terminal when the input signal transitions is boosted by twice the level of the input signal by the boosting capacitor, whereby the output current of the input buffer circuit is doubled. As a result, the slope in which the output signal of the input buffer circuit changes is sharp, and the delay time and skew are greatly reduced.

Digital information transmission system

Adaptive linear equalisation for walsh-modulated

Differential transmission circuit, disk array apparatus, and output signal setting method

To provide a signal transmitting/receiving apparatus etc. where a cable length can be measured by using a general-purpose cable, without using an interface. A differential transmission circuit by the present invention includes a signal output circuit sending a high-speed differential signal and a pulse wave; a signal input circuit including a terminating resistor; a bias controller controlling a bias voltage on a transmission path; a terminating resistance controller disconnecting the terminating resistor on sensing a bias voltage and connecting it on sensing no bias voltage, by a bias sensing circuit; a sensing input circuit sensing a pulse wave reflected at the signal input circuit; and an output setting controller setting an electric characteristic of a signal outputted from the signal output circuit by a propagation time from sending the pulse wave by the signal output circuit to receiving the reflected pulse wave by the sensing input circuit.

Apparatus suitable for use in an advanced digital baseband processor

The present disclosure relates to an advanced digital baseband processor for a base station in a cellular communications network. In general, the advanced digital baseband processor integrates multiple Radio Access Technologies (RATs). As used herein, a RAT is a radio access technology as defined by a corresponding standard. For example, in one embodiment, RATs integrated by the advanced digital baseband processor include a Code Division Multiple Access (CDMA) voice RAT (e.g., 3GPP2 CDMA 1x RTT or 3GPP2 CDMA 1x Advanced) as well as a CDMA Data Only, or Data Optimized, (DO) RAT (e.g., 3GPP2 CDMA EV-DO or 3GPP2 CDMA EV-DO Rev B). In another embodiment, the RATs integrated by the advanced digital baseband processor also include 3GPP Long Term Evolution (LTE). The RATs given above are only examples. The advanced digital baseband processor may integrate additional or alternative RATs.

Differential Pre-Emphasis Driver

실시예에 따른 차동 고대역 강조 구동장치는 제1전류를 공급하는 제1전류원; 상기 제1전류보다 큰 제2전류를 공급하는 제2전류원; 상기 제1전류원을 제1출력단자 및 제2출력단자와 선택적으로 연결시키는 제1선택회로; 상기 제2전류원을 상기 제1출력단자 및 상기 제2출력단자와 선택적으로 연결시키는 제2선택회로를 포함하고, 상기 제1선택회로 및 상기 제2선택회로는 상기 제1출력단자 및 상기 제2출력단자와 상기 제1전류원 및 상기 제2전류원의 연결을 조합적으로 선택함으로써 송신신호의 고대역 강조를 처리하는 것을 특징으로 한다. A differential high band emphasis driving apparatus according to an embodiment includes a first current source for supplying a first current; A second current source for supplying a second current greater than the first current; A first selection circuit for selectively connecting the first current source to a first output terminal and a second output terminal; And a second selection circuit for selectively connecting the second current source to the first output terminal and the second output terminal, wherein the first selection circuit and the second selection circuit comprise the first output terminal and the second output terminal. A high band emphasis of the transmission signal is handled by combining an output terminal, a connection between the first current source and the second current source. 실시예에 의하면, 최소 개수의 선택회로를 통하여 차동 고대역 강조 구동장치를 구현할 수 있으므로 구동장치의 제어가 용이하고, 회로 사이즈를 축소시킬 수 있있다. 또한, 선택회로 사이의 동기가 필요치 않으므로, 고대역 강조 구동장치의 구현 및 수신단의 데이터 복원이 용이하며, 선택 경로의 개폐 제어가 용이한 장점이 있다. According to the embodiment, the differential high-band emphasis driver can be implemented through the minimum number of selection circuits, thereby facilitating control of the driver and reducing the circuit size. In addition, since the synchronization between the selection circuits is not necessary, the implementation of the high-band emphasis driver and the data recovery of the receiver are easy, and the opening and closing control of the selection path is easy. 고대역 강조 방식, 푸시풀, 차동, 고대역 강조 구동장치, 스위치, 전류원 High Bandwidth Emphasis, Push-Pull, Differential, Highband Emphasis Drive, Switch, Current Source

Transceiver, data transfer control device, and electronic instrument

A transceiver includes upstream differential signal lines DPUP and DMUP, downstream differential signal lines DPDW and DMDW, common differential signal lines DPCM and DMCM, a first transmission driver of which outputs are connected to DPUP and DMUP, a second transmission driver of which outputs are connected to DPDW and DMDW, a first switch circuit which connects the first transmission driver to a logic circuit during upstream connection and connects the second transmission driver to the logic circuit during downstream connection, a second switch circuit which respectively connects DPUP and DMUP to DPCM and DMCM during the upstream connection and respectively connects DPDW and DMDW to DPCM and DMCM during the downstream connection, and a third transmission driver connected to DPCM and DMCM.

Apparatus suitable for use in an advanced digital baseband processor

The present disclosure relates to an advanced digital baseband processor for a base station in a cellular communications network. In general, the advanced digital baseband processor integrates multiple Radio Access Technologies (RATs). As used herein, a RAT is a radio access technology as defined by a corresponding standard. For example, in one embodiment, RATs integrated by the advanced digital baseband processor include a Code Division Multiple Access (CDMA) voice RAT (e.g., 3GPP2 CDMA 1x RTT or 3GPP2 CDMA 1x Advanced) as well as a CDMA Data Only, or Data Optimized, (DO) RAT (e.g., 3GPP2 CDMA EV-DO or 3GPP2 CDMA EV-DO Rev B). In another embodiment, the RATs integrated by the advanced digital baseband processor also include 3GPP Long Term Evolution (LTE). The RATs given above are only examples. The advanced digital baseband processor may integrate additional or alternative RATs.

Subscriber station for a serial bus system and method for sending a message in a serial bus system

Es ist eine Teilnehmerstation (20; 30) für ein Bussystem (1) und ein Verfahren zum Senden einer Nachricht mit unterschiedlichen Bitraten in einem Bussystem (1) bereitgestellt. Die Teilnehmerstation (20; 30) umfasst eine Sendestufe (220) zum Senden einer Nachricht (4; 5) auf eine Busleitung (3) des Bussystems (1), wobei die Sendestufe (220) beim Senden von verschiedenen Phasen einer Nachricht (4; 5) ausgestaltet ist, zwischen einer ersten Betriebsart und einer zweiten Betriebsart zu schalten, wobei die Sendestufe (220) in der ersten Betriebsart ausgestaltet ist, einen ersten Datenzustand als Buszustand mit unterschiedlichen Buspegeln für zwei Busadern (41, 42) der Busleitung (3) zu erzeugen und einen zweiten Datenzustand als Buszustand mit demselben Buspegel für die zwei Busadern (41, 42) der Busleitung (3) zu erzeugen, und wobei die Sendestufe (220) in der zweiten Betriebsart ausgestaltet ist, den ersten und zweiten Datenzustand jeweils als Buszustand mit unterschiedlichen Buspegeln für die zwei Busadern (41, 42) der Busleitung (3) zu erzeugen. There is provided a subscriber station (20; 30) for a bus system (1) and a method for transmitting a message with different bit rates in a bus system (1). The subscriber station (20; 30) comprises a transmission stage (220) for transmitting a message (4; 5) to a bus line (3) of the bus system (1), the transmission stage (220) transmitting different phases of a message (4; 5) is configured to switch between a first operating mode and a second operating mode, wherein the transmitting stage (220) is configured in the first operating mode, a first data state as a bus state with different bus levels for two bus wires (41, 42) of the bus line (3). and to generate a second data state as the bus state having the same bus level for the two bus wires (41, 42) of the bus line (3), and wherein the transmitting stage (220) is configured in the second mode, the first and second data states each as a bus state with different bus levels for ...

Digital signal detection for high speed signaling systems

Methods and apparatuses for detecting digital signals in high speed signaling systems. In at least one embodiment, at least one received input signal is combined with a plurality of predetermined reference signals according to a plurality of prior digital signal output states to generate a signal for detecting a present digital signal output state. In one aspect of the invention, a method for determining a digital signal state in a differential signaling system includes: comparing a first differential input signal to a second differential input signal; determining a prior digital signal output state; comparing the first differential input signal to one of a first reference voltage and a second reference voltage; comparing the second differential input signal to one of the first reference voltage and the second reference voltage; and determining a present digital signal output state from the prior digital signal output state and from all of the comparisons.

High speed differential pre-driver using common mode pre-charge

In general, the embodiments introduce a pre-charge state between an idle state (when no data in being transmitted) and an active state (when data is being transmitted). In the pre-charge state, both differential signals are pre-charged to the common mode voltage, which is also the crossover voltage. Similarly, an additional pre-charge state is inserted between the active state and the idle state when the signals transition from active to idle. Because both signals for each bit, including the first and last bits, are being driven from the same voltage level, the quality of the first and last bits are improved to be similar in quality to the middle bits.

SYSTEM AND METHOD FOR ACTIVE MANAGEMENT

Simultaneous lvds i/o signaling method and apparatus

First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half.

Termination apparatus, termination control method, and storage medium on which termination control program has been stored

本發明提供一種可形成最佳終端狀態的終端控制裝置，其包含：輸入端子，其為輸入信號所輸入；終端電阻部，其利用可設定電阻値的可變電阻作為輸入端子的終端；電壓測定部，其測定輸入信號的電壓；以及控制部，其在電壓並未包含於根據絶對最大額定值以及動作保證電壓對輸入信號所設定之目標電壓範圍內時，變更電阻値或目標電壓範圍。

Differential output driver

A differential output driver device for receiving a differential input voltage within a specific range having a first portion of a relatively higher voltage and a second portion of a relatively lower voltage and obtaining an identical voltage variation for output voltages of the first portion and the second portion is provided. The differential output driver device includes a step-down circuit for receiving the first portion of the relatively higher voltage and lowing the relatively higher voltage to a first output voltage, a step-up circuit for receiving the second potion of the relatively lower voltage and rising the relatively lower voltage to a second output voltage, a first compensation circuit electrically connected to the step-down circuit for providing a first bias to transform the first output voltage into a first compensation voltage, and a second compensation circuit electrically connected to the step-up circuit for providing a second bias to transform the second output voltage into a second compensation voltage, wherein the second compensation voltage and the first compensation voltage have the identical voltage variation value, so as to make the driver generate a periodic output voltage having a substantially regular waveform.

Peak cancellation crest factor reduction apparatus and method for reducing peak to average power ratio, and apparatus for determining peak value

제 1 기저대역 복소 신호로부터 진폭 값이 임계 값을 초과하는 클리핑 신호를 추출하는 클리핑부; 추출된 클리핑 신호에 포함된 복수의 진폭 값을 시간 순서대로 입력받고, 입력받은 복수의 진폭 값 중 제 1 진폭 값이 제 1 진폭 값 이전에 입력되는 제 2 진폭 값 및 제 1 진폭 값 이후에 입력되는 제 3 진폭 값보다 큰 경우, 제 1 진폭 값을 피크 값으로 결정하는 피크 값 결정부; 결정된 피크 값을 CPG(cancellation pulse generator)로 할당하는 CPG 할당부; 및 CPG로부터 생성되는 상쇄 신호를 제 1 기저대역 복소 신호로부터 차감하여 PAPR(peak to average power ratio)이 감소된 제 2 기저대역 복소 신호를 출력하는 감산부를 포함하는 것을 특징으로 하는 본 발명의 일 실시예에 따른 PC-CFR(peak cancellation crest factor reduction) 장치가 개시된다. A clipping unit for extracting a clipping signal whose amplitude value exceeds a threshold value from the first baseband complex signal; A plurality of amplitude values included in the extracted clipping signal are received in time order, a first amplitude value of a plurality of input amplitude values is inputted after a first amplitude value and a second amplitude value inputted before the first amplitude value, A peak value determining unit that determines the first amplitude value as a peak value when the first amplitude value is greater than the third amplitude value; A CPG allocator for allocating the determined peak value to a cancellation pulse generator (CPG); And a subtractor for subtracting the offset signal generated from the CPG from the first baseband complex signal to output a second baseband complex signal having a reduced peak to average power ratio (PAPR). A PC-CFR (peak cancellation crest factor reduction) device according to the example is disclosed.

Integrated circuit

Provided is an integrated circuit, relating to the field of electronic technology, and being used to reduce the area occupied in an integrated circuit by a quadrature coupler. The quadrature coupler in the integrated circuit is provided with a positive-phase differential input port (INP), a negative-phase differential input port (INN), a positive-phase differential through port (TP), a negative-phase differential through port (TN), a positive-phase differential coupling port (CP), a negative-phase differential coupling port (CN), a positive-phase differential isolation port (ISOP) and a negative-phase differential isolation port (ISON). The quadrature coupler is provided with a first coil (L1), a second coil (L2), a third coil (L3) and a fourth coil (L4) which are coupled to each other. The positive-phase differential input port (INP) and the positive-phase differential through port (TP) are provided at both ends of the first coil (L1). The negative-phase differential input port (INN) and the negative-phase differential through port (TN) are provided at both ends of the second coil (L2). The positive-phase differential coupling port (CP) and the positive-phase differential isolation port (ISOP) are provided at both ends of the third coil (L3). The negative-phase differential coupling port (CN) and the negative-phase differential isolation port (ISON) are provided at both ends of the fourth coil (L4).

Differential transmission circuit, disk array apparatus, and output signal setting method

To provide a signal transmitting/receiving apparatus etc. where a cable length can be measured by using a general-purpose cable, without using an interface. A differential transmission circuit by the present invention includes a signal output circuit sending a high-speed differential signal and a pulse wave; a signal input circuit including a terminating resistor; a bias controller controlling a bias voltage on a transmission path; a terminating resistance controller disconnecting the terminating resistor on sensing a bias voltage and connecting it on sensing no bias voltage, by a bias sensing circuit; a sensing input circuit sensing a pulse wave reflected at the signal input circuit; and an output setting controller setting an electric characteristic of a signal outputted from the signal output circuit by a propagation time from sending the pulse wave by the signal output circuit to receiving the reflected pulse wave by the sensing input circuit.

Circuit for the operation of underground telegraph lines with quiescent current using a counter battery acting from the issuing body

Phase detector and retimer for clock and data recovery circuits

A phase detector and retimer circuit that includes a retimer circuit, a phase shift circuit coupled to the retimer circuit, and an error signal generation circuit coupled to the retimer circuit and the phase shift circuit. The retimer circuit is configured to receive a data signal and generate a first retimed data signal based on a first phase of a clock signal and a second retimed data signal based on a second phase of the clock signal. The phase shift circuit is configured to receive the data signal and phase shift the data signal to generate first, second, third, and fourth phase shifted data signals. The error signal generation circuit is configured to generate a first error signal and a second error signal based on the first and second retimed data signals and the first, second, third, and fourth phase shifted data signals.

Constellation design for a pcm modem

Modem constellations are designed by independently optimizing for each slot of a frame, the distances between constellation points used for that slot. A maximum number of points N(0) (824) are chosen having at least the minimum distance d0 without exceeding a power limitation Plim. Using N(0), an attemp t is made to increase the d0 in the constellation without exceeding Plim. Constellation may be further optimized by, where possible, decreasing N(0) (824) in a particular constellation without affecting the total data rate of the frame. Thus, a maximum potentially achievable data rate Rmax (830) is calculated given the number of points which are in each of the six constellations, and comparing Rmax to a standards-permitted data rate DR; an d then, if Rmax exceeds DR, by decreasing N(0) (824) in one or more constellations, provided the decrease in the number of points does not cause a recalculated Rmax to drop below DR. Further optimization is obtained by attempting to increase d0 in one or more slots by permitting that slot(s) to exceed Plim, provided the average power of the frame is not exceeded. This i s accomplished by finding the slot with the maximum error probability, increasing d0 for that slot (while maintaining N(0)) to thereby exceed frame power limitations for that slot, and checking to see whether the changes to the constellation in that slot violates the average frame power limitations. A simple system for checking average constellation power is also provided.</SD OAB>

Alarm output circuit

本发明提供一种警报输出电路，其能基于从一个输出端子输出的警报信号来应对同时产生多个警报因素的情况。该警报输出电路通知外部在智能功率模块中产生了警报因素(UV、OC、OH、OV)。数字/模拟转换器(5)中输入表示有无产生各警报因素(UV、OC、OH、OV)的数字数据，并输出对应的电压。电压控制振荡器(VCO)输出与数字/模拟转换器(5)的输出电压(V)相对应的频率的信号。

Differential transmission circuit, disk array device, and output signal setting method

Scheduler for layer mapped code words

An eNode-B includes PUSH mapping hardware for improved performance. A scheduler schedules first and second code words of first and second respective user devices. A buffer receives and stores first and second identifiers. A de-multiplexer outputs a first code word number based on the first identifier and a second code word number based on the second identifier. A set of completion queues store the first and second code word numbers. A sequence controller generates first and second select signals corresponding to the first and second identifiers. A multiplexer outputs one of the first and second code word numbers based on the select signals, and the scheduler schedules the first and second code words based on the first and second identifiers.

Constellation design for a PCM modem

Modem constellations are designed by independently optimizing for each slot of a frame, the distances between constellation points used for that slot. A maximum number of points N( 0 ) are chosen having at least the minimum distance d 0 without exceeding a power limitation Plim. Using N( 0 ), an attempt is made to increase the d 0 in the constellation without exceeding Plim. Constellations may be further optimized by, where possible, decreasing N( 0 ) in a particular constellation without affecting the total data rate of the frame. Thus, a maximum potentially achievable data rate Rmax is calculated given the number of points which are in each of the six constellations, and comparing Rmax to a standards-permitted data rate DR; and then, if Rmax exceeds DR, by decreasing N( 0 ) in one or more constellations, provided the decrease in the number of points does not cause a recalculated Rmax to drop below DR. Further optimization is obtained by attempting to increase d 0 in one or more slots by permitting that slot(s) to exceed Plim, provided the average power of the frame is not exceeded. This is accomplished by finding the slot with the maximum error probability, increasing d 0 for that slot (while maintaining N( 0 )) to thereby exceed frame power limitations for that slot, and checking to see whether the changes to the constellation in that slot violates the average frame power limitations. A simple system for checking average constellation power is also provided.

Digital equalizer for high-speed serial communications

Incoming data at a high-speed serial receiver is digitized and then digital signal processing (DSP) techniques may be used to perform digital equalization. Such digital techniques may be used to correct various data anomalies. In particular, in a multi-channel system, where crosstalk may be of concern, knowledge of the characteristics of the other channels, or even the data on those channels, may allow crosstalk to be subtracted out. Knowledge of data channel geometries, particularly in the context of backplane transmissions, may allow echoes and reflections caused by connectors to be subtracted out. As data rates increase, fractional rate processing can be employed. For example, the analog-to-digital conversion can be performed at half-rate and then two DSPs can be used in parallel to maintain throughput at the higher initial clock rate. At even higher rates, quadrature techniques can allow analog-to-digital conversion at quarter-rate, with four DSPs used in parallel.

Spectrum management systems and methods for cable networks

The present methods and systems provide spectrum management for enhancing upstream performance for cable networks. According to one embodiment, a method of enhancing upstream performance in a cable network includes the steps of measuring performance of an upstream channel at a first data signaling rate; determining whether the upstream channel supports a second data signaling rate based on the performance; and selectively transitioning to the second data signaling rate based on said determination. The second data signaling rate is a higher rate than the first data signaling rate.

Data transmission by switching resonance