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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Форма поиска

Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 11514. Отображено 100.
05-01-2012 дата публикации

Double molded chip scale package

Номер: US20120001322A1
Автор: Luke England, Yong Liu
Принадлежит: Fairchild Semiconductor Corp

Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages (CSPs) contain a die with an integrated circuit device, a patterned plating layer, and a second interconnect structure formed from a Cu etched substrate that has a portion of an upper surface connected to the patterned plating layer, a side surface, and a bottom surface. The die can be attached to the patterned plating layer by a first interconnect structure that uses wirebonding or that uses a flip chip attachment process. The CSP contains a double molded structure where a first molding layer encapsulates the die, the patterned plating layer, the first interconnect structure, and the upper surface of the second interconnect structure. The second molding layer encapsulates the side surface of the second interconnect structure without encapsulating the bottom surface of the second interconnect structure. With such a configuration, the second molding layer helps control warpage during the manufacturing process and no printed circuit board (PCB) substrate is needed when the package is used in an electronic device since the signal routing is performed by the second interconnect structure. Other embodiments are described.

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Номер записи: 1
21-05-2018 дата публикации

Устройство для формовки и обрезки выводов микросхем

Номер: RU0000179618U1
Автор: Владислав Алексеевич Трегубов, Елена Владимировна Короткова, Иван Иванович Зайченко
Принадлежит: Акционерное общество "Научно-исследовательский институт Приборостроения имени В.В. Тихомирова"

Полезная модель относится к радиоэлектронике, в частности к средствам подготовки интегральных микросхем к монтажу, а именно для формовки и обрезки их выводов. Технической проблемой, решаемой предлагаемой полезной моделью, является создание приспособления для формовки и обрезки выводов, расположенных в два ряда по стороне корпуса (корпуса типа 4229.132-3 микросхем 1986 ВЕ91Т и др.). Технический результат предлагаемой полезной модели заключается в предотвращении деформации и разрушения выводов микросхем, расположенных в два ряда по стороне ее корпуса, в результате чрезмерного давления на них в процессе формовки и обрезки. Для достижения указанного технического результата устройство выполнено следующим образом. Устройство содержит основание (1), на котором закреплен матрицедержатель (2). В матрицедержатель (2) установлены направляющие колонки (13) и матрица (3), в которой выполнено углубление (4) для размещения микросхемы (14). Верхняя плита (12) подвижно установлена на направляющие колонки (13). К верхней плите (12) прикреплен держатель (11), в котором жестко закреплен пуансон обрезки (7). В пуансоне обрезки (7) установлен по скользящей посадке формовочный пуансон (6). В формовочный пуансон (6) подвижно установлен прижим (5). Прижим (5) и формовочный пуансон (6) выступают из пуансона обрезки (7). Боковые стороны прижима (5) выполнены ступенчатыми. На верхней стороне прижима (5) в формовочном пуансоне (6) расположен первый буфер (8). Первый буфер (8) закреплен крышкой (9), которая жестко установлена в формовочном пуансоне (6). На крышке (9) расположен второй буфер (10), более твердый, чем первый. Кроме того, на боковых сторонах матрицы (3) выполнены ступеньки (16), таким образом, что при формовке они устанавливаются между ступеньками прижима (5). 2 з.п.4 ил. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 179 618 U1 (51) МПК H05K 13/00 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК H01L 21/4842 (2006.01); H01L 23/ ...

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Номер записи: 2
12-01-2012 дата публикации

Semiconductor device

Номер: US20120007224A1
Автор: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
Принадлежит: Hitachi Hokkai Semiconductor Ltd, Renesas Electronics Corp

In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

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Номер записи: 3
26-01-2012 дата публикации

Substrate for semiconductor element, method for manufacturing substrate for semiconductor element, and semiconductor device

Номер: US20120018867A1
Автор: Junko Toda, Susumu Maniwa, Takehito Tsukamoto
Принадлежит: Toppan Printing Co Ltd

Provided is a manufacturing method of a semiconductor element substrate including: a step of forming a first photoresist pattern on a first surface of a metallic plate, to form a semiconductor element mounting part, a semiconductor element electrode connection terminal, a wiring, an outer frame part, and a slit; a step of forming a second photoresist pattern on the second surface of the metallic plate; a step of forming the slit by half etching to connect the metallic chip with a four corners of the outer frame part; a step of forming a plurality of concaved parts on the second surface of the metallic plate; a step of forming a resin layer by injecting a resin to the plurality of concaved parts; and a step of etching the first surface of the metallic plate and forming the semiconductor element electrode connection terminal and the outer frame.

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Номер записи: 4
23-02-2012 дата публикации

Packaging Integrated Circuits

Номер: US20120043650A1
Автор: Liang Kng Ian Koh, Richard Mangapul Sinaga
Принадлежит: INFINEON TECHNOLOGIES AG

An integrated circuit 15 is placed onto a lead frame 101 having lead fingers 109 of substantially constant thickness along their length. Wires are formed from the lead fingers 109 to corresponding electrical contacts the integrated circuit. Following the wire bonding process, the thickness of the tips of the lead fingers 109 is reduced by a laser process, to form tips of reduced thickness desirable for a subsequent moulding operation. Thus, at the time of the wire bonding the tips of the fingers 109 need not have a gap beneath them, so that more secure wire bonds to the lead fingers 109 can be formed.

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Номер записи: 5
15-03-2012 дата публикации

Method of manufacture of integrated circuit packaging system with stacked integrated circuit

Номер: US20120064668A1
Автор: Henry Descalzo Bathan, Jairus Legaspi Pisigan, Zigmund Ramirez Camacho
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: forming a base lead having an outer protrusion and an inner protrusion with a recess in between; forming a stack lead having an elongated portion; mounting a base integrated circuit over the inner protrusion or under the elongated portion; mounting the stack lead over the base lead and the base integrated circuit; connecting a stack integrated circuit and the stack lead with the stack integrated circuit over the base integrated circuit; and encapsulating at least a portion of both the base integrated circuit and the stack integrated circuit with the base lead and the stack lead exposed.

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Номер записи: 6
22-03-2012 дата публикации

Integrated Power Converter Package With Die Stacking

Номер: US20120068320A1
Автор: Eric Yang, Hunt Hang Jiang, Jinghai Zhou
Принадлежит: Monolithic Power Systems Inc

An integrated circuit for implementing a switch-mode power converter is disclosed. The integrated circuit comprises at least a first semiconductor die having an electrically quiet surface, a second semiconductor die for controlling the operation of said first semiconductor die stacked on said first semiconductor die having said electrically quiet surface and a lead frame structure for supporting said first semiconductor die and electrically coupling said first and second semiconductor dies to external circuitry.

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Номер записи: 7
03-05-2012 дата публикации

Integrated circuit package system with encapsulation lock

Номер: US20120104579A1
Автор: Byung Tai Do, Sung Uk Yang
Принадлежит: Individual

An integrated circuit package system includes an external interconnect having a lead tip and a lead body, including a recess in the lead body including a first recess segment, having an orientation substantially parallel to the lengthwise dimension of the lead body, and a second recess segment intersecting and perpendicular to the first recess segment along a lead body top surface of the lead body, the first recess segment at a bottom portion of the second recess segment; an internal interconnect between an integrated circuit die and the external interconnect; and an encapsulation to cover the external interconnect with the recess filled.

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Номер записи: 8
03-05-2012 дата публикации

Method for manufacturing leadframe, packaging method for using the leadframe and semiconductor package product

Номер: US20120104588A1
Автор: Hong-Chin Lin, Nan-Jang Chen
Принадлежит: MediaTek Inc

A leadframe package includes a die pad with four unitary, outwardly extending slender bars; a plurality of leads arranged along periphery of the die pad; a separate pad segment separated from the die pad and isolated from the plurality of leads; a semiconductor die mounted on an upper side of the die pad, wherein the semiconductor die contains first bond pads wire-bonded to respective the plurality of leads and a second bond pad wire-bonded to the separate pad segment; and a molding compound encapsulating the semiconductor die, the upper side of the die pad, the first suspended pad segment and inner portions of the plurality of leads.

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Номер записи: 9
03-05-2012 дата публикации

Method for manufacturing semiconductor device

Номер: US20120108013A1
Автор: Atsushi Fujisawa, Hiroshi Fujii
Принадлежит: Renesas Electronics Corp

In QFN packages for vehicles which are required to have high reliability, the side surface of leads is mostly covered with lead-to-lead resin protrusions, which prevent smooth formation of solder fillets during reflow mounting. When the lead-to-lead protrusions are mechanically removed using a punching die, there is a high possibility of causing cracks of the main body of the package or terminal deformation. When a spacing is provided between the punching die and the main body of the package in order to avoid such damages, a resin residue is produced to hinder complete removal of this lead-to-lead resin protrusion. The present invention provides a method for manufacturing semiconductor device of a QFN type package using multiple leadframes having a dam bar for tying external end portions of a plurality of leads. This method includes a step of removing a sealing resin filled between the circumference of a mold cavity and the dam bar by using laser and then carrying out surface treatment, for example, solder plating.

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Номер записи: 10
10-05-2012 дата публикации

Semiconductor device with nested rows of contacts

Номер: US20120112333A1
Автор: Qiang Liu, Qingchun He, Zhaojun Tian
Принадлежит: FREESCALE SEMICONDUCTOR INC

A molded surface mount semiconductor device has electrical contact elements disposed in a set of pairs of zigzag rows extending adjacent and generally parallel to opposite edges of an active face of a semiconductor die. Each of the pairs of rows includes an inner zigzag row of electrical contact elements nested inside an outer zigzag row of electrical contact elements. The electrical contact elements of the inner and outer zigzag rows are partially inter-digitated. A lead frame used in making the device also has a die pad located inside the set of pairs of zigzag rows, and an outer frame element located outside the set of pairs of zigzag rows, and which support the electrical contact elements of the inner and outer zigzag rows respectively.

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Номер записи: 11
24-05-2012 дата публикации

Semiconductor device package with electromagnetic shielding

Номер: US20120126378A1
Автор: Allan C. Toriaga, Anang Subagio, Michael H. McKerreghan, Romarico S. San Antonio
Принадлежит: Unisem (Mauritius) Holdings Ltd

A package for a semiconductor device includes shielding from RF interference. The package has a lead frame with a lead and a connecting bar. The lead has an inner end for connecting to the device and an outer end having an exposed surface at the package side face. The connecting bar also has an end with an exposed surface at the package side face. A molding compound overlying the leadframe forms a portion of the side face. Electrically conductive shielding forms a top surface of the package, and extends downward therefrom to form an upper portion of the package side face. The exposed surface at the connecting bar end has an upper edge higher than the upper edge of the exposed surface of lead end. Accordingly, the shielding makes electrical contact with the connecting bar adjacent to its exposed surface, while being electrically isolated from the lead.

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Номер записи: 12
19-07-2012 дата публикации

Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices

Номер: US20120181689A1
Автор: Byung Tai Do, Linda Pei Ee CHUA, Reza A. Pagaila
Принадлежит: Stats Chippac Pte Ltd

A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A recessed region with angled or vertical sidewall is formed in the peripheral area. A conductive layer is formed in the recessed region. A first stud bump is formed over a contact pad of the semiconductor die. A second stud bump is formed over the first conductive layer within the recessed region. A bond wire is formed between the first and second stud bumps. A third stud bump is formed over the bond wire and first stud bump. A dicing channel partially formed through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the bond wire and stud bumps.

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Номер записи: 13
02-08-2012 дата публикации

Method for manufacturing semiconductor device

Номер: US20120196405A1
Автор: Ken Sakamoto, Mitsugu Tanaka, Taishi Sasaki, Taketoshi Shikano
Принадлежит: Mitsubishi Electric Corp

A method of manufacturing a semiconductor device comprises: preparing a lead frame including a package external region and a package internal region, a burred surface being provided at a top end of a side of the lead frame, and a fracture surface being provided in the vicinity of the top end of the side; chamfering the top end of the side in the package external region; mounting a semiconductor element on the lead frame and sealing the semiconductor element with mold resin in the package internal region; and removing resin burr provided on the side of the lead frame in the package external region after the chamfering and the sealing.

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Номер записи: 14
27-09-2012 дата публикации

Integrated circuit packaging system with leveling standoff and method of manufacture thereof

Номер: US20120241926A1
Автор: Emmanuel Espiritu, Henry Descalzo Bathan, Zigmund Ramirez Camacho
Принадлежит: Stats Chippac Pte Ltd

A method of manufacture of an integrated circuit packaging system includes: providing a lead; mounting an integrated circuit adjacent the lead; molding an encapsulation encapsulating the lead and the integrated circuit; and forming a leveling standoff protruded from the same surface of the encapsulation as the lead with the integrated circuit between the lead and the leveling standoff electrically isolated from the lead and the integrated circuit.

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Номер записи: 15
27-09-2012 дата публикации

Semiconductor memory card

Номер: US20120241933A1
Автор: Katsuyoshi Watanabe, Kazuhide Doi, Naohisa Okumura, Takeshi Ikuta, Taku Nishiyama
Принадлежит: Toshiba Corp

In an embodiment, a semiconductor memory card includes a lead frame including external connection terminals, a lead portion, a chip component mounting portion and a semiconductor chip mounting portion, a chip component mounted on the chip component mounting portion, a memory chip disposed on the semiconductor chip mounting portion, and a controller chip. A rewiring layer is formed on a surface of the memory chip. The lead frame is resin-sealed. An electric circuit of the controller chip and the memory chip on the lead frame is formed by the lead portion, the rewiring layer and a metal wire connected to electrode pad of the chips, the lead portion, and the rewiring layer.

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Номер записи: 16
27-09-2012 дата публикации

Integrated circuit packaging system with lead frame etching and method of manufacture thereof

Номер: US20120241962A1
Автор: Zigmund Ramirez Camacho
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: providing a pre-plated leadframe having a contact pad and a die paddle pad; forming an isolated contact from the pre-plated leadframe and the contact pad; mounting an integrated circuit die over the die paddle pad; and encapsulating with an encapsulation the integrated circuit die and the isolated contact, the encapsulation having a bottom surface which is planar and exposing in the bottom surface only the contact pad and the die paddle pad.

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Номер записи: 17
18-10-2012 дата публикации

Method for making circuit board

Номер: US20120260502A1
Автор: Lee-Sheng Yen
Принадлежит: Advance Materials Corp

A method for making the same is disclosed. First, a first substrate and a second substrate are provided. The first substrate includes a release film attached to a carrier. The second substrate includes a copper film covered with a solder mask. Second, the solder masked is patterned. Next, the release film and the patterned solder mask are pressed together so that the first substrate is attached to the second substrate. Then, the copper film is patterned to form a first pattern and a second pattern. The first pattern is in direct contact with the release film and the second pattern is in direct contact with the patterned solder mask. Later, a passivation is formed to cover the first pattern and the second pattern to form a circuit board structure. Afterwards, a package is formed on the carrier to form a packaging structure.

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Номер записи: 18
15-11-2012 дата публикации

Apparatus and methods for electronic amplification

Номер: US20120286878A1
Автор: Alan W. Ake, David Dening
Принадлежит: Skyworks Solutions Inc

Apparatus and methods for electronic amplification are disclosed herein. In certain implementations, an amplifier is provided for amplifying a RF signal, and the amplifier includes a first transistor and a second transistor electrically connected in a Darlington configuration. The first and second transistors can be, for example, bipolar or field effect transistors and the first transistor can amplify an input signal and provide the amplified input signal to the second transistor. The first and second transistors are electrically connected to a power low node such as a ground node through first and second bias circuits, respectively. In certain implementations, the first transistor includes an inductor disposed in the path from the first transistor to the power low voltage. By including the inductor in the path from the first transistor to the ground node, the third order distortion of the amplifier can be improved.

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Номер записи: 19
13-12-2012 дата публикации

Saw Type Package without Exposed Pad

Номер: US20120315728A1
Автор: Dana Liu, Elite Lee
Принадлежит: Shanghai Kaihong Electronic Co Ltd

In one embodiment, a method for manufacturing a saw type pad is provided. The method includes performing a first molding process to form a first molded layer beneath a pad of a lead frame. A semiconductor device is placed on the pad. A second molding process is performed to form a second molded layer. The first molded layer and the second molded layer form an encapsulation to enclose the semiconductor device and the pad. The lead frame is singulated to form an individualized semiconductor package. The pad is not exposed from a bottom surface of the semiconductor package.

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Номер записи: 20
27-12-2012 дата публикации

Dc/dc convertor power module package incorporating a stacked controller and construction methodology

Номер: US20120326287A1
Автор: Ashok S. Prabhu, Jaime A. Bayan, Rajeev Joshi
Принадлежит: National Semiconductor Corp

Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices.

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Номер записи: 21
10-01-2013 дата публикации

Semiconductor device

Номер: US20130009292A1
Автор: Hitoshi Kawasaki
Принадлежит: Toshiba Corp

According to an embodiment, a semiconductor device includes a first frame, a semiconductor element fixed to the first frame, a second frame, a third frame and a resin package. The second frame faces the first frame and is away from the first frame, the second frame being electrically connected to the semiconductor element via a metal wire. The resin package covers the semiconductor element, the first frame, and the second frame. The first frame and the second frame are exposed in one major surface of the resin package. The third frame juxtaposed to one of the first frame and the second frame, the third frame being continuously exposed from the major surface of the resin package to a side surface in contact with the major surface.

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Номер записи: 22
10-01-2013 дата публикации

Conductive chip disposed on lead semiconductor package and methods of making the same

Номер: US20130009309A1
Автор: David Chong, Jatinder Kumar
Принадлежит: Individual

In one implementation, an apparatus includes a semiconductor die, a lead, a non-conductive epoxy, and a conductive epoxy. The semiconductor die includes an upper surface and a lower surface opposite the upper surface. The lead is electrically coupled to the upper surface of the semiconductor die. The non-conductive epoxy is disposed on a first portion of the lower surface of the semiconductor die. The conductive epoxy is disposed on a second portion of the lower surface of the semiconductor die. In some implementations, a conductive wire extends from the lead to the upper surface of the semiconductor die to electrically couple the lead to the upper surface of the semiconductor die.

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Номер записи: 23
07-02-2013 дата публикации

Bonded wire semiconductor device

Номер: US20130032932A1
Автор: Li Ting Celina ONG, Yin Kheng Au, Zi-Song Poh
Принадлежит: FREESCALE SEMICONDUCTOR INC

A bonded wire semiconductor device includes a sub-assembly including a semiconductor die having an active face with a set of internal electrical contact elements and an externally exposed set of electrical contact elements. A set of bond wires make respective electrical connections between the internal electrical contact elements and the externally exposed set of electrical contact elements. A molding compound encapsulates the semiconductor die with the active face embedded in the molding compound. The bond wires have the same length. The bond wires are bonded to the internal electrical contact elements and to the externally exposed electrical contact elements at first and second curved arrays and of bond positions respectively. The first and second curved arrays and of bond positions have corresponding concentric shapes.

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Номер записи: 24
14-02-2013 дата публикации

Flat heat pipe

Номер: US20130037244A1
Автор: Hai-Ping Shen, Nien-Tien Cheng, Sheng-Liang Dai, Sheng-Lin Wu, Yu-Liang Lo
Принадлежит: Individual

A flat heat pipe includes a casing, a wick structure received in the casing, and a working medium contained in the casing and saturated in the wick structure. The casing has an upper plate and a bottom plate opposite to the upper plate. The wick structure is attached only to the bottom plate of the casing. The wick structure spaces from the upper plate with a vapor channel defined between the upper plate and the wick structure.

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Номер записи: 25
21-02-2013 дата публикации

Bump-On-Leadframe Semiconductor Package With Low Thermal Resistance

Номер: US20130043572A1
Автор: Keng Hung Lin, Richard K. Williams
Принадлежит: Advanced Analogic Technologies Hong Kong Ltd, Advanced Analogic Technologies Inc

In a bump-on-leadframe semiconductor package a metal bump formed on a integrated circuit die is used to facilitate the transfer of heat generated in a semiconductor substrate to a metal heat slug and then to an external mounting surface. A structure including arrays of thermal vias may be used to transfer the heat from the semiconductor substrate to the metal bump

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Номер записи: 26
25-04-2013 дата публикации

Integrated circuit packaging system with planarity control and method of manufacture thereof

Номер: US20130099367A1
Автор: Arnel Senosa Trasporto, Byung Tai Do, Emmanuel Espiritu, Linda Pei Ee CHUA
Принадлежит: Stats Chippac Pte Ltd

A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a partially removed portion including: a conductive pattern having a lower surface on a top frame surface of the leadframe, a contact protrusion and a support lead on the lower surface of the conductive pattern, the support lead for supporting the partially removed portion of the leadframe during an encapsulation process, and a contact pad on a bottom surface of the contact protrusion; mounting an integrated circuit die above the conductive pattern; applying an encapsulation on the integrated circuit die and the conductive pattern, the lower surface of the conductive pattern exposed from the encapsulation; and removing at least a portion of the leadframe to form a contact lead and expose a bottom surface of the encapsulation.

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Номер записи: 27
02-05-2013 дата публикации

Large panel leadframe

Номер: US20130109137A1
Автор: Chan Boon Meng, Phang Hon Keat, Yong Lam Wai
Принадлежит: Carsem M Sdn Bhd

A method of manufacturing an integrated circuit package includes mounting a large panel leadframe having a substantially square shape to a ring. The large panel leadframe includes a plurality of die pads and a corresponding plurality of leads arranged in a matrix pattern. An integrated circuit chip is attached to each of the die pads. An encapsulant material is applied over the integrated circuit chips and at least a part of the large panel leadframe. Each of the die pads and its corresponding leads are separated from the large panel leadframe to form individual integrated circuit packages. The steps of attaching the integrated circuit chips and applying the encapsulant material are performed while the large panel leadframe is mounted to a taped ring.

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Номер записи: 28
06-06-2013 дата публикации

Electronic Device and a Method for Fabricating an Electronic Device

Номер: US20130140685A1
Автор: Alexander Heinrich, Kok Chai Goh, Konrad Roesl, Michael Juerss, Oliver EICHINGER, Tobias Schmidt
Принадлежит: INFINEON TECHNOLOGIES AG

The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

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Номер записи: 29
13-06-2013 дата публикации

Semiconductor device

Номер: US20130147064A1
Автор: Tomoaki Uno, Yukihiro Sato
Принадлежит: Renesas Electronics Corp

The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7 D 2 , a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.

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Номер записи: 30
04-07-2013 дата публикации

Apparatus for integrated circuit packaging

Номер: US20130168839A1
Автор: Ying Zhao
Принадлежит: Analog Devices Inc

Apparatuses are disclosed, such as those involving integrated circuit packaging. In one embodiment, a chip package includes: an encapsulation having a top surface and a bottom surface facing away from the top surface. The package further includes a leadframe including a plurality of leads. Each of the leads includes an exposed portion exposed through one of edges of the bottom surface of the encapsulation. The exposed portion has a length. At least one of exposed portions positioned along one of the edges of the bottom surface of the encapsulation has a length different from other exposed portions along the edge. The package can also include a dummy pad exposed through a corner of the bottom surface. The configuration can enhance solder joint reliability of the package when the package is attached to a printed circuit board.

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Номер записи: 31
08-08-2013 дата публикации

Package manufacturing method and semiconductor device

Номер: US20130200505A1
Автор: Koji Ono
Принадлежит: Canon Inc

A method for manufacturing a package comprises a first step of forming a metal pattern including a frame and a plurality of leads extending inward from the frame, a second step of molding a resin pattern including a first resin portion which holds the plurality of leads from an inner side thereof, and second resin portions which cover bottom surfaces of peripheral portions, adjacent to portions to be removed, in the plurality of leads while exposing bottom surfaces of the portions to be removed in the plurality of leads, so as to hold the plurality of leads from a lower side thereof, and a third step of cutting the plurality of leads into a plurality of first leads and a plurality of second leads by removing the portions to be removed in the plurality of leads while the resin pattern keeps holding the peripheral portions in the plurality of leads.

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Номер записи: 32
15-08-2013 дата публикации

Method of forming an electronic package and structure

Номер: US20130208439A1
Автор: Azhar Aripin
Принадлежит: Individual

In one embodiment, an electronic package structure includes multiple rows of I/O pads and is formed without a flag portion. An electronic device may be attached to a pair of adjacent inner rows of I/O pads. The pair of adjacent inner rows of I/O pads is configured to support, at least in part, the electronic device, and to receive connective structures, such as wire bonds. Connective structures may electrically connect the electronic device to the multiple rows of I/O pads, and an encapsulating layer covers portions of the I/O pads, the electronic device and the connective structures.

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Номер записи: 33
22-08-2013 дата публикации

DC/DC Converter Power Module Package Incorporating a Stacked Controller and Construction Methodology

Номер: US20130214399A1
Автор: Ashok S. Prabhu, Jaime Bayan, Rajeev Joshi
Принадлежит: National Semiconductor Corp

Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices.

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Номер записи: 34
29-08-2013 дата публикации

SEMICONDUCTOR PACKAGE

Номер: US20130221503A1
Автор: Yamane Tae
Принадлежит:

A semiconductor package including a semiconductor chip; a base member on which the semiconductor chip is mounted; a plurality of leads formed on the base member, the leads including inner ends electrically connected to the semiconductor chip and outer ends; and an index for identifying locations of specific leads. 1. A semiconductor device , comprising:a semiconductor chip having a first side and a second side opposite the first side;a plurality of electrode pads disposed on the semiconductor chip along the first side;a base member on which the semiconductor chip is mounted; and a first index lead, a second index lead and a plurality of inner leads disposed on the base member, the inner leads being arranged between the first index lead and the second index lead, and the first index lead, the second index lead and the inner leads being electrically connected with the electrode pads of the semiconductor chip across the first side of the semiconductor chip,wherein a first distance between ends of the first and second index leads and the first side is longer than a second distance between each of ends of the inner leads and the first side, andwherein all ends of the inner leads are coincident with a line which is in parallel to the first side.2. The semiconductor device according to the claim 1 , wherein the first and second index leads are longer than the inner leads.3. The semiconductor device according to the claim 1 , wherein the first index lead claim 1 , the second index lead and the inner leads are electrically connected with the electrode pads of the semiconductor chip via aurous bumps.4. The semiconductor device according to the claim 1 , wherein the first index lead claim 1 , the second index lead and the inner leads are made from copper.5. The semiconductor device according to the claim 4 , wherein the first index lead claim 4 , the second index lead and the inner leads are covered with tin.6. The semiconductor device according to the claim 1 , wherein a ...

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Номер записи: 35
29-08-2013 дата публикации

PRINTED WIRING BOARD

Номер: US20130221505A1
Автор: FURUSAWA Takeshi, FURUTANI Toshiki
Принадлежит: IBIDEN CO., LTD.

A printed wiring board includes a substrate, a first buildup formed on a first surface of the substrate and including the outermost conductive layer, and a second buildup layer formed on a second surface of the substrate and including the outermost conductive layer. The outermost layer of the first buildup has pads positioned to connect a semiconductor component, the first buildup has a component mounting region directly under the component such that the outermost layer of the first buildup has a portion in the region, the outermost layer of the second buildup has a portion directly under the region, and the portions satisfy the ratio in the range of from 1.1 to 1.35, where the ratio is obtained by dividing a planar area of the portion of the second buildup by a planar area of the portion of the first buildup. 1. A printed wiring board , comprising:a substrate having a first surface and a second surface on an opposite side of the first surface;a first buildup layer formed on the first surface of the substrate and comprising a resin insulation layer and a plurality of conductive layers including an outermost conductive layer; anda second buildup layer formed on the second surface of the substrate and comprising a resin insulation layer and a plurality of conductive layers including an outermost conductive layer,wherein the outermost conductive layer of the first buildup layer has a plurality of pads positioned to connect a semiconductor element, the first buildup layer has a component mounting region directly under the semiconductor element such that the outermost conductive layer of the first buildup layer has a conductive portion in the component mounting region, the outermost conductive layer of the second buildup layer has a conductive portion directly under the component mounting region, and the conductive portion in the outermost conductive layer of the first buildup layer and the conductive portion in the outermost conductive layer of the second buildup layer ...

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Номер записи: 36
26-09-2013 дата публикации

Integrated circuit packaging system with terminals and method of manufacture thereof

Номер: US20130249077A1
Автор: Arnel Senosa Trasporto, Byung Tai Do, Linda Pei Ee CHUA
Принадлежит: Stats Chippac Pte Ltd

A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a mounting platform; applying an attach layer on the mounting platform; mounting an integrated circuit die on the attach layer; forming an encapsulation on the integrated circuit die and the attach layer, the mounting platform exposed from the encapsulation; and forming a terminal having a terminal protrusion from the leadframe, the terminal protrusion below a horizontal plane of the mounting platform.

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Номер записи: 37
03-10-2013 дата публикации

Lead frame, semiconductor device, and method for manufacturing lead frame

Номер: US20130256854A1
Автор: Hiroshi Shimizu, Kazutaka Kobayashi, Toshio Kobayashi, Toshiyuki Okabe, Yasuyuki Kimura
Принадлежит: Shinko Electric Industries Co Ltd

A lead frame includes a plurality of leads defined by an opening extending in a thickness direction. An insulating resin layer fills the opening to entirely cover side surfaces of each lead and to support the leads. A first surface of each lead is exposed from a first surface of the insulating resin layer.

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Номер записи: 38
03-10-2013 дата публикации

SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF

Номер: US20130256860A1
Автор: Koike Nobuya, Sato Yukihiro
Принадлежит:

There is provided a technology enabling the improvement of the reliability of a semiconductor device manufactured by physically fixing separately formed chip mounting portion and lead frame. A feature of an embodiment resides in that, a second junction portion formed in a suspension lead is fitted into a first junction portion formed in a chip mounting portion, thereby to physically fix the chip mounting portion and the suspension lead. Specifically, the first junction portion is formed of a concave part disposed in the surface of the chip mounting portion. The second junction portion forms a part of the suspension lead. 1. A semiconductor device , comprising:(a) a semiconductor chip including a plurality of pads formed over the surface thereof;(b) a first member having a top surface including the semiconductor chip mounted thereover, and a bottom surface on the opposite side of the top surface;(c) a suspension lead fixed with the first member;(d) a plurality of leads disposed around the first member;(e) a plurality of wires each for electrically coupling each of the pads formed over the semiconductor chip with each of the leads; and(f) a sealing body for sealing the semiconductor chip, a part of the first member, a part of the suspension lead, a part of each of the leads, and, the wires,wherein in the first member, a first junction portion formed of a concave part is formed,wherein the suspension lead includes a second junction portion, andwherein fixing between the first member and the suspension lead is performed by fitting the second junction portion into the first junction portion.2. The semiconductor device according to claim 1 ,wherein fixing between the first member and the suspension lead is performed by inserting and compression-bonding the second junction portion into the first junction portion.3. The semiconductor device according to claim 2 ,wherein the depth of the concave part is larger than the thickness of the second junction portion.4. The ...

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Номер записи: 39
10-10-2013 дата публикации

Lead frame with grooved lead finger

Номер: US20130264693A1
Автор: Kok Leong Chan, Wai Keong Wong, Wei Kee CHAN
Принадлежит: FREESCALE SEMICONDUCTOR INC

A lead finger of a lead frame has a number of channels or grooves in a portion of its top surface that provide a locking mechanism for securing a bond wire to the lead finger. The bond wire may be attached to the lead finger by stitch bonding.

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Номер записи: 40
24-10-2013 дата публикации

Arrangements For An Integrated Sensor

Номер: US20130277782A1
Автор: Michael C. Doogue, Vijay Mangtani, William P. Taylor
Принадлежит: Allegro Microsystems LLC

An integrated circuit can have a first substrate supporting a magnetic field sensing element and a second substrate supporting another magnetic field sensing element. The first and second substrates can be arranged in a variety of configurations. Another integrated circuit can have a first magnetic field sensing element and second different magnetic field sensing element disposed on surfaces thereof.

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Номер записи: 41
07-11-2013 дата публикации

LEAD FRAME FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE PACKAGE USING THE LEAD FRAME

Номер: US20130292812A1
Автор: CHO Kyu-chae, HAN Jae-kwan, SEO Young-chun
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A lead frame for a semiconductor device and a semiconductor device package using the lead frame. The lead frame includes a package body having an internal space configured to mount a semiconductor device, and a lead unit disposed so as to apply voltages to the semiconductor device. The lead unit includes internal leads embedded in the package body and having an area in which the semiconductor device is to be mounted, and external leads each being connected to the internal leads, respectively . Each external lead protrudes from the package body and each has a contact portion that contacts a printed circuit board (PCB). The lead frame also includes and a support structure disposed on external sides of the package body and supporting the external leads. 1. A lead frame comprising:a package body having an internal space configured to mount a semiconductor device;a lead unit disposed so as to apply voltages to the semiconductor device and comprising internal leads embedded in the package body and having an area in which the semiconductor device is to be mounted, and external leads each being connected to the internal leads, respectively, each protruding from the package body and each having a contact portion that contacts a printed circuit board (PCB); anda support structure disposed on external sides of the package body and supporting the external leads.2. The lead frame of claim 1 , wherein the lead unit comprises a first lead unit and a second lead unit claim 1 , andthe first lead unit comprises a first internal lead and a first external lead,the second lead unit comprises a second internal lead and a second external lead, andthe first external lead and the second external lead are bent along the external sides of the package body.3. The lead frame of claim 2 , wherein the external sides of the package body comprise:a left side;a right side that faces the left side;a front side that connects the left side and the right side;a rear side that faces the front side; anda ...

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Номер записи: 42
14-11-2013 дата публикации

Plated terminals with routing interconnections semiconductor device

Номер: US20130299979A1
Автор: Saravuth Sirinorakul
Принадлежит: UTAC Thai Ltd

A semiconductor package includes terminals, each having an exposed surface that is flush with a bottom surface of the semiconductor package, and a layer of interconnection routings disposed within the semiconductor package. At least one interconnection routing is electrically coupled with a terminal and extends planarly therefrom. The semiconductor package also includes at least one die coupled with the layer of interconnection routings. In some embodiments, the semiconductor package also includes one or more additional intermediary layers. Each intermediary layer includes a via layer and an associated routing layer. The associated routing layer includes associated routings. At least one associated routing is electrically coupled with a terminal and extends planarly therefrom. Each via layer couples two routing layers. The semiconductor package also includes a locking mechanism for fastening a package compound with the interconnection routings and the terminals.

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Номер записи: 43
21-11-2013 дата публикации

Conductive chip disposed on lead semiconductor package and methods of making the same

Номер: US20130307134A1
Автор: David Chong, Jatinder Kumar
Принадлежит: Fairchild Semiconductor Corp

In one implementation, a method of forming a conductive device can include depositing a non-conductive epoxy on a first portion of a lower surface of a semiconductor die, and can include depositing a conductive epoxy on a second portion of the lower surface of the semiconductor die.

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Номер записи: 44
02-01-2014 дата публикации

Wiring substrate and semiconductor device

Номер: US20140001648A1
Автор: Atsushi Nakamura, Mitsuyoshi Imai
Принадлежит: Shinko Electric Industries Co Ltd

A wiring substrate includes an adhesive layer, a wiring layer, and a support substrate. The adhesive layer includes a first surface and a second surface that is opposite to the first surface. The wiring layer is formed on the first surface of the adhesive layer. The support substrate is formed on the second surface of the adhesive layer. The wiring layer is partially exposed in a through hole extending through the adhesive layer and the support substrate in a thicknesswise direction. The support substrate is adhered to the adhesive layer in a removable manner.

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Номер записи: 45
02-01-2014 дата публикации

Sgs or gsgsg pattern for signal transmitting channel, and pcb assembly, chip package using such sgs or gsgsg pattern

Номер: US20140002935A1
Автор: Nan-Jang Chen, Yau-Wai Wong
Принадлежит: MediaTek Inc

A printed circuit board (PCB) assembly includes a PCB having a core substrate, a plurality of conductive traces on a first surface of the PCB, and a ground layer on the second surface of the PCB. The conductive traces comprise a pair of differential signal traces. An intervening reference trace is disposed between the differential signal traces. A connector is disposed at one end of the plurality of conductive traces. A semiconductor package is mounted on the first surface at the other end of the plurality of conductive traces.

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Номер записи: 46
09-01-2014 дата публикации

MOUNTING SUBSTRATE AND OPTICAL UNIT

Номер: US20140008674A1
Автор: Aoyagi Akiyoshi, Doi Masato, Ohshige Yoichi, Watanabe Toshihiko
Принадлежит: SONY CORPORATION

A mounting substrate includes: a wiring substrate; and a plurality of optical elements mounted on a mounting surface of the wiring substrate, and each having a first electrode and a second electrode. The wiring substrate includes a support substrate, a plurality of first wires, and a plurality of second wires. The first wires and the second wires are provided within a layer between the support substrate and the mounting surface. The first wires are electrically connected with the first electrodes. The second wires are electrically connected with the second electrodes, and each have cross-sectional area larger than cross-sectional area of each of the first wires. 1. A mounting substrate , comprising:a wiring substrate; anda plurality of optical elements mounted on a mounting surface of the wiring substrate, and each having a first electrode and a second electrode, whereinthe wiring substrate includes a support substrate, a plurality of first wires, and a plurality of second wires, the first wires and the second wires being provided within a layer between the support substrate and the mounting surface,the first wires are electrically connected with the first electrodes, andthe second wires are electrically connected with the second electrodes and are disposed within a layer between the support substrate and a layer that includes the first wires, and each have cross-sectional area larger than cross-sectional area of each of the first wires.2. The mounting substrate according to claim 1 , whereinthe plurality of first wires extend in a first direction and are disposed side-by-side, the first wires being disposed to avoid locations beneath the respective optical elements, andthe plurality of second wires extend in a second direction intersecting with the first direction and are disposed side-by-side in a direction intersecting with the second direction, the second wires being disposed without avoiding the locations beneath the respective optical elements.3. The mounting ...

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Номер записи: 47
09-01-2014 дата публикации

LIGHT-EMITTING DEVICE AND LEAD FRAME STRIP

Номер: US20140008693A1
Автор: FENG YA-CHING
Принадлежит:

A light-emitting device in one embodiment comprises a lead frame, an adhesive, and a light-emitting element. The lead frame comprises two conductive members. The two conductive members are separated by a gap. Each conductive member comprises an upper surface and a lower surface. The upper surface and the lower surface are opposite to each other. The adhesive fills the gap and partially covers the upper and lower surfaces of each conductive member. The light-emitting element is disposed on the upper surface of one conductive member. The light-emitting element electrically connects the two conductive members. 1. A light-emitting device comprising:a lead frame comprising two conductive members separated by a gap, wherein each conductive member comprises an upper surface and a lower surface opposite to the upper surface;an adhesive filling the gap and partially covering the upper and lower surfaces of each conductive member; anda light-emitting element disposed on the upper surface of one conductive member of the two conductive members, electrically connecting the two conductive members.2. The light-emitting device of claim 1 , wherein the adhesive protrudes from the upper surface of each conductive member to a thickness of not less than ten micrometers.3. The light-emitting device of claim 1 , wherein the adhesive protrudes from the upper surface of each conductive member to a thickness in a range of from 25 micrometers to 35 micrometers.4. The light-emitting device of claim 1 , wherein the adhesive protrudes from the upper surface of each conductive member to a thickness of not less than 30 micrometers.5. The light-emitting device of claim 1 , wherein the adhesive extends from the gap onto the upper surface of each conductive member to a distance of not less than one micrometer.6. The light-emitting device of claim 1 , wherein the adhesive extends from the gap onto the upper surface of each conductive member to a distance of not less than five micrometers.7. The light ...

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Номер записи: 48
16-01-2014 дата публикации

Very extremely thin semiconductor package

Номер: US20140015117A1
Автор: Saravuth Sirinorakul, Somchai Nondhasitthichai
Принадлежит: UTAC Thai Ltd

A package and method of making thereof. The package includes a first plated area, a second plated area, a die, a bond, and a molding. The die is attached to the first plated area, and the bond couples the die to the first and/or the second plated areas. The molding encapsulates the die, the bonding wire, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package.

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Номер записи: 49
23-01-2014 дата публикации

LOWER SEMICONDUCTOR MOLDING DIE, SEMICONDUCTOR PACKAGE, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE

Номер: US20140021593A1
Автор: JANG Ae-nee, JANG Jae-gwon, KIM Young-lyong
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor package may include a circuit board chip having a through-hole, a semiconductor device mounted on the circuit board chip, and an encapsulant. The encapsulant encapsulates the semiconductor device, fills the through-hole and has an external pattern that is the complement of a mold within which the encapsulant was formed. The external pattern on one side of the package reflects a mold shape that retards the flow of encapsulant material relative to the flow of encapsulant material on the opposite side of the package. 1. A semiconductor package molding die comprising:a mounting surface configured for receiving a plurality of circuit board chips, each having a through-hole; anda plurality of window patterns, each aligned with the through-hole of a circuit board chip, each window pattern extending in a first direction under a corresponding one of the circuit board chips,wherein each of the window patterns comprises a first passage pattern having a first width and a second passage pattern having a second width different from the first width.2. The molding die of claim 1 , further configured for receiving an encapsulant which fills the through-hole and the window patterns.3. The molding die of claim 1 , wherein the first passage pattern and the second passage pattern are connected alternately in the first direction.4. The molding die of claim 1 , wherein the second width is greater than the first width.5. The molding die of claim 4 , wherein the second passage pattern is deeper than the first passage pattern.6. The molding die of claim 4 , wherein the second passage pattern is longer than the first passage pattern.7. The molding die of claim 6 , wherein the first passage pattern is disposed adjacent to an end of each of the circuit board chips claim 6 , and the second passage pattern is disposed adjacent to the through-hole of each of the circuit board chips.8. The molding die of claim 4 , wherein each of the window patterns further comprises a third passage ...

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Номер записи: 50
30-01-2014 дата публикации

SYSTEM AND METHOD TO MANUFACTURE AN IMPLANTABLE ELECTRODE

Номер: US20140027888A1
Автор: GULARI MAYURACHAT NING, Hetke Jamille Farraye, Kipke Daryl R., Kong Kc, Pellinen David S., Vetter Rio J.
Принадлежит: NeuroNexus Technologies, Inc.

The method of the preferred embodiments includes the steps of providing a base having a frame portion and a center portion; building a preliminary structure coupled to the base; removing a portion of the preliminary structure to define a series of devices and a plurality of bridges; removing the center portion of the base such that the frame portion defines an open region, wherein the plurality of bridges suspend the series of devices in the open region defined by the frame; and encapsulating the series of devices. The method is preferably designed for the manufacture of semiconductor devices, and more specifically for the manufacture of encapsulated implantable electrodes. The method, however, may be alternatively used in any suitable environment and for any suitable reason. 1. An implantable electrode system , comprising:a) a wafer comprising a frame portion defining an open region;b) at least a first electrode structure comprising a first conductive lead and at least one of a first stimulation electrode site and a first recording electrode site; andc) at least a first and a second bridges, the first bridge extending from a first bridge frame end connected to the frame portion to a first bridge electrode end connected to the first electrode structure in the open region, and the second bridge extending from a second bridge frame end connected to the frame portion spaced from the first bridge frame end to a second bridge electrode end connected to the first electrode structure in the open region,d) wherein the first electrode structure is connected to the first and second bridges in the open region, spaced from the frame portion to be thereby suspended in the open region defined by the frame portion of the base by the first and second bridges.2. The implantable electrode system of further including:a) at least a second electrode structure comprising a second conductive lead and at least one of a second stimulation electrode site and a second recording electrode site ...

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Номер записи: 51
30-01-2014 дата публикации

RESIN MOLDED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20140027894A1
Автор: Saito Kiyoshi, UMETANI Yuji, YOSHIMI Hideaki
Принадлежит:

This invention is directed to provide a method of manufacturing a resin molded semiconductor device with high reliability by preventing a resin leakage portion from occurring due to burrs on a lead frame formed by punching. The method of manufacturing the resin molded semiconductor device according to the invention includes bonding a semiconductor die on an island in a lead frame, electrically connecting the semiconductor die with the lead frame, resin-molding the lead frame on which the semiconductor die is bonded, and applying prior to the resin-molding a compressive pressure that is higher than a clamping pressure applied in the resin-molding to a region of the lead frame being clamped by molds in the resin-molding of the lead frame. 13-. (canceled)4. A resin molded semiconductor device , comprising:a semiconductor die;a lead; anda resin package in which the semiconductor die and part of the lead are embedded,wherein the lead comprises a dent portion which extends from inside the resin package to outside the resin package and is formed on a top side of the lead, the top side being the same side as the side of the lead on which the semiconductor die is disposed.5. The resin molded semiconductor device of claim 4 , wherein a surface roughness of the dent portion is smaller than a surface roughness of the lead not having the dent portion.6. The resin molded semiconductor device of claim 4 , wherein burrs of the dent portion is smaller than burrs of the lead not having the dent portion.7. The resin molded semiconductor device of claim 4 , further comprising a wire that is bonded to the lead at a position of the lead that is closer to the semiconductor die than to the dent potion.8. The resin molded semiconductor device of claim 4 , wherein the device is part of a single in-line package.9. The resin molded semiconductor device of claim 4 , wherein the device is part of a quad flat package.10. The resin molded semiconductor device of claim 4 , wherein the semiconductor ...

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Номер записи: 52
06-02-2014 дата публикации

Thin Leadframe QFN Package Design of RF Front-Ends for Mobile Wireless Communication

Номер: US20140036471A1
Автор: Cindy Yuen, Duc Chu
Принадлежит: Individual

Systems and methods are disclosed herein for a low cost, compact size, and thin half-etched leadframe quad-flat no-leads (QFN) package that integrates RF passive elements in the QFN leadframe for linearized PA design and RF FEMs. The integrated RF passive elements in the QFN leadframe may include RF inductors (e.g., meanders lines or spirals) for amplifier bias or RF matching, extension bar of the ground paddle for inter-stage matching or jumper pads for connection. The integrated RF passive elements may also include transmission lines for output power matching, coupled line structures such as RF couplers, RF divider or combiner realized using transmission lines with proper impedance and length, jumper pads for adjusting the bond wire length, etc. The RF parameters of the integrated passive elements are adjustable using different length and number of wire bond for fine tuning the performance of the PAM or the RF FEM.

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Номер записи: 53
06-02-2014 дата публикации

Method for plating a semiconductor package lead

Номер: US20140038356A1
Автор: Leo M. Higgins, III
Принадлежит: Individual

A method of forming a packaged semiconductor device includes loading an array of package sites in position for saw singulation, saw singulating the array of package sites, and performing a non-electrolytic plating operation on exposed lead tips of individual packages from the array of package sites as the array of package sites is saw singulated.

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Номер записи: 54
20-02-2014 дата публикации

Selective Leadframe Planishing

Номер: US20140048920A1
Автор: Abbott Donald C.
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

A metal leadframe strip () for semiconductor devices comprising a plurality of sites () for assembling semiconductor chips, the sites alternating with zones () for connecting the leadframe to molding compound runners; the sites () having mechanically rough and optically matte surfaces (); the zones () having at least portions with mechanically flattened and optically shiny metal surfaces (); and the flattened surface portions transitioning into the rough surface portions by a step. 1. A metal leadframe strip for semiconductor devices comprising:a plurality of sites for assembling semiconductor chips, the sites alternating with zones for connecting the leadframe to molding compound runners;the sites having a mechanically rough and optically matte surface; andthe zones having at least portions with a mechanically flattened and optically shiny metal surface, the flattened surface portions transitioning into the rough surface portions by a step.2. The leadframe strip of further including the mechanically rough and optically matte surface of the sites on both sides of the leadframe claim 1 , and the mechanically flattened and optically shiny surface of the zones on both sides of the leadframe.3. The leadframe strip of wherein the rough metal surfaces have an average roughness of 90±20 nm claim 1 , enhancing the adhesion of the leadframe metal to a molding compound.4. The leadframe strip of wherein the flattened metal surfaces have an average roughness of 35±20 nm claim 3 , reducing the adhesion of the leadframe metal to a molding compound.5. The leadframe strip of wherein the flattened metal surfaces have been created by selectively planishing portions of the rough surfaces of the leadframe strip claim 4 , wherein the planishing process causes a thickness reduction of the rough-surface leadframe metal by 10±5%.6. The leadframe strip of wherein the step spacing the smooth surface portions from the rough surface portions equals the thickness reduction of the rough-surface ...

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Номер записи: 55
27-02-2014 дата публикации

STACKED DUAL CHIP PACKAGE HAVING LEVELING PROJECTIONS

Номер: US20140054758A1
Автор: Amato John, Bhalla Anup, Liu Kai, Lu Jun, So Yueh-Se, Xue Yan Xun, Yilmaz Hamza, Zhang Xiaotian
Принадлежит: Alpha and Omega Semiconductor Incorporated

The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication. 1. A semiconductor package comprising:a first semiconductor die;a dip structure attached to the first semiconductor die; anda plurality of leveling projections located between the clip structure and the first semiconductor die, such that the clip structure is parallel with the semiconductor die, wherein an adhesive material is located between at least some of the leveling projections, attaching the clip structure to the first semiconductor die.2. The package of wherein said leveling projections have a common height.3. The package of wherein said clip structure is in electrical communication with a package lead.4. The package of wherein the leveling projections are electrically non-conductive.5. The package of wherein at least some of said adhesive material is electrically conductive and located between at least some of the leveling projections claim 4 , electrically connecting at least a portion of the clip structure to the first semiconductor die.6. The package of wherein the clip structure further comprises a first conductive segment and a second conductive segment.7. The package of wherein the tops of the first and second conductive segments are co-planar.8. The package of wherein the first conductive segment is conductively attached to the first semiconductor die claim 7 , and the second conductive segment is superimposed with but electrically isolated from the first semiconductor die.9. The package of further comprising a second semiconductor chip stacked on the clip structure on a side opposite that of the first semiconductor die.10. A semiconductor package comprising:a first semiconductor die;a clip structure, having first and second conductive segments, attached to the first semiconductor die; anda plurality of ...

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Номер записи: 56
27-02-2014 дата публикации

Method of manufacturing semiconductor device

Номер: US20140054759A1
Автор: Hiroyoshi Taya, Tadatoshi Danno, Yoshiharu Shimizu
Принадлежит: Renesas Electronics Corp

A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for supporting the tab, leads having respective surfaces exposed to outer edge portions of a back surface of the sealing body, and wires connecting pads formed on the semiconductor chip and the leads. End portions of the suspension leads positioned in an outer periphery portion of the sealing body are unexposed to the back surface of the sealing body, but are covered with the sealing body. Stand-off portions of the suspending leads are not formed in resin molding. When cutting the suspending leads, corner portions of the back surface of the sealing body are supported by a flat portion of a holder portion in a cutting die having an area wider than a cutting allowance of the suspending leads, whereby chipping of the resin is prevented.

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Номер записи: 57
06-03-2014 дата публикации

Electronic device and semiconductor device

Номер: US20140061821A1
Автор: Hiroyuki Nakamura, Kenya Kawano, Yukihiro Sato
Принадлежит: Renesas Electronics Corp

Provided is an electronic device having a semiconductor device and a mounting board. The semiconductor device has a die pad, a semiconductor chip on the die pad, a coupling member coupling the die pad to the semiconductor chip, and a semiconductor package member covering the upper portion of the semiconductor chip and the side surface of the die pad. In this semiconductor device, the plane area of the coupling member coupling the mounting board to the die pad is smaller than the plane area of the lower surface of the die pad exposed from the semiconductor package material. This makes it possible to reduce separation between the die pad and the semiconductor chip resulting from cracks, due to temperature cycling, of the coupling member present between the die pad and the semiconductor chip.

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Номер записи: 58
06-03-2014 дата публикации

Leadframes, air-cavity packages, and electronic devices with offset vent holes, and methods of their manufacture

Номер: US20140061883A1
Автор: Philip H. Bowles, Stephen R. Hooper
Принадлежит: Individual

A leadframe (e.g., incorporated in a device package) includes a feature (e.g., a die pad or lead) with a vent hole formed between first and second opposed surfaces. The cross-sectional area of the vent hole varies substantially between the surfaces (e.g., the vent hole has a constricted portion). The vent hole may be formed from a first opening extending from the first surface toward the second surface to a first depth that is less than a thickness of the leadframe feature, and a second opening extending from the second surface toward the first surface to a second depth that is less than the thickness of the leadframe feature, but that is large enough for the second opening to intersect the first opening. Vertical central axes of the openings are horizontally offset from each other, and the constricted portion of the vent hole corresponds to the intersection of the openings.

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Номер записи: 59
13-03-2014 дата публикации

Manufacturing method of semiconductor device and semiconductor device

Номер: US20140070389A1
Автор: Naoko Taniguchi, Yoshiharu Kaneda
Принадлежит: Renesas Electronics Corp

To enhance the reliability of a semiconductor device. The semiconductor device includes die pads, over which a first semiconductor chip and a second semiconductor chip are mounted respectively, a plurality of support pins that support each of the die pads, a plurality of inner leads and outer leads arranged around the die pads, a plurality of wires that electrically couple the semiconductor chips to the inner leads, and a sealing body that seals the semiconductor chips, the inner leads, and the wires. Each of the die pads is supported by three support pins integrally formed together with the die pad, and each of second support pins of each pair of the three support pins is arranged between the inner leads adjacent to each other.

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Номер записи: 60
20-03-2014 дата публикации

SEMICONDUCTOR DEVICE AND LEAD FRAME USED FOR THE SAME

Номер: US20140077348A1
Автор: GOTO Yoshiaki
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame. 19-. (canceled)10. A semiconductor memory device , comprising:an element-mounting region;a semiconductor memory element mounted on the element-mounting region;a rectangular region sealing the semiconductor memory element with resin;an element-supporting portion supporting the semiconductor memory element, the element-supporting portion having an opening;a plurality of first hanging elements provided at a first long edge side of the rectangular region, and extending from the element-supporting portion to the first long edge;an outer lead portion having a plurality of outer leads arranged at first and second short edge sides of the rectangular region; andan inner lead portion having a plurality of inner leads, at least a part of the inner leads being routed in the element-mounting region, and one end of at least one of the inner leads being arranged at a second long edge side of the rectangular region,wherein at least a part of the inner leads has a first portion extended to the one end of the inner leads, a second portion extended to the outer leads arranged at the first short edge side, and a third portion routed in the element-mounting region so as to extend in a direction which intersects the first and second portions,wherein at least another part of the inner leads has a fourth portion extended to the one end of the inner ...

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Номер записи: 61
27-03-2014 дата публикации

Semiconductor Device Having a Clip Contact

Номер: US20140084433A1
Автор: Josef Hoeglauer, Khalil Hosseini, Ralf Otremba
Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device comprises a carrier. Further, the semiconductor devices comprises a semiconductor chip comprising a first main surface and a second main surface opposite to the first main surface, wherein a first electrode is arranged on the first main surface and the semiconductor chip is mounted on the carrier with the second main surface facing the carrier. Further, an encapsulation body embedding the semiconductor chip is provided. The semiconductor device further comprises a contact clip, wherein the contact clip is an integral part having a bond portion bonded to the first electrode and having a terminal portion forming an external terminal of the semiconductor device.

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Номер записи: 62
27-03-2014 дата публикации

Resin-encapsulated semiconductor device and method of manufacturing the same

Номер: US20140084435A1
Автор: Noriyuki Kimura
Принадлежит: Seiko Instruments Inc

A resin-encapsulated semiconductor device includes: a semiconductor element mounted on a die pad portion; a plurality of lead portions disposed so that distal end parts thereof are opposed to the die pad portion; a metal thin wire for connecting an electrode of the semiconductor element to the lead portion; and an encapsulating resin for partially encapsulating those components. A bottom surface part of the die pad portion, and a bottom surface part, an outer surface part, and an upper end part of the lead portion are exposed from the encapsulating resin. A plated layer is formed on the exposed lead bottom surface part and the exposed lead upper end part.

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Номер записи: 63
03-04-2014 дата публикации

SURFACE MOUNT PACKAGE FOR A SEMICONDUCTOR INTEGRATED DEVICE, RELATED ASSEMBLY AND MANUFACTURING PROCESS

Номер: US20140091443A1
Автор: DUCA Roseanne, Formosa Kevin, Goh Kim-Yong, Zhang Xueren
Принадлежит:

A surface mount package of a semiconductor device, has: an encapsulation, housing at least one die including semiconductor material; and electrical contact leads, protruding from the encapsulation to be electrically coupled to contact pads of a circuit board; the encapsulation has a main face designed to face a top surface of the circuit board, which is provided with coupling features designed for mechanical coupling to the circuit board to increase a resonant frequency of the mounted package. The coupling features envisage at least a first coupling recess defined within the encapsulation starting from the main face, designed to be engaged by a corresponding coupling element fixed to the circuit board, thereby restricting movements of the mounted package. 1. A surface mount package comprising:an encapsulation housing a die of semiconductor material, the encapsulation including a first surface having a coupling element configured to mechanically engage a corresponding coupling element of a first surface of a circuit board; andelectrical contact leads protruding from the encapsulation and configured to be coupled to contact pads of the first surface of the circuit board.2. The package according to claim 1 , wherein the coupling element of the encapsulation is a recess claim 1 , to wherein the engagement between the recess and the coupling element of the circuit board restricts movement of the encapsulation when the package is mounted onto the first surface of the circuit board.3. The package according to claim 2 , wherein the recess has a depth along a direction transverse to the first surface comprised between 50 μm and 150 μm.4. The package according to claim 3 , wherein the recess is a first recess claim 3 , the package further comprising a second recess claim 3 , the second recess being configured to receive a second coupling element of the first surface of the circuit board.5. The package according to claim 4 , wherein the encapsulation has a generically ...

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Номер записи: 64
10-04-2014 дата публикации

LEADFRAME FOR SEMICONDUCTOR PACKAGES

Номер: US20140097012A1
Автор: Cheng Tao
Принадлежит: MEDIATEK INC.

A leadframe for semiconductor packages is provided. The leadframe includes a die pad, a side rail, a tie bar, and a plurality of leads. The side rail is around the die pad. The tie bar connects the die pad and the side rail. The leads extend from the side rail to close proximity to the die pad. The leads includes a first lead and a second lead being at opposite locations of the leadframe relative to a center line through the die pad. The first and second leads are substantially asymmetrical with each other relative to the center line and have different impedance values. The plurality of leads are disconnected to each other. 1. A leadframe for semiconductor packages , comprising:a die pad;a side rail around the die pad;a tie bar connecting the die pad and the side rail; anda plurality of leads extending from the side rail in close proximity to the die pad, comprising a first lead and a second lead being at opposite locations of the leadframe relative to a center line through the die pad, wherein the first and second leads are substantially asymmetrical with each other relative to the center line and have different impedance values, wherein the plurality of leads are disconnected to each other.2. The leadframe as claimed in claim 1 , wherein the first and second leads comprise substantially different lead lengths.3. The leadframe as claimed in claim 1 , wherein the first and second leads comprise substantially different lead widths.4. The leadframe as claimed in claim 1 , wherein the first and second leads comprise substantially asymmetrical extending traces.5. The leadframe as claimed in claim 1 , wherein the plurality of leads further comprise a third lead adjacent to the first lead claim 1 , and a fourth lead adjacent to the second lead.6. The leadframe as claimed in claim 5 , wherein a space between the first and third leads is substantially different from that between the second and fourth leads.7. The leadframe as claimed in claim 5 , wherein a pitch between the ...

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Номер записи: 65
10-04-2014 дата публикации

Power Quad Flat No-Lead (PQFN) Package in a Single Shunt Inverter Circuit

Номер: US20140097531A1
Автор: Barbosa Roel, Fernando Dean, Takahashi Toshio
Принадлежит: INTERNATIONAL RECTIFIER CORPORATION

According to an exemplary implementation, a power quad flat no-lead (PQFN) package includes a driver integrated circuit (IC) situated on a leadframe. The PQFN package further includes low-side U-phase, low-side V-phase, and low-side W-phase power switches situated on the leadframe. A logic ground of the leadframe is coupled to a support logic circuit of the driver IC. A power stage ground of the leadframe is coupled to sources of the low-side U-phase, low-side V-phase, and low-side W-phase power switches. The power stage ground can further be coupled to gate drivers of the driver IC. 1. A power quad flat no-lead (PQFN) package comprising:a driver integrated circuit (IC) situated on a leadframe;U-phase, V-phase, and W-phase power switches situated on said leadframe;a logic ground of said leadframe coupled to a support logic circuit of said driver IC;a power stage ground of said leadframe coupled to sources of said U-phase, V-phase, and W-phase power switches.2. The PQFN package of claim 1 , wherein said power stage ground is further coupled to gate drivers of said driver IC.3. The PQFN package of claim 1 , comprising at least one wirebond connecting said power stage ground of said leadframe to said source of said W-phase power switch.4. The PQFN package of claim 1 , comprising at least one wirebond connecting said source of said W-phase power switch to said source of said V-phase power switch.5. The PQFN package of claim 1 , comprising at least one wirebond connecting said source of said V-phase power switch to said source of said U-phase power switch.6. The PQFN package of claim 1 , comprising at least one wirebond connecting a power stage ground terminal of said PQFN package to said source of said W-phase power switch.7. The PQFN package of claim 1 , comprising at least one wirebond connecting a logic ground terminal of said PQFN package to said support logic circuit of said driver IC.8. The PQFN package of claim 1 , comprising at least one wirebond connecting said ...

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Номер записи: 66
01-01-2015 дата публикации

Semiconductor device

Номер: US20150001699A1
Автор: Katsuhiko Funatsu, Tomoaki Uno, Yuichi Yato, Yukihiro Sato
Принадлежит: Renesas Electronics Corp

A semiconductor device includes a first chip mounting portion, a first semiconductor chip arranged over the first chip mounting portion, a first pad formed in a surface of the first semiconductor chip, a first lead which serves as an external coupling terminal, a first conductive member which electrically couples the first pad and the first lead, and a sealing body which seals a part of the first chip mounting portion, the first semiconductor chip, a part of the first lead, and the first conductive member. The first conductive member includes a first plate-like portion, and a first support portion formed integrally with the first plate-like portion. An end of the first support portion is exposed from the sealing body, and the first support portion is formed with a first bent portion.

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Номер записи: 67
06-01-2022 дата публикации

SEMICONDUCTOR MODULE AND SEMICONDUCTOR DEVICE USED THEREFOR

Номер: US20220005743A1
Автор: INUTSUKA Yoshihiro, MIZUNO Naohito, Nakano Takahiro, OKURA Yasushi, OSAWA Seigo, TAKENAKA Masayuki
Принадлежит:

A semiconductor module includes a first heat sink member, a semiconductor device, a second heat sink member, a lead frame, a second sealing member. The semiconductor device includes a semiconductor element, a first sealing member for covering the semiconductor element, a first wiring and a second wiring electrically connected to the semiconductor element, and a rewiring layer on the semiconductor element and the sealing member. The second heat sink member is disposed on the semiconductor device. The lead frame is electrically connected to the semiconductor device through a bonding member. The second sealing member covers a portion of the first heat sink member, the semiconductor and a portion of the second heat sink member. A surface of the second heat sink member faces the semiconductor device. The semiconductor device has a portion protruded from an outline of the second surface sink member. 1. A semiconductor module comprising:a first heat sink member; a semiconductor element,', 'a first sealing member covering the semiconductor element,', 'a first wiring and a second wiring electrically connected to the semiconductor element, and', 'a rewiring layer disposed on the semiconductor element and the sealing member;, 'a semiconductor device including'}a second heat sink member disposed on the semiconductor device;a lead frame electrically connected to the semiconductor device through a bonding member; anda second sealing member covering a portion of the first heat sink member, the semiconductor and a portion of the second heat sink member,wherein the second heat sink member has a first surface and a second surface,wherein the second surface of the second heat sink member faces the semiconductor device,wherein the semiconductor device has a portion protruded from an outline of the second surface of the second heat sink member, andwherein the second wiring has an end extending to the portion of the semiconductor device protruded from the outline of the second surface of ...

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Номер записи: 68
06-01-2022 дата публикации

Semiconductor device

Номер: US20220005753A1
Автор: Atsushi Yamaguchi, Hiroyuki SAKAIRI, Takukazu Otsuka
Принадлежит: ROHM CO LTD

Semiconductor device A1 includes: first terminal 201A and second terminal 201B; first switching element 1A including first gate electrode 12A, first source electrode 13A and first drain electrode 14A; and second switching element 1B including second gate electrode 12B, second source electrode 13B and second drain electrode 14B. First switching element 1A and second switching element 1B are connected in series to each other between first terminal 201A and second terminal 201B. Semiconductor device A1 includes first capacitor 3A connected in parallel to first switching element 1A and second switching element 1B between first terminal 201A and second terminal 201B. First switching element 1A and second switching element 1B are aligned in y direction. First capacitor 3A overlaps with at least one of first switching element 1A and second switching element 1B as viewed in z direction. These arrangements serve to suppress surge voltage.

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Номер записи: 69
05-01-2017 дата публикации

Electronic device and method of manufacturing the same

Номер: US20170005025A1
Автор: FROEHLER Ulrich, GRAWERT Felix, KATZMAIER Ernst, KIRCHNER Uwe, MENTE Rene, Otremba Ralf, SCHLOEGL Andreas, Wahl Uwe
Принадлежит:

Various embodiments provide an electronic device, wherein the electronic device comprises a mounting surface configured to mount the electronic device to an external structure and having a first size; a backside electrode having a second size and having arranged thereon a die electrically connected to the backside electrode; wherein the first size is at least three times the second size. 1. An electronic device comprising:a mounting surface configured to mount the electronic device to an external structure and having a first size;a backside electrode having a second size and having arranged thereon a die electrically connected to the backside electrode;wherein the first size is at least three times the second size.2. The electronic device according to claim 1 , wherein the first size is at least five times the second size.3. The electronic device according to claim 1 , further comprising an encapsulation encapsulating at least partially the electronic device.4. The electronic device according to claim 3 , wherein the encapsulation is formed by an encapsulation material at least partially forming the backside of the electronic device.5. The electronic device according to claim 3 , wherein the encapsulation comprises a plurality of encapsulation materials claim 3 , wherein a first encapsulation material covers the backside of the backside electrode and a second encapsulation material covers a frontside of the electronic device.6. The electronic device according to claim 5 , wherein the first encapsulation material has a different dielectric constant than the second encapsulation material.7. The electronic device according to claim 5 , wherein the first encapsulation material has a different specific heat conductivity than the second encapsulation material.8. The electronic device according to claim 1 , wherein the mounting surface and the backside surface partially overlap in area.9. An electronic module comprising{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'an ...

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Номер записи: 70
05-01-2017 дата публикации

LEADFRAME PACKAGE WITH STABLE EXTENDED LEADS

Номер: US20170005028A1
Автор: TALLEDO Jefferson
Принадлежит:

Embodiments of the present disclosure are directed to leadframes having the cantilevered extension that includes an integral support on the end of the lead nearest the die pad. A support integral to the leadframe allows the support to be built to the proper height to support the cantilevered lead in each package and reduces or eliminates the upward, downward, and side to side deflections caused or allowed by supports built-in to the tooling of the manufacturing equipment. Also, by building the support into the leadframe, the leadframes may be pretaped prior to the die attach and wire bonding steps of the manufacturing process. 1. A semiconductor package , comprising:a die pad having a die attach surface;a semiconductor die coupled to the die attach surface of the die pad;a plurality of leads spaced apart from at least one side of the die pad, the plurality of leads having first ends and second ends, the first ends being nearer the die pad than the second ends;lands at the second ends of the plurality of leads;cantilevered beams extending from the lands and forming the first ends of the leads, each of the cantilevered beams having a first surface and a second surface opposite the first surface;encapsulation material located over the semiconductor die and portions of the leads, including the first surfaces and portions of the second surfaces of the cantilevered beams; andat least one cavity in the encapsulation material that exposes portions of the second surfaces of the leads to an environment outside the semiconductor package.2. The semiconductor package of claim 1 , further comprising a conductive wire coupling the semiconductor die to the first surface of one of the cantilevered beams claim 1 , the at least one cavity being formed at the first ends of the leads.3. The semiconductor package of wherein the at least one cavity is a trench exposing the portions of the second surfaces of the plurality of leads.4. The semiconductor package of wherein the at least one ...

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Номер записи: 71
05-01-2017 дата публикации

METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE HAVING A MULTI-LAYER ENCAPSULATED CONDUCTIVE SUBSTRATE AND STRUCTURE

Номер: US20170005029A1
Автор: Bang Won Bae, Chung Ji Young, Kim Byong Jin, Kim Gi Jeong
Принадлежит: AMKOR TECHNOLOGY, INC.

In one embodiment, a semiconductor package includes a multi-layer encapsulated conductive substrate having a fine pitch. The multi-layer encapsulated conductive substrate includes a conductive leads spaced apart from each other, a first encapsulant disposed between the leads, a first conductive layer electrically connected to the plurality of leads, conductive pillars disposed on the first conductive layer, a second encapsulant encapsulating the first conductive layer and the conductive pillars, and a second conductive layer electrically connected to the conductive pillars and exposed in the second encapsulant. A semiconductor die is electrically connected to the second patterned conductive layer. A third encapsulant covers at least the semiconductor die. 1. A semiconductor package comprising: a plurality of leads spaced apart from each other;', 'a first encapsulant disposed between the plurality of leads;', 'a first conductive layer electrically connected to the plurality of leads;', 'conductive pillars disposed on the first conductive layer;', 'a second encapsulant encapsulating the first conductive layer and the conductive pillars; and', 'a second conductive layer electrically connected to the conductive pillars and disposed adjacent the second encapsulant;, 'a multi-layer encapsulated conductive substrate comprisinga semiconductor die electrically coupled to the second conductive layer; anda third encapsulant encapsulating at least the semiconductor die.2. The semiconductor package of claim 1 , wherein a bottom surface of the first encapsulant protrudes to a bottom portion of the multi-layer encapsulated conductive substrate more than bottom surfaces of the plurality of leads.3. The semiconductor package of further comprising:solder structures attached to the bottom surfaces of the plurality of leads.4. The semiconductor package of claim 1 , wherein bottom surfaces of the plurality of leads protrude to a bottom portion of the multi-layer encapsulated conductive ...

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Номер записи: 72
05-01-2017 дата публикации

Flat No-Leads Package With Improved Contact Pins

Номер: US20170005030A1
Автор: Kenganantanon Ekgachai, Kitnarong Rangsun, Punyapor Prachit
Принадлежит: MICROCHIP TECHNOLOGY INCORPORATED

According to an embodiment of the present disclosure, a leadframe for an integrated circuit (IC) device may comprise a center support structure for mounting an IC chip, a plurality of pins extending from the center support structure, and a bar connecting the plurality of pins remote from the center support structure. Each pin of the plurality of pins may include a dimple. 19-. (canceled)10. A method for manufacturing an integrated circuit (IC) device in a flat no-leads package , the method comprising:mounting an IC chip onto a center support structure of a leadframe, the leadframe including:the center support structure;a plurality of pins extending from the center support structure; anda bar connecting the plurality of pins remote from the center support structure;wherein each pin of the plurality of pins includes a dimple;bonding the IC chip to at least some of the plurality of pins;encapsulating the leadframe and bonded IC chip creating an IC package; andcutting the IC package free from the bar by sawing through the encapsulated lead frame at a set of cutting lines intersecting the dimples of the plurality of pins, exposing an end face of each of the plurality of pins and leaving a portion of the dimples that extends from the bottom surface of the IC package to a side surface with the exposed end faces of the pins.11. A method according to claim 10 , further comprising:performing an isolation cut to isolate individual pins of the IC package without separating the IC package from the lead frame; andperforming a circuit test of the isolated individual pins after the isolation cut.12. A method according to claim 10 , further comprising bonding the IC chip to at least some of the plurality of pins using wire bonding.13. A method according to claim 10 , further comprising plating the exposed portion of the plurality of pins claim 10 , including the dimples claim 10 , on a bottom surface of the IC package before cutting the IC package free from the bar.14. A method for ...

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Номер записи: 73
05-01-2017 дата публикации

SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MOUNTING STRUCTURE

Номер: US20170005031A1
Автор: KIMURA Akihiro
Принадлежит:

A semiconductor device includes a plurality of die pad sections, a plurality of semiconductor chips, each of which is arranged in each of the die pad sections, a resin encapsulation portion having a recess portion for exposing at least a portion of the die pad sections, the resin encapsulation portion configured to cover the die pad sections and the semiconductor chips, and a heat radiation layer arranged in the recess portion. The heat radiation layer includes an elastic layer exposed toward a direction in which the recess portion is opened. The heat radiation layer directly faces at least a portion of the die pad sections. The elastic layer overlaps with at least a portion of the die pad sections when seen in a thickness direction of the heat radiation layer. 121-. (canceled)22. A semiconductor device manufacturing method , comprising:preparing a semiconductor chip, a heat radiation plate and a lead frame having a die pad section;joining the semiconductor chip to the die pad section;causing the heat radiation plate to directly face the die pad section; andforming an encapsulating resin portion that covers the semiconductor chip, the heat radiation plate and the die pad section,wherein the act of forming the encapsulating resin portion comprises joining the heat radiation plate and the die pad section by the encapsulating resin portion23. The method of claim 22 , wherein the die pad section has a die pad major surface and a die pad rear surface claim 22 , the act of joining the semiconductor chip comprises joining the semiconductor chip to the die pad major surface claim 22 , and causing the heat radiation plate to directly face the die pad section comprises causing the heat radiation plate to directly face the die pad rear surface.24. The method of claim 23 , wherein the heat radiation plate is exposed from the encapsulating resin portion in the act of forming the encapsulating resin portion.25. The method of claim 22 , further comprising preparing a first mold ...

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Номер записи: 74
07-01-2016 дата публикации

Exposed die clip bond power package

Номер: US20160005626A1
Автор: Emil Casey Israel, Leonardus Antonius Elisabeth van Gemert
Принадлежит: NXP BV

In an example embodiment, an integrated circuit (IC) comprises a device die having a top-side surface and an under-side surface, the top-side surface having bond pads connected to active circuit elements, the under-side surface having a conductive surface. A first set of lead frame clips having upper portions and lower portions, are solder-anchored, on the upper portions, to a first set of bond pads; the lower portions are flush with the conductive surface. Wires are bonded to an additional set of bond pads opposite the first set of bond pads and to lower lead frame portions of a second set of lead frame clips opposite the first set of lead frame clips; the lower lead frame portions of the second set of lead frame clips are flush with the conductive surface. The device is encapsulated in a molding compound leaving exposed the conductive surface and underside surfaces of the first and second sets of the lead frame portions.

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Номер записи: 75
07-01-2016 дата публикации

ELECTRONIC DEVICE COMPRISING AN IMPROVED LEAD FRAME

Номер: US20160005678A1
Автор: Magni Pierangelo, ROSSI Roberto
Принадлежит: STMICROELECTRONICS S.R.L.

An electronic device includes a chip and a support element which supports the chip. Leads are provided to be electrically coupled to at least one terminal of the chip. A coupling element is mounted to a free region of the support element that is not occupied by the chip. The coupling element includes a conductive portion electrically connected to at least one lead and to the at least one terminal of the chip to obtain an electrical coupling. 1. An electronic device , comprising:a chip of semiconductor material configured to implement functionalities of the electronic device,a support element for supporting the chip,a plurality of leads each one adapted to be electrically coupled to at least one terminal of the chip, anda coupling element on a free region of the support element that is not occupied by the chip, said coupling element comprising a conductive portion electrically connected to at least one lead and to the at least one terminal of the chip to obtain said electrical coupling.2. The electronic device according to claim 1 , wherein the conductive portion is electrically connected to the at least one lead by a wire connection between the at least one lead and a region of the conductive portion proximal to the at least one lead claim 1 , and wherein the conductive portion is electrically connected to the at least one terminal by a wire connection between the at least one terminal and a region of the conductive portion proximal to the at least one terminal.3. The electronic device according to claim 1 , further comprising an electronic component configured to be electrically coupled to the at least one lead claim 1 , said electronic component being mounted claim 1 , within the electronic device claim 1 , on the coupling element claim 1 , and being electrically connected claim 1 , within the electronic device claim 1 , to said at least one lead and to said at least one terminal of the chip.4. The electronic device according to claim 3 , wherein said conductive ...

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Номер записи: 76
07-01-2016 дата публикации

Matrix Lid Heatspreader for Flip Chip Package

Номер: US20160005682A1
Автор: Leal George R., Pham Tim V.
Принадлежит: Freescale Semiconductor, Inc.

A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array () designed for direct attachment to an array of integrated circuit die () by including a thermal interface adhesion layer () to each die () and encapsulating the attached heat spreader lid array () and array of integrated circuit die () with mold compound () except for planar upper lid surfaces of the heat spreader lids (). 110-. (canceled)11. A semiconductor package , comprising:a substrate having first and second surfaces;a die having first and second surfaces, where the first surface of the die is flip-chip bonded to the first surface of the substrate;a compressed, laterally expansive, thermally conductive interface layer formed to cover the second surface of the die; anda heat spreader lid comprising an exposed heat dissipation surface layer and a plurality of connection spars extending laterally from the heat dissipation surface layer, where the heat dissipation surface layer contacts the compressed, laterally expansive, thermally conductive interface layer and is positioned apart from the substrate to define an encapsulation molding region in which encapsulation mold compound material is located to permanently attach the substrate, die, and heat spreader lid.12. The semiconductor package of claim 11 , where the plurality of connection spars extend laterally to be co-planar with the exposed heat dissipation surface layer.13. The semiconductor package of claim 11 , where the plurality of connection spars extend laterally as downset connection spars that are not co-planar with the exposed heat dissipation surface layer.14. The semiconductor package of claim 11 , where the heat spreader lid is formed with a thermally conductive layer of copper claim 11 , nickel or an alloy thereof.15. The semiconductor package of claim 11 , where the exposed heat dissipation surface layer has a thermal contact surface that is at ...

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Номер записи: 77
05-01-2017 дата публикации

SEMICONDUCTOR PACKAGE HAVING AN ISOLATION WALL TO REDUCE ELECTROMAGNETIC COUPLING

Номер: US20170005621A1
Автор: Musa Sarmad K., Santos Fernando A., Shah Mahesh K., Szymanowski Margaret A.
Принадлежит:

A system and method for packaging a semiconductor device that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate on which a first circuit and a second circuit are formed proximate to each other. An isolation wall of electrically conductive material is located between the first circuit and the second circuit, the isolation wall being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. Several types of isolation walls are presented. 1. A semiconductor device comprising:a substrate with a surface;a first circuit on the substrate and comprising a plurality of electrical components, including a first transistor, and a first wire bond array electrically coupled between the first transistor and a first lead;a second circuit on the substrate and comprising a plurality of electrical components, including a second transistor, and a second wire bond array electrically coupled between the second transistor and a second lead; andan isolation wall formed of electrically conductive material and located between the first circuit and the second circuit in an air cavity above the surface of the substrate, the isolation wall formed of a body of material that is oriented perpendicular to the surface of the substrate and extending above a height of the first and second wire bond arrays, the isolation wall being configured to reduce electromagnetic coupling between the first circuit and the second circuit during an operation of at least one of the first circuit and the second circuit, wherein the isolation wall is formed by a section of a lead frame for the semiconductor device, and wherein the lead frame also includes the first lead and the second lead.2. The semiconductor device as recited in claim 1 , wherein the lead frame is formed by an electrically conductive sheet claim 1 , and the isolation wall is formed by a section of the lead frame that is ...

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Номер записи: 78
04-01-2018 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20180005923A1
Автор: OTSUBO Yoshitaka, Shimizu Yasutaka, TABATA Mituharu
Принадлежит: Mitsubishi Electric Corporation

A semiconductor device includes: a circuit pattern, at least one or more wires joined thereto, an electrode terminal joining thereto, and a semiconductor element. The electrode terminal includes a horizontally extending portion extending along a main surface and connected to the wire, and a bent portion at which an extending direction of the electrode terminal is changed relative to the horizontally extending portion. Each of the wires has joint portions at which each of the wires and the circuit pattern are joined to each other. In a plan view, the joint portions are located on an outside of a portion where each of the wires and the electrode terminal overlap each other. 1. A semiconductor device comprising:a circuit pattern formed on one main surface of an insulating substrate and at least partially having conductivity;at least one or more wires joined to the circuit pattern and having conductivity,an electrode terminal joined to the wires, thereby being electrically connected to the circuit pattern; anda semiconductor element joined to the circuit pattern,the electrode terminal including a horizontally extending portion extending along the one main surface and connected to the wires, and a bent portion at which an extending direction of the electrode terminal is changed relative to the horizontally extending portion,each of the wires having a joint portion at which each of the wires and the circuit pattern are joined to each other,in a plan view, the joint portion being located on an outside of a portion where each of the wires and the electrode terminal overlap each other.2. The semiconductor device according to claim 1 , wherein the joint portions are provided at two or more positions so as to be spaced apart from each other.3. The semiconductor device according to claim 1 , wherein the joint portion is arranged in a region on a side of the horizontally extending portion with respect to the bent portion in a direction connecting the horizontally extending ...

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Номер записи: 79
04-01-2018 дата публикации

Lead frame and method of producing a chip housing

Номер: US20180005924A1
Автор: Martin Brandl, Tobias Gebuhr
Принадлежит: OSRAM Opto Semiconductors GmbH

A lead frame used to produce a chip package includes a first lead frame section and a second lead frame section connected to one another by a bar, wherein the bar includes a first longitudinal section, a second longitudinal section and a third longitudinal section, the first longitudinal section adjoins the first lead frame section and the third longitudinal section adjoins the second lead frame section, the first longitudinal section and the third longitudinal section are oriented parallel to one another, the first longitudinal section and the second longitudinal section form an angle not equal to 180° and not equal to 90°, and the lead frame is planar.

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Номер записи: 80
04-01-2018 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20180005926A1
Автор: IWAI Yuji, MIYAWAKI Katsumi
Принадлежит: Mitsubishi Electric Corporation

A semiconductor device includes a lead frame comprising a first terminal and a second terminal for grounding, a sealing resin which covers the lead frame, an exposed part which is a part of the second terminal and is exposed from the sealing resin and a conductive material which covers the surface of the sealing resin and contacts the second terminal at the exposed part. 1. A semiconductor device comprising:a lead frame comprising a first terminal and a second terminal for grounding;a sealing resin which covers the lead frame;an exposed part which is a part of the second terminal and is exposed from the sealing resin; anda conductive material which covers the surface of the sealing resin and contacts the second terminal at the exposed part.2. The semiconductor device according to claim 1 ,wherein the first terminal and the second terminal are arranged at an end of the semiconductor device,the second terminal is higher than the first terminal at the end, andthe sealing resin comprises a thin wall part at the end, whose height is equal to that of the second terminal at the end.3. The semiconductor device according to claim 2 ,wherein the second terminal comprises:a third terminal which is comprised by the lead frame and has the same height as the first terminal; anda conductive piece which is disposed on the surface of the third terminal.4. The semiconductor device according to claim 2 ,wherein the lead frame comprises a die pad for mounting a semiconductor chip, andthe second terminal is electrically conducted with the die pad.5. The semiconductor device according to claim 2 ,wherein the exposed part and the thin wall part are formed so as to enclose the semiconductor chip, andthe conductive material covers the surfaces of the exposed part and the thin wall part which enclose the semiconductor chip.6. The semiconductor device according to claim 1 ,wherein the second terminal is higher than the first terminal,the second terminal is aligned with the sealing resin in ...

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Номер записи: 81
04-01-2018 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20180005981A1
Автор: Fujii Kenji, Haga Motoharu, Kasuya Yasumasa, KIMURA Akihiro, NAGAHARA Toichi, Yoshida Shingo
Принадлежит: ROHM CO., LTD.

A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film. 1. A semiconductor device comprising:an interlayer insulating film formed on a semiconductor substrate;an uppermost layer wiring made of copper and formed on the interlayer insulating film;a passivation film formed on the uppermost layer wiring and selectively exposing a top surface of the uppermost layer wiring as an electrode pad; anda bonding wire made of copper and bonded directly to the electrode pad.2. The semiconductor device according to claim 1 , wherein the bonding wire is stitch bonded directly to the electrode pad.3. The semiconductor device according to claim 1 , wherein the bonding wire is bonded to the electrode pad by a stud bump.4. The semiconductor device according to claim 1 , wherein a thickness of the electrode pad is no less than 10 μm.5. The semiconductor device according to claim 1 , wherein a thickness of the electrode pad is 10 μm to 15 μm.6. The semiconductor device according to claim 1 , further comprising a lower layer wiring covered with the interlayer insulating film claim 1 , whereinthe uppermost layer wiring includes a protrusion extending inside the interlayer insulating film,the lower layer wiring is electrically connected to the electrode pad via a pathway including the protrusion.7. The ...

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Номер записи: 82
07-01-2021 дата публикации

Lead frame assembly for a semiconductor device

Номер: US20210005538A1
Автор: Adam Richard Brown, Dave Anderson, Ricardo Lagmay Yandoc
Принадлежит: Nexperia BV

This disclosure relates to a lead frame assembly for a semiconductor device, a semiconductor device and an associated method of manufacture. The lead frame assembly includes a die attach structure and a clip frame structure. The clip frame structure includes a die connection portion configured to contact a contact terminal on a top side of the semiconductor die; and a continuous lead portion extending along the die connection portion. The continuous lead portion is integrally formed with the die connection portion.

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Номер записи: 83
07-01-2021 дата публикации

SEMICONDUCTOR DEVICE WITH GALVANICALLY ISOLATED SEMICONDUCTOR CHIPS

Номер: US20210005539A1
Автор: Schaller Rainer Markus
Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device includes a chip carrier, a first semiconductor chip arranged on the chip carrier, the first semiconductor chip being located in a first electrical potential domain when the semiconductor device is operated, a second semiconductor chip arranged on the chip carrier, the second semiconductor chip being located in a second electrical potential domain different from the first electrical potential domain when the semiconductor device is operated, and an electrically insulating structure arranged between the first semiconductor chip and the second semiconductor chip, which is designed to galvanically isolate the first semiconductor chip and the second semiconductor chip from each other. 1. A semiconductor device , comprising:a chip carrier;a first semiconductor chip arranged on the chip carrier, the first semiconductor chip being located in a first electrical potential domain during operation of the semiconductor device;a second semiconductor chip arranged on the chip carrier, the second semiconductor chip being located in a second electrical potential domain different from the first electrical potential domain when the semiconductor device is operated; andan electrically insulating structure arranged between the first semiconductor chip and the second semiconductor chip, which is configured to galvanically isolate the first semiconductor chip and the second semiconductor chip from each other.2. The semiconductor device as claimed in claim 1 , wherein the electrically insulating structure is free of alkaline-earth components.3. The semiconductor device as claimed in claim 1 , wherein the electrically insulating structure is free of plasticizers and solvents.4. The semiconductor device as claimed in claim 1 , wherein:the first electrical potential domain corresponds to a first ground potential, the first semiconductor chip being connected to the first ground potential, andthe second electrical potential domain corresponds to a second ground potential ...

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Номер записи: 84
07-01-2021 дата публикации

Method of making leadframe strip

Номер: US20210005540A1
Автор: Anis Fauzi Bin Abdul Aziz, Lee Han Meng@Eugene Lee, Wei Fen Sueann LIM
Принадлежит: Texas Instruments Inc

A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad and first and second dam bars located adjacent to opposite first and second sides of the die attach pad, respectively. A plurality of continuous lead structures extend, uninterrupted by other structure, between opposing ones of the dam bars of horizontally adjacent leadframes. The plurality of integrally connected leadframes are arranged in a plurality of vertical columns, wherein die attach pads in one vertical column are vertically offset from die attach pads in adjacent vertical columns.

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Номер записи: 85
07-01-2021 дата публикации

Lead frames including lead posts in different planes

Номер: US20210005541A1
Автор: Jo Ean Joanna Chye, Lee Shuang Wang, Thai Kee Gan
Принадлежит: INFINEON TECHNOLOGIES AG

A lead frame includes a die pad having a surface, a first lead post, a first lead, a second lead post, and a second lead. The first lead post has a surface coplanar with the surface of the die pad and is in a first plane. The first lead is coupled to the first lead post. The second lead post is in a second plane different from the first plane. The second lead is coupled to the second lead post.

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Номер записи: 86
07-01-2021 дата публикации

GANG CLIP

Номер: US20210005569A1
Автор: Quijano Lorraine Duldulao, Quijano Michael Kirby Chua
Принадлежит:

An integrated circuit (IC) package includes a lead frame and a first die attached to the lead frame. The IC package also includes a first clip attached to first die and the lead frame. The IC package further includes a second die attached to first clip and the lead frame. The IC package still further includes a second clip with a clip foot adhered to the lead frame on a first side of the second clip, the second clip extending to and contacting a side of the second die via a layer of solder paste. The second clip includes a sawn or lased edge at a second side of the second clip opposing the first side of the second clip. 1. An integrated circuit (IC) package comprising:a lead frame;a first die adhered to the lead frame on a first side of the first die;a first clip having a clip foot adhered to the lead frame, the first clip extending from the lead frame and contacting a second side of the first die on a first side of the first clip via a first layer of solder paste wherein the second side of the first die opposes the first side of the first die;a second die with a first side adhered to a second side of the first clip via a second layer of solder paste, wherein the second side of the first clip opposes the first side of the first clip; anda second clip having a clip foot adhered to the lead frame on a first side of the second clip, the second clip extending from the lead frame to a second side of the second die via a third layer of solder paste, the second side of the second die opposing the first side of the second die, wherein the second clip has an sawn or lased edge on a second side of the second clip, wherein the second side of the second clip opposes the first side of the second clip.2. The IC package of claim 1 , wherein the sawn or lased edge is parallel to an edge of the lead frame.3. The IC package of claim 1 , wherein the second clip comprises a high side that includes the sawn or lased edge claim 1 , and wherein a surface of the high side that is ...

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Номер записи: 87
02-01-2020 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20200006206A1
Автор: Toyokazu Shibata
Принадлежит: Toshiba Corp

According to embodiments, there is a semiconductor device comprising: a first die pad; a first inner lead arranged inside a molded resin; a second die pad; and a second inner lead arranged inside the resin, wherein a part of the first inner lead and a part of the second inner lead are adhered and electrically connected to each other, a first semiconductor chip mounted on the first die pad is electrically connected to a second semiconductor chip mounted on the second die pad via the first inner lead and the second inner lead, and an end face of one end of the first inner lead and the second inner lead that are adhered to each other is exposed to a side surface of the resin.

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Номер записи: 88
02-01-2020 дата публикации

Molded Semiconductor Package

Номер: US20200006267A1
Автор: Aileen Manantan Soriano, Fong Mei Lum, Hock Heng Chong, Mei Chin Ng, MUHAMMAD Muhammat Sanusi, Soon Lock Goh, Swee Kah Lee
Принадлежит: INFINEON TECHNOLOGIES AG

A molded semiconductor package includes a mold compound having opposing first and second main surfaces and an edge extending between the first and second main surfaces. A semiconductor die is embedded in the mold compound. A plurality of metal pads embedded in the mold compound are electrically connected to the semiconductor die. The metal pads have a bottom face which is uncovered by the mold compound at the second main surface of the mold compound. The metal pads disposed around a periphery of the molded package have a side face which is uncovered by the mold compound at the edge of the mold compound. The faces of the metal pads uncovered by the mold compound are plated. The side face of each metal pad disposed around the periphery of the molded package is recessed inward from the edge of the mold compound. A corresponding manufacturing method is also described.

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Номер записи: 89
04-01-2018 дата публикации

METHOD OF MANUFACTURING A CIRCUIT DEVICE

Номер: US20180006578A1
Автор: HORIUCHI Fumio, INAGAKI Yuhki, KUDO Kiyoaki, MASHIMO Shigeaki, SAKURAI Akira
Принадлежит: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

In one form, a method of manufacturing a circuit device comprises providing a lead frame comprising a plurality of leads, each comprising an island portion, a bonding portion elevated from the island portion, a slope portion extending obliquely so as to connect the island portion and the bonding portion, and a lead portion extending from the bonding portion. First and second transistors and first and second diodes are mounted upper surfaces of island portions of respective first and second leads, and are connected to the respective leads through wirings that connect the transistors and diodes to the bonding portions of the respective leads. Lower surfaces of the island portions are attached to an upper surface of a circuit board, and the circuit board, the transistors, the diodes, and the lead frame are encapsulated by a resin, so that the lead portions are not covered by the resin. 1. A method of manufacturing a circuit device , comprising:providing a lead frame comprising a plurality of leads, each comprising an island portion, a bonding portion elevated from the island portion, a slope portion extending obliquely so as to connect the island portion and the bonding portion, and a lead portion extending from the bonding portion;mounting a first transistor and a first diode of a first phase on an upper surface of the island portion of a first lead;connecting the first transistor and the first diode of the first phase to a bonding portion of a second lead by a first wiring;mounting a second transistor and a second diode of the first phase on the upper surface of the island portion of a third lead;connecting the second transistor and the second diode of the first phase to a bonding portion of the second lead by a second wiring;attaching lower surfaces of the island portion of each of the plurality of leads to an upper surface of a circuit board; andencapsulating by a resin the circuit board, the first and second transistors, the first and second diodes and the lead ...

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Номер записи: 90
02-01-2020 дата публикации

3D-Stacked Module with Unlimited Scalable Memory Architecture for Very High Bandwidth and Very High Capacity Data Processing Devices

Номер: US20200006367A1
Автор: He Samba, Krutzik Christian, Yamaguchi James
Принадлежит: Irvine Sensors Corporation

A 3-D memory module comprising a plurality of packaged integrated memory circuits or devices is mounted to a substrate with integrated pins that are edge-connected on two surfaces where the top surface provides an edge connection from the integrated memory circuits to an orthogonally-mounted memory controller circuit through a wide-word interface. Each integrated memory device can be accessed independently wherein the memory controller is configured to reduce the wide-word interface to a serial interface which is brought to the opposite surface of the memory module for electrical coupling to an external system or printed circuit assembly. 1. A device comprising a plurality of packaged memory integrated circuits mounted to a substrate with integrated pins that are edge connected on two surfaces where the top surface provides an edge connection from the integrated circuits to an orthogonally mounted memory controller through a wide-word interface and configured where each integrated circuit can be accessed independently and wherein the memory controller reduces the wide-word interface to a serial interface which is routed to an opposite face for attachment to a system substrate.2. A method of producing the device of wherein the package substrate uses a lead frame that is soldered or welded to the substrate and each finger of the lead frame is used for aligning the layers to the required pitch to mount the controller as well as providing a means for compliance and flexibility in achieving said pitch.3. A method using the lead frame of wherein after the plurality of packages are stacked and the lead frame fingers are bent in a J-lead fashion to provide a planar surface for mounting the controller circuit.4. A method of communication between cubes using the faces of the module in any direction independently to allow bypassing of routing signals out of the overall physical memory and back in.5. A method of using the enclosure to help channel communication via waveguide ( ...

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Номер записи: 91
03-01-2019 дата публикации

Method for Producing Electronic Device With Multi-Layer Contact

Номер: US20190006311A1
Автор: EICHINGER Oliver, Goh Kok Chai, HEINRICH Alexander, Juerss Michael, Roesl Konrad, SCHMIDT TOBIAS
Принадлежит:

A method for producing an electric device with a multi-layer contact is disclosed. In an embodiment, a method includes providing a carrier, the carrier having a metallic layer disposed on its surface, providing a semiconductor substrate, forming a layer stack on the semiconductor substrate and attaching the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer. 1. A method for fabricating an electronic device , the method comprising:providing a carrier, the carrier having a metallic layer disposed on its surface, wherein the metallic layer comprises Ni or NiNiP;providing a semiconductor substrate; directly depositing an electrical contact layer on the semiconductor substrate, the electrical contact layer being a single elemental Al layer;', 'directly depositing a functional layer on the electrical contact layer, the functional layer comprising Ti or an alloy containing Ti;', 'directly depositing an adhesion layer on the functional layer, the adhesion layer comprising Ni or NiV;', 'directly depositing a solder layer on the adhesion layer, the solder layer being a single element Sn layer or a noble metal free alloy layer containing Sn; and', 'directly depositing a protective layer on the solder layer, the protection layer being an Ag layer; and, 'forming a layer stack on the semiconductor substrate bybonding the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer, the intermetallic phase comprising a binary alloy of Ni/Sn.2. The method according to claim 1 , wherein the electrical contact layer has a thickness in a range from 100 nm to 1 μm.3.The method according to claim 2 , wherein the functional layer has a thickness in a range from 50 nm to 200 nm.4382. The method according to claim claim 2 , wherein the solder layer has a thickness in ...

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Номер записи: 92
04-01-2018 дата публикации

SEMICONDUCTOR DEVICE AND MEASUREMENT DEVICE

Номер: US20180006604A1
Автор: SONE Toshihisa, TAKEI Akihiro, TAKEMASA Kengo, YAMADA Kazuya, Yoshida Yuichi
Принадлежит: LAPIS SEMICONDUCTOR CO., LTD.

A semiconductor device includes an electronic component that includes an oscillator and has terminals on one face. A semiconductor chip is electrically connected to the electronic component and also includes terminals on one face thereof. The electronic component and the semiconductor chip are mounted to a mounting base such that the terminals of the electronic component and the terminals of the semiconductor chip face in the same direction. First bonding wires are connected to the terminals of the semiconductor chip, and second bonding wires having an apex height smaller than that of the first bonding wires connect the terminals of the electronic component to the terminals of the semiconductor chip. A sealing member completely seals within at least the electronic component. 1. A semiconductor device , comprising:an electronic component that comprises an oscillator and comprises a plurality of terminals on one face;a semiconductor chip that is electrically connected to the electronic component and comprises a plurality of terminals on one face;a mounting base including a mounting section to which the electronic component and the semiconductor chip are each directly mounted on one face of the mounting base, such that the plurality of terminals of the electronic component and the plurality of terminals of the semiconductor chip face in a same direction, and a plurality of leads formed at a periphery of the mounting section, each of the plurality of leads including a mounting base terminal;first bonding wires that connect at least two of the plurality of terminals of the semiconductor chip to the mounting base terminals;second bonding wires that directly connect at least two of the plurality of terminals of the electronic component to the plurality of terminals of the semiconductor chip, and that have an apex height that is smaller than that of the first bonding wires;a third bonding wire that connects the mounting section to one of the mounting base terminals; anda ...

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Номер записи: 93
07-01-2021 дата публикации

MAGNETICALLY COUPLED GALVANICALLY ISOLATED COMMUNICATION USING LEAD FRAME

Номер: US20210006167A1
Автор: Balakrishnan Balu, Matthews David Michael Hugh
Принадлежит: POWER INTEGRATIONS, INC.

An integrated circuit package includes a lead frame and an encapsulation that substantially encloses the lead frame. The lead frame further includes a first conductor comprising a first conductive loop and a second conductor galvanically isolated from the first conductor, proximate to and magnetically coupled to the first conductive loop to provide a communication link between the first and second conductor. The second conductor includes a first conductive portion, a second conductive portion, and a wire coupling together the first conductive portion and the second conductive portion. 1. An integrated circuit package , comprising:an encapsulation; and a first conductive loop disposed substantially within the encapsulation;', 'a second conductive loop disposed substantially within the encapsulation and substantially all of the second conductive loop is outside of the first conductive loop; and', 'wherein the first and second conductive loops are configured to form a magnetically coupled communication link.', 'a galvanic isolator coupled to the first conductive loop such that there is galvanic isolation between the first and the second conductive loops,'}], 'a lead frame, a portion of the lead frame disposed within the encapsulation, the lead frame comprising2. The integrated circuit package of claim 1 , further comprising:a first circuit coupled to the first conductive loop; and wherein one of the first and second circuits is configured to control properties of a transmitter current to produce a changing magnetic field in proximity to a corresponding one of the first and second conductive loops, thereby inducing a voltage that is generated across an other one of the first and second conductive loops that is subjected to the changing magnetic field and results in a current flow in the other one of the inner and outer conductive loops, and', 'wherein the other one of the first and second circuits is configured to receive an electrical parameter induced by the one of ...

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Номер записи: 94
03-01-2019 дата публикации

Heterojunction Semiconductor Device for Reducing Parasitic Capacitance

Номер: US20190006504A1
Автор: Chen Shih-Peng, LIAO Wen-Chia, Lin Li-Fan, Shiue Ching-Chuan, YANG Chun-Chieh
Принадлежит:

A semiconductor device including an active layer made of III-V group semiconductors, a source electrode and a drain electrode disposed on the active layer, a gate electrode disposed on or above the active layer and between the source electrode and the drain electrode, an interlayer dielectric covering the source electrode, the drain electrode, and the gate electrode and having a plurality of inter-gate via holes. The semiconductor device further includes an inter-source layer, an inter-drain layer, and an inter-gate layer disposed on the interlayer dielectric. The semiconductor device further includes an inter-gate plug filled in the inter-gate via hole and electrically connected to the gate electrode and the inter-gate layer, and a gate field plate being separated from the gate electrode and electrically connected to the gate electrode through the inter-gate layer. 1. A semiconductor device , comprising:an active layer made of III-V group semiconductor materials;a source electrode disposed on the active layer;a drain electrode disposed on the active layer;a gate electrode disposed above the active layer and between the source electrode and the drain electrode;a gate field plate disposed above the active layer;an interlayer dielectric covering the source electrode, the drain electrode, the gate field plate, and the gate electrode, the interlayer dielectric having a plurality of inter-gate via holes;an inter-source layer disposed on the interlayer dielectric and electrically connected to the source electrode;an inter-drain layer disposed on the interlayer dielectric and electrically connected to the drain electrode;an inter-gate layer disposed on the interlayer dielectric, wherein the gate field plate is separated from the gate electrode and electrically connected to the gate electrode through the inter-gate layer; anda plurality of inter-gate plugs filled into the inter-gate via holes;wherein at least one of the inter-gate via holes positioned on the gate field ...

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Номер записи: 95
08-01-2015 дата публикации

Semiconductor device

Номер: US20150008568A1
Автор: Hiroyuki Fujita, Keiichiro Hayashi, Koji Tsukagoshi, Masaru Akino, Sadao Oku
Принадлежит: Seiko Instruments Inc

Provided is a semiconductor device including a package having a hollow portion, which can meet the need of reduction in size and thickness. The semiconductor device includes: a resin molded member ( 1 ) including a hollow portion ( 10 ) having an inner bottom surface on which a semiconductor chip ( 6 ) is mounted, a surrounding portion ( 1 b ) that surrounds the hollow portion ( 10 ), and a bottom surface portion ( 1 a ); an inner lead ( 2 e, 2 f ); and an outer lead ( 2 a, 2 b ) exposed from the resin molded member ( 1 ). The inner lead buried in the molded member ( 1 ) includes an L-shaped lead extending portion having a through hole formed therethrough.

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Номер записи: 96
08-01-2015 дата публикации

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Номер: US20150008569A1
Автор: Kaneda Yoshiharu, Taniguchi Naoko
Принадлежит:

A semiconductor device includes a die pad, which includes an upper surface and a lower surface, the upper surface forming a rectangular shape in plan view; a plurality of support pins that support the die pad; a plurality of inner leads arranged around the die pad; a plurality of outer leads connected to each of the inner leads; a semiconductor chip which includes a main surface and a back surface and in which a plurality of electrode pads is formed in the main surface; a plurality of wires which electrically couple the electrode pads of the semiconductor chip to the inner leads respectively; and a sealing body that seals the support pins, the inner leads, the semiconductor chip, and the wires. A first support pin of the plurality of support pins is integrally formed together with the die pad. The first support pin is terminated inside the sealing body. 1. A semiconductor device comprising:a die pad, which includes an upper surface and a lower surface opposite to the upper surface, the upper surface forming a rectangular shape in plan view;a plurality of support pins that support the die pad;a plurality of inner leads arranged around the die pad;a plurality of outer leads connected to each of the inner leads;a semiconductor chip which includes a main surface and a back surface opposite to the main surface and in which a plurality of electrode pads is formed in the main surface, the semiconductor chip being mounted over the die pad so that the back surface faces the upper surface of the die pad;a plurality of wires which electrically couple the electrode pads of the semiconductor chip to the inner leads respectively; anda sealing body that seals the support pins, the inner leads, the semiconductor chip, and the wires,wherein a first support pin of the plurality of support pins is integrally formed together with the die pad,wherein the first support pin is terminated inside the sealing body.2. The semiconductor device according to claim 1 ,wherein a tip of the first ...

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Номер записи: 97
27-01-2022 дата публикации

Semiconductor module

Номер: US20220028761A1
Автор: Takafumi Yamada, Toru Yamada
Принадлежит: Fuji Electric Co Ltd

A semiconductor module includes a semiconductor device having a gate runner extending in a first direction at an upper surface of the semiconductor device, and a metal wiring plate having a first bonding portion with a bonding surface to which the upper surface of the semiconductor device is bonded via a first bonding material. The first bonding portion has a plurality of first protrusions at the bonding surface. Each first protrusion protrudes toward the semiconductor device, and is provided in a position away from the gate runner by a first distance in a plan view of the semiconductor module.

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Номер записи: 98
27-01-2022 дата публикации

SURFACE MOUNT PACKAGE FOR A SEMICONDUCTOR DEVICE

Номер: US20220028767A1
Автор: Amaro Michael Gerald, Anjum Naweed, KULKARNI MAKARAND RAMKRISHNA
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

A lead for a surface mount package for a semiconductor device, and the surface mount package employing the same. In one example, the lead includes a central segment with a first side and a second side, a first extension from a portion of the first side, and a second extension from a portion of the second side. The lead also includes a recess extending through a portion of the central segment, the first extension and the second extension. 1. A lead of a semiconductor package , comprising:a central segment having a first side and a second side;a first extension from a portion of the first side;a second extension from a portion of the second side; anda recess extending through a portion of the central segment, the first extension and the second extension.2. The lead as recited in claim 1 , wherein the first extension intersects a junction between the central segment and the recess on the first side of the central segment.3. The lead as recited in claim 1 , wherein the central segment has a thickness greater than a thickness of the first extension and the second extension.4. The lead as recited in claim 1 , wherein a thickness of the first extension is substantially equal to a thickness of the second extension.5. The lead as recited in claim 1 , wherein the recess comprises a concave shape.6. The lead as recited in claim 1 , wherein the recess comprises a step shape.7. The lead as recited in claim 1 , wherein the first extension of the lead includes an angular edge opposite the recess.8. A package claim 1 , comprising:a semiconductor die attached to a die attach pad; and a central segment having a first side and a second side;', 'a first extension from a portion of the first side;', 'a second extension from a portion of the second side; and', 'a recess extending through a portion of the central segment, the first extension and the second extension of the lead, a portion of the lead being exposed from a molding compound covering the semiconductor die., 'a lead coupled to ...

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Номер записи: 99
27-01-2022 дата публикации

Multi-chip package structure

Номер: US20220028831A1
Автор: Po-Chuan Lin
Принадлежит: Egalax Empia Technology Inc

A multi-chip package structure includes outer leads, a first chip and a second chip. The outer leads are disposed on four sides of a chip bonding area of a package carrier thereof, respectively. The first chip is fixed on the chip bonding area and includes a core and a seal ring. Input/output units, and first bonding pads are disposed, in an outward order, on the sides of the core. Each first bonding pad is electrically connected to a corresponding outer lead through a first wire. Dummy pads are disposed between the input/output units and the at least one side of the core. The second chip is stacked on the core and includes second bonding pads connected to the corresponding outer leads through second wires and dummy pads, so as to prevent from short circuit caused by soldering overlap and contact between the wires.

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Номер записи: 100