Verfahren und Vorrichtung zum Reduzieren des Effekts dielektrischer Absorption in einem SAR-ADC

Es wird ein Analog/Digital-Wandler mit sukzessivem Annäherungsregister (SAR-ADC) geschaffen, in dem der Einfluss dielektrischer Absorption mit einer Korrekturschaltung reduziert ist, die dafür ausgebildet ist, ein derzeitiges digitales Codewertsignal basierend wenigstens teilweise auf einem früheren digitalen Codewertsignal, einer Erfassungszeit und der Temperatur anzupassen.

KURVENGENERATOR

Analog-to-digital conversion

SEMICONDUCTOR STORAGE DEVIC3

... 1407152 Integrated circuits NIPPON GAKKI SEIZO KK 31 July 1972 [31 July 1971 (2) 1 Sept 1971 22 Nov 1971 (3)] Divided out of 1406691 Heading H1K [Also in Division H3] The storage medium of an integrated semiconductor analogue store consists of a diffused resistive track with a plurality of tapping points, representing analogue values, which are selectively connected to an output terminal via switches operated in response to signals from read-out circuitry. The switches may be bipolar transistors or JUGFETs but as described are IGFETs the drains of which are constituted by side branches from the track and the sources of which are interconnected by a diffused strip. The gates may be connected to the terminals of read-out circuitry via a matrix of diffused tracks and deposited aluminium strips interconnected at selected intersections in accordance with fixed information to be stored. A suitable MOS circuit producing read out pulses at its terminals in a predetermined order in response to a ...

Improvements in and relating to systems for translating analog values into numericalvalues

... 921,880. Analogue-to-digital converters. VYZUMNY USTAV OBRABECICH STROJU A OBRABENI PRAHA. Nov. 1, 1960 [Nov. 2, 1959], No. 37580/60. Class 40 (1). The angular position of a system of shafts coupled together through 10:1 1 reduction gearing is converted into digital form by selecting one out of a group of ten leads provided for each shaft, by means of movable contacts which co-operate with ten fixed contacts. Two movable contacts are provided for each shaft except the least significant, one or the other of these contacts, which are spaced apart by half a digit division, being selected in accordance with the position of the preceding shaft by means of diode gates 011-411 and 511-911, Fig. 4, in order to prevent errors when a transition 0-9 or 9-0 takes place. Contacts 0-9 are respectively connected to indicator lamps 01-91 and, for example, to a machinetool control system operated in accordance with instructions set by a record card or ...

Analog-to-digital conversion

PROCEDURE AND DEVICE FOR THE DETERMINATION AND USE OF THE SAMPLING RATE FOR THE DECODING OF WATER-MARK INFORMATION, WHICH IN A RECEIVED SIGNAL WAS EMBEDDED AND WITH AN ORIGINAL SAMPLING RATE ON THE CODING SIDE

Anordnung zur Abtastung eines kodierten Rastermassstabes

Anordnung zum Verwandeln der Winkellagen von Wellen in eine numerische Form sowie zum Steuern dieser Wellen

Schaltungsanordnung zur Integration einer sich in Abhängigkeit von der Zeit oder einer Zeitfunktion aperiodisch ändernden Grösse

Generatore di corrente comandato da un segnale binario per l'erogazione su un carico di una corrente intermittente

Analog-Digitalwandler

Dispositif d'indication de la position d'un point par rapport à au moins une coordonnée

Codiervorrichtung für Drehwinkel

Digitales Messsystem für Drehbewegungen

Verfahren und Anordnung zur Synchronisation des Ziffernsprungs bei digitalen Absolut-Messystemen

Digital voltmeter

Bipolar summation cct. with unipolar output - provides polarity information using delay chain and trigger feed to linear output gates

scale of coding to binary decimal code

Improvement with the analogical-digital converters

A DEVICE FOR MEASURING THE AZIMUTH ANGLE OF INCIDENCE OF A BEAM OF LIGHT

Numerical system of measurement for rotation movements

Coder of posting and visualization.

Rapid, accurate A=D converter - has error correction circuit using code differences to correct code by successive approximations

The analogue-digital converter has a conversion circuit which compares an analogue voltage with a displayed code. The code being represented by the elements of a register (5). The analogue voltage being applied to the second input of a comparator (3). The analogue voltage supplied to the comparator (3) second input is also applied to an input of a multiplexor circuit (1). The multiplexor (1) input is selected once in two times under the control of a logic circuit. The converter has an error correction arithmetic circuit (8) which supplies under the control of the logic circuit (4), a corrected code from the displayed codes obtained at the registers (5) output. This corrected code is provided firstly when whatever input of the multiplexor input (1) circuit has been selected. Then when the input connected to the output of the conversion circuit has been selected. The error correction arithmetic circuit corrects the first code using the difference between the first and second codes obtained.

Rapid, accurate A=D converter - has error correction circuit using code differences to correct code by successive approximations

Transducers of precision

Cyclic Digital to Analog Converter as pipeline architecture

Successive Approximation Register Analog-to-Digital Converter and associated control method

A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) is disclosed. The SAR ADC includes a switched capacitor array, a buffer, a comparator and a control logic circuit. The switched capacitor array is arranged to sample an input signal according to a switch control signal to generate a sampling signal. The buffer is arranged to generate a common mode voltage. The comparator is arranged to receive the sampling signal and the common mode voltage in order to generate a comparison result. The control logic circuit is arranged to generate an output signal according to the comparison result, and generate the switch control signal to control the switched capacitor array. The control logic circuit further generates an operation control signal to adjust a Miller compensation capacitor inside the buffer. An associated control method is also disclosed.

СПОСОБ И УСТРОЙСТВО ДЛЯ ОПРЕДЕЛЕНИЯ И ИСПОЛЬЗОВАНИЯ ЧАСТОТЫ ДИСКРЕТИЗАЦИИ ДЛЯ ДЕКОДИРОВАНИЯ ИНФОРМАЦИИ ВОДЯНОГО ЗНАКА, ВСТРОЕННОЙ В ПРИНИМАЕМЫЙ СИГНАЛ, ВЫБРАННЫЙ С ПОМОЩЬЮ ИСХОДНОЙ ЧАСТОТЫ ДИСКРЕТИЗАЦИИ НА СТОРОНЕ КОДЕРА

1. Способ определения и использования частоты (ASFR) дискретизации для декодирования (WMDF) информации (INFB) водяного знака (ВЗ), встроенный в принимаемый сигнал (RWAS), дискретизированный с исходной частотой дискретизации на стороне кодера, причем упомянутое декодирование включает в себя корреляцию (CORR) с по меньшей мере одним эталонным образцом (REFP), причем способ, отличающийся тем, что содержит этапы, на которых: ! в режиме поиска: ! для последовательных частей или кадров упомянутого принятого сигнала (RWAS) многократно сканируют (RCTRLU) возможные частоты дискретизации в диапазоне частот (LSFR, HSFR), включающем в себя упомянутую исходную частоту дискретизации, таким образом декодируя ВЗ (WMDF), с использованием этих возможных частот (ASFR) дискретизации, соответствующей части или кадра упомянутого принятого сигнала, ! причем для каждой возможной частоты дискретизации, использованной при декодировании ВЗ, определяют соответствующее битовое значение (CONF) достоверности ВЗ, полученное из упомянутой корреляции (CORR), и суммируют или комбинируют (RCTRLU) значения достоверности для каждой из возможных частот дискретизации, ! и причем, как только значение достоверности текущей возможной частоты дискретизации оказывается большим или равным первому пороговому значению (MPAR), выходят из режима поиска и переходят в нормальный режим с этой выбранной возможной частотой дискретизации; ! определяют (RCTRLU) максимум и второй максимум среди суммарных значений достоверности, причем, как только их отношение или разность оказывается больше второго порогового значения (MPAR), или когда достигается максимальное число (MPAR) циклов сканирования, выходят из уп� РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) 2009 102 228 (13) A (51) МПК G10L 19/00 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ, ПАТЕНТАМ И ТОВАРНЫМ ЗНАКАМ (12) ЗАЯВКА НА ИЗОБРЕТЕНИЕ (21), (22) Заявка: 2009102228/08, 23.01.2009 (71) Заявитель(и): ТОМСОН ЛАЙСЕНСИНГ (FR) (30) Конвенционный приоритет: 24.01.2008 ...

Improvements in or relating to displacement displaying systems

... 969,035. Electric selective signalling. LABORATOIRES DE PHYSIQUE APPLIQUEE. July 28,1961 [July 29,19601,No.27431/61. Heading G4H. An analogue-to-digital conversion system comprises means for obtaining a decimal representation of the position of a member and uses a plurality of switches having, respectively, 10, 102, 103,... 10n contacts, the wiper arms of all the switches being driven at the same speed by the member. In the Figure, shaft 1 moves wipers 5, 6, and 7, 8 and 9 at the same speed over banks of contacts Gu, Gd and Gc. Gc comprises ten contacts, GD one hundred contacts and Gu one thousand. Sets Vc, Vd, Vu of ten lamps each are associated with each bank of contacts and indicate the position of the shaft. Banks Gu and Gd are arranged so that each set of ten contacts joined to the lamps Vu and Vd isthe mirror image of the adjacent sets-this simplifies the printed wiring lay-out- and two wipers contact each bank. Only one wiper of each pair is in circuit ...

Binary scale reader

... 966, 974. Binary scale readers. CLEVITE CORPORATION. Nov. 1, 1960, No. 37491/60. Heading G4H. A reader for a natural binary coded scale comprises a plate 21, Fig. 2 divided into strips which correspond in number and location to the tracks of the scale to be read, each strip having an ordered series of reader areas of two distinct types e.g. transparent and opaque, the areas of one type 21A2-21A5 and 21B2-21B5 for the more significant tracks being symmetrically disposed about a centre line CL and occurring in the same cyclic sequence as the corresponding areas on the scale, whereas the areas 21A1 and 21B1 for the least significant track, although occurring in the same cyclic sequence as the corresponding areas on the scale, may be assymmetrically disposed about the centre line. The plate 21 co-operates with two sets of photo-cells illuminated by light transmitted through the scale and the respective portions A, B of plate 21. In Fig. 11 plate 21 is shown superimposed upon the scale with ...

Improvements in or relating to pulse code modulation systems

... 957,503. Pulse code modulation systems. BRITISH TELECOMMUNICATIONS RESEARCH Ltd. Nov. 14, 1960 [Nov. 13, 1959], No. 38629/59. Heading H4L. In a pulse code modulation system logic circuits are employed for giving an amplitude compression effect in conjunction with an encoder including a comparator. The system described involves ten binary digits plus a sign digit which are converted into a code of six binary digits plus a sign digit. The arrangement is as follows. Starting from the most significant digit the number of consecutive 0's up to the 6th place is counted and this number translated into a 3-digit binary code. If the number of 0's does not exceed 6 the next digit necessarily a 1, is not transmitted and the next three digits are transmitted unchanged, any remainder being neglected. If the number of initial 0's is 7 or more the number 7 is transmitted corresponding to the first 7 0's and the remaining three digits are transmitted unchanged. At the receiver the process is reversed and ...

A DEVICE FOR MEASURING THE AZIMUTH ANGLE OF INCIDENCE OF A BEAM OF LIGHT

... 1,205,345. Measuring the angle of incidence of a light beam. ERNST LEITZ G.m.b.H. July 25, 1968 [Aug.3, 1967; March 7, 1968], No.35645/68. Heading G1A. A device for measuring in one of two rectangular co-ordinates the azimuth angle of incidence of an almost parallel light beam comprises two reflecting surfaces facing towards and substantially parallel to each other so as to define a compartment through which the incident beam may be passed to be measured photo-electrically irrespective of variation in its angle of incidence in the direction normal to the parallel reflecting surfaces and the angle it is desired to measure. Light may be introduced by a convex lens 3, Fig. 1b, to a compartment comprising a block of glass, quartz, or plastics material, and the co-ordinate X to a point L on the back of the block may be measured photo-electrically by for example an arrangement which includes an electro-magnetically vibrated wire between the spot and the photo-cell. The position of the spot may ...

Apparatus for calculating the integrals of time-dependent functions

... 1,110,070. Integrating apparatus. H. LIST. 9 Nov., 1965 [13 Nov., 1964], No. 47362/65. Heading G4G and G4H. In apparatus for integrating a variable y with respect to a second variable x, a generator 1 (Fig. 1), supplies a sawtooth waveform the width of which is determined by the variable x = f(t) to a voltage comparator 8 for comparison with the variable y = f(x). The output from the comparator which is a series of pulsewidth-modulated signals is applied to an AND gate 12 to which are fed clock pulses 11 and a pulse of a width representing the limits of integration. In one embodiment the train of pulses from the AND gate 12 are fed to a counter 15. In a second embodiment (Fig. 3, not shown) the pulses charge a capacitor (19), the charge on which is measured by a moving coil instrument (21), the charging voltage being fed to an oscillograph (23).

NETWORK FOR THE CONVERSION OF ANALOGUE AND DIGITAL VALUES

1397484 Digital to analogue converters HOTTINGER BALDWIN MESSTECHNIK GmbH 16 Nov 1973 [17 Nov 1972] 53338/73 Heading G4H In a digital to analogue converter each bit of the digital code contributes to the analogue output signal an amount less than " 1 " plus the sum of the amounts contributed by the bits defining the next lower numerical value; " 1 " being the amount contributed by the least significant bit. For a binary digital input code, the bits may be weighted according to a geometric progression of ratio 1À90 to 1À99 (or otherwise between 1 and 2). In Fig. 4, the ratio is 1À95. In Fig. 5, Rp = 100 K, Rr = 48À7 K, Ra = 97À6 K, giving a ratio of 1-98. Thus when incrementing by 1 from, e.g., 01111 it is necessary to switch in one or more lower order bits as well to achieve the desired unity change in the analogue output. Because of this, not all possible digital combinations are available but no gaps occur in the analogue spectrum even if a highly significant bit stage has a weighting error of 5%. The invention is particularly useful in systems having a feedback loop containing an A-D and a D-A converter, e.g. for measuring peak values, Fig. 7 (not shown) or for taring, Fig. 8 (not shown).

Magnetic tape position measuring device

... 1,082,881. Electric position indication. KEUFFEL & ESSER CO. March 4, 1966 [March 8, 1965], No. 9595/66. Heading G4H. The position of a movable member is indicated by a magnetic tape having a scale recorded along its length for co-operation with a magnetic head on the movable member. In the form of Fig. 1 a pointer is carried over a chart 11 by a slider 22 moving on rails 20 which are themselves carried by sliders 14, 15 on rails 12, 13. Magnetic tapes are let into the rails 20 and 12 to be read by heads on the sliders and produce the signals. The coding on the tape, Fig. 4, includes four binary bits 1, 2, 4, 8 repeatedly indicating values 1-9, and three binary bits A, B, C indicating powers of ten. The reading heads are connected through a logical circuit to an indicator panel having lamps arranged in five columns. There is a separate panel for X, Y and Z movements. In the first nine positions the binary equivalents of values 1-9 are displayed in turn in the right-hand column of lamps.

DIGITAL TEMPERATURE INDICATOR HAVING AN AUTOMATIC DRIFT CORRECTION CIRCUIT

Electric device of transmission of orders or information using the reflected binary code, and its applications

Synchronous frequency modulation of numerical data

Analogue-digital converter

Successive approximation analog-to-digital converter and method of analog-to-digital conversion

An analog-to-digital converter includes a digital-to-analog converting circuit, a comparator, a comparator offset detector, and a signal processing circuit. The digital-to-analog converting circuit generates a reference voltage signal that changes in response to a comparator offset compensation signal, samples and holds an analog input signal, and performs a digital-to-analog conversion on digital output data to generate a hold voltage signal. The comparator compares the hold voltage signal with the reference voltage signal in response to a clock signal to generate a comparison output voltage signal. The comparator offset detector generates the comparator offset compensation signal based on the comparison output voltage signal. The signal processing circuit performs successive approximation based on the comparison output voltage signal to generate the digital output data.

Multi-level quantizer with current mode DEM switch matrices and separate DEM decision logic for a multibit sigma delta modulator

A multilevel quantizer is provided in combination with dynamic element matching (DEM) circuitry in a multibit sigma-delta modulator. The DEM circuitry is implemented in a divided manner as two major component parts: at least one current mode DEM switch matrix (SM), and an associated DEM decision logic block that implements the DEM control algorithm and that controls the SM. The DEM decision logic block is removed from the delay sensitive sigma-delta feedback loop, while the DEM SM remains within the feedback loop. Also described is a convenient and efficient technique to implement the DEM SM, using current steering logic within the multibit quantizer. In this case one or more DEM switching matrices may be provided within the quantizer for reordering the N-1 digital output bits of the N-level quantizer.

Analog-Wandler und speicher-programmierbares Steuerungssystem

Ein eine speicher-programmierbare Steuerung bildender und eine analog-digital Wandlung durch Verwendung von Offset/Verstärkungs-Werten (401) ausführender Analog-Wandler (30), wobei der Analog-Wandler (30) umfasst: eine Offset/Verstärkungs-Wert-Speichereinheit (321), welche aus einem nichtflüchtigen Speicher (32) gebildet wird und darauf die Offset/Verstärkungs-Werten (401) speichert; eine Operationseinheit (31), welche analog-digital Wandlung durch Verwendung der Offset/Verstärkungs-Werte (401) auf der Offset/Verstärkungs-Wert-Speichereinheit (321) als Werte für eine Interpolations-Operation ausführt; und eine Vorherige-Offset/Verstärkungs-Wert-Speichereinheit (322), welche aus einem nichtflüchtigen Speicher (32) gebildet wird und darauf die in der Vergangenheit verwendeten Offset/Verstärkungs-Werte (401) auf der Offset/Verstärkungs-Wert-Speichereinheit (321) als vorherige Offset/Verstärkungs-Werte (402) speichert, wobei die Operationseinheit (31) eine Offset/Verstärkungs-Wert-Einstelleinheit ...

Improvements in or relating to codecs

A Codec for encoding analogue signals into digital signals and for decoding digital signals to produce analogue signals for use in a telephone system includes two separate analogue input channels within the Codec the two channels being selectable by the Codec to process in a sequential manner information from either channel, encoding and decoding occurring at such a high speed that the Codec may be used with external multiplexing to process simultaneously 8 or more analogue channels. ...

ANALOGUE-DIGITAL CONVERTERS

... 1347932 A/D converters SIEMENS AG 9 March 1972 [22 March 1971] 10904/72 Heading G4H An A/D converter comprises a plurality of separate A/D stages 1-4 each having their input connected to a respective sample-andhold circuit 5-8 the inputs of which are connected in parallel to an analog input 9, and which are controlled by a device 10 whereby the A/D stages are fed serially one after the other by the circuits 5-8 with samples of the signal at 9, the output of each converter stage being taken to respective buffer stores 11-14 from which the digital signals are fed one after the other to a main output store 19 via switch devices 15-18 which are also controlled by the device 10. The apparatus is stated to maintain high resolution whilst operating at the maximum operation speed of the stages 1-4.

DISPLAY DEVICES

... 1368822 Display devices MARCONI CO Ltd 29 Feb 1972 [4 May 1971] 13035/71 Heading G4H In a display device, the indicators in a (straight or curved) series array of indicators are selectively energized using notional twodimensional co-ordinate selection. The two "co-ordinate directions" are scanned repetitively, a given indicator being energized by a suitably-timed input pulse. The indicators are light-emitting diodes, and further diodes can be provided as scale markings.

The analog/digital conversion in Δ - Σ overload detection and correction

ANALOGUE-DIGITAL CONVERTERS

Assembly to transform the analogical values of information into a train of impulses coded according to a binary code of permutation

Analogical data translator in numerical data

IMPROVEMENTS IN OR RELATING TO DIGITAL MEASUREMENTS

Analogical-digital converter for measuring devices

Coder of posting and visualization

Multi-channel pipelined signal converter

Successive approximation register analog-to-digital converter and associated control method

本發明揭露了一種連續逼近暫存式類比數位轉換器，其包含有開關電容陣列、緩衝器、比較器及控制邏輯電路。開關電容陣列用以根據開關控制信號來對輸入信號進行取樣以產生取樣信號，緩衝器用以產生共模電壓，比較器用以接收取樣信號以及共模電壓以產生比較結果，控制邏輯電路用以根據比較結果以產生輸出信號並產生開關控制信號以控制開關電容陣列；此外，控制邏輯電路另外產生操作控制信號，以調整緩衝器內部的米勒補償電容。此外，本發明也另外揭露了相關的控制方法。

METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS (ADCS)

An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

DYNAMIC HIGH-RESOLUTION ANALOG TO DIGITAL CONVERTER AND OPERATING METHOD THEREOF

A dynamic high-resolution ADC according to an example embodiment may include a dynamic amplifier configured to amplify, by as much as a first gain, the sampled-and-held analog signal received from the sample and hold circuit; DAC configured to convert a digital signal input from a decoder into an analog signal; a residue signal amplifier connected to the dynamic amplifier and the DAC and configured to calculate a difference between an output signal of the dynamic amplifier and an output signal of the DAC and amplify the difference by as much as a second gain; an ADC connected to the residue signal amplifier and configured to convert an output signal of the residue signal amplifier into a digital signal; and a decoder connected to the ADC and configured to decode, into digital data, an output signal of the ADC input by the ADC.

Process for mismatch correction of the output signal of a time-interleaved analog to digital converter

The invention relates to a process for mismatch correction of the output signal of a time-interleaved analog to digital converter, the output signal containing frequency components that include beside the desired signal tones one or more mismatch spur component groups, said process comprising: - generating (100) an analytical signal of the output signal of the time-interleaved analog to digital module, thereby creating a complex valued signal; - frequency shifting (101) of the analytical signal in order to shift the desired signal tone to the frequency locations of the corresponding mismatch spur component group by multiplication with a complex modulation vector; - creating (103) a mismatch identification signal for a mismatch spur component group by placing the mismatch spur component group at the conjugate frequency location of a desired signal tone, - subjecting (104) the mismatch identification signal to an IQ mismatch correction algorithm in order to derive mismatch spur parameters ...

Analog-digital-converter

... 964, 526. Shaft position digitisers. K. ZUSE. June 16, 1961 [June 18, 1960], No. 21761/61. Heading G4H. The position of a shaft is represented, in one embodiment, by a thirteen bit signal which is obtained from a coded scale having only three tracks each of which consist of a single series of binary code elements. Part of the scale is shown in Fig. 3 in which the units track SK 0 is read five bits at a time by a reading window F 1 , the pattern of code elements repeating after every twenty bits, so that each of digits 0-9 is represented by two different five bit signals sensed by photo-cells 1-5, Fig. 4a and applied to a decoding matrix Wp 0 , Fig. 4 which marks the corresponding lead 0, 01-9, 91. The tens and hundreds digits are represented by binary-coded blocks of four code elements selected from tracks SK 1 and SK 2 as shown in Fig. 3. The five-bit units digit determines whether the first or the last two blocks of four code elements are to be read from tracks SK 1 ...

Digital potentiometer for reflected binary code

... 783,654. Electric selective signalling and control systems. BENDIX AVIATION CORPORATION. Aug. 30, 1955 [Sept. 7, 1954], No. 24882/55. Class 40 (1). In an electric signalling or control system employing reflected binary code, digital relays responsive to the code signals connect a number of fixed impedances into a circuit in such combination as to produce in the circuit a total impedance corresponding to the value of the code. The circuit may be in the form of a continuous closed potentiometer which replaces the conventional transmitter in a synchro system. Fig. 1 shows a four-digit potentiometer comprising sections I, II, III, IV, each comprising a line 10, and a line 11 including a resistor the value of which doubles in successively higher digital sections. Digital switches 12 are controlled by relays D1 to D4 and for binary O complete the connection shown in solid lines and for binary 1 the connection shown in dotted lines. Actuation of any switch 12 transposes all the resistors between ...

Systems and methods for reducing audio artifacts from switching between paths of a multi-path signal processing

An audio processing system may include a controller 220 and a plurality of processing paths, e.g. a first path 201a and a second path 201b, the paths being arranged to generate respective digital signals based on an analogue input signal. The first path 201a may have a lower gain and a higher noise floor than the second path 201b. The controller 220 may be configured to determine that a transition between the first path and the second path needs to occur based on the occurrence of the analogue input signal crossing a threshold, or a prediction that the input signal will cross the threshold. In response to determining that a transition between the first path and the second path needs to occur, the controller blends the transition between the ADC paths during or near zero crossing points of the analogue input signal.

Pulse-width converter

... 955,229. Semi-conductor multi-state circuits. STANDARD TELEPHONES & CABLES Ltd. Nov. 8, 1962 [Nov. 8, 1961], No. 42256/62. Heading H3T. [Also in Division G4] A pulse-width converter uses a monostable trigger circuit to control current flow in a chain of tunnel diodes TDK having different peak currents, one state of the trigger circuit allowing the current flow in chain TDK to increase and the circuit being triggered to the other state for a predetermined time when the peak current of a tunnel diode is exceeded, current increase and triggering occurring alternately for the duration of the pulse to be converted. With switches a1 and a2 closed and open, respectively, a switch i is kept open for the duration of the pulse to be converted. When switch i is first opened, a transistor Tr2 conducts and a transistor Trl is cut off, thereby increasing current flow through the diode chain TDK and charging a capacitor C. When the peak current of a diode is exceeded, the potential across ...

Improvements in and relating to digital voltmeters

... 1,095,695. Measuring voltages. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. Nov. 1, 1965 [Nov. 4, 1964], No. 46061/65. Heading G4H. Apparatus for measuring an analogue input voltage U x comprises a comparator 1 into which is fed the voltage U x and a compensation voltage U c representative of the count in a counter 14, the output voltage from the comparator U v = U x - U c being fed via amplifiers 8, 9, 10 and threshold devices 11, 12, 13 to control the counter 14. In the form shown the difference voltage U v is fed to gate 11 having a threshold value 111 mV to pass a pulse to the most significant decade 15 of counter 14 if the voltage exceeds the threshold value. Similarly the difference voltage after an amplification by 10 at amplifier 9 is fed to gate 12 having a threshold value 110 to pass the pulse to the second decade 16 of the counter if this value is exceeded. After a further amplification by 10 the voltage is fed to gate 13 having a threshold value 50 mV to control the least ...

Switching configuration for the integration of unique, fast-acting procedures

Resolver signal conversion device and method

Process of conversion of an electric quantity into a pulse repetition frequency and means of realization

New servo system of engine of servomechanism

Device allowing the measurement of electric charges and very weak currents

Electromechanical coder of analog-to-digital position decimal

Measuring circuits of the amplitude of impulses

Tracking analog-to-digital converter with adaptive slew rate boosting

A tracking ADC with adaptive slew rate boosting can dynamically adjust one or more of its operational parameters in response to detecting a slew rate limit condition. In some embodiments, slew rate boosting can include increasing the value of a digital error signal in response to detection of a slew rate limit condition. In other embodiments, slew rate boosting can include increasing a clock frequency of the tracking ADC in response to detection of a slew rate limit condition.

Localized dynamic element matching and dynamic noise scaling in digital-to-analog converters (DACs)

Methods and systems are provided for enhanced digital-to-analog conversions. A segmentation-based digital-to-analog converter (DAC) may be configured for applying digital-to-analog conversions to N-bit inputs. The segmentation-based DAC may comprise a plurality of DAC elements, with each DAC element being operable to apply digital-to-analog conversion based on a single bit, and an encoder operable to generate an x-bit output. The number of DAC elements may be different than number of bits (N) in inputs to the DAC. One or more bits of the N-bit input may be applied to the encoder to generate the x-bit output, with each bit in the x-bit output being applied to a corresponding one of the plurality of DAC elements. Remaining one or more bits of the N-bit input, if any, may be applied directly to a corresponding one or more of the plurality of DAC elements.

Successive-approximation-register (SAR) analog-to-digital converter (ADC) attenuation capacitor calibration method and apparatus

A fixed capacitor is coupled between a top plate of an attenuation capacitor and a variable voltage reference. The error in the attenuation capacitor may be calibrated out with the variable voltage reference and the fixed correction capacitor. The variable voltage reference varies the charge on the attenuation capacitor and thereby compensates for error(s) therein. A calibration digital-to-analog converter may be used in conjunction with or substituted for the variable voltage reference, and may be programmed for different charge compensation values from the SAR logic during an iterative SAR DAC capacitive switching process.

OPTIMIZED ARRAYS FOR SEGMENTED SUCCESSIVE-APPROXIMATION-REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTER (ADC)

An integrated circuit including a segmented successive approximation register (SAR) analog-to-digital converter (ADC) includes a first capacitive structure with a first plurality of capacitive structure subcomponents that each include a first terminal selectively connected to one of a plurality of input voltage nodes and a second terminal connected to a common conductor, and second capacitive structure with a second plurality of capacitive structure subcomponents that each include a first terminal selectively connected to one of the plurality of input voltage nodes and a second terminal connected to the common conductor. The first and second plurality of capacitive structure subcomponents are arranged in an array in which none of the first plurality of capacitive structure subcomponents are directly adjacent to one another and none of the second plurality of capacitive structure subcomponents are directly adjacent to one another in a first row in the array. 1. An integrated circuit comprising: a first capacitive structure comprising a first plurality of capacitive structure subcomponents with first terminals connected to respective selective switches and second terminals connected to a common conductor;', 'a second capacitive structure comprising a second plurality of capacitive structure subcomponents with first terminals connected to selective switches, and second terminals connected to the common conductor;, 'a segmented successive approximation register (SAR) analog-to-digital converter (ADC) including a nominal capacitive value of each of the first plurality of capacitive structure subcomponents is a multiple of a nominal capacitive value of each of the second plurality of capacitive structure subcomponents, and', 'the first and second plurality of capacitive structure subcomponents are arranged in an array in which no more than two of the first plurality of capacitive structure subcomponents are directly adjacent to one another in a first direction in the ...

СПОСОБ И УСТРОЙСТВО ДЛЯ ОПРЕДЕЛЕНИЯ И ИСПОЛЬЗОВАНИЯ ЧАСТОТЫ ДИСКРЕТИЗАЦИИ ДЛЯ ДЕКОДИРОВАНИЯ ИНФОРМАЦИИ ВОДЯНОГО ЗНАКА, ВСТРОЕННОЙ В ПРИНИМАЕМЫЙ СИГНАЛ, ВЫБРАННЫЙ С ПОМОЩЬЮ ИСХОДНОЙ ЧАСТОТЫ ДИСКРЕТИЗАЦИИ НА СТОРОНЕ КОДЕРА

FIELD: information technologies. SUBSTANCE: method to detect and use sampling frequency for decoding of water sign information built into a received signal sampled with the initial sampling frequency at the coder's side, besides, the specified decoding includes correlation with at least one reference sample, in which in the searching mode: possible sampling frequencies are repeatedly scanned in the frequency range thus decoding the water sign; the maximum and the second maximum are determined among summary validity values; besides, as soon as their ratio or their difference becomes higher than the second threshold value, or when the maximum number of scanning cycles is achieved, the specified searching mode is terminated, and the specified normal mode is launched, where the selected possible sampling frequency is accepted as the initial sampling frequency, and the water sign of the received signal is decoded part by part or frame by frame sing the selected possible sampling frequency. EFFECT: correct detection of a sampling frequency for decoding of water sign information built into a received distorted signal. 18 cl, 2 dwg РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) 2 481 649 (13) C2 (51) МПК G10L 19/018 (2013.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ИЗОБРЕТЕНИЯ К ПАТЕНТУ (21)(22) Заявка: 2009102228/08, 23.01.2009 (24) Дата начала отсчета срока действия патента: 23.01.2009 (73) Патентообладатель(и): ТОМСОН ЛАЙСЕНСИНГ (FR) (43) Дата публикации заявки: 27.07.2010 Бюл. № 21 2 4 8 1 6 4 9 (45) Опубликовано: 10.05.2013 Бюл. № 13 2 4 8 1 6 4 9 R U Адрес для переписки: 129090, Москва, ул. Б. Спасская, 25, стр.3, ООО "Юридическая фирма Городисский и Партнеры" (54) СПОСОБ И УСТРОЙСТВО ДЛЯ ОПРЕДЕЛЕНИЯ И ИСПОЛЬЗОВАНИЯ ЧАСТОТЫ ДИСКРЕТИЗАЦИИ ДЛЯ ДЕКОДИРОВАНИЯ ИНФОРМАЦИИ ВОДЯНОГО ЗНАКА, ВСТРОЕННОЙ В ПРИНИМАЕМЫЙ СИГНАЛ, ВЫБРАННЫЙ С ПОМОЩЬЮ ИСХОДНОЙ ЧАСТОТЫ ДИСКРЕТИЗАЦИИ НА СТОРОНЕ КОДЕРА таким образом декодируя водяной знак; определяют максимум и второй ...

Digital-to-analogue data converters

Analogue-digital converter

... 1,028,954. Semi-conductor pulse circuits. DANFOSS A/S Jan. 21, 1965 [Jan. 21, 1964], No. 2736/65. Heading H3T. [Also in Division G4] An analogue voltage U A is applied to a solidstate threshold device 4 which is in turn connected to an integrating capacitor 5 and a differentiating capacitor 7. When the difference between U A and U C exceeds the threshold voltage, device 4 switches to a low resistance state, the direction of conduction through device 4 depending on the polarity of the difference between U A and U C . As U A rises by one increment, device 4 conducts and capacitor 5 is charged until the current through device 4 drops to a predetermined low level. A positive pulse is derived from capacitor 7 and passes through diode 9 for each positive increment of U A . A negative pulse is derived from capacitor 7 and passes through diode 12 for each negative increment of U A .

IMPROVEMENTS IN OR RELATING TO DIGITAL MEASUREMENTS

... 1276053 Measuring displacement ERNST LEITZ GmbH 17 July 1970 [29 July 1969] 34712/70 Heading G4H In apparatus in which the displacement of a member is converted to digital form by sensing a coded scale, to prevent errors at transitions, the sensors of all but the finest coded track are arranged to give outputs at a lower, intermediate and higher level (Fig. 2, not shown) the least significant sensor giving outputs signals only at the lower and intermediate levels, to determine each higher bit value, the output of the least significant sensor being added to the associated sensor output and the resulting signal fed to a discriminator 18 (Fig. 3) to give a " 1 " bit output if the track sensor output is at the higher level or the outputs of both the least significant sensor and the track sensor are at the intermediate level. As described, the two levels may be generated by (1) using an intermediate marking on the track over a range T, (2) using a stepped shutter or (3) using two shutters at ...

Digital measuring system for rotary movements

... 1,090,125. Electric selective signalling. LICENTIA PATENTVERWALTUNGS G.m.b.H. March 5, 1965 [March 9, 1964], No. 9484/65. Heading G4H. A photo-electric shaft position digitizing system is characterized in that one coded disc is illuminated by light passing either over or through a transparent annulus in a second coded disc. This feature means that all the discs of the system can be illuminated from a single light source.

A DEVICE FOR DIGITAL MEASURING OF PULSE RATE

... 1,243,122. Frequency measuring. TESLA NARODNI PODNIK. 14 Aug., 1969, No. 40729/69. Heading G4H. In a digital frequency measuring system of the type in which a difference signal r (Fig. 5) is derived by a difference circuit 1 from a feedback frequency signal p and the input frequency signal n, the time intervals between pulses of the difference signal are measured, the reciprocals of these intervals being digitally derived in a circuit 3 and accumulated (additively or subtractively) in a circuit 4 controlling a pulse generator 5 delivering the feedback signal p. In the stable condition the state of circuit 4 represents the input. The time intervals between pulses may be determined by counting pulses of known frequency f 0 . A single order counting stage may be used, which when full alters the frequency f 0 by one order. The order of the frequency then determines in which order of the adding circuit the reciprocal of the counter value should be accumulated. If the distribution of the input ...

ANALOG-TO-DIGITAL DRIVE CIRCUITRY HAVING BUILT-IN TIME GAIN COMPENSATION FUNCTIONALITY FOR ULTRASOUND APPLICATIONS

A time gain compensation (TGC) circuit for an ultrasound device includes a first amplifier having an integrating capacitor and a control circuit configured to generate a TGC control signal that controls an integration time of the integrating capacitor, thereby controlling a gain of the first amplifier. The integration time is an amount of time an input signal is coupled to the first amplifier before the input signal is isolated from the first amplifier.

Control circuit for analogue numerical display - display in form of moving point, band or column

Reader of angle

A method and system for electrical pulse counting for use in digital voltmeters, counters, or the like

Process and apparatus of quantification

System of numerical control of the angular position of a tree

Analog-to-digital converter

Patent FR2049534A5

METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS (ADCS)

An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision. 111-. (canceled)12. The ADC according to claim 21 , wherein the comparator is operable to set one or more least significant bits of the codeword up to claim 21 , but not including claim 21 , the one or more overlapping redundant bits in the codeword for a current comparison step claim 21 , the one or more least significant bits being set to a value derived from a value of a bit that was determined in an immediately preceding decision.13. The ADC according to claim 21 , wherein the timer is operable to generate the timeout signal based on a dynamically and/or adaptively determined threshold time.14. The ADC according to claim 13 , wherein the determined threshold time is selected so as to guarantee that a magnitude of a difference between the analog input and the reference input is within an overlapping range corresponding to the one or more overlapping redundant bits.15. The ADC according to claim 21 , wherein the comparator is operable to compare claim 21 , for said each of a plurality of comparison steps claim 21 , the analog input to the ...

Multi-channel pipelined signal converter

A signal converter such as a multi-channel pipelined signal converter includes a plurality of pipelined signal converters and a decision unit. Each of the pipelined signal converters has a respective plurality of stage cells coupled in series with switched coupling between the pipelined signal converters. The decision unit determines a respective selected path through the stage cells of the plurality of pipelined signal converters for each of a plurality of input signals during a signal path selection mode.

D=A converter decoding characteristic testing - involves application of analogue output to A=D converter and comparison with input signal

The D-A converter belongs to an A-D converter based on the method of successive approminations. Its characteristics is tested for deviation from a specified decoding characteristic. Analogue signals delivered by the D-A converter (DA) at its analogue output (EA) in response to a digital signal applied to its digital input (JD), are applied to the analogue signal input (JA) of a calibrated analogue-digital converter (AD). Digital signals applied to the D-A converter are compared in a comparator (VD) with the A-D converter output digital signals.

Improvements in or relating to electrical digital-to-analogue signal converters

... 1,000,689. Electric selective signalling. AUTOMATIC TELEPHONE & ELECTRIC CO. Ltd. June 26, 1964, No. 26626/64. Drawings to Specification. Heading G4H. In an electrical digital-to-analogue converter, each bit of the digital input is fed to a corresponding section comprising bi-stable devices equal in number to the weight of the bit, to produce currents in two output leads (each connected to every section) in dependence on the number of bi-stable devices assuming one state and the other state respectively, the relative currents in the two output leads signifying the analogue equivalent of the digital input. In the particular embodiment, each bi-stable device (all identical) is a differential amplifier and each bit is supplied in normal and inverted form on a pair of leads. The two output leads may be connected to opposing deflection coils in a cathode-ray tube. Zero adjustment means are provided.

Analogue-to-digital converter

A digitally companding p.c.m. encoder

... 1,099,868. Selective signalling. STANDARD TELEPHONES & CABLES Ltd. Aug. 17, 1966, No. 36812/66. Heading G4H. In a non-linear analogue-todigital converter covering the range 0-1024 (negative inputs being inverted before being digitized and a sign digit made equal to 0) first the particular one of eight ranges or octaves, 0 to 8, 8 to 16, 16 to 32, 32 to 64, 64 to 128, 128 to 256, 256 to 512 and 512 to 1024, in which the input lies is ascertained and represented by three bits, referred to as the " octave number," and secondly, the position of the input within its octave is determined linearly, accurately to three bits referred to as the octave position." Thus in the first octave 0 to 8, each increment in the octave position corresponds to a unit increment in the input, whereas in the eighth octave, 512 to 1024, each increment corresponds to an increment of 64 in the input. The octave number is determined by a series of eight units C2A, S2A; C2B, S2B; C2G, S2G; Fig. 1 (the first stage C1 is ...

Analog-to-digital conversion

The drain voltage of transistor M3 is maintained constant by a feedback loop OP1, I2 so that charge is not injected into the ramp signal node by parasitic capacitor C2 when the comparator switches. The ramp signal may be commonly applied to many comparators in a CMOS imaging sensor. The technique prevents dependency of a pixel ADC output on the signal values of other pixels in the row. The bias currents I4 and I5 in the output stages may be set so that the current consumption is independent of the comparator state. The input capacitance of the comparator is independent of the state of the comparator, which is beneficial in successive-approximation, cyclic and pipeline ADCs (figures 10 to 12).

SEMICONDUCTOR STORAGE DEVICE

1406691 Integrated circuits NIPPON GAKKI SEIZO KK 31 July 1972 [31 July 1971 (2) 1 Sept 1971 22 Nov 1971 (3)] 35683/72 Heading H1K [Also in Divisions G5 and H3] In a monolithic semiconductor analogue storage system stored information is represented by impedances exhibited by discrete elements within the monolith, which are selectively brought into circuit by switches operated in response to signals from read-out circuitry. The switches may be bipolar transistors or JUGFETs but as described are IGFETs. Typically, Fig. 1, the impedances are lengths of diffused resistive regions P 1 -P n defined between one end, constituting the drain of an IGFET, and an intermediate point connected via a common aluminium track to an output terminal T out which is connected through a load resistor to a voltage source. The resistors are successively switched into circuit by pulses applied by the read-out circuit to the gates of the associated IGFETs in response to a train of clock pulses. Operation of the read-out circuit is described. To simplify manufacture, which involves conventional diffusion, oxide patterning and aluminium deposition steps, instead of using a mask to form single interconnecting holes CP, &c. in the oxide overlying each resistor region, as shown, specific to a particular set of stored values, a plurality of holes or a continuous slot is formed over each region and particular stored values then determined by depositing the aluminium connector, as shown in Fig. 10 to short out the unwanted parts of the regions. Any holes not covered by the connector are optionally covered by isolated patches of aluminium for passivation. In alternative forms Figs. 3 and 4 respectively (not shown) in which the impedances are the channels of IGFETs which are identical except in respect of their channel lengths (Fig. 3, not shown) or widths (Fig. 4, not shown) and the common load is also an IGFET the read out pulses are fed to the respective IGFET gates. Finally as shown in Fig. 8 ...

Method and Apparatus for Calibration of Successive Approximation Register Analog-to-Digital Converters

A successive approximation register (SAR) ADC includes an SAR comparator circuit including first and second inputs, a control input, and first and second outputs. The SAR comparator circuit further includes a plurality of capacitors coupled to the first and second inputs and includes a plurality of switches configured to couple the plurality of capacitors to one of a first voltage and a second voltage. The SAR ADC further includes a calibration circuit coupled to the first and second outputs and to the control input of the SAR comparator. The calibration circuit is configured to control the plurality of switches to selectively couple the plurality of capacitors to one of the first and second voltages to provide a calibration signal to the SAR comparator circuit. The calibration circuit is configured to calibrate the SAR comparator based on corresponding output signals at the first and second outputs. 1. A successive approximation register (SAR) analog-to-digital converter (ADC) comprising:an SAR comparator circuit including first and second inputs, a control input, and first and second outputs, the SAR comparator circuit including a plurality of capacitors coupled to the first and second inputs and including a plurality of switches configured to couple the plurality of capacitors to one of a first voltage and a second voltage; anda calibration circuit coupled to the first and second outputs and to the control input of the SAR comparator circuit, the calibration circuit including a signal generator to provide a control signal configured to control the plurality of switches to selectively couple the plurality of capacitors to one of the first and second voltages provide a calibration signal to the SAR comparator circuit, the calibration circuit configured to calibrate the SAR comparator circuit based on corresponding output signals at the first and second outputs.2. The SAR ADC of claim 1 , wherein the calibration circuit comprises an error computation unit coupled to ...

SWITCHING SCHEME FOR ISI MITIGATION IN DATA CONVERTERS

Embodiments of the present disclosure may provide a switching scheme for tri-level unit elements with ISI mitigation. A tri-level unit element may include a first and second current source and a plurality of switches arranged to form three circuit branches between the first and the second current source. The first circuit branch may include two switches connected in parallel between the first current source and a first output terminal and two switches connected in parallel between the second current source and the first output terminal. The second circuit branch may include two switches connected in parallel between the first current source and a second output terminal and two switches connected in parallel between the second current source and the second output terminal. The third circuit branch may include switches to couple the first current source and the second current source to a dump node. 120-. (canceled)21. A method of mitigating inter-symbol interference in a tri-level digital to analog converter (DAC) , comprising:receiving, at the tri-level DAC, a digital data signal;converting the digital data signal into an analog signal in at least one tri-level unit element by switching within the tri-level unit element based on the digital data signal, wherein the inter-symbol interference generated by the conversion is independent of the digital data signal; andoutputting the analog signal.22. The method of claim 21 , further comprising:receiving a clock signal, andcontrolling the switching based on the clock signal.23. The method of claim 22 , wherein the switching occurs multiple times in a clock cycle.24. The method of claim 21 , wherein the inter-symbol interference generated by the conversion is substantially the same as in a preceding conversion.25. The method of claim 21 , further comprising:receiving a current from a current source,wherein the switching includes switching the current to an output based on the digital data signal.26. The method of claim 25 , ...

Transmitter Noise Shaping

Embodiments of the disclosed invention address a method, apparatus and computer program product for enabling enhanced transmitter noise shaping. Thereby, a first digital-to-analog conversion is performed on a digital signal resulting in first analog signal, a noise shaping on the digital signal is performed for obtaining a noise shaped signal and performing a second digital-to-analog conversion on the noise shaped signal resulting in a second analog signal, and the first analog signal and the second analog signal are added for obtaining an output signal.

METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS (ADCS)

An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision. 120-. (canceled)21. An analog-to-digital converter (ADC) , comprising:a comparator comprising an analog input, a reference input, a preemption input, a codeword output, and a validation output, a codeword on the codeword output of the comparator comprising one or more overlapping redundant bits, wherein if a preemption is indicated at the preemption input, the validation output is set to indicate the preemption and one or more bits of the codeword are set to a particular value, and wherein if a preemption is not indicated at the preemption input, the validation output is set to indicate a valid decision and one or more bits of the codeword are set according to a comparison between the analog input and the reference input;a digital-to-analog converter (DAC) comprising a codeword input and a reference output, wherein the reference output of the DAC is operably coupled to the reference input of the comparator and the codeword input of the DAC is operably coupled to the codeword output of the comparator; anda timer operable to set a preemption output ...

METHOD AND DEVICE FOR COMPENSATING BANDWIDTH MISMATCHES OF TIME INTERLEAVED ANALOG TO DIGITAL CONVERTERS

A device can be used for compensating bandwith mismatches of time interleaved analog to digital converters. A processor of the device determines, for each original sample stream, an estimated difference between the time constant of a low pass filter representative of the corresponding converter and a reference time constant of a reference low pass filter, and uses this estimated difference and a filtered stream to correct the original stream and deliver a corrected stream of corrected samples. 112-. (canceled)13. A method of direct compensation of bandwidth mismatch , the method comprising:receiving M original trains of M original samples from of M time-interleaved converters, M being greater than two, each converter being considered in the first order as comprising a first order low-pass filter;digitally filtering the M original trains delivering M corresponding filtered trains of filtered samples, the filtering having a transfer function substantially equal to the product of a transfer function of a reference low-pass filter and a transfer function of a derivative filter multiplied by a reference time constant of the reference low-pass filter; and performing an estimation process to deliver an estimated difference between the time constant of the first order low-pass filter associated with the corresponding converter and the reference time constant, the estimation process comprising a first generation of a first item of differentiated power information relative to the original train and a second generation of a second item of information of differentiated power relative to at least one of the M filtered trains, and', 'performing a correction process of the original samples of the original train using the filtered samples of the corresponding filtered train and the corresponding estimated difference, in such a way as to deliver a corrected train of corrected samples., 'for each original train of original samples,'}14. The method according to claim 13 , wherein the ...

ANALOG-TO-DIGITAL CONVERTER AND SELF-DIAGNOSIS METHOD FOR ANALOG-TO-DIGITAL CONVERTER

An analog-to-digital converter includes an input terminal to which an analog input voltage is input, a digital-to-analog converter unit, a comparator that compares the analog input voltage and an output voltage of the digital-to-analog converter unit with each other, a successive approximation register that stores a conversion result output from the comparator, a generator unit that generates added digital data and subtracted digital data, the added digital data and the subtracted digital data being obtained by adding and subtracting the conversion result to and from the conversion result retained by the successive approximation register, respectively, and a determination unit that determines whether or not a failure is occurring, by using a result of the comparison between the analog input voltage and output levels obtained by the digital-to-analog converter unit converting the added digital data and the subtracted digital data. 1. An analog-to-digital converter comprising:an input terminal to which an analog input voltage is input;a digital-to-analog converter unit;a comparator that compares the analog input voltage and an output voltage of the digital-to-analog converter unit with each other;a successive approximation register that stores a conversion result output from the comparator;a generator unit that generates added digital data and subtracted digital data, the added digital data and the subtracted digital data being obtained by adding and subtracting the conversion result to and from the conversion result retained by the successive approximation register, respectively; anda determination unit that determines whether or not a failure is occurring, by using a result of the comparison between the analog input voltage and output levels obtained by the digital-to-analog converter unit converting the added digital data and the subtracted digital data.2. The analog-to-digital converter according to claim 1 , wherein the determination unit determines that a ...

CONTINUOUS TRACKING OF MISMATCH CORRECTION IN BOTH ANALOG AND DIGITAL DOMAINS IN AN INTERLEAVED ADC

A system. The system includes a first tracking filter configured to track a frequency domain mismatch profile between component analog-to-digital convertors (ADCs) of an interleaved ADC (IADC), and a second tracking filter configured to a track a frequency independent timing delay mismatch and a timing delay mismatch correction error based on frequency domain mismatch profile estimates. An output of the first tracking filter determines a correction of a frequency dependent mismatch profile in an output of the interleaved ADC and an output of the second tracking filter determines a correction of the timing delay mismatch correction error in the output of the interleaved ADC. 1. A. system comprising:a first tracking filter configured to track a frequency domain mismatch profile between component analog-to-digital convertors (ADCs) of an interleaved ADC (IADC); 'an output of the first tracking filter determines a correction of a frequency dependent mismatch profile in an output of the interleaved ADC and an output of the second tracking filter determines a correction of the timing delay mismatch correction error in the output of the interleaved ADC.', 'a second tracking filter configured to a track a frequency independent timing delay mismatch and a timing delay mismatch correction error based on frequency domain mismatch profile estimates; and wherein2. The system of further comprising control logic coupled to the first and second tracking filters claim 1 , and wherein the control logic is configured to:couple the frequency domain mismatch profile estimate to the first and second tracking filters in a first correction phase; andcouple a difference of the frequency domain mismatch profile estimate and an output of the first tracking filter to the second tracking filter in a second correction phase.3. The system of wherein the control logic is further configured to couple the difference of the frequency domain mismatch profile estimate and an output of the first ...

Detecting and Preventing Light-Based Injection Attacks

This document describes techniques and apparatuses directed at detecting and preventing light-based injection attacks. In aspects, a computing device includes executable instructions of an input manager, an audio sensor having subtracting circuitry, and a light sensor. One or more processors executing instructions of the input manager is configured to receive and analyze signals generated by the audio sensor, the light sensor, and the subtracting circuit. Upon analysis, the input manager can detect and prevent light-based injection attacks. 1. A computing device comprising:an audio sensor, the audio sensor configured to detect differences in air pressure andgenerate first electrical signals;a light sensor, the light sensor configured to detect electromagnetic radiation and generate second electrical signals;at least one processor; andat least one computer-readable storage medium comprising instructions of an input manager that, when executed by the at least processor, cause the processor to perform signal subtraction of the second electrical signals generated by the light sensor from the first electrical signals generated by the audio sensor.2. The computing device of claim 1 , wherein the audio sensor is a micro-electro-mechanical system (MEMS) microphone.3. The computing device of claim 1 , wherein the light sensor is integrated within the audio sensor.4. The computing device of claim 1 , wherein the light sensor is configured to detect electromagnetic radiation in a 3 terahertz (THz) to 3 petahertz (PHz) frequency range.5. The computing device of claim 1 , wherein the at least one processor executing instructions of an input manager detects and prevents a light-based injection attack claim 1 , and further warns a user.6. A micro-electro-mechanical system (MEMS) microphone claim 1 , the MEMS microphone comprising:a MEMS transducer, the MEMS transducer having at least one backplate and a mechanical diaphragm forming a capacitor, the mechanical diaphragm configured ...

LOCALIZED DYNAMIC ELEMENT MATCHING AND DYNAMIC NOISE SCALING IN DIGITAL-TO-ANALOG CONVERTERS (DACS)

Methods and systems are provided for using localized dynamic element matching (DEM) and/or dynamic noise scaling (DNS) in digital-to-analog converters (DACs). Adaptive (localized) DEM may be applied in a DAC, by selecting one or more of a plurality DAC elements in the DAC, forcing the selected one or more of the plurality of DAC elements not to switch during digital-to-analog conversions, and scrambling remaining one or more of plurality of DAC elements when generating an output of the DAC. The adaptive DEM may be applied when the DAC input is backed off from full-scale. DNS may be applied in a DAC, by adaptively selecting one or more of a plurality DAC elements in the DAC and switching off the selected one or more of the plurality DAC elements such that the selected one or more of the plurality DAC elements do not contribute to generating an output of the DAC. 1. A method , comprising: selecting one or more of a plurality of DAC elements in the DAC;', 'forcing the selected one or more of the plurality of DAC elements not to switch during digital-to-analog conversion of an input to the DAC; and', 'scrambling remaining one or more of the plurality of DAC elements when generating an output of the DAC that corresponds to the input to the DAC., 'applying adaptive dynamic element matching, in a digital-to-analog converter (DAC), during digital-to-analog conversion, by2. The method of claim 1 , comprising scrambling the remaining one or more of the plurality of DAC elements such that a mismatch error caused thereby does not lead to nonlinear distortion.3. The method of claim 1 , comprising applying the adaptive dynamic element matching when the DAC input is backed off from full-scale.4. The method of claim 1 , comprising controlling the plurality of DAC elements claim 1 , during adaptive dynamic element matching claim 1 , via a switching arrangement comprising one or more switching elements configured for controlling switching of the plurality of DAC elements.5. The ...

ANALOG-TO-DIGITAL CONVERTER CIRCUIT AND METHOD FOR ANALOG-TO-DIGITAL CONVERSION

In one embodiment an analog-to-digital converter circuit has an input for receiving a first analog signal level and a second analog signal level, a ramp generator adapted to provide a ramp signal, a comparison unit coupled to the input and the ramp generator, a control unit coupled to the comparison unit the control unit having a counter, the control unit being prepared to enable the counter as a function of a comparison of the ramp signal with the first analog signal level and the second analog signal level, and an output for providing an output digital value as a function of a relationship between the first analog signal level and the second analog signal level. Therein the ramp signal has at least one linearly rising and at least one linearly falling portion and an adjustable shift at a reversal point between the rising and the falling portion of the ramp signal, the shift depending on the number of rising and falling portions of the ramp signal. 1. An analog-to-digital converter circuit havingan input for receiving a first analog signal level and a second analog signal level,a ramp generator adapted to provide a ramp signal,a comparison unit coupled to the input and the ramp generator,a control unit coupled to the comparison unit the control unit having a counter, the control unit being prepared to enable the counter as a function of a comparison of the ramp signal with the first analog signal level and the second analog signal level, andan output for providing an output digital value as a function of a relationship between the first analog signal level and the second analog signal level,wherein the ramp signal has at least one linearly rising and at least one linearly falling portion and an adjustable shift at a reversal point between the rising and falling portion of the ramp signal, the shift depending on the number of rising and falling portions of the ramp signal.2. The analog-to-digital converter circuit according to claim 1 , wherein the shift at the ...

Reference Voltage Generator for an Analog-Digital Converter and Method for Analog-Digital Conversion

Analog-digital converter configured for conversion of an input voltage, represented by a pair of input potentials, into a binary code using successive approximation. The analog-digital converter comprises a reference voltage generator (RVG) supplying a first pair of reference potentials and a second pair of reference potentials. The analog-digital converter further comprises a switched capacitor array (SCA) configured to receive the first and the second pair of reference potentials as well as a control unit (CTRL) coupled to the switched capacitor array (SCA) and configured to switch capacitors of the switched capacitor array (SCA) either to the first pair of reference potentials or to the second pair of reference potentials depending on a progress of the conversion. 1. Reference voltage generator (RVG) for supplying a first pair of reference potentials at a first terminal pair and a second pair of reference potentials at a second terminal pair to a switched capacitor array (SCA) of an analog-digital converter working with successive approximation , wherein{'b': 1', '2, 'the reference voltage generator (RVG) comprises a first input (I) and a second input (I) to be coupled to an external voltage supply (EVS); and'}{'b': 1', '2, 'a first charge reservoir (RESa) with a first and a second terminal coupled between the first terminal pair, the first terminal coupled to the first input (I) via a first switch and the second terminal coupled to the second input (I) via a second switch; and'}{'b': 1', '2, 'the second terminal pair is coupled to the first input (I) and the second input (I).'}2. Reference voltage generator (RVG) according to claim 1 , further comprising:{'b': 1', '1, 'a first charge pump (CP) coupled to the first terminal of the first charge reservoir (RESa) via a first pump switch (PS); and'}{'b': 2', '2, 'a second charge pump (CP) coupled to the second terminal of the first charge reservoir (RESa) via a second pump switch (PS).'}31212. Reference voltage ...

MULTIPLE SAMPLING STAGE RECEIVER AND RELATED METHODS

A line receiver including an analog-to-digital converter is described. The line receiver may include an input stage, a first sampling stage, an integration stage, and a second sampling stage. The input stage may be configured to receive an input voltage representative of a signal transmitted by a transmitter, and to convert the input voltage to a current. The input stage may include a trans-conductance stage. The current may be sampled using the first sampling stage. The sampled current may be converted to a voltage using the integration stage. The integration stage may include a trans-impedance stage. The voltage obtained using the integration stage may be sampled using the second sampling stage. 1. A line receiver comprising:an input stage configured to receive an input signal and to generate an intermediate signal;a first sampling stage coupled to the input stage and configured to sample the intermediate signal at a first rate;an integration stage coupled to the first sampling stage and configured to integrate the sampled intermediate signal; anda second sampling stage coupled to the integrator stage and configured to sample the integrated sampled intermediate signal at a second rate,wherein the first sampling stage comprises a plurality of switches configured to sample the intermediate signal at different times and wherein the integration stage comprises a plurality of integrators, each of the plurality of integrators being coupled to a respective switch of the plurality of switches.2. The line receiver of claim 1 , wherein the integration stage comprises an amplifier and a capacitor coupled between an input terminal and an output terminal of the amplifier.3. The line receiver of claim 2 , wherein the input terminal of the amplifier is clamped to a fixed potential.4. The line receiver of claim 2 , wherein the amplifier has a gain that is greater than 1.5. The line receiver of claim 2 , wherein the amplifier has a gain that is greater than or equal to 100.6. The ...

SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER AND METHOD OF ANALOG-TO-DIGITAL CONVERSION

An analog-to-digital converter includes a digital-to-analog converting circuit, a comparator, a comparator offset detector, and a signal processing circuit. The digital-to-analog converting circuit generates a reference voltage signal that changes in response to a comparator offset compensation signal, samples and holds an analog input signal, and performs a digital-to-analog conversion on digital output data to generate a hold voltage signal. The comparator compares the hold voltage signal with the reference voltage signal in response to a clock signal to generate a comparison output voltage signal. The comparator offset detector generates the comparator offset compensation signal based on the comparison output voltage signal. The signal processing circuit performs successive approximation based on the comparison output voltage signal to generate the digital output data. 1. An analog-to-digital converter , comprising: generate a reference voltage signal, the reference voltage signal changing in response to a comparator offset compensation signal,', 'sample and hold an analog input signal, and', 'perform a digital-to-analog conversion on digital output data to generate a hold voltage signal;, 'a digital-to-analog converting circuit configured to,'}a comparator configured to compare the hold voltage signal with the reference voltage signal in response to a clock signal to generate a comparison output voltage signal;a comparator offset detector configured to generate the comparator offset compensation signal based on the comparison output voltage signal; anda signal processing circuit configured to perform analog-to-digital conversion using a successive approximation based on the comparison output voltage signal to generate the digital output data.2. The analog-to-digital converter of claim 1 , wherein the analog-to-digital converter is configured to claim 1 ,perform an analog-to-digital conversion on a comparator offset to generate the comparator offset compensation ...

ANALOG CONVERTER AND PROGRAMMABLE LOGIC CONTROLLER SYSTEM

An analog converter includes an offset/gain value storage unit that is composed of a nonvolatile memory and stores therein offset/gain values, an operation unit that performs analog-digital conversion by using the offset/gain values in the offset/gain value storage unit as values for an interpolation operation, a previous offset/gain value storage unit that is composed of a nonvolatile memory and stores therein, as previous offset/gain values, the offset/gain values in the offset/gain value storage unit used in the past, wherein the operation unit includes an offset/gain value setting unit that controls setting of the offset/gain values in the offset/gain value storage unit and storage of the previous offset/gain values in the previous offset/gain value storage unit. 1. An analog converter constituting a programmable logic controller and performing analog-digital conversion by using offset/gain values , the analog converter comprising:an offset/gain value storage unit that is composed of a nonvolatile memory and stores therein the offset/gain values;an operation unit that performs analog-digital conversion by using the offset/gain values in the offset/gain value storage unit as values for an interpolation operation; anda previous offset/gain value storage unit that is composed of a nonvolatile memory and stores therein, as previous offset/gain values, the offset/gain values in the offset/gain value storage unit used in the past,wherein the operation unit includes an offset/gain value setting unit that controls setting of the offset/gain values in the offset/gain value storage unit and storage of the previous offset/gain values in the previous offset/gain value storage unit.2. The analog converter according to claim 1 , wherein claim 1 , upon reception of a setting request for new offset/gain values in the offset/gain value storage unit claim 1 , the offset/gain value setting unit stores the new offset/gain values in the offset/gain value storage unit after storing ...

ANALOG TO DIGITAL CONVERSION CIRCUIT

An analog-to-digital (AD) convertor includes: an AD conversion circuit; and a correction circuit that corrects an output value of the AD conversion circuit based on a correction value, wherein the correction circuit generates a plurality of elemental correction values based on a plurality of output values which are converted values of a plurality of analog values by the AD conversion circuit, wherein the correction value is determined by an average value of remaining values obtained by removing a deviated value from the plurality of elemental correction values. 1. An analog-to-digital (AD) convertor , comprising:an AD conversion circuit; anda correction circuit that corrects an output value of the AD conversion circuit based on a correction value,wherein the correction circuit generates a plurality of elemental correction values based on a plurality of output values which are converted values of a plurality of analog values by the AD conversion circuit,wherein the correction value is determined by an average value of remaining values obtained by removing a deviated value from the plurality of elemental correction values.2. The AD converter according to claim 1 , wherein the deviated value includes at least one of a maximum value and a minimum value of the plurality of elemental correction values.3. The AD converter according to claim 2 , wherein the deviated value further includes at least one of a predetermined upper limit value and a predetermined lower limit value.4. The AD converter according to claim 1 , wherein the deviated value includes a predetermined range of values for the plurality of elemental correction values.5. The AD converter according to claim 4 , wherein the predetermined range of values includes at least one of top N values and low M values (N claim 4 , M: an integer value greater than or equal to 2).6. A calibration method of an analog-to-digital (AD) converter claim 4 , comprising:generating a plurality of elemental correction values based on ...

ANALOG-TO-DIGITAL DRIVE CIRCUITRY HAVING BUILT-IN TIME GAIN COMPENSATION FUNCTIONALITY FOR ULTRASOUND APPLICATIONS

A time gain compensation (TGC) circuit for an ultrasound device includes a first amplifier having an integrating capacitor and a control circuit configured to generate a TGC control signal that controls an integration time of the integrating capacitor, thereby controlling a gain of the first amplifier. The integration time is an amount of time an input signal is coupled to the first amplifier before the input signal is isolated from the first amplifier. 1. A time gain compensation (TGC) circuit for an ultrasound device , comprising:a first amplifier having a first integrating capacitor; anda control circuit configured to control a gain of the first amplifier by generating a TGC control signal that controls an integration time of the first integrating capacitor, the integration time comprising an amount of time an input signal is coupled to the first amplifier before the input signal is isolated from the first amplifier.2. The TGC circuit of claim 1 , wherein the first amplifier comprises a differential amplifier.3. The TGC circuit of claim 2 , wherein the differential amplifier comprises an analog-to-digital converter (ADC) driver.4. The TGC circuit of claim 1 , wherein the control circuit further comprises:a second amplifier having a feedback capacitor, the second amplifier configured as a comparator circuit, wherein the control circuit generates the TGC control signal by a comparison between an output voltage of the second amplifier and a threshold voltage determined by a value of a variable gain control input signal.5. The TGC circuit of claim 4 , wherein the second amplifier comprises an operational amplifier.6. The TGC circuit of claim 1 , wherein the integration time controlled by the TGC control signal is dependent upon an RC time constant of the control circuit and a voltage of the variable gain control input signal.7. The TGC circuit of claim 6 , wherein an output gain of the first amplifier is proportional to a ratio between resistance and capacitance ...

SYSTEM FOR CONVERSION BETWEEN ANALOG DOMAIN AND DIGITAL DOMAIN WITH MISMATCH ERROR SHAPING

The invention provides a system for conversion between analog domain and digital domain with mismatch error shaping, including a DAC, a first injection circuit couple to the DAC, and a second injection circuit coupled to the DAC. The DAC generates a first analog value in response to a first digital value, and generates a second analog value in response to a second digital value. The first injection circuit enables an analog injection value to be injected to the second analog value when the DAC generates the second analog value, wherein the analog injection value is converted from a digital injection value formed by a subset of bits of the first digital value. The second injection circuit combines the digital injection value and one of the following: the second digital value and a related value obtained according to the second analog value. 1. A system for conversion between analog domain and digital domain with mismatch error shaping , comprising:a DAC (digital-to-analog converter) generating a first analog value in response to a first digital value, and generating a second analog value in response to a second digital value;a first injection circuit couple to the DAC, enabling an analog injection value to be injected to the second analog value when the DAC generates the second analog value, wherein the analog injection value is converted from a digital injection value formed by a subset of bits of the first digital value; anda second injection circuit coupled to the DAC, for combining the digital injection value and one of the following: the second digital value and a related value obtained according to the second analog value.2. The system of further comprising:a first ADC (analog-to-digital converter) for converting an input analog value to the second digital value,a first sum block coupled between the input analog value and the DAC for subtracting the second analog value from the input analog value to form an internal analog value,a second ADC coupled to the ...

ANALOG INPUT DEVICE

An analog input device, which converts an inputted analog signal to a digital signal and outputs the digital signal, includes a high resolution AD converter, a first low resolution AD converter, and a second low resolution AD converter. When a difference between a first digital signal converted by the high resolution AD converter and a second digital signal converted by the first low resolution AD converter is equal to or less than a predetermined first threshold, the analog input device outputs first digital signal. When the difference between the first digital signal and the second digital signal is larger than the predetermined first threshold, the analog input device stops an output of the first digital signal. 1. An analog input device , which converts an analog signal input to the analog input device to a digital signal and outputs the digital signal that is converted , the analog input device comprising:a high resolution analog to digital converter executing an analog to digital conversion to the analog signal with a first resolution and outputting a first digital signal that is converted;a first microcomputer including a first low resolution analog to digital converter, the first low resolution analog to digital converter executing an analog to digital conversion to the analog signal with a second resolution and outputting a second digital signal that is converted, and the second resolution being lower than the first resolution;a second microcomputer including a second low resolution analog to digital converter, the second low resolution analog to digital converter executing an analog to digital conversion to the analog signal with the second resolution and outputting a third digital signal that is converted;a first comparator comparing the first digital signal output from the high resolution analog to digital converter with the second digital signal output from the first low resolution analog to digital converter as a first comparison process;a digital ...

Method and apparatus to reduce effect of dielectric absorption in sar adc

A successive approximation register analog to digital converter (SAR ADC) is provided in which impact of dielectric absorption is reduced with a correction circuit configured to adjust a present digital code value signal based at least in part upon a previous digital code value signal, an acquisition time and temperature.

Analog-to-digital converter with bandpass noise transfer function

Methods and apparatus for providing bandpass analog to digital conversion (ADC) in RF receiver circuitry of a wireless-communication device. The bandpass ADC includes first noise-shaping successive approximation register (NS-SAR) circuitry arranged in a first path and second NS-SAR circuitry arranged in a second path parallel to the first path, wherein the first and second NS-SAR circuitries are configured to alternately sample an analog input voltage at a particular sampling rate and to output a digital voltage at the particular sampling rate.

PARAMETER CORRECTION FOR CASCADED SIGNAL COMPONENTS

Various examples are directed to crosspoint switches and methods of use thereof. An example cross point switch comprises a first row buffer, a second row buffer, a first column buffer, and a second column buffer. The crosspoint switch may also comprise a first switch that, when closed, electrically couples the second row buffer to the first column buffer, and a correction controller. The correction controller may be configured to send a first correction signal to the first row buffer, send a second correction signal to the second row buffer; receive an indication that the first switch is closed, send a third correction signal to the first column buffer; and send a fourth correction signal to the second column buffer. 17-. (canceled)8. A crosspoint switch , comprising:a first row buffer comprising: a first row buffer input; a first row buffer output; and a first row buffer correction input;a second row buffer comprising: a second row buffer input electrically coupled to the first row buffer output;a second row buffer output; and a second row buffer correction input;a first column buffer comprising: a first column buffer input; a first column buffer output; and a first column buffer correction input;a second column buffer comprising: a second column buffer input electrically coupled to the first column buffer output; a second column buffer output; and a second column buffer correction input;a first switch having an open position and a closed position, wherein when the first switch is in the closed position, the second row buffer output is electrically coupled to the first column buffer input; send a first correction signal to the first row buffer;', 'send a second correction signal to the second row buffer;', 'receive an indication that the first switch is closed;', 'after receiving the indication that the first switch is closed, send a third correction signal to the first column buffer; and', 'after receiving the indication that the first switch is closed, send a ...

LOCALIZED DYNAMIC ELEMENT MATCHING AND DYNAMIC NOISE SCALING IN DIGITAL-TO-ANALOG CONVERTERS (DACS)

Methods and systems are provided for using localized dynamic element matching (DEM) and/or dynamic noise scaling (DNS) in digital-to-analog converters (DACs). Adaptive (localized) DEM may be applied in a DAC, by selecting one or more of a plurality DAC elements in the DAC, forcing the selected one or more of the plurality of DAC elements not to switch during digital-to-analog conversions, and scrambling remaining one or more of plurality of DAC elements when generating an output of the DAC. The adaptive DEM may be applied when the DAC input is backed off from full-scale. DNS may be applied in a DAC, by adaptively selecting one or more of a plurality DAC elements in the DAC and switching off the selected one or more of the plurality DAC elements such that the selected one or more of the plurality DAC elements do not contribute to generating an output of the DAC. 1. A method , comprising: selecting one or more of a plurality of DAC elements in the DAC;', 'forcing the selected one or more of the plurality of DAC elements not to switch during digital-to-analog conversion of an input to the DAC; and', 'scrambling remaining one or more of the plurality of DAC elements when generating an output of the DAC that corresponds to the input to the DAC., 'applying adaptive dynamic element matching, in a digital-to-analog converter (DAC), during digital-to-analog conversion, by2. The method of claim 1 , comprising scrambling the remaining one or more of the plurality of DAC elements such that a mismatch error caused thereby does not lead to nonlinear distortion.3. The method of claim 1 , comprising applying the adaptive dynamic element matching when the DAC input is backed off from full-scale.4. The method of claim 1 , comprising controlling the plurality of DAC elements claim 1 , during adaptive dynamic element matching claim 1 , via a switching arrangement comprising one or more switching elements configured for controlling switching of the plurality of DAC elements.5. The ...

Comparator and analog-to-digital converter

Embodiments of the present invention provide a comparator and an analog-to-digital converter. A sampling module, a pre-amplifying module, and a coupling module in the comparator obtain a third differential voltage signal according to a positive input signal and a negative reference signal, and obtain a fourth differential voltage signal according to a negative input signal and a positive reference signal. A latch that is in the comparator and formed by a first P-type field effect transistor, a second P-type field effect transistor, a third field effect transistor, a fourth field effect transistor, a first switch, and a second switch is directly cross-coupled through gates, and directly collects the third differential voltage signal and the fourth differential voltage signal to the gates, so as to drive the latch to start positive feedback.

Delta-sigma modulation apparatus and dynamic element-matching circuit thereof

A delta-sigma modulation apparatus and a dynamic element-matching circuit thereof are disclosed. The dynamic element-matching circuit includes a data aligner, a logic operation circuit, and a delayer. The data aligner receives an input matching data and a pointer signal and shifts the input matching data according to the pointer signal to generate an output matching data. The logic operation circuit receives the output matching data and performs a logic operation on the output matching data to generate a preceding pointer signal. The delayer receives the preceding pointer signal and delays the preceding pointer signal according to a sample clock pulse to generate the pointer signal.

METHODS AND DEVICES FOR STORING PARAMETERS

Methods and devices are provided in which a first parameter partial value (p) is stored in a first memory () and a second parameter partial value (p) is stored in a second memory (). A parameter value (p) of a parameter can then be obtained by combining the first parameter partial value (p) with the second parameter partial value (p). 1. Converter device for analog-to-digital or digital-to-analog conversion , comprising:a first memory for storing a first parameter value,a second memory for storing a second parameter value, wherein the first memory is different than the second memory,wherein the converter device is configured to correct a result of the conversion on the basis of the first parameter value and the second parameter value.2. Converter device according to claim 1 , wherein the first memory is of a different memory type than the second memory.3. Converter device according to claim 2 , wherein the first memory is less sensitive to a corruption of stored data than the second memory.4. Converter device according to any of to claim 2 , wherein the first memory comprises at least one of a hardwired logic and a read-only memory.5. Converter device according to claim 1 , wherein the second memory comprises an electrically programmable read-only memory claim 1 , a flash memory claim 1 , a random excess memory or a register.6. Converter device according to claim 1 , wherein the second memory has a smaller bit width than the first memory.7. Converter device according to claim 1 ,wherein the first parameter value comprises a first parameter partial value of a parameter,wherein the second parameter value comprises a second parameter partial value of the parameter,wherein the converter device comprises a combination unit for combining the first parameter partial value with the second parameter partial value to form a parameter value of the parameter.8. Device according to claim 7 , wherein the converter device comprises a circuit for converting a first digital value ...

POWER ROUTER APPARATUS FOR GENERATING CODE-MODULATED POWERS

A power router apparatus includes: a power divider that divides predetermined power into a plurality of divided powers including first divided power and second divided power; a first code modulator that code-modulates the first divided power with a first modulation code to generate first code-modulated power, which is alternating-current power; and a second code modulator that code-modulates the second divided power with a second modulation code to generate second code-modulated power, which is alternating-current power. 1. A power router apparatus comprising:a power divider that divides predetermined power into a plurality of divided powers including first divided power and second divided power;a first code modulator that code-modulates the first divided power with a first modulation code to generate first code-modulated power, which is alternating-current power; anda second code modulator that code-modulates the second divided power with a second modulation code to generate second code-modulated power, which is alternating-current power.2. The power router apparatus according to claim 1 ,wherein at least one of the first modulation code and the second modulation code includes an orthogonal code.3. The power router apparatus according to claim 1 ,wherein the first code modulator includes a first circuit including a plurality of first switches; andthe second code modulator includes a second circuit including a plurality of second switches.4. The power router apparatus according to claim 1 ,wherein the first code modulator includes a first H-bridge circuit in which four first bidirectional switch circuits are connected in a full-bridge configuration; andthe second code modulator includes a second H-bridge circuit in which four second bidirectional switch circuits are connected in a full-bridge configuration.5. The power router apparatus according to claim 3 ,wherein the first code modulator further includes a first control circuit that generates a plurality of first ...

N-Path Interleaving Analog-to-Digital Converter (ADC) with Background Calibration

A system and method are provided of performing background corrections for an interleaving analog-to-digital converter (ADC). An analog input signal s() is accepted having a first frequency f1 and a bandwidth (BW). A clock at frequency fs creates n sample clocks with evenly spaced phases, each having a sample clock frequency of fs/2. A first tone signal s() is generated at second frequency f2, outside BW. The analog input signal and the first tone signal are combined, creating a combination signal, which is sampled using the sample clocks, creating n digital sample signals per clock period 1/fs. The n digital sample signals are interleaved, creating an interleaved signal. Corrections are applied that minimize errors in the interleaved signal, to obtain a corrected digital output. Errors are determined at an alias frequency f3, associated with the second frequency f2, to obtain correction information for a rotating pair of digital sample signals. 1. A method of performing background corrections for an n-path interleaving analog-to-digital converter (ADC) , the method comprising:{'b': '1', 'i': 't', 'accepting an analog input signal s() having a first frequency f1 and a bandwidth (BW);'}generating a clock having a clock frequency fs;creating n sample clocks with evenly spaced phases, each having a sample clock frequency of fs/n, where n is an integer greater than 2;{'b': '2', 'i': 't', 'generating a first tone signal s() having a predetermined second frequency f2 outside BW;'}combining the analog input signal and the first tone signal, creating a combination signal;sampling the combination signal using the n sample clocks, creating n digital sample signals per clock period 1/fs;interleaving the n digital sample signals, creating an interleaved signal;applying corrections that minimize errors in the interleaved signal to obtain a corrected digital output; and,for a pair of digital sample signals, determining errors at an alias frequency f3, associated with the second ...

ANALOG-TO-DIGITAL DRIVE CIRCUITRY HAVING BUILT-IN TIME GAIN COMPENSATION FUNCTIONALITY FOR ULTRASOUND APPLICATIONS

A time gain compensation (TGC) circuit for an ultrasound device includes a first amplifier having an integrating capacitor and a control circuit configured to generate a TGC control signal that controls an integration time of the integrating capacitor, thereby controlling a gain of the first amplifier. The integration time is an amount of time an input signal is coupled to the first amplifier before the input signal is isolated from the first amplifier. 1. A method of controlling gain in a time gain compensation (TGC) circuit for an ultrasound device , the method comprising:generating, by a control circuit, a TCG control signal to control an integration time of a first integrating capacitor of a first amplifier of the TGC circuit, the integration time comprising an amount of time an input signal is coupled to the first amplifier before the input signal is isolated from the first amplifier.2. The method of claim 1 , wherein the first amplifier comprises a differential amplifier.3. The method of claim 2 , wherein the differential amplifier comprises an analog-to-digital converter (ADC) driver.4. The method of claim 1 , further comprising generating the TGC control signal by comparing an output voltage of a second amplifier and a threshold voltage determined by a value of a variable gain control input signal claim 1 , the second amplifier configured as a comparator circuit and having a feedback capacitor.5. The method of claim 4 , wherein the second amplifier comprises an operational amplifier.6. The method of claim 1 , wherein the integration time controlled by the TGC control signal is dependent upon an RC time constant of the control circuit and a voltage of the variable gain control input signal.7. The method of claim 6 , wherein an output gain of the first amplifier is proportional to a ratio between resistance and capacitance values of the control circuit and resistance and capacitance values of the first amplifier.85. The method of claim 7 , wherein the ratio is ...

Circuit Arrangement, Charge-Redistribution Analog-to-Digital Conversion Circuit, and Method for Controlling a Circuit Arrangement

A circuit arrangement includes charge stores logically arranged in an array configuration having logical columns of charge stores including at least first, second, third and fourth columns of charge stores. A control circuit is configured to control a switching network operably coupled to the charge stores, and to affect a first circuit configuration in a first time segment and a second circuit configuration in a second time segment, the circuit configurations being different from one another. In the first circuit configuration, the first and third columns of charge stores receive a first polarity component of a differential signal, and the second and fourth columns of charge stores receive a second polarity component of the differential signal. In the second circuit configuration, the first and second columns of charge stores receive the first polarity component, and the third and fourth columns of charge stores receive the second polarity component. 1. A circuit arrangement , comprising:a plurality of charge stores logically arranged in an array configuration comprising a plurality of logical columns of charge stores, the plurality of logical columns of charge stores comprising at least a first, a second, a third and a fourth column of charge stores;a switching network operably coupled to the plurality of charge stores; anda control circuit configured to control the switching network so as to affect a first circuit configuration in a first time segment and a second circuit configuration in a second time segment, the first circuit configuration and the second circuit configuration being different from one another,wherein in the first circuit configuration, the first and the third columns of charge stores receive a first polarity component of a differential signal, and the second and the fourth columns of charge stores receive a second polarity component of the differential signal,wherein in the second circuit configuration, the first and the second columns of ...

APPARATUS FOR PROGRAMMABLE INSERTION DELAY TO DELAY CHAIN-BASED TIME TO DIGITAL CIRCUITS

An apparatus for delaying a plurality of chain-based time-to-digital circuits (TDCs). The apparatus includes a plurality of propagation path devices each connected to a respective one of the plurality of TDCs, each propagation path device delays a common start signal by a selectable amount based on a delay selection signal received by the propagation path device, and transmits the delayed start signal to the respective one of the TDCs. 1. A PET system , comprising:a plurality of propagation path devices each connected to a respective one of the plurality of time-to-digital circuits (TDCs), each propagation path device configured to delay a common start signal sent to each propagation path device by a selectable amount based on a delay selection signal received by the propagation path device, and to transmit the delayed start signal to the respective one of the TDCs.2. The system according to claim 1 , wherein each propagation path device includes a plurality of delay modules each providing a different amount delay to the start signal.3. The system according to claim 2 , wherein the plurality of delay modules of each propagation path device are disposed in series between an input receiving the start signal and an output connected to the respective one of the TDCs.4. The system according to claim 2 , wherein each of the plurality of delay modules is activated to receive the start signal based on the delay selection signal.5. The system according to claim 4 , wherein the plurality of delay modules of each propagation path device are disposed in series between an input receiving the start signal and an output connected to the respective TDC and when one of the delay modules is activated by the delay selection signal claim 4 , the start signal bypasses each delay module upstream from the activated delay module and passes though each delay module downstream from the activated delay module.6. The system according to claim 2 , wherein each of the plurality of delay modules ...

Successive-Approximation-Register (SAR) Analog-to-Digital Converter (ADC) Attenuation Capacitor Calibration Method and Apparatus

A fixed capacitor is coupled between a top plate of an attenuation capacitor and a variable voltage reference. The error in the attenuation capacitor may be calibrated out with the variable voltage reference and the fixed correction capacitor. The variable voltage reference varies the charge on the attenuation capacitor and thereby compensates for error(s) therein. A calibration digital-to-analog converter may be used in conjunction with or substituted for the variable voltage reference, and may be programmed for different charge compensation values from the SAR logic during an iterative SAR DAC capacitive switching process.

Front-end circuit and encoder

A preamplifier amplifies signals input to first and second input terminals. A first switching circuit receives first and second input signals and outputs those to the first and second input terminals. A switched capacitor circuit samples two signals amplified by the preamplifier. Differential signals sampled by the switched capacitor circuit are respectively input to third and fourth input terminals of an integration circuit, and the integration circuit outputs differential signals obtained by those input signals to first and second output terminals. A second switching circuit switches a connection relationship between the switched capacitor circuit and the integration circuit. Each time the cycle changes, the first and second switching circuits switch the connection relationships to cause the signals amplified by the preamplifier to be sampled by double correlation sampling.

ADC WITH NOISE-SHAPING SAR

Representative implementations of devices and techniques provide analog to digital conversion of analog inputs. A multistage comparator using a feed-forward technique can provide noise shaping of conversion errors. For example, the comparator may feed a conversion error forward from a first stage to a next stage of the multistage comparator. 1. An apparatus , comprising:a first stage arranged to receive an analog input and to perform a first conversion based on the analog input;a delay component arranged to receive and delay a conversion error of the first conversion, based on a predetermined delay;a combiner arranged to receive an output of the first stage and to combine the output with the error to form an input of a next stage; anda next stage arranged to receive the output of the first stage combined with the error, and to perform a conversion based on the output of the first stage and the error, an output of the next stage resulting in a digital approximation of the analog input.2. The apparatus of claim 1 , further comprising one or more additional next stages arranged to receive the output of the first stage combined with the error claim 1 , and to perform one or more next conversions based on the output of the first stage and the error.3. The apparatus of claim 1 , further comprising one or more sample and hold components arranged to acquire the conversion error of the first conversion and to output the error based on the predetermined delay.4. The apparatus of claim 3 , wherein one or more of the sample and hold components includes one or more capacitances.5. The apparatus of claim 1 , wherein the predetermined delay is based on one or more conversion cycles.6. The apparatus of claim 1 , wherein the first stage and/or the final stage include one or more operational transconductance amplifiers (OTAs).7. The apparatus of claim 6 , wherein at least one of the one or more OTAs comprises a quantity of metal-oxide-semiconductor field-effect transistors (MOSFETs). ...

METHOD AND APPARATUS TO REDUCE EFFECT OF DIELECTRIC ABSORPTION IN SAR ADC

A successive approximation register analog to digital converter (SAR ADC) is provided in which impact of dielectric absorption is reduced with a correction circuit configured to adjust a present digital code value signal based at least in part upon a previous digital code value signal, an acquisition time and temperature. 1. A successive approximation analog to digital converter comprising:a positive digital to analog converter (PDAC) and a negative digital to analog converter (NDAC) configured to provide respective test signals in response to each of multiple analog input signals; andshuffle control switch circuitry configured to shuffle a first capacitor between a coupling of the first capacitor within the PDAC and a coupling of the first capacitor within the NDAC after each conversion by the PDAC and NDAC of a selected one of the analog input signals to the respective test signals.2. The converter of claim 1 , wherein the converter includes a differential comparator claim 1 , further including:a control circuit coupled to receive comparison signals provided from the differential comparator and to provide control signals to cause the shuffle control switch circuitry to shuffle the first capacitor between each conversion by the PDAC and NDAC.3. The converter of claim 1 , wherein the shuffle control switch circuitry is further configured to shuffle a second capacitor between a coupling of the second capacitor within the PDAC and a coupling of the second capacitor within the NDAC after each conversion by the PDAC and NDAC claim 1 , wherein the shuffle control switch circuitry is configured to selectably shuffle the first capacitor and the second capacitor between the PDAC and the NDAC.4. The converter of claim 3 , wherein the PDAC and the NDAC are alternately in:a first coupling state in which the PDAC includes the first capacitor and a third capacitor and the NDAC includes the second capacitor and a fourth capacitor, anda second coupling state in which the PDAC ...

A/D CONVERTER CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT

An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value. 1. An analog-to-digital converter circuit that converts an analog input signal into a digital quantity comprising:an analog-to-digital converter unit that converts the analog input signal into a pre-correction digital value; anda corrector unit that digitally corrects the pre-correction digital value output from the analog-to-digital converter unit,wherein the corrector unit includes:a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the analog-to-digital converter unit and summing them, anda weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.2. The analog-to-digital converter circuit according to claim 1 ,wherein the weighting coefficient search unit ...

Segmented Digital-To-Analog Converter With Overlapping Segments

In one embodiment, a segmented digital-to-analog converter (DAC) has two configurations (i.e., sub-DACs) with overlapping operating ranges and a data mapper that maps the digital input signal into two different digital signals, one for each sub-DAC. The currents generated by the sub-DACs are combined and then used to generate the corresponding analog output signal. Because the sub-DACs have overlapping operating ranges, the DAC can be calibrated to account for process variations that result in the actual current ratio between the two sub-DACs being different from the ideal, designed current ratio. Calibration algorithms generate calibration constants that are applied by the data mapper when mapping the digital input signal into the two digital signals respectively applied to the two sub-DACs. In this way, high-precision DACs can be implemented without requiring expensive circuitry to handle undesirable current mismatch resulting from process variations. 1. A segmented digital-to-analog converter for converting a digital input signal into an analog output signal , the converter comprising:a first sub-converter capable of generating a first sub-converter range of possible analog signal magnitudes and configured to convert a first digital signal, based on the digital input signal, into a first analog signal within the first range;a second sub-converter capable of generating a second sub-converter range of possible analog signal magnitudes and configured to convert a second digital signal, based on the digital input signal, into a second analog signal within the second sub-converter range, wherein the second sub-converter range overlaps with the first sub-converter range; anda combiner configured to combine the first and second analog signals to generate the analog output signal.2. The converter of claim 1 , wherein:the first sub-converter is capable of generating a smallest non-zero value of the first analog signal;the second sub-converter is capable of generating a ...

ANALOG TO DIGITAL CONVERSION CIRCUIT

During a period of calibration of the ADC, the effect of unexpected external noise can be excluded. 1. An analog to digital convertor comprising:an AD conversion circuit that converts an analog value of an input signal into a digital value and outputs a converted value; andan averaging circuit that calculates a correction value by a calibration operation,wherein the converted value is corrected using the correction value and a converted value after the correction is output,wherein an elemental correction value on the basis of a converted value by the AD conversion circuit corresponding to a predetermined analog value is supplied to the averaging circuit a plurality of times in the calibration operation, andwherein the averaging circuit calculates the average value of the remaining elemental correction values obtained by removing, at least, the maximum value and the minimum value from the elemental correction values supplied a plurality of times, and calculates the correction value on the basis of the average value in the calibration operation.2. The analog to digital convertor according to claim 1 ,wherein the AD conversion circuit is an L-bit sequential comparison-type AD conversion circuit (K and L are positive integers equal to or larger than 2 and 3, respectively) that includes a first capacitor to which a first capacitance value is set as a design value, second to K-th capacitors to each of which a capacitance value equal to one over a power of 2 of the first capacitance value is sequentially set as a design value, and a K+1-th capacitor to which a capacitance value same as that of the K-th capacitor is set as a design value,wherein the capacitance value of the K+1-th capacitor can be set using a digital value of L−K bits in a range where the design value is the maximum value as the effective capacitance,wherein the converted value of the predetermined analog value in the calibration operation is a difference value between digital values converted from the ...

Verification, Validation, And Applications Support For Analog-To-Digital Converter Systems

A microcontroller includes an analog-to-digital (ADC) controller circuit, an ADC converter circuit, and a multiplexer configured to multiplex output of the ADC converter circuit and a data source to the ADC controller circuit. 1. An analog-to-digital (ADC) converter , comprising:an ADC controller circuit;an ADC converter circuit; anda multiplexer configured to multiplex output of the ADC converter circuit and a first data source to the ADC controller circuit.2. The ADC of claim 1 , wherein the multiplexer is further configured to further multiplex output of a second data source with the output of the ADC converter circuit and the first data source.3. The ADC of claim 1 , wherein the first data source includes emulated data.4. The ADC of claim 1 , wherein the multiplexer is configured to select output of the first data source to the ADC controller circuit when the ADC converter is in a debug mode.5. The ADC of claim 4 , wherein in the debug mode the multiplexer may be configured to output data emulating response of the ADC converter circuit.6. The ADC of claim 1 , wherein the multiplexer is configured to select output of the ADC converter circuit to the ADC controller circuit when the ADC converter is in a conversion mode.7. The ADC of claim 6 , wherein the multiplexer is configured to select output of the ADC converter circuit to the ADC controller circuit when the ADC converter is in a conversion mode.8. The ADC of claim 1 , wherein the first data source is a memory including data emulating operation of the ADC converter.9. The ADC of claim 1 , wherein the first data source is an input for receiving externally emulated data emulating operation of the ADC converter.10. The ADC of claim 1 , further comprising an input to receive a determination of which of the ADC converter circuit and the first data source are to be routed to the ADC controller circuit.11. A microcontroller claim 1 , comprising:an analog-to-digital (ADC) controller circuit;an ADC converter circuit; ...

DIGITAL-TO-ANALOG CONVERSION CIRCUIT

A digital-to-analog conversion circuit includes an operational amplification module having an operational amplifier connected to an output transistor to form a negative feedback circuit to obtain equal voltages at positive and negative ends. A negative end current flowing into the negative end is proportional to a positive end current flowing into the positive end. An input end of a conversion module is connected in parallel with a first resistor of the operational amplification module to obtain the same voltage as the first resistor, and an analog current proportional to the negative end current and positive end current. An output end of the conversion module is connected with the source of the output transistor and configured to receive the analog current and to make the analog current flow to an output resistor via the drain of the output transistor, to obtain an output current proportional to the positive end current. 1. A digital-to-analog conversion circuit , comprising: an operational amplification module and a conversion module;the operational amplification module comprises an operational amplifier, an output transistor and a first resistor;an output end of the operational amplifier is connected with the gate of the output transistor, a negative end of the operational amplifier is connected with the source of the output transistor, and voltage at the negative end is supplemented based on the voltage supplied by the source of the output transistor, so that voltages at positive and negative ends are equal, as well as a negative end current flowing into the negative end is proportional to a positive end current flowing into the positive end; andthe conversion module is configured to convert digital signals to an analog current; and an input end of the conversion module is connected with a first end of the first resistor of the operational amplification module, and an output end of the conversion module is connected with a second end of the first resistor of the ...

SUCCESSIVE APPROXIMATION DIGITAL VOLTAGE REGULATION METHODS, DEVICES AND SYSTEMS

A low power voltage regulator includes a weighted transistor array having a plurality of transistor switches with a total conductance of G, corresponding to bits from a MSB to LSB. A transistor switch corresponding to the MSB has a conductance of G/2 and remaining bits have a consecutive descending conductance of G/2to the LSB, and search time takes a low number of cycles by starting with the MSB. A redundant LSB transistor switch has the same G/2conductance of the LSB. The redundant LSB is used to correct steady-state errors, and a proportional derivative controller compensates output voltage. The compensation in a method eliminates an output pole of the voltage regulator to provide a stable voltage regulator operation irrespective of load current, load capacitance, or sampling frequency. Voltage can be regulated via the additional LSB below the resolution limit via pulse width modulation. 1. A low power voltage regulator , comprising:{'sup': N', 'N, 'a weighted transistor array having a plurality of transistor switches with a total conductance of G, the switches corresponding to bits ranging from a most significant bit (MSB) to a least significant bit (LSB), a transistor switch corresponding to the MSB having a conductance of G/2 and remaining bits having a consecutive descending conductance of G/2to the LSB, and further including a redundant LSB transistor switch having the same G/2conductance of the LSB;'}a search controller that conducts a binary search by turning on respective ones of the plurality of transistor switches beginning with the MSB to find a total conductance value of said weighed transistor array that realizes the nearest output voltage to a desired target output voltage;a LSB controller to enable the redundant LSB transistor in response to steady-state errors;an overshoot controller that interrupts the search controller in response to voltage or current step changes that are large enough to cause predetermined amounts of overshoot or undershoot; ...

DELAY-FREE POLY-PHASE QUANTIZER AND QUANTIZATION METHOD FOR PWM MISMATCH SHAPING

A system and method for pulse-width modulation (PWM) mismatch shaping. The method includes receiving a multi-bit pulse-code modulated (PCM) signal and generating a voltage ramp signal. The method includes generating a first corrected signal based on a first feedback signal and the multi-bit PCM signal. The method includes generating a first single-bit PWM signal based on the first corrected signal and the voltage ramp signal. The method includes delaying the voltage-ramp signal and generating a second corrected signal based on a second feedback signal and the multi-bit PCM signal. The method includes generating a second single-bit PWM signal based on the second corrected signal and the delayed voltage ramp signal and generating a multi-bit pulse-density modulation (PDM) signal based on the first single-bit PWM signal and the second single-bit PWM signal. 1. A delta-sigma modulator for pulse-width modulation (PWM) mismatch shaping , the delta-sigma modulator comprising:a first PWM modulator having a first input terminal, a second input terminal, and an output terminal;a voltage ramp generator having an output terminal coupled to the second input terminal of the first PWM modulator;a first delay element having an input terminal and an output terminal, the input terminal of the first delay element being coupled to the output terminal of the voltage ramp generator; anda second PWM modulator having a first input terminal coupled to the first input terminal of the first PWM modulator, a second input terminal, and an output terminal, the second input terminal of the second PWM modulator being coupled to the output terminal of the first delay element; anda loop filter having a first input terminal, a second input terminal, and an output terminal, the output terminal of the loop filter coupled to the first input terminal of the first PWM modulator and to the first input terminal of the second PWM modulator.2. (canceled)3. The delta-sigma modulator of claim 1 , wherein the ...

ANALOG TO DIGITAL CONVERSION CIRCUIT

An analog to digital (AD) converter includes an AD conversion circuit, and a calibration circuit that calibrates an output value of the AD conversion circuit. The calibration circuit includes a right-shift circuit that shifts an accumulated value of values obtained by removing a deviated value from a plurality of output values of the AD conversion circuit. The calibration circuit calibrates the output value of the AD conversion circuit based on the shifted value. 1. An analog to digital (AD) converter , comprising:an AD conversion circuit; anda calibration circuit that calibrates an output value of the AD conversion circuit, 'a right-shift circuit that shifts an accumulated value of values obtained by removing a deviated value from a plurality of output values of the AD conversion circuit, and', 'wherein the calibration circuit compriseswherein the calibration circuit calibrates the output value of the AD conversion circuit based on the shifted value.2. The AD converter according to claim 1 , further comprising an accumulation circuit that accumulates the plurality of output values of the AD conversion circuit claim 1 ,wherein the right-shift circuit shifts a value obtained by subtracting the deviated value from the accumulated value.3. The AD converter according to claim 1 , further comprising an accumulation circuit that accumulates values obtained by removing the deviated value from the plurality of output values of the AD conversion circuit claim 1 ,wherein the right-shift circuit shifts the accumulated value.4. The AD converter according to claim 1 , wherein the deviated value includes at least one of a maximum value and a minimum value of the plurality of output values of the AD conversion circuit.5. The AD converter according to claim 2 , wherein the deviated value includes at least one of a maximum value and a minimum value of the plurality of output values of the AD conversion circuit.6. The AD converter according to claim 3 , wherein the deviated value ...

PARAMETER CORRECTION FOR CASCADED SIGNAL COMPONENTS

Various examples are directed to systems and methods for providing correction to cascaded signal components. A correction signal may be applied to multiple signal components in a set of cascaded signal components. 1. A system , comprising: a first signal input;', 'a first signal output; and', 'a first correction input;, 'a first signal component comprisinga first digital-to-analog converter (DAC) comprising a first DAC input and a first DAC output coupled to the first correction input; a second signal input electrically coupled to the first signal output;', 'a second signal output; and', 'a second correction input;, 'a second signal component comprisinga second DAC comprising a second DAC input and a second DAC output coupled to the second correction input; and send a first correction signal for the first signal component to the first DAC input; and', 'send a second correction signal for the second signal component to the second DAC input., 'a correction controller configured to2. The system of claim 1 , further comprising a communication bus electrically coupling the correction controller claim 1 , the first DAC input and the second DAC input claim 1 , wherein the communication bus comprises a data line claim 1 , a clock line claim 1 , and a write enable.3. The system of claim 1 , wherein the first signal component comprises an amplifier having a gain claim 1 , and wherein the first correction signal affects the gain of the amplifier.4. The system of claim 1 , wherein the first signal component comprises a buffer and the second signal component comprises a buffer.5. The system of claim 1 , wherein the first signal component comprises a differential buffer claim 1 , wherein the first signal output comprises a positive side output and a negative side output claim 1 , wherein the differential buffer comprises a supplemental current source claim 1 , and wherein the first DAC is configured to:receive the first correction signal; andsend, to the first correction input, ...

Dynamic Range Extension of Analog-to-Digital Converters

A method and system for extending the dynamic range of non-discontinuous analog data. 1. A method of extending the dynamic range of analog to digital converters , comprising:inputting a signalconvening said signal to voltageconverting the signal from analog to digital while wrapping the digital signal, andevaluating the signal for large differences between samples, wherein said differences are unwrapped to produce signals with increased bit depth and extending the signal dynamic range without clipping.2. The method of claim 1 , wherein the differences between samples are reduced. This Application claims the benefit of U.S. Provisional Application No. 62/297,191, entitled “Dynamic Range Extension of Analog-to-digital Converters” filed Feb. 19, 2016 which is hereby incorporated by reference.Many digital devices, such as analog-to-digital converters (ADCs), digital signal processors, and scientific instruments have bit depth limits. This allows for reduced computational demands and improved device performance, but results in limiting the size of functions or signals devices can represent. For example, limited bit depths are problematic in ADCs used for audio recording because overflow of the audio signal results in sound distortion. Attempts to solve this problem have included increasing the sample rate or utilizing interleaved or stacked ADCs, but these solutions come with increased cost, labor, and space requirements.A method that extends the dynamic range of devices with limited bit depth by recovering wrapped signals solves the issue described above. Such method and related opportunities are included in this disclosure.In one embodiment, the present invention provides a method of extending the dynamic range of an analog-to-digital conversion while preserving the overall quality of the signal. The process of the present invention uses an algorithm to locate signal wrapping and restore the waveform, allowing for extended dynamic range and/or increased resolution. ...

DIGITAL-TO-ANALOG CONVERTER WITH CORRECTION FOR PARASITIC ROUTING RESISTANCE

An embodiment of a digital-to-analog converter circuit includes a resistor network connected to an output node, a switch network having a first plurality of switches connecting the resistor network to a first circuit node and a second plurality of switches connecting the resistor network to a second circuit node, a voltage reference to supply a reference voltage to the first circuit node, and a current generator connected to the first circuit node and the second circuit node, to generate a compensation current, draw the compensation current from the first circuit node, and supply the compensation current to the second circuit node. The current generator can generate the compensation current as a function of a current or a voltage of a component of the voltage reference or as a function of an analog output voltage produced at the output node. 1. A digital-to-analog converter (DAC) circuit , comprising:a resistor network connected to an output node;a switch network having a first plurality of switches connecting the resistor network to a first circuit node and a second plurality of switches connecting the resistor network to a second circuit node;a voltage reference to supply a reference voltage to the first circuit node; anda current generator connected to the first circuit node and the second circuit node, to generate a compensation current, draw the compensation current from the first circuit node, and supply the compensation current to the second circuit node.2. The DAC circuit of claim 1 , wherein the current generator generates the compensation current as a function of the at least one of a current or a voltage of a component of the voltage reference.3. The DAC circuit of claim 1 , wherein the current generator generates the compensation current as a function of an analog output voltage produced at the output node and corresponding to a conversion of a digital input received by the DAC circuit to the analog domain.4. The DAC circuit of claim 1 , wherein the ...

ANALOG TO DIGITAL CONVERTER DEVICE AND METHOD OF CALIBRATING CLOCK SKEW

An analog to digital converter (ADC) device includes ADC circuitries, a calibration circuitry, and a skew adjustment circuitry. The ADC circuitries are configured to convert an input signal according to interleaved clock signals, in order to generate first quantization outputs. The calibration circuitry is configured to perform at least one calibration operation according to the first quantization outputs, in order to generate second quantization outputs. The skew adjustment circuitry is configured to determine maximum value signals, to which the second quantization outputs respectively correspond during a predetermined interval, and to average the maximum value signals to generate a reference signal, and to compare the reference signal with each of the maximum value signals to generate adjustment signals, in order to reduce a clock skew of the ADC circuitries. 1. An analog to digital converter device , comprising:a plurality of analog to digital converter circuitries configured to convert an input signal according to a plurality of interleaved clock signals, in order to generate a plurality of first quantization outputs;a calibration circuitry configured to perform at least one calibration operation according to the plurality of first quantization outputs, in order to generate a plurality of second quantization outputs; anda skew adjustment circuitry configured to determine a plurality of maximum value signals, to which the plurality of second quantization outputs respectively correspond during a predetermined interval, and to average the plurality of maximum value signals to generate a reference signal, and to compare the reference signal with each of the plurality of maximum value signals to generate a plurality of adjustment signals, in order to reduce a clock skew of the plurality of analog to digital converter circuitries.2. The analog to digital converter device of claim 1 , wherein the skew adjustment circuitry is configured to find an absolute value of each ...

A/D CONVERTER CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT

An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value. 1. An analog-to-digital converter circuit that converts an analog input signal into a digital quantity comprising:an analog-to-digital converter unit that converts the analog input signal into a pre-correction digital value; anda corrector unit that digitally corrects the pre-correction digital value,wherein the corrector unit includes:a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying weighting coefficients provided for each bit by each bit of the pre-correction digital value and summing them, anda search vector generator unit that generates search vectors based on each bit of the pre-correction digital value and an approximate value of each bit of the pre-correction digital value, andan error signal generator unit that calculates error signals based on the post-correction digital value and an approximate value of the post-correction digital value, anda weighting coefficient search unit that searches for the weighting coefficients ...

Distributed Gain Stage for High Speed High Resolution Pipeline Analog to Digital Converters

In an embodiment, multiple MDAC stages are coupled in parallel to form an MDAC having the desired gain and capacitor size. Each stage may include capacitors and an OTA that are much smaller than the corresponding capacitors and OTA would be for a large single stage. Interconnect for each stage may be shorter than the single stage case, and thus the parasitic resistance and capacitance may be lower. Power consumption may be reduced, and performance of the amplifier may be increased, due to the reduced parasitic resistance and capacitance. The area occupied by the circuitry may be lower as well. Process variation within a given stage may be lower. The process variation between stages may induce noise in the output, but the parallel connection of the stages may serve to reduce the noise, in some embodiments.

Successive approximation register analog-to-digital converter and associated control method

A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) is disclosed. The SAR ADC includes a switched capacitor array, a buffer, a comparator and a control logic circuit. The switched capacitor array is arranged to sample an input signal according to a switch control signal to generate a sampling signal. The buffer is arranged to generate a common mode voltage. The comparator is arranged to receive the sampling signal and the common mode voltage in order to generate a comparison result. The control logic circuit is arranged to generate an output signal according to the comparison result, and generate the switch control signal to control the switched capacitor array. The control logic circuit further generates an operation control signal to adjust a Miller compensation capacitor inside the buffer. An associated control method is also disclosed.

Temperature measurement system

A temperature measurement system is disclosed. In accordance with some embodiments of the present disclosure, a temperature measurement system may comprise a resistor, a thermistor, a resistance-to-current converter configured to generate a current signal based on a resistance, an analog-to-digital converter (ADC) configured to receive a first current signal based on the resistor, convert the first current signal into a first digital signal, receive a second current signal based on the thermistor, and convert the second current signal into a second digital signal, and a calculation stage communicatively coupled to an ADC output and configured to determine a first digital value based on the first digital signal, determine a second digital value based on the second digital signal, calculate a resistance ratio based on the first digital value and the second digital value, and determine a temperature output value based on the resistance ratio.

METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS (ADCS)

An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision. 120-. (canceled)21. An analog-to-digital converter (ADC) , comprising:a comparator comprising an analog input, a reference input, a preemption input, a codeword output, and a validation output, wherein the validation output indicates a valid decision and the codeword output indicates a comparison between the analog input and the reference input when a preemption is not indicated at the preemption input;a digital-to-analog converter (DAC) comprising a codeword input and a reference output, wherein the reference output of the DAC is operably coupled to the reference input of the comparator and the codeword input of the DAC is operably coupled to the codeword output of the comparator; anda timer operable to set a preemption output in time according to a validation input, wherein the validation input of the timer is operably coupled to the validation output of the comparator and the preemption output of the timer is operably coupled to the preemption input of the comparator.22. The ADC according to claim 21 , wherein the comparator is operable to ...

Analog-to-digital conversion

An analog-to-digital conversion apparatus 10 comprises a plurality of analog-to-digital converters 30 and a ramp generator 20 . Each of the analog-to-digital converters 30 comprises an analog signal input for receiving an analog signal level and a ramp signal input. A control stage is arranged to compare the ramp signal with the analog signal level and, based on the comparison, to enable a counter provided at the analog-to-digital converter or to latch a digital value received from a counter. The control stage comprises a comparator in the form of a first differential amplifier with a first branch connected to the input for receiving the ramp signal, a second branch connected to the analog signal input and an output, and a biasing current source for biasing the first differential amplifier. A feedback circuit controls the biasing current source. The feedback circuit comprises a second differential amplifier OP 1 with a first input connected to a node 46 on the first branch and a second input connected to a reference voltage VB such that the node on the first branch is maintained at a substantially constant voltage.

ANALOG TO DIGITAL CONVERSION CIRCUIT

An analog-to-digital (AD) convertor includes: a capacitance digital-to-analog (DA) convertor circuit; a comparator circuit coupled to the capacitance DA convertor circuit; and a calibration circuit that calculates a correction value for the AD convertor, wherein the capacitance DA convertor circuit includes a first capacitor, a second capacitor, n number of capacitors (n being integer equal to or larger than 3), each of the capacitors from first to n-th to be activated based on input digital data, wherein each of the first and second capacitors is designed for having a first capacitance value, wherein the n-th capacitor is designed for having twice the capacitance value of the (n−1)-th capacitor, wherein the calibration circuit calculates the correction value based on first and second results of the AD convertor, and wherein the first result is generated using the n-th capacitor and the second result is generated using the capacitors from first to (n−1)-th.

ADAPTIVE CONFIGURATION TO ACHIEVE LOW NOISE AND LOW DISTORTION IN AN ANALOG SYSTEM

Noise and distortion reduction in a signal processed through analog circuitry includes providing noise reduction circuitry to reduce signal noise generated by at least one analog circuit element. The noise reduction circuitry is adaptively configured to adjust a rate to apply noise reduction to the signal without introducing unwanted distortion. Distortion reduction circuitry is adaptively configured to adjust a rate to apply distortion reduction to the signal without introducing unwanted noise. The signal is processed through the analog circuitry using the adaptively configured noise reduction circuitry and adaptively configured distortion reduction circuitry to reduce both noise and distortion in the signal. 1. A method for reducing noise in a signal processed through analog circuitry , the method comprising:providing noise reduction circuitry to reduce signal noise generated by at least one analog circuit element;setting a first noise threshold associated with the analog circuit element, the first noise threshold approximating an amplitude of the signal above which noise reduction generates unacceptable signal distortion;adaptively configuring the noise reduction circuitry based on a comparison of the amplitude of the signal and the first noise threshold by adjusting a rate to apply noise reduction to the signal; andprocessing the signal through the analog circuitry using the adaptively configured noise reduction circuitry to reduce noise in the signal.2. The method of claim 1 , wherein the noise reduction circuitry comprises chopping circuitry and adaptively configuring the noise reduction circuitry comprises reducing a chopping rate if the signal amplitude is greater than the first noise threshold.3. The method of claim 1 , wherein if the amplitude is greater than the first noise threshold claim 1 , adaptively configuring the noise reduction circuitry comprises stopping the application of the noise reduction for the signal.4. The method of claim 1 , further ...

Extensible environmental data collection pack

An environmental data collection system includes a controller and one or more smart sensors coupled to the controller, each smart sensor comprising a memory, the memory configured to store configuration and calibration data for each data channel output by sensing devices of the smart sensors.

Signal processing system using analog-to-digital converter with digital-to-analog converter circuits operating in different voltage domains and employing mismatch error shaping technique and associated signal processing method

A signal processing system includes an analog-to-digital converter (ADC) that is used to convert a first analog value into a first digital value and convert a second analog value into a second digital value. The ADC includes a first digital-to-analog converter (DAC) circuit and a second DAC circuit operating in different voltage domains. A first bit segment and a second bit segment of each digital value are determined via the first DAC circuit and the second DAC circuit, respectively. An analog injection value is injected to the second analog value, the analog injection value is converted from a digital injection value formed by a subset of bits of the second bit segment of the first digital value, and the second bit segment of the second digital value is derived from injecting the digital injection value to a digital value determined by the second DAC circuit.

METHODS AND DEVICES FOR STORING PARAMETERS

Methods and devices are provided in which a first parameter partial value (p) is stored in a first memory () and a second parameter partial value (p) is stored in a second memory (). A parameter value (p) of a parameter can then be obtained by combining the first parameter partial value (p) with the second parameter partial value (p). 1. Converter device for analog-to-digital or digital-to-analog conversion , comprising:a first memory for storing a first parameter value,a second memory for storing a second parameter value, wherein the first memory is different than the second memory,wherein the converter device is configured to correct a result of the conversion on the basis of the first parameter value and the second parameter value.2. Converter device according to claim 1 , wherein the first memory is of a different memory type than the second memory.3. Converter device according to claim 2 , wherein the first memory is less sensitive to a corruption of stored data than the second memory.4. Converter device according to any of to claim 2 , wherein the first memory comprises at least one of a hardwired logic and a read-only memory.5. Converter device according to claim 1 , wherein the second memory comprises an electrically programmable read-only memory claim 1 , a flash memory claim 1 , a random excess memory or a register.6. Converter device according to claim 1 , wherein the second memory has a smaller bit width than the first memory.7. Converter device according to claim 1 ,wherein the first parameter value comprises a first parameter partial value of a parameter,wherein the second parameter value comprises a second parameter partial value of the parameter,wherein the converter device comprises a combination unit for combining the first parameter partial value with the second parameter partial value to form a parameter value of the parameter.8. Device according to claim 7 , wherein the converter device comprises a circuit for converting a first digital value ...

COLUMN A/D CONVERTER, COLUMN A/D CONVERSION METHOD, SOLID IMAGING DEVICE, AND CAMERA SYSTEM

The present invention relates to a column A/D converter, column A/D conversion method, imaging device, and camera system that can reduce the amount of IR drop by dispersing the current consumed during the count operation, mitigate the counter characteristic degradation, readily reduce the amount of fluctuation in the power source voltage, and achieve operation at a low power source voltage. The column A/D converter includes a plurality of column processing units including an A/D conversion function, a plurality of counters configured to generate digital codes in response to a reference clock and arranged corresponding to each or a set of the column processing units, and a count start offset unit configured to trigger a pseudo count operation in each of the counters and to offset a count start code for at least two or more counters among the plurality of counters before the reference clock is supplied to the counters. 1. A column A/D converter comprising:a plurality of column processing units including an analog-digital (A/D) conversion function to convert analog signals into digital signals;a plurality of counters configured to generate digital codes in response to a reference clock and arranged corresponding to each or a set of the columns; anda count start offset unit configured to trigger a pseudo count operation in each of the counters and to offset a count start code for at least two or more counters among the plurality of counters before the reference clock is supplied to the counters.2. The column A/D converter according to claim 1 ,wherein the count start offset unit inputs a code offset pulse with a different pulse value into each counter before the reference clock is supplied to the counters.3. The column A/D converter according to claim 1 ,wherein the count start offset unit includes a logical circuit configured to select the reference clock and the code offset pulse and to input the selected reference clock and code offset pulse into the counters.4. The ...

METHODS AND APPARATUS TO REDUCE NON-LINEARITY IN ANALOG TO DIGITAL CONVERTERS

Methods and apparatus for reducing non-linearity in analog to digital converters are disclosed. An example apparatus includes an analog-to-digital converter to convert an analog signal into a digital signal; and a non-linearity corrector coupled to the analog-to-digital converter to determine a derivative of the digital signal; determine cross terms including a combination of the digital signal and the derivative of the digital signal; and determine a non-linearity term corresponding to a combination of the cross terms. 1. An apparatus comprising:an analog-to-digital converter to convert an analog signal into a digital signal; and determine a derivative of the digital signal;', 'determine cross terms including a combination of the digital signal and the derivative of the digital signal; and', 'determine a non-linearity term corresponding to the cross terms., 'a non-linearity corrector coupled to the analog-to-digital converter to2. The apparatus of claim 1 , further including a summer coupled to the non-linearity corrector to combine the non-linearity term with the digital signal.3. The apparatus of claim 2 , wherein combining the non-linearity term with the digital signal reduces non-linearity of the digital signal.4. The apparatus of claim 1 , wherein the non-linearity corrector is to determine Volterra terms of the digital signal claim 1 , the determining of the non-linearity term further corresponding to the Volterra terms.5. The apparatus of claim 4 , wherein the non-linearity corrector is to scale the cross terms and the Volterra terms by first non-linearity coefficients corresponding to characteristics of the analog-to-digital converter.6. The apparatus of claim 4 , wherein the digital signal includes a first signal corresponding to first samples at first points in time and a second signal corresponding to second samples at second points in time different from the first points in time.7. The apparatus of claim 6 , wherein the analog-to-digital converter is an ...

A/D CONVERTER CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT

An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value. 1. An analog-to-digital converter circuit that converts an analog input signal into a digital quantity comprising:an analog-to-digital converter unit that converts the analog input signal into a pre-correction digital value; anda corrector unit that digitally corrects the pre-correction digital value output from the analog-to-digital converter unit,wherein the corrector unit includes:a storage device that stores a first pre-correction digital value output from the analog-to-digital converter unit;a first weighting coefficient multiplier unit that outputs a first post-correction digital value obtained by multiplying a weighting coefficient by each bit of the first pre-correction value and summing them; anda weighting coefficient search unit that searches for a weighting coefficient so as to minimize an error signal generated based on the first post-correction digital value and an approximate value for the first post-correction digital value, anda second weighting coefficient multiplier ...

LOCALIZED DYNAMIC ELEMENT MATCHING AND DYNAMIC NOISE SCALING IN DIGITAL-TO-ANALOG CONVERTERS (DACS)

Methods and systems are provided for controlling operations of digital-to-analog converters (DACs), particularly ones comprising multiple DAC elements. In particular, a plurality of DAC elements in a digital-to-analog converter (DAC) may be controlled during digital-to-analog conversions, with the controlling comprising use of a switching arrangement that comprises one or more switching elements configured for controlling switching of each of the plurality of DAC elements. The controlling may comprise forcing one or more of the plurality of DAC elements in the DAC to not switch during the digital-to-analog conversions. Further, the remaining DAC elements may be scrambled. The controlling of the plurality of DAC elements in the DAC may be based on analysis of an input to the DAC that is being converted. The analysis may comprise determining when the input is backed off from full-scale. A switching sequence may be applied, via each of the one or more switching elements. 134-. (canceled)35. A method , comprising: controlling a plurality of DAC elements in said DAC during digital-to-analog conversion of an input to said DAC;', 'wherein said controlling comprises using a switching arrangement that comprises one or more switching elements configured for controlling switching of each of said plurality of DAC elements., 'in a digital-to-analog converter (DAC)36. The method of claim 35 , wherein said controlling comprises forcing one or more of said plurality of DAC elements in said DAC to not switch during the digital-to-analog conversion of said input to said DAC.37. The method of claim 36 , comprising scrambling a remaining one or more of said plurality of DAC elements.38. The method of claim 35 , comprising controlling said plurality of DAC elements in said DAC based on analysis of said input to said DAC.39. The method of claim 38 , wherein said analysis comprises determining when said input to said DAC is backed off from full-scale.40. The method of claim 35 , ...

AMPLIFIER CALIBRATION

A device includes an amplifier and calibration circuitry coupled to the amplifier. The calibration circuitry is configured to receive calibration values. The calibration circuitry is also configured to generate an output value in response to receiving a timing input. 1. A device comprising:an amplifier having first and second primary differential inputs, -and first and second auxiliary differential inputs, and an output;conversion circuitry configured to generate calibration values based on the output of the amplifier; andcalibration circuitry configured to generate an output value based on the calibration values in response to a timing input and to provide a compensation signal that is based on the output value to one of the auxiliary differential inputs of the amplifier.2. The device of claim 1 , the output value corresponding to a sum of calibration values divided by a particular value.3. The device of claim 2 , wherein the particular value corresponds to a number of calibration cycles.4. The device of claim 1 , wherein the calibration circuitry comprises:an accumulator configured store a sum of calibration values; anda divider configured to generate the output value by dividing the sum of calibration values by a particular value.5. The device of claim 1 , wherein receipt of the timing input indicates that a count of the calibration values corresponds to a number of calibration cycles.6. The device of claim 5 , wherein claim 5 , during a calibration mode claim 5 , the amplifier is connected to the calibration circuitry and disconnected from other circuitry.7. The device of claim 1 , wherein the conversion circuitry comprises a successive approximation register configured to provide the calibration values to the calibration circuitry.8. The device of claim 1 , wherein the conversion circuitry comprises an automatic offset voltage compensation circuit configured to provide the calibration values to the calibration circuitry.9. The device of claim 1 , wherein the ...

ANALOG-TO-DIGITAL DRIVE CIRCUITRY HAVING BUILT-IN TIME GAIN COMPENSATION FUNCTIONALITY FOR ULTRASOUND APPLICATIONS

A time gain compensation (TGC) circuit for an ultrasound device includes a first amplifier having an integrating capacitor and a control circuit configured to generate a TGC control signal that controls an integration time of the integrating capacitor, thereby controlling a gain of the first amplifier. The integration time is an amount of time an input signal is coupled to the first amplifier before the input signal is isolated from the first amplifier. 1. An ultrasound system , comprising:an analog-to-digital converter (ADC) driver circuit configured to provide time gain compensation (TGC) and including a first amplifier having an integrating capacitor in a feedback configuration; anda control circuit configured to generate a TGC control signal that controls an integration time of the integrating capacitor, the integration time comprising an amount of time that an input signal is coupled to the first amplifier before the input signal is isolated from the first amplifier.2. The ultrasound system of claim 1 , wherein the ADC driver circuit further comprises:an ADC sample and hold capacitor selectively coupled to an output terminal of the first amplifier;an offset voltage capacitor coupled to an input terminal of the first amplifier;a first switch configured to discharge the integrating capacitor during a reset mode of operation;a second switch configured to couple the input signal to the first amplifier following the reset mode of operation, and to thereafter isolate the input signal from the first amplifier according to the TGC control signal, the second switch also configured to couple the input signal to the offset voltage capacitor during an offset cancellation mode of operation;a third switch configured to equalize the input and output terminals of the first amplifier during the offset cancellation mode; anda fourth switch configured to couple the output terminal of the first amplifier to the ADC sample and hold capacitor during a sample mode of operation.3. The ...

METHOD FOR DIGITAL ERROR CORRECTION FOR BINARY SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER (ADC)

An analog input voltage is converted to a digital code by, generating a first set of confirmed bits based on a first series of comparisons of an output of a digital-to-analog converter with the analog input voltage and generating a second set of confirmed bits based on a second series of comparisons of the output of the digital-to-analog converter with the analog input voltage. The first set of confirmed bits is independent of the second series of comparisons. The bits of the digital output code corresponding to the analog input voltage are generated based on the first set of confirmed bits, the second set of confirmed bits and a constant value representative of a voltage shift introduced in the digital-to-analog converter between the first series of comparisons and the second series of comparisons. 1. A method , comprising:generating, using control logic, a first binary code having M+1 bits, M being an integer greater than 1;generating, using the control logic, a second binary code having N−M+1 bits, N being an integer greater than M;carrying out a first binary decision using successive approximation register (SAR) processing on the bits of the first binary code by a first digital to analog conversion block of an analog to digital converter to generate a first voltage to be compared, using a comparator, with an input voltage to be converted;generating a first segment of M+1 confirmed bits based on the comparison of the first voltage with the input voltage;carrying out a second binary decision using SAR processing on the bits of the second binary code by a second digital to analog conversion block of the analog to digital converter to generate a second voltage to be compared with said input voltage;generating a second segment of N−M+1 confirmed bits based on the comparison of the second voltage with the input voltage, wherein the first segment of M+1 confirmed bits do not change based on the second binary decision processing or the second segment of confirmed bits; ...

Analog to digital acquisition eliminating uncertainty of level test in high noise environments

A method of determining the quality of a sensed signal has capturing, comparing, categorizing, and a decision-making steps. The capturing step is used to capture a plurality of signals. A magnitude of each of the plurality of signals is compared to a predetermined value to determine a relationship between each of the plurality of signals to the predetermined value. A result of each comparison is categorized according to one of a plurality of predetermined criteria. The categorizing step is repeated at least until a predetermined number of results has been reached in at least one of the plurality of predetermined criteria. A decision is made based on which of the plurality of predetermined criteria reaches the predetermined number.

ANALOG TO DIGITAL CONVERTER AND A METHOD FOR ANALOG TO DIGITAL CONVERSION

An analog to digital converter (ADC) that may include an input configured to receive a first signal and a second signal; a signal generator that is configured to generate multiple signals, the multiple signals may include a phase-shifted clock signals that are phase shifted from each other, first pulse width modulation (PWM) related signals indicative of a value of the first signal, second PWM related signals indicative of a value of the second signals, a first sampled stream, a second stream that have substantially opposite phases, and phase related signals related to the first sampled stream and the second sampled stream; wherein the first sampled stream and the second sampled stream are generated based on at least one of the phase shifted clock signals; and a processing unit that is configured to receive at least some of the multiple signals, the at least some of the multiple signals may include the first PWM related signals, the second PWM related signals, and the phase related signals; generate, based on the at least some of the multiple samples, virtual counter values and virtual phase values that are mutually aligned; determine a value of a difference between the first signal and the second signal, and output an ADC output signal indicative of the difference between the first signal and the second signal. 1. An analog to digital converter (ADC) comprising:an input configured to receive a first signal and a second signal;a signal generator that is configured to generate multiple signals, the multiple signals may include a phase-shifted clock signals that are phase shifted from each other, first pulse width modulation (PWM) related signals indicative of a value of the first signal, second PWM related signals indicative of a value of the second signals, a first sampled stream, a second stream that have substantially opposite phases, and phase related signals related to the first sampled stream and the second sampled stream; wherein the first sampled stream and ...

Analog to digital converter and a method for analog to digital conversion

An analog to digital converter (ADC) receives first and second analog input signals. A charge sampling demultiplexer includes multiple capacitors that sample the first and second analog input signals, and generates multiple input samples representative of charge stored on the capacitors. A plurality of sub-ADCs each include first and second charge-to-time converters, which receive from the charge sampling demultiplexer respective first and second input sample of the first and second analog input signals and output respective first and second pulse-width-modulated (PWM) signals responsively to the respective first and second input samples. Temporal processing circuitry processes the PWM signals to generate a digital value indicative of a temporal difference between the first and second PWM signals. Output reordering circuitry receives the digital value from each of the sub-ADCs and generates a digital output indicative of a difference between the first and second analog input signals. 1. An analog to digital converter (ADC) , comprising:an input stage configured to receive first and second analog input signals;a charge sampling demultiplexer, which comprises multiple capacitors that are coupled to sample the first and second analog input signals, and which is configured to generate multiple input samples representative of charge stored on the capacitors; first and second charge-to-time converters, which are coupled to receive from the charge sampling demultiplexer a respective first input sample of the first analog input signal and a respective second input sample of the second analog input signal and to output respective first and second pulse-width-modulated (PWM) signals responsively to the respective first and second input samples; and', 'temporal processing circuitry, which is coupled to process the PWM signals to generate a digital value indicative of a temporal difference between the first and second PWM signals; and, 'a plurality of sub-ADCs, each sub-ADC ...

数据转换器以及相关模数转换器、数模转换器及芯片

本申请公开了一种数据转换器(112)。所述数据转换器包括输入端(98)、数模转换器(116)以及映射单元(114)。所述输入端用来接收输入信号。所述数模转换器包括多个数模转换器单元用来产生输出信号。所述映射单元，耦接于所述输入端以及所述数模转换器之间，用来使所述多个数模转换器单元依据所述多个数模转换器单元的特定电气特性来在所述多个数模转换器单元被选通的一相对顺序上等效地排列以进行数字模拟转换。本申请另提供模数转换器、数模转换器及相关芯片。

Resolver signal conversion device and method

在旋转变压器信号转换装置及其方法中，将来自旋转变压器的正弦波输出放大并进行模拟－数字转换后，通过带通滤波器，将具有以励磁信号的频率为中心频率的、规定频带的频率成分取出，与基于所述励磁信号的参考信号同步进行采样，根据该采样的信号作成检测角度信号的正弦值。同样，根据来自旋转变压器的余弦波输出作成检测角度信号的余弦值，根据检测角度信号的正弦值和余弦值计算出检测角度。借助于此，消除输入的旋转变压器信号受到马达产生的磁场和PWM驱动引起的开关噪声等造成的干扰噪声的影响，因为运算处理不具有频率相关性，因此降低了检测角度的误差。

Successive approximation analog to digital converter and method of analog to digital conversion

비교기 옵셋 보상 기능을 갖는 아날로그-디지털 변환기 및 아날로그-디지털 변환 방법이 개시된다. 아날로그-디지털 변환기는 디지털-아날로그 변환 회로, 비교기, 비교기 옵셋 검출 회로 및 신호처리 회로를 포함할 수 있다. 디지털-아날로그 변환 회로는 비교기 옵셋 보상 신호에 응답하여 변화되는 기준전압 신호를 발생하고, 아날로그 입력신호를 샘플/홀드하고, 디지털 출력 데이터에 대해 디지털-아날로그 변환을 수행하여 홀드 전압신호를 발생한다. 비교기는 클럭신호에 응답하여 홀드 전압신호를 기준 전압신호와 비교하여 비교 출력 전압신호를 발생한다. 비교기 옵셋 검출 회로는 비교 출력 전압신호에 기초하여 비교기 옵셋 보상 신호를 발생한다. 신호처리 회로는 비교 출력 전압신호에 기초하여 연속 접근(successive approximation)을 수행하여 디지털 출력 데이터를 발생한다. 따라서, 아날로그-디지털 변환기는 비교기의 옵셋이 감소하고 전력 소모가 적다. An analog-to-digital converter and an analog-to-digital conversion method with comparator offset compensation are disclosed. The analog-to-digital converter may include a digital-to-analog conversion circuit, a comparator, a comparator offset detection circuit and a signal processing circuit. The digital-analog conversion circuit generates a reference voltage signal that changes in response to the comparator offset compensation signal, samples / holds the analog input signal, and performs digital-analog conversion on the digital output data to generate a hold voltage signal. The comparator generates a comparison output voltage signal by comparing the hold voltage signal with the reference voltage signal in response to the clock signal. The comparator offset detection circuit generates a comparator offset compensation signal based on the comparator output voltage signal. The signal processing circuit performs successive approximation based on the comparison output voltage signal to generate digital output data. Therefore, the analog-to-digital converter reduces the offset of the comparator and consumes less power.

Analog / Digital Converter

본 발명은 아날로그/디지털 변환기에 관한 것으로, 종래 아날로그/디지털 변환기는 입력전압과 기준전압을 단순히 비교하여 디지털화하고 이를 아무런 처리없이 저장한 후 출력함으로써, 그 변환된 값의 신뢰성이 감소하는 문제점이 있었다. 이와 같은 문제점을 감안한 본 발명은 출력데이터를 특정 프로그램에 따라 보상하는 출력데이터 보상수단과; 제어신호에 따라 출력데이터 또는 출력데이터 보상수단의 보상된 출력데이터를 선택하여 내부 데이터 버스로 출력하는 선택수단을 더 포함하여 디지털 변환된 출력데이터를 출력하고, 이를 자료로하여 아날로그/디지털 변환기의 동작 특성을 판단한 후에, 그 아날로그/디지털 변환기의 출력데이터를 보상하는 보상수단을 두고, 그 보상수단에 의해 보상된 출력데이터 또는 보상되지 않은 출력데이터를 선택적으로 출력하는 선택수단을 둠으로써, 출력데이터를 이상적인 값으로 보상하여 출력하여 신뢰성을 향상시키는 효과가 있다. The present invention relates to an analog-to-digital converter, and the conventional analog-to-digital converter has a problem in that the reliability of the converted value is reduced by simply comparing the input voltage with the reference voltage and digitizing and storing the same without any processing. . In view of the above problems, the present invention includes an output data compensation means for compensating output data according to a specific program; And outputting the digitally converted output data by selecting the output data or the compensated output data of the output data compensating means and outputting them to the internal data bus according to the control signal. After determining the characteristic, the output data is determined by providing compensation means for compensating the output data of the analog-to-digital converter, and selecting means for selectively outputting the output data compensated by the compensation means or uncompensated output data. It has the effect of improving reliability by compensating for the ideal value and outputting it.

Device for reading graduations

Device for encoding the angular position of a shaft

Device for converting a continuous displacement into discrete signals

Patent FR2157761A1

Method for locating the position of a moving member or device and device for implementing the method

Device for converting a continuous displacement into discrete signals

High-speed ADC error calibration circuit

本发明属于模数转换集成电路领域，特点是发明一款高速ADC误差校准电路，以补偿校准预置放大器以及比较器的输入失调，而不影响整个ADC的正常工作。本次发明采用一种可以降低时钟相位偏移，实现高速ADC误差校准的采样电路。该电路结构采用在放大器的输入端额外增加一个差分对，固定一端，调节另一端来补偿失调电压。建立后端自动补偿环路，将失调补偿嵌入在正常的模数转换过程。这种采样电路可以广泛应用于时间交织(Time‑interleaved)ADC，它可以避免传统的基于延时锁相环(DLL)的多相位时钟产生电路。

Device for collecting digital information from rotating drums

Method and device for transforming measurement values according to a determined function

Parasitic capacitance digital compensation method and device

本发明公开了一种寄生电容数字补偿方法和装置。该方法包括：通过模数转换得到数字码字，其中，数字码字包括符号位码字、L位高端码字和L位低端码字，L位高端码字是由L个高端位的电容转换得到的码字，L位低端码字是由L个低端位的电容转换得到的码字；对L位低端码字进行补偿，得到补偿后的低端码字；将补偿后的低端码字与符号位码字、高端码字结合，得到中间码字；对中间码字进行补偿，得到补偿后的全码字。通过本发明，达到了提高模数转换精确度的效果。

Analog-to-digital conversion

An analog-to-digital conversion apparatus 10 comprises a plurality of analog-to-digital converters 30 and a ramp generator 20 . Each of the analog-to-digital converters 30 comprises an analog signal input for receiving an analog signal level and a ramp signal input. A control stage is arranged to compare the ramp signal with the analog signal level and, based on the comparison, to enable a counter provided at the analog-to-digital converter or to latch a digital value received from a counter. The control stage comprises a comparator in the form of a first differential amplifier with a first branch connected to the input for receiving the ramp signal, a second branch connected to the analog signal input and an output, and a biasing current source for biasing the first differential amplifier. A feedback circuit controls the biasing current source. The feedback circuit comprises a second differential amplifier OP 1 with a first input connected to a node 46 on the first branch and a second input connected to a reference voltage VB such that the node on the first branch is maintained at a substantially constant voltage.

Band-pass analog-to-digital converter, receiving circuit, communication device, and analog-to-digital conversion method

本发明提供了一种带通模数转换器，用于无线通信装置的射频接收电路中的模数转换。该带通模数转换器包括位于第一路径中的第一噪声整形逐次逼近寄存器(NS‑SAR)电路和位于第二路径中的第二NS‑SAR电路，所述第二路径与所述第一路径并行，其中，所述第一NS‑SAR电路和所述第二NS‑SAR电路用于以特定采样率交替采样模拟输入电压并得到采样输出电压，以及，对所述采样输出电压进行模数转换，以提供数字输出。相应地，本发明还提供了一种接收电路、无线通信装置和将模拟输入电压转换为数字电压的方法。采用本发明，可以降低功耗。

Analog acquisition dynamic compensation method and system

本发明涉及一种模拟量采集动态补偿方法及系统，该补偿方法通过实时计算晶振的实际频率与理论频率的差值，得出需要调整的采样间隔序号和间隔宽度，然后对采样间隔进行动态调整，并对采样序号进行对齐，FPGA以外接B码对时源作为秒脉冲基准，实时更新当前晶振的实际频率，并动态调整采样间隔。在本发明的技术方案中，FPGA以外接B码对时源作为秒脉冲基准，实时更新当前晶振的实际频率，并动态调整采样间隔，最大限度的保障模拟量采集的可靠稳定。

Asynchronous sampling rate conversion device and conversion method

本发明公开了一种异步采样率转换装置及转换方法，该装置包括插值滤波器、补偿模块、时钟生成器和除频器；该装置的电路简单，实现成本低，无需复杂的高阶滤波器，可以在只需一个采样率时钟的情况下实现无损转换，克服了现有技术中或需要两个时钟，或采用复杂的滤波器设计并将数据过采样到一个很高的频率的异步采样率转换装置的缺陷。

Current comparator for eliminating offset error and comparison method

该发明公开了一种消除失调误差的电流比较器及比较方法，应用于高速高精度的电流舵模数转换器。将参考电流源I U 正极接电压源，负极接开关K 0 ，开关K 0 另一端接跨导放大器的负输入端；电容C A1 一端接跨导放大器的负输入端，另一端接地；跨导放大器的正极接地，输出端接参考电流源I U 的负极；第k个电流源I k 正极接第k个电流源开关K k ,负极接地，第k个电流源开关K k 另一端接电流源I U 的负极，其中k＝1、2、3......K；电容C A2 的左极板接电流源I U 的负极，右极板接比较器预放大级的负输入端；比较器预放大级的负输入端与输出端通过开关K′ 0 连接，比较器预放大级的正输入端接地，比较器预放大级的输出端为本发明电流比较器的输出。本发明能消除比较器失调的影响，无需额外的电流比较器就能实现电流大小的比较。

Reference voltage generator for an analog-digital converter and method for analog-digital conversion