Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performance

A method to form SOI devices using wafer bonding. A first substrate is provided having trenches in a first side. A first insulating layer is formed over the first side of the first substrate and filling the trenches. We planarize the first insulating layer to form isolation regions (e.g., STI). The three embodiments of the invention planarize the first insulating layer to different levels. In the second embodiment, the first insulating layer is etched back to form a recess. This recess later forms an air gap. We provide a second substrate having a second insulating layer over a first side of the second substrate. We bond the second insulating layer to the first insulating layer. Next, we thin the first substrate from the second side to expose the first insulating layer to form active areas between the isolation regions. Lastly, devices are formed in and on the active areas.

Method to fabricate aligned dual damascene openings

A method of forming an aligned dual damascene opening, comprising including the following sequential steps. A structure having a metal structure formed thereover is provided. A layer stack is formed over the metal structure. The layer stack comprises, in ascending order: a bottom etch stop layer; a lower dielectric material layer; a middle etch stop layer; a middle dielectric material layer; and an upper dielectric layer. The upper dielectric layer is patterned to form an opening exposing a portion of the underlying middle dielectric material layer. The opening having a width. A patterned mask layer is formed over the patterned upper dielectric layer leaving exposed opposing portions of the patterned upper dielectric layer. The middle dielectric material layer is patterned to form an opening therein using the patterned mask layer and the exposed portions of the upper dielectric layer as masks. The middle dielectric material layer opening exposing a portion of the middle etch stop layer.

Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application

A method of manufacturing conductive lines that are thicker (not wider) in the critical paths areas. We form a plurality of first level conductive lines over a first dielectric layer. The first conductive lines run in a first direction. The first level conductive lines are comprised of a first level first conductive line and a second first level conductive line. We form a second dielectric layer over the first level conductive lines and the first dielectric layer. Next, we form a via opening in the second dielectric layer over a portion of the first level first conductive line. A plug is formed filling the via opening. We form a trench pattern in the second dielectric layer. The trench pattern is comprised of trenches that are approximately orthogonal to the first level conductive lines. We fill the trenches with a conductive material to form supplemental second lines. We form second level conductive lines over the supplemental second lines and the plug. The second level conductive lines ...

Slot designs in wide metal lines

A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug.

Dual silicon-on-insulator device wafer die

A silicon-on-insulator semiconductor device is provided in which a single wafer die contains a transistor over an insulator layer to form a fully depleted silicon-on-insulator device and a transistor formed in a semiconductor island over an insulator structure on the semiconductor wafer forms a partially depleted silicon-on-insulator device.

Method to fabricate aligned dual damacene openings

An aligned dual damascene opening structure, comprising the following. A structure having a metal structure formed thereover. A patterned layer stack over the metal structure; the layer stack comprising, in ascending order: a patterned bottom etch stop layer; a patterned lower dielectric material layer; a patterned middle etch stop layer; and a patterned middle dielectric material layer; the lower and middle dielectric layers being comprised of the same material. An upper trench opening in the patterned bottom etch stop layer and the patterned lower dielectric material layer; and a lower via opening in the patterned middle etch stop layer and the patterned middle dielectric material layer. The lower via opening being in communication with the upper trench opening. Wherein the upper trench opening and the lower via opening comprise an aligned dual damascene opening.

Method to fabricate elevated source/drain transistor with large area for silicidation

A method for forming a transistor having an elevated source/drain structure is described. A gate electrode is formed overlying a substrate and isolated from the substrate by a gate dielectric layer. Isolation regions are formed in and on the substrate wherein the isolation regions have a stepped profile wherein an upper portion of the isolation regions partly overlaps and is offset from a lower portion of the isolation regions in the direction away from the gate electrode. Ions are implanted into the substrate between the gate electrode and the isolation regions to form source/drain extensions. Dielectric spacers are formed on sidewalls of the gate electrode and the isolation regions. A conductive layer is deposited overlying the substrate, the gate electrode, and the isolation regions and planarized to leave the conductive layer adjacent to the gate electrode and separated from the gate electrode by the dielectric spacers wherein the conductive layer forms elevated source/drain junctions ...

Formation of metal silicide layer over copper interconnect for reliability enhancement

A method of fabrication of a sputtered metal silicide layer over a copper interconnect. We form a dielectric layer over a conductive layer. We form an interconnect opening in the dielectric layer. We form a copper layer at least filling the interconnect opening. We planarize the copper layer to form a copper interconnect in the interconnect opening. The copper interconnect is over polished to form a depression. We form metal silicide layer over the copper interconnect using a low temperature sputtering process. We can form a cap layer over the metal silicide layer.

SIMPLIFIED METHOD TO REDUCE OR ELIMINATE STI OXIDE DIVOTS

A method for forming shallow trench isolation wherein oxide divots at the edge of the isolation and active regions are reduced or eliminated is described. A trench is etched into a semiconductor substrate. An oxide layer is deposited overlying the semiconductor substrate and filling the trench. Nitrogen atoms are implanted into the oxide layer overlying the trench. The substrate is annealed whereby a layer of nitrogen-rich oxide is formed at the surface of the oxide layer overlying the trench. The oxide layer is planarized to the semiconductor substrate wherein the nitrogen-rich oxide layer is planarized more slowly than the oxide layer resulting in a portion of the oxide layer remaining overlying the trench after the oxide layer overlying swthe aid semiconductor substrate has been removed wherein the portion of the oxide layer remaining provides a smooth transition between the shallow trench isolation and the active areas completing the formation of shallow trench isolation in the fabrication ...

Integrated circuit with self-aligned line and via and manufacturing method therefor

An integrated circuit and manufacturing method therefor is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.

INTEGRATED CIRCUIT WITH SELF-ALIGNED LINE AND VIA

An integrated circuit is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.

AIR FILTER

An air filter having an inlet for air and an outlet for air comprises a body having a central channel, a first side with a first area, a second side having a second area, and a middle having a middle area, positioned between the first side and the second side. The middle area is less than the first area and less than the second area. A first fan is positioned in the body near the first side, and a second fan positioned in the body near the second side, and each fan blows air in the same direction. A filter cartridge is positioned in the central channel at the middle, wherein during operation air flows from the inlet to the filter cartridge to the outlet. 116-. (canceled)17. An air filter having an Inlet for air and an outlet for air comprising in combination:a body having a central channel, a first side, a second side, and a middle positioned between the first side and the second side, wherein a constriction is formed In the central channel at the middle;a first fan positioned in the central channel near the first side, a second fan positioned In the central channel near the second side, wherein each fan blows air In the same direction: anda filter cartridge positioned In the central channel at the middle, wherein during operation air flows from the inlet to the filter cartridge to the outlet, and substantially all air blown from the first fan passes through the second fan.18. The air filter of wherein the filter cartridge comprises a perforated housing containing a filtering agent.19. The air fitter of wherein the filtering agent is one of activated carbon and charcoal.20. The air filter of wherein the perforated housing is provided with a plurality of perforations allowing air access to the filtering agent.21. The air filter of wherein the perforations are aligned in a direction generally perpendicular to a flow of the air.22. The air filter of further comprising an Inlet cap at the inlet and an outlet cap at the outlet23. The air filter of further comprising a ...

TSV Backside Processing Using Copper Damascene Interconnect Technology

Generally, the subject matter disclosed herein relates to interconnect structures used for making electrical connections between semiconductor chips in a stacked or 3D chip configuration, and methods for forming the same. One illustrative method disclosed herein includes forming a conductive via element in a semiconductor substrate, wherein the conductive via element is formed from a front side of the semiconductor substrate so as to initially extend a partial distance through the semiconductor substrate. The illustrative method also includes forming a via opening in a back side of the semiconductor substrate to expose a surface of the conductive via element, and filling the via opening with a layer of conductive contact material. 1. A method , comprising:forming a conductive via element in a semiconductor substrate, wherein said conductive via element is formed from a front side of said semiconductor substrate so as to initially extend a partial distance through said semiconductor substrate;forming a via opening in a back side of said semiconductor substrate to expose a surface of said conductive via element; andfilling said via opening with a layer of conductive contact material.2. The method of claim 1 , further comprising forming an isolation layer in said via opening prior to filling said via opening.3. The method of claim 2 , wherein forming said isolation layer comprises performing a material deposition process.4. The method of claim 2 , wherein forming said isolation layer comprises performing an oxidation process.5. The method of claim 2 , wherein forming said isolation layer comprises forming a portion of said isolation layer above said surface of said conductive via element and removing said portion of said isolation layer prior to filling said via opening.6. The method of claim 1 , further comprising forming a dielectric material layer above said back side of said semiconductor substrate.7. The method of claim 6 , wherein said dielectric material layer ...

Crack-Arresting Structure for Through-Silicon Vias

The subject matter disclosed herein relates to structures formed on semiconductor chips that are used for at least partially addressing the thermally induced stresses and metallization system cracking problems in a semiconductor chip that may be caused by the presence of through-silicon vias (TSV's), and which may be due primarily to the significant differences in thermal expansion between the materials of the TSV's and the semiconductor-based materials that generally make up the remainder of the semiconductor chip. One device disclosed herein includes a substrate and a crack-arresting structure positioned above the substrate, the crack-arresting structure comprising a plurality of crack-arresting elements and having a perimeter when viewed from above. The device also includes a conductive structure positioned at least partially within the perimeter of the crack-arresting structure, and a conductive element extending through an opening in the crack-arresting structure, wherein the conductive element is conductively coupled to the conductive structure. 1. A device , comprising:a substrate;a crack-arresting structure positioned above said substrate, said crack-arresting structure comprising a plurality of crack-arresting elements and having a perimeter when viewed from above;a conductive structure positioned at least partially within said perimeter of said crack-arresting structure; anda conductive element extending through an opening in said crack-arresting structure, wherein said conductive element is conductively coupled to said conductive structure.2. The device of claim 1 , wherein said crack-arresting structure is positioned in a metallization system comprising a plurality of metallization layers claim 1 , said metallization system being positioned above said substrate.3. The device of claim 2 , wherein said crack-arresting structure extends from said substrate to a last metallization layer of said plurality of metallization layers.4. The device of claim 2 , ...

BACK-SIDE MOM/MIM DEVICES

Back-side MOM/MIM structures are integrated on a device with front-side circuitry. Embodiments include forming a substrate having a front side and a back side that is opposite the front side, the substrate including circuitry on the front side of the substrate; and forming a metal-oxide-metal (MOM) capacitor, a metal-insulator-metal (MIM) capacitor, or a combination thereof on the back side of the substrate. Other embodiments include forming a through-silicon via (TSV), in the substrate, connecting the MOM capacitor, the MIM capacitor, or a combination thereof to the circuitry on the front side of the substrate. 1. A method comprising:forming a substrate having a front side and a back side that is opposite the front side, the substrate including circuitry on the front side of the substrate; andforming a metal-oxide-metal (MOM) capacitor, a metal-insulator-metal (MIM) capacitor, or a combination thereof on the back side of the substrate.2. The method according to claim 1 , comprising forming a through-silicon via (TSV) claim 1 , in the substrate claim 1 , connecting the MOM capacitor claim 1 , the MIM capacitor claim 1 , or a combination thereof to the circuitry on the front side of the substrate.3. The method according to claim 1 , wherein the circuitry on the front side of the substrate includes a front-side MOM capacitor claim 1 , a front-side MIM capacitor claim 1 , or a combination thereof4. The method according to claim 1 , comprising forming the MOM capacitor by forming a plurality of parallel fingers.5. The method according to claim 4 , comprising forming the parallel fingers by forming a plurality of ultra thick metal (UTM) fingers.6. The method according to claim 1 , comprising forming the MOM capacitor by:forming a first layer, including a first set of parallel fingers, on the back side of the substrate; andforming one or more other layers, including one or more other sets of parallel fingers, under the first layer on the back side of the substrate.7. The ...

METHOD FOR FORMING HEAT SINK WITH THROUGH SILICON VIAS

Semiconductor devices are formed with through silicon vias extending into the semiconductor substrate from a backside surface for improved heat dissipation. Embodiments include forming a cavity in a backside surface of a substrate, the substrate including a gate stack on a frontside surface, and filling the cavity with a thermally conductive material. 1. A method comprising:forming a cavity in a backside surface of a substrate, the substrate including a gate stack on a frontside surface; andfilling the cavity with a thermally conductive material.2. The method according to claim 1 , further comprising filling the cavity by electrochemical plating (ECP).3. The method according to claim 1 , further comprising forming a liner material layer in the cavity prior to filling the cavity with the thermally conductive material.4. The method according to claim 1 , further comprising:forming a second cavity in the backside surface of the substrate; andfilling the second cavity with the thermally conductive material,wherein a pitch ratio of an average diameter of the first and second cavities to a distance between the first and second cavities is 1:x, where x is 2 or larger.5. The method according to claim 1 , further comprising forming the cavity to a depth of 6 to 10 μm into the substrate.6. The method according to claim 1 , further comprising forming the cavity to a width of 6 μm or larger at the backside surface of the substrate.7. The method according to claim 1 , further comprising aligning the cavity with an area of higher heat generation.8. The method according to claim 1 , further comprising forming a layer of the thermally conductive material on the backside surface of the substrate.9. A device comprising:a substrate having a frontside surface and a backside surface, the substrate including a gate stack on the frontside surface; anda thermally conductive material extending into the substrate from the backside surface.10. The device according to claim 9 , wherein the ...

Device with integrated power supply

Semiconductor devices and methods for forming a semiconductor device are disclosed. The semiconductor device includes a die. The die includes a die substrate having first and second major surfaces. The semiconductor device includes a power module disposed below the second major surface of the die substrate. The power module is electrically coupled to the die through through silicon via (TSV) contacts.

DIELECTRIC POSTS IN METAL LAYERS

A semiconductor device is disclosed. The semiconductor device includes a substrate comprises a plurality of metal layers. The semiconductor device also includes dielectric posts disposed in the metal layers. The density of the dielectric posts in the metal layers is equal to about 15-25%. 1. A semiconductor device comprising:a substrate comprises a plurality of metal layers; anddielectric posts disposed in the metal layers, wherein the density of the dielectric posts in the metal layers is equal to about 15-25%.2. The semiconductor device of further comprising via bar disposed in between adjacent metal layers.3. The semiconductor device of wherein the metal layers are disposed in a crack stop region.4. The semiconductor device of wherein the via bar comprises a mesh design or a straight line design.5. The semiconductor device of wherein the metal layers comprise wide metal lines.6. The semiconductor device of wherein the wide metal lines are about 4.5-7 μm wide.7. The semiconductor device of wherein the wide metal lines are wider than about 7 μm wide.8. The semiconductor device of wherein the dielectric posts comprise a dielectric material.9. The semiconductor device of wherein the dielectric posts extend the thickness of the wide metal lines.10. The semiconductor device of wherein the dielectric posts do not come into contact with the via bars above and below the wide metal lines.11. A semiconductor device comprising:a substrate comprises a plurality of metal levels having metal layers disposed in a crack stop region; anddielectric posts disposed in the metal layers, wherein the density of the dielectric posts in the metal layers is equal to about 15-25%.12. The semiconductor device of further comprising via levels disposed in between adjacent metal levels.13. The semiconductor device of wherein via bars are disposed in the via levels.14. The semiconductor device of wherein the via bars comprise a mesh design or straight line design.15. The semiconductor device of ...

System and Method for Peeling a Semiconductor Chip From a Tape Using a Multistage Ejector

A system and method for peeling a semiconductor chip from a tape using a multistage ejector is disclosed. A housing in the multistage ejector houses a plural sets of tape removing contacts. A pick and place unit is moved slowly to have contact with the chip. A vacuum source is utilized for generating vacuum to suck the tape. Plural sets of contacts such as inner, middle and outer contacts are independently or together moved below the tape at various stages by utilizing their respective actuation mechanism. A controller can independently control the movements of each contact to effectively remove or loosen the tape from the chip. A pick and place unit can then pick up the chip easily without any damage to chip. 1. A system for peeling a semiconductor chip from a tape , the system comprising:a housing having a top surface, wherein the top surface is positioned under the tape on which the chip is attached;a plural sets of tape removing contacts provided at the center of the top surface of the housing, wherein each of the plural sets of tape removing contacts is capable of moving independently or together with the other sets;a plurality of vacuum channels surrounding the plural sets of tape removing contacts;a vacuum source coupled to the plurality of vacuum channels for creating a vacuum to hold the tape firmly; anda controller for controlling the vacuum source and the plural sets of tape removing contacts,wherein the chip is removed from the tape due to the synchronous movement of the plural sets of tape removing contacts once the vacuum source is turned on.3. The system of claim 1 , wherein each set of the plural sets of tape removing contacts is coupled to a respective actuation mechanism that facilitates its movement based upon trigger received from the controller.4. The system of claim 1 , wherein contacts of the plural sets of tape removing contacts comprises at least one of pins or needles.5. The system of claim 1 , further comprising a pickup and place unit ...

TRANSFER SYSTEM FOR FLIPPING AND MULTIPLE CHECKING OF ELECTRONIC DEVICES

The present invention includes a transfer system for flipping and checking electronic devices. A first rotary device has a plurality of transfer heads configured to pick electronic devices from a wafer table and place the electronic devices on a transfer head of a second rotary device. Check stations can be positioned around the first and second rotary devices and configured to inspect or check the electronic devices during the flipping process. The transfer system can further include an imaging device to inspect the accuracy of picking and placing of the electronic devices during the flipping process. The wafer table and the first rotary device are inclined to increase the operation space. The system accurately picks, flips and transfers chips at a high operation speed. 1. A transfer system for flipping and checking electronic devices , said transfer system comprising:a wafer table inclined about a first angle with respect to a horizontal axis;a first rotary device positioned at a second angle with respect to a horizontal axis, said first rotary device comprising a plurality of first transfer heads circumferentially arranged around said first rotary device, said first transfer heads configured to pick and hold said electronic devices from said wafer table and transfer said electronic devices to a second rotary device;the second rotary device being rotatable about a horizontal axis, said second rotary device comprising a plurality of second transfer heads vertically arranged on a circumference of said second rotary device, said second rotary device configured to pick said electronic devices from said first rotary device and transfer said electronic devices to a handling device;a first imaging device to inspect said electronic devices to be picked from the wafer table;a second imaging device to inspect said electronic devices to be placed on the handling device;a plurality of check stations positioned around said first and second rotary devices, said plurality of ...

DEVICE WITH INTEGRATED PASSIVE COMPONENT

Semiconductor devices and methods for forming a semiconductor device are presented. The semiconductor device includes a die which includes a die substrate having first and second major surfaces. The semiconductor device includes a passive component disposed below the second major surface of the die substrate. The passive component is electrically coupled to the die through through silicon via (TSV) contacts. 1. A semiconductor device comprising:a die which includes a die substrate having first and second major surfaces; anda passive component disposed below the second major surface of the die substrate, wherein the passive component is electrically coupled to the die through through silicon via (TSV) contacts.2. The semiconductor device of wherein the TSV contacts are disposed within the die substrate.3. The semiconductor device of wherein the first major surface is an active substrate surface while the second major surface is an inactive substrate surface.4. The semiconductor device of wherein circuit components are disposed on the first major surface.5. The semiconductor device of wherein:the passive component includes an inductor having at least first and second terminals; andthe TSV contacts are coupled to the first and second terminals.6. The semiconductor device of wherein the inductor directly contacts the second major surface of the die substrate.7. The semiconductor device of wherein the die is an interposer die.8. The semiconductor device of wherein the TSV contacts are disposed within the interposer.9. The semiconductor device of comprising a die being disposed on a first interposer surface while the passive component is disposed on a second interposer surface.10. The semiconductor device of wherein the die is coupled to the interposer by TSV contacts within the die substrate or bump connections on the first interposer surface.11. A method for forming a semiconductor device comprising:providing a die which includes a die substrate having first and second ...

SLOT DESIGNS IN WIDE METAL LINES

A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug. 1. A device comprising:a substrate;a dielectric layer disposed over the substrate, wherein the dielectric layer corresponds to an interconnect level of the device; anda continuous conductive line disposed in a trench in the dielectric layer, wherein the continuous conductive line surrounds at least one dielectric structure within the continuous conductive line, the dielectric structure partially interrupts the continuous conductive line, wherein the dielectric structure is positioned in a portion of the continuous conductive line which has a via plug in communication therewith.2. The device of wherein the dielectric structure is of a sufficient dimension to reduce stress related defects in the continuous conductive line and the via plug in a via level which is in communication with the continuous conductive line in proximity of the dielectric structure.3. The device of wherein:the dielectric structure is of sufficient size to reduce stress related defects in the continuous conductive line and the via plug in a via level in communication with the continuous conductive line in proximity of the dielectric structure; andthe continuous conductive line comprises copper.4. The device of wherein the continuous conductive line ...

Laser Scribing Of Thin-Film Solar Cell Panel

The present invention describes an apparatus for a first laser scribing (P 1 ) on the front electrode of a thin film solar cell panel and a similar apparatus for subsequent laser scribing (P 2 ,P 3 ) on the semiconductor layer and semiconductor layer/rear electrode. Before starting scribing process (P 1 ), the left hand edge or reference line on the left hand edge on a workpiece is aligned substantively parallel to the linear drive before translating the workpiece on the apparatus. Similarly, the first and second scribed lines (Lp 1 ,Lp 2 ) formed during the P 1 and P 2 processes are separately aligned parallel to the linear drive before starting the relevant process (P 2 ,P 3 ). Alternatively, parallelism of the workpiece is carried out for each batch of the workpiece. In both apparatuses, the laser sources are mounted on independently motorised axes.

System and Method for Lead Foot Angle Inspection Using Multiview Stereo Vision

The present invention includes a system and method for three-dimensional imaging and analysis of electronic components. Specifically, it permits rapid and reliable inspection of the lead foot angle in integrated circuit packages. A first image capturing device, a second image capturing device and a third image capturing device are arranged in a “corner shape” or “L-shape.” The first image capturing device forms the corner and obtains an image of the bottom of the component. The perspective viewing angle of the second image capturing device and the perspective viewing angle of the third image capturing device are orthogonal to each other to allow accurate three-dimensional reconstruction of the lead angles and detection of flaws or bends. 19.- (canceled)10. A system for analyzing the lead foot angle of an integrated circuit package comprising:a) a support for the object;b) a light source;c) a first image capturing device comprising a first lens and a first sensor and being mounted at a first bottom viewing angle that is perpendicular to a plane where the object is placed for capturing a first bottom view image,d) a second image capturing device comprising a second lens and a second sensor and being mounted at a second perspective viewing angle from the object for capturing a second perspective view image,e) a third image capturing device comprising a third lens and a third sensor and being mounted at a third perspective viewing angle from the object for capturing a third perspective view image,wherein the first, second and third image capturing devices form a corner shape with the first image capturing device in the center, the second image capturing device on a left side of the first image capturing device and the third image capturing device on a front side of the first image capturing device;wherein a first optical axis of the first imaging capturing device is a line passing through the center of said first lens and the center of said first sensor, a second ...

Dual silicon-on-insulator device wafer die

A silicon-on-insulator semiconductor device and manufacturing method therefor is provided in which a single wafer die contains a transistor over an insulator layer to form a fully depleted silicon-on-insulator device and a transistor formed in a semiconductor island over an insulator structure on the semiconductor wafer forms a partially depleted silicon-on-insulator device.

Versatile copper-wiring layout design with low-k dielectric integration

A method to integrate low dielectric constant dielectric materials with copper metallization is described. A metal line is provided overlying a semiconductor substrate and having a nitride capping layer thereover. A polysilicon layer is deposited over the nitride layer and patterned to form dummy vias. A dielectric liner layer is conformally deposited overlying the nitride layer and dummy vias. A dielectric layer having a low dielectric constant is spun-on overlying the liner layer and covering the dummy vias. The dielectric layer is polished down whereby the dummy vias are exposed. Thereafter, the dielectric layer is cured whereby a cross-linked surface layer is formed. The dummy vias are removed thereby exposing a portion of the nitride layer within the via openings. The exposed nitride layer is removed. The via openings are filled with a copper layer which is planarized to complete copper metallization in the fabrication of an integrated circuit device.

Flip chip in package using flexible and removable leadframe

A method for forming semiconductor packages is disclosed. The method involves providing a support substrate and forming at least one conductive layer thereon. The method also includes coupling the at least one conductive layer to a support face of a film substrate for securing the at least one conductive layer to the support face and removing the support substrate from the at least one conductive layer. The at least one interconnector is adhered to the film substrate for forming an interposer. The method further involves bonding a integrated circuit chip to the at least one conductive layer of the interposer and disposing a compound over the support face to thereby encapsulate the integrated circuit chip and the least one conductive layer for forming an encapsulated package therefrom. Portions of the at least one conductive layer is then exposed by removing the film substrate from the encapsulated package.

TSV backside processing using copper damascene interconnect technology

Generally, the subject matter disclosed herein relates to interconnect structures used for making electrical connections between semiconductor chips in a stacked or 3D chip configuration, and methods for forming the same. One illustrative method disclosed herein includes forming a conductive via element in a semiconductor substrate, wherein the conductive via element is formed from a front side of the semiconductor substrate so as to initially extend a partial distance through the semiconductor substrate. The illustrative method also includes forming a via opening in a back side of the semiconductor substrate to expose a surface of the conductive via element, and filling the via opening with a layer of conductive contact material.

Semiconductor package singulating system and method

Flip chip bonder and method therefor

Dielectric posts in metal layers

A semiconductor device is disclosed. The semiconductor device includes a substrate comprises a plurality of metal layers. The semiconductor device also includes dielectric posts disposed in the metal layers. The density of the dielectric posts in the metal layers is equal to about 15-25%.

Method to fabricate elevated source/drain transistor with large area for silicidation

Antimicrobial compounds from bacillus subtilis for use against animal and human pathogens

Antimicrobial compounds from Bacillus subtilis for use against animal and human pathogens. A novel strain of Bacillus subtilis was isolated from the gastrointestinal tract of poultry and was found to produce a factor or factors that have excellent inhibitory effects on Clostridium perfringens, Clostridium difficile, Campylobacter jejuni, Campylobacter coli, and Streptococcus pneumoniae. The factor(s) retain full viability and antimicrobial activity after heat treatment. The invention provides a method of treatment of pathogenic microorganisms including C. perfringens.

Flip chip in package using flexible and removable leadframe

A method for forming semiconductor packages is disclosed. The method involves providing a support substrate and forming at least one conductive layer thereon. The method also includes coupling the at least one conductive layer to a support face of a film substrate for securing the at least one conductive layer to the support face and removing the support substrate from the at least one conductive layer. The at least one interconnector is adhered to the film substrate for forming an interposer. The method further involves bonding a integrated circuit chip to the at least one conductive layer of the interposer and disposing a compound over the support face to thereby encapsulate the integrated circuit chip and the least one conductive layer for forming an encapsulated package therefrom. Portions of the at least one conductive layer is then exposed by removing the film substrate from the encapsulated package.

Semiconductor package singulating system and method

INTEGRATED CIRCUIT (IC) CHIPS ARE FABRICATED WITH MULTIPLE IC CHIPS BEING TYPICALLY ARRANGED ON A SINGLE SUBSTRATE WHICH IS SINGULATED TO OBTAIN INDIVIDUALLY SEPARATED PACKAGES OF IC CHIPS THEREFROM. GENERALLY, THE PACKAGES FORMING THE SUBSTRATE ARE SEPARATED USING A SAW, A DICING SAW OR THE LIKE CUTTING DEVICES. THE SUBSTRATES IS OFTEN SUPPORTED ON A RUBBER PAD WHICH INTERFACES THE SUBSTRATE AND A SAW JIG OR THE LIKE SUPPORT. AIR IS THE EXTRACTED THROUGH A PLURALITY OF HOLES FORMED IN THE RUBBER PAD FOR CREATING A VACUUM THERETHROUGH. THE VACUUM SECURES THE SUBSTRATES TO THE SAW JIG BOTH BEFORE AND AFTER THE PACKAGES ARE SEPARATED AND DURING THE SAWING THEREOF. IN ADDITION TO THE USE OF VACUUM,TYPICAL METHODS AND SYSTEMS USE ADHESIVE PADS FOR FURTHER SECURING THE SUBSTRATE. HOWEVER, THESE CONVENTIONAL METHODS AND SYSTEMS SUFFER FROM THE NEED FOR AN ADDITIONAL STEP OF SUBSTRATE REMOVAL.AN EMBODIMENT OF THE INVENTION DISCLOSES A SAW JIG FOR SUPPORTING A SUBSTRATE ON A COMPRESSIBLE SUPPORT PAD. A CLAMP IS MOUNTABLE ONTO THE SAW JIG FOR CLAMPING THE SUBSTRATE THEREBETWEEN WITHOUT IMPEDING ACCESS OF A SAW BLADE TO THE SUBSTRATE. VACUUM THROUGH CHANNELS FORMED IN THE SUPPORT PAD AND SAW JIG GENERATES SUCTION FORCES FOR POSITIONALLY IMMOBILISING THE SUBSTRATE IN COMBINATION WITH THE CLAMPING FORCES OF THE CLAMP DURING SINGULATION OF THE SUBSTRATE BY THE SAW BLADE.

Method to fabricate aligned dual damascene openings

An aligned dual damascene opening structure, comprising the following. A structure having a metal structure formed thereover. A patterned layer stack over the metal structure; the layer stack comprising, in ascending order: a patterned bottom etch stop layer; a patterned lower dielectric material layer; a patterned middle etch stop layer; and a patterned middle dielectric material layer; the lower and middle dielectric layers being comprised of the same material. An upper trench opening in the patterned bottom etch stop layer and the patterned lower dielectric material layer; and a lower via opening in the patterned middle etch stop layer and the patterned middle dielectric material layer. The lower via opening being in communication with the upper trench opening. Wherein the upper trench opening and the lower via opening comprise an aligned dual damascene opening.

Antimicrobial compounds from bacillus subtilis for use against animal and human pathogens

Antimicrobial compounds from Bacillus subtilis for use against animal and human pathogens. A novel strain of Bacillus subtilis was isolated from the gastrointestinal tract of poultry and was found to produce a factor or factors that have excellent inhibitory effects on Clostridium perfringens, Clostridium difficile, Campylobacter jejuni, Campylobacter coli, and Streptococcus pneumoniae. The factor(s) retain full viability and antimicrobial activity after heat treatment. The invention provides a method of treatment of pathogenic microorganisms including C. perfringens.

Handler for semiconductor singulation and method therefor

A water jet handler ( 200 ) has a loading location ( 205 ), a cutting location ( 210 ), and an unloading location ( 215 ); and two movable mounts ( 240 and a 245 ). As a first movable mount ( 240 ) receives a molded substrate at the loading location ( 205 ), and transport it to the cutting location ( 210 ), a second movable mount ( 245 ) transports singulated semiconductor packages of a previously singulated molded substrate from the cutting location ( 210 ) to the unloading location ( 215 ). As the molded substrate on the first movable mount ( 240 ) is cut in the X direction ( 232 ) by a water jet, the singulated semiconductor packages are unloaded. The molded substrate is then transferred to the second movable mount ( 245 ) on which it is cut in the Y direction ( 272 ) to produce singulated semiconductor packages, as the first movable mount ( 240 ) returns to the loading location ( 205 ), when another molded substrate is loaded.

Method for fabricating soi devices with option of incorporating air-gap feature for better insulation and performance

Handler for semiconductor singulation and method therefor

System and method for peeling a semiconductor chip from a tape using a multistage ejector

A system and method for peeling a semiconductor chip from a tape using a multistage ejector is disclosed. A housing in the multistage ejector houses a plural sets of tape removing contacts. A pick and place unit is moved slowly to have contact with the chip. A vacuum source is utilized for generating vacuum to suck the tape. Plural sets of contacts such as inner, middle and outer contacts are independently or together moved below the tape at various stages by utilizing their respective actuation mechanism. A controller can independently control the movements of each contact to effectively remove or loosen the tape from the chip. A pick and place unit can then pick up the chip easily without any damage to chip.

具有積體被動組件之設備

本發明提出數種半導體設備及形成半導體設備的方法。該半導體設備含有包含晶粒基板的晶粒，該晶粒基板具有第一及第二主表面。該半導體設備包含配置於該晶粒基板之該第二主表面下的被動組件。該被動組件通過數個矽通孔(TSV)接觸件電性耦合至該晶粒。

System and method for peeling a semiconductor chip from a tape using a multistage ejector

A system and method for peeling a semiconductor chip from a tape using a multistage ejector is disclosed. A housing in the multistage ejector houses a plural sets of tape removing contacts. A pick and place unit is moved slowly to have contact with the chip. A vacuum source is utilized for generating vacuum to suck the tape. Plural sets of contacts such as inner, middle and outer contacts are independently or together moved below the tape at various stages by utilizing their respective actuation mechanism. A controller can independently control the movements of each contact to effectively remove or loosen the tape from the chip. A pick and place unit can then pick up the chip easily without any damage to chip.

System and method for peeling a semiconductor chip from a tape using a multistage ejector

A system and method for peeling a semiconductor chip (604) from a tape (606) using a multistage ejector is disclosed. A housing (102) in the multistage ejector houses an inner (202), middle (204) and outer (206) set of tape removing contacts. A pick and place unit is moved slowly to have contact with the chip (604). A vacuum source is utilized for generating vacuum to suck the tape (606). The inner (202), middle (204) and outer (206) sets of tape removing contacts are independently or together moved below the tape (606) at various stages by utilizing their respective actuation mechanism. A controller can independently control the movements of each inner (202), middle (204) and outer (206) sets of tape removing contact to effectively remove or loosen the tape (606) from the chip. A pick and place unit can then pick up the chip (604) easily without any damage to chip. [FIG. 2]

System and method for peeling a semiconductor chip from a tape using a multistage ejector

A system and method for peeling a semiconductor chip from a tape using a multistage ejector is disclosed. A housing in the multistage ejector houses a plural sets of tape removing contacts. A pick and place unit is moved slowly to have contact with the chip. A vacuum source is utilized for generating vacuum to suck the tape. Plural sets of contacts such as inner, middle and outer contacts are independently or together moved below the tape at various stages by utilizing their respective actuation mechanism. A controller can independently control the movements of each contact to effectively remove or loosen the tape from the chip. A pick and place unit can then pick up the chip easily without any damage to chip.

Air filter

An air filter having an inlet for air and an outlet for air comprises a body having a central channel, a first side with a first area, a second side having a second area, and a middle having a middle area, positioned between the first side and the second side. The middle area is less than the first area and less than the second area. A first fan is positioned in the body near the first side, and a second fan positioned in the body near the second side, and each fan blows air in the same direction. A filter cartridge is positioned in the central channel at the middle, wherein during operation air flows from the inlet to the filter cartridge to the outlet.

Slot designs in wide metal lines

SLOT DESIGNS IN WIDE METAL LINES A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug. FIGURE 1B-1 L

整合電源供應之設備

本文涉及一種具有整合電源供應的設備，所揭露的是半導體設備及用於形成半導體設備的方法。半導體設備包含晶粒。晶粒包含具有第一與第二主表面的晶粒基板。半導體設備包含置於晶粒基板的第二主表面下方的電源模組。電源模組是透過矽穿孔接點電耦合於晶粒。

Multiple surface viewer

Switch

SWITCH An electrical switch 100 suitable for switching an electrical connection between at least two terminals is provided. The switch 100 comprises a switch body in the form of a housing 110, an actuating member in the form of a switch button 120, and a resiliently flexible leaf spring 130. The switch button 120 is pivotally engaged with the housing 110 to be movable relative to the housing 110 between a first position and a second position. The switch button 120 is pivotally engaged with the housing 110. The leaf spring 130 is held in an elastically bowed condition between a support formation in the form of a notch 112 on the housing 110 at one end 131, and a holding formation, in the form of a slot 124 on the switch button 120 at its other end 132. The leaf spring 130 is further movable between a first bowed condition in which the leaf spring is bowed to one side and a second bowed condition in which the leaf spring 130 is bowed to the other side.

Slot designs in wide metal lines

SLOT DESIGNS IN WIDE METAL LINESAbstractmethud and stole:tine Fu(' C! in kkci'dP iiaPS P;:dt.ICT tdruss, Ancxampki <anti:Aida-nu, inuthod nfri for Sim I iREtCOU CCL s:twoure comprising: thiercouneu comprising'a wide line. 'The wide line has a firD slot, Tim first slot is it:pact:id n that dirt:Inc:it from n via plug so that thie first slot retiovns strass nn the 'Nicht line and the via plug. The gia plug an centdct the wale line From above: or halotv. Anutho emegpleibodnnent is ii dual thHIPP:Ceiltf ".1:10.PItorweciE tin-ware comprising: an dual drunacetio shaped imonfioniturit cornprining a via ping, a Uriitt chu and a wide line The. vitifle Fun has the fftnit sit:it. "lilt first tilot itt spwxgl a first distance Fro :m zhe via plug so that the: find slN ruhrtve:t stress nu the wide line and the via plug.FIGURE IBI

Handler for semiconductor singulation and method therefor

A WATER JET HANDLER (200) HAS A LOADING LOCATION (205), A CUTTING LOCATION (210), AND AN UNLOADING LOCATION (215); AND TWO MOVABLE MOUNTS (240 AND 245). AS A FIRST MOVABLE MOUNT (240) RECEIVES A MOLDED SUBSTRATE AT THE LOADING LOCATION (205), AND TRANSPORTS IT TO THE CUTTING LOCATION (210), A SECOND MOVABLE MOUNT (245) TRANSPORTS SINGULATED SEMICONDUCTOR PACKAGES OF A PREVIOUSLY SINGULATED MOLDED SUBSTRATE FROM THE CUTTING LOCATION (210) TO THE UNLOADING LOCATION (215). AS THE MOLDED SUBSTRATE ON THE FIRST MOVABLE MOUNT (240) IS CUT IN THE X DIRECTION (232) BY A WATER JET, THE SINGULATED SEMICONDUCTOR PACKAGES ARE UNLOADED. THE MOLDED SUBSTRATE IS THEN TRANSFERRED TO THE SECOND MOVABLE MOUNT (245) ON WHICH IT IS CUT IN THE Y DIRECTION (272) TO PRODUCE SINGULATED SEMICONDUCTOR PACKAGES, AS THE FIRST MOVABLE MOUNT (240) RETURNS TO THE LOADING LOCATION (205), WHERE ANOTHER MOLDED SUBSTRATE IS LOADED.

System and method for lead foot angle inspection using multiview stereo vision

The present invention includes a system and method for three-dimensional imaging and analysis of electronic components. Specifically, it permits rapid and reliable inspection of the lead foot angle in integrated circuit packages. A first image capturing device, a second image capturing device and a third image capturing device are arranged in a "corner shape" or "L-shape." The first image capturing device forms the corner and obtains an image of the bottom of the component. The perspective viewing angle of the second image capturing device and the perspective viewing angle of the third image capturing device are orthogonal to each other to allow accurate three-dimensional reconstruction of the lead angles and detection of flaws or bends.

Transfer system for flipping and multiple checking of electronic devices

The present invention includes a transfer system (70) for flipping and checking electronic devices (40, 41, 42, 43). A first rotary device (20) has a plurality of transfer heads (30, 31, 32, 33, 34, 35) configured to pick electronic devices (40, 41, 42, 43) from a wafer table (21) and place the electronic devices (40, 41, 42, 43) on a transfer head (30, 31, 32, 33, 34, 35) of a second rotary device (50). Check stations (22, 23, 24) can be positioned around the first and second rotary devices (20, 50) and configured to inspect or check the electronic devices (40, 41, 42, 43) during the flipping process. The transfer system (70) can further include an imaging device (25, 64) to inspect the accuracy of picking and placing of the electronic devices (40, 41, 42, 43) during the flipping process. The wafer table (21) and the first rotary device (20) are inclined to increase the operation space. The system accurately picks, flips and transfers chips at a high operation speed. FIG. 7 accompanies the abstract.

Integrated circuit system employing low-k dielectrics and method of manufacture thereof

A method of manufacture of an integrated circuit system includes: fabricating a substrate having an integrated circuit; applying a low-K dielectric layer over the integrated circuit; forming a via and a trench, in the low-K dielectric layer, over the integrated circuit; forming a structure surface by a chemical-mechanical planarization (CMP) process; and applying a direct implant to the structure surface for forming an implant layer and a metal passivation layer including repairing damage, to the low-K dielectric layer, caused by the CMP process.

Laser scribing of thin-film solar cell panel

The present invention describes an apparatus (100) for a first laser scribing (P1) on the front electrode of a thin film solar cell panel and a similar apparatus (100a) for subsequent laser scribing (P2, P3) on the semiconductor layer and semiconductor layer/rear electrode. Before starting scribing process P1, the left hand edge or reference line on the left hand edge on a workpiece is aligned substantively parallel to the linear drive (140) before translating the workpiece on the apparatus (100). Similarly, the first and second scribed lines (Lp1, Lp2) formed during the P1 and P2 processes are separately aligned parallel to the linear drive (140) before starting the relevant process (P2, P3). Alternatively, parallelism of the workpiece is carried out for each batch of the workpiece. In both apparatuses (100, 100a), the laser sources (150) are mounted on independently motorised axes.

Laser scribing of thin-film solar cell panel

Laser scribing of thin-film solar cell panel

A method for laser scribing of thin-films for the manufacture of solar cell panels comprises loading a workpiece with the transparent substrate facing downwards in an input station of a first machine; biasing a reference edge of the workpiece against a front and rear stopper associated with a linear drive; translating the workpiece back and forth between the input station and output station and firing two or more laser beams at a first frequency substantially vertically through a space between the input and output stations to pass through the transparent substrate of the workpiece to scribe parallel lines on the front electrodes with reference to the edge of the workpiece in contact with the front and rear stoppers; and indexing the two or more laser sources and repeating the back and forth translation of the work piece between the input and output stations.

Structure and method for fabricating a bond pad structure

Integrated circuit system employing low-k dielectrics and method of manufacture thereof

Broad-spectrum antibacterial and antifungal activity of lactobacillus johnsonii d115

The present invention demonstrated the potential use of Lactobacillus johnsonii D115 as a probiotic, as a prophylactic agent or as a surface treatment of materials against human and animal pathogens such as Brachyspira pilosicoli, Brachyspira hyodysenteriae, Shigella sonnei, Vibrio cholera, Vibrio parahaemolyticus, Campylobacter jejuni, Streptococcus pneumoniae, Enterococcus faecalis, Enterococcus faecium, Clostridium perfringens, Yersinia enterocolitica, Escherichia coli, Klebbsiella pneumoniae, Staphylococcus aureus, Salmonella spp., Bacillus cereus, Aspergillus niger and Fusarium chlamydosporum. The proteineous antimicrobial compound was partially characterized and found to be heat tolerant up to 121°C for 15 min, and acid tolerant up to pH1 for 30 min at 40°C. The compound is also stable to enzymatic digestion, being able to retain more than 60% antimicrobial activity when treated with pepsin and trypsin.

System and method for peeling a semiconductor chip from a tape using a multistage ejector

A system and method for peeling a semiconductor chip from a tape using a multistage ejector is disclosed. A housing in the multistage ejector houses a plural sets of tape removing contacts. A pick and place unit is moved slowly to have contact with the chip. A vacuum source is utilized for generating vacuum to suck the tape. Plural sets of contacts such as inner, middle and outer contacts are independently or together moved below the tape at various stages by utilizing their respective actuation mechanism. A controller can independently control the movements of each contact to effectively remove or loosen the tape from the chip. A pick and place unit can then pick up the chip easily without any damage to chip.

Broad-spectrum antibacterial and antifungal activity of Lactobacillus johnsonii D115