ЭЛЕКТРОННАЯ СХЕМА ЗАМЕДЛЕНИЯ И СХЕМЫ ЗАДЕРЖКИ

Изобретение относится к области взрывных работ и касается детонаторов с электронным замедлением, в частности к программируемым детонаторам с электронным замедлением инициирования. Технический результат - повышение надежности работы детонаторов. Схема электронного замедления, используемая для инициирования с замедлением детонаторов, содержит генератор, программируемую схему таймера и схему управления работой. Генератор вырабатывает тактовый сигнал, который определяется скоростью разрядки конденсатора по отношению к опорному напряжению REF. Второй конденсатор заряжается до напряжения, которое превышает REF, и, когда напряжение первого конденсатора падает ниже значения REF, вырабатывается внутренний сигнал, и конденсаторы переключаются таким образом, что первый конденсатор заряжается, в то время как второй конденсатор разряжается. Фиксатор вырабатывает импульсы тактовой частоты в соответствии с внутренними сигналами. Схема программируемого таймера включает счетчик колебаний и группу программирования ...

КОММУТИРУЮЩЕЕ УСТРОЙСТВО С ЗАЩИТОЙ ОТ ТОКОВОЙ ПЕРЕГРУЗКИ

Коммутирующее устройство содержит нагрузку (1), триак (2), схему управления, состоящую из формирователя импульсов (6), электронного выключателя (9), порогового устройства (15) и каскада задержки времени (12); нагрузка включена (1) в силовую цепь триака (2), к управляющему электроду триака (5) подключен выход (7) формирователя импульсов (6); вход формирователя импульсов (8) подключен к выходу Q электронного выключателя (9); вход электронного выключателя (11) подключен через устройство задержки времени (12) к выходу (18) порогового устройства (15), пороговое устройство выполнено с чувствительным к отрицательному напряжению входом (16) и подключено этим входом к управляющему электроду (5) триака (2). Устройство позволяет защитить нагрузку от токовой перегрузки, защитить электродвигатель от аварии при заклинивании. В качестве порогового устройства может быть применен аналоговый компаратор, оптрон или n-p-n транзистор, включенный по схеме с общей базой. Технический результат - повышение надежности ...

ЛИНИЯ ЗАДЕРЖКИ

Изобретение относится к устройствам передачи информационного сигнала и может найти применение в системах управления, контроля, измерения, вычислительных устройствах, устройствах связи и других устройствах различных отраслей техники. Линия связи содержит однотактный D-триггер, управляемый посредством схем ИЛИ, ИЛИ-НЕ, а также генератор прямоугольных импульсов, двоичный счетчик импульсов и дешифратор. Устройство позволяет сдвигать во времени короткий импульсный сигнал и изменять после сдвига его длительность. 1 ил.

РЕЛЕ ВРЕМЕНИ

Изобретение относится к импульсной технике и может быть использовано в качестве таймера в системах управления. Достигаемый технический результат - повышение достоверности функционирования. Реле времени содержит блок управления, электромагнитные реле, резистор, контрольный выход, плюсовую шину источника питания, выходы и общую шину. 2 ил.

Электронный таймер

Использование: изобретение относится к импульсной технике и позволяет уменьшить время, необходимое для задания временной уставки, и повысить полноту контроля. Сущность изобретения: электронный таймер содержит исполнительный ключ ...

РЕЛЕ ВРЕМЕНИ

Реле времени, содержащее ключ на транзисторе, исполнительное реле, кнопку запуска, времязадающий конденсатор, зарядный резистор, подключенный первым выводом к первой шине источника питания, резистор, первый вывод которого подключен к базе транзистора ключа, отличающееся тем, что, с целью повышения стабильности выдержки времени за счет исключения влияния времени срабатывания кнопки запуска, в него введено пусковое электромагнитное реле, ограничивающий резистор, подключенный между эмиттером транзистора ключа и второй шиной источника питания, а коллектор транзистора ключа подключен через последовательно соединенные обмотку исполнительного реле и его замыкающий контакт, параллельно которому подключена кнопка запуска, к первой шине источника питания, причем первый вывод времязадающего конденсатора соединен с второй шиной источника питания, второй вывод подсоединен через размыкающий и замыкающий контакты пускового электромагнитного реле соответственно к второму выводу зарядного резистора и второму ...

Устройство задержки

Реле времени

Реле времени

Элемент выдержки времени

Изобретение относится к автоматике и импульсной технике, в частное- ти к импульсным и потенциальным логическим устройствам транспортных средств, и может быть использовано в качестве реле времени. Целью изобретения является расширение предела вьщержки времени. Дпя достижения этой цели в злемент вьщержки времени дополнительно введены два резистора и транзистор с полярностью, противоположной полярности выходного транзистора. На чертеже показаны мостовая схема с конденсатором 1 и источником питания 2 в диагонали моста , плечи которого выпо лнены зарядным резистором 3, входным ключом 4, диодом 5 разрядным резистором 6, соединенным с базой выходного транзистора 7, резистор 8, ограничительный диод 9, разделительный диод 10, резистор 11, транзистор 12 с резисторами 13 и 14 соответственно в базовой и коллекторной цепях. Резистор 6 шунтируется цепью из открытого транзистора 12 и резистора 14. Это обеспечивает независимость тока базы транзистора 7 от тока разряда конденсатора 1 и, следовательно, от ...

Формирователь временных интервалов

Изобретение относится к импульсной технике и может быть использовано в цепях автоматического выключения различной аппаратуры . Цель изобретения - расширение функциональных возможностей формирователя временных интервалов за счет увеличения времени срабатывания и расширения диапазона регулировки времени срабатывания . Импульс с выхода первого разряда счетчика 1 заряжает конденсатор 6. Ток заряда создает на блоке 7 падение напряжения , которое закрывает транзистор 2. На счетный вход счетчика 1 импульсы не поступают . После разряда конденсатора 6 транзистор 2 открывается и импульсы вновь поступают на счетный вход счетчика 1. 1 з.п.ф-лы, 2 ил.

Бесконтактное реле времени

Реле времени

Устройство задержки

Устройство для задержки импульсов

Реле времени

Управляемая линия задержки импульсных радиосигналов

Реле времени

Изобретение относится к автоматике и импульсной технике и может быть использовано в аппаратуре различного назначения, например в программно-временных устройствах,Целью СИ изобретения является повышение помехозащищенности реле времени при сохранении его точности. Реле времени содержит блок 1 управления, элементы ИЛИ 2 и 10, интегратор 3, пороговый элемент А, инверторы 5 и 8, элемент ИЛИ-НЕ 6, элементы И 7, 9 и 12,триггер 11, генератор 13, счетчик 14 импульсов , дешифратор 15, входную шину 16 и выходную шину 17, Предлагаемое реле времени позволяет формировать выходной сигнал с высокой точностью временной задержки и может быть использовано в системах с высоким уровнем помех. Возможная реализация блока управления приводится в описании изобретения, 5 ил. i (Л II 00 to О) о СХ) ...

Устройство задержки

Реле времени

Реле времени

Реле времени

Реле времени

Способ функционального регулирования времени задержек электрических сигналов

Реле времени

Устройство задержки

Полупроводниковое реле времени

Реле времени периодических включений

Программное устройство для выдачи импульсных команд

Устройство выдержки времени

Устройство для регулирования задержки входного сигнала

PEЛE BPEMEHИ

Устройство задержки

Реле времени

Реле времени

Реле времени

Реле времени

Таймер

Изобретение может быть использовано в многоканальных реле времени, Цель изобретения - расширение функциональных возможностей и упрощение устройства таймера при увеличении количества временных интервалов. Таймер содержит запоминающие устройства 2-1 - 2-2, счетчики 4-1 - 4-2, блок (Б) 5 набора временных интервалов, устройство 6 устранения дребезга, Б 8 управления, Б 12 установки канала записи, кнопку 13 Пуск, генератор 14, дешифраторы 15-1 - 15-2 и индикаторы 16-1 - 16-2, В описании изобретения дана электрическая схема Б 8 управления. 1 з.п. ф-лы, 2 ил. Раг. 1 ...

Реле времени

Реле времени

Устройство задержки

Реле времени

Изобретение может быть использовано в устройствах aвтo aтики различного назначения , в частности, применяе.мых в станкостроении . Изобретение уменьшает потребляемую мощность и повышает надежность работы реле, что достигается предложенной схемой построения. Реле содержит резисторы , показанные на чертеже, выпрямитель на диодах 2, 3, 4 и 5, конденсатор 6 фильтра, стабилитрон 8, параллельно которому подключен узел 9 установки исходного состояния , выполненный на транзисторе 10, конденсатор 13, генератор 14, счетчик импульсов 15, выходной усилитель 16 на транзисторе 17 с электромагнитным реле 18 в коллекторной цепи, резисторах 19 и .20 и диоде 21. Усилитель 16 подключен параллельно резистору 7 параметрического стабилизатора. Клеммы 22 и 23 служат для подачи напряжения питания. Стабилитрон и стабилизированная часть схемы запитываются в основ- юм током выходного усилителя. 1 ил. G S ...

Реле времени

Реле времени

Автоматический выключатель с задержкой на выключение

Изобретение относится к импульсной технике и может быть использовано для включения и выключения различных устройств, в частности, бытовой радиоаппаратуры. Цель изобретения - повышение надежности достигается путем уменьшения влияния параметров входных импульсов на время задержки на выключение. Автоматический выключатель содержит первый и второй триггеры, 1 и 2, первый и второй конденсаторы 6 и 11, первый и второй диоды 10 и 12, шину 8 питания, входную 3 и выходную 7 шины. При прекращении импульсов на входе 3 через время заряда конденсатора 11 опрокинется триггер 2, затем через время заряда конденсатора 6 опрокинется триггер 1. На выходе 7 установится уровень логической 1. 1 ил.

Дискретно-аналоговая линия задержки

... 1. ДИСКРЕТНО-АНАЛОГОВАЯ ЛИНИЯ ЗАДЕРЖКИ, содержащая генератор тактовых импульсов триггера, блок преобразования, включенный между источником сигнала и входом первого запоминающего звена, запоминающие звенья, образованные из двух параллельно включенных нечетных и четных запоминающих ячеек, каждая из которых содержит ключ записи и ключ считывания , соединенные с одной пластиной накопительного конденсатора, также операционные усилители, подключенные между выходами и входами запоминающих звеньев, отличающаяся тем, что, с целью повышения точности, в нее введены вторые ключи записи и вторые ключи считывания, входящие в нечетные и четные запоминающие ячейки, а также дополнительные запоминающие ячейки, включенные своими входами на инвертирующие входы соответствующих операционных усилителей, неинвертирующие входы которых соединены с общей шиной, а своими выходами- - не выходами соответствующих операционных усилителей, причем накопительные конденсаторы дополнительных запоминающих- ячеек подключены ...

Устройство задержки импульсов

Фотореле

Устройство для запоминания начальной фазы напряжения

Реле времени

Электронное реле времени

ЭЛЕКТРОННОЕ РЕЯЕ ВРЕМЕНИ, содержащее ячейку памяти и узел обратной связи, состоящий из двух диодов , двух триодов, четырех резисторов и времязадающей КС-цепи, отличающееся тем, что, с целью уменьшения времени готовности реле к последующему пуску, в узел обратной связи введена вторая времязадающая КС-цепь, при этом инверсный выход ячейки памяти подключен к эмиттеру первого триода, .коллектор первого триода соединен с динамическим сбрасывающим входом ячейки памяти, первым выводом конденсатора первой RC-цепи и через резистор с положительной шиной питания, база первого триггера соединена с одним выводом конденсатора и одним выводом резистора второй RC-цепи и с анодом первого диода, катод которого соединен с анодом второго диода, а катод второго диода подключен к нулевой шине пита- ния, второй конец резистора второй RC-цепи подключен к положительной шине питания, база второго триода - к второму выводу конденсатора и пер (/) вому выводу резистора первой ЛС-цепи, второй вывод этого резистора подключен ...

Реле времени

Реле времени

РЕЛЕ ВРЕМЕНИ, содержащее времязадающую RC-цепь, первый диодный мост, однонаправленная диагональ которого через балансные резисторы подключена между шинами источника питания, непроводящая диагональ подключена к выходу операцион- кого усилителя и через нагрузочный резистор к общей шине, ключевой блок, два входа которого подключены к од:нонаправленной диагонали первого ди1 одного моста, отличающееся тем, что, с целью расширения функциональных возможностей, в него введены два диодных моста, однонаправленная диагональ каждого из которых через соотвеЕствующие балансные резисторы подключена между шинами источника питания, ограничитель напряжения и нормирующий резистор , причем конденсатор времязадающей КС-цепи включен в,непроводящую диагональ второго диодного моста, между точкой соединения нагрузочного резистора с непроводящей диагональю первого диодного моста и входом опе1 рационного усилителя,выводы непроводящей диагонали третьего диодного моста включены между входом операционного усилителя ...

Устройство выдержки времени на включение

Реле времени

Линия задержки импульсов

Schaltungsanordnung zum Beeinflussen des Schaltzustandes eines Relais ueber eine vorbestimmte Zeit

ON/OFF delay circuit for consumer appliance circuit e.g. baking oven ventilation motor comprises RC timer system

Circuit for delayed ON and OFF of consumer appliance contains timer, incorporated in control circuit activated by closing of switch. Timer contains RC members for run-up and run-down delay, while timer output delays switch-on of consumer appliance. Breaking of switch starts run-down delay, during which consumer appliance is switched-off. Preferably current supply of electronic module takes place via different current paths during run-up delay period, operating period and in run-down delay period, so that run-up and run-down delay times are independent.

Zeitrelais

Delayed switching circuit for power supply - disconnects supply after given delay when equipment is moved

The switching circuit has a switch (4) responding to the movement of the electrical equipment (1) whose power supply (Battery) (3) the switching circuit controls. A change in the state of this switch sets a delay circuit (14-16), which interrupts or reduces the supply of current to the equipment after its delay has expired if the switch state does not change for a second time. The current supply is also interrupted or reduced on the basis of measured signal (if used e.g. in a voltmeter, ammeter, etc.). The interruption is accomplished by a load switch (12). The supply for the delay circuit is taken upstream of the load switch. The interruption depends solely on whether the equipment is moved and not necessarily on the presence of any input signal.

Transduktorschaltung zur Erzeugung einer einstellbar zeitabhaengigen Sollwertspannung

Schlummerzeitgeber für audiovisuelle Geräte und Verfahren zum Betrieb eines solchen Zeitgebers

Elektronischer Zeitgeber

ELEKTRONISCHE ZEITTAKTSCHALTUNG

Kühlgerät mit Netzschalter

ELEKTRISCHE SCHALTUHR

SICHERHEITSSCHALTUNG MIT ZWEI GETRENNTEN ZEITKREISEN

SCHALTUNGSANORDNUNG ZUR REGELUNG DER SCHALTVERZOEGERUNG UND/ODER VERLUSTLEISTUNGSAUFNAHME VON INTEGRIERTEN FET- SCHALTKREISEN

TIMER FOR A CAMERA

... 1361428 Delayed shutter actuation NIPPON KOGAKU KK 27 Sept 1971 [30 Sept 1970] 44914/71 Heading G2A [ Also in Division H3] An electronic timing circuit for a camera includes a pulse generating circuit which consists of two similar timing sections T1-T7, T11-T16 each producing an output a given time after receiving an input, the outputs being used to trigger the start of the opposite timer circuit and also being combined in an AND gate T7, T8, T10 to produce at T9 the desired output timing signal. The circuit permits repetitive, timedelayed or time-limited photography with cine or motor-driven still cameras. Starting with the switches SW1 to SW4 set as shown in Fig. 2, closure of SW1 connects the battery to the normally conductive T2, and C1 starts to charge through R1 at (t 0 ) Fig. 3 (not shown). When C1 voltage is sufficient to turn on T3-T4 (t 1 ), T5 is also turned on and T7, T6 latch T5 in its on state. The emitter of T8 thus goes high enough relative to the collector of the normally ...

DETECTOR FOR ALTERNATING-CURRENT SIGNALS

... 1435910 Signal detector circuits COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS CIT-ALCATEL 31 Dec 1973 [29 Dec 1972] 60250/73 Heading H3T In a detector for alternating current signals comprising a first rectifier D2 connected to receive the A.C. input signal E1, E2 and a first capacitance C2 charged by the rectifier and shunted by first and second resistances B1 R2 in series, the second resistance R2 is shunted by a second capacitor C3, of larger capacitance than C2, in series with a second rectifier D3 output terminals S1 S2 are connected across the second resistance R2. The forward conduction direction of the second rectifier D3 is such that the second capacitor C3 charges with a predetermined time constant and smooths the output of the first rectifier D2 when an A.C. signal appears at the input of the detector and the second rectifier D3 isolates the charge on the second capacitor C3 the output terminals S1 S2 when the A.C. input signal disappears. The output S1, S2 may be used connected ...

RELAYRELEASE DELAY CIRCUIT

... 1386011 Delayed release circuit for a relay GTE AUTOMATIC ELECTRIC LABORATORIES Inc 2 May 1972 [3 May 1971] 20445/72 Heading H3T A delayed release relay circuit comprises first and second relay operating paths in parallel the first controlling the second via a voltage stabilized time delay circuit and an amplifier whereby the second circuit releases the relay after a delay following the opening of the first circuit. As shown, closure of switch SW operates the relay, discharges the timing capacitor C1 and, via Q1, causes the alternative operating circuit Q2 for the relay to conduct. Opening contact SW allows C1 to change negatively and when its voltage reaches the reference voltage applied to the emitter of transistor Q1 the transistor cuts off causing Q2 to cut off and release the relay. The reference voltage is derived via Q3 from a potentiometer, R6, R7 connected across the charging supply for C1 so that the delay period does not vary with variations in the supply voltage.

SOLID STATE TO,ER

... 1408157 Pulse generators SPRAGUE DEVICES Inc 28 Nov 1972 54959/72 Heading H3T A solid state timer comprises a trigger circuit 70-77 for generating clock pulses of predetermined repetition rate, a frequency divider including cascade connected bi-stable units 92- 97, an arrangement 113-129 for resetting the divider after delivery of an output signal to a load circuit 100-109 and a switch 87 responsive to the output signal for providing an additional charging path for the trigger circuit so as to increase the clock repetition rate. The trigger circuit includes a unijunction transistor 74 and a normal charging path including RC components 70-72. In operation, the output of the divider 92-97 formed after a predetermined delay turns off transistor 100 for activating a relay via transistors 102, 109. Circuit elements 121-124 are provided for inhibiting a system race condition as power is switched on. The divider may be reset when its output becomes low and a high output is produced at the output ...

Improvement in or relating to electronic timers

... 1,087,678. Transistor line delay switches. G. V. CONTROLS Inc. July 26, 1966 [July 28, 1965], No. 33648/66. Heading H3T. A time delay circuit comprises a bridge having a pair of ratio arms 14 and 11, 13 and a pair of timing arms 22, 21, a base emitter path of a transistor T 1 connected between the junction of the ratio arms and the junction of the timing arms and the transistor and an electronic switch T 3 connected in series across the other diagonal of the bridge. In operation of the circuit shown, upon making switch S, capacitor 21 charges through resistor 22 until its potential at the base of T 1 exceeds the bias at its emitter, whereupon the transistor commences to conduct. The voltage change at its collector is amplified by T 1 to render T 3 , conducting so that regenerative action rapidly switches on the transistors. The voltage change at the emitter of T 3 renders a thyristor 40 conductive to energize the load connected at 0. The capacitor rapidly discharges through the base-emitter ...

Improvements in or relating to electric timing devices

... 542,461. Electromagnetic relays. IGRANIC ELECTRIC CO., Ltd., and TAYLOR, J. R. Jan. 29, 1941, No. 1176. [Class 38 (v)] In a timing device wherein opening of contacts 2 causes a condenser 4 to discharge through a winding 1 so as to delay the de-energization thereof, the discharging circuit includes a resistance 5 which is not included in the charging circuit for the condenser. This is effected by means of a switch 8 which is operated simultaneously with the switch 2. Thus the condenser 4 charges quickly and discharges slowly.

Time lag switching device

In a two-terminal timer, particularly for lights 1, momentary closure of a switch 3 resets an intergrated circuit timer 10 and discharges a capacitor C1 in the direction A to B through the coil 4 of a latching relay thereby closing relay contacts 5 to energise the lights 1. When the timer 10 times out, a transistor 11 is turned on to discharge a capacitor C2 in the direction B to A through the coil 4 thereby opening contacts 5 to turn the light 1 off. The timing period can be extended by momentary closure of switch 3 before the timer 10 times out, but not by maintaining switch 3 closed. In an alternative enbodiment, (Fig 3), the latching relay is of the type having two coils (12). ...

Input activated and resettable timer

A microphone senses a sound generated by the user clapping his hands and converts the sound into an electric signal which is applied to a flip-flop circuit to set the latter. The output of the flip-flop circuit is supplied through a time constant circuit to a drive and control circuit for operating a sound generating device having a reproducing stylus and a recorded disk. A reset signal producing circuit is provided to produce a reset signal for the flip-flop circuit when a second sound is sensed by the microphone within a predetermined time period set by the time constant circuit, thereby stopping the operation of the sound generating device.

TIMER

TIMER

A timer device, which displays a load operation state, includes a clock counter, a load counter, a display and a controller. The display displays a count value of the load counter when the load counter is counting and displays a count value of the clock counter otherwise. The controller causes the display to flash in synchronism with the changing of the count of the load counter when the load counter is being operated.

FREQUENCY GENERATING CIRCUIT

Improvements in or relating to generators for generating time-related signals

A voltage comparator with several parallel output channels connected to respective threshold circuits is responsive to the increase of the charge voltage of a capacitor with a linear variation of output currents in the channels. The different output currents, equal or different to each other but all with the same variation rates, are converted into control voltages of the threshold circuits, which are of different value but change with identical rates, so as to reach the threshold value of the respective threshold circuits at different times. From the outputs of the threshold circuits there exit the desired timely connected synchronously related signals, which may be either simple leading or trailing fronts or pulses.

ELECTRONIC TIMER OSCILLATOR

DIGITAL TIME FUZE

Method of operation of a fail-safe solid state relay

A method for operating a fail-safe programmable solid-state relay, the method comprising the steps of performing a set of self-tests at an initial start-up and cyclically during the powered state of the solid-state relay, wherein a self-test comprises continuously detecting and comparing a state of the at least one switch with an expected state therefor and wherein if any self-test within the set detects an unexpected state, substantially simultaneously therewith a failure flag is set in a non-volatile memory and the at least one switching circuits are set to a safe or default state; setting an integrity flag and an integrity count flag within the memory when all self-tests in the set are passed; and reading the failure flag from the memory at any subsequent start-up, wherein if the failure flag is not set, the integrity count flag is read and a set of self-tests is performed.

Improvements in or relating to electrical timing circuits

... 1,115,602. Transistor switching circuits. BRITISH TELECOMMUNICATIONS RESEARCH Ltd. 18 July, 1966 [19 July, 1965], No. 30607/65. Heading H3T. [Also in Division G4] A timing circuit for a road traffic signal system comprises a capacitor C forming a Miller integrator circuit with transistors VT2 and VT3. When a contact S1 is closed a step voltage is applied to the base of VT2 causing the capacitor C to discharge until VT4 conducts and operates relay RR. The period timed can be varied by varying the step voltage by adjustment of the resistance RS in the emitter circuit of VT1. If contact S2 is closed the timing circuit is held in its existing state until the contact is re-opened. A Zener diode D6 stabilizes the power supply and diodes D1-D4 compensate for temperature variations. The contacts S1 and S2 may be replaced by transistors (VT7 and VT6 in Fig. 4, not shown).

CONTROL CIRCUIT

A system for releasing floatable underwater equipment or other movable apparatus from movement-preventing securing mechanism

... 1,140,170. Time control of electric circuits. E.G. & G. INTERNATIONAL Inc. May 23,1967 [May 23, 1966], No. 24015/67. Heading G3T. Movable apparatus such as buoyant under water equipment is released from movement preventing securing mechanism by means actuated electrically by a signal released by a time delay means after the latter has received a predetermined number of electrical impulses. Closure of switch S by a rotary cam 7 applies a series of pulses to the base of a transistor Q1 to render it intermittently conducting thereby causing a further transistor Q2 to apply a series of pulses to a relay coil RL. After receiving a predetermined number of such pulses the relay coil RL actuates a switch S1 to energize an electrically operable squib cartridge 8. The latter then releases a linkage Fig. 1 (not shown) connecting a floatable underwater equipment, such a monitoring or sensing apparatus to an anchor or mooring. A tether line may be stored in a container adjacent the floatable apparatus ...

TIMING CIRCUIT

... 1529103 Transistor switching circuits GENERAL SIGNAL CORP 17 Feb 1976 [21 Feb 1975] 06224/76 Heading H3T An electrical timing circuit, for providing a relatively long delay without the need for an unduly large capacitance, comprises a charge storage means 26, a discharge path via 30, 32, 40, 42, 44 for discharging the storage means, a timing means 54 operative in response to charge on 26 to permit the said discharging repetitively for discrete periods spaced by longer intervals, and means for providing an indication, via 66, when 26 is discharged to a predetermined level. In an embodiment, used on a train to delay automatic application of the brakes, the circuit 12 operates continuously as long as a switch 110 is closed, capacitor 26 being maintained charged. If 110 is opened operation of the circuit 12 continues until the charge remaining on 26 is insufficient. Circuit 12 has one time constant provided by the charging of a relatively small capacitor 40 through an FET 30, and another time ...

ELECTRONIC TIME SWITCH

The timing switch described transfers the edges of normalized square wave pulses with delay. In this arrangement, either only the positive or only the negative edges or both edges are optionally delayed by a predetermined time which results in a high degree of immunity to interference signals. The timing switch contains a basic circuit, acting as multivibrator stage, with an operational amplifier (E) operating as analog integrator and a switching transistor (Tr) and an additional circuit, equipped differently depending on the desired delay mode, of diodes (Z1, Z2, D1-D3) and of fixed (R4, R5) and variable (P1, P2) resistors. This additional circuit forms feedback for the multivibrator stage and thus determines the transfer characteristic of the timing switch. The operating delay can be predetermined at the potentiometer (P1) and the drop-out delay can be predetermined at the potentiometer (P2). ...

AUTOMATIC ON/OFF DIGITALLY TIMED SWITCHING DEVICE

Electric delay device

Digital operate/release timer

Operate/release timing circuits are employed to generate time delayed pulse signals, for example, dial pulses, wink signals and other supervisory signals employed in telecommunications signaling systems. Pulse position and pulse width errors and other problems found in prior operate/release timers are resolved by employing a single digital counter and associated control logic elements. The timing circuit is controllably configured into several timer circuit arrangements including an integrating timer, AM timer, integrating timer including coast option, and AM timer including coast option. With the coast option enabled, initial noise immunity in the pulse signal is realized by resetting the counter to an initial state in response to any discontinuity in the input pulse signal until the input pulse signal is continuously present for a predetermined interval. Pulse break, gap and the like immunity is achieved by controlling the counter to count up for a predetermined interval regardless of ...

Improved safety control system including an electromagnetic control device operated by a time delay circuit

... 837,445. Electromagnetic relays. MINNEAPOLIS - HONEYWELL REGULATOR CO. Oct. 19, 1956 [Oct. 21, 1955], No. 31898/56. Class 38 (5). A safety control system for a machine in which both hands of the operator must be used to operate, respectively, a pair of switches and in which when one switch has been operated the other must be operated within a predetermined time thereafter, the time interval being variable from 4 secs. to zero, comprises an A.C. circuit 10, 11 having connected thereacross a rectifier 21 and condenser 20 in series with the normally closed contacts 14, 15 of a pair of manual switches 12, 13, a relay coil 25 being connected across the rectifier and resistors 28, 29 being connected across the rectifier and condenser. The load 32 is energized when the normally open contact 26 of relay 25 and the normally open contacts 16, 17 of switches 12, 13 are closed. In operation the condenser 20 is charged through rectifier 21 and the coil 25 is energized by a pulsating direct current to ...

CONTROL CIRCUITS FOR VEHICLE REAR WINDOW HEATERS

... 1500512 Transistor delay circuits LUCAS ELECTRICAL Ltd 21 Jan 1975 [29 Jan 1974] 03984/74 Heading H3T [Also in Division H2] A control circuit for a vehicle rear window heater 35 comprises a bi-stable circuit 15, 16 biased to occupy a first state, with transistor 15 conducting, when it is connected to a supply 11, switch 21, 21a operable by the bi-stable circuit and occupying first and second positions when the bi-stable circuit is in its first and second states respectively and providing power to the heater 35 when it is in its second position, a normally open switch 31 coupled with the bi-stable circuit to change the state of the latter each time it is operated, and a monostable circuit 33, 37, 42, 46, 49 coupled to the switch 21 and being held in its unstable state when the switch is in its first position, as shown, the monostable being coupled to the base of transistor 16 of the bi-stable to drive the bi-stable to its first state upon reversion to its stable state. When in its first ...

SCHALTUNGSANORDNUNG FUR DIE LINEARE UND BZW. ODER NICHTLINEARE VERANDERUNG DER BREITE ELEKTRISCHER IMPULSE

DEVICE FOR ACTIVATING AT LEAST A TIME-DELAYED IGNITION ELEMENT

ELECTRONIC SWITCH WITH TWO CONNECTIONS

STATIC FREQUENCY CHANGER WITH A DELAY CIRCUIT FOR PWM SIGNALS

Микропрограммное реле времени

Полезная модель относится к области автоматики и вычислительной техники. Технический результат – повышение надежности устройства для коммутации электрических цепей через заданное время. Микропрограммное реле времени содержит: корпус, крышку с циферблатом, колодку внешних подключений, переключатель временных интервалов, механически связанный с трехвыводным переменным резистором, электронный блок, представляющий собой плату, на которой размещены кварцевый резонатор, стабилизатор напряжения, выходное устройство, контактные площадки, микроконтроллер. В микроконтроллер интегрированы тактовый генератор, предварительный делитель частоты, два таймера, аналогово-цифровой преобразователь (АЦП), энергонезависимая память (EPROM) с управляющей микропрограммой, для записи данных в которую используются контактные площадки, процессор, интерфейс SPI. Трехвыводной переменный резистор используется в качестве датчика положения переключателя временных интервалов, формирующего напряжение, которое считывается с помощью АЦП. Для этого вывод подвижного контакта переменного резистора соединен со входом АЦП микроконтроллера, а два других вывода соединены с положительным и отрицательным выводами стабилизатора напряжения, на вход которого подается напряжение питания устройства, поступающее от колодки внешних подключений. 3 ил. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 199 163 U1 (51) МПК H03K 17/28 (2006.01) H01H 43/00 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК H03K 17/28 (2020.05); H01H 43/00 (2020.05) (21)(22) Заявка: 2020114073, 03.04.2020 (24) Дата начала отсчета срока действия патента: Дата регистрации: 19.08.2020 (45) Опубликовано: 19.08.2020 Бюл. № 23 1 9 9 1 6 3 R U (54) Микропрограммное реле времени (57) Реферат: Полезная модель относится к области автоматики и вычислительной техники. Технический результат – повышение надежности устройства для коммутации электрических цепей через заданное время. Микропрограммное реле ...

Pulse generation circuit

A DC source generates a DC voltage between a positive electrode and a negative electrode. An inductive element and a parallel-connected switch-circuits unit are provided in a conductive path extending from the positive electrode to the negative electrode. The parallel-connected switch-circuits unit includes a plurality of switch circuits connected in parallel with one another. The switch circuit opens and closes the conductive path in accordance with a drive signal inputted from a drive circuit. The drive signal causes the plurality of switch circuits to successively perform an ON operation in which the conductive path is closed and then opened. A pulse voltage generation period in which a pulse voltage occurs in the inductive element continuously follows an ON period which is a duration from when the conductive path is closed to when the conductive path is opened.

Switch with improved edge rate control

This documents discusses, among other things, apparatus and methods for a switch circuit including a break-before-make delay and a gradual turn-on. In an example, a switch circuit can include a switch transistor having a control node and coupled to a first node and a second node, a delay circuit configured to receive control information and to provide the control information after a delay interval, and a gradual turn-on circuit configured to receive the delayed control information from the delay circuit and to transition the transistor from the off-state to the on-state over a ramp interval in response to the delayed control information.

Drive circuit with adjustable dead time

A drive circuit includes a first input terminal configured to receive a first input signal, a first output terminal configured to provide a first drive signal, a second output terminal configured to provide a second drive signal, and a mode selection terminal configured to have a mode selection element connected thereto. The drive circuit is configured to generate the first and second drive signals dependent on the first input signal such that there is a dead time between a time when one of the first and second drive signals assumes an off-level and a time when the other one of the first and second drive signals assumes an on-level, and evaluate at least one electrical parameter of the mode selection element and is configured to adjust a first signal range of the first drive signal and a second signal range of the second drive signal dependent on the evaluated parameter and to adjust the dead time dependent on the evaluated parameter.

Power Converter

The present invention provides a power converter including a power semiconductor device, a driver circuit section that outputs a driving signal for driving the power semiconductor device, a buffer circuit section that includes a PNP transistor and an NPN transistor and that outputs a gate voltage for driving the power semiconductor device, a first delay circuit section that receives the driving signal and that generates a first delay signal on the basis of the received driving signal, a first MOSFET that has a drain electrode connected with the output of the buffer circuit section and that is driven on the basis of the first delay signal. A current flows through the buffer circuit section and the first MOSFET on the basis of the received driving signal, the first delay circuit section outputs the first delay signal after the buffer circuit section exits the transient state and turns on, and the gate voltage is applied to the power semiconductor device from the buffer circuit section to turn the power semiconductor device on by the switching operation of the first MOSFET based on the first delay signal. 1. A power converter , comprising:a power semiconductor device;a driver circuit section that outputs a driving signal for driving the power semiconductor device;a buffer circuit section that includes a PNP transistor and an NPN transistor and that outputs a gate voltage for driving the power semiconductor device;a first delay circuit section that receives the driving signal and that generates a first delay signal based on the received driving signal; anda first MOSFET that has a drain electrode connected with an output of the buffer circuit section and that is driven based on the first delay signal, whereina current flows through the buffer circuit section and the first MOSFET based on the received driving signal,the first delay circuit section outputs the first delay signal after the buffer circuit section exits a transient state and turns on, andthe gate voltage is ...

Method for splitting a pattern for use in a multi-beamlet lithography apparatus

The invention relates to a method for splitting a pattern for use in a multi-beamlet lithography apparatus. The method comprises providing an input pattern to be exposed onto a target surface by means of a plurality of beamlets of the multi-beamlet lithography apparatus. Within the input pattern first and second regions are identified. A first region is a region that is exclusively exposable by a single beamlet of the plurality of beamlets. A second region is a region that is exposable by more than one beamlet of the plurality of beamlets. On the basis of an assessment of the first and second regions it is determined what portion of the pattern is to be exposed by each beamlet. 1. A method for splitting a pattern for use in a multi-beamlet lithography apparatus , the method comprising:providing an input pattern to be exposed onto a target surface by means of a plurality of beamlets of the multi-beamlet lithography apparatus;identifying first regions within the input pattern, each first region being a region that is exclusively exposable by a single beamlet of the plurality of beamletsidentifying second regions within the input pattern, each second region being a region that is exposable by more than one beamlet of the plurality of beamlets; anddetermining what portion of the pattern is to be exposed by each beamlet on the basis of an assessment of the first and second regions.2. The method of claim 1 , wherein the assessment of the first and second regions includes:identifying features to be exposed within the pattern;determining, for each feature, whether the features are located within a first region, a second region or both;deciding, for each feature, which beamlet exposes the features on the basis of the determined feature location.3. The method of claim 2 , wherein claim 2 , upon determining that a feature is completely located in a first region claim 2 , deciding includes assigning exposure of the feature to the beamlet configured to expose said first region.4 ...

DC CONNECTION DEVICE

Provided is a DC connection device including a first connector connected to a DC power source side or a load side; and a second connector connected to the first connector. The first connector or the second connector has a semiconductor switch that is turned on when a portion of at least one of terminals of one of the first and second connectors is brought into contact with a terminal of the other of the first and second connectors, and is turned off before the terminal of the one of the first and second connectors is completely separated from the terminal of the other of the first and second connectors. 1. A DC connection device , comprising:a first connector connected to a DC power source or a load; and a second connector connected to the first connector,wherein the first connector or the second connector has a semiconductor switch that is turned on when a portion of at least one of terminals of one of the first and second connectors is brought into contact with a terminal of the other of the first and second connectors, and is turned off before the terminal of the one of the first and second connectors is completely separated from the terminal of the other of the first and second connectors.2. A DC connection device , comprising:a first connector connected to a DC power source or a load, the first connector having a pair of first connection terminals; anda second connector connected to the first connector, the second connector having a pair of second connection terminals to be electrically connected to the first connection terminals,wherein the first connector comprises:a semiconductor switch connected in series between the DC power source or the load and any one of the first connection terminals;a connection-state detecting unit for detecting a relative positional relationship between the second connection terminal and the first connection terminal; anda control circuit for turning on or off the semiconductor switch according to a result detected by the ...

External Power Transistor Control

The present document relates to the control of an external power transistor. In particular, the present document relates to a method and system for avoiding ringing at the external power transistor subsequent to switching of the external power transistor. A driver circuit to generate a drive signal for switching a driven switch between an off-state and an on-state is described. The driver circuit comprises a drive signal generation unit configured to generate a high drive signal triggering the driven switch to switch to the on-state; wherein an output resistance of the driver circuit is adjustable; an oscillation detection unit to detect a degree of oscillation on the drive signal; and a resistance control unit to adjust the output resistance of the driver circuit based on the degree of oscillation on the drive signal.

SWITCHED CAPACITOR CIRCUIT UTILIZING DELAYED CONTROL SIGNAL AND INVERTING CONTROL SIGNAL FOR PERFORMING SWITCHING OPERATION AND RELATED CONTROL METHOD

A switched capacitor circuit includes an inverter, a first capacitor, and a first switch unit. The inverter is arranged to receive a control signal to generate an inverting control signal corresponding to the control signal. The first capacitor is coupled between a first output port and a first node. The first switch unit is arranged to receive a first input signal and a second input signal, and selectively couple the second input signal to the first node according to the first input signal. The first input signal is determined by one of the control signal and the inverting control signal, and the second input signal is determined by the other of the control signal and the inverting control signal. 2. The switched capacitor circuit of claim 1 , wherein the first switch unit is a transistor claim 1 , and a gate claim 1 , a source and a drain of the transistor is coupled to the first input signal claim 1 , the second input signal and the first node claim 1 , respectively.4. The switched capacitor circuit of claim 3 , wherein a delay time by which the first input signal is delayed is determined according to an impedance of the first capacitor and an impedance of the first switch unit.5. The switched capacitor circuit of claim 3 , wherein the delay unit is configured to prevent an oscillation voltage of the first node from being lower than zero.6. The switched capacitor circuit of claim 1 , further comprising:a second capacitor, coupled between a second output port and a second node;a second switch unit, coupled between the first node and the second node, for selectively coupling the first node to the second node according to the first input signal; anda third switch unit, coupled to the second node, for receiving the first input signal and the second input signal, and selectively coupling the second input signal to the second node according to the first input signal.7. The switched capacitor circuit of claim 6 , wherein the first switch unit claim 6 , the second switch ...

Signal transmission circuits

A signal transmission circuit includes a first selection driver configured to generate a first drive signal in response to an input signal and a first selection signal and drive a transmission signal in response to the first drive signal, and a second selection driver configured to delay the input signal by a first delay time to generate a first delay signal. The second selection driver generates a second drive signal in response to the first delay signal and a second selection signal, generates a first code signal in response to the input signal and the second selection signal, and drives the transmission signal in response to the second drive signal and the first code signal.

Low Current Start Up Including Power Switch

The present document relates to a start-up circuit comprising a power switch wherein a circuit charges a supply voltage capacitor. The capacitor provides a supply voltage to a power switch; the power switch forms a switched power converter with a power converter network. The circuit comprises a source and gate interface for coupling the circuit to the power switch; a capacitor interface couples the circuit to the supply voltage capacitor; a start-up path couples the gate interface to the capacitor interface; wherein the startup path provides a voltage at the gate interface which is at or above a threshold voltage of the power switch; and a charging path couples the source interface to the capacitor interface; wherein the charging path provides a charging current to the capacitor interface, when the power switch is in on-state. 1. An electronic circuit configured to charge a supply voltage capacitor , wherein the supply voltage capacitor is intended for providing a supply voltage to a gate of a source-controlled power switch; wherein the power switch forms a switched-mode power converter , in conjunction with a power converter network; and wherein the drain of the power switch is coupled to a mains voltage; wherein the circuit comprisesa gate interface and a source interface intended for coupling the circuit to the gate and a source of the power switch, respectively;a capacitor interface intended for coupling the circuit to the supply voltage capacitor;a start-up path arranged to couple the gate interface to the capacitor interface; wherein the start-up path is configured to apply a voltage at the gate interface, which is at or above a threshold voltage of the power switch; anda charging path arranged to couple the source interface to the capacitor interface; wherein the charging path is configured to provide a charging current to the capacitor interface, when the power switch is in on-state.2. The circuit of claim 1 , whereinwherein a drain and the gate of the power ...

Voltage control of semiconductor integrated circuits

A circuit is disclosed that includes a plurality of voltage control circuits. Each voltage control circuit of the voltage control circuits includes a driver circuit and a switch circuit. The driver circuit is configured to receive a control signal having a series of pulses. The switch circuit is configured to generate a driving voltage when being turned on. The driver circuit alternately turns on and off the switch circuit in accordance with the series of pulses.

COMPARATOR ARCHITECTURE AND RELATED METHODS

A system is disclosed. The system includes a first stage configured to receive Vand V, the first stage including an input transistor pair, wherein the input voltage is coupled to the input transistor pair, the input transistor pair is coupled to ground, and the input transistor pair includes at a common drain a high-gain node having a voltage V. The system further include a second stage coupled to the high-gain node and configured to generate Vbased on a difference between Vand V, the second stage comprising a resistor and an inverter transistor pair, wherein the gates of the inverter transistor pair are coupled to the high-gain node of the first stage and the resistor couples the high-gain node of first stage to a common drain of the inverter transistor pair and is configured to provide and/or draw current to and/or from the high-gain node of first stage. 1. A circuit comprising:a first stage configured to receive an input voltage and a reference voltage, the first stage comprising a reference transistor pair and a clamp transistor, wherein:the reference voltage is coupled to the reference transistor pair;the reference transistor pair is coupled to ground;the reference transistor pair comprises at a common drain a drain-gate node having a drain-gate voltage; anda source of the clamp transistor is coupled to a high-gain node, a gate of the clamp transistor is coupled to a clamp voltage, and gates of the inverter transistor pair are coupled to the high-gain node of the first stage; and', 'the resistor couples the high-gain node of the first stage to a common drain of the inverter transistor pair and is configured to provide and/or draw current to and/or from the high-gain node of the first stage., 'a second stage coupled to the high-gain node and configured to generate an output voltage based on a difference between the input voltage and the reference voltage, the second stage comprising a resistor and an inverter transistor pair, wherein2. The circuit of claim 1 , ...

MICROELECTRONIC CIRCUIT CAPABLE OF SELECTIVELY ACTIVATING PROCESSING PATHS, AND A METHOD FOR ACTIVATING PROCESSING PATHS IN A MICROELECTRONIC CIRCUIT

A microelectronic circuit comprises a plurality of logic units and register circuits arranged into a plurality of processing paths. At least one monitor circuit () is associated with a first register circuit (), said monitor circuit () being configured to produce a timing event observation signal as a response to a change in a digital value at an input (D) of the first register circuit () that took place later than an allowable time limit defined by a triggering signal (CP) to said first register circuit (). A first processing path goes through a first logic unit () to said first register circuit () and is a delay critical processing path due to an amount of delay that it is likely to generate. The microelectronic circuit comprises a controllable data event injection point () for controllably generating a change of a digital value propagating to said first logic unit () irrespective of what other data is processed on said first processing path. Said microelectronic circuit is configured to freeze a first digital value stored in said first register circuit () for a time during which the change generated through said controllable data event injection point () propagates to said first register circuit. 115-. (canceled)16. Microelectronic circuit , comprising:a plurality of logic units and register circuits, said logic units and register circuits arranged into a plurality of processing paths, andat least one monitor circuit associated with a first register circuit of said plurality of register circuits, said monitor circuit being configured to pro-duce a timing event observation signal as a response to a change in a digital value at an input of the first register circuit that took place later than an allowable time limit defined by a triggering signal to said first register circuit;wherein a first processing path of said plurality of processing paths goes through a first logic unit of said plurality of logic units to said first register circuit,and wherein said first ...

SECONDARY CIRCUIT AND TIMING DEVICE FOR APPLIANCE

A circuit configuration is disclosed for use in an appliance includes a power switch configured to open and close a first group of electrical contacts, where the contacts while closed cause the appliance to energize upon a user initiating a use of the appliance. The circuit configuration also includes a primary timing device electrically connected to the first group of electrical contacts, the primary timing device being actuated upon energization of the appliance and the primary timing device being configured to de-energize the appliance after a first time period by opening the first group of electrical contacts. The circuit configuration also includes a secondary timing device electrically connected to the power switch by a second group of electrical contacts, where the secondary timing device is configured to de-energize the appliance after a second time period, where the second time period is set based on the first time period. 1. A circuit configuration for use in an appliance , comprising:a power switch electrically coupled to a power source, the power switch configured to open and close a first group of electrical contacts, wherein the contacts while closed cause the appliance to energize upon a user initiating a use of the appliance;a primary timing device electrically connected to the first group of electrical contacts, the primary timing device being actuated upon energization of the appliance and the primary timing device being configured to de-energize the appliance after a first time period by opening the first group of electrical contacts;a secondary timing device electrically connected to the power switch by a second group of electrical contacts, wherein the secondary timing device is configured to de-energize the appliance after a second time period, wherein the second time period is set based on the first time period, and wherein the second time period is a third time period longer than the first time period.2. The circuit configuration of claim 1 , ...

EXPANSION CONTROL CIRCUIT

An expansion control circuit includes a delay circuit coupled to a first expansion module and a switching circuit coupled to a second expansion module. The switching circuit includes a buffer and a switching module. The buffer is coupled to the first expansion module. The first expansion module outputs a first control signal upon being switched on and outputs a second control signal after a working time. The delay circuit outputs a disconnecting signal upon being switched on. The buffer is switched off upon receiving the disconnect signal. The delay circuit further outputs a connecting signal after a delay time after outputting the disconnecting signal. The buffer is switched on upon receiving the connect signal. The buffer further outputs the second control signal to the switching module upon being switched on. The switching module controls the second expansion module to be switched on v receiving the second control signal. 1. An expansion control circuit comprising:a delay circuit coupable to a first expansion module; and a buffer coupable to the first expansion module, and', 'a switching module configured to couple to a second expansion module;, 'a switching circuit having output a first control signal upon being switched on, and', 'output a second control signal after a preset working time;, 'wherein the first expansion module is configured to enable the buffer to be switched off subsequent to being switched on, and', 'enable the buffer to be switched on subsequent to being switched off;, 'wherein the delay circuit is configured towherein the buffer is configured to output the second control signal to the switching module upon being switched on; andwherein the switching module is configured to control the second expansion module to be switched on upon receiving the second control signal.2. The expansion control circuit of claim 1 , wherein the switching module comprises a first field effect transistor (FET) and a second FET claim 1 , the first FET is switched ...

Circuit and Method for Controlling Charge Injection in Radio Frequency Switches

A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors. A method for controlling charge injection in a switch circuit is disclosed whereby injected charge is generated at resistively-isolated nodes between series coupled switching transistors, and the injected charge is conveyed to at least one node of the switch circuit that is not resistively-isolated. 1. A switch circuit , comprising: (1) a plurality of resistively-isolated nodes, each resistively-isolated node located between a different pair of the switching transistors in series; and', '(2) at least one non-resistively-isolated node located adjacent to one of the plurality of the switching transistors in series;, '(a) a plurality of switching transistors coupled in series to selectively convey a signal from an input of the series coupled switching transistors to an output of the series coupled switching transistors, the series of switching transistors includingand (1) each charge injection control module includes a switch module coupled to a control signal and having an ON-state and an OFF-state; and', '(2) each switch module selectively switches between the ON-state and the OFF-state in response to the coupled control signal, thereby controlling the communication of ...

Delay Line System and Switching Apparatus with Embedded Attenuators

Systems, methods, and apparatus for reducing standing wave reflections between delay line modules are described. The delay line modules include semiconductor switches, particularly MOSFET switches fabricated on silicon-on-insulator (“SOI”) and silicon-on-sapphire (“SOS”) substrates and embedded attenuators.

CHARGE PUMP APPARATUS

A charge pump apparatus is provided. A two-phase clock signal and a four-phase clock signal for respectively driving a two-phase charge pump circuit and a four-phase charge pump circuit are generated according to delay signals of coupling nodes between delay circuits of a ring oscillator circuit. 1. A charge pump apparatus , comprising:a first two-phase charge pump circuit and a first four-phase charge pump circuit coupled in series, wherein the first four-phase charge pump circuit coupled to an output terminal of the first two-phase charge pump circuit; and [ 'a plurality of delay circuits connected in series as a delay circuit chain, wherein an output terminal of the delay circuit chain is coupled to an input terminal of the delay circuit chain, and the input terminal of the delay circuit chain receives an input clock signal; and', 'a ring oscillator circuit, comprising, 'a logic circuit, coupled to the ring oscillator circuit, the first two-phase charge pump circuit and the first four-phase charge pump circuit, wherein the logic circuit generates a first two-phase clock signal for driving the first two-phase charge pump circuit and a first four-phase clock signal for driving the first four-phase charge pump circuit according to a plurality of delay signals of coupling a plurality of nodes between the delay circuits., 'a driving circuit, coupled to the first two-phase charge pump circuit and the first four-phase charge pump circuit, the driving circuit comprising2. The charge pump apparatus as claimed in claim 1 , wherein the delay circuit chain comprises a first delay circuit claim 1 , a second delay circuit and a third delay circuit connected in series claim 1 , the first delay circuit delays the input clock signal claim 1 , the second delay circuit delays an output signal of the first delay circuit claim 1 , the third delay circuit delays an output signal of the second delay circuit claim 1 , and the logic circuit generates the first two-phase clock signal ...

TIMER

A timer may include a power plug, an AC/DC transforming circuit, a relay circuit, a recharging circuit, and a control circuit that includes a relay output, a key input, and an LCD output. The timer may further include a 2.4V battery and a main body. In one embodiment, the key input includes a plurality of buttons. By pressing one or more of these buttons, signals can be transmitted into the key input of the control circuit. The timer may further include an LCD display and the information displayed thereon is transmitted from the LCD output of the control circuit. The power plug can be connected to an AC power source to bring in the power to the AC/DC transforming circuit to generate a 12V DC current that can be transmitted to the recharging circuit to charge the 2.4V battery, as well as providing power to the relay circuit. 1. A timer comprising a power plug to connect to a power source , an AC/DC transforming circuit , a relay circuit , a recharging circuit , and a control circuit that includes a relay output , a key input , an LCD output and an LCD display ,wherein the key input may include a plurality of buttons. By pressing one or more of these buttons, signals can be transmitted into the key input of the control circuit, and the information displayed thereon is transmitted from the LCD output of the control circuit,wherein the LCD display is divided into the following portions: (1) TIMER ON/TIMER OFF; (2) REPEAT ON/REPEAT OFF; (3) RANDOM; (4) DELAY START; and (5) RUN TIME, and the above fie portions are simultaneously displayed.2. The timer of claim 1 , the timer further comprises a 2.4V battery and a main body.3. The timer of claim 2 , wherein the power plug is connected to an AC power source to bring in the power to the AC/DC transforming circuit to generate a 12V DC current that can be transmitted to the recharging circuit to charge the 2.4V battery claim 2 , as well as providing power to the relay circuit.4. The timer of claim 3 , wherein the five portions ...

TRANSISTOR SWITCH INCLUDING INDEPENDENT CONTROL OF TURN-ON AND SLEW RATE

The disclosed transistor switching methodology enables independent control of transistor turn-on delay and slew rate, including charging, during a pre-charge period, a transistor control input to a threshold voltage Vwith a predetermined turn-on delay; and then charging, during a switch-on period, the transistor control input from Vto an operating point with a predetermined slew rate. This methodology is adaptable to load switching applications, for example, to control a high side/low side load switch such that, during the switch on period, the output voltage supplied to the load rises from zero volts to an operating load voltage with the predetermined slew rate. In one embodiment, I_delay and I_slew_rate currents are used to charge the transistor control input respectively during the pre-charge and switch-on periods. In another embodiment, the I-delay and I-slew rate currents are controlled by a replica switch with a control input coupled to the control input of a main switch, with the replica switch characterized by a threshold voltage substantially identical to the main switch threshold voltage V. 1. A transistor switch circuit , comprising{'sub': 'T', 'a transistor switch characterized by a turn-on threshold voltage V; and'} [{'sub': 'T', 'during a pre-charge period initiated by a switch-on signal, charging the transistor control input to Vwith a predetermined turn-on delay; and then'}, {'sub': 'T', 'during a switch-on period, charging the transistor control input from Vto an operating point with a predetermined slew rate.'}], 'switch control circuitry coupled to a control input of the transistor, and configured to independently control turn-on delay and output voltage slew rate, by2. The circuit of claim 1 , wherein the transistor is an NFET coupled to the power source as a high-side switch.3. The circuit of claim 1 , wherein the transistor is a load switch coupled to a load; andwherein the switch control circuitry is configured to control switching the load ...

SEMICONDUCTOR DEVICE

A semiconductor device has a drive unit outputting a first drive signal to a first electrode and a second drive signal to a second electrode, an instruction signal generation unit generating an instruction signal as a basis of the drive signals and a control unit outputting a first control signal as a basis of the first drive signal and a second control signal as a basis of the second drive signal, based on the instruction signal to control the drive unit. The control unit synchronizes the first control signal with the instruction signal, delays a turning-on timing of the second control signal by a predetermined time relative to the instruction signal and determines a turning-off timing of the second control signal based on a previous pulse width of the instruction signal. 1. A semiconductor device for driving a control electrode , which includes a first electrode and a second electrode in parallel , to control turning-on and turning-off of a switching element , comprising:a drive unit for outputting a first drive signal to a first electrode and a second drive signal to a second electrode, to drive turning-on and turning-off of a switching element;an instruction signal generation unit for generating an instruction signal as a basis of the drive signals; anda control unit for outputting a first control signal as a basis of the first drive signal and a second control signal as a basis of the second drive signal, based on the instruction signal to control the drive unit; whereinthe control unit synchronizes the first control signal with the instruction signal, delays a turning-on timing of the second control signal by a predetermined time relative to the instruction signal and determines a turning-off timing of the second control signal based on a previous pulse width of the instruction signal.2. The semiconductor device according to claim 1 , wherein the control unit includes:a delay unit for delaying the turning-on timing of the second control signal;a pulse width ...

RECONFIGURABLE POWER SWITCH CHAINS FOR EFFICIENT DYNAMIC POWER SAVING

Traditionally, designs have been very conservative on power grid design using higher margins than those needed for safe operation. This is especially true for process driver designs which may not have enough data on process characteristics. This invention allows us to recoup these inefficiencies and to speed up the power up/power down dynamically. This invention sequences plural power supply switches serially or in plural parallel sets as set by a wake up mode. 1. A power control system for a power domain on an integrated circuit comprising:a power supply;a plurality of power switches, each having a first terminal connected to said power supply, a second terminal connected to a power supply input of the power domain and an input for control of conduction between said first terminal and said second terminal; and power up the power domain by supplying signals on said outputs to inputs of corresponding power switches to sequentially cause said power switches to conduct until all power switches are turned conduct, and', 'power up the power domain by supplying signals on said outputs to inputs of corresponding power switches to conduct via at least two power switches simultaneously., 'a power supply controller having a plurality of outputs, each output connected to said input of a corresponding power switch, said power supply controller operable to'}2. The power supply control system of claim 1 , wherein:said plurality of power switches is eight power switches; andsaid power supply controller is operable to power up the power domain by supplying signals to conduct via at least two power switches simultaneously by simultaneously causing a first pair of power switches to conduct, following a delay simultaneously causing a second pair of power switches to conduct, following a delay simultaneously causing a third pair of power switches to conduct and following a delay simultaneously causing a fourth pair of power switches to conduct.3. The power supply control system of ...

HYBRID SWITCH INCLUDING GAN HEMT AND MOSFET

A hybrid switch apparatus includes a gate drive circuit producing a gate drive signal, a GaN high electron mobility transistor (HEMT) having a first gate, a first drain, and a first source. A silicon (Si) MOSFET has a second gate, a second drain, and a second source. The GaN HEMT and the Si MOSFET are connected in a parallel arrangement so that (i) the first drain and the second drain are electrically connected and (ii) the first source and the second source are electrically connected. The second gate is connected to the gate drive circuit output to receive the gate drive signal. A delay block has an input connected to the gate drive circuit output and an delay block output is configured to produce a delayed gate drive signal for driving the GaN HEMT. 112.-. (canceled)13. An apparatus comprising:means for producing (i) a gate drive signal on a gate drive output and (ii) a delayed gate drive signal that is delayed relative to said gate drive signal, wherein said gate drive signal comprises an ON state and an OFF state;a first type of electrical switching device having a first gate, a first drain, and a first source;a second type of switching device different from said first type of switching device wherein said second type of switching device includes a second gate, a second drain, and a second source, said first type of switching device and said second type of switching device being electrically connected in a parallel arrangement wherein (i) said first drain and said second drain are electrically connected and (ii) said first source and said second source are electrically connected;wherein said first gate of said first type of switching device is electrically connected to said producing means to receive said delayed gate drive signal and said second gate of said second type of switching device is electrically connected to said producing means to receive said gate drive signal;wherein in said paralleled arrangement said second type of switching device has a source- ...

DRIVE CIRCUIT FOR POWER SEMICONDUCTOR DEVICES

In a general aspect, an apparatus can include a low-side drive circuit configured to control a low-side device of a power semiconductor device pair and a high-side drive circuit configured to control a high-side device of the power semiconductor device pair. The high-side drive circuit can include an input circuit configured to receive an input signal and produce, based on the input signal, a first control signal, from which a latch set signal is produced to turn on the high-side device, and a second control signal, from which a latch reset signal is produced to turn off the high-side device. The high-side drive circuit can further include an overlap-prevention circuit configured to prevent timing overlap between the second control signal and a voltage-recovery period of the high-voltage circuit, where the voltage-recovery period occurs after turning off the high-side device of the power semiconductor device pair. 1. An apparatus , comprising:a low-side drive circuit configured to control a low-side device of a power semiconductor device pair; and [ receive an input signal; and', 'produce, based on the input signal, a first control signal and a second control signal;, 'an input circuit configured to, 'in response to the first control signal, provide a set signal to turn on the high-side device of the power semiconductor device pair; and', 'a high-voltage circuit configured to, 'in response to the second control signal, provide a reset signal to turn off, 'a high-side drive circuit configured to control a high-side device of the power semiconductor device pair, the high-side drive circuit includingthe high-side device of the power semiconductor device pair,the high-voltage circuit including an overlap-prevention circuit configured to prevent timing overlap between the second control signal and a voltage-recovery period of the high-voltage circuit, the voltage-recovery period occurring after turning off the high-side device of the power semiconductor device pair.2. ...

SHIFT REGISTER AND GATE DRIVING CIRCUIT THEREOF

An Nth shift register includes a pull up unit, a driving unit, a first pull down unit, a second pull down unit, and a third pull down unit. The pull up unit is used for providing a first pull up signal according to a first clock signal, a second clock signal, and a starting pulse. The driving unit is used for providing a driving signal according to the first pull up signal and providing a gate signal according to the first clock signal and the driving signal. The first pull down unit is used for pulling down the first pull up signal according to the first clock signal. The second pull down unit is used for pulling down the driving signal according to a second pull up signal. The third pull down unit is used for pulling down the gate signal according to the second clock signal. 1. A shift register comprising:a pull up unit for providing a first pull up signal according to a first clock signal, a second clock signal, and a starting pulse;a third transistor having a control end for receiving the first clock signal, a first end coupled to the pull up unit, and a second end for receiving a low voltage;a fifth transistor having a first end for receiving the first clock signal, and a second end for providing a gate signal;a sixth transistor having a control end for receiving the second clock signal, a first end coupled to the second end of the fifth transistor, and a second end coupled to the second end of the third transistor; anda seventh transistor having a control end for receiving a second pull up signal, a first end coupled to a control end of the fifth transistor, and a second end coupled to the second end of the third transistor.2. The shift register of further comprising a fourth transistor having a control end coupled to the pull up unit claim 1 , a first end coupled to the control end of the fourth transistor claim 1 , and a second end coupled to the control end of the fifth transistor for providing a driving signal.3. The shift register of claim 1 , wherein the ...

REVERSE CONDUCTION MODE SELF TURN-OFF GATE DRIVER

An apparatus includes a switch module, a sense circuit coupled to the switch module and configured to indicate an operating conduction mode of the switch module, and a drive circuit operatively coupled to the switch module to enable and disable forward conducting mode of the switch module. Once the switch module is in forward conducting mode, the drive circuit is configured to maintain enablement of the forward conducting mode even if the sense circuit indicates reverse conduction mode. 1. An apparatus comprising:a switch module;a sense circuit coupled to the switch module and configured to indicate an operating conduction mode of the switch module; anda drive circuit operatively coupled to the switch module to enable and disable a forward conducting mode of the switch module;wherein once the switch module is operating in the forward conducting mode, the drive circuit is configured to maintain enablement of the switch module in the forward conducting mode even if the sense circuit indicates that the switch module is operating in a reverse conduction mode.2. The apparatus of claim 1 , wherein the switch module comprises an IGBT and a diode disposed in anti-parallel with the IGBT.3. The apparatus of claim 1 , wherein the switch module comprises a BIGT.4. The apparatus of claim 1 , wherein the drive circuit is configured to determine whether the switch module is operating in the reverse conduction mode within an interlock time.5. The apparatus of claim 1 , wherein the sense circuit comprises a current sense circuitry configured to determine a polarity of a current flowing through power terminals of the switch module claim 1 , and wherein the sense circuit is configured to determine whether the switch module is operating in the reverse conduction mode based on the polarity of the switch module current.6. The apparatus of claim 5 , wherein the current sense circuitry is configured to provide a current estimation by measuring a voltage across a parasitic inductance ...

ISOLATED OUTPUT SWITCHING CIRCUIT

A semiconductor device includes an output switching device having an input node, an output node, and a control input node. The control input node enables an input voltage applied to the input node to be switched to the output node. A gate pull-down circuit controls the control input node of the output switching device in response to at least one control signal. The gate pull-down circuit activates the output switching device by raising the voltage level of the control input node above the voltage level of the output node and deactivates the output switching device by clamping the control input node to the voltage level of the output node. A gate pull-up circuit receives an enable signal and generates the at least one control signal to the gate pull-down circuit in response to the enable signal. 1. A semiconductor device comprising:an output switching device having an input node, an output node, and a control input node, the control input node enables an input voltage applied to the input node to be switched to the output node;a gate pull-down circuit to control the control input node of the output switching device in response to at least one control signal, the gate pull-down circuit activates the output switching device by raising the voltage level of the control input node above the voltage level of the output node and deactivates the output switching device by clamping the control input node to the voltage level of the output node; anda gate pull-up circuit that receives an enable signal and generates the at least one control signal to the gate pull-down circuit in response to the enable signal.2. The semiconductor device of claim 1 , wherein the gate pull-down circuit includes at least one transistor device to apply a voltage to the control input node to activate and deactivate the output switching device.3. The semiconductor device of claim 2 , wherein the gate pull-up circuit further comprises a slope control circuit to control a slope of the rise and fall ...

DRIVING DEVICE AND SWITCHING DEVICE

In recent years, it has been desired to further shorten the dead time. Provided is a driving device that drives on/off a main switching element to which a free wheeling diode is anti-parallel connected, wherein the driving device includes a determination unit configured to output a determination signal indicating whether free wheeling current is flowing from a source terminal to a drain terminal of the main switching element; and a drive control unit configured to reduce a switching speed when the main switching element is driven from an on-state to an off-state on condition that the determination signal indicating that the free wheeling current is flowing is output. 1. A driving device that drives on/off a main switching element to which a free wheeling diode is anti-parallel connected , the driving device comprising:a determination unit configured to output a determination signal indicating whether free wheeling current is flowing from a source terminal to a drain terminal of the main switching element; anda drive control unit configured to reduce a switching speed when the main switching element is driven from an on-state to an off-state on condition that the determination signal indicating that the free wheeling current is flowing is output.2. The driving device according to claim 1 , wherein the drive control unit reduces a switching speed when the main switching element is driven from an on-state to an-off-state on condition that the determination signal indicating that the free wheeling current is flowing is output at any timing between a time when an opposite switching element connected in series to the main switching element is set in an off-state and a time when the main switching element is set in an off-state.3. The driving device according to claim 1 , wherein the drive control unit performs control in which the main switching element is set in an on-state on condition that it is determined that the free wheeling current is flowing and that an on ...

CURRENT BREAK CIRCUIT, SEMICONDUCTOR DEVICE HAVING THE SAME AND OPERATING METHOD THEREOF

A current break circuit includes a current break control circuit suitable for sequentially outputting a first enable signal and a second enable signal with a time difference in response to at least one control signal, and a current break switch circuit suitable for outputting or blocking a second voltage in response to a first voltage, wherein the current break switch circuit forms a first current path in response to the first enable signal and a second current path in response to the second enable signal when blocking the second voltage. 1. A current break circuit , comprising:a current break control circuit suitable for sequentially outputting a first enable signal and a second enable signal with a time difference in response to at least one control signal; anda current break switch circuit suitable for outputting or blocking a second voltage in response to a first voltage, wherein the current break switch circuit forms a first current path in response to the first enable signal and a second current path in response to the second enable signal when blocking the second voltages.2. The current break circuit of claim 1 , wherein the current break control circuit comprises:a first enable signal output circuit for outputting the first enable signal in response to the at least one control signal; anda delay circuit for outputting the second enable signal after a predetermined time delay from when the first enable signal is applied.3. The current break circuit of claim 2 , wherein the first enable signal output circuit comprises a NAND gate for outputting the first enable signal in response to the at least one control signal.4. The current break circuit of claim 3 , wherein the at least one control signal includes an active mode signal claim 3 , a power on reset signal and a chip enable signal.5. The current break circuit of claim 4 , wherein the first enable signal output circuit further comprises:a first inverter for inverting and outputting the active mode signal; ...

Semiconductor circuit

Provided is a semiconductor circuit. The semiconductor circuit includes: an input node configured to receive an enable signal, a sense enable signal, and a clock signal; and a clock gating circuit configured to output an enable clock signal corresponding to the clock signal while a signal level of the enable signal is at a first level regardless of a signal level of the sense enable signal, when the semiconductor circuit is in a high-voltage mode, and output an enable clock signal corresponding to the clock signal while a signal level of at least one of the enable signal and the sense enable signal is at the first level, when the semiconductor circuit is in a low-voltage mode.

INTEGRATED CLOCK GATER (ICG) USING CLOCK CASCODE COMPLIMENTARY SWITCH LOGIC

Inventive aspects include an integrated clock gater (ICG) circuit having clocked complimentary voltage switched logic (CICG) that delivers high performance while maintaining low power consumption characteristics. The CICG circuit provides a small enable setup time and a small clock-to-enabled-clock delay. A significant reduction in clock power consumption is achieved in both enabled and disabled modes, but particularly in the disabled mode. Complimentary latches work in tandem to latch different voltage levels at different nodes depending on the voltage level of the received clock signal and whether or not an enable signal is asserted. An inverter takes the voltage level from one of the nodes, inverts it, and outputs a gated clock signal. The gated clock signal may be active or quiescent depending on the various voltage levels. Time is “borrowed” from an evaluation window and added to a setup time to provide greater tolerances for receiving the enable signal. 1. A complimentary voltage switched integrated clock gater (CICG) circuit , comprising:a first node configured to pre-charge to a first voltage level in response to a first level of a clock signal and a first level of an enable signal;a second node configured to pre-charge to the first voltage level in response to the first level of the clock signal and the first level of the enable signal;a first latch coupled to the first node, the first latch being configured to latch the first node to a second voltage level in response to a second level of the clock signal and a second level of the enable signal if the enable signal transitions to the second level before or at substantially a same time that the clock signal transitions from the first level to the second level; anda second latch coupled to the second node, the second latch being configured to latch the second node to the first voltage level in response to the second level of the clock signal and the second level of the enable signal if the enable signal ...

DRIVE CIRCUIT AND SEMICONDUCTOR DEVICE

A drive circuit includes one constant voltage circuit for generating a first voltage and a second voltage, a first output circuit connected to the constant voltage circuit to receive the first voltage and the second voltage and receive a gate drive signal, a second output circuit connected to the constant voltage circuit to receive the first voltage and the second voltage and receive the gate drive signal, a first terminal connected to an output of the first output circuit, and a second terminal connected to an output of the second output circuit, wherein a voltage generated by the constant voltage circuit is applied to a plurality of semiconductor switching elements connected in parallel during switching. 1. A drive circuit comprising:one constant voltage circuit for generating a first voltage and a second voltage;a first output circuit connected to the constant voltage circuit to receive the first voltage and the second voltage and receive a gate drive signal;a second output circuit connected to the constant voltage circuit to receive the first voltage and the second voltage and receive the gate drive signal;a first terminal connected to an output of the first output circuit; anda second terminal connected to an output of the second output circuit,wherein the first output circuit applies the first voltage to the first terminal only during a predetermined first period when the gate drive signal rises; after the first period has elapsed, increases a voltage of the gate drive signal and applies the gate drive signal with the increased voltage to the first terminal; and applies the second voltage to the first terminal only during a predetermined second period when the gate drive signal falls, andthe second output circuit applies the first voltage to the second terminal only during the first period when the gate drive signal rises; after the first period has elapsed, increases a voltage of the gate drive signal and applies the gate drive signal with the increased ...

METHOD AND SYSTEM FOR SOFT SWITCHING OF A RELAY

Provided is a system for soft switching of an electromechanical relay in a lighting control system using a sensor to detect a specified non-zero position in the electrical input waveform. Following this non-zero position, an adaptive time delay is applied before activation of the relay coil. An error detection circuit measures a time error between relay operation and the zero electrical input condition. This error signal is used to update the adaptive time delay for future relay operations. Using such a procedure has been shown to limit electrical stress on the relay, and therefore lengthen its life. 1. A method for controlling activation time of a relay , comprising:detecting a specified non-zero position of an input power source waveform;switching a relay contact after detecting the non-zero position in accordance with a delay time quantum;creating an error factor based upon a comparison between the switching and a soft switching behavior threshold; andapplying an adaptive timing process to adjust the delay time quantum until the error factor substantially approaches zero when the threshold is reached.2. The method of claim 1 , wherein the non-zero position can be a positive or negative electrical input maximum; and whereinthe applying is in accordance with soft switching principles.3. The method of claim 1 , wherein the error factor is created by adjusting the delay time quantum.4. The method of claim 3 , wherein the adaptive timing process adjusts the delay time quantum incrementally until the error factor substantially approaches zero.5. The method of claim 1 , wherein the adaptive timing process adjusts the delay time quantum incrementally until the error factor substantially approaches zero.6. A signal detection system for controlling an external device configured to receive an electrical input claim 1 , comprising:a contact;a coil for energizing the contact;a sensor electrically coupled to the contact for identifying a specified non-zero position on an ...

COOPERATIVE CONTROL METHOD FOR POWER SEMICONDUCTOR ELEMENTS CONNECTED IN PARALLEL, CURRENT BALANCE CONTROL DEVICE, AND POWER MODULE

A cooperative control method for a plurality of power semiconductor elements connected in parallel. The cooperative control method includes (1) connecting, in a daisy chain configuration, a plurality of current balance control circuits each for driving a corresponding power semiconductor element, and (2) responsive to an input to cause the power semiconductor elements to simultaneously perform switching operations, comparing current information of each power semiconductor element with that of an adjacent power semiconductor element, and delaying, using the current balance control circuits, turn-on time or turn-off time of each power semiconductor element, upon determining that the turn-on time or the turn-off time is earlier than turn-on time or turn-off time obtained from the current information of the adjacent power semiconductor element. 1. A cooperative control method for a plurality of power semiconductor elements connected in parallel , the cooperative control method comprising:connecting, in a daisy chain configuration, a plurality of current balance control circuits for respectively driving the plurality of power semiconductor elements connected in parallel; and comparing current information of each of the power semiconductor elements with current information of another of the power semiconductor elements that is adjacent to said each power semiconductor element, and', 'delaying, by one of the current balance control circuits corresponding to said each power semiconductor element, turn-on time or turn-off time obtained from the current information of said each power semiconductor element, upon determining that the turn-on time or the turn-off time is earlier than turn-on time or turn-off time obtained from the current information of the another power semiconductor element., 'responsive to an input to cause the plurality of power semiconductor elements to simultaneously perform switching operations,'}2. A current balance control device for driving one of a ...

METHOD FOR SWITCHING OVER A SEMICONDUCTOR SWITCH

A device and a method for switching over a semiconductor switch with a switching signal acting on a control connection of the semiconductor switch, the switching signal being switched over as a response to registering a switchover of an activation signal; a down time being ascertained between the start of the switchover of the switching signal and the switchover of the semiconductor switch; the switchover of the semiconductor switch being delayed by a waiting period, for example by delaying the output of the switching signal and/or changing the signal level, so that an actual switching time, corresponding to a setpoint switching time, between the registration of the switchover of the activation signal and the switchover of the semiconductor switch is obtained. 113-. (canceled)14. A method for switching over a semiconductor switch with a switching signal , the method comprising:providing the switching signal to act on a control connection of the semiconductor switch. wherein the switching signal is switched over as a response to registering a switchover of an activation signal;ascertaining a down time between a start of the switchover of the switching signal and the switchover of the semiconductor switch, wherein the switchover of the semiconductor switch is delayed by a waiting period, so that an actual switching time, corresponding to a setpoint switching time, between the registration of the switchover of the activation signal and the switchover of the semiconductor switch is obtained.15. The method of claim 14 , wherein the switchover of the semiconductor switch is delayed by delaying the start of the switchover of the switching signal and/or by reducing the signal level of the switching signal.16. The method of claim 14 , wherein the semiconductor switch is switched over from a non-conductive state to a conductive state or vice versa.17. The method of claim 14 , wherein the switching signal is switched over from a first level to a second level.18. The method of ...

LEVEL SHIFTER

A level shifter includes a first output terminal and a second output terminal. After an output signal in a high level state is outputted from the first output terminal and an inverted output signal in a low level state is outputted from the second output terminal, a weak driving circuit is connected between the first output terminal and a power supply voltage, and a strong driving circuit is connected between the second output terminal and the power supply voltage. After the output signal in the low level state is outputted from the first output terminal and the inverted output signal in the high level state is outputted from the second output terminal, the strong driving circuit is connected between the first output terminal and the power supply voltage, and the weak driving circuit is connected between the second output terminal and the power supply voltage. 1. A level shifter , comprising:a first strong driving path;a first weak driving path;a second strong driving path;a second weak driving path;a selecting module comprising a first selecting circuit and a second selecting circuit, wherein the first strong driving path is connected between a power supply voltage and a first input terminal of the first selecting circuit, the first weak driving path is connected between the power supply voltage and a second input terminal of the first selecting circuit, the second strong driving path is connected between the power supply voltage and a first input terminal of the second selecting circuit, and the second weak driving path is connected between the power supply voltage and a second input terminal of the second selecting circuit;a first P-type transistor, wherein a source terminal of the first P-type transistor is connected with an output terminal of the second selecting circuit, a drain terminal of the first P-type transistor is connected with a first node, and a gate terminal of the first P-type transistor is connected with a second node;a second P-type transistor, ...

GATE DRIVER

A gate driver is provided. The gate driver amplifies an input control signal to drive gates of high and low side transistors. A high side driving chip amplifies a high side control signal for controlling the high side transistor and outputs the amplified high side control signal to the gate of the high side transistor. A low side driving chip amplifies a low side control signal and outputs the amplified low side control signal to the gate of the low side transistor. An emitter terminal of the gate of the high side transistor is connected to a collector terminal of the low side transistor. The high side driving chip is separately prepared from the low side driving chip. 1. A gate driver amplifying an input control signal to drive gates of high and low side transistors , comprising:a high side driving chip amplifying a high side control signal for controlling the high side transistor and outputting the amplified high side control signal to the gate of the high side transistor; anda low side driving chip amplifying a low side control signal and outputting the amplified low side control signal to the gate of the low side transistor,wherein an emitter terminal of the gate of the high side transistor is connected to a collector terminal of the low side transistor,the high side driving chip is separately prepared from the low side driving chip, andthe low side driving chip comprises a dead time control unit dead-time controlling the low side control signal and generating the dead-time controlled low side control signal, and an output driver amplifying the dead-time controlled low side control signal and outputting the amplified signal.2. The gate driver according to claim 1 , wherein the dead time controller dead-time controls the low side control signal on the basis of the high side control signal.3. The gate driver according to claim 2 , wherein the dead time control unit delivers the low side control signal after a predetermined time passes from when the high side ...

ELECTRONIC CIRCUITRY AND POWER CONVERTER

Electronic circuitry includes a control circuit controlling a drive circuit for a semiconductor device; and a delay circuit receiving a first signal instructing the drive circuit to drive the semiconductor device with first driving force and output the first signal to the control circuit. The delay circuit receives a second signal at an interval of a first time or “n” times of the first time after the first signal is received, “n” being an integer greater than or equal to 2, and the second signal instructing the drive circuit to drive the semiconductor device with second driving force, delays outputting of the second signal for a delay time shorter than the first time, and outputs the second signal to the control circuit after the first signal is outputted and further after the first time or “n” times of the first time and the delay time elapses. 1. Electronic circuitry comprising:a control circuit configured to control a drive circuit for a semiconductor device; anda delay circuit configured to receive a first signal instructing the drive circuit to drive the semiconductor device with first driving force and output the first signal to the control circuit,wherein the delay circuit is configured to receive a second signal at an interval of a first time or “n” times of the first time after the first signal is received, “n” being an integer greater than or equal to 2, and the second signal instructing the drive circuit to drive the semiconductor device with second driving force, andthe delay circuit is configured to delay outputting of the second signal for a delay time shorter than the first time, and output the second signal to the control circuit after the first signal is outputted and further after the first time or “n” times of the first time and the delay time elapses.2. The electronic circuitry according to claim 1 , further comprising:a first detection circuit configured to detect a third signal instructing the drive circuit to put the semiconductor device in ...

SWITCHING POWER CONNECTOR AND ELECTRICAL CONNECTION ELEMENT WITH SAFETY INTERLOCK

An electrical connection element is for a power connector. The power connector includes an electrical component having a number of first electrical mating members. The electrical connection element comprises: a housing including a number of second electrical mating members structured to be electrically connected to the number of first electrical mating members; a contact assembly enclosed by the housing and being electrically connected to the number of second electrical mating members; and an operating mechanism for opening and closing the contact assembly. The contact assembly is structured to electrically connect and disconnect power while the number of first electrical mating members remain mechanically coupled to the number of second electrical mating members. 1. An electrical connection element for a power connector , said power connector comprising an electrical component , said electrical connection element comprising:a housing;a contact assembly enclosed by said housing and being electrically connected to said number of second electrical mating members; anda toggle operating mechanism structured to open and close said contact assembly,wherein said contact assembly is structured to electrically connect and disconnect power while a number of first electrical mating members remain mechanically coupled to a number of second electrical mating members.2. The electrical connection element of wherein said toggle operating mechanism is structured to open and close said contact assembly by a snap-action.3. The electrical connection element of wherein:said toggle operating mechanism includes a toggle linkage, said toggle linkage defining a line of action and a toggle line;said toggle linkage operatively coupled to said contact assembly;said toggle linkage movable between a first configuration, wherein said contact assembly is open, and a second configuration wherein said contact assembly is closed; andwherein when said toggle linkage line of action is on a first side ...

METHODS AND CIRCUITRY FOR SAMPLING A SIGNAL

Circuitry and methods for sampling a signal are disclosed. An example of the circuitry includes a node for coupling the circuitry to the signal being sampled and a plurality of capacitors, wherein each capacitor is selectively coupled to the node by a switch. An analog-to-digital converter is coupled to the node and is for measuring the voltages of individual ones of the plurality of capacitors and converting the voltages to digital signals. Delay circuitry is coupled to each of the switches, the delay circuitry is for closing one switch at a time for a predetermined period. 1. Circuitry for sampling a signal , the circuitry comprising:a node for coupling the circuitry to the signal being sampled;a plurality of capacitors, each capacitor selectively coupled to the node by a switch;an analog-to-digital converter (ADC) coupled to the node for measuring the voltages of individual ones of the plurality of capacitors and converting the voltages to digital signals; anddelay circuitry coupled to each of the switches, the delay circuitry for closing one switch at a time for a predetermined period.2. The circuitry of claim 1 , wherein the signal being sampled is the drain-to-source voltage of a transistor.3. The circuitry of claim 1 , wherein the voltage being sampled is the gate voltage of a transistor.4. The circuitry of claim 1 , wherein the voltage being sampled is one of the drain-to-source voltage or the gate voltage of a transistor during a state change of the transistor.5. The circuitry of claim 1 , further comprising a multiplexer coupled to the node claim 1 , the multiplexer having at least a first input coupled to a first signal being sampled and a second input coupled to a second signal being sampled.6. The circuitry of claim 5 , wherein the first input of the multiplexer is coupled to the drain of a transistor and wherein the second input is coupled to the gate of the transistor.7. The circuitry of claim 1 , further comprising a pulse generator claim 1 , the ...

SYSTEMS, METHODS, AND APPARATUSES FOR TEMPERATURE AND PROCESS CORNER SENSITIVE CONTROL OF POWER GATED DOMAINS

Apparatuses and methods for temperature and process corner sensitive control of power gated domains are described. An example apparatus includes an internal circuit; a power supply line; and a power gating control circuit which responds, at least in part, to a first change from a first state to a second state of a control signal to initiate supplying a power supply voltage from the power supply line to the internal circuit, and continue supplying the power supply voltage from the power supply line to internal circuit for at least a timeout period from a second change from the second state to the first state of the control signal, in which the timeout period represent temperature dependency. 1. An apparatus comprising:an internal circuit;a power supply line; anda power gating control circuit configured to respond, at least in part, to a first change from a first state to a second state of a control signal to initiate supplying a power supply voltage from the power supply line to the internal circuit, and continue supplying the power supply voltage from the power supply line to internal circuit for at least a timeout period from a second change from the second state to the first state of the control signal, wherein the timeout period is configured to represent temperature dependency.2. The apparatus as claimed in claim 1 , wherein the power gating control circuit is configured to reset a detection of the timeout period when a third change from the first state to the second state appears during the timeout period.3. The apparatus as claimed in claim 1 , wherein the temperature dependency is configured to represent that the timeout period is shortened as temperature increases.4. The apparatus as claimed in claim 1 , wherein the power gating control circuit comprises a leakage monitor configured to detect an amount of leakage current of the internal circuit to set the timeout period.5. The apparatus as claimed in claim 4 , wherein the power supply control circuit ...

DRIVE METHOD AND DRIVE CIRCUIT FOR POWER SWITCH, AND POWER SUPPLY SYSTEM

Disclosed a drive method, a drive circuit for a power switch and a power supply system. During the turning-on period of the power switch, which can be roughly divided into three processes, a current limiting module is used to limit the current flowing through the power switch for preventing current overshoot, a logic control module is used for controlling the current limiting module not to operate before the turning-on period and the control terminal of the power switch is turned off; during the turning-on period, a feedback circuit adjusts the gate voltage of the power switch for controlling the current flowing through the power switch to reach a predetermined limited value quickly and then maintain at the limited value until the power switch is fully turned on. The current limiting module can be employed in various embodiments. According to the disclosure, the current flowing through the power switch can be effectively controlled during the turning-on period, and the driving time for turning on the power switch is decreased. 1. A drive method for a power switch , wherein a turning-on period of said power switch comprises:a first process, in which said power switch receives a control signal at a control terminal, when said control signal turns from an ineffective state to an effective state representing turning on, a voltage of said control terminal of said power switch starts to increase, as said voltage of said control terminal increases, said power switch begins to be gradually conductive, and a current flowing through said power switch begins to increase to reach a predetermined limited value;a second process, in which said voltage of said control terminal of said power switch is controlled for maintaining said current flowing through said power switch at said limited value, drain-source impedance of said power switch is reduced and drain-source voltage of said power switch gradually decreases; anda third process, in which said current flowing through said ...

ACCIDENTAL-SHUTDOWN-PROOF SWITCH CONTROL APPARATUS AND METHOD FOR ROBOT-ASSISTED SURGICAL DEVICE

Apparatuses and methods for preventing accidental-shutdown in a robot-assisted surgical device are disclosed. An exemplary control apparatus includes an on/off key configured to trigger a start action or a shutdown action, an on/off control module configured to detect the shutdown action of the on/off key and obtain a shutdown intention through man-machine interaction, and an on/off hardware circuit configured to detect the start action and send a signal to a power supply. The on/off hardware circuit is configured to detect the shutdown action of the on/off key and a shutdown control signal sent by the on/off control module and send a signal to cut off the power supply. The control apparatus can reduce the probability of accidental shutdown caused by system software and hardware failure or man-made mis-operation and improve the operating reliability of the robot-assisted surgical device without significantly increasing cost. 110.-. (canceled)11. An on/off control device , comprising:an on/off key configured to trigger a start action or a shutdown action;an on/off control module configured to detect the shutdown action of the on/off key and obtain a shutdown intention through man-machine interaction; andan on/off hardware circuit configured to send a signal for cutting off power supply based on a hardware shutdown signal triggered by the on/off key and a shutdown control signal sent by the on/off control module.12. The on/off control device of claim 11 , wherein:the on/off key comprises a switch button for toggling between start and shutdown functions; orthe on/off key comprises an on button for starting up and an off button for shutting down.13. The on/off control device of claim 11 , further comprising a system power supply module comprising a power supply on/off control circuit.14. The on/off control device of claim 13 , wherein:the on/off hardware circuit comprises an on/off key detection circuit and a shutdown action circuit;an input terminal of the on/off key ...

POWER SUPPLY DEVICE OF A DISCHARGE CIRCUIT SEQUENCE

The power supply device () includes: 110-. (canceled)11. A power supply device , comprising:a main command input for the activation or deactivation of the power supply device; a command input for the activation or deactivation of the power supply unit depending on a signal originating from the main command input; and', 'a power output adapted to provide a supply current when the power supply unit is activated;, 'a power supply unit, includinga discharge circuit connecting the power output to a reference potential via a controlled switch; and a first charge or discharge timing circuit having a relaxation time during a transitory period in the presence or absence of a power supply signal; and', one input is connected to the main control input of the power supply device;', 'another input is connected to the output of the first timing circuit; and', 'the output is connected for control to the controlled switch;, 'a first logic circuit, in which], 'a control circuit for the controlled switch of the discharge circuit, the control circuit including no activation signal is present on the main control input; and', 'the output of the first timing circuit has reached a value greater than or equal to that provided at an end of the relaxation time of the first timing circuit., 'the first logic circuit being adapted so that the controlled switch is only turned on when the two following conditions are met12. The power supply device according to claim 11 , wherein the first logic circuit is an OR gate.13. The power supply device according to claim 11 , wherein the first logic circuit is an AND gate having two inverting inputs.14. The power supply device according to claim 11 , wherein the first timing circuit includes a capacitor connected between the other input of the first logic circuit and a reference potential and a resistor connected between the other input of the first logic circuit and the command input for the activation or deactivation of the power supply unit.15. The ...

A COMPARATOR FOR CONTROLLING DEAD-TIME BETWEEN SWITCHING TRANSISTORS

This document discloses a comparator that is configured to control dead-time between two or more switching transistors. In particular, it is disclosed that the comparator is configured to generate a suitable delay between the switching “OFF” of a transistor and the switching “ON” of another transistor so that the amount of shoot through current flowing between these two transistors are greatly minimized. 1. A comparator circuit configured to generate a delay between an ON time for a first transistor and an OFF time for a second transistor in a pulser circuit , the comparator circuit comprising:{'sub': PGATE', 'PGATE, 'a gate voltage sensing circuit configured to generate a gate monitoring current Ibased on a detected gate voltage of the second transistor V;'}{'sub': 'PMOS', 'a current sensing circuit configured to generate a drain monitoring current Ibased on a detected drain current of the second transistor; and'}{'sub': CMP.REF', 'PGATE.MON', 'PGATE', 'PMOS.MON', 'PMOS', 'PGATE.MON', 'PMOS.MON', 'CMP.REF, 'a current comparator circuit configured to compare a reference current Ito a sum of a scaled gate monitoring current Ithat is scaled from the gate monitoring current Iand a scaled drain monitoring current Ithat is scaled from the drain monitoring current I, whereby the first transistor in the pulser circuit is turned ON when the sum of the scaled gate monitoring current Iand the scaled drain monitoring current Iis less than the reference current I.'}2. The comparator circuit according to wherein the gate monitoring current Iis directly proportional to a voltage difference between the detected gate voltage of the second transistor Vand a source voltage of the second transistor V.3. The comparator circuit according to whereby the gate voltage sensing circuit comprises:{'sub': 'DDH', 'claim-text': {'sub': PGATE', 'PGATE, 'the switch transistor is configured to regulate the gate monitoring current Iat a drain of the switch transistor based on the detected gate ...

A DEAD TIME CIRCUIT FOR A SWITCHING CIRCUIT AND A SWITCHING AMPLIFIER

A dead time circuit () for a switching circuit is disclosed. The dead-time circuit comprises: an input () for receiving a switching signal of the switching circuit with at least one supply rail having a ground bounce signal; first and second outputs (); a first feedforward path () coupled to the first output and arranged to receive the switching signal; a second feedforward path () coupled to the second output and arranged to receive the switching signal; a first feedback path () forming a first feedback loop between the first output and the second feedforward path; and a second feedback path () forming a second feedback loop between the second output and the first feedforward path; wherein each of the first and second feedforward paths includes a respective first and second delay circuit (), each having a time delay greater than a predetermined time period of the ground bounce signal. A switching amplifier is also disclosed. 1. A dead time circuit for a switching circuit , the dead-time circuit comprising:(i) an input for receiving a switching signal of the switching circuit with at least one supply rail having a ground bounce signal;(ii) first and second outputs;(iii) a first feedforward path coupled to the first output and arranged to receive the switching signal;(iv) a second feedforward path coupled to the second output and arranged to receive the switching signal;(v) a first feedback path forming a first feedback loop between the first output and the second feedforward path; and(vi) a second feedback path forming a second feedback loop between the second output and the first feedforward path;wherein each of the first and second feedforward paths includes a respective first and second delay circuit, each having a time delay greater than a predetermined time period of the ground bounce signal.2. A dead time circuit according to claim 1 , wherein the first feedforward path includes a first logic gate for receiving the switching signal and an output signal from ...

Dv/dt control in mosfet gate drive

An electronic switching circuit having a field effect transistor with a source, a drain, and a gate. A capacitor and resistor are connected in series between a gate and the source of the field effect transistor. The input signal to the circuit is connected at the junction between the capacitor and resistor.

SIGNAL TRANSMISSION CIRCUIT, SWITCH DRIVING DEVICE, AND POWER MODULE

A filter circuit includes a first rise delay circuit that delays a rising time of a first shifted signal by a predetermined time for output and a first fall delay circuit that delays a falling time of a second shifted signal by a predetermined time for output. The first rise delay circuit is configured so that a second rise delay signal does not follow a change in a first voltage toward a decreasing side and follows a change in the first voltage toward an increasing side. The first fall delay circuit is configured so that a second fall delay signal does not follow a change in the first voltage toward a decreasing side and follows a change in the first voltage toward an increasing side. 1. A signal transmission circuit comprising:a level shifter that is actuated with a first voltage and a second voltage, which is lower than the first voltage, and level-shifts each of a first input signal and a second input signal to output a first shifted signal and a second shifted signal; anda filter circuit that is actuated with the first voltage and the second voltage and performs a filtering process on each of the first shifted signal and the second shifted signal, wherein a first rise delay circuit that delays a rising time of the first shifted signal by a predetermined time for output, and', 'a first fall delay circuit that delays a falling time of the second shifted signal by a predetermined time for output, wherein', 'the first rise delay circuit includes a first rise delay NOT circuit that inverts the first shifted signal for output and a second rise delay NOT circuit that inverts a first rise delay signal of the first rise delay NOT circuit,', 'the first fall delay circuit includes a first fall delay NOT circuit that inverts the second shifted signal for output and a second fall delay NOT circuit that inverts a first fall delay signal of the first fall delay NOT circuit for output,', 'the first rise delay circuit is configured so that a second rise delay signal of the ...

HIGH-VOLTAGE SWITCHING CIRCUIT, CORRESPONDING DEVICE AND METHOD

First and second comparators receive input signals of opposed polarities and drive operation of a switch in response thereto. A first current generator supplies a first current to the switch which, in response to the control of the first and second comparators, applies the first current, alternatively, to a first node or a second node. A second current generator sinks a second current from the first node and a third current generator sinks a third current from the second node. A logic circuit has inputs coupled to the first node and the second node, respectively, receives respective switching signals having fast switching wavefronts and delayed switching wavefronts. The output of logic circuit is configured for switching between a first state and a second state with switching between the first state and the second state triggered by the fast switching wavefronts of the respective switching signals. 1. A circuit , including:a first comparator and a second comparator having respective differential inputs configured for receiving input signals of opposed polarities, the first comparator and the second comparator having respective output nodes,a first reference current generator,a switch driven by the output nodes of the first and second comparators, the switch having an input coupled to the first reference current generator and configured to transfer a first current output from the first reference current generator alternatively to a first node and a second node in response to the output nodes of the first and second comparators,a pair of second reference current generators, coupled to the first node and the second node, respectively, wherein second currents of the pair of second reference current generators are applied to the first node and the second node, respectively, with a sign opposite to a sign of the first current,a logic circuit having a first input coupled to the first node and a second input coupled to the second node so as to receive first and second ...

Gate driver and power module

A programmable decoder ( 201 ) includes a counter ( 204 A) whose count value increases for each clock; an address decoder ( 205 A) for converting the count value into an address; a storage ( 251 A) storing a table defining data according to the address converted from the count value; and a latch unit ( 207 ) for latching the data according to the address output from the storage ( 251 A). A variable driver ( 202 ) includes a plurality of MOS transistors ( 208 ), ( 209 ), ( 210 ). The latch unit ( 207 A) has outputs connected to control electrodes of a plurality of MOS transistors ( 208 ), ( 209 ), ( 210 ). The table defines a plurality of data items in the table so that the driving force of the variable driver ( 202 ) increases with an increase of the count value. A counter ( 20 A) updates the count value while the arm control signal is being activated.

Thermal-Type Flow Meter

A thermal-type flow meter for representing a flow rate of air by the frequency of a periodic signal, wherein abnormalities in the waveform of an output signal due to frequency variation is prevented while high-frequency noise is suppressed. The thermal-type flow meter pertaining to the present invention is provided with a plurality of switching elements connected in parallel, and varies a delay width between the switching elements in accordance with variation of the frequency of a periodic signal for representing a flow rate.

Half-bridge gate driver control

A power circuit is described that includes a half-bridge and a driver for controlling a first switch of the half-bridge. The driver is configured to cause the first switch to transition between operating in an on-state of the first switch and an off-state of the first switch based at least in part on a driver signal and a voltage at the half-bridge.

POWER SWITCH DEVICE

Power switch devices and methods are provided where an undervoltage event in a supply voltage is detected. Information regarding the undervoltage event is stored in a memory element. The memory element is supplied by a control signal. 1. A switch device , comprising:a control terminal,a switch, wherein a control input of the switch is coupled to the control terminal,a supply voltage terminal,an undervoltage detection circuit configured to detect an undervoltage of a supply voltage provided to the supply terminal, anda memory element configured to store information regarding a detected undervoltage, wherein the memory element is coupled to the control terminal to be supplied by a signal at the control terminal.2. The device of claim 1 , wherein the memory element comprises a latch.3. The device of claim 1 , wherein the undervoltage detection circuit comprises comparator and a rising edge detection circuit coupled to an output of the comparator.4. The device of claim 1 , further comprising a level shifter coupled between the undervoltage detection circuit and the memory element.5. The device of claim 1 , further comprising a voltage regulation circuit coupled between the input terminal and the memory element.6. The device of claim 1 , further comprising a delay circuit configured to delay switching on of the switch based on the information stored in the memory element.7. The device of claim 6 , wherein the delay is between 1 and 100 ms.8. The device of claim 6 , wherein the delay circuit comprises an oscillator.9. The device of claim 1 , wherein the undervoltage detection circuit comprises an edge detection circuit and a further circuit which provides a signal to the edge detection circuit claim 1 , and further comprising a level shifter arranged between the further circuit and the edge detection circuit or downstream of the edge detection circuit.10. The device of claim 9 , wherein the further circuit comprises a comparator.11. A power switch device claim 9 , ...

H-bridge gate control circuit

A gate control circuit for controlling gates of at least a half side of an H-bridge circuit includes: an input terminal configured to connect to a PWM signal; a power terminal configured to connect to a voltage source that supplies a positive voltage; a ground terminal configured to connect to a ground reference; and a control circuit connected with the input terminal, the power terminal, and the ground terminal. The control circuit includes: two high side switches configured to be connected with the voltage source respectively through the power terminal; two low side switches configured to be connected with the ground reference respectively through the ground terminal; a first inverter connecting the two high side switches; a second inverter connecting the two low side switches; and a first resistor and a second resistor connecting the two high side switches to the two low side switches respectively.

POWER CONVERTER WITH ZERO-VOLTAGE SWITCHING

A power converter circuit includes a power stage that includes a transformer and a switch. The switch can be controlled in response to a PWM signal to provide a primary current through a primary winding of the transformer to induce a secondary current in a secondary winding of the transformer to generate an output voltage. The power stage includes a switching node between the switch and the primary winding having a switching voltage. The circuit also includes a switching controller configured to generate the PWM signal in response to a ramp signal. The ramp signal can have an amplitude of a slope that is proportional to a decay rate of a magnetizing current of the transformer and generated in response to feedback from the power stage. The switch can be activated in response to the switching voltage having an amplitude of approximately zero volts based on the amplitude of the ramp signal. 1. A power converter circuit comprising:a power stage comprising a transformer and a switch, the switch being controlled in response to a pulse-width modulation (PWM) signal to provide a primary current through a primary winding of the transformer to induce a secondary current in a secondary winding of the transformer to generate an output voltage, the power stage comprising a switching node between the switch and the primary winding having a switching voltage; anda switching controller configured to generate the PWM signal in response to a ramp signal, the ramp signal having a slope that is proportional to a decay rate of a magnetizing current associated with the transformer and generated in response to at least one feedback voltage from the power stage, the switch being activated in response to the switching voltage having an amplitude of approximately zero volts based on the amplitude of the ramp signal.2. The circuit of claim 1 , wherein the transformer further comprises an auxiliary winding that is configured to generate an auxiliary voltage claim 1 , wherein the switching ...

CONTROL CIRCUIT, CONTROL METHOD, AND NON-TRANSITORY STORAGE MEDIUM

A control circuit, which is one aspect of the present invention, controls a gate signal input to a semiconductor switching element. The control circuit includes a load signal measuring device, a gate signal generator, and a timing adjuster. The load signal measuring device measures a load signal of the semiconductor switching element. The gate signal generator generates the gate signal on the basis of the load signal. The timing adjuster adjusts a timing of when the gate signal is input to the semiconductor switching element on the basis of a history of the load signal. 1. A control circuit configured to control a gate signal input to a semiconductor switching element , comprising:a load signal measuring device configured to measure a load signal of the semiconductor switching element;a gate signal generator configured to generate the gate signal on the basis of the load signal; anda timing adjuster configured to adjust a timing of when the gate signal is input to the semiconductor switching element on the basis of a history of the load signal.2. The control circuit according to claim 1 , whereinthe timing adjuster sets the timing of when the gate signal is input to the semiconductor switching element prior to a predetermined timing.3. The control circuit according to claim 2 , wherein an adjustment time calculator configured to calculate adjustment time on the basis of a first differential signal related to the load signal appearing during a first input period in which the gate signal is input, and a second differential signal related to the load signal appearing during a second input period in which the gate signal is input; and', 'a gate signal output device configured to output the gate signal, prior to the predetermined timing, to the semiconductor switching element on the basis of the adjustment time., 'the timing adjuster includes4. The control circuit according to claim 3 , a comparator configured to calculate a first time point at which a difference between ...

CONTROLLING A CONTROLLABLY CONDUCTIVE DEVICE BASED ON ZERO-CROSSING DETECTION

A load control device may control power delivered to an electrical load from an AC power source. The load control device may include a controllably conductive device adapted to be coupled in series electrical connection between the AC power source and the electrical load, a zero-cross detect circuit configured to generate a zero-cross signal representative of the zero-crossings of an AC voltage. The zero-cross signal may be characterized by pulses occurring in time with the zero-crossings of the AC voltage. The load control device may include a control circuit operatively coupled to the controllably conductive device and the zero cross detect circuit. The control circuit may be configured to identify a rising-edge time and a falling-edge time of one of the pulses of the zero-cross signal, and may control a conductive state of the controllably conductive device based on the rising-edge time and the falling-edge time of the pulse. 1. A load control device for controlling power delivered to an electrical load from an AC power source , the load control device comprising:a controllably conductive device adapted to be coupled in series electrical connection between the AC power source and the electrical load;a zero-cross detect circuit configured to generate a zero-cross signal representative of zero-crossings of an AC voltage, the zero-cross signal characterized by a plurality of pulses occurring in time with the zero-crossings of the AC voltage; and identify a rising-edge time and a falling-edge time of one of the pulses of the zero-cross signal; and', 'control a conductive state of the controllably conductive device based on the rising-edge time and the falling-edge time of the pulse., 'a control circuit operatively coupled to the controllably conductive device and the zero-cross detect circuit and configured to2. The load control device of claim 1 , wherein the AC voltage comprises an AC voltage generated by the AC power source claim 1 , and the control circuit is ...

TIMING ADJUSTMENT METHOD FOR DRIVE CIRCUIT AND TIMING ADJUSTMENT CIRCUIT FOR DRIVE CIRCUIT

A timing adjustment method for a drive circuit, including: a rise detector for a rise start when a voltage-driven semiconductor element is turned off; a timing signal output unit outputting a speed change timing signal after a set delay time has elapsed from the rise start; and a conduction controller for a conduction control terminal of the semiconductor element using the timing signal, comprises: defining an estimated terminal voltage of the conduction control terminal when a rise completion time elapses; increasing a delay time by a predetermined unit time, and changing the drive signal to a turning off level again, when the conduction control terminal doesn't fall below the estimated terminal voltage after the drive signal is changed to a turning off level before the level is inverted; and determining a delay time, when the conduction control terminal falls below the estimated terminal voltage initially, as a set value. 1. A timing adjustment method for a drive circuit , a rise detection unit that detects a rise start of an inter-conduction-terminal voltage of a voltage-driven semiconductor element when the voltage-driven semiconductor element is turned off;', 'a timing signal output unit that outputs a speed change timing signal after a set delay time has elapsed from detection of the rise start; and', 'a conduction control unit that initially discharges a conduction control terminal of the voltage-driven semiconductor element at a high speed, and changes a discharge speed to a low speed after the speed change timing signal is input, when the voltage-driven semiconductor element is turned off in response to an input drive signal,, 'the drive circuit includingthe timing adjustment method of adjusting a delay time set to the timing signal output unit, the method comprising:defining a time interval, from the rise start of the inter-conduction terminal voltage until the inter-conduction terminal voltage reaches a power supply voltage supplied to a high-potential ...

DISCHARGE CIRCUIT FOR POWER SUPPLY UNIT

A discharge circuit for a power supply unit includes a pulse width modulator (PWM) chip, a first and second electronic switch, and a resistor. The first electronic switch receives a power good signal from the power supply unit. When a system power terminal outputs a voltage later than a stand-by power terminal, a voltage creep outputted by the PWM chip is discharged through the resistor and the second electronic switch. 1. A discharge circuit , comprising:a power supply unit outputting a power good signal;a pulse width modulator chip comprising a control pin and a phase output pin, wherein the control pin is coupled to the power supply unit, to receive the power good signal; andfirst and second electronic switches each comprising first to third terminals, wherein the first terminal of the first electronic switch is coupled to the control pin, and is coupled to a first system power terminal through a first resistor, the second terminal of the first electronic switch is connected to ground, the third terminal of the first electronic switch is coupled to a stand-by power terminal through a second resistor; the third terminal of the first electronic switch is coupled to the first terminal of the second electronic switch; the second terminal of the second electronic switch is connected to ground, the third terminal of the third electronic switch is coupled to the phase output pin through a third resistor;wherein when the first terminals of the first and second electronic switches are at low-voltage level, the first and second electronic switches are turned on; when the first terminals of the first and second electronic switches, the first and second electronic switch are turned off2. The discharge circuit of claim 1 , further comprising a delay unit claim 1 , the delay unit is coupled between the third terminal of the first electronic switch and the first terminal of the second electronic switch.3. The discharge circuit of claim 2 , wherein the delay unit comprises a ...

DISCHARGE CIRCUIT FOR POWER SUPPLY UNIT

A discharge circuit includes a pulse width modulator (PWM) chip, a first and second electronic switch, and a resistor. The first electronic switch receives a voltage creep from the PWM chip. When the voltage creep is less than a voltage making the first electronic switch to turned on, the voltage creep is discharged through the resistor and the second electronic switch. 1. A discharge circuit , comprising:a pulse width modulator chip comprising a phase output pin coupled to a first terminal of an inductance; andfirst and second electronic switches each comprising first to third terminals, wherein the first terminal of the first electronic switch is coupled to a second terminal of the inductance through a first resistor, the second terminal of the first electronic switch is connected to ground, the third terminal of the first electronic switch is coupled to a stand-by power terminal through a second resistor; the third terminal of the first electronic switch is coupled to the first terminal of the second electronic switch; the second terminal of the second electronic switch is connected to ground, the third terminal of the third electronic switch is coupled to the second terminal of the inductance through a third resistor;wherein when the first terminals of the first and second electronic switches are at low-voltage level, the first and second electronic switches are turned on; when the first terminals of the first and second electronic switches, the first and second electronic switch are turned off2. The discharge circuit of claim 1 , further comprising a fourth resistor claim 1 , wherein the third terminal of the second electronic switch is coupled to the second terminal of the inductance through the fourth resistor.3. The discharge circuit of claim 2 , wherein the PWM chip further comprises a high gate output pin claim 2 , a low gate output pin claim 2 , and a voltage output pin claim 2 , the high gate output pin is coupled to a first terminal of a third ...

GLITCH IMMUNE NON-OVERLAP OPERATION OF TRANSISTORS IN A SWITCHING REGULATOR

A circuit includes a first gate control circuit including a first time delay element and first and second logic gates. The first time delay element and first and second logic gates receive a pulse width modulation (PWM) signal. The first logic gate includes a first output and second logic gate includes a second output. The circuit also includes a second gate control circuit that includes a second time delay element and third and fourth logic gates. The second time delay element includes an input coupled to the output of the first time delay element. The third logic gate includes a third output, and the fourth logic gate includes a fourth output. A first gate driver receives a first signal from one of the first or third outputs. A second gate driver receives a second signal from one of the second or fourth outputs. 1. A circuit , comprising:a first gate control circuit including a first time delay element, a first logic gate, and a second logic gate, the first time delay element including an output, wherein the first time delay element, the first logic gate, and the second logic gate are configured to receive a pulse width modulation (PWM) signal, and wherein the first logic gate includes a first output and the second logic gate includes a second output;a second gate control circuit including a second time delay element, a third logic gate, and a fourth logic gate, wherein the second time delay element includes an input coupled to the output of the first time delay element, the second time delay element includes an output, the third logic gate includes a third output, and the fourth logic gate includes a fourth output;a first gate driver configured to receive a first signal from one of the first or third outputs; anda second gate driver configured to receive a second signal from one of the second or fourth outputs.2. The circuit of claim 1 , further including:a first selection circuit coupled to the first and third output and configured to provide the first signal ...

Switching Power Connector and Electrical Connection Element With Safety Interlock

An electrical connection element is for a power connector. The power connector includes an electrical component having a number of first electrical mating members. The electrical connection element comprises: a housing including a number of second electrical mating members structured to be electrically connected to the number of first electrical mating members; a contact assembly enclosed by the housing and being electrically connected to the number of second electrical mating members; and an operating mechanism for opening and closing the contact assembly. The contact assembly is structured to electrically connect and disconnect power while the number of first electrical mating members remain mechanically coupled to the number of second electrical mating members. 1. An electrical connection element for a power connector , said power connector comprising an electrical component said electrical connection element comprising:a housing;a contact assembly enclosed by said housing and being electrically connected to said number of second electrical mating members; anda toggle operating mechanism structured to open and close said contact assembly,wherein said contact assembly is structured to electrically connect and disconnect power while a number of first electrical mating members remain mechanically coupled to a number of second electrical mating members.2. The electrical connection element of wherein said toggle operating mechanism is structured to open and close said contact assembly by a snap-action.3. The electrical connection element of wherein:said contact assembly includes a number of line-side contacts, a number of load-side contacts, and a number of movable conductor members, each conductor member associated with one line-side contact and one load-side contact;each said conductor member movable between a first position, wherein said associated line-side contact and said associated load-side contact are not electrically connected, and a second position, wherein ...

Controller and power converter using the same

The object of the present invention is to provide a controller, and a power converter using the same, which can expand the range of a voltage applied to a load. The present invention provides a controller, which includes a switch signal unit configured to output a control signal repeating a high state and a low state by receiving a first signal and a second signal, a first signal generation unit configured to generate the first signal, and configured to transmit the first signal to the switch signal unit, and a second signal generation unit configured to generate the second signal by comparing a sensing voltage and a variable first reference voltage, and configured to transmit the second signal to the switch signal unit, wherein the first signal generation unit is configured to adjust a transmission time of the first signal by sensing a voltage level of the first reference voltage, and a power converter using the same.

Semiconductor Integrated Circuit Device

An NBTI malfunction of a P-channel MOS transistor is prevented. A semiconductor integrated circuit device includes a reset pulse control unit RPC. The reset pulse control unit RPC generates a reset pulse RP for recovery from degradation caused by NBTI of a MOS transistor that receives a negative voltage at the gate of the transistor in a standby status. After the generated reset pulse RP is inputted to the gate of the MOS transistor, an action control signal ACC for activating the MOS transistor is inputted to the gate of the MOS transistor to activate the transistor. 1. A semiconductor integrated circuit device comprising a reset pulse control unit that generates a reset pulse for recovery from degradation caused by NBTI of a MOS transistor , inputs the reset pulse to a gate of the MOS transistor , and then inputs an action control signal for activating the MOS transistor to the gate of the MOS transistor.2. A semiconductor integrated circuit device according to claim 1 , wherein the reset pulse control unit comprises:a reset pulse generating unit that generates the reset pulse based on the action control signal; anda signal switching control unit that outputs one of the action control signal and the reset pulse to the gate of the MOS transistor based on the reset pulse generated by the reset pulse generating unit,the signal switching control unit outputting the reset pulse to the gate of the MOS transistor before outputting the action control signal to the gate of the MOS transistor.3. The semiconductor integrated circuit device according to claim 2 , wherein the reset pulse generated by the reset pulse generating unit is a pulse signal having a higher voltage than an absolute value of a threshold voltage of the MOS transistor.4. The semiconductor integrated circuit device according to claim 2 , wherein the reset pulse generated by the reset pulse generating unit is a reference potential of the MOS transistor.5. The semiconductor integrated circuit device ...

CONTACTOR HAVING ELECTRONIC COIL CONTROL

The disclosure relates to a contactor having electronic coil control for a magnet coil, the operation of keeping the pull-in power of the magnet coil constant being formed by current clocking, and having a safety-related output assembly of a programmable logic controller for the fault diagnosis of the contactor, the safety-related output assembly determining the flow of current flowing into the contactor and detecting a fault if a limit value is undershot and switching off. In the contactor disclosed herein, a connectable base load is integrated in the contactor. 1. A contactor comprising:an electronic coil control for a magnet coil, wherein the electronic coil control is configured to keep a pull-in power of the magnet coil constant by current clocking;a safety-related output assembly of a programmable logic controller for fault diagnosis of the contactor, wherein the safety-related output assembly is configured to determine a flow of current into the contactor, detect a fault when a limit value is undershot, and switch off, anda connectable base load integrated in the contactor.2. The contactor of claim 1 , wherein the connectable base load is connected in a start-up phase of the contactor when current is not flowing through the magnet coil.3. The contactor of claim 2 , wherein the connectable base load is connected in pause times of the current clocking for the magnet coil.4. The contactor of claim 3 , further comprising:a switch connected in series with the connectable base load.5. The contactor of claim 4 , wherein a signal specifying the clock for the coil control is impressed on the switch in an inverted manner.6. The contactor of claim 5 , further comprising:a time control integrated in the contactor.7. The contactor of claim 6 , wherein an active phase of the time control is restricted to the pull-in process of the contactor.8. The contactor of claim 1 , wherein the connectable base load is connected in pause times of the current clocking for the magnet ...

PIXEL STRUCTURE

The disclosure provides a light emitting diode including a light emitting diode (LED), a first transistor, a second transistor and capacitor. A cathode terminal of the LED is configured to receive a first power supply voltage. A first port of the capacitor coupled to the gate of the first transistor is configured to store a data signal in a first duration. A first port of the second transistor is configured to receive a second power supply voltage. A gate of the second transistor is configured to receive a PWM signal in a second duration. A second port of the second transistor is coupled to the second port of the first transistor. The second transistor is turned on for a conducting time in the second duration according to the PWM signal, and the first transistor provides, in the conducting time, a drive current to the LED according to the data signal. 1. A pixel structure , comprising:a light emitting diode, wherein a cathode terminal of the light emitting diode is configured to receive a first power supply voltage;a first transistor, wherein a first port of the first transistor is coupled to an anode terminal of the light emitting diode;a capacitor, wherein a first port of the capacitor is coupled to a gate of the first transistor, a second port of the capacitor is coupled to the cathode terminal of the light emitting diode, and the capacitor is configured to store a data signal in a first duration; anda second transistor, wherein a first port of the second transistor is configured to receive a second power supply voltage, a gate of the second transistor is configured to receive a pulse width modulation (PWM) signal in a second duration, and a second port of the second transistor is coupled to a second port of the first transistor;wherein the second transistor is turned on for a conducting time in the second duration according to the PWM signal, and the first transistor provides, in the conducting time, a drive current to the light emitting diode according to the ...

DRIVE DEVICE

A drive device for controlling a power switching element to turn on and off includes: an on-side circuit performing an on operation of the power switching element; an off-side circuit performing an off operation of the power switching element; and a temperature detector detecting a temperature. At least one of the on-side and off-side circuits includes a current path for supplying or drawing a gate current of the power switching element and a switch circuit for switching the gate current. The switch circuit transitionally changes the gate current based on the temperature of the power switching element when the switching circuit switches the gate current. 1. A drive device for controlling a power switching element to turn on and off , the drive device comprising:an on-side circuit that performs an on operation of the power switching element;an off-side circuit that performs an off operation of the power switching element; anda temperature detector that detects a temperature of the power switching element, wherein:at least one of the on-side circuit or the off-side circuit includes a current path for supplying or drawing a gate current of the power switching element and a switch circuit for switching the gate current of the power switching element;the switch circuit transitionally changes the gate current based on the temperature of the power switching element detected by the temperature detector when the switching circuit switches the gate current; a plurality of main MOS transistors as output transistors that provide the current path;', 'a sense MOS transistor that includes a gate in common with the main MOS transistors, and provides a current mirror with respect to the main MOS transistors to define a drain current of each main MOS transistor; and', 'a sense current control circuit that controls a drain current of the sense MOS transistor to be constant;', 'the switch circuit is connected to the gate of each of the main MOS transistors, and controls each of the ...

LOW POWER HIGH FREQUENCY DIGITAL PULSE FREQUENCY MODULATOR

Described is an apparatus that comprises: a programmable delay line (PDL) to receive a pulse-width modulation (PWM) signal as input and to generate a first output; a selection unit operable to provide PWM signal or its inverted version as a second output; and a sequential unit coupled to the PDL, the sequential unit to sample the second output with the first output, the sequential unit to generate a pulse-frequency modulation (PFM) output. Described is also a voltage regulator which comprises: mutually coupled on-die inductors for coupling to a load; a bridge, coupled to the mutually coupled on-die inductors, including a low-side switch and a high-side switch; a PWM controller for controlling the low-side and high-side switches during a first load current; and a PFM controller for controlling the low-side and high-side switches during a second load current, the second load current being smaller than the first load current, the PFM controller comprising: a comparator for comparing output voltage of the load with a reference voltage; and a first PDL coupled to the comparator for determining turn-on duration of the high-side switch. 1. An apparatus comprising:a programmable delay line (PDL) to receive a pulse-width modulated (PWM) signal as input and to generate a first output;a selection unit operable to provide PWM signal or its inverted version as a second output; anda sequential unit coupled to the PDL, the sequential unit to sample the second output with the first output, the sequential unit to generate a pulse-frequency modulated (PFM) output.2. The apparatus of further comprises a finite state machine (FSM) coupled to the PDL and the sequential unit.3. The apparatus of claim 2 , wherein the FSM is operable to adjust delay of the first output relative to the PWM signal.4. The apparatus of claim 2 , wherein the FSM is operable to generate a third output for controlling turn-on time of a high-side switch of a voltage regulator (VR).5. The apparatus of claim 4 , ...

CIRCUIT AND METHOD FOR CONTROLLING CHARGE INJECTION IN RADIO FREQUENCY SWITCHES

A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors. A method for controlling charge injection in a switch circuit is disclosed whereby injected charge is generated at resistively-isolated nodes between series coupled switching transistors, and the injected charge is conveyed to at least one node of the switch circuit that is not resistively-isolated. 1(a) a plurality of N signal switching ACC transistors, each ACC transistor including (A) a gate coupled to a gate resistor configured to be coupled to a gate control signal, and (B) a gate-controlled channel, wherein the plurality of ACC transistors are coupled in series through their respective gate-controlled channels between an input node and an output node to selectively convey an RF signal between the input node to the output node in response to the gate control signal, the ACC transistors further including at least one resistively-isolated inner node, each inner node located between adjacent pairs of the ACC transistors and receiving injected charge when the plurality of ACC transistors is switched from an ON state to an OFF state; and(b) a plurality of charge injection control resistors, each charge injection control resistor operatively coupled between a ...

Transmission device, air-conditioning apparatus, and air-conditioning system

Provided is a transmission device for transmitting and receiving data through a transmission channel. The transmission device includes a transmission circuit unit configured to transmit data to the transmission channel. When an overcurrent caused by a simultaneous transmission of data to the transmission channel is detected during data transmission, the transmission circuit unit increases an output resistance, which is a resistance value for an output to the transmission channel, to an resistance value corresponding to a characteristic of a facility equipment item that transmits data to the transmission channel at the same time as itself.

MITIGATION OF SIMULTANEOUS SWITCHING OUTPUT EFFECTS

Method of reducing simultaneous switching output (SSO) impact in a system through the use of signal integrity/power integrity (SI/PI) simulations for each channel in the system includes calculating a worst case scenario current for a channel of the system, and calculating a worst case channel skew for a channel of the system. Based on the worst case scenario current and the worst case channel skew, a switching current is determined for the system. 1. A method of determining current use in a multi-channel device , comprising:calculating a worst case scenario current for a channel of the device;calculating a worst case channel skew for a channel of the device; anddetermining, based on the worst case scenario current and the worst case channel skew, a switching pattern for channels of the device.2. The method of claim 1 , wherein the switching pattern is determined using at least one of a combination of time delay between switching of channels and grouping multiple channels.3. The method of claim 1 , wherein calculating a worst case scenario for current consumption is based on expected worst case operating conditions of the device.4. The method of claim 1 , wherein calculating a worst skew for a channel comprises calculating a worst positive skew and a worst negative skew for the channel.5. The method of claim 1 , and further comprising performing a layout implementation to spread the channel switching over a bit period using the determined switching pattern.6. The method of claim 1 , wherein determining a switching pattern for channels of the device comprises:spreading channel switching evenly across a bit period;calculating a maximum switching current for the evenly spread channels;determining iteratively whether one of a plurality of groups of channels having switching spread evenly over the bit period results in a lower maximum switching current; andperforming a layout implementation to spread the channel switching over the bit period using the iteration of the ...

DRIVING APPARATUS AND SWITCHING APPARATUS

A driving apparatus including: gate driving circuit to drive gates of a first semiconductor element and a second semiconductor element connected in series between a positive side power supply line and a negative side power supply line; a first timing generating circuit to generate a first timing signal when voltage applied to the second semiconductor element becomes reference voltage during a turn-off period of the first semiconductor element; and a first driving condition change circuit, wherein the gate driving circuit relaxes change in a charge amount of the gate of the first semiconductor element, according to the first timing signal. 1. A driving apparatus comprising:gate driving circuit to drive gates of a first semiconductor element and a second semiconductor element connected in series between a positive side power supply line and a negative side power supply line;a first timing generating circuit to generate a first timing signal when voltage applied to the first semiconductor element is increased to higher than or equal to reference voltage during a turn-off period of the first semiconductor element; anda first driving condition change circuit, wherein the gate driving circuit relaxes change in a charge amount of a gate of the first semiconductor element, according to the first timing signal.2. The driving apparatus according to claim 1 , wherein the first timing generating circuit is pre-adjusted so as to generate the first timing signal when claim 1 , after receiving a control signal to turn off the first semiconductor element and starting turn-off of the first semiconductor element claim 1 , time reaches a timing before voltage applied to the first semiconductor element becomes higher than or equal to reference voltage.3. The driving apparatus according to claim 1 , wherein the reference voltage is higher than or equal to voltage between the positive side power supply line and the negative side power supply line.4. The driving apparatus according to ...

Method for Driving a Load

An electronic switch includes a load path connected in series with the load and a drive terminal for receiving a drive signal. The electronic switch is operable to switch between a first operation state and a second operation state dependent on the drive signal. In a first switching cycle, the electronic switch is switched from the first operation state to the second operation state and a voltage across the load is evaluated during the first switching cycle in order to obtain a measured switching profile. The measured switching profile is compared with a reference profile. A drive profile dependent on the comparison is provided. The drive profile is used to drive the electronic switch in a second switching cycle after the first switching cycle. At least two drive parameters are used at different times in the at least one second switching cycle to drive the electronic switch. 1. A method for driving a load , the method comprising:providing an electronic switch comprising a load path coupled in series with the load and a drive terminal for receiving a drive signal, the electronic switch operable to switch between a first operation state and a second operation state dependent on the drive signal;in a first switching cycle, switching the electronic switch from the first operation state to the second operation state and evaluating a voltage across the load during the first switching cycle in order to obtain a measured switching profile;comparing the measured switching profile with a reference profile and providing a drive profile dependent on the comparison;using the drive profile to drive the electronic switch in a second switching cycle after the first switching cycle, wherein drive parameters are used at different times in the second switching cycle to drive the electronic switch.2. The method of claim 1 , wherein evaluating the voltage across the load comprises:evaluating the voltage at a plurality of different times during the change of the operation state, wherein ...

CONTROL CIRCUIT FOR CONTROLLING A PUSH-PULL CIRCUIT AND METHOD THEREOF

A control circuit for generating a first control signal and a second control signal includes: an inverter, used for generating an inverted clock according to an input clock; a first delay circuit, used for generating a first delay control signal; a second delay circuit, used for generating a second delay control signal; a first mask circuit, used for generating a first mask signal according to the input clock; a second mask circuit, used for generating a second mask signal according to the inverted input clock; a first logic determining circuit, used for generating the first control signal to the first delay circuit according to the second mask signal and the input clock; and a second logic determining circuit, used for generating the second control signal to the second delay circuit according to the first mask signal and the inverted clock. 1. A control circuit for generating a first control signal and a second control signal , comprising:an inverter, arranged for inverting an input clock to generate an inverted clock;a first delayed clock, arranged for delaying the first control signal to generate a first delay control signal;a second delayed clock, arranged for delaying the second control signal to generate a second delay control signal;a first mask circuit, coupled to the first delay circuit and the input clock, arranged for filtering out the first delay control signal not larger than a first time period to generate a first mask signal according to the input clock;a second mask circuit, coupled to the second delay circuit and the inverted input clock, arranged for filtering out the second delay control signal not larger than a second time period to generate a second mask signal according to the inverted input clock;a first logic determining circuit, arranged for generating the first control signal to the first delay circuit according to the second mask signal and the input clock; anda second logic determining circuit, arranged for generating the second control ...

SYNCHRONIZING PARALLEL POWER SWITCHES

The invention generally relates to methods and circuits for controlling switching of parallel coupled power semiconductor switching devices (), for example for use in a power converter. In an example, there is provided a circuit for controlling switching of parallel coupled power semiconductor switching devices (), the circuit comprising: a plurality of drive modules (), each said module for controlling a said power semiconductor switching device (); control circuitry to transmit switch command signals to the modules, each said switch command signal to trigger a said drive module to control a said power semiconductor switching device to switch state; and voltage isolation between the drive modules and the control circuitry, wherein each said drive module for controlling a said device comprises: timing circuitry () to compare a switching delay of the device and a reference delay, wherein said switching delay is a time interval between detecting a said switching command signal at the drive module and switching of the device in accordance with the detected switching command signal; and delay circuitry () to provide a controllable delay to delay a said triggering by a said switching command signal received at the module subsequent to the detected switching command signal, the delay circuitry configured to control the controllable delay according to a result of said comparison of said switching delay of the device, to thereby reduce a time difference between the reference delay and a said switching delay of the device switching in accordance with the subsequent switching command signal. 1. A circuit for controlling switching of parallel coupled power semiconductor switching devices , the circuit comprising:a plurality of drive modules each controlling a respective power semiconductor switching device;control circuitry to transmit switch command signals to the modules, each switch command signal to trigger a said drive module to control a said power semiconductor ...

SWITCHING CIRCUIT

A circuit has an operational voltage supply node that carries an operational voltage having an operational voltage value, a reference voltage supply node that carries a reference voltage having a reference voltage value, and a sub-circuit and switching circuit between the operational voltage supply node and the reference voltage supply node. The switching circuit is in series with the sub-circuit and controls a current through the sub-circuit based on a difference between the operational voltage value and a nominal operational voltage value. 1. A circuit comprising:an operational voltage supply node configured to carry an operational voltage having an operational voltage value;a reference voltage supply node configured to carry a reference voltage having a reference voltage value;a sub-circuit between the operational voltage supply node and the reference voltage supply node; anda switching circuit between the operational voltage supply node and the reference voltage supply node and in series with the sub-circuit, the switching circuit configured to control a current through the sub-circuit based on a difference between the operational voltage value and a nominal operational voltage value.2. The circuit of claim 1 , further comprising a control circuit configured to:generate a control signal based on the operational voltage value; andsupply the control signal to the switching circuit.3. The circuit of claim 2 , wherein the control circuit is configured to change a logic state of the control signal after a delay if the operational voltage value is greater than a first value based on the nominal operational voltage value.4. The circuit of claim 3 , wherein the control circuit is configured to respond to a first signal having a logic state indicating a wake up mode by:initiating the delay;generating the control signal having a first logic state during the delay based on a stored logic value indicating the operational voltage value being greater than the first value ...

Semiconductor device and method of generating power-on reset signal

A semiconductor device and a method of generating a power-on reset signal are provided. The semiconductor device includes a regulator configured to generate a regulated power supply voltage having a lower voltage value than a power supply voltage based on the power supply voltage and output the regulated power supply voltage to an internal power supply line, and a power-on reset circuit configured to generate a signal which has a first level at which reset is prompted immediately after power for the power supply voltage is turned on and which transitions to a second level at which reset release is prompted from the first level when a voltage value of the internal power supply line has risen as a power-on reset signal.

DRIVE CIRCUIT

Embodiments of this application relate to the field of electricity, and disclose a drive circuit. In some embodiments of this application, the drive circuit includes a low-side driver module and a delay module, the delay module is configured to output a delay signal of preset duration to the low-side driver module in a case that a control module is being reset; and the low-side driver module is configured to: according to on the delay signal of preset duration, maintain a first state within the preset duration, the first state being the same as a second state; where the second state is a working state of the low-side driver module before the control module is reset, and the second state includes being on or off. The embodiments can help avoid safety hazards caused by unexpected disconnection of a drive signal of the control module. 1. A drive circuit , wherein the drive circuit comprises a low-side driver module and a delay module;the delay module is configured to output a delay signal of preset duration to the low-side driver module in a case that a control module is being reset; andthe low-side driver module is configured to: according to the delay signal of preset duration, maintain a first state within the preset duration, wherein the first state is the same as a second state;wherein the second state is a working state of the low-side driver module before the control module is reset, and the second state comprises being on or off.2. The drive circuit according to claim 1 , wherein the delay module comprises a delay unit and a first pull-up unit; a first controlled terminal of the delay unit is connected to both the first pull-up unit and a first output terminal of the control module claim 1 , a second controlled terminal of the delay unit is connected to a second output terminal of the control module claim 1 , and an output terminal of the delay unit is connected to a control terminal of the low-side driver module; andthe delay unit is configured to: when an ...

VOLTAGE DIVIDER CONTROL CIRCUIT

One or more techniques or systems for controlling a voltage divider are provided herein. In some embodiments, a control circuit is configured to bias a pull up unit of a voltage divider using an analog signal, thus enabling the voltage divider to be level tunable. In other words, the control circuit enables the voltage divider to output multiple voltage levels. Additionally, the control circuit is configured to bias the pull up unit based on a bias timing associated with a pull down unit of the voltage divider. For example, the pull up unit is activated after the pull down unit is activated. In this manner, the control circuit provides a timing boost, thus enabling the voltage divider to stabilize more quickly. 1. A control circuit configured to at least one of:bias a pull up unit of a voltage divider using an analog signal associated with a Vppu voltage level; orbias the pull up unit of the voltage divider based on a delay time (Tppu) associated with a pull down unit of the voltage divider.2. The control circuit of claim 1 , the control circuit configured to bias the pull up unit of the voltage divider based on at least one of a first voltage level claim 1 , a second voltage level claim 1 , or a third voltage level claim 1 , the first voltage level above a logic low voltage level claim 1 , the third voltage level below a logic high voltage level claim 1 , and the second voltage level between the first voltage level and the third voltage level.3. The control circuit of claim 1 , configured to bias a second pull up unit of a second voltage divider using the analog signal associated with the Vppu voltage level.4. The control circuit of claim 3 , configured to bias the second pull up unit of the second voltage divider based on the Tppu associated with a second pull down unit of the second voltage divider.5. The control circuit of claim 1 , the control circuit configured to bias a plurality of voltage dividers using the analog signal associated with the Vppu voltage ...

Delay Line System and Switching Apparatus with Embedded Attenuators

Systems, methods, and apparatus for reducing standing wave reflections between delay line modules are described. The delay line modules include semiconductor switches, particularly MOSFET switches fabricated on silicon-on-insulator (“SOI”) and silicon-on-sapphire (“SOS”) substrates and embedded attenuators. 1. A monolithically integrated switch comprising:an input port configured to carry the input signal;a plurality of switches configured to provide a plurality of conduction paths;a first output port and a second output port;a first conduction path of the plurality of conduction paths between the input port and the first output port, the first conduction path comprising a first attenuator block comprising one or more shunting resistors coupled to one or more series connected switches of the plurality of switches;a second conduction path of the plurality of conduction paths between the input port and the second output port;a first shunting path of the plurality of conduction paths between the first output port and a reference potential;a second shunting path of the plurality of conduction paths between the second output port and the reference potential;wherein:a low impedance or high impedance of a conduction path of the plurality of conduction paths is selectively provided by one or more switches of the plurality of switches based on a mode of operation of the switch;during a first mode of operation of the switch, the first conduction path and the second shunting path are low impedance conduction paths, and the second conduction path and the first shunting path are high impedance conduction paths, andduring a second mode of operation of the switch, the second conduction path and the first shunting path are low impedance conduction paths, and the first conduction path and the second shunting path are high impedance conduction paths.2. The monolithically integrated switch of claim 1 , wherein the second conduction path further comprises a second attenuator block ...

Electronic power switch

In accordance with aspects of the present invention, a power control circuit includes a MAIN window comparator circuit providing a MAIN signal; an AUX window comparator circuit providing an AUX signal; a state machine receiving the MAIN signal and the AUX signal; a MAIN slew circuit coupled to drive a MAIN switch, the MAIN switch coupled between MAIN and an output; an AUX slew circuit coupled to drive an AUX switch, the AUX switch coupled between AUX and the output; wherein the state machine operates to continuously activate either the MAIN switch or the AUX switch according to the MAIN signal and the AUX signal such that the output is continuously coupled to either a MAIN input or an AUX input with minimum disruption to output voltage, input and output capacitance inrush currents or reverse conduction. What really makes the circuit unique is it is combined with an adjustable forward biased rectification circuit for each channel of MAIN and AUX.

Delay Line System and Switching Apparatus with Embedded Attenuators

Systems, methods, and apparatus for reducing standing wave reflections between delay line modules are described. The delay line modules include semiconductor switches, particularly MOSFET switches fabricated on silicon-on-insulator (“SOI”) and silicon-on-sapphire (“SOS”) substrates and embedded attenuators. 1. A monolithically integrated switch comprising:an input port configured to carry the input signal;a plurality of switches configured to provide a plurality of conduction paths;a first output port and a second output port;a first conduction path of the plurality of conduction paths between the input port and the first output port, the first conduction path comprising a first attenuator block comprising one or more shunting resistors coupled to one or more series connected switches of the plurality of switches;a second conduction path of the plurality of conduction paths between the input port and the second output port;a first shunting path of the plurality of conduction paths between the first output port and a reference potential;a second shunting path of the plurality of conduction paths between the second output port and the reference potential;wherein:a low impedance or high impedance of a conduction path of the plurality of conduction paths is selectively provided by one or more switches of the plurality of switches based on a mode of operation of the switch;during a first mode of operation of the switch, the first conduction path and the second shunting path are low impedance conduction paths, and the second conduction path and the first shunting path are high impedance conduction paths, andduring a second mode of operation of the switch, the second conduction path and the first shunting path are low impedance conduction paths, and the first conduction path and the second shunting path are high impedance conduction paths.2. The monolithically integrated switch of claim 1 , wherein the second conduction path further comprises a second attenuator block ...

SWITCHING DEVICE FOR CONDUCTING AND INTERRUPTING ELECTRICAL CURRENTS

A switching device for conducting and disconnecting electric currents includes: a first mechanical contact assembly; a semiconductor switch, which is in parallel to the first mechanical contact assembly; a second mechanical contact assembly, which is connected in series to the first mechanical contact assembly; and a switching electronics, which switch on and off the semiconductor switch. The switching electronics are operable, during a closing process of the first mechanical contact assembly, to turn on the semiconductor switch after a first predetermined time period t−0 after initialization of the switching electronics, and to turn the semiconductor switch off again after a second predetermined time period t−1. The first predetermined time period t−0 is set by the switching electronics depending on the first mechanical contact assembly. 1: A switching device for conducting and disconnecting electric currents , comprising:a first mechanical contact assembly;a semiconductor switch, which is in parallel to the first mechanical contact assembly;a second mechanical contact assembly, which is connected in series to the first mechanical contact assembly; anda switching electronics, which is configured to switch on and off the semiconductor switch,wherein the switching electronics is configured, during a closing process of the first mechanical contact assembly, to turn on the semiconductor switch after a first predetermined time period t−0 after initialization of the switching electronics, and to turn the semiconductor switch off again after a second predetermined time period t−1, andwherein the first predetermined time period t−0 is set by the switching electronics depending on the first mechanical contact assembly.2: The switching device according to claim 1 ,whereinthe switching electronics is configured to set the second predetermined time period t−1 depending on the first mechanical contact assembly.3: The switching device according to claim 1 ,whereinthe switching ...

SWITCH DEVICE FOR SWITCHING AN ANALOG ELECTRICAL INPUT SIGNAL

A switch device for switching an analog electrical input signal includes: a switching transistor being a flipped-well-silicon-on-insulator-NMOS transistor; and a bootstrapping arrangement including a voltage providing arrangement for providing a floating voltage during the on-state, wherein the floating voltage is provided at a positive terminal and at a negative terminal of the voltage providing arrangement; wherein the bootstrapping arrangement is configured in such way that during the on-state the positive terminal is electrically connected to the front gate contact of the switching transistor and to the back gate contact of the switching transistor, and the negative terminal is electrically connected to the source contact of the switching transistor; wherein the bootstrapping arrangement is configured in such way that during the off-state the positive terminal and the negative terminal are not electrically connected to the switching transistor. 1. Switch device for switching an analog electrical input signal , the switch device comprising:a switching transistor being a flipped-well-silicon-on-insulator-NMOS transistor comprising a source contact being electrically connected to a source region, a drain contact being electrically connected to a drain region, a front gate contact being electrically connected to a gate region and a back gate contact being electrically connected to a flipped well;an input contact for receiving the analog electrical input signal, wherein the input contact is electrically connected to the source contact of the switching transistor;an output contact for outputting an analog electrical output signal corresponding to the analog electrical input signal during an on-state of the switch device and for not outputting the analog electrical output signal during an off-state of the switch device, wherein the output contact is electrically connected to the drain contact of the switching transistor; anda bootstrapping arrangement comprising a ...

SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME

Provided is a technique for reducing the size and cost of a semiconductor device. A semiconductor device includes an IGBT module having an IGBT, and a MOSFET module having a MOSFET whose operational property is different from that of the IGBT, the MOSFET module being connected to the IGBT module in parallel. The semiconductor device is capable of selectively executing an operation mode in which switching timing in the IGBT module and switching timing in the MOSFET module are non-identical. 1. A semiconductor device comprising:a first power semiconductor module comprising a first power semiconductor switching element; anda second power semiconductor module comprising a second power semiconductor switching element whose operational property is different from an operational property of the first power semiconductor switching element, the second power semiconductor module being connected to the first power semiconductor module in parallel,the semiconductor device being capable of selectively executing an operation mode in which switching timing in the first power semiconductor module and switching timing in the second power semiconductor module are non-identical.2. The semiconductor device according to claim 1 , wherein the second power semiconductor module further comprises an input pin to which a signal is input for executing the operation mode.3. The semiconductor device according to claim 1 , wherein the first power semiconductor module and the second power semiconductor module are configured to selectively execute the operation mode in response to a signal from a control circuit configured to control the first power semiconductor module and the second power semiconductor module.4. The semiconductor device according to claim 1 , whereinwith respect to a package size or a rated current, the first power semiconductor module is larger than the second power semiconductor module, andno heat-dissipation fin is in contact with the second power semiconductor module.5. The ...

Timing Controller for Dead-Time Control

Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion (e.g. DC/DC) and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors. According to an aspect, timing control of edges of a control signal to the high voltage semiconductor devices is provided by a basic edge delay circuit that includes a transistor, a current source and a capacitor. An inverter can be selectively coupled, via a switch, to an input and/or an output of the basic edge delay circuit to allow for timing control of a rising edge or a falling edge of the control signal.

DRIVING APPARATUS AND SWITCHING APPARATUS

A driving apparatus including: gate driving circuit to drive gates of a first semiconductor element and a second semiconductor element connected in series between a positive side power supply line and a negative side power supply line; a first timing generating circuit to generate a first timing signal when voltage applied to the second semiconductor element becomes reference voltage during a turn-off period of the first semiconductor element; and a first driving condition change circuit, wherein the gate driving circuit relaxes change in a charge amount of the gate of the first semiconductor element, according to the first timing signal. 1. A driving apparatus comprising:gate driving circuit to drive gates of a first semiconductor element and a second semiconductor element connected in series between a positive side power supply line and a negative side power supply line;a first timing generating circuit to generate a first timing signal starting when voltage applied to the first semiconductor element is increased to higher than or equal to reference voltage during a turn-off period of the first semiconductor element; anda first driving condition change circuit, wherein the gate driving circuit relaxes change in a charge amount of a gate of the first semiconductor element, during the generation of the first timing signal.2. The driving apparatus according to claim 1 , wherein the first timing generating circuit is pre-adjusted so as to generate the first timing signal when claim 1 , after receiving a control signal to turn off the first semiconductor element and starting turn-off of the first semiconductor element claim 1 , time reaches a timing before voltage applied to the first semiconductor element becomes higher than or equal to reference voltage.3. The driving apparatus according to claim 1 , wherein the reference voltage is higher than or equal to voltage between the positive side power supply line and the negative side power supply line.4. The driving ...

PROGRAMMABLE BIASING FOR PIN DIODE DRIVERS

Driving circuitry is described that includes multiple programmable bias voltages useful for biasing radio-frequency components such as PIN diodes and gallium-nitride devices. Programmable voltages as high as 30 volts and as low as −20 volts are generated. The drive circuitry can operate from a single, low-voltage power source. 1. A driver circuit comprising:a substrate on which the driver circuit is assembled;a supply voltage contact configured to receive electrical power from a power source;a boost converter connected to the supply voltage contact and configured to convert a first voltage received from the power source to a second voltage that is greater than the first voltage and to a third voltage that is less than the first voltage;a low-dropout regulator configured to convert the second voltage to a fourth voltage; anda programmable register configured to receive a digital signal and output a first control signal responsive to the received digital signal that alters at least the fourth voltage within a positive voltage range that is greater than zero volts.2. The driver circuit of claim 1 , wherein the positive voltage range is from approximately 15 volts to approximately 28 volts.3. The driver circuit of claim 1 , wherein the programmable register is further configured to output a second control signal that alters the third voltage within a negative voltage range that is less than zero volts.4. The driver circuit of claim 3 , wherein the negative voltage range is from approximately −8 volts to approximately −20 volts.5. The driver circuit of claim 1 , wherein the supply voltage contact is the only contact for receiving power that powers the driver circuit.6. The driver circuit of claim 1 , wherein the boost converter comprises:two transistors;two inductor contacts on the substrate that are connected to the two transistors; andswitching circuitry configured to switch current through an inductor that attaches to the two inductor contacts.7. The driver circuit of ...

POSITIVE AND NEGATIVE DC-DC CONVERTER FOR BIASING RF CIRCUITS

A multi-voltage converter is described that includes multiple programmable bias voltages of positive and negative values that may be used to bias radio-frequency components such as PIN diodes and gallium-nitride devices. Programmable voltages as high as 30 volts and as low as −20 volts are generated. Outputs may be provided to a sequencing circuit for biasing gallium-nitride transistors and amplifiers. 1. A voltage converter comprising:a substrate on which the voltage converter is assembled;a supply voltage contact configured to receive electrical power from a power source having a positive voltage;a boost converter connected to the supply voltage contact and configured to convert a first voltage received from the power source to a second voltage that is greater than the first voltage, to a third voltage that is greater than the first voltage, and to a negative voltage;a low-dropout regulator configured to convert the second voltage to a fourth voltage; anda register configured to output a first control signal that sets at least the fourth voltage within a positive voltage range that is greater than zero volts.2. The voltage converter of claim 1 , wherein the boost converter is configured to output up to 80 mA for the fourth voltage and/or the negative voltage.3. The voltage converter of claim 1 , wherein the supply voltage contact is the only contact for receiving power that powers the voltage converter.4. The voltage converter of claim 1 , wherein the register is programmable and is configured to receive a digital signal via a programming contact on the substrate and alter a value of the first control signal responsive to the received digital signal.5. The voltage converter of claim 4 , wherein the register is further configured to output a second control signal that alters the negative voltage within a negative voltage range.6. The voltage converter of claim 5 , wherein the negative voltage range is from approximately −8 volts to approximately −20 volts.7. The ...

INTEGRATED CIRCUIT DELAY CELL

An integrated circuit delay cell includes an input circuit to establish a current level in the circuit, a switch configured to control an on/off time of a delay circuit, a delay circuit including at least one current starved stage configured to mirror the current level, the delay circuit configured to control a speed of a rise and/or fall time of an output signal, and a glitch discharging circuit connected to the delay circuit configured to tolerate and discharge unwanted charge of the delay circuit. 1. An integrated circuit delay cell , comprising:an input circuit to establish a current level in the circuit;a switch configured to control an on/off time of a delay circuit;the delay circuit including at least one current starved stage configured to mirror the current level and a plurality of nodes,the delay circuit configured to control a speed of a rise and/or fall time of an output signal; anda glitch discharging circuit coupled to the delay circuit and configured to discharge the plurality of nodes within the delay circuit, before the current level is established in the circuit, in response to a received power-on-reset signal.2. The delay cell of claim 1 , wherein the delay circuit includes a plurality of current starved stages.3. The delay cell of claim 2 , wherein each stage includes a current limiting transistor and an inverter.4. (canceled)5. The delay cell of claim 1 , wherein each of the plurality of nodes is connected to a decoupling capacitor.6. The delay cell of claim 5 , wherein at least one of the decoupling capacitors is connected in parallel with a pull-down transistor.7. The delay cell of claim 6 , wherein the pull-down transistor is an NMOS transistor.8. The delay cell of claim 10 ,wherein the pull-up transistor is a PMOS transistor.9. The delay cell of claim 5 , wherein at least one of the decoupling capacitors is connected in parallel with a clamping transistor.10. The delay cell of claim 5 , wherein at least one of the decoupling capacitors is ...

A SWITCHING CIRCUIT AND THE METHOD THEREOF

A switching circuit having a low side driver providing a three-level low side drive signal keeps a low side power switch slightly on during a dead time between the low side power switch turn off and a high side power switch turn on, thus a current flowing through a body diode is mostly distributed to the slightly on low side power switch instead of the body diode. 1. A switching circuit , comprising:a high side power switch having a first terminal coupled to an input voltage of the switching circuit, a second terminal coupled to a switching node, and a control terminal configured to receive a high side driving signal;a low side power switch having a first terminal coupled to the switching node, a second terminal coupled to a reference ground, and a control terminal configured to receive a low side driving signal; anda low side driver having a first input terminal coupled to the switching node to receive a switching signal, a second input terminal configured to receive a switching control signal, and an output terminal configured to provide the low side driving signal based on the switching signal and the switching control signal;wherein the high side power switch and the low side power switch are turned on and off alternatively, and the low side driving signal has a middle drive value between a power voltage of the low side driver and the reference ground during a dead time between the low side power switch turn off and the high side power switch turn on, to slightly turn on the low side power switch.2. The switching circuit of claim 1 , further comprising a high side driver having an input terminal coupled to the switching control signal and an output terminal configured to provide the high side driving signal based on the switching control signal.3. The switching circuit of claim 1 , wherein the low side driver comprises:an inverter having a power terminal configured to receive the power voltage, a ground terminal coupled to a voltage source to receive a voltage ...

CONVERTER AND METHOD FOR SUPPRESSING LOOP INTERFERENCE OF CONVERTER

The invention provides a converter and a method for suppressing loop interference of converter. The converter includes first and second switching sets connected to each other. Each switching set includes a plurality of switching devices. The plurality of second switching devices are configured to be turned on for a first time after the turn-off time of the plurality of first switching devices, such that each of the plurality of second switching devices provides a path for current within the first time to reduce a potential difference between the first end of at least one of the plurality of second switching devices and the first end of the remaining of the plurality of second switching devices. 1. A converter , comprising:a first switching set, comprising a plurality of first switching devices, wherein first ends of the plurality of first switching devices are electrically connected to each other, and second ends of the plurality of first switching devices are electrically connected to each other; anda second switching set electrically connected to the first switching set, wherein the second switching set comprises a plurality of second switching devices, and first ends of the plurality of second switching devices are electrically connected to each other, and second ends of the plurality of second switching devices are electrically connected to each other;wherein the plurality of second switching devices are turned on for a first time after the turn-off time of the plurality of first switching devices, such that each of the plurality of second switching devices provides a current loop within the first time to reduce an electrical potential difference between the first end of at least one of the plurality of second switching devices and the first end of the remaining of the plurality of second switching devices.2. The converter according to claim 1 , wherein the electrical potential difference is zero.3. The converter according to claim 1 , wherein the second ...

LOAD SWITCH CIRCUIT AND CONTROL METHOD

The present application provides a load switch circuit including a power transistor, the first terminal is configured to receive the power supply voltage, and the second terminal is the output terminal of the load switch circuit and is coupled with an external inductive load; a clamping module including at least a mutually coupled clamping unit and a driving unit; the clamping unit, including a voltage-current converter and a first resistor, the first resistor is coupled between the output terminal of the voltage-current converter and the second terminal of the power transistor, the positive input terminal of the voltage-current converter receives the power supply voltage, and the negative input terminal is coupled to the second terminal of the power transistor; the current output by the voltage-current converter generates a reference voltage drop on the first resistor; the output terminal of the drive unit is coupled to the control terminal of the power transistor when the difference between the power supply voltage and the output voltage of the power transistor is greater than or equal to the preset clamping threshold, the clamping unit outputs an effective drive control signal to the driving unit; the preset clamping threshold is sum of the reference voltage drop and the threshold of the first transistor. 1. A control method of a switch circuit , including:generating a reference current through a voltage-current converter, the voltage-current converter having an equivalent resistance;generating a clamping threshold based on at least a reference voltage generated by the reference current on a reference resistor; andin response to a difference between a power supply voltage and an output voltage at an output node of the switching circuit is greater than or equal to the clamping threshold, turning on a power transistor that provides the output voltage.2. The method of claim 1 , further comprising:in response to the output voltage of the switch circuit is lower than ...

SEMICONDUCTOR APPARATUS AND A SEMICONDUCTOR SYSTEM CAPABLE OF ADJUSTING TIMINGS OF DATA AND DATA STROBE SIGNAL

A semiconductor apparatus includes a first receiver, a second receiver, a first delay line, and a second delay line. The first receiver receives an input signal using a first supply voltage. The first delay line delays an output of the first receiver based on a first delay control signal and a first complementary delay control signal to generate a received signal. The second receiver receives a clock signal using a second supply voltage. The second delay line delays an output of the second receiver based on a second delay control signal and a second complementary delay control signal to generate a received clock signal. Delay amounts of the first and second delay lines are complementarily changed based on the first and second supply voltages. 1. A semiconductor apparatus comprising:a first receiver configured to receive an input signal using a first supply voltage;a first delay line configured to delay an output of the first receiver, based on a first delay control signal and a first complementary delay control signal, to generate a received signal;a second receiver configured to receive a clock signal using a second supply voltage;a second delay line configured to delay an output of the second receiver, based on a second delay control signal and a second complementary delay control signal, to generate a received clock signal;a first voltage detection circuit configured to receive the first supply voltage as a positive input signal, to receive the second supply voltage as a negative input signal, and to compare the levels of the first and second supply voltages to generate the first delay control signal and the first complementary delay control signal; anda second voltage detection circuit configured to receive the second supply voltage as a positive input signal, to receive the first supply voltage as a negative input signal, and to compare the levels of the first and second supply voltages to generate the second delay control signal and the second complementary ...

HIGHLY LINEAR TIME AMPLIFIER WITH POWER SUPPLY REJECTION

A highly linear time amplifier with power supply rejection. In a reset stage, the threshold value of an over-threshold detector is used for resetting an output node of an amplifier, to eliminate the impact of power supply voltage changes on the threshold value of the threshold detector. A node capacitor unit is charged under the control of an input clock signal. After completion of charging, the node capacitor unit is discharged under the control of a synchronous clock signal. The time amplification gain only depends on the proportion of the charge and discharge current, and the charging and discharging time are completely linear in principle, which eliminates the nonlinearity of the traditional time amplifier, and reduces the negative impact of threshold change on system performance. 1. A highly linear time amplifier with power supply rejection , comprisinga clock control logic generating unit, receiving the input clock signal and a synchronous clock signal, and generating a control clock signal;a node capacitor unit, charging and discharging according to the control clock signal;a switching power supply unit, comprising a plurality of switching constant current source modules, an input terminal of the switching constant current source module is connected with an output terminal of the clock control logic generating unit;wherein the switching constant current source module charges the node capacitor unit under a control of the input clock signal, after charging is completed, the node capacitor unit discharge under a control of the synchronous clock signal, to achieve time amplification.2. The highly linear time amplifier with power supply rejection according to claim 1 , further comprising:an over-threshold detection unit, performing over-threshold detection;a resetting network, comprising an over-threshold detector common mode generating unit and a common mode output buffer interconnected with the over-threshold detection unit;wherein an input terminal of the over ...

FAULT MONITORING SYSTEMS AND METHODS FOR DETECTING CONNECTIVITY FAULTS

The present invention provides a fault monitoring system for detecting connectivity faults in a device control centre. The fault monitoring system comprising for the or each control section, at least a first pair of temperature sensors, one of the first pair of temperature sensors being adapted to detect the temperature of a of the first pair of terminals (T), and the other of the first pair of temperature sensors being adapted to detect the temperature of the other of the first pair of terminals (T)—The system comprises a processor configured to receive the detected temperatures, calculate an IN-OUT difference the IN-OUT difference, being a difference between the temperatures of the first pair of terminals (ΔT), compare the calculated IN-OUT difference with a predetermined threshold value (ΔT*), whereby a calculated difference IN-OUT (ΔT) greater than the predetermined threshold value (ΔT*) is indicative of a connectivity fault at one of the first pair of terminals, and to generate at least one output signal based on the results of the comparison. 164-. (canceled)65. A fault monitoring system for detecting connectivity faults in a device control center , the device control center including at least one control section configured to control the supply of electrical power from a power source to a respective at least one device , the or each control section being electrically connected between the power source and the respective device at least a first pair of terminals , one of the first pair of terminals connecting the control section to of the power source side of a first power line and the other of the first pair of terminals connecting the control section to the device side of the first power line such that the control section completes the power circuit of the device , the fault monitoring system comprising:{'sub': L1-IN', 'L1-OUT, 'for the or each control section, at least a first pair of temperature sensors, one of the first pair of temperature sensors being ...

INTEGRATED CLOCK GATER (ICG) USING CLOCK CASCODE COMPLIMENTARY SWITCH LOGIC

Inventive aspects include an integrated clock gater (ICG) circuit having clocked complimentary voltage switched logic (CICG) that delivers high performance while maintaining low power consumption characteristics. The CICG circuit provides a small enable setup time and a small clock-to-enabled-clock delay. A significant reduction in clock power consumption is achieved in both enabled and disabled modes, but particularly in the disabled mode. Complimentary latches work in tandem to latch different voltage levels at different nodes depending on the voltage level of the received clock signal and whether or not an enable signal is asserted. An inverter takes the voltage level from one of the nodes, inverts it, and outputs a gated clock signal. The gated clock signal may be active or quiescent depending on the various voltage levels. Time is “borrowed” from an evaluation window and added to a setup time to provide greater tolerances for receiving the enable signal. 113-. (canceled)14. A complimentary voltage switched integrated clock gater (CICG) circuit , comprising:first and second pre-charge transistors configured to receive a clock signal;a first node connected to the first pre-charge transistor, the first pre-charge transistor being configured to pre-charge the first node responsive to the clock signal;a second node connected to the second pre-charge transistor, the second pre-charge transistor being configured to pre-charge the second node responsive to the clock signal;a first latch connected to the first node; anda second latch connected to the second node.15. The CICG circuit of claim 14 , further comprising:an inverter connected to the first node, the inverter being configured to invert a voltage level of the first node and to produce a gated clock signal.16. The CICG circuit of claim 14 , further comprising:an evaluation transistor configured to receive the clock signal;an enable transistor connected to the evaluation transistor and configured to receive an ...

DRIVING DEVICE FOR SEMICONDUCTOR ELEMENTS

To provide a driving device for semiconductor elements that is capable of suppressing variation in switching time caused by driving capability and temperature. A driving device for semiconductor elements includes: a semiconductor chip in which a voltage control type semiconductor element is formed; a temperature detecting unit configured to detect temperature of the semiconductor chip; a driving-capability adjusting unit configured to adjust driving capability of the voltage control type semiconductor element according to temperature detection values detected by the temperature detecting unit; and a timing adjusting unit configured to adjust switching time of the voltage control type semiconductor element according to the temperature detection values detected by the temperature detecting unit. 1. A driving device for semiconductor elements comprising:a semiconductor chip in which a voltage control type semiconductor element is formed;a temperature detecting unit configured to detect temperature of the semiconductor chip;a driving-capability adjusting unit configured to adjust driving capability of the voltage control type semiconductor element according to temperature detection values detected by the temperature detecting unit; anda timing adjusting unit configured to adjust switching time of the voltage control type semiconductor element according to the temperature detection values detected by the temperature detecting unit.2. The driving device for semiconductor elements according to claim 1 , whereinthe timing adjusting unit is connected between the driving-capability adjusting unit and the voltage control type semiconductor element.3. The driving device for semiconductor elements according to claim 1 , whereinthe timing adjusting unit is connected at a previous stage of the driving-capability adjusting unit.4. The driving device for semiconductor elements according to claim 1 , whereinthe timing adjusting unit is configured with a variable delay circuit capable ...

CONTROL OF REVERSE-CONDUCTING IGBT

A method and an arrangement of controlling a reverse-conducting IGBT (RC-IGBT) component in a circuit comprising a series connection of controllable switch components where at least one of the controllable switch components is an RC-IGBT and the other component is to be controlled to a conductive state. The method comprising applying a pre-trigger pulse to the gate electrode of the RC-IGBT during reverse conduction of the RC-IGBT at a first time instant (t), the pre-trigger pulse corresponding to a turn-on gate pulse, applying a turn-on gate pulse at a second time instant (t) to the other controllable switch component of the series connection for controlling the other controllable switch component to a conductive state such that the pre-trigger pulse and the turn-on gate pulse overlap, and ending the pre-trigger pulse after a delay time at the third time instant (t), the delay time being the time period when the turn-on gate pulse and the pre-trigger pulse overlap. 1. A method of controlling a reverse-conducting IGBT (RC-IGBT) component in a circuit comprising a series connection of controllable switch components where at least one of the controllable switch components is an RC-IGBT and the other component is to be controlled to a conductive state , the method comprising{'sub': '1', 'applying a pre-trigger pulse to the gate electrode of the RC-IGBT during reverse conduction of the RC-IGBT at a first time instant (t), the pre-trigger pulse corresponding to a turn-on gate pulse,'}{'sub': '2', 'applying a turn-on gate pulse at a second time instant (t) to the other controllable switch component of the series connection for controlling the other controllable switch component to a conductive state such that the pre-trigger pulse and the turn-on gate pulse overlap, and'}{'sub': '3', 'ending the pre-trigger pulse after a delay time at the third time instant (t), the delay time being the time period when the turn-on gate pulse and the pre-trigger pulse overlap.'}2. A method ...