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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 18. Отображено 14.
14-01-2021 дата публикации

Method for calibrating capacitor voltage coefficient of high-precision successive approximation analog-to-digital converter

Номер: US20210013896A1
Автор: Dongbing Fu, TING Li, Yabo NI, Yong Zhang, Zhengbo Huang
Принадлежит: CETC 24 Research Institute

The present disclosure relates to the field of semiconductor integrated circuits, and to a method for calibrating a capacitor voltage coefficient of a high-precision successive approximation analog-to-digital converter (SAR ADC). The method includes: calibrating a voltage coefficient; obtaining a sampled charged charge according to a capacitance model with the voltage coefficient; according to an INL value obtained by testing, first verifying whether a maximum value of INL occurs in the place shown in Equation 3, then obtaining two very close second-order capacitor voltage coefficients according to Equation 4, and taking an average value thereof as a second-order capacitor voltage coefficient; and then calibrating the second-order capacitor voltage coefficient in a digital domain. In the present disclosure, a capacitor voltage coefficient can be extracted based on INL and the capacitor voltage coefficient is calibrated at a digital backend without adding an analog calibration circuit, thereby improving conversion accuracy of the ADC.

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Номер записи: 1
24-03-2022 дата публикации

Error extraction method for foreground digital correction of pipeline analog-to-digital converter

Номер: US20220094366A1
Автор: Dongbing Fu, TING Li, Yabo NI, Yong Zhang, Zhengbo Huang
Принадлежит: CETC 24 Research Institute, Chongqing Gigachip Technology Co Ltd

An error extraction method for foreground digital correction of a pipeline analog-to-digital converter including: acquiring a transmission curve of a pipeline analog-to-digital converter, and controlling an input signal to be within a sub-segment 0 of the transmission curve; during extraction of error information of an ith pipeline stage, setting a magnitude of the input signal according to Formula (I); locking the outputs of all previous-stage comparators in the i th pipeline stage of the pipeline analog-to-digital converter; and completing, according to original output code of the pipeline analog-to-digital converter, error extraction by means of adaptive iteration, stage-by-stage, sequentially from a last stage to a first stage of a pipeline. During quantization of error value, the invention performs, by means of a fitting-based adaptive algorithm, foreground extraction of a capacitance mismatch error, a gain bandwidth error, and a kickback error in each stage of the pipeline, without any additional circuit.

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Номер записи: 2
29-04-2021 дата публикации

Pipelined Analog-To-Digital Converter Having Input Signal Pre-Comparison and Charge Redistribution

Номер: US20210126646A1
Автор: Guangbing Chen, Ruzhang Li, TING Li, Yabo NI, Yong Zhang, Zhengbo Huang
Принадлежит: CETC 24 Research Institute

The present disclosure provides a pipelined analog-to-digital converter having input signal pre-comparison and charge redistribution, including: one-stage or multi-stage of pipelined structure unit, a first flash analog-to-digital converter, and an adjusting output unit. Each stage of the pipelined structure unit is used to quantify the input signal. The first flash analog-to-digital converter quantizes a residual signal output by a final pipelined structure unit, and outputs a corresponding quantized value. The adjusting output unit combines each of the quantized values according to a connection order of the multi-stage pipelined structure unit and a flash analog-to-digital conversion unit to output a complete quantization result. By using the pre-comparison and charge redistribution technologies, the number of comparators of different stages of pipelined sub ADC is reduced and the low power consumption design is achieved, signal sample-and-hold and residual signal amplification establishing are simultaneously carried out, thus improving the conversion rate.

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Номер записи: 3
01-07-2021 дата публикации

HIGHLY LINEAR TIME AMPLIFIER WITH POWER SUPPLY REJECTION

Номер: US20210203277A1
Автор: "WANG Jianan", FU Dongbing, HUANG Zhengbo, LI Ting, NI Yabo, Zhang Yong
Принадлежит: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION

A highly linear time amplifier with power supply rejection. In a reset stage, the threshold value of an over-threshold detector is used for resetting an output node of an amplifier, to eliminate the impact of power supply voltage changes on the threshold value of the threshold detector. A node capacitor unit is charged under the control of an input clock signal. After completion of charging, the node capacitor unit is discharged under the control of a synchronous clock signal. The time amplification gain only depends on the proportion of the charge and discharge current, and the charging and discharging time are completely linear in principle, which eliminates the nonlinearity of the traditional time amplifier, and reduces the negative impact of threshold change on system performance. 1. A highly linear time amplifier with power supply rejection , comprisinga clock control logic generating unit, receiving the input clock signal and a synchronous clock signal, and generating a control clock signal;a node capacitor unit, charging and discharging according to the control clock signal;a switching power supply unit, comprising a plurality of switching constant current source modules, an input terminal of the switching constant current source module is connected with an output terminal of the clock control logic generating unit;wherein the switching constant current source module charges the node capacitor unit under a control of the input clock signal, after charging is completed, the node capacitor unit discharge under a control of the synchronous clock signal, to achieve time amplification.2. The highly linear time amplifier with power supply rejection according to claim 1 , further comprising:an over-threshold detection unit, performing over-threshold detection;a resetting network, comprising an over-threshold detector common mode generating unit and a common mode output buffer interconnected with the over-threshold detection unit;wherein an input terminal of the over ...

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Номер записи: 4
01-07-2021 дата публикации

Voltage-to-time converter and method for reducing parasitic capacitance and power supply influences

Номер: US20210203344A1
Автор: Dongbing Fu, Jian'an Wang, TING Li, Yabo NI, Yong Zhang, Zhengbo Huang
Принадлежит: CETC 24 Research Institute

The present disclosure provides a voltage-to-time converter and method for reducing parasitic capacitance and power supply influences. The voltage-to-time converter includes: a main sampling network, a compensation sampling network, a discharge network and an over-threshold detection unit. The influence of a traditional VTC parasitic capacitance on a VTC output swing amplitude is reduced by using the compensation sampling network. A sampling common-mode level of the compensation sampling network is compensated, such that the influence of the low-frequency disturbance of a power supply voltage on a threshold of a traditional VTC threshold detection circuit is reduced. The output swing amplitude of the voltage-to-time converter of the present disclosure can reduce the influence of a parasitic capacitance. A voltage common-mode level of a VTC input end is related to a power supply voltage, which reduces a conversion error caused by the influence of the power supply voltage on a threshold.

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Номер записи: 5
18-06-2020 дата публикации

METHOD AND SYSTEM FOR RECOGNIZING USER ACTIONS WITH RESPECT TO OBJECTS

Номер: US20200193148A1
Автор: HE Hualin, NI Yabo, Pan Chunxiang, Zeng Anxiang
Принадлежит:

The specification discloses a computer-implemented method for user action determination, comprising: recognizing an item displacement action performed by a user; determining a first time and a first location of the item displacement action; recognizing a target item in a non-stationary state; determining a second time when the target item is in the non-stationary state and a second location where the target item is in the non-stationary state; and in response to determining that the first time matches the second time and the first location matches the second location, determining that the item displacement action of the user is performed with respect to the target item. 1. A computer-implemented method for user action determination , comprising:recognizing an item displacement action performed by a user;determining a first time and a first location of the item displacement action;recognizing a target item in a non-stationary state;determining a second time when the target item is in the non-stationary state and a second location where the target item is in the non-stationary state; andin response to determining that the first time matches the second time and the first location matches the second location, determining that the item displacement action of the user is performed with respect to the target item.2. The method according to claim 1 , wherein the item displacement action performed by the user comprises flipping one or more items claim 1 , moving one or more items claim 1 , or picking up one or more items.3. The method according to claim 1 , wherein recognizing the item displacement action performed by the user comprises:obtaining a video recording the item displacement action of the user;cropping the video to obtain a video of hands including images of the user's hands;inputting the video of hands into a classification model; andobtaining from the classification model a determination regarding whether the user has performed the item displacement action.4. ...

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Номер записи: 6
09-09-2021 дата публикации

BUFFER CIRCUIT AND BUFFER

Номер: US20210281269A1
Автор: "WANG Jianan", Chen Guangbing, FU Dongbing, Hu Gangyi, HUANG Xingfa, HUANG Zhengbo, Li Ruzhang, LI Ting, NI Yabo, XU Zicheng, Yuan Jun, Zhang Yong
Принадлежит: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION

The present disclosure provides a buffer circuit and a buffer. The buffer circuit includes: an input follower circuit for following the voltage change of the first input signal; an input follower linearity boosting circuit for improving follower linearity of the input follower circuit; a first voltage bootstrap circuit for bootstrapping the voltage of the first input signal; a second voltage bootstrap circuit for bootstrapping the voltage of the second input signal; a third voltage bootstrap circuit for providing corresponding quiescent operation point voltage; a compensation follower circuit for following the compensation voltage; a compensation follower linearity boosting circuit for improving follower linearity of the compensation follower circuit; a first load for collecting the buffered voltage; a bias circuit for providing a bias current for the buffer; a bias linearity boosting circuit for improving linearity of the bias circuit; a second load for generating a nonlinear compensation current. 1. A buffer circuit , wherein the buffer circuit is applied to an input buffer and comprises:an input follower circuit, an input end of the input follower circuit is connected with a first input signal to follow a voltage change of the first input signal;an input follower linearity boosting circuit connected with the input follower circuit and a first voltage bootstrap circuit, to improve follower linearity of the input follower circuit;the first voltage bootstrap circuit connected between the first input signal and the input follower linearity boosting circuit, a difference between an output voltage and an input voltage of the first voltage bootstrap circuit is a fixed level, to provide a corresponding quiescent operation point voltage for the input follower linearity boosting circuit;a second voltage bootstrap circuit, an input end of the second voltage bootstrap circuit is connected with a second input signal, and an output end of the second voltage bootstrap circuit ...

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Номер записи: 7
14-07-2022 дата публикации

Substrate-enhanced comparator and electronic device

Номер: US20220224320A1
Автор: Dongbing Fu, Guangbing Chen, Jian'an Wang, TING Li, Yabo NI, Yong Zhang, Zhengbo Huang, Zicheng XU
Принадлежит: CETC 24 Research Institute, Chongqing Gigachip Technology Co Ltd

The present disclosure provides a substrate-enhanced comparator and electronic device, the comparator including: a cross-coupled latch, for connecting input signals to the gate of a cross-coupled MOS transistor to form a first input of the latch; output buffers, connected to the cross-coupled latch for amplifying output signals of the latch; AC couplers, connected to the output buffers for receiving and amplifying the output signals of the latch, coupling the output signals to substrates of the cross-coupled MOS transistors to form second inputs of the latch. The cross-coupled latch is also for output signal regenerative latching based on input signals sampled at the first inputs and input signals sampled at the second inputs. The present disclosure introduces additional substrate inputs to the cross-coupled structure of the conventional latch as the second inputs of the latch.

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Номер записи: 8
31-05-2022 дата публикации

Error extraction method for foreground digital correction of pipeline analog-to-digital converter

Номер: US11349489B2
Автор: Dongbing Fu, TING Li, Yabo NI, Yong Zhang, Zhengbo Huang
Принадлежит: CETC 24 Research Institute, Chongqing Gigachip Technology Co Ltd

An error extraction method for foreground digital correction of a pipeline analog-to-digital converter including: acquiring a transmission curve of a pipeline analog-to-digital converter, and controlling an input signal to be within a sub-segment 0 of the transmission curve; during extraction of error information of an ith pipeline stage, setting a magnitude of the input signal according to Formula (I); locking the outputs of all previous-stage comparators in the ith pipeline stage of the pipeline analog-to-digital converter; and completing, according to original output code of the pipeline analog-to-digital converter, error extraction by means of adaptive iteration, stage-by-stage, sequentially from a last stage to a first stage of a pipeline. During quantization of error value, the invention performs, by means of a fitting-based adaptive algorithm, foreground extraction of a capacitance mismatch error, a gain bandwidth error, and a kickback error in each stage of the pipeline, without any additional circuit.

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Номер записи: 9
19-03-2024 дата публикации

Interface circuit and electronic apparatus

Номер: US11936378B2
Автор: Dongbing Fu, Gangyi Hu, Guangbing Chen, Jian'an Wang, Ruzhang Li, TING Li, Yabo NI, Yong Zhang
Принадлежит: CETC 24 Research Institute, Chongqing Gigachip Technology Co Ltd

An interface circuit and an electronic apparatus, including: a programmable current array ( 1 ), generating a first current and a second current transmitted to a common mode and differential mode generation circuit ( 2 ) according to an input code, and a third current and a fourth current transmitted to a driving bias generation circuit ( 3 ) according to the input code; the common mode and differential mode generation circuit ( 2 ), generating a common mode voltage according to the first current, and generating a high level voltage and a low level voltage according to the second current and the common mode voltage; a driving bias generation circuit ( 3 ), simulating a load according to the third and fourth currents, and generating a bias voltage based on the load and the low and high level voltages; an output driving circuit ( 4 ), converting an input signal into a differential signal in which the common mode voltage and a differential mode amplitude are configurable.

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Номер записи: 10
04-07-2024 дата публикации

Method for calibrating analog-to-digital converter

Номер: US20240223202A1
Автор: CHAO Chen, Dongbing Fu, Guangbing Chen, Huaiqiang YU, Jianan Wang, Liang Li, Ruzhang Li, TING Li, Yabo NI, Yong Zhang
Принадлежит: China Electronics Technology Group Corp No 24 Research Institute

A method for calibrating an analog-to-digital converter includes the following steps: conducting an initial performance test and judgement on the analog-to-digital converter; if the initial performance test succeeds, performing a pre-trimming and judgement on the analog-to-digital converter; if the pre-trimming succeeds, performing an error extraction on the analog-to-digital converter, obtaining errors of conversion stages of the analog-to-digital converter; performing an error soft trimming and test on the analog-to-digital converter according to the errors of the conversion stages; and if the error soft trimming and test of the analog-to-digital converter succeed, performing an error hard trimming and test on the analog-to-digital converter according to the errors of the conversion stages.

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Номер записи: 11
11-04-2024 дата публикации

Circuits, chips, systems and methods for eliminating random perturbation

Номер: US20240120932A1
Автор: Can Zhu, Dongbing Fu, Jiahao PENG, Jianan Wang, Liang Li, LU LIU, TING Li, Xiaofeng Shen, Yabo NI, Yong Zhang
Принадлежит: Chongqing Gigachip Technology Co Ltd

Embodiments of the disclosure provide a circuit, chip, system, and method for eliminating random perturbation. The circuit includes a weight calculating module for receiving digital signals and random perturbation digital quantity, using least mean square error algorithm to calculate weight deviation iteration coefficient based on digital signal and digital quantity, and updating perturbation weight in real-time according to weight deviation iteration coefficient; and a perturbation eliminating module for eliminating perturbation signal in output digital signal of quantizer according to perturbation weight updated in real-time and updating perturbation weight in real-time according to weight deviation iteration coefficient, and then calculating current perturbation weight in real time to realize self-calibration of perturbation weight. Even if the manufacturing process or working environment of the current chip changes, perturbation weight can be dynamically adjusted, to ideally eliminate perturbation signal in digital signal.

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Номер записи: 12
07-09-2021 дата публикации

Voltage-to-time converter and method for reducing parasitic capacitance and power supply influences

Номер: US11115039B2
Автор: Dongbing Fu, Jian'an Wang, TING Li, Yabo NI, Yong Zhang, Zhengbo Huang
Принадлежит: CETC 24 Research Institute

The present disclosure provides a voltage-to-time converter and method for reducing parasitic capacitance and power supply influences. The voltage-to-time converter includes: a main sampling network, a compensation sampling network, a discharge network and an over-threshold detection unit. The influence of a traditional VTC parasitic capacitance on a VTC output swing amplitude is reduced by using the compensation sampling network. A sampling common-mode level of the compensation sampling network is compensated, such that the influence of the low-frequency disturbance of a power supply voltage on a threshold of a traditional VTC threshold detection circuit is reduced. The output swing amplitude of the voltage-to-time converter of the present disclosure can reduce the influence of a parasitic capacitance. A voltage common-mode level of a VTC input end is related to a power supply voltage, which reduces a conversion error caused by the influence of the power supply voltage on a threshold.

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Номер записи: 13
29-08-2024 дата публикации

Method for correcting analog-to-digital converter

Номер: US20240291496A1
Автор: CHAO Chen, Dongbing Fu, Guangbing Chen, Huaiqiang YU, Jianan Wang, Liang Li, Ruzhang Li, TING Li, Yabo NI, Yong Zhang
Принадлежит: China Electronics Technology Group Corp No 24 Research Institute

A method for correcting an analog-to-digital converter includes the following steps: extracting gain errors and weight errors of all conversion stages of an analog-to-digital converter; performing first correction on the analog-to-digital converter based on the gain errors and the weight errors; extracting jitter errors of all conversion stages of the analog-to-digital converter after the first correction; and performing a second correction on the analog-to-digital converter based on the jitter errors. According to the disclosure, the gain errors, the weight errors, and the jitter errors of all conversion stages are successively extracted, and then the analog-to-digital converter is corrected. Precision after the corrections is higher. An actual weight of each quantization unit at each conversion stage, an actual inter-stage gain of each conversion stage and an actual weight of jitter are extracted, impact of a jitter weight is eliminated during outputting, and a signal-to-noise ratio of analog-to-digital conversion is increased.

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Номер записи: 14